Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.20 96.89 91.99 97.67 100.00 98.28 97.45 98.14


Total test records in report: 472
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T304 /workspace/coverage/default/23.rom_ctrl_smoke.3791444165 Jul 27 05:36:03 PM PDT 24 Jul 27 05:36:13 PM PDT 24 364312525 ps
T305 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1802355442 Jul 27 05:36:30 PM PDT 24 Jul 27 05:38:27 PM PDT 24 3895400710 ps
T306 /workspace/coverage/default/14.rom_ctrl_stress_all.2186335276 Jul 27 05:35:54 PM PDT 24 Jul 27 05:36:07 PM PDT 24 1370491459 ps
T307 /workspace/coverage/default/7.rom_ctrl_smoke.3123009089 Jul 27 05:35:41 PM PDT 24 Jul 27 05:35:52 PM PDT 24 3504961482 ps
T308 /workspace/coverage/default/6.rom_ctrl_smoke.2235499123 Jul 27 05:35:40 PM PDT 24 Jul 27 05:35:51 PM PDT 24 1070244878 ps
T309 /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1582522439 Jul 27 05:36:42 PM PDT 24 Jul 27 06:44:04 PM PDT 24 93996537624 ps
T310 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3790760662 Jul 27 05:36:23 PM PDT 24 Jul 27 05:36:29 PM PDT 24 558973802 ps
T311 /workspace/coverage/default/35.rom_ctrl_smoke.4133222962 Jul 27 05:36:21 PM PDT 24 Jul 27 05:36:33 PM PDT 24 1042442927 ps
T312 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1901197569 Jul 27 05:36:14 PM PDT 24 Jul 27 05:36:25 PM PDT 24 260062664 ps
T313 /workspace/coverage/default/13.rom_ctrl_alert_test.3449449112 Jul 27 05:35:52 PM PDT 24 Jul 27 05:35:57 PM PDT 24 126949784 ps
T314 /workspace/coverage/default/10.rom_ctrl_alert_test.1984073648 Jul 27 05:35:58 PM PDT 24 Jul 27 05:36:02 PM PDT 24 89813491 ps
T315 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2313802150 Jul 27 05:36:18 PM PDT 24 Jul 27 05:36:25 PM PDT 24 551825237 ps
T316 /workspace/coverage/default/21.rom_ctrl_smoke.3839510810 Jul 27 05:35:55 PM PDT 24 Jul 27 05:36:06 PM PDT 24 326775183 ps
T317 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.514784363 Jul 27 05:36:08 PM PDT 24 Jul 27 05:36:20 PM PDT 24 251508887 ps
T318 /workspace/coverage/default/1.rom_ctrl_stress_all.762422943 Jul 27 05:35:27 PM PDT 24 Jul 27 05:35:34 PM PDT 24 164894974 ps
T319 /workspace/coverage/default/41.rom_ctrl_alert_test.4249939452 Jul 27 05:36:30 PM PDT 24 Jul 27 05:36:34 PM PDT 24 87100024 ps
T320 /workspace/coverage/default/5.rom_ctrl_alert_test.4240434211 Jul 27 05:35:41 PM PDT 24 Jul 27 05:35:45 PM PDT 24 172986196 ps
T321 /workspace/coverage/default/41.rom_ctrl_stress_all.811247963 Jul 27 05:36:24 PM PDT 24 Jul 27 05:36:34 PM PDT 24 378435116 ps
T322 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1623046988 Jul 27 05:35:42 PM PDT 24 Jul 27 05:35:54 PM PDT 24 251725776 ps
T323 /workspace/coverage/default/35.rom_ctrl_alert_test.2782396765 Jul 27 05:36:20 PM PDT 24 Jul 27 05:36:25 PM PDT 24 249815748 ps
T324 /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1539458550 Jul 27 05:36:15 PM PDT 24 Jul 27 05:56:28 PM PDT 24 69773804814 ps
T325 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1919927302 Jul 27 05:36:41 PM PDT 24 Jul 27 05:36:53 PM PDT 24 532233223 ps
T326 /workspace/coverage/default/42.rom_ctrl_smoke.2234407318 Jul 27 05:36:32 PM PDT 24 Jul 27 05:36:44 PM PDT 24 564142159 ps
T327 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2077702009 Jul 27 05:35:56 PM PDT 24 Jul 27 05:36:43 PM PDT 24 669580424 ps
T328 /workspace/coverage/default/3.rom_ctrl_alert_test.4091988420 Jul 27 05:35:41 PM PDT 24 Jul 27 05:35:46 PM PDT 24 85497491 ps
T329 /workspace/coverage/default/35.rom_ctrl_stress_all.173861444 Jul 27 05:36:16 PM PDT 24 Jul 27 05:36:42 PM PDT 24 589931747 ps
T330 /workspace/coverage/default/26.rom_ctrl_alert_test.191995367 Jul 27 05:36:06 PM PDT 24 Jul 27 05:36:13 PM PDT 24 1883156173 ps
T331 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4122477887 Jul 27 05:35:41 PM PDT 24 Jul 27 05:35:48 PM PDT 24 499633640 ps
T332 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3268857115 Jul 27 05:35:57 PM PDT 24 Jul 27 05:36:04 PM PDT 24 138151987 ps
T333 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1703945217 Jul 27 05:35:42 PM PDT 24 Jul 27 05:35:59 PM PDT 24 982897096 ps
T334 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1407517813 Jul 27 05:36:07 PM PDT 24 Jul 27 05:36:18 PM PDT 24 491145902 ps
T335 /workspace/coverage/default/45.rom_ctrl_smoke.2640164638 Jul 27 05:36:33 PM PDT 24 Jul 27 05:36:43 PM PDT 24 186746323 ps
T336 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.4238705657 Jul 27 05:36:23 PM PDT 24 Jul 27 06:24:00 PM PDT 24 278084425930 ps
T337 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3797575327 Jul 27 05:36:43 PM PDT 24 Jul 27 05:36:48 PM PDT 24 97675291 ps
T338 /workspace/coverage/default/16.rom_ctrl_stress_all.501407724 Jul 27 05:35:56 PM PDT 24 Jul 27 05:36:04 PM PDT 24 222832863 ps
T339 /workspace/coverage/default/18.rom_ctrl_alert_test.1036470948 Jul 27 05:35:57 PM PDT 24 Jul 27 05:36:02 PM PDT 24 465140009 ps
T340 /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3917829522 Jul 27 05:36:08 PM PDT 24 Jul 27 06:13:47 PM PDT 24 240652367114 ps
T341 /workspace/coverage/default/14.rom_ctrl_alert_test.3484209096 Jul 27 05:35:53 PM PDT 24 Jul 27 05:35:58 PM PDT 24 176639999 ps
T342 /workspace/coverage/default/33.rom_ctrl_smoke.2550458045 Jul 27 05:36:22 PM PDT 24 Jul 27 05:36:34 PM PDT 24 1104025443 ps
T343 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3668090425 Jul 27 05:35:56 PM PDT 24 Jul 27 05:36:02 PM PDT 24 197452138 ps
T344 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3368564602 Jul 27 05:36:14 PM PDT 24 Jul 27 05:37:14 PM PDT 24 1154040595 ps
T345 /workspace/coverage/default/27.rom_ctrl_stress_all.511805510 Jul 27 05:36:01 PM PDT 24 Jul 27 05:36:47 PM PDT 24 4991550182 ps
T346 /workspace/coverage/default/38.rom_ctrl_alert_test.380261631 Jul 27 05:36:21 PM PDT 24 Jul 27 05:36:26 PM PDT 24 346815033 ps
T347 /workspace/coverage/default/12.rom_ctrl_alert_test.167703370 Jul 27 05:35:54 PM PDT 24 Jul 27 05:35:59 PM PDT 24 495519264 ps
T348 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3668397374 Jul 27 05:36:09 PM PDT 24 Jul 27 05:36:18 PM PDT 24 642483197 ps
T349 /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1968675087 Jul 27 05:35:58 PM PDT 24 Jul 27 06:37:45 PM PDT 24 133690009421 ps
T350 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.927734974 Jul 27 05:36:31 PM PDT 24 Jul 27 05:36:41 PM PDT 24 281144679 ps
T351 /workspace/coverage/default/37.rom_ctrl_smoke.578414300 Jul 27 05:36:17 PM PDT 24 Jul 27 05:36:29 PM PDT 24 535763098 ps
T352 /workspace/coverage/default/23.rom_ctrl_alert_test.2924495687 Jul 27 05:36:09 PM PDT 24 Jul 27 05:36:15 PM PDT 24 460411752 ps
T353 /workspace/coverage/default/1.rom_ctrl_smoke.1295837473 Jul 27 05:35:29 PM PDT 24 Jul 27 05:35:39 PM PDT 24 696205101 ps
T354 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3615280153 Jul 27 05:36:03 PM PDT 24 Jul 27 05:36:14 PM PDT 24 258420395 ps
T355 /workspace/coverage/default/24.rom_ctrl_stress_all.660214685 Jul 27 05:36:08 PM PDT 24 Jul 27 05:36:40 PM PDT 24 1352672817 ps
T356 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1392714187 Jul 27 05:36:21 PM PDT 24 Jul 27 05:36:29 PM PDT 24 514482640 ps
T357 /workspace/coverage/default/46.rom_ctrl_alert_test.832690810 Jul 27 05:36:43 PM PDT 24 Jul 27 05:36:48 PM PDT 24 89074694 ps
T358 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3055825565 Jul 27 05:36:05 PM PDT 24 Jul 27 05:36:10 PM PDT 24 99985820 ps
T359 /workspace/coverage/default/19.rom_ctrl_alert_test.329622076 Jul 27 05:35:55 PM PDT 24 Jul 27 05:36:00 PM PDT 24 253997716 ps
T360 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.95882617 Jul 27 05:36:13 PM PDT 24 Jul 27 07:43:06 PM PDT 24 26664053154 ps
T361 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1568342349 Jul 27 05:35:56 PM PDT 24 Jul 27 05:37:26 PM PDT 24 1928520351 ps
T362 /workspace/coverage/default/27.rom_ctrl_smoke.3906019832 Jul 27 05:36:07 PM PDT 24 Jul 27 05:36:19 PM PDT 24 1058413952 ps
T363 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.624122357 Jul 27 05:35:54 PM PDT 24 Jul 27 05:38:07 PM PDT 24 2770795575 ps
T364 /workspace/coverage/default/33.rom_ctrl_alert_test.73241064 Jul 27 05:36:12 PM PDT 24 Jul 27 05:36:17 PM PDT 24 404875109 ps
T365 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1739299575 Jul 27 05:35:31 PM PDT 24 Jul 27 05:35:43 PM PDT 24 258824382 ps
T366 /workspace/coverage/default/39.rom_ctrl_stress_all.4141342374 Jul 27 05:36:22 PM PDT 24 Jul 27 05:36:33 PM PDT 24 269888182 ps
T367 /workspace/coverage/default/26.rom_ctrl_smoke.3139828180 Jul 27 05:36:11 PM PDT 24 Jul 27 05:36:23 PM PDT 24 526216771 ps
T368 /workspace/coverage/default/2.rom_ctrl_alert_test.92062297 Jul 27 05:35:28 PM PDT 24 Jul 27 05:35:32 PM PDT 24 171569908 ps
T369 /workspace/coverage/default/18.rom_ctrl_smoke.1673322845 Jul 27 05:35:59 PM PDT 24 Jul 27 05:36:10 PM PDT 24 193959186 ps
T370 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2144094953 Jul 27 05:36:41 PM PDT 24 Jul 27 05:38:07 PM PDT 24 1331023154 ps
T371 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2003627032 Jul 27 05:36:20 PM PDT 24 Jul 27 05:37:51 PM PDT 24 1383256929 ps
T372 /workspace/coverage/default/36.rom_ctrl_smoke.131480118 Jul 27 05:36:21 PM PDT 24 Jul 27 05:36:31 PM PDT 24 1099412330 ps
T373 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1251356574 Jul 27 05:35:40 PM PDT 24 Jul 27 05:35:51 PM PDT 24 259944553 ps
T374 /workspace/coverage/default/49.rom_ctrl_alert_test.967146227 Jul 27 05:36:44 PM PDT 24 Jul 27 05:36:49 PM PDT 24 517077561 ps
T375 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1260506569 Jul 27 05:36:18 PM PDT 24 Jul 27 05:36:27 PM PDT 24 340426984 ps
T376 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1845654819 Jul 27 05:36:08 PM PDT 24 Jul 27 05:36:14 PM PDT 24 162251945 ps
T377 /workspace/coverage/default/20.rom_ctrl_stress_all.2012841958 Jul 27 05:35:56 PM PDT 24 Jul 27 05:36:46 PM PDT 24 3668255536 ps
T378 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3661505290 Jul 27 05:35:55 PM PDT 24 Jul 27 05:36:04 PM PDT 24 975005877 ps
T379 /workspace/coverage/default/26.rom_ctrl_stress_all.4088750619 Jul 27 05:36:08 PM PDT 24 Jul 27 05:36:34 PM PDT 24 504170992 ps
T380 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1675264815 Jul 27 05:35:53 PM PDT 24 Jul 27 05:37:48 PM PDT 24 2600213952 ps
T60 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3182574400 Jul 27 05:55:01 PM PDT 24 Jul 27 05:55:08 PM PDT 24 297623255 ps
T61 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2843349892 Jul 27 05:55:11 PM PDT 24 Jul 27 05:55:16 PM PDT 24 895641450 ps
T381 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3410936734 Jul 27 05:54:54 PM PDT 24 Jul 27 05:54:59 PM PDT 24 132208608 ps
T62 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3689086741 Jul 27 05:54:52 PM PDT 24 Jul 27 05:55:00 PM PDT 24 533504218 ps
T57 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3908585059 Jul 27 05:55:17 PM PDT 24 Jul 27 05:56:26 PM PDT 24 254441112 ps
T106 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3806509960 Jul 27 05:55:12 PM PDT 24 Jul 27 05:55:17 PM PDT 24 89272985 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.796539945 Jul 27 05:54:58 PM PDT 24 Jul 27 05:55:07 PM PDT 24 130489843 ps
T58 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.506441378 Jul 27 05:55:11 PM PDT 24 Jul 27 05:56:21 PM PDT 24 567614261 ps
T383 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2248738869 Jul 27 05:55:02 PM PDT 24 Jul 27 05:55:09 PM PDT 24 131777763 ps
T112 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4080241141 Jul 27 05:54:54 PM PDT 24 Jul 27 05:55:00 PM PDT 24 498856425 ps
T113 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2935132493 Jul 27 05:55:10 PM PDT 24 Jul 27 05:55:43 PM PDT 24 4329507225 ps
T384 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.882119663 Jul 27 05:54:54 PM PDT 24 Jul 27 05:54:59 PM PDT 24 371119145 ps
T107 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.353848257 Jul 27 05:55:11 PM PDT 24 Jul 27 05:55:17 PM PDT 24 129187341 ps
T114 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.663451959 Jul 27 05:54:50 PM PDT 24 Jul 27 05:55:19 PM PDT 24 1132161110 ps
T385 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.302390933 Jul 27 05:55:10 PM PDT 24 Jul 27 05:55:16 PM PDT 24 770705836 ps
T115 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2378534522 Jul 27 05:55:10 PM PDT 24 Jul 27 05:55:15 PM PDT 24 96569269 ps
T65 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1038748908 Jul 27 05:55:11 PM PDT 24 Jul 27 05:55:17 PM PDT 24 130091634 ps
T108 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.381931020 Jul 27 05:54:56 PM PDT 24 Jul 27 05:55:02 PM PDT 24 2471939892 ps
T386 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4134259338 Jul 27 05:55:12 PM PDT 24 Jul 27 05:55:16 PM PDT 24 333225794 ps
T387 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3257306618 Jul 27 05:55:09 PM PDT 24 Jul 27 05:55:14 PM PDT 24 371655234 ps
T388 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1235534654 Jul 27 05:55:12 PM PDT 24 Jul 27 05:55:16 PM PDT 24 90200528 ps
T59 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3422016242 Jul 27 05:55:10 PM PDT 24 Jul 27 05:55:49 PM PDT 24 860108236 ps
T66 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.4024757935 Jul 27 05:55:11 PM PDT 24 Jul 27 05:55:42 PM PDT 24 783764106 ps
T67 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2958203582 Jul 27 05:54:50 PM PDT 24 Jul 27 05:55:35 PM PDT 24 3152498176 ps
T389 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.116358055 Jul 27 05:55:13 PM PDT 24 Jul 27 05:55:20 PM PDT 24 156065465 ps
T68 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3630301440 Jul 27 05:55:20 PM PDT 24 Jul 27 05:55:24 PM PDT 24 87550115 ps
T390 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3061373631 Jul 27 05:55:10 PM PDT 24 Jul 27 05:55:18 PM PDT 24 442448819 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.61373907 Jul 27 05:55:02 PM PDT 24 Jul 27 05:55:06 PM PDT 24 172586755 ps
T392 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3598025173 Jul 27 05:54:51 PM PDT 24 Jul 27 05:54:55 PM PDT 24 89238654 ps
T69 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2334739587 Jul 27 05:54:58 PM PDT 24 Jul 27 05:55:31 PM PDT 24 825335831 ps
T125 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.701879016 Jul 27 05:55:11 PM PDT 24 Jul 27 05:55:48 PM PDT 24 525406543 ps
T393 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4277203075 Jul 27 05:55:13 PM PDT 24 Jul 27 05:55:18 PM PDT 24 120913778 ps
T129 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.785000831 Jul 27 05:54:54 PM PDT 24 Jul 27 05:55:31 PM PDT 24 2505521644 ps
T394 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3541292970 Jul 27 05:55:02 PM PDT 24 Jul 27 05:55:07 PM PDT 24 132455189 ps
T395 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3242383596 Jul 27 05:54:49 PM PDT 24 Jul 27 05:54:54 PM PDT 24 350152863 ps
T109 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1985922143 Jul 27 05:55:09 PM PDT 24 Jul 27 05:55:14 PM PDT 24 308206979 ps
T133 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4035307382 Jul 27 05:55:13 PM PDT 24 Jul 27 05:55:50 PM PDT 24 390910408 ps
T396 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.403652385 Jul 27 05:55:22 PM PDT 24 Jul 27 05:55:28 PM PDT 24 263261816 ps
T110 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1351870454 Jul 27 05:55:02 PM PDT 24 Jul 27 05:55:07 PM PDT 24 1381250304 ps
T123 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1879757232 Jul 27 05:55:13 PM PDT 24 Jul 27 05:56:21 PM PDT 24 996599184 ps
T397 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2670692727 Jul 27 05:55:10 PM PDT 24 Jul 27 05:55:18 PM PDT 24 450018377 ps
T398 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3275026021 Jul 27 05:55:13 PM PDT 24 Jul 27 05:55:21 PM PDT 24 347801920 ps
T399 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1060585873 Jul 27 05:55:11 PM PDT 24 Jul 27 05:55:16 PM PDT 24 162251624 ps
T400 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1818481123 Jul 27 05:55:00 PM PDT 24 Jul 27 05:55:08 PM PDT 24 1028849306 ps
T401 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1112500956 Jul 27 05:55:12 PM PDT 24 Jul 27 05:55:18 PM PDT 24 153507819 ps
T70 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3834862015 Jul 27 05:54:48 PM PDT 24 Jul 27 05:54:52 PM PDT 24 348374395 ps
T71 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1631068265 Jul 27 05:55:12 PM PDT 24 Jul 27 05:55:17 PM PDT 24 261833476 ps
T72 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.684377790 Jul 27 05:55:00 PM PDT 24 Jul 27 05:55:27 PM PDT 24 558302893 ps
T121 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3267224036 Jul 27 05:55:14 PM PDT 24 Jul 27 05:55:37 PM PDT 24 2086914483 ps
T73 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3011302960 Jul 27 05:54:47 PM PDT 24 Jul 27 05:54:52 PM PDT 24 494340884 ps
T74 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1696334655 Jul 27 05:54:55 PM PDT 24 Jul 27 05:55:02 PM PDT 24 94295319 ps
T402 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3657841716 Jul 27 05:55:03 PM PDT 24 Jul 27 05:55:08 PM PDT 24 759974564 ps
T111 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.101851470 Jul 27 05:55:02 PM PDT 24 Jul 27 05:55:10 PM PDT 24 1010335633 ps
T84 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4049322295 Jul 27 05:55:17 PM PDT 24 Jul 27 05:55:35 PM PDT 24 757377670 ps
T130 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.314046399 Jul 27 05:54:59 PM PDT 24 Jul 27 05:55:44 PM PDT 24 1546029810 ps
T85 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3842947114 Jul 27 05:55:17 PM PDT 24 Jul 27 05:55:35 PM PDT 24 368953626 ps
T403 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1841419106 Jul 27 05:55:12 PM PDT 24 Jul 27 05:55:17 PM PDT 24 518950011 ps
T404 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2476678562 Jul 27 05:55:13 PM PDT 24 Jul 27 05:55:18 PM PDT 24 332517078 ps
T405 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.290125096 Jul 27 05:55:11 PM PDT 24 Jul 27 05:55:18 PM PDT 24 544951204 ps
T86 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2955931954 Jul 27 05:55:14 PM PDT 24 Jul 27 05:55:36 PM PDT 24 615665413 ps
T406 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1229141536 Jul 27 05:54:51 PM PDT 24 Jul 27 05:54:57 PM PDT 24 520908560 ps
T407 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1756571495 Jul 27 05:55:23 PM PDT 24 Jul 27 05:55:32 PM PDT 24 178576199 ps
T408 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.568220366 Jul 27 05:55:17 PM PDT 24 Jul 27 05:55:24 PM PDT 24 1390806542 ps
T409 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3508475451 Jul 27 05:55:14 PM PDT 24 Jul 27 05:56:04 PM PDT 24 50047188672 ps
T410 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3667172848 Jul 27 05:54:55 PM PDT 24 Jul 27 05:55:00 PM PDT 24 1382575442 ps
T411 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1447382438 Jul 27 05:55:00 PM PDT 24 Jul 27 05:55:06 PM PDT 24 522344914 ps
T412 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2126777766 Jul 27 05:55:19 PM PDT 24 Jul 27 05:55:24 PM PDT 24 322246640 ps
T413 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1948636207 Jul 27 05:55:12 PM PDT 24 Jul 27 05:55:39 PM PDT 24 1284749092 ps
T87 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2058018208 Jul 27 05:55:24 PM PDT 24 Jul 27 05:55:28 PM PDT 24 226501053 ps
T126 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.693247330 Jul 27 05:55:02 PM PDT 24 Jul 27 05:56:10 PM PDT 24 1483713408 ps
T94 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.774470726 Jul 27 05:55:12 PM PDT 24 Jul 27 05:55:16 PM PDT 24 171526171 ps
T89 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.573164794 Jul 27 05:55:01 PM PDT 24 Jul 27 05:55:05 PM PDT 24 89707007 ps
T88 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3639459719 Jul 27 05:55:02 PM PDT 24 Jul 27 05:55:07 PM PDT 24 539281879 ps
T414 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2416981209 Jul 27 05:55:25 PM PDT 24 Jul 27 05:55:32 PM PDT 24 561856326 ps
T415 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3086413982 Jul 27 05:55:19 PM PDT 24 Jul 27 05:55:25 PM PDT 24 2488609767 ps
T416 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3164829789 Jul 27 05:55:21 PM PDT 24 Jul 27 05:55:30 PM PDT 24 507711557 ps
T417 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1806752683 Jul 27 05:55:12 PM PDT 24 Jul 27 05:55:16 PM PDT 24 86700310 ps
T418 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1364090279 Jul 27 05:54:47 PM PDT 24 Jul 27 05:54:53 PM PDT 24 655384431 ps
T419 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1847828528 Jul 27 05:55:13 PM PDT 24 Jul 27 05:55:19 PM PDT 24 499624030 ps
T420 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.801246191 Jul 27 05:55:18 PM PDT 24 Jul 27 05:55:25 PM PDT 24 142933640 ps
T421 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1099867458 Jul 27 05:55:13 PM PDT 24 Jul 27 05:55:41 PM PDT 24 570950844 ps
T422 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.370586361 Jul 27 05:54:49 PM PDT 24 Jul 27 05:54:57 PM PDT 24 130591219 ps
T95 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1259003968 Jul 27 05:55:12 PM PDT 24 Jul 27 05:55:34 PM PDT 24 2083157205 ps
T423 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4240874891 Jul 27 05:55:12 PM PDT 24 Jul 27 05:55:18 PM PDT 24 150212162 ps
T424 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2095282474 Jul 27 05:55:00 PM PDT 24 Jul 27 05:55:05 PM PDT 24 124515074 ps
T425 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3589763268 Jul 27 05:55:17 PM PDT 24 Jul 27 05:55:25 PM PDT 24 993577214 ps
T426 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1326159581 Jul 27 05:55:13 PM PDT 24 Jul 27 05:55:41 PM PDT 24 1128575086 ps
T427 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2824993572 Jul 27 05:55:14 PM PDT 24 Jul 27 05:55:22 PM PDT 24 167040242 ps
T428 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.476376691 Jul 27 05:55:10 PM PDT 24 Jul 27 05:55:19 PM PDT 24 471596763 ps
T90 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3145923072 Jul 27 05:55:02 PM PDT 24 Jul 27 05:55:10 PM PDT 24 131951794 ps
T429 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.795355649 Jul 27 05:54:57 PM PDT 24 Jul 27 05:55:01 PM PDT 24 351594275 ps
T430 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.987292620 Jul 27 05:55:09 PM PDT 24 Jul 27 05:55:16 PM PDT 24 175176963 ps
T431 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2629386774 Jul 27 05:54:47 PM PDT 24 Jul 27 05:54:51 PM PDT 24 320969629 ps
T432 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.308085155 Jul 27 05:55:01 PM PDT 24 Jul 27 05:55:09 PM PDT 24 828397215 ps
T433 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2152520416 Jul 27 05:55:14 PM PDT 24 Jul 27 05:55:19 PM PDT 24 422195474 ps
T434 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3432259393 Jul 27 05:55:12 PM PDT 24 Jul 27 05:55:19 PM PDT 24 89324342 ps
T435 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.605793526 Jul 27 05:54:49 PM PDT 24 Jul 27 05:54:58 PM PDT 24 273706319 ps
T135 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.905855177 Jul 27 05:55:09 PM PDT 24 Jul 27 05:55:45 PM PDT 24 588052402 ps
T436 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1697538918 Jul 27 05:55:03 PM PDT 24 Jul 27 05:55:08 PM PDT 24 127069254 ps
T437 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2996961626 Jul 27 05:54:50 PM PDT 24 Jul 27 05:54:54 PM PDT 24 85728787 ps
T438 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2359767898 Jul 27 05:55:11 PM PDT 24 Jul 27 05:55:19 PM PDT 24 126851543 ps
T439 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.603561465 Jul 27 05:54:56 PM PDT 24 Jul 27 05:55:00 PM PDT 24 288613976 ps
T440 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3073718003 Jul 27 05:55:09 PM PDT 24 Jul 27 05:55:14 PM PDT 24 182676760 ps
T441 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3709831530 Jul 27 05:54:53 PM PDT 24 Jul 27 05:55:31 PM PDT 24 361248300 ps
T124 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3253512616 Jul 27 05:55:28 PM PDT 24 Jul 27 05:56:06 PM PDT 24 1688610835 ps
T91 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1294053242 Jul 27 05:55:19 PM PDT 24 Jul 27 05:55:38 PM PDT 24 386080216 ps
T134 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1424474792 Jul 27 05:55:11 PM PDT 24 Jul 27 05:55:51 PM PDT 24 253604798 ps
T442 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3957246581 Jul 27 05:55:13 PM PDT 24 Jul 27 05:55:18 PM PDT 24 552477920 ps
T443 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1704734958 Jul 27 05:55:19 PM PDT 24 Jul 27 05:55:25 PM PDT 24 350120366 ps
T444 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.797394600 Jul 27 05:55:13 PM PDT 24 Jul 27 05:55:21 PM PDT 24 127749285 ps
T445 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1219605241 Jul 27 05:55:23 PM PDT 24 Jul 27 05:55:28 PM PDT 24 257634587 ps
T446 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1079901068 Jul 27 05:55:17 PM PDT 24 Jul 27 05:55:22 PM PDT 24 1380748543 ps
T447 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3724577252 Jul 27 05:54:52 PM PDT 24 Jul 27 05:54:59 PM PDT 24 95929588 ps
T136 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3150183582 Jul 27 05:55:13 PM PDT 24 Jul 27 05:56:22 PM PDT 24 528309542 ps
T448 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2960558160 Jul 27 05:55:02 PM PDT 24 Jul 27 05:55:35 PM PDT 24 829950586 ps
T449 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2550867772 Jul 27 05:55:10 PM PDT 24 Jul 27 05:55:16 PM PDT 24 632638788 ps
T450 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3926234768 Jul 27 05:54:55 PM PDT 24 Jul 27 05:55:02 PM PDT 24 254042000 ps
T127 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1384004173 Jul 27 05:54:55 PM PDT 24 Jul 27 05:56:05 PM PDT 24 1799629458 ps
T451 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2195394020 Jul 27 05:54:54 PM PDT 24 Jul 27 05:55:04 PM PDT 24 1898069111 ps
T452 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.829867181 Jul 27 05:55:10 PM PDT 24 Jul 27 05:55:15 PM PDT 24 1234803988 ps
T453 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1661037062 Jul 27 05:55:13 PM PDT 24 Jul 27 05:55:20 PM PDT 24 594970079 ps
T454 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1167225494 Jul 27 05:55:13 PM PDT 24 Jul 27 05:55:21 PM PDT 24 286469013 ps
T92 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3787376541 Jul 27 05:55:11 PM PDT 24 Jul 27 05:55:39 PM PDT 24 565270126 ps
T455 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1615749116 Jul 27 05:54:53 PM PDT 24 Jul 27 05:54:58 PM PDT 24 132936177 ps
T456 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.195774956 Jul 27 05:54:52 PM PDT 24 Jul 27 05:54:58 PM PDT 24 139574334 ps
T132 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1643131260 Jul 27 05:55:10 PM PDT 24 Jul 27 05:56:18 PM PDT 24 436613952 ps
T457 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2053824490 Jul 27 05:55:24 PM PDT 24 Jul 27 05:56:02 PM PDT 24 205975510 ps
T458 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3233367834 Jul 27 05:54:54 PM PDT 24 Jul 27 05:54:58 PM PDT 24 554199352 ps
T459 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1745584375 Jul 27 05:54:48 PM PDT 24 Jul 27 05:55:58 PM PDT 24 425888915 ps
T460 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.518133959 Jul 27 05:54:53 PM PDT 24 Jul 27 05:55:02 PM PDT 24 7123904924 ps
T461 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1193799165 Jul 27 05:54:55 PM PDT 24 Jul 27 05:55:03 PM PDT 24 96955686 ps
T462 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3969488853 Jul 27 05:54:53 PM PDT 24 Jul 27 05:55:25 PM PDT 24 3136892666 ps
T131 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2016901806 Jul 27 05:55:13 PM PDT 24 Jul 27 05:55:52 PM PDT 24 610574093 ps
T463 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2365252545 Jul 27 05:55:13 PM PDT 24 Jul 27 05:55:19 PM PDT 24 252078625 ps
T464 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3745057113 Jul 27 05:54:54 PM PDT 24 Jul 27 05:54:59 PM PDT 24 498651465 ps
T465 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3386322674 Jul 27 05:54:54 PM PDT 24 Jul 27 05:55:03 PM PDT 24 468183882 ps
T466 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1565640484 Jul 27 05:55:13 PM PDT 24 Jul 27 05:55:18 PM PDT 24 2497648515 ps
T128 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2639661331 Jul 27 05:55:10 PM PDT 24 Jul 27 05:56:21 PM PDT 24 593398399 ps
T467 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2355474519 Jul 27 05:55:10 PM PDT 24 Jul 27 05:55:17 PM PDT 24 832494062 ps
T468 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.71146212 Jul 27 05:55:14 PM PDT 24 Jul 27 05:55:36 PM PDT 24 531880004 ps
T93 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.268759444 Jul 27 05:54:56 PM PDT 24 Jul 27 05:55:00 PM PDT 24 90146026 ps
T469 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1947372210 Jul 27 05:55:02 PM PDT 24 Jul 27 05:55:07 PM PDT 24 150405019 ps
T470 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.810458434 Jul 27 05:55:11 PM PDT 24 Jul 27 05:55:16 PM PDT 24 521705130 ps
T471 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.644483579 Jul 27 05:55:15 PM PDT 24 Jul 27 05:55:19 PM PDT 24 347100760 ps
T472 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2619451831 Jul 27 05:55:09 PM PDT 24 Jul 27 05:55:13 PM PDT 24 86606798 ps

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1683239565
Short name T5
Test name
Test status
Simulation time 177550136859 ps
CPU time 669.81 seconds
Started Jul 27 05:35:54 PM PDT 24
Finished Jul 27 05:47:05 PM PDT 24
Peak memory 236336 kb
Host smart-c4f967bf-b52c-4fcb-9031-547fdd284b12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683239565 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1683239565
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2834188264
Short name T8
Test name
Test status
Simulation time 4070021467 ps
CPU time 119.55 seconds
Started Jul 27 05:36:33 PM PDT 24
Finished Jul 27 05:38:33 PM PDT 24
Peak memory 234276 kb
Host smart-79285e6c-057c-485e-b7c0-38acc17faa25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834188264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2834188264
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.4095204217
Short name T1
Test name
Test status
Simulation time 80857394003 ps
CPU time 3866.88 seconds
Started Jul 27 05:36:06 PM PDT 24
Finished Jul 27 06:40:33 PM PDT 24
Peak memory 231472 kb
Host smart-51360934-edf8-4371-87b7-08a1e7139554
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095204217 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.4095204217
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.506441378
Short name T58
Test name
Test status
Simulation time 567614261 ps
CPU time 70.08 seconds
Started Jul 27 05:55:11 PM PDT 24
Finished Jul 27 05:56:21 PM PDT 24
Peak memory 212400 kb
Host smart-48b6d80b-f86f-40ce-8dc5-1931d251a335
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506441378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.506441378
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2995587172
Short name T50
Test name
Test status
Simulation time 1689983564 ps
CPU time 117.57 seconds
Started Jul 27 05:36:22 PM PDT 24
Finished Jul 27 05:38:20 PM PDT 24
Peak memory 234276 kb
Host smart-0eb70e2b-95b6-48c4-8e2e-fd8ec2a01988
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995587172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2995587172
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.608893864
Short name T64
Test name
Test status
Simulation time 621050720 ps
CPU time 16.8 seconds
Started Jul 27 05:35:42 PM PDT 24
Finished Jul 27 05:35:59 PM PDT 24
Peak memory 215480 kb
Host smart-8e305ff4-40a5-4a75-adef-f87371fe0b5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608893864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.608893864
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.890793251
Short name T21
Test name
Test status
Simulation time 948886458 ps
CPU time 99.62 seconds
Started Jul 27 05:35:27 PM PDT 24
Finished Jul 27 05:37:07 PM PDT 24
Peak memory 237188 kb
Host smart-612edb45-1043-4c54-ad23-48fa0503cf33
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890793251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.890793251
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2958203582
Short name T67
Test name
Test status
Simulation time 3152498176 ps
CPU time 45.21 seconds
Started Jul 27 05:54:50 PM PDT 24
Finished Jul 27 05:55:35 PM PDT 24
Peak memory 210796 kb
Host smart-2b885ce0-731b-4de7-ab5b-c5b07b2c4fd9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958203582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2958203582
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1384004173
Short name T127
Test name
Test status
Simulation time 1799629458 ps
CPU time 70.39 seconds
Started Jul 27 05:54:55 PM PDT 24
Finished Jul 27 05:56:05 PM PDT 24
Peak memory 218832 kb
Host smart-98b83f7b-8a80-4849-be87-c3e63a5fb984
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384004173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1384004173
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3661997058
Short name T151
Test name
Test status
Simulation time 171926571 ps
CPU time 4.15 seconds
Started Jul 27 05:35:28 PM PDT 24
Finished Jul 27 05:35:33 PM PDT 24
Peak memory 211768 kb
Host smart-b1f0b324-6a7f-47ba-b264-33d1689272fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661997058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3661997058
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.583737350
Short name T141
Test name
Test status
Simulation time 4139239144 ps
CPU time 16.05 seconds
Started Jul 27 05:35:58 PM PDT 24
Finished Jul 27 05:36:14 PM PDT 24
Peak memory 212740 kb
Host smart-1111258d-601d-4864-bbfd-639def309a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583737350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.583737350
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.536622771
Short name T98
Test name
Test status
Simulation time 249451152 ps
CPU time 11.06 seconds
Started Jul 27 05:35:28 PM PDT 24
Finished Jul 27 05:35:39 PM PDT 24
Peak memory 212796 kb
Host smart-39122310-aa2c-4e80-8985-91ee5389bb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536622771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.536622771
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1879757232
Short name T123
Test name
Test status
Simulation time 996599184 ps
CPU time 68.1 seconds
Started Jul 27 05:55:13 PM PDT 24
Finished Jul 27 05:56:21 PM PDT 24
Peak memory 212432 kb
Host smart-f60a35da-f54a-4d49-8232-912e8dd67c70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879757232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1879757232
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2157508731
Short name T42
Test name
Test status
Simulation time 9940152662 ps
CPU time 109.46 seconds
Started Jul 27 05:36:07 PM PDT 24
Finished Jul 27 05:37:57 PM PDT 24
Peak memory 212980 kb
Host smart-99ef42cf-402e-4a8d-84d3-ba26d1d316c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157508731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2157508731
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3787376541
Short name T92
Test name
Test status
Simulation time 565270126 ps
CPU time 27.66 seconds
Started Jul 27 05:55:11 PM PDT 24
Finished Jul 27 05:55:39 PM PDT 24
Peak memory 210724 kb
Host smart-a68b608c-2932-42b1-923b-a2aebef0d644
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787376541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3787376541
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1948636207
Short name T413
Test name
Test status
Simulation time 1284749092 ps
CPU time 26.79 seconds
Started Jul 27 05:55:12 PM PDT 24
Finished Jul 27 05:55:39 PM PDT 24
Peak memory 210668 kb
Host smart-70a20e2d-ce03-4a91-a992-65c9312e90f6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948636207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1948636207
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2639661331
Short name T128
Test name
Test status
Simulation time 593398399 ps
CPU time 71.35 seconds
Started Jul 27 05:55:10 PM PDT 24
Finished Jul 27 05:56:21 PM PDT 24
Peak memory 212512 kb
Host smart-189c29f5-7a1d-4c10-92e8-6e9987770240
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639661331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2639661331
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1643131260
Short name T132
Test name
Test status
Simulation time 436613952 ps
CPU time 67.49 seconds
Started Jul 27 05:55:10 PM PDT 24
Finished Jul 27 05:56:18 PM PDT 24
Peak memory 213192 kb
Host smart-6dea5374-ec1d-45e4-84ab-0413279e4e2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643131260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1643131260
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3689086741
Short name T62
Test name
Test status
Simulation time 533504218 ps
CPU time 7.31 seconds
Started Jul 27 05:54:52 PM PDT 24
Finished Jul 27 05:55:00 PM PDT 24
Peak memory 210720 kb
Host smart-d2b168bd-5229-4ea0-a02b-4e0b272cb09e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689086741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3689086741
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3791255980
Short name T82
Test name
Test status
Simulation time 773350877 ps
CPU time 34.63 seconds
Started Jul 27 05:35:53 PM PDT 24
Finished Jul 27 05:36:28 PM PDT 24
Peak memory 216088 kb
Host smart-638acb7d-d040-497e-8a09-213e869a6bda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791255980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3791255980
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2035070192
Short name T96
Test name
Test status
Simulation time 1662517098 ps
CPU time 19.09 seconds
Started Jul 27 05:36:22 PM PDT 24
Finished Jul 27 05:36:41 PM PDT 24
Peak memory 214304 kb
Host smart-dd351095-ac20-4028-a21d-73e385fb32a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035070192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2035070192
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3834862015
Short name T70
Test name
Test status
Simulation time 348374395 ps
CPU time 4.06 seconds
Started Jul 27 05:54:48 PM PDT 24
Finished Jul 27 05:54:52 PM PDT 24
Peak memory 210624 kb
Host smart-5b16f664-795d-4d26-acc5-87ae0db39e3a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834862015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3834862015
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1364090279
Short name T418
Test name
Test status
Simulation time 655384431 ps
CPU time 5.18 seconds
Started Jul 27 05:54:47 PM PDT 24
Finished Jul 27 05:54:53 PM PDT 24
Peak memory 210548 kb
Host smart-c3f67241-a7e6-4b9b-bfe9-a5711c96ddfc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364090279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1364090279
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.370586361
Short name T422
Test name
Test status
Simulation time 130591219 ps
CPU time 8.24 seconds
Started Jul 27 05:54:49 PM PDT 24
Finished Jul 27 05:54:57 PM PDT 24
Peak memory 210536 kb
Host smart-8710dfe6-9ff5-4c35-8689-8d317c24550b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370586361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.370586361
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.195774956
Short name T456
Test name
Test status
Simulation time 139574334 ps
CPU time 5.89 seconds
Started Jul 27 05:54:52 PM PDT 24
Finished Jul 27 05:54:58 PM PDT 24
Peak memory 218916 kb
Host smart-4094abc6-5696-4724-bfb1-01dbc55df67d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195774956 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.195774956
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3011302960
Short name T73
Test name
Test status
Simulation time 494340884 ps
CPU time 4.93 seconds
Started Jul 27 05:54:47 PM PDT 24
Finished Jul 27 05:54:52 PM PDT 24
Peak memory 210564 kb
Host smart-9560787c-20f5-4a02-a9d7-6cecf422320b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011302960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3011302960
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3242383596
Short name T395
Test name
Test status
Simulation time 350152863 ps
CPU time 4.12 seconds
Started Jul 27 05:54:49 PM PDT 24
Finished Jul 27 05:54:54 PM PDT 24
Peak memory 210452 kb
Host smart-2e4a0a9b-ff63-424a-b4d6-804a70303bda
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242383596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3242383596
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2629386774
Short name T431
Test name
Test status
Simulation time 320969629 ps
CPU time 4.23 seconds
Started Jul 27 05:54:47 PM PDT 24
Finished Jul 27 05:54:51 PM PDT 24
Peak memory 210504 kb
Host smart-bb0ac064-bc81-40e0-a04a-61004f395be2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629386774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2629386774
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.605793526
Short name T435
Test name
Test status
Simulation time 273706319 ps
CPU time 9.27 seconds
Started Jul 27 05:54:49 PM PDT 24
Finished Jul 27 05:54:58 PM PDT 24
Peak memory 218860 kb
Host smart-80b1d4eb-167d-4b87-97cc-20b561330cd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605793526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.605793526
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1745584375
Short name T459
Test name
Test status
Simulation time 425888915 ps
CPU time 70 seconds
Started Jul 27 05:54:48 PM PDT 24
Finished Jul 27 05:55:58 PM PDT 24
Peak memory 212480 kb
Host smart-ef260c10-eb67-4e44-b3d1-bfc5dd9fe924
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745584375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1745584375
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3745057113
Short name T464
Test name
Test status
Simulation time 498651465 ps
CPU time 5.22 seconds
Started Jul 27 05:54:54 PM PDT 24
Finished Jul 27 05:54:59 PM PDT 24
Peak memory 210584 kb
Host smart-6aaa9a35-9aad-498a-b00e-f91d5901c570
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745057113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3745057113
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1229141536
Short name T406
Test name
Test status
Simulation time 520908560 ps
CPU time 5.56 seconds
Started Jul 27 05:54:51 PM PDT 24
Finished Jul 27 05:54:57 PM PDT 24
Peak memory 210612 kb
Host smart-a5a957a1-59d6-42b7-91ed-26c16196093e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229141536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1229141536
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3926234768
Short name T450
Test name
Test status
Simulation time 254042000 ps
CPU time 6.66 seconds
Started Jul 27 05:54:55 PM PDT 24
Finished Jul 27 05:55:02 PM PDT 24
Peak memory 210568 kb
Host smart-0d0c9d13-6e6f-418d-a2db-2a65f7ce4b37
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926234768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3926234768
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.882119663
Short name T384
Test name
Test status
Simulation time 371119145 ps
CPU time 4.62 seconds
Started Jul 27 05:54:54 PM PDT 24
Finished Jul 27 05:54:59 PM PDT 24
Peak memory 218812 kb
Host smart-8a719532-f6c2-48ae-9238-5b1048f04d74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882119663 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.882119663
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2996961626
Short name T437
Test name
Test status
Simulation time 85728787 ps
CPU time 4.16 seconds
Started Jul 27 05:54:50 PM PDT 24
Finished Jul 27 05:54:54 PM PDT 24
Peak memory 210592 kb
Host smart-c9e40028-d82b-448d-8057-aa1eedc0b453
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996961626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2996961626
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3233367834
Short name T458
Test name
Test status
Simulation time 554199352 ps
CPU time 4.08 seconds
Started Jul 27 05:54:54 PM PDT 24
Finished Jul 27 05:54:58 PM PDT 24
Peak memory 210436 kb
Host smart-3b148c64-d298-4856-8ccd-eaf42552cd4d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233367834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3233367834
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3410936734
Short name T381
Test name
Test status
Simulation time 132208608 ps
CPU time 5.08 seconds
Started Jul 27 05:54:54 PM PDT 24
Finished Jul 27 05:54:59 PM PDT 24
Peak memory 210496 kb
Host smart-1d6c7c3c-4bf3-4f05-a924-e92fd333599a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410936734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3410936734
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.663451959
Short name T114
Test name
Test status
Simulation time 1132161110 ps
CPU time 28.11 seconds
Started Jul 27 05:54:50 PM PDT 24
Finished Jul 27 05:55:19 PM PDT 24
Peak memory 210648 kb
Host smart-031f1911-d70a-49fa-9173-c28d11ece6c4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663451959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.663451959
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3724577252
Short name T447
Test name
Test status
Simulation time 95929588 ps
CPU time 6.01 seconds
Started Jul 27 05:54:52 PM PDT 24
Finished Jul 27 05:54:59 PM PDT 24
Peak memory 210640 kb
Host smart-5b894550-9faa-4148-b13d-1333a7b1baef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724577252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3724577252
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2195394020
Short name T451
Test name
Test status
Simulation time 1898069111 ps
CPU time 10.12 seconds
Started Jul 27 05:54:54 PM PDT 24
Finished Jul 27 05:55:04 PM PDT 24
Peak memory 214456 kb
Host smart-df7aad12-66d4-4bb6-b2bd-d7dc0a885f2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195394020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2195394020
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3073718003
Short name T440
Test name
Test status
Simulation time 182676760 ps
CPU time 4.81 seconds
Started Jul 27 05:55:09 PM PDT 24
Finished Jul 27 05:55:14 PM PDT 24
Peak memory 218864 kb
Host smart-6dcad783-8939-4ed3-9a79-c024b3161b5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073718003 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3073718003
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4134259338
Short name T386
Test name
Test status
Simulation time 333225794 ps
CPU time 4.23 seconds
Started Jul 27 05:55:12 PM PDT 24
Finished Jul 27 05:55:16 PM PDT 24
Peak memory 210624 kb
Host smart-b8b2f1ab-24ea-44f8-8276-f38e3ed64a92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134259338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4134259338
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2955931954
Short name T86
Test name
Test status
Simulation time 615665413 ps
CPU time 22.35 seconds
Started Jul 27 05:55:14 PM PDT 24
Finished Jul 27 05:55:36 PM PDT 24
Peak memory 210740 kb
Host smart-5ab242a1-42f8-4890-bb7d-f02657b044e6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955931954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2955931954
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1565640484
Short name T466
Test name
Test status
Simulation time 2497648515 ps
CPU time 5.05 seconds
Started Jul 27 05:55:13 PM PDT 24
Finished Jul 27 05:55:18 PM PDT 24
Peak memory 218840 kb
Host smart-3239a6b1-fb44-43de-982d-cadeb4e6251b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565640484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1565640484
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3432259393
Short name T434
Test name
Test status
Simulation time 89324342 ps
CPU time 6.8 seconds
Started Jul 27 05:55:12 PM PDT 24
Finished Jul 27 05:55:19 PM PDT 24
Peak memory 215680 kb
Host smart-247b2d13-dc3d-4ba8-84f2-5c611cb3acd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432259393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3432259393
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2016901806
Short name T131
Test name
Test status
Simulation time 610574093 ps
CPU time 38.78 seconds
Started Jul 27 05:55:13 PM PDT 24
Finished Jul 27 05:55:52 PM PDT 24
Peak memory 218800 kb
Host smart-514fe72f-ec82-4538-8233-cd5eaa0a54fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016901806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2016901806
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4240874891
Short name T423
Test name
Test status
Simulation time 150212162 ps
CPU time 5.46 seconds
Started Jul 27 05:55:12 PM PDT 24
Finished Jul 27 05:55:18 PM PDT 24
Peak memory 218828 kb
Host smart-f60ca701-42b3-4eb7-b273-baf14056b8b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240874891 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4240874891
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2843349892
Short name T61
Test name
Test status
Simulation time 895641450 ps
CPU time 5.2 seconds
Started Jul 27 05:55:11 PM PDT 24
Finished Jul 27 05:55:16 PM PDT 24
Peak memory 218724 kb
Host smart-d256b4d8-2d6a-4941-ad15-7c03ff273b73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843349892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2843349892
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2619451831
Short name T472
Test name
Test status
Simulation time 86606798 ps
CPU time 4.59 seconds
Started Jul 27 05:55:09 PM PDT 24
Finished Jul 27 05:55:13 PM PDT 24
Peak memory 210608 kb
Host smart-252033d0-1548-46b0-8039-0ac116b55767
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619451831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2619451831
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1167225494
Short name T454
Test name
Test status
Simulation time 286469013 ps
CPU time 7.95 seconds
Started Jul 27 05:55:13 PM PDT 24
Finished Jul 27 05:55:21 PM PDT 24
Peak memory 215668 kb
Host smart-cbdf3496-93be-432b-ae8b-13a413503ace
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167225494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1167225494
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1424474792
Short name T134
Test name
Test status
Simulation time 253604798 ps
CPU time 39.42 seconds
Started Jul 27 05:55:11 PM PDT 24
Finished Jul 27 05:55:51 PM PDT 24
Peak memory 212348 kb
Host smart-24474570-ad87-4bff-b96f-1e09ec22d2fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424474792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1424474792
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1112500956
Short name T401
Test name
Test status
Simulation time 153507819 ps
CPU time 6.12 seconds
Started Jul 27 05:55:12 PM PDT 24
Finished Jul 27 05:55:18 PM PDT 24
Peak memory 218868 kb
Host smart-72922dd7-08c3-47bc-95e4-70ede827f40d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112500956 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1112500956
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.810458434
Short name T470
Test name
Test status
Simulation time 521705130 ps
CPU time 5.14 seconds
Started Jul 27 05:55:11 PM PDT 24
Finished Jul 27 05:55:16 PM PDT 24
Peak memory 218772 kb
Host smart-33d4e3d8-daf7-45a7-9fbe-09d1a6e2c1a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810458434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.810458434
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2365252545
Short name T463
Test name
Test status
Simulation time 252078625 ps
CPU time 6.01 seconds
Started Jul 27 05:55:13 PM PDT 24
Finished Jul 27 05:55:19 PM PDT 24
Peak memory 218828 kb
Host smart-e61b4eb8-fb7a-4106-ba32-2c89fefa795d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365252545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2365252545
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2824993572
Short name T427
Test name
Test status
Simulation time 167040242 ps
CPU time 7.32 seconds
Started Jul 27 05:55:14 PM PDT 24
Finished Jul 27 05:55:22 PM PDT 24
Peak memory 218716 kb
Host smart-9bc947dc-28a9-4706-b8ec-0c5fc76c853e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824993572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2824993572
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3957246581
Short name T442
Test name
Test status
Simulation time 552477920 ps
CPU time 5.05 seconds
Started Jul 27 05:55:13 PM PDT 24
Finished Jul 27 05:55:18 PM PDT 24
Peak memory 215172 kb
Host smart-96eabf3c-ca2d-4b68-8fad-3868fa2fbaae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957246581 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3957246581
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1060585873
Short name T399
Test name
Test status
Simulation time 162251624 ps
CPU time 4.19 seconds
Started Jul 27 05:55:11 PM PDT 24
Finished Jul 27 05:55:16 PM PDT 24
Peak memory 217408 kb
Host smart-5d82ec57-7c5a-4873-98ea-e97d777a024d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060585873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1060585873
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2935132493
Short name T113
Test name
Test status
Simulation time 4329507225 ps
CPU time 32.78 seconds
Started Jul 27 05:55:10 PM PDT 24
Finished Jul 27 05:55:43 PM PDT 24
Peak memory 210732 kb
Host smart-99fa08a6-9c49-4119-b374-bb4906a09910
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935132493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2935132493
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1661037062
Short name T453
Test name
Test status
Simulation time 594970079 ps
CPU time 6.6 seconds
Started Jul 27 05:55:13 PM PDT 24
Finished Jul 27 05:55:20 PM PDT 24
Peak memory 210832 kb
Host smart-cdeeffa4-611e-495e-a447-12aa3e677f75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661037062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1661037062
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2355474519
Short name T467
Test name
Test status
Simulation time 832494062 ps
CPU time 7.39 seconds
Started Jul 27 05:55:10 PM PDT 24
Finished Jul 27 05:55:17 PM PDT 24
Peak memory 215620 kb
Host smart-570c6d0d-6fa7-43e3-9d7a-b5d38950bd85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355474519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2355474519
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2152520416
Short name T433
Test name
Test status
Simulation time 422195474 ps
CPU time 5.23 seconds
Started Jul 27 05:55:14 PM PDT 24
Finished Jul 27 05:55:19 PM PDT 24
Peak memory 218952 kb
Host smart-d4f21bd2-0bf1-4e50-badd-3f99abd857e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152520416 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2152520416
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1806752683
Short name T417
Test name
Test status
Simulation time 86700310 ps
CPU time 4.25 seconds
Started Jul 27 05:55:12 PM PDT 24
Finished Jul 27 05:55:16 PM PDT 24
Peak memory 210472 kb
Host smart-8b581a93-3a6d-4c7c-9aed-62aaeeb15fff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806752683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1806752683
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.71146212
Short name T468
Test name
Test status
Simulation time 531880004 ps
CPU time 21.43 seconds
Started Jul 27 05:55:14 PM PDT 24
Finished Jul 27 05:55:36 PM PDT 24
Peak memory 210556 kb
Host smart-f21d3bc3-1599-451d-a2a5-11d2682acbf9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71146212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pas
sthru_mem_tl_intg_err.71146212
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2476678562
Short name T404
Test name
Test status
Simulation time 332517078 ps
CPU time 4.42 seconds
Started Jul 27 05:55:13 PM PDT 24
Finished Jul 27 05:55:18 PM PDT 24
Peak memory 210532 kb
Host smart-c0c98ec8-9e8d-4988-9d19-fa64fedac693
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476678562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2476678562
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.797394600
Short name T444
Test name
Test status
Simulation time 127749285 ps
CPU time 7.25 seconds
Started Jul 27 05:55:13 PM PDT 24
Finished Jul 27 05:55:21 PM PDT 24
Peak memory 218820 kb
Host smart-0be3d329-c4f9-46e0-bf98-e3d3dd152f5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797394600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.797394600
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3150183582
Short name T136
Test name
Test status
Simulation time 528309542 ps
CPU time 68.97 seconds
Started Jul 27 05:55:13 PM PDT 24
Finished Jul 27 05:56:22 PM PDT 24
Peak memory 212304 kb
Host smart-62624ff8-fca7-462a-b405-e673c7be45bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150183582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3150183582
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1847828528
Short name T419
Test name
Test status
Simulation time 499624030 ps
CPU time 5.13 seconds
Started Jul 27 05:55:13 PM PDT 24
Finished Jul 27 05:55:19 PM PDT 24
Peak memory 214656 kb
Host smart-7d247dfd-4b32-47be-9d26-0976b53f5bc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847828528 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1847828528
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.774470726
Short name T94
Test name
Test status
Simulation time 171526171 ps
CPU time 4.03 seconds
Started Jul 27 05:55:12 PM PDT 24
Finished Jul 27 05:55:16 PM PDT 24
Peak memory 217916 kb
Host smart-9f2c923d-ed57-4aab-8608-6ce360b296e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774470726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.774470726
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3267224036
Short name T121
Test name
Test status
Simulation time 2086914483 ps
CPU time 22.1 seconds
Started Jul 27 05:55:14 PM PDT 24
Finished Jul 27 05:55:37 PM PDT 24
Peak memory 210628 kb
Host smart-ad9a28f1-486c-4cdc-b5a8-a4239c8bd08f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267224036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3267224036
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.353848257
Short name T107
Test name
Test status
Simulation time 129187341 ps
CPU time 5.18 seconds
Started Jul 27 05:55:11 PM PDT 24
Finished Jul 27 05:55:17 PM PDT 24
Peak memory 210656 kb
Host smart-f0174d2b-ac93-4c62-85c3-688dff33d417
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353848257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.353848257
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3061373631
Short name T390
Test name
Test status
Simulation time 442448819 ps
CPU time 7.56 seconds
Started Jul 27 05:55:10 PM PDT 24
Finished Jul 27 05:55:18 PM PDT 24
Peak memory 218884 kb
Host smart-8586713d-3ad7-4b75-a5b4-1aaee8cb0d3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061373631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3061373631
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3589763268
Short name T425
Test name
Test status
Simulation time 993577214 ps
CPU time 7.61 seconds
Started Jul 27 05:55:17 PM PDT 24
Finished Jul 27 05:55:25 PM PDT 24
Peak memory 212840 kb
Host smart-68b63010-cf2e-4b71-b0db-275cfab0a071
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589763268 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3589763268
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1079901068
Short name T446
Test name
Test status
Simulation time 1380748543 ps
CPU time 4.22 seconds
Started Jul 27 05:55:17 PM PDT 24
Finished Jul 27 05:55:22 PM PDT 24
Peak memory 217844 kb
Host smart-e6979d83-84c4-41f7-8e93-37b63084ffbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079901068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1079901068
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1259003968
Short name T95
Test name
Test status
Simulation time 2083157205 ps
CPU time 22.04 seconds
Started Jul 27 05:55:12 PM PDT 24
Finished Jul 27 05:55:34 PM PDT 24
Peak memory 210664 kb
Host smart-08475745-5148-4f06-8363-17cc369a2ad6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259003968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1259003968
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3086413982
Short name T415
Test name
Test status
Simulation time 2488609767 ps
CPU time 5.16 seconds
Started Jul 27 05:55:19 PM PDT 24
Finished Jul 27 05:55:25 PM PDT 24
Peak memory 210732 kb
Host smart-671a00ac-a084-46b2-91a4-c58ef6d6afcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086413982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3086413982
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.987292620
Short name T430
Test name
Test status
Simulation time 175176963 ps
CPU time 7.05 seconds
Started Jul 27 05:55:09 PM PDT 24
Finished Jul 27 05:55:16 PM PDT 24
Peak memory 215836 kb
Host smart-c6b42592-ccaf-4716-8e29-e50e7185a482
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987292620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.987292620
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4035307382
Short name T133
Test name
Test status
Simulation time 390910408 ps
CPU time 37.25 seconds
Started Jul 27 05:55:13 PM PDT 24
Finished Jul 27 05:55:50 PM PDT 24
Peak memory 212264 kb
Host smart-81d4ddce-ba4e-4908-82fb-f86ce9805bc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035307382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.4035307382
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.403652385
Short name T396
Test name
Test status
Simulation time 263261816 ps
CPU time 5.19 seconds
Started Jul 27 05:55:22 PM PDT 24
Finished Jul 27 05:55:28 PM PDT 24
Peak memory 211976 kb
Host smart-72927148-b5b4-4346-8cc1-1ee6580a136d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403652385 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.403652385
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3630301440
Short name T68
Test name
Test status
Simulation time 87550115 ps
CPU time 4.14 seconds
Started Jul 27 05:55:20 PM PDT 24
Finished Jul 27 05:55:24 PM PDT 24
Peak memory 218648 kb
Host smart-dbd33f22-af11-45ab-857e-a0e7aa406775
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630301440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3630301440
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4049322295
Short name T84
Test name
Test status
Simulation time 757377670 ps
CPU time 18.41 seconds
Started Jul 27 05:55:17 PM PDT 24
Finished Jul 27 05:55:35 PM PDT 24
Peak memory 210732 kb
Host smart-2df0bdad-6051-4513-8576-5bff36989de4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049322295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4049322295
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2126777766
Short name T412
Test name
Test status
Simulation time 322246640 ps
CPU time 5.22 seconds
Started Jul 27 05:55:19 PM PDT 24
Finished Jul 27 05:55:24 PM PDT 24
Peak memory 218796 kb
Host smart-b11e7198-d36e-4ce9-8fa4-472960690a36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126777766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2126777766
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1756571495
Short name T407
Test name
Test status
Simulation time 178576199 ps
CPU time 8.82 seconds
Started Jul 27 05:55:23 PM PDT 24
Finished Jul 27 05:55:32 PM PDT 24
Peak memory 218852 kb
Host smart-6dd21f37-5f64-47c6-a01a-d4ffa4da2ae7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756571495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1756571495
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3908585059
Short name T57
Test name
Test status
Simulation time 254441112 ps
CPU time 69.04 seconds
Started Jul 27 05:55:17 PM PDT 24
Finished Jul 27 05:56:26 PM PDT 24
Peak memory 218812 kb
Host smart-4f1b7be8-0c6d-4a32-b72c-810d786cdd39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908585059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3908585059
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2416981209
Short name T414
Test name
Test status
Simulation time 561856326 ps
CPU time 6.09 seconds
Started Jul 27 05:55:25 PM PDT 24
Finished Jul 27 05:55:32 PM PDT 24
Peak memory 215668 kb
Host smart-00b542da-a990-4d95-a641-6e422306c05b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416981209 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2416981209
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.644483579
Short name T471
Test name
Test status
Simulation time 347100760 ps
CPU time 4.11 seconds
Started Jul 27 05:55:15 PM PDT 24
Finished Jul 27 05:55:19 PM PDT 24
Peak memory 218024 kb
Host smart-24b9085e-d3bf-409d-b9ef-9b85f498e821
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644483579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.644483579
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3842947114
Short name T85
Test name
Test status
Simulation time 368953626 ps
CPU time 18.24 seconds
Started Jul 27 05:55:17 PM PDT 24
Finished Jul 27 05:55:35 PM PDT 24
Peak memory 210708 kb
Host smart-80d21e12-c101-4b4c-8dfb-cbad65d20677
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842947114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3842947114
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1219605241
Short name T445
Test name
Test status
Simulation time 257634587 ps
CPU time 5.11 seconds
Started Jul 27 05:55:23 PM PDT 24
Finished Jul 27 05:55:28 PM PDT 24
Peak memory 210576 kb
Host smart-945dab5b-ce6a-45de-872d-3f8c9639f7da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219605241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1219605241
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1704734958
Short name T443
Test name
Test status
Simulation time 350120366 ps
CPU time 6.54 seconds
Started Jul 27 05:55:19 PM PDT 24
Finished Jul 27 05:55:25 PM PDT 24
Peak memory 215516 kb
Host smart-77734565-5e1f-450c-9fe3-35a4e1a05a22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704734958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1704734958
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2053824490
Short name T457
Test name
Test status
Simulation time 205975510 ps
CPU time 37.19 seconds
Started Jul 27 05:55:24 PM PDT 24
Finished Jul 27 05:56:02 PM PDT 24
Peak memory 218868 kb
Host smart-9b4f2dea-c893-42de-965d-f4b3603d8421
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053824490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2053824490
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3164829789
Short name T416
Test name
Test status
Simulation time 507711557 ps
CPU time 8.29 seconds
Started Jul 27 05:55:21 PM PDT 24
Finished Jul 27 05:55:30 PM PDT 24
Peak memory 215680 kb
Host smart-9a1ec71c-2d75-494e-866e-64429376ba29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164829789 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3164829789
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2058018208
Short name T87
Test name
Test status
Simulation time 226501053 ps
CPU time 4.14 seconds
Started Jul 27 05:55:24 PM PDT 24
Finished Jul 27 05:55:28 PM PDT 24
Peak memory 217448 kb
Host smart-3b2f843f-6307-4338-8384-de2df6e7a4e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058018208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2058018208
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1294053242
Short name T91
Test name
Test status
Simulation time 386080216 ps
CPU time 18.76 seconds
Started Jul 27 05:55:19 PM PDT 24
Finished Jul 27 05:55:38 PM PDT 24
Peak memory 210664 kb
Host smart-3a67fe76-ca06-4363-b415-1da493e1e232
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294053242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1294053242
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.801246191
Short name T420
Test name
Test status
Simulation time 142933640 ps
CPU time 7.11 seconds
Started Jul 27 05:55:18 PM PDT 24
Finished Jul 27 05:55:25 PM PDT 24
Peak memory 210612 kb
Host smart-30e63865-1b8c-4900-ac53-4b4131c65d24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801246191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.801246191
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.568220366
Short name T408
Test name
Test status
Simulation time 1390806542 ps
CPU time 6.69 seconds
Started Jul 27 05:55:17 PM PDT 24
Finished Jul 27 05:55:24 PM PDT 24
Peak memory 215372 kb
Host smart-38fe754f-d319-4fb2-bc7e-b429ca8cf105
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568220366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.568220366
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3253512616
Short name T124
Test name
Test status
Simulation time 1688610835 ps
CPU time 37.84 seconds
Started Jul 27 05:55:28 PM PDT 24
Finished Jul 27 05:56:06 PM PDT 24
Peak memory 211168 kb
Host smart-c3d1decd-347b-43af-8666-7820065de1bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253512616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3253512616
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.268759444
Short name T93
Test name
Test status
Simulation time 90146026 ps
CPU time 4.25 seconds
Started Jul 27 05:54:56 PM PDT 24
Finished Jul 27 05:55:00 PM PDT 24
Peak memory 218656 kb
Host smart-b90e3c09-4e06-4c46-9479-d5cfa2e1ddbe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268759444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.268759444
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4080241141
Short name T112
Test name
Test status
Simulation time 498856425 ps
CPU time 5.36 seconds
Started Jul 27 05:54:54 PM PDT 24
Finished Jul 27 05:55:00 PM PDT 24
Peak memory 218780 kb
Host smart-c2832e41-0744-4b46-a59c-bad2db6bed45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080241141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.4080241141
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1193799165
Short name T461
Test name
Test status
Simulation time 96955686 ps
CPU time 7.48 seconds
Started Jul 27 05:54:55 PM PDT 24
Finished Jul 27 05:55:03 PM PDT 24
Peak memory 210544 kb
Host smart-80f6a32a-2ddc-4f8c-9468-e7c520069997
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193799165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1193799165
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.518133959
Short name T460
Test name
Test status
Simulation time 7123904924 ps
CPU time 8.49 seconds
Started Jul 27 05:54:53 PM PDT 24
Finished Jul 27 05:55:02 PM PDT 24
Peak memory 216464 kb
Host smart-26979100-7495-4c8a-ae20-91bce63caee3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518133959 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.518133959
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.381931020
Short name T108
Test name
Test status
Simulation time 2471939892 ps
CPU time 5.13 seconds
Started Jul 27 05:54:56 PM PDT 24
Finished Jul 27 05:55:02 PM PDT 24
Peak memory 218744 kb
Host smart-34aaa815-c4b4-4ecf-8e2f-56c9d5678c41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381931020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.381931020
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.603561465
Short name T439
Test name
Test status
Simulation time 288613976 ps
CPU time 4.19 seconds
Started Jul 27 05:54:56 PM PDT 24
Finished Jul 27 05:55:00 PM PDT 24
Peak memory 210424 kb
Host smart-ab1b4a87-5b90-4091-a825-8469b824498f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603561465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.603561465
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3598025173
Short name T392
Test name
Test status
Simulation time 89238654 ps
CPU time 4.16 seconds
Started Jul 27 05:54:51 PM PDT 24
Finished Jul 27 05:54:55 PM PDT 24
Peak memory 210460 kb
Host smart-6059f408-9862-4cad-93f9-41127c8f3160
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598025173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3598025173
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3969488853
Short name T462
Test name
Test status
Simulation time 3136892666 ps
CPU time 32.1 seconds
Started Jul 27 05:54:53 PM PDT 24
Finished Jul 27 05:55:25 PM PDT 24
Peak memory 210752 kb
Host smart-d663198c-b491-431e-8ba3-6ec98f7a0c8c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969488853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3969488853
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3667172848
Short name T410
Test name
Test status
Simulation time 1382575442 ps
CPU time 5.4 seconds
Started Jul 27 05:54:55 PM PDT 24
Finished Jul 27 05:55:00 PM PDT 24
Peak memory 218832 kb
Host smart-cac0fe43-e12c-4824-b23d-25b5942dd117
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667172848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3667172848
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.796539945
Short name T382
Test name
Test status
Simulation time 130489843 ps
CPU time 8.64 seconds
Started Jul 27 05:54:58 PM PDT 24
Finished Jul 27 05:55:07 PM PDT 24
Peak memory 218900 kb
Host smart-ad39c40d-c0e1-491c-ab0a-71c471d8ff35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796539945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.796539945
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3709831530
Short name T441
Test name
Test status
Simulation time 361248300 ps
CPU time 37.85 seconds
Started Jul 27 05:54:53 PM PDT 24
Finished Jul 27 05:55:31 PM PDT 24
Peak memory 210968 kb
Host smart-0b5391b7-e542-4738-8b29-462911155785
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709831530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3709831530
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3639459719
Short name T88
Test name
Test status
Simulation time 539281879 ps
CPU time 5.11 seconds
Started Jul 27 05:55:02 PM PDT 24
Finished Jul 27 05:55:07 PM PDT 24
Peak memory 218636 kb
Host smart-de544bbc-eb0d-4900-a7d0-321c2e5b03c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639459719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3639459719
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3541292970
Short name T394
Test name
Test status
Simulation time 132455189 ps
CPU time 5.45 seconds
Started Jul 27 05:55:02 PM PDT 24
Finished Jul 27 05:55:07 PM PDT 24
Peak memory 210580 kb
Host smart-abf9ed10-1ad7-417b-b3cb-4a82b4016519
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541292970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3541292970
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1696334655
Short name T74
Test name
Test status
Simulation time 94295319 ps
CPU time 7.41 seconds
Started Jul 27 05:54:55 PM PDT 24
Finished Jul 27 05:55:02 PM PDT 24
Peak memory 210512 kb
Host smart-55ad894d-9d56-4075-b0e5-593ab151284c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696334655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1696334655
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1947372210
Short name T469
Test name
Test status
Simulation time 150405019 ps
CPU time 5.01 seconds
Started Jul 27 05:55:02 PM PDT 24
Finished Jul 27 05:55:07 PM PDT 24
Peak memory 215640 kb
Host smart-bef35459-76b0-4248-91b9-09a4a4370ca8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947372210 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1947372210
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2095282474
Short name T424
Test name
Test status
Simulation time 124515074 ps
CPU time 4.29 seconds
Started Jul 27 05:55:00 PM PDT 24
Finished Jul 27 05:55:05 PM PDT 24
Peak memory 210504 kb
Host smart-981d3a02-7013-414d-8765-016e51a4c3e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095282474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2095282474
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1615749116
Short name T455
Test name
Test status
Simulation time 132936177 ps
CPU time 4.96 seconds
Started Jul 27 05:54:53 PM PDT 24
Finished Jul 27 05:54:58 PM PDT 24
Peak memory 210484 kb
Host smart-ed99ce16-e4da-4777-a8fe-4030cc06e535
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615749116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1615749116
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.795355649
Short name T429
Test name
Test status
Simulation time 351594275 ps
CPU time 4.25 seconds
Started Jul 27 05:54:57 PM PDT 24
Finished Jul 27 05:55:01 PM PDT 24
Peak memory 210420 kb
Host smart-955ee988-2677-4542-9f54-700e360d21a0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795355649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
795355649
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2334739587
Short name T69
Test name
Test status
Simulation time 825335831 ps
CPU time 32.91 seconds
Started Jul 27 05:54:58 PM PDT 24
Finished Jul 27 05:55:31 PM PDT 24
Peak memory 210740 kb
Host smart-48ac98a2-738d-4538-97cd-9b970d82c503
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334739587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2334739587
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.101851470
Short name T111
Test name
Test status
Simulation time 1010335633 ps
CPU time 7.57 seconds
Started Jul 27 05:55:02 PM PDT 24
Finished Jul 27 05:55:10 PM PDT 24
Peak memory 210672 kb
Host smart-3e788a94-7f38-4d46-b648-263055513f0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101851470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.101851470
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3386322674
Short name T465
Test name
Test status
Simulation time 468183882 ps
CPU time 9.11 seconds
Started Jul 27 05:54:54 PM PDT 24
Finished Jul 27 05:55:03 PM PDT 24
Peak memory 214672 kb
Host smart-4997d4c8-dcf3-41ed-bf6b-e396778990b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386322674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3386322674
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.785000831
Short name T129
Test name
Test status
Simulation time 2505521644 ps
CPU time 36.89 seconds
Started Jul 27 05:54:54 PM PDT 24
Finished Jul 27 05:55:31 PM PDT 24
Peak memory 218896 kb
Host smart-c0d26a2a-96e4-4a36-a960-50301eb7f344
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785000831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.785000831
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.573164794
Short name T89
Test name
Test status
Simulation time 89707007 ps
CPU time 4.53 seconds
Started Jul 27 05:55:01 PM PDT 24
Finished Jul 27 05:55:05 PM PDT 24
Peak memory 210588 kb
Host smart-57d354f9-30cf-42d5-bca8-9d71208aed4e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573164794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.573164794
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3657841716
Short name T402
Test name
Test status
Simulation time 759974564 ps
CPU time 4.44 seconds
Started Jul 27 05:55:03 PM PDT 24
Finished Jul 27 05:55:08 PM PDT 24
Peak memory 217568 kb
Host smart-e06bf985-5d85-4123-b4c8-fdeb10201115
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657841716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3657841716
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3145923072
Short name T90
Test name
Test status
Simulation time 131951794 ps
CPU time 8.13 seconds
Started Jul 27 05:55:02 PM PDT 24
Finished Jul 27 05:55:10 PM PDT 24
Peak memory 210636 kb
Host smart-c8a8d5f4-75bf-415f-b2ee-77d764b4e6de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145923072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3145923072
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3182574400
Short name T60
Test name
Test status
Simulation time 297623255 ps
CPU time 6.15 seconds
Started Jul 27 05:55:01 PM PDT 24
Finished Jul 27 05:55:08 PM PDT 24
Peak memory 215520 kb
Host smart-24a9c974-4317-4b32-9211-ea7c2b74123a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182574400 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3182574400
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1697538918
Short name T436
Test name
Test status
Simulation time 127069254 ps
CPU time 5.14 seconds
Started Jul 27 05:55:03 PM PDT 24
Finished Jul 27 05:55:08 PM PDT 24
Peak memory 210576 kb
Host smart-3c1e778c-11ac-4c31-8ee4-fdc2abb6c588
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697538918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1697538918
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.61373907
Short name T391
Test name
Test status
Simulation time 172586755 ps
CPU time 4.34 seconds
Started Jul 27 05:55:02 PM PDT 24
Finished Jul 27 05:55:06 PM PDT 24
Peak memory 210436 kb
Host smart-c7dc5592-d8da-47ba-97e0-163547274b26
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61373907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_
mem_partial_access.61373907
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1818481123
Short name T400
Test name
Test status
Simulation time 1028849306 ps
CPU time 8.06 seconds
Started Jul 27 05:55:00 PM PDT 24
Finished Jul 27 05:55:08 PM PDT 24
Peak memory 210496 kb
Host smart-116f6786-d070-41c3-8847-344498f92bd8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818481123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1818481123
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.684377790
Short name T72
Test name
Test status
Simulation time 558302893 ps
CPU time 27.12 seconds
Started Jul 27 05:55:00 PM PDT 24
Finished Jul 27 05:55:27 PM PDT 24
Peak memory 210692 kb
Host smart-2f8f9a21-4097-481b-96e0-3a79b8f5a37b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684377790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.684377790
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1351870454
Short name T110
Test name
Test status
Simulation time 1381250304 ps
CPU time 5.13 seconds
Started Jul 27 05:55:02 PM PDT 24
Finished Jul 27 05:55:07 PM PDT 24
Peak memory 210640 kb
Host smart-0621b2c3-72e5-4214-950c-76471dedd5cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351870454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1351870454
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2248738869
Short name T383
Test name
Test status
Simulation time 131777763 ps
CPU time 7.63 seconds
Started Jul 27 05:55:02 PM PDT 24
Finished Jul 27 05:55:09 PM PDT 24
Peak memory 214584 kb
Host smart-63ecb5a8-70f9-4baa-8a3e-409b9014accc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248738869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2248738869
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.693247330
Short name T126
Test name
Test status
Simulation time 1483713408 ps
CPU time 68.13 seconds
Started Jul 27 05:55:02 PM PDT 24
Finished Jul 27 05:56:10 PM PDT 24
Peak memory 218868 kb
Host smart-df2457a3-19f2-4540-960f-c9555b0f67ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693247330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.693247330
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2550867772
Short name T449
Test name
Test status
Simulation time 632638788 ps
CPU time 5.72 seconds
Started Jul 27 05:55:10 PM PDT 24
Finished Jul 27 05:55:16 PM PDT 24
Peak memory 215892 kb
Host smart-6297d264-125d-4fd4-923b-f51cad31df25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550867772 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2550867772
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1447382438
Short name T411
Test name
Test status
Simulation time 522344914 ps
CPU time 5.16 seconds
Started Jul 27 05:55:00 PM PDT 24
Finished Jul 27 05:55:06 PM PDT 24
Peak memory 218616 kb
Host smart-bf3a5355-9bf7-4358-aba4-6333260fc41c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447382438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1447382438
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2960558160
Short name T448
Test name
Test status
Simulation time 829950586 ps
CPU time 32.92 seconds
Started Jul 27 05:55:02 PM PDT 24
Finished Jul 27 05:55:35 PM PDT 24
Peak memory 210728 kb
Host smart-afda4d1e-3fc7-4a9e-a022-7a71a76f737a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960558160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2960558160
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1985922143
Short name T109
Test name
Test status
Simulation time 308206979 ps
CPU time 4.25 seconds
Started Jul 27 05:55:09 PM PDT 24
Finished Jul 27 05:55:14 PM PDT 24
Peak memory 218752 kb
Host smart-fbb6088d-0f4a-4880-860e-ebb2d07243af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985922143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1985922143
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.308085155
Short name T432
Test name
Test status
Simulation time 828397215 ps
CPU time 7.99 seconds
Started Jul 27 05:55:01 PM PDT 24
Finished Jul 27 05:55:09 PM PDT 24
Peak memory 218824 kb
Host smart-a585039f-37ac-44fb-b8a4-fa6b7af196d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308085155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.308085155
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.314046399
Short name T130
Test name
Test status
Simulation time 1546029810 ps
CPU time 45.02 seconds
Started Jul 27 05:54:59 PM PDT 24
Finished Jul 27 05:55:44 PM PDT 24
Peak memory 219004 kb
Host smart-6c8250dd-c59e-4072-b59a-d82e19fd7590
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314046399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.314046399
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.116358055
Short name T389
Test name
Test status
Simulation time 156065465 ps
CPU time 6.27 seconds
Started Jul 27 05:55:13 PM PDT 24
Finished Jul 27 05:55:20 PM PDT 24
Peak memory 215244 kb
Host smart-d3506b57-b644-4a6c-b59a-f631477c4a86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116358055 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.116358055
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1235534654
Short name T388
Test name
Test status
Simulation time 90200528 ps
CPU time 4.28 seconds
Started Jul 27 05:55:12 PM PDT 24
Finished Jul 27 05:55:16 PM PDT 24
Peak memory 210516 kb
Host smart-2836e43a-3df5-4d9f-bb14-b79891b99fa2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235534654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1235534654
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1326159581
Short name T426
Test name
Test status
Simulation time 1128575086 ps
CPU time 27.24 seconds
Started Jul 27 05:55:13 PM PDT 24
Finished Jul 27 05:55:41 PM PDT 24
Peak memory 210636 kb
Host smart-201942bb-e35f-4373-83c0-1c18c804f553
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326159581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1326159581
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3806509960
Short name T106
Test name
Test status
Simulation time 89272985 ps
CPU time 4.32 seconds
Started Jul 27 05:55:12 PM PDT 24
Finished Jul 27 05:55:17 PM PDT 24
Peak memory 210664 kb
Host smart-a4ce65ae-d4d6-4a0a-a942-9f397f55de08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806509960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3806509960
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2670692727
Short name T397
Test name
Test status
Simulation time 450018377 ps
CPU time 7.49 seconds
Started Jul 27 05:55:10 PM PDT 24
Finished Jul 27 05:55:18 PM PDT 24
Peak memory 215780 kb
Host smart-a2ba7718-f0fc-46b8-b866-60bc743080c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670692727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2670692727
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.701879016
Short name T125
Test name
Test status
Simulation time 525406543 ps
CPU time 36.5 seconds
Started Jul 27 05:55:11 PM PDT 24
Finished Jul 27 05:55:48 PM PDT 24
Peak memory 218840 kb
Host smart-f11a8fe0-508a-4bff-9726-025c779fd9b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701879016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.701879016
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4277203075
Short name T393
Test name
Test status
Simulation time 120913778 ps
CPU time 5.23 seconds
Started Jul 27 05:55:13 PM PDT 24
Finished Jul 27 05:55:18 PM PDT 24
Peak memory 214052 kb
Host smart-bbf285ad-1495-4dae-9bc6-827ef3795aa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277203075 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4277203075
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1631068265
Short name T71
Test name
Test status
Simulation time 261833476 ps
CPU time 5 seconds
Started Jul 27 05:55:12 PM PDT 24
Finished Jul 27 05:55:17 PM PDT 24
Peak memory 218700 kb
Host smart-1c654d7a-5c91-405e-99ff-8cb4467df478
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631068265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1631068265
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3508475451
Short name T409
Test name
Test status
Simulation time 50047188672 ps
CPU time 49.81 seconds
Started Jul 27 05:55:14 PM PDT 24
Finished Jul 27 05:56:04 PM PDT 24
Peak memory 210784 kb
Host smart-13dbad3c-61c2-4b24-979a-18fc6b54e5ef
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508475451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3508475451
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1841419106
Short name T403
Test name
Test status
Simulation time 518950011 ps
CPU time 5.08 seconds
Started Jul 27 05:55:12 PM PDT 24
Finished Jul 27 05:55:17 PM PDT 24
Peak memory 210684 kb
Host smart-d2b8a5ef-2851-4a33-b6cb-306ea8d2dc5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841419106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1841419106
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.476376691
Short name T428
Test name
Test status
Simulation time 471596763 ps
CPU time 9.18 seconds
Started Jul 27 05:55:10 PM PDT 24
Finished Jul 27 05:55:19 PM PDT 24
Peak memory 218844 kb
Host smart-929b1e00-161d-4ec1-a863-a51f05961e87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476376691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.476376691
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.905855177
Short name T135
Test name
Test status
Simulation time 588052402 ps
CPU time 35.96 seconds
Started Jul 27 05:55:09 PM PDT 24
Finished Jul 27 05:55:45 PM PDT 24
Peak memory 218812 kb
Host smart-14f33eeb-d7e4-4b3c-a85b-28eca05b0541
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905855177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.905855177
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.302390933
Short name T385
Test name
Test status
Simulation time 770705836 ps
CPU time 5.83 seconds
Started Jul 27 05:55:10 PM PDT 24
Finished Jul 27 05:55:16 PM PDT 24
Peak memory 214800 kb
Host smart-8795e785-700a-41bc-9d8c-ef3ceeb7f85f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302390933 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.302390933
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2378534522
Short name T115
Test name
Test status
Simulation time 96569269 ps
CPU time 4.3 seconds
Started Jul 27 05:55:10 PM PDT 24
Finished Jul 27 05:55:15 PM PDT 24
Peak memory 217692 kb
Host smart-6f63fb4f-8330-415a-bf71-9a5b9cc5da42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378534522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2378534522
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1099867458
Short name T421
Test name
Test status
Simulation time 570950844 ps
CPU time 27.93 seconds
Started Jul 27 05:55:13 PM PDT 24
Finished Jul 27 05:55:41 PM PDT 24
Peak memory 210664 kb
Host smart-8dfe896d-f12f-41fb-b0b2-b12f7f8add67
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099867458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1099867458
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.829867181
Short name T452
Test name
Test status
Simulation time 1234803988 ps
CPU time 5.14 seconds
Started Jul 27 05:55:10 PM PDT 24
Finished Jul 27 05:55:15 PM PDT 24
Peak memory 210708 kb
Host smart-07d6e62f-3dea-4a48-891c-569502fefa72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829867181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.829867181
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3275026021
Short name T398
Test name
Test status
Simulation time 347801920 ps
CPU time 7.69 seconds
Started Jul 27 05:55:13 PM PDT 24
Finished Jul 27 05:55:21 PM PDT 24
Peak memory 218852 kb
Host smart-5b63ab1f-4b54-4200-8238-d56bebe1925e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275026021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3275026021
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3422016242
Short name T59
Test name
Test status
Simulation time 860108236 ps
CPU time 38.59 seconds
Started Jul 27 05:55:10 PM PDT 24
Finished Jul 27 05:55:49 PM PDT 24
Peak memory 211028 kb
Host smart-ac34b0a0-d3fd-4a32-8cb1-ad8daed00fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422016242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3422016242
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3257306618
Short name T387
Test name
Test status
Simulation time 371655234 ps
CPU time 4.81 seconds
Started Jul 27 05:55:09 PM PDT 24
Finished Jul 27 05:55:14 PM PDT 24
Peak memory 218912 kb
Host smart-b29710a7-2f02-4836-94d6-219fd61d012e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257306618 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3257306618
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1038748908
Short name T65
Test name
Test status
Simulation time 130091634 ps
CPU time 5.19 seconds
Started Jul 27 05:55:11 PM PDT 24
Finished Jul 27 05:55:17 PM PDT 24
Peak memory 218780 kb
Host smart-564fd875-d2ad-48a1-9c93-dbfb525e9e25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038748908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1038748908
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.4024757935
Short name T66
Test name
Test status
Simulation time 783764106 ps
CPU time 31.54 seconds
Started Jul 27 05:55:11 PM PDT 24
Finished Jul 27 05:55:42 PM PDT 24
Peak memory 210660 kb
Host smart-ef0088a4-cb14-4242-87ce-9666a69728a9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024757935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.4024757935
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.290125096
Short name T405
Test name
Test status
Simulation time 544951204 ps
CPU time 6.94 seconds
Started Jul 27 05:55:11 PM PDT 24
Finished Jul 27 05:55:18 PM PDT 24
Peak memory 218744 kb
Host smart-cbc04bf7-6a66-49b8-839c-73f7cbf70adb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290125096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.290125096
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2359767898
Short name T438
Test name
Test status
Simulation time 126851543 ps
CPU time 8.16 seconds
Started Jul 27 05:55:11 PM PDT 24
Finished Jul 27 05:55:19 PM PDT 24
Peak memory 218868 kb
Host smart-bcda3aa4-6857-44c6-9384-aa56e8febc51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359767898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2359767898
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2890942042
Short name T37
Test name
Test status
Simulation time 2499464524 ps
CPU time 5.04 seconds
Started Jul 27 05:35:28 PM PDT 24
Finished Jul 27 05:35:33 PM PDT 24
Peak memory 211824 kb
Host smart-ec4c948e-5a3c-462c-b72b-2904e9c5d642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890942042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2890942042
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4280484179
Short name T45
Test name
Test status
Simulation time 4182280454 ps
CPU time 123.85 seconds
Started Jul 27 05:35:29 PM PDT 24
Finished Jul 27 05:37:33 PM PDT 24
Peak memory 213116 kb
Host smart-5292601c-0c80-4370-9f6a-86ea0713dc20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280484179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.4280484179
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.57289943
Short name T301
Test name
Test status
Simulation time 290469319 ps
CPU time 6.44 seconds
Started Jul 27 05:35:28 PM PDT 24
Finished Jul 27 05:35:35 PM PDT 24
Peak memory 211852 kb
Host smart-c572771a-9f47-45f6-8cba-b1ac8c048a9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57289943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.57289943
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3049227388
Short name T261
Test name
Test status
Simulation time 481933564 ps
CPU time 12.15 seconds
Started Jul 27 05:35:28 PM PDT 24
Finished Jul 27 05:35:40 PM PDT 24
Peak memory 214280 kb
Host smart-94f55130-d195-4bda-b8b7-4c7c277d7f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049227388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3049227388
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3148974899
Short name T182
Test name
Test status
Simulation time 2128007769 ps
CPU time 26.97 seconds
Started Jul 27 05:35:26 PM PDT 24
Finished Jul 27 05:35:53 PM PDT 24
Peak memory 217396 kb
Host smart-2007154b-f35b-48b2-abcb-88a681b015e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148974899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3148974899
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3500992508
Short name T276
Test name
Test status
Simulation time 20183433696 ps
CPU time 207.39 seconds
Started Jul 27 05:35:27 PM PDT 24
Finished Jul 27 05:38:55 PM PDT 24
Peak memory 235288 kb
Host smart-d03bbbcc-6e54-44ba-b88e-c000067c5870
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500992508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3500992508
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3219241468
Short name T213
Test name
Test status
Simulation time 4089730844 ps
CPU time 16.87 seconds
Started Jul 27 05:35:29 PM PDT 24
Finished Jul 27 05:35:46 PM PDT 24
Peak memory 212540 kb
Host smart-2584ff62-d859-4b6c-ac31-d74262e8920c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219241468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3219241468
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3974636062
Short name T195
Test name
Test status
Simulation time 230856757 ps
CPU time 6.47 seconds
Started Jul 27 05:35:26 PM PDT 24
Finished Jul 27 05:35:32 PM PDT 24
Peak memory 211880 kb
Host smart-c0606019-5c7a-4286-93ce-9e1580649a10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3974636062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3974636062
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2545467484
Short name T20
Test name
Test status
Simulation time 1437635893 ps
CPU time 100.64 seconds
Started Jul 27 05:35:27 PM PDT 24
Finished Jul 27 05:37:07 PM PDT 24
Peak memory 237248 kb
Host smart-9dd89788-652c-4675-a1f5-58c3614be63d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545467484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2545467484
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1295837473
Short name T353
Test name
Test status
Simulation time 696205101 ps
CPU time 10.37 seconds
Started Jul 27 05:35:29 PM PDT 24
Finished Jul 27 05:35:39 PM PDT 24
Peak memory 214176 kb
Host smart-cae60094-23be-4a0f-aa30-9063ecdb0451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295837473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1295837473
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.762422943
Short name T318
Test name
Test status
Simulation time 164894974 ps
CPU time 7.46 seconds
Started Jul 27 05:35:27 PM PDT 24
Finished Jul 27 05:35:34 PM PDT 24
Peak memory 211800 kb
Host smart-ece34ab9-1975-4e60-8328-ffb387a17e97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762422943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.762422943
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1984073648
Short name T314
Test name
Test status
Simulation time 89813491 ps
CPU time 4.3 seconds
Started Jul 27 05:35:58 PM PDT 24
Finished Jul 27 05:36:02 PM PDT 24
Peak memory 211780 kb
Host smart-5ed23d53-0115-43bd-96d0-f3dace2d192a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984073648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1984073648
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3033407599
Short name T205
Test name
Test status
Simulation time 6486936233 ps
CPU time 116.37 seconds
Started Jul 27 05:35:54 PM PDT 24
Finished Jul 27 05:37:50 PM PDT 24
Peak memory 238228 kb
Host smart-43bd1029-0f76-4eb4-a928-25488fb20a57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033407599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3033407599
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1013862747
Short name T227
Test name
Test status
Simulation time 177681898 ps
CPU time 9.57 seconds
Started Jul 27 05:35:56 PM PDT 24
Finished Jul 27 05:36:06 PM PDT 24
Peak memory 212596 kb
Host smart-67bb192c-2254-4914-81eb-57c840f0e516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013862747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1013862747
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3136584902
Short name T146
Test name
Test status
Simulation time 278927717 ps
CPU time 6.22 seconds
Started Jul 27 05:35:56 PM PDT 24
Finished Jul 27 05:36:03 PM PDT 24
Peak memory 211824 kb
Host smart-d0ee3477-0ceb-41ca-8af4-4b123a03c72f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3136584902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3136584902
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.4188696174
Short name T119
Test name
Test status
Simulation time 1098507909 ps
CPU time 12.23 seconds
Started Jul 27 05:35:53 PM PDT 24
Finished Jul 27 05:36:05 PM PDT 24
Peak memory 214624 kb
Host smart-7038e10b-d798-4d71-a85e-099404b2cff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188696174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.4188696174
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2237161428
Short name T283
Test name
Test status
Simulation time 1521008673 ps
CPU time 30.22 seconds
Started Jul 27 05:35:56 PM PDT 24
Finished Jul 27 05:36:26 PM PDT 24
Peak memory 216744 kb
Host smart-c4e1ca28-6883-4f62-b205-3fb1bb4a8a95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237161428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2237161428
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1943210919
Short name T289
Test name
Test status
Simulation time 147854892812 ps
CPU time 1457.53 seconds
Started Jul 27 05:35:53 PM PDT 24
Finished Jul 27 06:00:11 PM PDT 24
Peak memory 236348 kb
Host smart-11073152-97df-4f72-8bfb-af898b963190
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943210919 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1943210919
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.835263114
Short name T280
Test name
Test status
Simulation time 180487419 ps
CPU time 5.31 seconds
Started Jul 27 05:35:58 PM PDT 24
Finished Jul 27 05:36:04 PM PDT 24
Peak memory 211732 kb
Host smart-05f0de46-c2b4-496b-afed-171e0c228b5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835263114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.835263114
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1313762632
Short name T185
Test name
Test status
Simulation time 24199981881 ps
CPU time 178.8 seconds
Started Jul 27 05:35:54 PM PDT 24
Finished Jul 27 05:38:53 PM PDT 24
Peak memory 235116 kb
Host smart-5de7ae5a-a4e4-4e9c-a54a-cff1e042bc96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313762632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1313762632
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2360880714
Short name T97
Test name
Test status
Simulation time 3553136950 ps
CPU time 11.42 seconds
Started Jul 27 05:35:57 PM PDT 24
Finished Jul 27 05:36:09 PM PDT 24
Peak memory 211956 kb
Host smart-3cfbedf2-20c7-4cd0-a042-c60091e2a96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360880714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2360880714
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3668090425
Short name T343
Test name
Test status
Simulation time 197452138 ps
CPU time 5.87 seconds
Started Jul 27 05:35:56 PM PDT 24
Finished Jul 27 05:36:02 PM PDT 24
Peak memory 211792 kb
Host smart-5817ef7e-ae1e-4261-bc3b-5b37360c42ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3668090425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3668090425
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3483285743
Short name T172
Test name
Test status
Simulation time 1292907264 ps
CPU time 11.85 seconds
Started Jul 27 05:35:54 PM PDT 24
Finished Jul 27 05:36:06 PM PDT 24
Peak memory 214268 kb
Host smart-6020f061-1001-4b3a-be8b-feae0cd2c60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483285743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3483285743
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3017926688
Short name T162
Test name
Test status
Simulation time 430526368 ps
CPU time 6.83 seconds
Started Jul 27 05:35:53 PM PDT 24
Finished Jul 27 05:36:00 PM PDT 24
Peak memory 211736 kb
Host smart-dc899c90-c27a-41c7-906a-ce44d012b5b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017926688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3017926688
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.167703370
Short name T347
Test name
Test status
Simulation time 495519264 ps
CPU time 5.1 seconds
Started Jul 27 05:35:54 PM PDT 24
Finished Jul 27 05:35:59 PM PDT 24
Peak memory 211736 kb
Host smart-40c1dd50-cb16-412d-8f8e-13a9bf74c6b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167703370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.167703370
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.460549080
Short name T229
Test name
Test status
Simulation time 4524023475 ps
CPU time 78.1 seconds
Started Jul 27 05:35:52 PM PDT 24
Finished Jul 27 05:37:10 PM PDT 24
Peak memory 234636 kb
Host smart-c5ef22a2-a42f-41d2-ada5-c0576201b3d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460549080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.460549080
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2083555344
Short name T302
Test name
Test status
Simulation time 1998922791 ps
CPU time 8.65 seconds
Started Jul 27 05:35:51 PM PDT 24
Finished Jul 27 05:36:00 PM PDT 24
Peak memory 211880 kb
Host smart-9959c041-4c0d-4478-8315-31b9ae5c9821
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2083555344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2083555344
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.517920574
Short name T202
Test name
Test status
Simulation time 276801241 ps
CPU time 12.22 seconds
Started Jul 27 05:35:53 PM PDT 24
Finished Jul 27 05:36:05 PM PDT 24
Peak memory 214256 kb
Host smart-b2355836-5e1b-4ca1-af7c-9bda155c8ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517920574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.517920574
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3449449112
Short name T313
Test name
Test status
Simulation time 126949784 ps
CPU time 5.12 seconds
Started Jul 27 05:35:52 PM PDT 24
Finished Jul 27 05:35:57 PM PDT 24
Peak memory 211764 kb
Host smart-8d027208-a45c-4071-932b-24a0a6ba6a7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449449112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3449449112
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3983699552
Short name T260
Test name
Test status
Simulation time 4763956272 ps
CPU time 75.61 seconds
Started Jul 27 05:35:58 PM PDT 24
Finished Jul 27 05:37:14 PM PDT 24
Peak memory 213112 kb
Host smart-5cc1b892-bde2-42c0-9adb-94ddfbf37139
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983699552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3983699552
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2214644816
Short name T154
Test name
Test status
Simulation time 4138141393 ps
CPU time 15.54 seconds
Started Jul 27 05:35:56 PM PDT 24
Finished Jul 27 05:36:12 PM PDT 24
Peak memory 212748 kb
Host smart-987309e0-abbc-47d5-8735-24be8bb68011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214644816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2214644816
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1312157944
Short name T296
Test name
Test status
Simulation time 394403195 ps
CPU time 5.74 seconds
Started Jul 27 05:35:52 PM PDT 24
Finished Jul 27 05:35:57 PM PDT 24
Peak memory 211888 kb
Host smart-dbdb9744-214b-4fc4-9d9c-0b1f6900f514
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1312157944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1312157944
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.972961777
Short name T226
Test name
Test status
Simulation time 719113948 ps
CPU time 10.39 seconds
Started Jul 27 05:35:58 PM PDT 24
Finished Jul 27 05:36:09 PM PDT 24
Peak memory 214504 kb
Host smart-6c154f24-1d9d-42c5-b253-67997dd50493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972961777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.972961777
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3557190587
Short name T243
Test name
Test status
Simulation time 2130955327 ps
CPU time 25.62 seconds
Started Jul 27 05:35:56 PM PDT 24
Finished Jul 27 05:36:22 PM PDT 24
Peak memory 217008 kb
Host smart-56ac3545-2711-42b9-ac0a-369cd79b04e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557190587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3557190587
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3484209096
Short name T341
Test name
Test status
Simulation time 176639999 ps
CPU time 4.18 seconds
Started Jul 27 05:35:53 PM PDT 24
Finished Jul 27 05:35:58 PM PDT 24
Peak memory 211720 kb
Host smart-1f48d2da-db4a-415d-aab8-816b05f6a7e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484209096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3484209096
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1472065133
Short name T41
Test name
Test status
Simulation time 9749523402 ps
CPU time 102.37 seconds
Started Jul 27 05:35:53 PM PDT 24
Finished Jul 27 05:37:36 PM PDT 24
Peak memory 235332 kb
Host smart-de708d88-4e4b-420e-bbdf-4f3ee96fdb38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472065133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1472065133
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3661505290
Short name T378
Test name
Test status
Simulation time 975005877 ps
CPU time 9.21 seconds
Started Jul 27 05:35:55 PM PDT 24
Finished Jul 27 05:36:04 PM PDT 24
Peak memory 212620 kb
Host smart-64868953-2b38-49e2-8d2b-ba670720945a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661505290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3661505290
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3268857115
Short name T332
Test name
Test status
Simulation time 138151987 ps
CPU time 6.75 seconds
Started Jul 27 05:35:57 PM PDT 24
Finished Jul 27 05:36:04 PM PDT 24
Peak memory 211872 kb
Host smart-579eca01-f108-45ca-a61e-3e9dc3f169e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3268857115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3268857115
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1950689457
Short name T274
Test name
Test status
Simulation time 264231104 ps
CPU time 11.98 seconds
Started Jul 27 05:35:55 PM PDT 24
Finished Jul 27 05:36:07 PM PDT 24
Peak memory 214424 kb
Host smart-16109a25-4d76-42fd-bce8-c46f17cf83b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950689457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1950689457
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2186335276
Short name T306
Test name
Test status
Simulation time 1370491459 ps
CPU time 13.55 seconds
Started Jul 27 05:35:54 PM PDT 24
Finished Jul 27 05:36:07 PM PDT 24
Peak memory 213880 kb
Host smart-068e241a-d635-4233-a66d-99e5b3ca097f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186335276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2186335276
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.345546096
Short name T269
Test name
Test status
Simulation time 1127441786 ps
CPU time 5.21 seconds
Started Jul 27 05:35:56 PM PDT 24
Finished Jul 27 05:36:02 PM PDT 24
Peak memory 211764 kb
Host smart-4730971f-4443-4aba-ac43-6bf92173e24a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345546096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.345546096
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2893772469
Short name T250
Test name
Test status
Simulation time 13299781193 ps
CPU time 71.66 seconds
Started Jul 27 05:35:54 PM PDT 24
Finished Jul 27 05:37:06 PM PDT 24
Peak memory 234116 kb
Host smart-2de2f111-040a-43f7-ae85-b9ca188c15f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893772469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2893772469
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2032088337
Short name T28
Test name
Test status
Simulation time 3938784401 ps
CPU time 15.78 seconds
Started Jul 27 05:35:54 PM PDT 24
Finished Jul 27 05:36:10 PM PDT 24
Peak memory 212868 kb
Host smart-44447107-1f0d-47c5-a17a-0e617af7a9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032088337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2032088337
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1642990988
Short name T300
Test name
Test status
Simulation time 201131341 ps
CPU time 6.49 seconds
Started Jul 27 05:35:55 PM PDT 24
Finished Jul 27 05:36:01 PM PDT 24
Peak memory 211872 kb
Host smart-6fc96183-bb50-4758-bf47-480756a911d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1642990988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1642990988
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.397060329
Short name T32
Test name
Test status
Simulation time 1055604314 ps
CPU time 11.89 seconds
Started Jul 27 05:35:54 PM PDT 24
Finished Jul 27 05:36:06 PM PDT 24
Peak memory 214724 kb
Host smart-99f6388b-962b-4401-8863-118ebcdbe9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397060329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.397060329
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2479299708
Short name T218
Test name
Test status
Simulation time 520599525 ps
CPU time 14.21 seconds
Started Jul 27 05:35:53 PM PDT 24
Finished Jul 27 05:36:07 PM PDT 24
Peak memory 214472 kb
Host smart-8e691fd8-befa-4bc9-aceb-b4fc7df70e41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479299708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2479299708
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1757347502
Short name T240
Test name
Test status
Simulation time 112742164 ps
CPU time 4.35 seconds
Started Jul 27 05:35:57 PM PDT 24
Finished Jul 27 05:36:01 PM PDT 24
Peak memory 211764 kb
Host smart-aa0cbd2a-7b6e-4bc6-b161-c4c9fbfd70cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757347502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1757347502
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2077702009
Short name T327
Test name
Test status
Simulation time 669580424 ps
CPU time 46.11 seconds
Started Jul 27 05:35:56 PM PDT 24
Finished Jul 27 05:36:43 PM PDT 24
Peak memory 237928 kb
Host smart-9cd71f1d-cc65-4b12-9577-560d8270b7ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077702009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2077702009
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1295305543
Short name T140
Test name
Test status
Simulation time 170352687 ps
CPU time 9.37 seconds
Started Jul 27 05:35:54 PM PDT 24
Finished Jul 27 05:36:04 PM PDT 24
Peak memory 212668 kb
Host smart-09ccede6-0435-41bd-8e3a-333dbf243450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295305543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1295305543
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.779289190
Short name T204
Test name
Test status
Simulation time 134493789 ps
CPU time 6.49 seconds
Started Jul 27 05:35:53 PM PDT 24
Finished Jul 27 05:36:00 PM PDT 24
Peak memory 211876 kb
Host smart-bfbfe6a0-d70b-4d3b-8c5c-f43e1fe4b304
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=779289190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.779289190
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2424393490
Short name T222
Test name
Test status
Simulation time 988493951 ps
CPU time 11.93 seconds
Started Jul 27 05:35:56 PM PDT 24
Finished Jul 27 05:36:08 PM PDT 24
Peak memory 214584 kb
Host smart-ae6c6faa-d760-4c05-bf56-ee30f3b5b456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424393490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2424393490
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.501407724
Short name T338
Test name
Test status
Simulation time 222832863 ps
CPU time 7.75 seconds
Started Jul 27 05:35:56 PM PDT 24
Finished Jul 27 05:36:04 PM PDT 24
Peak memory 211812 kb
Host smart-23c09a98-6cde-4037-a17d-e0034e5366d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501407724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.501407724
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1016660853
Short name T26
Test name
Test status
Simulation time 126506722 ps
CPU time 5.2 seconds
Started Jul 27 05:35:56 PM PDT 24
Finished Jul 27 05:36:01 PM PDT 24
Peak memory 212000 kb
Host smart-ec64ce5a-9eff-4256-80ca-cbcfaf6df8e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016660853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1016660853
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2856044983
Short name T221
Test name
Test status
Simulation time 7683686959 ps
CPU time 122.33 seconds
Started Jul 27 05:35:52 PM PDT 24
Finished Jul 27 05:37:55 PM PDT 24
Peak memory 238216 kb
Host smart-2b63848b-ff86-4865-b763-2fa2d374d4d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856044983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2856044983
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2982995500
Short name T299
Test name
Test status
Simulation time 511076443 ps
CPU time 11.41 seconds
Started Jul 27 05:35:54 PM PDT 24
Finished Jul 27 05:36:05 PM PDT 24
Peak memory 212640 kb
Host smart-958c18f6-86c8-43cd-b8cf-ec992dc3d861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982995500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2982995500
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.4228589809
Short name T284
Test name
Test status
Simulation time 1040947841 ps
CPU time 8.51 seconds
Started Jul 27 05:35:52 PM PDT 24
Finished Jul 27 05:36:01 PM PDT 24
Peak memory 211916 kb
Host smart-308e66cb-5c55-4594-b8b9-22ac592c8436
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4228589809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.4228589809
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2206616483
Short name T194
Test name
Test status
Simulation time 187732634 ps
CPU time 10.44 seconds
Started Jul 27 05:35:53 PM PDT 24
Finished Jul 27 05:36:04 PM PDT 24
Peak memory 214304 kb
Host smart-d38d4e68-e62b-485d-af82-f7a12e90aac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206616483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2206616483
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3514619255
Short name T83
Test name
Test status
Simulation time 2832324532 ps
CPU time 27.86 seconds
Started Jul 27 05:35:58 PM PDT 24
Finished Jul 27 05:36:26 PM PDT 24
Peak memory 215240 kb
Host smart-624cdabd-774e-4ff0-aae7-52de0308550d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514619255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3514619255
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1036470948
Short name T339
Test name
Test status
Simulation time 465140009 ps
CPU time 5.14 seconds
Started Jul 27 05:35:57 PM PDT 24
Finished Jul 27 05:36:02 PM PDT 24
Peak memory 211768 kb
Host smart-3e5993a5-0093-458b-a158-aa92ac48ae67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036470948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1036470948
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1568342349
Short name T361
Test name
Test status
Simulation time 1928520351 ps
CPU time 89.21 seconds
Started Jul 27 05:35:56 PM PDT 24
Finished Jul 27 05:37:26 PM PDT 24
Peak memory 240908 kb
Host smart-e4e05014-b8b1-4a07-bba1-b41ef132b604
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568342349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1568342349
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3705375202
Short name T245
Test name
Test status
Simulation time 510103967 ps
CPU time 11.41 seconds
Started Jul 27 05:35:56 PM PDT 24
Finished Jul 27 05:36:08 PM PDT 24
Peak memory 212636 kb
Host smart-2e3e9911-4344-44a3-b070-4ce8c727461f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705375202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3705375202
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3520410272
Short name T158
Test name
Test status
Simulation time 96500493 ps
CPU time 5.62 seconds
Started Jul 27 05:35:59 PM PDT 24
Finished Jul 27 05:36:04 PM PDT 24
Peak memory 211820 kb
Host smart-8894025d-ccea-412c-a48d-83806a4f7c31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3520410272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3520410272
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1673322845
Short name T369
Test name
Test status
Simulation time 193959186 ps
CPU time 10.74 seconds
Started Jul 27 05:35:59 PM PDT 24
Finished Jul 27 05:36:10 PM PDT 24
Peak memory 214232 kb
Host smart-52ce1216-e540-43a3-be28-39bb8cbf26aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673322845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1673322845
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1350084209
Short name T199
Test name
Test status
Simulation time 555750280 ps
CPU time 25.38 seconds
Started Jul 27 05:35:55 PM PDT 24
Finished Jul 27 05:36:21 PM PDT 24
Peak memory 216352 kb
Host smart-94042a83-560a-4f02-9968-7a56a2b627f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350084209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1350084209
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2360735034
Short name T273
Test name
Test status
Simulation time 106795478550 ps
CPU time 1857.27 seconds
Started Jul 27 05:35:55 PM PDT 24
Finished Jul 27 06:06:53 PM PDT 24
Peak memory 238668 kb
Host smart-1fbaae89-b745-4127-8dcd-a7fa5ed59631
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360735034 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2360735034
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.329622076
Short name T359
Test name
Test status
Simulation time 253997716 ps
CPU time 5.22 seconds
Started Jul 27 05:35:55 PM PDT 24
Finished Jul 27 05:36:00 PM PDT 24
Peak memory 211692 kb
Host smart-dc540b21-cba9-4d95-80a6-2aa922b7f8ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329622076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.329622076
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1675264815
Short name T380
Test name
Test status
Simulation time 2600213952 ps
CPU time 114.34 seconds
Started Jul 27 05:35:53 PM PDT 24
Finished Jul 27 05:37:48 PM PDT 24
Peak memory 238244 kb
Host smart-88999876-cbec-44da-b008-664fd6f1dee6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675264815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1675264815
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1329347831
Short name T143
Test name
Test status
Simulation time 997912829 ps
CPU time 11.19 seconds
Started Jul 27 05:35:52 PM PDT 24
Finished Jul 27 05:36:04 PM PDT 24
Peak memory 211836 kb
Host smart-96c93ebd-1fa9-4699-950f-57826e561320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329347831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1329347831
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3465999536
Short name T231
Test name
Test status
Simulation time 102166423 ps
CPU time 5.98 seconds
Started Jul 27 05:35:59 PM PDT 24
Finished Jul 27 05:36:05 PM PDT 24
Peak memory 211912 kb
Host smart-d325cc70-64ea-4805-9958-9863ac12e7c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3465999536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3465999536
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.256232304
Short name T79
Test name
Test status
Simulation time 263267768 ps
CPU time 12.17 seconds
Started Jul 27 05:35:56 PM PDT 24
Finished Jul 27 05:36:08 PM PDT 24
Peak memory 214372 kb
Host smart-ad6ae24a-bede-4c37-9e8c-9b67e24ae508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256232304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.256232304
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.389259561
Short name T81
Test name
Test status
Simulation time 188818436 ps
CPU time 10.34 seconds
Started Jul 27 05:35:56 PM PDT 24
Finished Jul 27 05:36:07 PM PDT 24
Peak memory 214768 kb
Host smart-4e4d0ab1-fd48-48e3-8a1c-904df858929b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389259561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.389259561
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3803742996
Short name T55
Test name
Test status
Simulation time 24009968816 ps
CPU time 925.85 seconds
Started Jul 27 05:35:58 PM PDT 24
Finished Jul 27 05:51:24 PM PDT 24
Peak memory 228108 kb
Host smart-962eb718-eb1c-4339-b2cf-06a0fab43005
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803742996 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.3803742996
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.92062297
Short name T368
Test name
Test status
Simulation time 171569908 ps
CPU time 4.18 seconds
Started Jul 27 05:35:28 PM PDT 24
Finished Jul 27 05:35:32 PM PDT 24
Peak memory 211736 kb
Host smart-3d6c6fd8-0a0c-4c98-b681-764cdddb22ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92062297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.92062297
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2199217203
Short name T4
Test name
Test status
Simulation time 3340005534 ps
CPU time 173.53 seconds
Started Jul 27 05:35:26 PM PDT 24
Finished Jul 27 05:38:19 PM PDT 24
Peak memory 238248 kb
Host smart-1639ae26-d2ab-4eb5-8c0c-e0c8cb3cfb3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199217203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2199217203
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1739299575
Short name T365
Test name
Test status
Simulation time 258824382 ps
CPU time 11.41 seconds
Started Jul 27 05:35:31 PM PDT 24
Finished Jul 27 05:35:43 PM PDT 24
Peak memory 212336 kb
Host smart-f04be1e6-3178-41e2-be43-12911032f6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739299575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1739299575
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1557629050
Short name T293
Test name
Test status
Simulation time 187929699 ps
CPU time 5.45 seconds
Started Jul 27 05:35:28 PM PDT 24
Finished Jul 27 05:35:34 PM PDT 24
Peak memory 211792 kb
Host smart-a75ed738-cc9c-4535-85cf-316a6aa3cf8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1557629050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1557629050
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.518742061
Short name T22
Test name
Test status
Simulation time 395810450 ps
CPU time 51.91 seconds
Started Jul 27 05:35:29 PM PDT 24
Finished Jul 27 05:36:21 PM PDT 24
Peak memory 236844 kb
Host smart-a60c53b2-4201-4783-abab-3836dc48448e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518742061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.518742061
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.152786566
Short name T201
Test name
Test status
Simulation time 721253514 ps
CPU time 9.93 seconds
Started Jul 27 05:35:28 PM PDT 24
Finished Jul 27 05:35:38 PM PDT 24
Peak memory 213400 kb
Host smart-da3b8ccf-3349-43a9-b919-4d4453d19f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152786566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.152786566
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1156941526
Short name T186
Test name
Test status
Simulation time 2241324195 ps
CPU time 26.82 seconds
Started Jul 27 05:35:27 PM PDT 24
Finished Jul 27 05:35:54 PM PDT 24
Peak memory 214860 kb
Host smart-9037053f-e5eb-4af7-ac68-0687408094ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156941526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1156941526
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2346854566
Short name T27
Test name
Test status
Simulation time 594619007 ps
CPU time 4.29 seconds
Started Jul 27 05:35:59 PM PDT 24
Finished Jul 27 05:36:03 PM PDT 24
Peak memory 211764 kb
Host smart-6e30906b-d275-4242-98e6-12f3311900fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346854566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2346854566
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.624122357
Short name T363
Test name
Test status
Simulation time 2770795575 ps
CPU time 132.49 seconds
Started Jul 27 05:35:54 PM PDT 24
Finished Jul 27 05:38:07 PM PDT 24
Peak memory 213180 kb
Host smart-fa14076f-4b6a-411a-9d7a-5acbc5146349
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624122357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.624122357
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2594837251
Short name T290
Test name
Test status
Simulation time 182872652 ps
CPU time 9.46 seconds
Started Jul 27 05:35:57 PM PDT 24
Finished Jul 27 05:36:07 PM PDT 24
Peak memory 212552 kb
Host smart-e6d122e8-4dc3-4a19-92cd-52485ddc571e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594837251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2594837251
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.117111411
Short name T228
Test name
Test status
Simulation time 835612077 ps
CPU time 5.39 seconds
Started Jul 27 05:35:54 PM PDT 24
Finished Jul 27 05:36:00 PM PDT 24
Peak memory 211864 kb
Host smart-8497a78c-f48c-4eac-b3cd-ce5ee2150b7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=117111411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.117111411
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.861659914
Short name T292
Test name
Test status
Simulation time 535295854 ps
CPU time 12.22 seconds
Started Jul 27 05:35:53 PM PDT 24
Finished Jul 27 05:36:06 PM PDT 24
Peak memory 213300 kb
Host smart-9036ab2f-6439-403e-a62d-0c0a1f97145d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861659914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.861659914
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2012841958
Short name T377
Test name
Test status
Simulation time 3668255536 ps
CPU time 49.59 seconds
Started Jul 27 05:35:56 PM PDT 24
Finished Jul 27 05:36:46 PM PDT 24
Peak memory 217384 kb
Host smart-8507bf64-44a8-4d5c-be13-217ef8c3c489
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012841958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2012841958
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2923914287
Short name T54
Test name
Test status
Simulation time 95801030054 ps
CPU time 2054.16 seconds
Started Jul 27 05:35:57 PM PDT 24
Finished Jul 27 06:10:11 PM PDT 24
Peak memory 252712 kb
Host smart-c421aa32-b4d1-4cbb-b62c-5359e8d9156b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923914287 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2923914287
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1720038620
Short name T63
Test name
Test status
Simulation time 2693063810 ps
CPU time 7.69 seconds
Started Jul 27 05:36:00 PM PDT 24
Finished Jul 27 05:36:08 PM PDT 24
Peak memory 211840 kb
Host smart-5fb86ba0-9964-4372-a256-8039b9dddce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720038620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1720038620
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.992964611
Short name T265
Test name
Test status
Simulation time 6968520935 ps
CPU time 110.92 seconds
Started Jul 27 05:35:55 PM PDT 24
Finished Jul 27 05:37:46 PM PDT 24
Peak memory 225868 kb
Host smart-2c5d6dbb-83e6-45fa-b225-23b70c7a9ff4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992964611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.992964611
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.662795785
Short name T152
Test name
Test status
Simulation time 252717916 ps
CPU time 11.16 seconds
Started Jul 27 05:35:56 PM PDT 24
Finished Jul 27 05:36:07 PM PDT 24
Peak memory 212764 kb
Host smart-2e9e7139-e426-44ce-902a-624af62f605e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662795785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.662795785
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1400120288
Short name T116
Test name
Test status
Simulation time 142128976 ps
CPU time 6.48 seconds
Started Jul 27 05:35:57 PM PDT 24
Finished Jul 27 05:36:04 PM PDT 24
Peak memory 211868 kb
Host smart-88e0ca8f-7b11-41f5-8ecf-8e7fb4ac7f67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1400120288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1400120288
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3839510810
Short name T316
Test name
Test status
Simulation time 326775183 ps
CPU time 10.52 seconds
Started Jul 27 05:35:55 PM PDT 24
Finished Jul 27 05:36:06 PM PDT 24
Peak memory 214512 kb
Host smart-06e01a7f-535a-4372-8f50-b65f95496e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839510810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3839510810
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.4140800317
Short name T207
Test name
Test status
Simulation time 761044009 ps
CPU time 13.48 seconds
Started Jul 27 05:35:57 PM PDT 24
Finished Jul 27 05:36:10 PM PDT 24
Peak memory 214300 kb
Host smart-fbb94b0c-7cba-467e-8731-2cb3bdd39696
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140800317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.4140800317
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3030438047
Short name T180
Test name
Test status
Simulation time 518908956 ps
CPU time 5.3 seconds
Started Jul 27 05:36:05 PM PDT 24
Finished Jul 27 05:36:10 PM PDT 24
Peak memory 211764 kb
Host smart-97bc46b3-ce2d-4cbd-aa56-730b2901cbf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030438047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3030438047
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1797967478
Short name T285
Test name
Test status
Simulation time 4980757652 ps
CPU time 125.99 seconds
Started Jul 27 05:36:06 PM PDT 24
Finished Jul 27 05:38:12 PM PDT 24
Peak memory 238084 kb
Host smart-8461a949-4d0e-4b9b-8f43-34e08989dcca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797967478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1797967478
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4171625443
Short name T47
Test name
Test status
Simulation time 1388258583 ps
CPU time 9.23 seconds
Started Jul 27 05:36:07 PM PDT 24
Finished Jul 27 05:36:17 PM PDT 24
Peak memory 212544 kb
Host smart-e3b6f8aa-c85b-4057-8ba4-9e54d0af9b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171625443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4171625443
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3285896813
Short name T157
Test name
Test status
Simulation time 553280563 ps
CPU time 6.37 seconds
Started Jul 27 05:36:07 PM PDT 24
Finished Jul 27 05:36:14 PM PDT 24
Peak memory 211868 kb
Host smart-2e48a356-4cbd-424d-ac96-9791b567f4ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3285896813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3285896813
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2711959472
Short name T38
Test name
Test status
Simulation time 524007216 ps
CPU time 12.02 seconds
Started Jul 27 05:36:09 PM PDT 24
Finished Jul 27 05:36:21 PM PDT 24
Peak memory 212664 kb
Host smart-ca5c0b14-798b-4ee7-ad59-190c34fb7dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711959472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2711959472
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2932236013
Short name T257
Test name
Test status
Simulation time 480605817 ps
CPU time 25.74 seconds
Started Jul 27 05:36:07 PM PDT 24
Finished Jul 27 05:36:33 PM PDT 24
Peak memory 215900 kb
Host smart-c19f66e7-4279-473f-8ef8-84400db41d88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932236013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2932236013
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2529798540
Short name T242
Test name
Test status
Simulation time 232565091209 ps
CPU time 7256.19 seconds
Started Jul 27 05:36:07 PM PDT 24
Finished Jul 27 07:37:05 PM PDT 24
Peak memory 236332 kb
Host smart-75e45537-d06a-4d1b-92ba-0aabfd73b3fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529798540 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2529798540
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2924495687
Short name T352
Test name
Test status
Simulation time 460411752 ps
CPU time 5.24 seconds
Started Jul 27 05:36:09 PM PDT 24
Finished Jul 27 05:36:15 PM PDT 24
Peak memory 211776 kb
Host smart-f550ef77-dcae-4f13-adc7-00a4cacaf8f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924495687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2924495687
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3368564602
Short name T344
Test name
Test status
Simulation time 1154040595 ps
CPU time 59.44 seconds
Started Jul 27 05:36:14 PM PDT 24
Finished Jul 27 05:37:14 PM PDT 24
Peak memory 236732 kb
Host smart-71cf2b87-4840-40e8-9085-58e909f6db08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368564602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3368564602
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3615280153
Short name T354
Test name
Test status
Simulation time 258420395 ps
CPU time 11.04 seconds
Started Jul 27 05:36:03 PM PDT 24
Finished Jul 27 05:36:14 PM PDT 24
Peak memory 212684 kb
Host smart-16278b9d-9df8-41d6-9813-a8c6703b39cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615280153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3615280153
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2690650241
Short name T174
Test name
Test status
Simulation time 176011603 ps
CPU time 6.5 seconds
Started Jul 27 05:36:05 PM PDT 24
Finished Jul 27 05:36:12 PM PDT 24
Peak memory 211836 kb
Host smart-e3574c5d-0c1a-41fc-9988-d6cdf4ff3ea2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2690650241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2690650241
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3791444165
Short name T304
Test name
Test status
Simulation time 364312525 ps
CPU time 10.05 seconds
Started Jul 27 05:36:03 PM PDT 24
Finished Jul 27 05:36:13 PM PDT 24
Peak memory 214016 kb
Host smart-c713679d-da61-46e0-ba9a-fc584f1c2399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791444165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3791444165
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1970004804
Short name T101
Test name
Test status
Simulation time 1579420700 ps
CPU time 21.02 seconds
Started Jul 27 05:36:05 PM PDT 24
Finished Jul 27 05:36:26 PM PDT 24
Peak memory 217132 kb
Host smart-8d99aedb-e2c2-4996-9460-dfc8590676bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970004804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1970004804
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3264991981
Short name T24
Test name
Test status
Simulation time 544213367 ps
CPU time 5.24 seconds
Started Jul 27 05:36:04 PM PDT 24
Finished Jul 27 05:36:10 PM PDT 24
Peak memory 211748 kb
Host smart-781e3f44-029c-4b67-9304-e685327d032c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264991981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3264991981
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3175540824
Short name T105
Test name
Test status
Simulation time 4053839607 ps
CPU time 89.57 seconds
Started Jul 27 05:36:11 PM PDT 24
Finished Jul 27 05:37:40 PM PDT 24
Peak memory 234232 kb
Host smart-77bec7e5-dcac-40fd-8861-33cb82fba9a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175540824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3175540824
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1407517813
Short name T334
Test name
Test status
Simulation time 491145902 ps
CPU time 11.47 seconds
Started Jul 27 05:36:07 PM PDT 24
Finished Jul 27 05:36:18 PM PDT 24
Peak memory 212620 kb
Host smart-139267ae-4d59-42f6-8c3d-7710bab8443e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407517813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1407517813
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1915862917
Short name T165
Test name
Test status
Simulation time 103008240 ps
CPU time 5.67 seconds
Started Jul 27 05:36:07 PM PDT 24
Finished Jul 27 05:36:13 PM PDT 24
Peak memory 211864 kb
Host smart-02bcc63c-ff43-47b3-a820-c024a005167a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1915862917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1915862917
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2894525541
Short name T282
Test name
Test status
Simulation time 187441542 ps
CPU time 10.26 seconds
Started Jul 27 05:36:08 PM PDT 24
Finished Jul 27 05:36:19 PM PDT 24
Peak memory 213056 kb
Host smart-720ad52b-4a43-43ea-ae1d-63d77f67d753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894525541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2894525541
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.660214685
Short name T355
Test name
Test status
Simulation time 1352672817 ps
CPU time 32.24 seconds
Started Jul 27 05:36:08 PM PDT 24
Finished Jul 27 05:36:40 PM PDT 24
Peak memory 216840 kb
Host smart-b7256862-4bf6-4adb-93fe-eaa94a44a7de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660214685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.660214685
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.738430582
Short name T53
Test name
Test status
Simulation time 23316036166 ps
CPU time 9531.63 seconds
Started Jul 27 05:36:08 PM PDT 24
Finished Jul 27 08:15:01 PM PDT 24
Peak memory 235416 kb
Host smart-46a4e642-caae-4991-ae52-a444ba26a0d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738430582 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.738430582
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2608620652
Short name T206
Test name
Test status
Simulation time 275398318 ps
CPU time 5.29 seconds
Started Jul 27 05:36:03 PM PDT 24
Finished Jul 27 05:36:09 PM PDT 24
Peak memory 211784 kb
Host smart-17ab9fbc-f1a0-4f3f-807d-68aaabfd7112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608620652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2608620652
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3747317989
Short name T46
Test name
Test status
Simulation time 665647440 ps
CPU time 9.54 seconds
Started Jul 27 05:36:04 PM PDT 24
Finished Jul 27 05:36:14 PM PDT 24
Peak memory 212980 kb
Host smart-22c9b689-9714-4407-9aa1-4391eb28b2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747317989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3747317989
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2851689807
Short name T248
Test name
Test status
Simulation time 100441195 ps
CPU time 5.55 seconds
Started Jul 27 05:36:04 PM PDT 24
Finished Jul 27 05:36:10 PM PDT 24
Peak memory 211912 kb
Host smart-5e5ce84b-4383-4654-b558-74054e1a75e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2851689807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2851689807
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.4063249876
Short name T291
Test name
Test status
Simulation time 386539800 ps
CPU time 10.4 seconds
Started Jul 27 05:36:13 PM PDT 24
Finished Jul 27 05:36:23 PM PDT 24
Peak memory 214412 kb
Host smart-37b28f12-e933-48d5-87dc-3d6d1d3cc6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063249876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.4063249876
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3579413953
Short name T3
Test name
Test status
Simulation time 1474494737 ps
CPU time 18.7 seconds
Started Jul 27 05:36:07 PM PDT 24
Finished Jul 27 05:36:26 PM PDT 24
Peak memory 214248 kb
Host smart-d0a829dd-c6fe-4d42-bf8f-efcb0c038290
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579413953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3579413953
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.95882617
Short name T360
Test name
Test status
Simulation time 26664053154 ps
CPU time 7611.55 seconds
Started Jul 27 05:36:13 PM PDT 24
Finished Jul 27 07:43:06 PM PDT 24
Peak memory 236320 kb
Host smart-463b47e6-826d-4116-bf28-df8f1573f5b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95882617 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.95882617
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.191995367
Short name T330
Test name
Test status
Simulation time 1883156173 ps
CPU time 7.44 seconds
Started Jul 27 05:36:06 PM PDT 24
Finished Jul 27 05:36:13 PM PDT 24
Peak memory 211688 kb
Host smart-21d9a5f7-617e-4be8-8e0b-ff71353c02d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191995367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.191995367
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.645860037
Short name T193
Test name
Test status
Simulation time 2457374355 ps
CPU time 82.08 seconds
Started Jul 27 05:36:07 PM PDT 24
Finished Jul 27 05:37:30 PM PDT 24
Peak memory 238280 kb
Host smart-15a3bab0-5054-4ec2-a901-c0fbd917fa99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645860037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.645860037
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.130679763
Short name T224
Test name
Test status
Simulation time 995990492 ps
CPU time 11.29 seconds
Started Jul 27 05:36:11 PM PDT 24
Finished Jul 27 05:36:22 PM PDT 24
Peak memory 212684 kb
Host smart-3dda0a1c-5bcd-4302-a405-735ce33cc4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130679763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.130679763
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3055825565
Short name T358
Test name
Test status
Simulation time 99985820 ps
CPU time 5.39 seconds
Started Jul 27 05:36:05 PM PDT 24
Finished Jul 27 05:36:10 PM PDT 24
Peak memory 211872 kb
Host smart-849c2cb4-a92b-46b0-a688-dba806848975
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3055825565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3055825565
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3139828180
Short name T367
Test name
Test status
Simulation time 526216771 ps
CPU time 11.57 seconds
Started Jul 27 05:36:11 PM PDT 24
Finished Jul 27 05:36:23 PM PDT 24
Peak memory 214188 kb
Host smart-077326d9-933e-4242-ab57-139dd35de785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139828180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3139828180
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.4088750619
Short name T379
Test name
Test status
Simulation time 504170992 ps
CPU time 26.01 seconds
Started Jul 27 05:36:08 PM PDT 24
Finished Jul 27 05:36:34 PM PDT 24
Peak memory 216164 kb
Host smart-5d8cd771-ab0a-478d-b51a-0203e027e100
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088750619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.4088750619
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3571710657
Short name T52
Test name
Test status
Simulation time 134692984202 ps
CPU time 1038.55 seconds
Started Jul 27 05:36:03 PM PDT 24
Finished Jul 27 05:53:22 PM PDT 24
Peak memory 233524 kb
Host smart-3606f177-bcc4-466a-9520-10f44a587b1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571710657 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3571710657
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.610852497
Short name T264
Test name
Test status
Simulation time 168803303 ps
CPU time 4.29 seconds
Started Jul 27 05:36:05 PM PDT 24
Finished Jul 27 05:36:10 PM PDT 24
Peak memory 211736 kb
Host smart-31d70a5f-ba3e-42b2-86ca-13024ab48542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610852497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.610852497
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3251272526
Short name T35
Test name
Test status
Simulation time 9852980237 ps
CPU time 125.49 seconds
Started Jul 27 05:36:08 PM PDT 24
Finished Jul 27 05:38:14 PM PDT 24
Peak memory 234512 kb
Host smart-b899e712-7572-4dbb-9170-ccf3adfce5a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251272526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3251272526
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3267741556
Short name T104
Test name
Test status
Simulation time 696226570 ps
CPU time 9.55 seconds
Started Jul 27 05:36:08 PM PDT 24
Finished Jul 27 05:36:18 PM PDT 24
Peak memory 212588 kb
Host smart-81e0ce27-866b-442c-8887-921befdaa533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267741556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3267741556
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.438440573
Short name T262
Test name
Test status
Simulation time 271956450 ps
CPU time 6.54 seconds
Started Jul 27 05:36:10 PM PDT 24
Finished Jul 27 05:36:17 PM PDT 24
Peak memory 211880 kb
Host smart-49c54931-69ae-4999-a480-d610b2ca6304
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438440573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.438440573
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3906019832
Short name T362
Test name
Test status
Simulation time 1058413952 ps
CPU time 11.67 seconds
Started Jul 27 05:36:07 PM PDT 24
Finished Jul 27 05:36:19 PM PDT 24
Peak memory 214656 kb
Host smart-22823570-af1d-4a16-8658-e3accab745ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906019832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3906019832
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.511805510
Short name T345
Test name
Test status
Simulation time 4991550182 ps
CPU time 46.01 seconds
Started Jul 27 05:36:01 PM PDT 24
Finished Jul 27 05:36:47 PM PDT 24
Peak memory 217324 kb
Host smart-36e01851-940c-4e04-9df1-4a728abd169b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511805510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.511805510
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.86452463
Short name T294
Test name
Test status
Simulation time 521892690 ps
CPU time 5.02 seconds
Started Jul 27 05:36:05 PM PDT 24
Finished Jul 27 05:36:10 PM PDT 24
Peak memory 211736 kb
Host smart-35d11b7d-4628-4e85-8c62-3139f0041955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86452463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.86452463
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3330420410
Short name T17
Test name
Test status
Simulation time 9942535273 ps
CPU time 81.34 seconds
Started Jul 27 05:36:13 PM PDT 24
Finished Jul 27 05:37:35 PM PDT 24
Peak memory 226020 kb
Host smart-29e872cf-5cc4-40b4-a6f5-ba170f971099
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330420410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3330420410
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.514784363
Short name T317
Test name
Test status
Simulation time 251508887 ps
CPU time 11.32 seconds
Started Jul 27 05:36:08 PM PDT 24
Finished Jul 27 05:36:20 PM PDT 24
Peak memory 212604 kb
Host smart-afc97b35-d457-4bd2-9832-cb526d6fff97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514784363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.514784363
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.842183830
Short name T148
Test name
Test status
Simulation time 95195160 ps
CPU time 5.83 seconds
Started Jul 27 05:36:05 PM PDT 24
Finished Jul 27 05:36:11 PM PDT 24
Peak memory 211820 kb
Host smart-a30a3906-dc1d-453b-a5b0-99e7d720a8dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=842183830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.842183830
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2417104517
Short name T200
Test name
Test status
Simulation time 3600388769 ps
CPU time 10.14 seconds
Started Jul 27 05:36:05 PM PDT 24
Finished Jul 27 05:36:15 PM PDT 24
Peak memory 213940 kb
Host smart-29b46af8-4531-4c9a-bf1e-a050fc560836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417104517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2417104517
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3060313463
Short name T295
Test name
Test status
Simulation time 549182895 ps
CPU time 30.61 seconds
Started Jul 27 05:36:12 PM PDT 24
Finished Jul 27 05:36:43 PM PDT 24
Peak memory 219776 kb
Host smart-562ec1e6-3006-426f-bf76-24cbd7bc0f86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060313463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3060313463
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1402199980
Short name T298
Test name
Test status
Simulation time 418413841 ps
CPU time 4.33 seconds
Started Jul 27 05:36:05 PM PDT 24
Finished Jul 27 05:36:09 PM PDT 24
Peak memory 211780 kb
Host smart-7fc45226-0d5d-48bd-b8fa-453558428631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402199980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1402199980
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3226641178
Short name T246
Test name
Test status
Simulation time 18956878979 ps
CPU time 123.32 seconds
Started Jul 27 05:36:06 PM PDT 24
Finished Jul 27 05:38:09 PM PDT 24
Peak memory 214120 kb
Host smart-976ba239-a299-480e-a966-ac2bd7a76f09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226641178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3226641178
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3668397374
Short name T348
Test name
Test status
Simulation time 642483197 ps
CPU time 9.48 seconds
Started Jul 27 05:36:09 PM PDT 24
Finished Jul 27 05:36:18 PM PDT 24
Peak memory 212944 kb
Host smart-897b5bf1-ac3a-40c5-b2fd-fad4f29c17bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668397374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3668397374
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.905874920
Short name T236
Test name
Test status
Simulation time 1095182410 ps
CPU time 8.99 seconds
Started Jul 27 05:36:08 PM PDT 24
Finished Jul 27 05:36:17 PM PDT 24
Peak memory 211872 kb
Host smart-087019fa-efdb-46f9-adc0-b9f764def5bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=905874920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.905874920
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3034669157
Short name T75
Test name
Test status
Simulation time 1100824755 ps
CPU time 12.27 seconds
Started Jul 27 05:36:07 PM PDT 24
Finished Jul 27 05:36:20 PM PDT 24
Peak memory 213716 kb
Host smart-21af3c25-9c3d-429d-891a-3fccbd9d9585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034669157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3034669157
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1505151166
Short name T249
Test name
Test status
Simulation time 1181712461 ps
CPU time 16.14 seconds
Started Jul 27 05:36:08 PM PDT 24
Finished Jul 27 05:36:24 PM PDT 24
Peak memory 213176 kb
Host smart-30cd52ac-0a45-4ab3-8533-2b65dc4ceeaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505151166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1505151166
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.4091988420
Short name T328
Test name
Test status
Simulation time 85497491 ps
CPU time 4.29 seconds
Started Jul 27 05:35:41 PM PDT 24
Finished Jul 27 05:35:46 PM PDT 24
Peak memory 211712 kb
Host smart-235c710c-4406-4d0b-a37a-29320ce6fce9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091988420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.4091988420
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1597141693
Short name T137
Test name
Test status
Simulation time 4228889474 ps
CPU time 65.05 seconds
Started Jul 27 05:35:40 PM PDT 24
Finished Jul 27 05:36:45 PM PDT 24
Peak memory 238112 kb
Host smart-a0c24fb7-959a-4b85-a3fe-ccc4a2605401
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597141693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1597141693
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1857688499
Short name T176
Test name
Test status
Simulation time 184211589 ps
CPU time 9.28 seconds
Started Jul 27 05:35:40 PM PDT 24
Finished Jul 27 05:35:49 PM PDT 24
Peak memory 212684 kb
Host smart-3ca25d1b-6641-4376-9d54-192c3953cea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857688499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1857688499
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.65530865
Short name T7
Test name
Test status
Simulation time 553838211 ps
CPU time 6.12 seconds
Started Jul 27 05:35:41 PM PDT 24
Finished Jul 27 05:35:47 PM PDT 24
Peak memory 211816 kb
Host smart-188c4896-e2b0-482f-a839-5920977d8ead
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=65530865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.65530865
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.869006520
Short name T30
Test name
Test status
Simulation time 614241089 ps
CPU time 101.05 seconds
Started Jul 27 05:35:41 PM PDT 24
Finished Jul 27 05:37:22 PM PDT 24
Peak memory 238716 kb
Host smart-1d552e07-883a-44d1-8f75-2b79d3f5da31
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869006520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.869006520
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.791673499
Short name T99
Test name
Test status
Simulation time 265093154 ps
CPU time 11.86 seconds
Started Jul 27 05:35:41 PM PDT 24
Finished Jul 27 05:35:53 PM PDT 24
Peak memory 212876 kb
Host smart-0de04ced-2836-4fce-a8b6-771f89ea69dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791673499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.791673499
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3910767741
Short name T166
Test name
Test status
Simulation time 1057331417 ps
CPU time 24.6 seconds
Started Jul 27 05:35:42 PM PDT 24
Finished Jul 27 05:36:07 PM PDT 24
Peak memory 216816 kb
Host smart-4683110e-d2bd-4c20-8e09-d951f48527a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910767741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3910767741
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3394209855
Short name T6
Test name
Test status
Simulation time 51982430174 ps
CPU time 1130.72 seconds
Started Jul 27 05:35:41 PM PDT 24
Finished Jul 27 05:54:32 PM PDT 24
Peak memory 236304 kb
Host smart-ab9655aa-6473-4c12-b474-5d73562a9725
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394209855 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.3394209855
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1677165983
Short name T211
Test name
Test status
Simulation time 130903357 ps
CPU time 5.05 seconds
Started Jul 27 05:36:11 PM PDT 24
Finished Jul 27 05:36:16 PM PDT 24
Peak memory 211780 kb
Host smart-9a6caf4d-d6f8-4680-96ee-b272f5bdc873
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677165983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1677165983
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.514131895
Short name T209
Test name
Test status
Simulation time 5342810131 ps
CPU time 64.72 seconds
Started Jul 27 05:36:07 PM PDT 24
Finished Jul 27 05:37:12 PM PDT 24
Peak memory 237920 kb
Host smart-16f5e833-efa2-4832-a704-04d2f4dad145
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514131895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.514131895
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1901197569
Short name T312
Test name
Test status
Simulation time 260062664 ps
CPU time 11.22 seconds
Started Jul 27 05:36:14 PM PDT 24
Finished Jul 27 05:36:25 PM PDT 24
Peak memory 212744 kb
Host smart-bb73c2f1-9df8-4678-887e-15ad8ce3402a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901197569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1901197569
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1845654819
Short name T376
Test name
Test status
Simulation time 162251945 ps
CPU time 6.51 seconds
Started Jul 27 05:36:08 PM PDT 24
Finished Jul 27 05:36:14 PM PDT 24
Peak memory 211872 kb
Host smart-0fb5adfd-a9bc-4d25-a864-6612607e88f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1845654819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1845654819
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2885394
Short name T12
Test name
Test status
Simulation time 831673891 ps
CPU time 10.22 seconds
Started Jul 27 05:36:14 PM PDT 24
Finished Jul 27 05:36:24 PM PDT 24
Peak memory 214452 kb
Host smart-8606c8ce-d34d-443d-8acb-bd9be0d2a107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2885394
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1607971947
Short name T208
Test name
Test status
Simulation time 270493881 ps
CPU time 13.43 seconds
Started Jul 27 05:36:06 PM PDT 24
Finished Jul 27 05:36:20 PM PDT 24
Peak memory 215212 kb
Host smart-701f1b5a-10aa-4ce3-bc57-9cf228d4558c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607971947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1607971947
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2220605278
Short name T120
Test name
Test status
Simulation time 72545230741 ps
CPU time 10705.7 seconds
Started Jul 27 05:36:06 PM PDT 24
Finished Jul 27 08:34:33 PM PDT 24
Peak memory 233932 kb
Host smart-85c75ba1-c4c4-4896-967a-783cb687d6c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220605278 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2220605278
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.4183845
Short name T220
Test name
Test status
Simulation time 461726975 ps
CPU time 4.21 seconds
Started Jul 27 05:36:04 PM PDT 24
Finished Jul 27 05:36:08 PM PDT 24
Peak memory 211808 kb
Host smart-337e21e1-223b-4fc1-94ab-f06d0218539a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4183845
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2572146700
Short name T281
Test name
Test status
Simulation time 577058757 ps
CPU time 9.75 seconds
Started Jul 27 05:36:05 PM PDT 24
Finished Jul 27 05:36:15 PM PDT 24
Peak memory 212500 kb
Host smart-620cb4ef-8a1f-4cca-b2f1-3e06da9f6046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572146700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2572146700
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2503695106
Short name T163
Test name
Test status
Simulation time 381932980 ps
CPU time 5.51 seconds
Started Jul 27 05:36:09 PM PDT 24
Finished Jul 27 05:36:14 PM PDT 24
Peak memory 211880 kb
Host smart-61835168-6e25-44e5-bffc-e228ef4f4d54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2503695106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2503695106
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.631470687
Short name T10
Test name
Test status
Simulation time 516203437 ps
CPU time 11.64 seconds
Started Jul 27 05:36:08 PM PDT 24
Finished Jul 27 05:36:20 PM PDT 24
Peak memory 214512 kb
Host smart-047c56d1-2e67-4292-9ae1-bdad514f620f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631470687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.631470687
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2788949218
Short name T76
Test name
Test status
Simulation time 3289964304 ps
CPU time 24.22 seconds
Started Jul 27 05:36:12 PM PDT 24
Finished Jul 27 05:36:37 PM PDT 24
Peak memory 217512 kb
Host smart-08bbaf7f-89ec-455c-a318-384b1bd9b4f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788949218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2788949218
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1471630587
Short name T160
Test name
Test status
Simulation time 458856915 ps
CPU time 5.08 seconds
Started Jul 27 05:36:22 PM PDT 24
Finished Jul 27 05:36:27 PM PDT 24
Peak memory 211768 kb
Host smart-81206225-2137-4999-8204-97a4b596ed96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471630587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1471630587
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1795626469
Short name T241
Test name
Test status
Simulation time 1062606899 ps
CPU time 55.95 seconds
Started Jul 27 05:36:08 PM PDT 24
Finished Jul 27 05:37:04 PM PDT 24
Peak memory 227364 kb
Host smart-b56760c0-0525-4b47-af9a-4be0a2f880aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795626469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1795626469
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4229282447
Short name T139
Test name
Test status
Simulation time 336513933 ps
CPU time 9.35 seconds
Started Jul 27 05:36:14 PM PDT 24
Finished Jul 27 05:36:23 PM PDT 24
Peak memory 212696 kb
Host smart-169bc823-34dd-494a-bc96-93b86dad0214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229282447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.4229282447
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1728559255
Short name T297
Test name
Test status
Simulation time 368578554 ps
CPU time 5.56 seconds
Started Jul 27 05:36:06 PM PDT 24
Finished Jul 27 05:36:12 PM PDT 24
Peak memory 211884 kb
Host smart-af5809c9-14a9-41d3-b581-b7d8643cf2f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1728559255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1728559255
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3973834387
Short name T275
Test name
Test status
Simulation time 269163574 ps
CPU time 11.67 seconds
Started Jul 27 05:36:08 PM PDT 24
Finished Jul 27 05:36:20 PM PDT 24
Peak memory 213760 kb
Host smart-ee9967f4-b053-4324-9949-905b3880afb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973834387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3973834387
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.899084294
Short name T203
Test name
Test status
Simulation time 283094755 ps
CPU time 18.25 seconds
Started Jul 27 05:36:06 PM PDT 24
Finished Jul 27 05:36:25 PM PDT 24
Peak memory 213532 kb
Host smart-4ea23534-60cc-4afb-bbaf-5d8d4b0108a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899084294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.899084294
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3917829522
Short name T340
Test name
Test status
Simulation time 240652367114 ps
CPU time 2259.33 seconds
Started Jul 27 05:36:08 PM PDT 24
Finished Jul 27 06:13:47 PM PDT 24
Peak memory 238348 kb
Host smart-8ac207ef-33c7-488c-b6e4-9ede352c42dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917829522 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.3917829522
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.73241064
Short name T364
Test name
Test status
Simulation time 404875109 ps
CPU time 4.83 seconds
Started Jul 27 05:36:12 PM PDT 24
Finished Jul 27 05:36:17 PM PDT 24
Peak memory 211656 kb
Host smart-dfb44ac5-d067-4ae7-8def-52caf7a2f7a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73241064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.73241064
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2003627032
Short name T371
Test name
Test status
Simulation time 1383256929 ps
CPU time 90.61 seconds
Started Jul 27 05:36:20 PM PDT 24
Finished Jul 27 05:37:51 PM PDT 24
Peak memory 238196 kb
Host smart-cc40088f-6e84-4199-bbb9-c6345a49cd92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003627032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2003627032
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3639048528
Short name T48
Test name
Test status
Simulation time 2078429884 ps
CPU time 9.37 seconds
Started Jul 27 05:36:21 PM PDT 24
Finished Jul 27 05:36:31 PM PDT 24
Peak memory 212716 kb
Host smart-54d585e9-a86c-4225-836d-2b19b2312d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639048528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3639048528
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2931102397
Short name T187
Test name
Test status
Simulation time 3549786655 ps
CPU time 8.55 seconds
Started Jul 27 05:36:22 PM PDT 24
Finished Jul 27 05:36:31 PM PDT 24
Peak memory 211960 kb
Host smart-686cc490-c77a-44a8-ab74-2e6aa4608a1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2931102397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2931102397
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2550458045
Short name T342
Test name
Test status
Simulation time 1104025443 ps
CPU time 11.98 seconds
Started Jul 27 05:36:22 PM PDT 24
Finished Jul 27 05:36:34 PM PDT 24
Peak memory 214540 kb
Host smart-3e3f8300-7354-4177-8f91-62b94d3aad47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550458045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2550458045
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3244906916
Short name T150
Test name
Test status
Simulation time 984266467 ps
CPU time 15.37 seconds
Started Jul 27 05:36:17 PM PDT 24
Finished Jul 27 05:36:33 PM PDT 24
Peak memory 214324 kb
Host smart-fc56b85c-6c7d-4a5f-a8ca-8bd8cd24cead
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244906916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3244906916
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.4238705657
Short name T336
Test name
Test status
Simulation time 278084425930 ps
CPU time 2856.89 seconds
Started Jul 27 05:36:23 PM PDT 24
Finished Jul 27 06:24:00 PM PDT 24
Peak memory 248380 kb
Host smart-1c42209d-6ced-4e57-b9a1-ebf474883c74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238705657 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.4238705657
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3808524104
Short name T159
Test name
Test status
Simulation time 260781343 ps
CPU time 5.12 seconds
Started Jul 27 05:36:19 PM PDT 24
Finished Jul 27 05:36:24 PM PDT 24
Peak memory 212000 kb
Host smart-fa783bae-caa4-4aca-b15b-f80fb3778875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808524104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3808524104
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3051337869
Short name T19
Test name
Test status
Simulation time 2357468170 ps
CPU time 68.22 seconds
Started Jul 27 05:36:16 PM PDT 24
Finished Jul 27 05:37:24 PM PDT 24
Peak memory 238272 kb
Host smart-45f2d205-1572-4da7-afae-546fe3df7cb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051337869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3051337869
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.998643187
Short name T153
Test name
Test status
Simulation time 171053907 ps
CPU time 9.53 seconds
Started Jul 27 05:36:14 PM PDT 24
Finished Jul 27 05:36:23 PM PDT 24
Peak memory 212644 kb
Host smart-a5df53a0-2f9d-46fb-ac91-98bbae092c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998643187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.998643187
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2313802150
Short name T315
Test name
Test status
Simulation time 551825237 ps
CPU time 6.38 seconds
Started Jul 27 05:36:18 PM PDT 24
Finished Jul 27 05:36:25 PM PDT 24
Peak memory 211912 kb
Host smart-52d0a9bf-ca09-49b9-a1f2-99dc275ba590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313802150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2313802150
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.31628441
Short name T189
Test name
Test status
Simulation time 1733366373 ps
CPU time 10.05 seconds
Started Jul 27 05:36:14 PM PDT 24
Finished Jul 27 05:36:24 PM PDT 24
Peak memory 214216 kb
Host smart-47d2fe5e-46ac-4756-99fc-7fee7394b29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31628441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.31628441
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3666577332
Short name T219
Test name
Test status
Simulation time 1091010353 ps
CPU time 17.83 seconds
Started Jul 27 05:36:21 PM PDT 24
Finished Jul 27 05:36:39 PM PDT 24
Peak memory 214224 kb
Host smart-519c491f-ccef-4654-929e-8cb4b26616bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666577332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3666577332
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2782396765
Short name T323
Test name
Test status
Simulation time 249815748 ps
CPU time 5.11 seconds
Started Jul 27 05:36:20 PM PDT 24
Finished Jul 27 05:36:25 PM PDT 24
Peak memory 211696 kb
Host smart-0a5a52ed-70b5-4a56-b45f-1ae888bed45e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782396765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2782396765
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2144636975
Short name T144
Test name
Test status
Simulation time 274361328 ps
CPU time 11.11 seconds
Started Jul 27 05:36:22 PM PDT 24
Finished Jul 27 05:36:34 PM PDT 24
Peak memory 212648 kb
Host smart-887ce9b7-1167-4aed-b133-7c0747f789a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144636975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2144636975
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2716053362
Short name T169
Test name
Test status
Simulation time 405455716 ps
CPU time 5.58 seconds
Started Jul 27 05:36:17 PM PDT 24
Finished Jul 27 05:36:23 PM PDT 24
Peak memory 212016 kb
Host smart-1626e133-43b2-4120-9967-c1de328b3555
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716053362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2716053362
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.4133222962
Short name T311
Test name
Test status
Simulation time 1042442927 ps
CPU time 12.21 seconds
Started Jul 27 05:36:21 PM PDT 24
Finished Jul 27 05:36:33 PM PDT 24
Peak memory 212664 kb
Host smart-eba148cc-dc0e-4a48-bb0b-80290fa064a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133222962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.4133222962
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.173861444
Short name T329
Test name
Test status
Simulation time 589931747 ps
CPU time 26.1 seconds
Started Jul 27 05:36:16 PM PDT 24
Finished Jul 27 05:36:42 PM PDT 24
Peak memory 217108 kb
Host smart-aeedc9a4-5eb6-44b6-95df-eef7304ec34c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173861444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.173861444
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3307787502
Short name T100
Test name
Test status
Simulation time 519889081 ps
CPU time 5.05 seconds
Started Jul 27 05:36:21 PM PDT 24
Finished Jul 27 05:36:26 PM PDT 24
Peak memory 211776 kb
Host smart-31f41470-eaa3-4da8-b350-e8d572dc2351
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307787502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3307787502
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.4052532849
Short name T44
Test name
Test status
Simulation time 3792035515 ps
CPU time 73.93 seconds
Started Jul 27 05:36:21 PM PDT 24
Finished Jul 27 05:37:35 PM PDT 24
Peak memory 236920 kb
Host smart-6b404d32-5ce6-4d8e-8142-e27a67ff53f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052532849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.4052532849
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1473143453
Short name T161
Test name
Test status
Simulation time 625859419 ps
CPU time 11.23 seconds
Started Jul 27 05:36:20 PM PDT 24
Finished Jul 27 05:36:31 PM PDT 24
Peak memory 212668 kb
Host smart-58293afb-f674-431e-9a75-9b5e4e58961a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473143453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1473143453
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3731177274
Short name T259
Test name
Test status
Simulation time 2635480117 ps
CPU time 6.22 seconds
Started Jul 27 05:36:20 PM PDT 24
Finished Jul 27 05:36:27 PM PDT 24
Peak memory 211820 kb
Host smart-8ea6ff3c-6c5b-44f8-ad63-28f7abea6265
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3731177274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3731177274
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.131480118
Short name T372
Test name
Test status
Simulation time 1099412330 ps
CPU time 9.64 seconds
Started Jul 27 05:36:21 PM PDT 24
Finished Jul 27 05:36:31 PM PDT 24
Peak memory 213776 kb
Host smart-febff2d4-0a3e-473d-9875-b74a513ad927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131480118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.131480118
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.520444474
Short name T212
Test name
Test status
Simulation time 469089805 ps
CPU time 19.47 seconds
Started Jul 27 05:36:15 PM PDT 24
Finished Jul 27 05:36:35 PM PDT 24
Peak memory 215924 kb
Host smart-735a38b6-5555-476b-a673-7829c366ce13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520444474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.520444474
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1539458550
Short name T324
Test name
Test status
Simulation time 69773804814 ps
CPU time 1212.5 seconds
Started Jul 27 05:36:15 PM PDT 24
Finished Jul 27 05:56:28 PM PDT 24
Peak memory 230228 kb
Host smart-0b226b09-2f58-40ac-be0f-10fa8c417c5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539458550 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1539458550
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.731649894
Short name T268
Test name
Test status
Simulation time 494805521 ps
CPU time 4.91 seconds
Started Jul 27 05:36:23 PM PDT 24
Finished Jul 27 05:36:28 PM PDT 24
Peak memory 211768 kb
Host smart-7aee332b-7b7b-49e0-aba5-be2d89829056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731649894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.731649894
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.95979547
Short name T217
Test name
Test status
Simulation time 10324965576 ps
CPU time 121.3 seconds
Started Jul 27 05:36:21 PM PDT 24
Finished Jul 27 05:38:22 PM PDT 24
Peak memory 238252 kb
Host smart-91f79005-b387-4831-b743-0a4b5149f634
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95979547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_co
rrupt_sig_fatal_chk.95979547
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3505145288
Short name T238
Test name
Test status
Simulation time 3548694419 ps
CPU time 11.31 seconds
Started Jul 27 05:36:13 PM PDT 24
Finished Jul 27 05:36:24 PM PDT 24
Peak memory 212684 kb
Host smart-37c17767-322a-4fa8-94e5-f87bcfcf14fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505145288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3505145288
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2942553887
Short name T266
Test name
Test status
Simulation time 144101334 ps
CPU time 6.71 seconds
Started Jul 27 05:36:21 PM PDT 24
Finished Jul 27 05:36:28 PM PDT 24
Peak memory 211760 kb
Host smart-69fb8b70-1824-4205-93e1-f05ba6b1ca5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2942553887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2942553887
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.578414300
Short name T351
Test name
Test status
Simulation time 535763098 ps
CPU time 11.41 seconds
Started Jul 27 05:36:17 PM PDT 24
Finished Jul 27 05:36:29 PM PDT 24
Peak memory 212424 kb
Host smart-98999cbf-372c-4211-8c62-d37392cf06c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578414300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.578414300
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1302951468
Short name T252
Test name
Test status
Simulation time 1789682701 ps
CPU time 21.82 seconds
Started Jul 27 05:36:19 PM PDT 24
Finished Jul 27 05:36:40 PM PDT 24
Peak memory 215096 kb
Host smart-f074982d-ee70-40b6-a33d-cf2bc8469974
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302951468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1302951468
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.380261631
Short name T346
Test name
Test status
Simulation time 346815033 ps
CPU time 4.18 seconds
Started Jul 27 05:36:21 PM PDT 24
Finished Jul 27 05:36:26 PM PDT 24
Peak memory 211660 kb
Host smart-55f6e36c-5380-4c03-a809-0301148fde65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380261631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.380261631
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4019209517
Short name T216
Test name
Test status
Simulation time 9292508592 ps
CPU time 125.71 seconds
Started Jul 27 05:36:17 PM PDT 24
Finished Jul 27 05:38:23 PM PDT 24
Peak memory 238292 kb
Host smart-25c387b1-0ebc-4117-8d30-8db04e949fe2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019209517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4019209517
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1260506569
Short name T375
Test name
Test status
Simulation time 340426984 ps
CPU time 9.45 seconds
Started Jul 27 05:36:18 PM PDT 24
Finished Jul 27 05:36:27 PM PDT 24
Peak memory 212960 kb
Host smart-3f7d50bb-9695-4b5c-aa0d-9701c508ea16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260506569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1260506569
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2648515235
Short name T147
Test name
Test status
Simulation time 512344997 ps
CPU time 6.46 seconds
Started Jul 27 05:36:21 PM PDT 24
Finished Jul 27 05:36:27 PM PDT 24
Peak memory 211860 kb
Host smart-63cd992b-639b-4390-b8cf-a12752c4b537
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2648515235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2648515235
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3044027735
Short name T164
Test name
Test status
Simulation time 716500079 ps
CPU time 10.04 seconds
Started Jul 27 05:36:14 PM PDT 24
Finished Jul 27 05:36:25 PM PDT 24
Peak memory 214232 kb
Host smart-b1cb15f0-3d76-4d63-9ff4-aa1f95e31ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044027735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3044027735
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1942303506
Short name T272
Test name
Test status
Simulation time 1140768101 ps
CPU time 34.37 seconds
Started Jul 27 05:36:15 PM PDT 24
Finished Jul 27 05:36:49 PM PDT 24
Peak memory 215764 kb
Host smart-35eb5b38-967c-47f1-bde7-261a918031b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942303506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1942303506
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.4147624627
Short name T196
Test name
Test status
Simulation time 36578561010 ps
CPU time 1386.21 seconds
Started Jul 27 05:36:18 PM PDT 24
Finished Jul 27 05:59:24 PM PDT 24
Peak memory 230956 kb
Host smart-b7b77eb8-d0fc-4ef3-94d3-faf7f5c6731b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147624627 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.4147624627
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.732018550
Short name T168
Test name
Test status
Simulation time 918547008 ps
CPU time 4.31 seconds
Started Jul 27 05:36:28 PM PDT 24
Finished Jul 27 05:36:33 PM PDT 24
Peak memory 211760 kb
Host smart-f65b3624-35dd-4ad9-b718-ed1a68293d87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732018550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.732018550
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2230886225
Short name T235
Test name
Test status
Simulation time 1501948989 ps
CPU time 85.82 seconds
Started Jul 27 05:36:30 PM PDT 24
Finished Jul 27 05:37:56 PM PDT 24
Peak memory 239652 kb
Host smart-ad187ce6-7c22-4284-bded-cbeab8e999d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230886225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2230886225
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.604430117
Short name T253
Test name
Test status
Simulation time 169922747 ps
CPU time 9.44 seconds
Started Jul 27 05:36:24 PM PDT 24
Finished Jul 27 05:36:34 PM PDT 24
Peak memory 212784 kb
Host smart-8b1caf90-d5df-4076-ab67-aec2b513fc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604430117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.604430117
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1392714187
Short name T356
Test name
Test status
Simulation time 514482640 ps
CPU time 8.52 seconds
Started Jul 27 05:36:21 PM PDT 24
Finished Jul 27 05:36:29 PM PDT 24
Peak memory 211760 kb
Host smart-f52558aa-7613-449e-a640-ebbded98e5ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1392714187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1392714187
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2185511640
Short name T177
Test name
Test status
Simulation time 297248822 ps
CPU time 12.07 seconds
Started Jul 27 05:36:15 PM PDT 24
Finished Jul 27 05:36:27 PM PDT 24
Peak memory 213352 kb
Host smart-5aec70ba-5850-42e8-93b2-266d8e519a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185511640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2185511640
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.4141342374
Short name T366
Test name
Test status
Simulation time 269888182 ps
CPU time 10.89 seconds
Started Jul 27 05:36:22 PM PDT 24
Finished Jul 27 05:36:33 PM PDT 24
Peak memory 215844 kb
Host smart-72a2d1db-2539-4721-9021-a9efce64f994
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141342374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.4141342374
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1437996531
Short name T258
Test name
Test status
Simulation time 509555849 ps
CPU time 7.55 seconds
Started Jul 27 05:35:43 PM PDT 24
Finished Jul 27 05:35:51 PM PDT 24
Peak memory 211728 kb
Host smart-c09a64fc-067c-41a8-afd2-4fb52e2a32ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437996531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1437996531
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3300038885
Short name T23
Test name
Test status
Simulation time 1283994161 ps
CPU time 61.9 seconds
Started Jul 27 05:35:44 PM PDT 24
Finished Jul 27 05:36:46 PM PDT 24
Peak memory 211956 kb
Host smart-f49d6958-e26b-4eee-930c-c6b80ed13272
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300038885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3300038885
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2030336703
Short name T39
Test name
Test status
Simulation time 510522200 ps
CPU time 11.55 seconds
Started Jul 27 05:35:42 PM PDT 24
Finished Jul 27 05:35:54 PM PDT 24
Peak memory 212688 kb
Host smart-b103d263-0426-4d74-a3e4-25323726d8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030336703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2030336703
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2521006167
Short name T117
Test name
Test status
Simulation time 1146192098 ps
CPU time 5.35 seconds
Started Jul 27 05:35:39 PM PDT 24
Finished Jul 27 05:35:44 PM PDT 24
Peak memory 211868 kb
Host smart-afe737c7-600d-4da9-b902-5acd59111f0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2521006167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2521006167
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.273471456
Short name T31
Test name
Test status
Simulation time 179454187 ps
CPU time 53.57 seconds
Started Jul 27 05:35:41 PM PDT 24
Finished Jul 27 05:36:35 PM PDT 24
Peak memory 237220 kb
Host smart-40e91a06-887f-4127-85d3-f82a82a32d9e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273471456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.273471456
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3995946124
Short name T77
Test name
Test status
Simulation time 1064140008 ps
CPU time 12.12 seconds
Started Jul 27 05:35:43 PM PDT 24
Finished Jul 27 05:35:55 PM PDT 24
Peak memory 214148 kb
Host smart-1827f336-7c63-4271-8503-40302237ca54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995946124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3995946124
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.4159903541
Short name T118
Test name
Test status
Simulation time 2648659552 ps
CPU time 15.64 seconds
Started Jul 27 05:35:41 PM PDT 24
Finished Jul 27 05:35:57 PM PDT 24
Peak memory 215504 kb
Host smart-ee4ee28d-8554-481d-b39e-e2583b4a24a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159903541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.4159903541
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.613213768
Short name T188
Test name
Test status
Simulation time 194341186 ps
CPU time 5.09 seconds
Started Jul 27 05:36:23 PM PDT 24
Finished Jul 27 05:36:28 PM PDT 24
Peak memory 211776 kb
Host smart-641f9821-7ae4-4168-bf1a-7dfdcfc91a6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613213768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.613213768
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3321602328
Short name T138
Test name
Test status
Simulation time 5253858581 ps
CPU time 89.38 seconds
Started Jul 27 05:36:25 PM PDT 24
Finished Jul 27 05:37:54 PM PDT 24
Peak memory 213112 kb
Host smart-ff3a4776-a564-4d89-87a3-2b6a036aba93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321602328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3321602328
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2809537710
Short name T270
Test name
Test status
Simulation time 696811465 ps
CPU time 9.43 seconds
Started Jul 27 05:36:25 PM PDT 24
Finished Jul 27 05:36:34 PM PDT 24
Peak memory 211900 kb
Host smart-22dbaceb-52cd-4be7-8462-244228902097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809537710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2809537710
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3790760662
Short name T310
Test name
Test status
Simulation time 558973802 ps
CPU time 6.44 seconds
Started Jul 27 05:36:23 PM PDT 24
Finished Jul 27 05:36:29 PM PDT 24
Peak memory 211964 kb
Host smart-81363472-d2b8-415f-9c6f-3cecf11b2d74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3790760662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3790760662
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3536892165
Short name T78
Test name
Test status
Simulation time 281630766 ps
CPU time 12.3 seconds
Started Jul 27 05:36:26 PM PDT 24
Finished Jul 27 05:36:38 PM PDT 24
Peak memory 213332 kb
Host smart-4cf2164b-25cb-48a8-9f08-61b9a74df6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536892165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3536892165
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3992921166
Short name T122
Test name
Test status
Simulation time 119690055774 ps
CPU time 1332.53 seconds
Started Jul 27 05:36:24 PM PDT 24
Finished Jul 27 05:58:37 PM PDT 24
Peak memory 237604 kb
Host smart-cc88311f-9ce7-4e66-84ce-81b7606485ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992921166 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.3992921166
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.4249939452
Short name T319
Test name
Test status
Simulation time 87100024 ps
CPU time 4.32 seconds
Started Jul 27 05:36:30 PM PDT 24
Finished Jul 27 05:36:34 PM PDT 24
Peak memory 211760 kb
Host smart-4d85fe02-a6b3-40ab-8a21-228640c9d000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249939452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.4249939452
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1106587114
Short name T287
Test name
Test status
Simulation time 7347382545 ps
CPU time 135.31 seconds
Started Jul 27 05:36:24 PM PDT 24
Finished Jul 27 05:38:40 PM PDT 24
Peak memory 213016 kb
Host smart-81186244-c3de-41a5-9a71-342ef136bdfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106587114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1106587114
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.874871904
Short name T34
Test name
Test status
Simulation time 228230014 ps
CPU time 9.5 seconds
Started Jul 27 05:36:24 PM PDT 24
Finished Jul 27 05:36:33 PM PDT 24
Peak memory 212612 kb
Host smart-fde70459-9bd4-4eff-9a65-2b7e9bfeda98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874871904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.874871904
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.685016641
Short name T232
Test name
Test status
Simulation time 139082146 ps
CPU time 6.7 seconds
Started Jul 27 05:36:24 PM PDT 24
Finished Jul 27 05:36:31 PM PDT 24
Peak memory 211888 kb
Host smart-79f28e8b-1fef-4180-8cfc-4f654fe9393d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=685016641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.685016641
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.934365494
Short name T247
Test name
Test status
Simulation time 1078848305 ps
CPU time 11.99 seconds
Started Jul 27 05:36:22 PM PDT 24
Finished Jul 27 05:36:34 PM PDT 24
Peak memory 213324 kb
Host smart-c8b875e5-336f-431c-95de-254796f95c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934365494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.934365494
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.811247963
Short name T321
Test name
Test status
Simulation time 378435116 ps
CPU time 9.84 seconds
Started Jul 27 05:36:24 PM PDT 24
Finished Jul 27 05:36:34 PM PDT 24
Peak memory 211724 kb
Host smart-c8e98872-2ba4-4de0-a676-660be35a42e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811247963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.811247963
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2882769906
Short name T255
Test name
Test status
Simulation time 178583764 ps
CPU time 4.24 seconds
Started Jul 27 05:36:34 PM PDT 24
Finished Jul 27 05:36:38 PM PDT 24
Peak memory 211764 kb
Host smart-573386f7-a626-4db7-a779-1b9ab24fb702
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882769906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2882769906
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2060438339
Short name T142
Test name
Test status
Simulation time 1669580689 ps
CPU time 9.61 seconds
Started Jul 27 05:36:34 PM PDT 24
Finished Jul 27 05:36:43 PM PDT 24
Peak memory 212672 kb
Host smart-6be0c95b-784f-4a20-a459-2f9b0448121e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060438339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2060438339
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.847938393
Short name T170
Test name
Test status
Simulation time 98102920 ps
CPU time 5.95 seconds
Started Jul 27 05:36:32 PM PDT 24
Finished Jul 27 05:36:39 PM PDT 24
Peak memory 211868 kb
Host smart-0ec27665-9027-4e3a-82b6-c98569f65474
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=847938393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.847938393
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2234407318
Short name T326
Test name
Test status
Simulation time 564142159 ps
CPU time 12.08 seconds
Started Jul 27 05:36:32 PM PDT 24
Finished Jul 27 05:36:44 PM PDT 24
Peak memory 214292 kb
Host smart-4a305b3b-1b31-4773-bb55-a3e61115eab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234407318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2234407318
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1073197730
Short name T15
Test name
Test status
Simulation time 610638534 ps
CPU time 12.24 seconds
Started Jul 27 05:36:33 PM PDT 24
Finished Jul 27 05:36:45 PM PDT 24
Peak memory 211756 kb
Host smart-58b53d1c-c060-4e10-a5e9-53e09e7debca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073197730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1073197730
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2541129379
Short name T25
Test name
Test status
Simulation time 419308219 ps
CPU time 4.28 seconds
Started Jul 27 05:36:33 PM PDT 24
Finished Jul 27 05:36:37 PM PDT 24
Peak memory 211772 kb
Host smart-3779fe73-a8e7-45a9-b408-ea49097ac530
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541129379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2541129379
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1802355442
Short name T305
Test name
Test status
Simulation time 3895400710 ps
CPU time 116.83 seconds
Started Jul 27 05:36:30 PM PDT 24
Finished Jul 27 05:38:27 PM PDT 24
Peak memory 214104 kb
Host smart-4cfb861b-b779-4080-b3d4-c6c06b5a4cde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802355442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1802355442
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.927734974
Short name T350
Test name
Test status
Simulation time 281144679 ps
CPU time 9.51 seconds
Started Jul 27 05:36:31 PM PDT 24
Finished Jul 27 05:36:41 PM PDT 24
Peak memory 213104 kb
Host smart-218059f9-5cd8-4460-a389-20e4784d1f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927734974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.927734974
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3101700050
Short name T36
Test name
Test status
Simulation time 389906242 ps
CPU time 5.6 seconds
Started Jul 27 05:36:30 PM PDT 24
Finished Jul 27 05:36:36 PM PDT 24
Peak memory 211896 kb
Host smart-6a190170-9377-4cdb-adc8-055ef798013a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3101700050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3101700050
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1880547021
Short name T233
Test name
Test status
Simulation time 549927192 ps
CPU time 12.42 seconds
Started Jul 27 05:36:31 PM PDT 24
Finished Jul 27 05:36:44 PM PDT 24
Peak memory 213932 kb
Host smart-472c918e-9d25-40e1-b5da-eb0d5701d08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880547021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1880547021
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.905758100
Short name T215
Test name
Test status
Simulation time 280534022 ps
CPU time 17.63 seconds
Started Jul 27 05:36:32 PM PDT 24
Finished Jul 27 05:36:50 PM PDT 24
Peak memory 212468 kb
Host smart-92efcdfd-458d-4676-98ca-3098161757c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905758100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.905758100
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2792278385
Short name T179
Test name
Test status
Simulation time 142914765 ps
CPU time 5.16 seconds
Started Jul 27 05:36:35 PM PDT 24
Finished Jul 27 05:36:40 PM PDT 24
Peak memory 211760 kb
Host smart-65693c55-4f03-4ed5-a8a4-70ada423bd2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792278385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2792278385
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3871791210
Short name T40
Test name
Test status
Simulation time 5047363467 ps
CPU time 153.55 seconds
Started Jul 27 05:36:28 PM PDT 24
Finished Jul 27 05:39:02 PM PDT 24
Peak memory 237172 kb
Host smart-3b3fa1db-8373-483d-99d3-2ce77bc08dbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871791210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3871791210
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2586071148
Short name T29
Test name
Test status
Simulation time 1028962981 ps
CPU time 15.82 seconds
Started Jul 27 05:36:33 PM PDT 24
Finished Jul 27 05:36:49 PM PDT 24
Peak memory 212624 kb
Host smart-59d3d442-d896-4e1e-afd8-4f6de9fb3266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586071148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2586071148
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2188979808
Short name T145
Test name
Test status
Simulation time 96162008 ps
CPU time 5.64 seconds
Started Jul 27 05:36:31 PM PDT 24
Finished Jul 27 05:36:37 PM PDT 24
Peak memory 211856 kb
Host smart-c3ca609c-6114-4708-9385-c95f9984592b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2188979808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2188979808
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.311418499
Short name T80
Test name
Test status
Simulation time 270592187 ps
CPU time 12.05 seconds
Started Jul 27 05:36:34 PM PDT 24
Finished Jul 27 05:36:46 PM PDT 24
Peak memory 214380 kb
Host smart-a7dae0b3-2cce-4d9f-b42f-72d72476d8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311418499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.311418499
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3260402392
Short name T167
Test name
Test status
Simulation time 383506505 ps
CPU time 23.43 seconds
Started Jul 27 05:36:34 PM PDT 24
Finished Jul 27 05:36:57 PM PDT 24
Peak memory 215448 kb
Host smart-11b17439-0ae9-471f-b115-0812952dfae1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260402392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3260402392
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.547440342
Short name T13
Test name
Test status
Simulation time 10445977783 ps
CPU time 452.33 seconds
Started Jul 27 05:36:32 PM PDT 24
Finished Jul 27 05:44:05 PM PDT 24
Peak memory 228076 kb
Host smart-c72c14e7-ff76-4a3e-a013-60ef9f0b7940
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547440342 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.547440342
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1825080651
Short name T288
Test name
Test status
Simulation time 253867227 ps
CPU time 5.2 seconds
Started Jul 27 05:36:43 PM PDT 24
Finished Jul 27 05:36:48 PM PDT 24
Peak memory 211688 kb
Host smart-b2bd099b-e2e3-46c6-9915-83c59f0496d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825080651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1825080651
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3406500095
Short name T190
Test name
Test status
Simulation time 39247234293 ps
CPU time 143.73 seconds
Started Jul 27 05:36:32 PM PDT 24
Finished Jul 27 05:38:56 PM PDT 24
Peak memory 235244 kb
Host smart-5a34f5c4-11af-44c4-b728-3f1e208999b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406500095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3406500095
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2159898589
Short name T271
Test name
Test status
Simulation time 672344103 ps
CPU time 9.57 seconds
Started Jul 27 05:36:34 PM PDT 24
Finished Jul 27 05:36:43 PM PDT 24
Peak memory 212988 kb
Host smart-5d8c8008-d9a6-4161-ba06-ad48cfc36326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159898589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2159898589
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.879501570
Short name T210
Test name
Test status
Simulation time 265747956 ps
CPU time 6.49 seconds
Started Jul 27 05:36:42 PM PDT 24
Finished Jul 27 05:36:48 PM PDT 24
Peak memory 211820 kb
Host smart-cfe1c238-fc87-4167-8ad5-b367954357b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=879501570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.879501570
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2640164638
Short name T335
Test name
Test status
Simulation time 186746323 ps
CPU time 10.09 seconds
Started Jul 27 05:36:33 PM PDT 24
Finished Jul 27 05:36:43 PM PDT 24
Peak memory 212820 kb
Host smart-f23d38d5-9021-4ce2-931b-522d41a2c052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640164638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2640164638
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3436038085
Short name T102
Test name
Test status
Simulation time 617334779 ps
CPU time 36 seconds
Started Jul 27 05:36:35 PM PDT 24
Finished Jul 27 05:37:11 PM PDT 24
Peak memory 215372 kb
Host smart-1cf3c6be-fb54-4888-b729-5aee32feb5a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436038085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3436038085
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.832690810
Short name T357
Test name
Test status
Simulation time 89074694 ps
CPU time 4.21 seconds
Started Jul 27 05:36:43 PM PDT 24
Finished Jul 27 05:36:48 PM PDT 24
Peak memory 211776 kb
Host smart-356eb6b5-6792-4d49-aa31-75d330219171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832690810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.832690810
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2144094953
Short name T370
Test name
Test status
Simulation time 1331023154 ps
CPU time 85.78 seconds
Started Jul 27 05:36:41 PM PDT 24
Finished Jul 27 05:38:07 PM PDT 24
Peak memory 228756 kb
Host smart-9e9b3611-7ab4-420d-bbf8-2a5ffd31918f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144094953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2144094953
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1021611085
Short name T244
Test name
Test status
Simulation time 168231106 ps
CPU time 9.67 seconds
Started Jul 27 05:36:41 PM PDT 24
Finished Jul 27 05:36:51 PM PDT 24
Peak memory 212944 kb
Host smart-ae202d4b-f323-4b54-9df7-82b631e16f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021611085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1021611085
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3797575327
Short name T337
Test name
Test status
Simulation time 97675291 ps
CPU time 5.64 seconds
Started Jul 27 05:36:43 PM PDT 24
Finished Jul 27 05:36:48 PM PDT 24
Peak memory 211912 kb
Host smart-dc501e08-dce1-43f8-91a3-e58184b7e145
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3797575327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3797575327
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1879001333
Short name T11
Test name
Test status
Simulation time 209890220 ps
CPU time 10.26 seconds
Started Jul 27 05:36:43 PM PDT 24
Finished Jul 27 05:36:54 PM PDT 24
Peak memory 214248 kb
Host smart-8e2c8800-fec2-45c9-a5fe-919c454d5bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879001333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1879001333
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1888214640
Short name T234
Test name
Test status
Simulation time 3777318063 ps
CPU time 40.58 seconds
Started Jul 27 05:36:45 PM PDT 24
Finished Jul 27 05:37:25 PM PDT 24
Peak memory 219040 kb
Host smart-4689a931-5ab1-4970-b72a-abb81cf61551
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888214640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1888214640
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3790650478
Short name T230
Test name
Test status
Simulation time 253778945692 ps
CPU time 2522.29 seconds
Started Jul 27 05:36:42 PM PDT 24
Finished Jul 27 06:18:45 PM PDT 24
Peak memory 240020 kb
Host smart-6f3c0607-9dcf-409a-b436-f6bf3cc40347
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790650478 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.3790650478
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3513011978
Short name T214
Test name
Test status
Simulation time 126275683 ps
CPU time 5.08 seconds
Started Jul 27 05:36:53 PM PDT 24
Finished Jul 27 05:36:58 PM PDT 24
Peak memory 211740 kb
Host smart-c7885fda-5110-4d43-a2b4-24ca449b01a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513011978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3513011978
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1306787612
Short name T237
Test name
Test status
Simulation time 6454342905 ps
CPU time 97.89 seconds
Started Jul 27 05:36:45 PM PDT 24
Finished Jul 27 05:38:23 PM PDT 24
Peak memory 228940 kb
Host smart-e28368c9-dff2-443f-9081-61ee91f3ff42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306787612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1306787612
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1667567828
Short name T155
Test name
Test status
Simulation time 544939544 ps
CPU time 11.35 seconds
Started Jul 27 05:36:43 PM PDT 24
Finished Jul 27 05:36:55 PM PDT 24
Peak memory 213112 kb
Host smart-90719f67-ea05-499a-b0a0-0a1ae613851c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667567828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1667567828
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2414381348
Short name T156
Test name
Test status
Simulation time 277670751 ps
CPU time 6.42 seconds
Started Jul 27 05:36:53 PM PDT 24
Finished Jul 27 05:37:00 PM PDT 24
Peak memory 211840 kb
Host smart-1fa7f0e4-247a-4f34-b9cc-9d66d8aa7811
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2414381348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2414381348
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3913041491
Short name T254
Test name
Test status
Simulation time 2606426181 ps
CPU time 11.72 seconds
Started Jul 27 05:36:44 PM PDT 24
Finished Jul 27 05:36:55 PM PDT 24
Peak memory 214296 kb
Host smart-0b30e740-45de-4115-bca0-5f9e732271d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913041491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3913041491
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1564602902
Short name T225
Test name
Test status
Simulation time 379331574 ps
CPU time 6.06 seconds
Started Jul 27 05:36:54 PM PDT 24
Finished Jul 27 05:37:00 PM PDT 24
Peak memory 211800 kb
Host smart-78bca31e-0a69-4444-b4af-a17c42e6d5ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564602902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1564602902
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2561898802
Short name T175
Test name
Test status
Simulation time 1385165890 ps
CPU time 5.17 seconds
Started Jul 27 05:36:42 PM PDT 24
Finished Jul 27 05:36:47 PM PDT 24
Peak memory 211688 kb
Host smart-6e6e207c-7080-43cf-8cc4-f532904a865e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561898802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2561898802
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2198468553
Short name T192
Test name
Test status
Simulation time 31788839231 ps
CPU time 154.04 seconds
Started Jul 27 05:36:42 PM PDT 24
Finished Jul 27 05:39:16 PM PDT 24
Peak memory 238232 kb
Host smart-2f5360c6-b6a1-4588-840a-be8f2a66878c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198468553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2198468553
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1919927302
Short name T325
Test name
Test status
Simulation time 532233223 ps
CPU time 11.25 seconds
Started Jul 27 05:36:41 PM PDT 24
Finished Jul 27 05:36:53 PM PDT 24
Peak memory 212728 kb
Host smart-aa1bdd74-f0bc-4462-8200-3c43f2db3166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919927302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1919927302
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1857225693
Short name T178
Test name
Test status
Simulation time 109905642 ps
CPU time 5.89 seconds
Started Jul 27 05:36:42 PM PDT 24
Finished Jul 27 05:36:48 PM PDT 24
Peak memory 211876 kb
Host smart-798b4b96-25fa-4bec-94cd-935b29a57a1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1857225693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1857225693
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1952022534
Short name T286
Test name
Test status
Simulation time 409345295 ps
CPU time 10.1 seconds
Started Jul 27 05:36:42 PM PDT 24
Finished Jul 27 05:36:52 PM PDT 24
Peak memory 213524 kb
Host smart-0573612b-c3f0-4503-a164-4d9d9be3f765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952022534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1952022534
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.389132466
Short name T267
Test name
Test status
Simulation time 1387432696 ps
CPU time 18.01 seconds
Started Jul 27 05:36:54 PM PDT 24
Finished Jul 27 05:37:12 PM PDT 24
Peak memory 214576 kb
Host smart-6b315434-c17f-4369-99d5-be260bab3706
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389132466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.389132466
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.967146227
Short name T374
Test name
Test status
Simulation time 517077561 ps
CPU time 5.18 seconds
Started Jul 27 05:36:44 PM PDT 24
Finished Jul 27 05:36:49 PM PDT 24
Peak memory 211692 kb
Host smart-025ad28e-072b-4daf-b2cd-6beae0207965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967146227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.967146227
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3713886266
Short name T303
Test name
Test status
Simulation time 2243791010 ps
CPU time 127.34 seconds
Started Jul 27 05:36:44 PM PDT 24
Finished Jul 27 05:38:51 PM PDT 24
Peak memory 237204 kb
Host smart-12b4441f-01e6-4bbd-a5eb-370818657706
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713886266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3713886266
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4200561600
Short name T9
Test name
Test status
Simulation time 521088168 ps
CPU time 11.12 seconds
Started Jul 27 05:36:41 PM PDT 24
Finished Jul 27 05:36:52 PM PDT 24
Peak memory 212664 kb
Host smart-79863a39-a954-43a4-9895-69b5081fd16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200561600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.4200561600
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.266176793
Short name T184
Test name
Test status
Simulation time 362055244 ps
CPU time 5.32 seconds
Started Jul 27 05:36:42 PM PDT 24
Finished Jul 27 05:36:47 PM PDT 24
Peak memory 211932 kb
Host smart-f559de78-1bed-44bb-b806-9ff16cf23f21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=266176793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.266176793
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2082280561
Short name T256
Test name
Test status
Simulation time 783990986 ps
CPU time 11.3 seconds
Started Jul 27 05:36:42 PM PDT 24
Finished Jul 27 05:36:53 PM PDT 24
Peak memory 213644 kb
Host smart-638f04d4-c36c-4a6b-8895-150ba2083727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082280561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2082280561
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.4170060594
Short name T173
Test name
Test status
Simulation time 1699235392 ps
CPU time 18.7 seconds
Started Jul 27 05:36:42 PM PDT 24
Finished Jul 27 05:37:00 PM PDT 24
Peak memory 216868 kb
Host smart-6bc7519b-22b9-4dc0-acb9-7d881b9c33f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170060594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.4170060594
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1582522439
Short name T309
Test name
Test status
Simulation time 93996537624 ps
CPU time 4042.11 seconds
Started Jul 27 05:36:42 PM PDT 24
Finished Jul 27 06:44:04 PM PDT 24
Peak memory 254340 kb
Host smart-970f3fe5-4915-4d5c-bc52-60b63c4c272a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582522439 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.1582522439
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.4240434211
Short name T320
Test name
Test status
Simulation time 172986196 ps
CPU time 4.28 seconds
Started Jul 27 05:35:41 PM PDT 24
Finished Jul 27 05:35:45 PM PDT 24
Peak memory 211840 kb
Host smart-6870d507-aafe-4953-88e7-22d46a5cb539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240434211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.4240434211
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4100167752
Short name T223
Test name
Test status
Simulation time 3063556986 ps
CPU time 158.89 seconds
Started Jul 27 05:35:41 PM PDT 24
Finished Jul 27 05:38:20 PM PDT 24
Peak memory 238260 kb
Host smart-55b5a0e3-8112-422b-892d-e5287be16523
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100167752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.4100167752
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3143920972
Short name T278
Test name
Test status
Simulation time 2269380828 ps
CPU time 11.14 seconds
Started Jul 27 05:35:40 PM PDT 24
Finished Jul 27 05:35:51 PM PDT 24
Peak memory 212744 kb
Host smart-4efdbd5b-2c3a-454c-8f39-8f82482d6c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143920972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3143920972
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1251094012
Short name T198
Test name
Test status
Simulation time 153034826 ps
CPU time 5.51 seconds
Started Jul 27 05:35:40 PM PDT 24
Finished Jul 27 05:35:45 PM PDT 24
Peak memory 211920 kb
Host smart-31a3172b-e518-4a6e-8a80-a88dcfed2cdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1251094012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1251094012
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2176351495
Short name T14
Test name
Test status
Simulation time 938104995 ps
CPU time 11.74 seconds
Started Jul 27 05:35:41 PM PDT 24
Finished Jul 27 05:35:53 PM PDT 24
Peak memory 214464 kb
Host smart-f33045f2-916d-4ddc-8c9f-57943ac5f597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176351495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2176351495
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3162162564
Short name T191
Test name
Test status
Simulation time 2829420435 ps
CPU time 28.81 seconds
Started Jul 27 05:35:42 PM PDT 24
Finished Jul 27 05:36:11 PM PDT 24
Peak memory 217388 kb
Host smart-1ab47df1-bc79-4ff2-a240-910df5a86751
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162162564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3162162564
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.4198604605
Short name T197
Test name
Test status
Simulation time 262222673 ps
CPU time 4.91 seconds
Started Jul 27 05:35:43 PM PDT 24
Finished Jul 27 05:35:48 PM PDT 24
Peak memory 211764 kb
Host smart-d9b43e0b-46bf-4c60-926d-e2afb695a376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198604605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.4198604605
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2312551256
Short name T18
Test name
Test status
Simulation time 14178954515 ps
CPU time 133.26 seconds
Started Jul 27 05:35:41 PM PDT 24
Finished Jul 27 05:37:54 PM PDT 24
Peak memory 240320 kb
Host smart-5fc407ab-fd75-4a24-8d88-e05349a91ab5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312551256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2312551256
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1251356574
Short name T373
Test name
Test status
Simulation time 259944553 ps
CPU time 11.45 seconds
Started Jul 27 05:35:40 PM PDT 24
Finished Jul 27 05:35:51 PM PDT 24
Peak memory 212564 kb
Host smart-507047eb-efd9-4e2c-ac0e-35d2bab57c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251356574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1251356574
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.880538544
Short name T16
Test name
Test status
Simulation time 797220184 ps
CPU time 6.49 seconds
Started Jul 27 05:35:42 PM PDT 24
Finished Jul 27 05:35:49 PM PDT 24
Peak memory 211820 kb
Host smart-94190fef-2356-4eb4-856a-459654d7c9cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=880538544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.880538544
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2235499123
Short name T308
Test name
Test status
Simulation time 1070244878 ps
CPU time 10.59 seconds
Started Jul 27 05:35:40 PM PDT 24
Finished Jul 27 05:35:51 PM PDT 24
Peak memory 213672 kb
Host smart-12281a13-a578-4228-8b55-627d118adede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235499123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2235499123
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2236866638
Short name T279
Test name
Test status
Simulation time 526121290 ps
CPU time 24.38 seconds
Started Jul 27 05:35:40 PM PDT 24
Finished Jul 27 05:36:05 PM PDT 24
Peak memory 217088 kb
Host smart-b51e00ee-f0fd-42bc-bb46-680f7221d2be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236866638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2236866638
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.4084062543
Short name T171
Test name
Test status
Simulation time 161583544 ps
CPU time 4.32 seconds
Started Jul 27 05:35:39 PM PDT 24
Finished Jul 27 05:35:44 PM PDT 24
Peak memory 211780 kb
Host smart-3830a833-da12-4689-b5c7-b192faf14d5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084062543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.4084062543
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1802430564
Short name T43
Test name
Test status
Simulation time 3086768572 ps
CPU time 130.77 seconds
Started Jul 27 05:35:43 PM PDT 24
Finished Jul 27 05:37:54 PM PDT 24
Peak memory 238256 kb
Host smart-3e792842-eb17-482d-b069-1f38dec6a521
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802430564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1802430564
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1623046988
Short name T322
Test name
Test status
Simulation time 251725776 ps
CPU time 11.47 seconds
Started Jul 27 05:35:42 PM PDT 24
Finished Jul 27 05:35:54 PM PDT 24
Peak memory 212640 kb
Host smart-afa66156-38bf-4823-856a-fbcfeafbec07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623046988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1623046988
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2478170743
Short name T33
Test name
Test status
Simulation time 1098319931 ps
CPU time 6.18 seconds
Started Jul 27 05:35:41 PM PDT 24
Finished Jul 27 05:35:47 PM PDT 24
Peak memory 211872 kb
Host smart-72fd3873-3ba8-4dc9-b03a-aaa436f7d400
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2478170743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2478170743
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3123009089
Short name T307
Test name
Test status
Simulation time 3504961482 ps
CPU time 10.61 seconds
Started Jul 27 05:35:41 PM PDT 24
Finished Jul 27 05:35:52 PM PDT 24
Peak memory 214448 kb
Host smart-293cf928-f7aa-4f4c-97ba-b95914718950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123009089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3123009089
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3619610534
Short name T56
Test name
Test status
Simulation time 52587690401 ps
CPU time 4219.72 seconds
Started Jul 27 05:35:42 PM PDT 24
Finished Jul 27 06:46:02 PM PDT 24
Peak memory 228156 kb
Host smart-e800a02d-a33f-4a45-8063-93386641c9d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619610534 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3619610534
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1443939454
Short name T181
Test name
Test status
Simulation time 131862595 ps
CPU time 5.34 seconds
Started Jul 27 05:35:40 PM PDT 24
Finished Jul 27 05:35:46 PM PDT 24
Peak memory 211704 kb
Host smart-14cc39a7-6807-46bc-bca7-66820980ee16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443939454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1443939454
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.485908716
Short name T263
Test name
Test status
Simulation time 5649893145 ps
CPU time 83.55 seconds
Started Jul 27 05:35:41 PM PDT 24
Finished Jul 27 05:37:05 PM PDT 24
Peak memory 234636 kb
Host smart-9127d3ab-6c8b-43ce-aa4b-b9d6f05c520a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485908716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.485908716
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.4278225102
Short name T149
Test name
Test status
Simulation time 259980328 ps
CPU time 11.01 seconds
Started Jul 27 05:35:42 PM PDT 24
Finished Jul 27 05:35:53 PM PDT 24
Peak memory 213192 kb
Host smart-ee1c74c9-2fa0-4871-b342-190173602a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278225102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.4278225102
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.4185753458
Short name T2
Test name
Test status
Simulation time 97122499 ps
CPU time 5.66 seconds
Started Jul 27 05:35:42 PM PDT 24
Finished Jul 27 05:35:48 PM PDT 24
Peak memory 211880 kb
Host smart-f82510d6-de99-4a24-b7f5-c4c72faf12d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4185753458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.4185753458
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2627226847
Short name T183
Test name
Test status
Simulation time 536962554 ps
CPU time 11.7 seconds
Started Jul 27 05:35:40 PM PDT 24
Finished Jul 27 05:35:51 PM PDT 24
Peak memory 213432 kb
Host smart-8fecb25f-44f4-44f7-8075-dc2eb81acb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627226847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2627226847
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1434464028
Short name T251
Test name
Test status
Simulation time 610182149 ps
CPU time 28.43 seconds
Started Jul 27 05:35:40 PM PDT 24
Finished Jul 27 05:36:09 PM PDT 24
Peak memory 214952 kb
Host smart-c5813f33-0918-49b1-b026-3205cbf1a8ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434464028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1434464028
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3926769090
Short name T51
Test name
Test status
Simulation time 195824559564 ps
CPU time 2113.39 seconds
Started Jul 27 05:35:41 PM PDT 24
Finished Jul 27 06:10:54 PM PDT 24
Peak memory 242504 kb
Host smart-7cb71c2b-d1a3-41b5-857f-77f85b2c375b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926769090 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3926769090
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.4024497894
Short name T277
Test name
Test status
Simulation time 227621149 ps
CPU time 4.24 seconds
Started Jul 27 05:35:51 PM PDT 24
Finished Jul 27 05:35:56 PM PDT 24
Peak memory 211736 kb
Host smart-5608f1db-1092-46a3-b229-33d42535b990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024497894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.4024497894
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4009318021
Short name T239
Test name
Test status
Simulation time 2929772227 ps
CPU time 52.4 seconds
Started Jul 27 05:35:43 PM PDT 24
Finished Jul 27 05:36:35 PM PDT 24
Peak memory 234132 kb
Host smart-6df2acc3-5e45-4d5c-b8e9-db0cc9386217
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009318021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.4009318021
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1703945217
Short name T333
Test name
Test status
Simulation time 982897096 ps
CPU time 16.12 seconds
Started Jul 27 05:35:42 PM PDT 24
Finished Jul 27 05:35:59 PM PDT 24
Peak memory 212556 kb
Host smart-83ca4679-010d-46af-8550-b9158c5fbf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703945217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1703945217
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4122477887
Short name T331
Test name
Test status
Simulation time 499633640 ps
CPU time 6.59 seconds
Started Jul 27 05:35:41 PM PDT 24
Finished Jul 27 05:35:48 PM PDT 24
Peak memory 211876 kb
Host smart-71454400-5018-4eff-b146-ec5aaacb8300
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122477887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4122477887
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3055660268
Short name T103
Test name
Test status
Simulation time 1096168608 ps
CPU time 12.43 seconds
Started Jul 27 05:35:39 PM PDT 24
Finished Jul 27 05:35:51 PM PDT 24
Peak memory 213244 kb
Host smart-2698364b-a336-42f5-af83-0dca522e4476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055660268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3055660268
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.943209398
Short name T49
Test name
Test status
Simulation time 649578833 ps
CPU time 29.32 seconds
Started Jul 27 05:35:40 PM PDT 24
Finished Jul 27 05:36:09 PM PDT 24
Peak memory 216660 kb
Host smart-9a048018-4680-48f5-957e-43d32c752d15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943209398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.943209398
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1968675087
Short name T349
Test name
Test status
Simulation time 133690009421 ps
CPU time 3705.68 seconds
Started Jul 27 05:35:58 PM PDT 24
Finished Jul 27 06:37:45 PM PDT 24
Peak memory 230540 kb
Host smart-f88f395a-17c8-4f87-90b6-9089dd83c955
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968675087 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.1968675087
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%