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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.35 96.89 92.13 97.67 100.00 98.62 97.30 98.83


Total test records in report: 476
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T303 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3843285171 Jul 28 07:23:49 PM PDT 24 Jul 28 07:26:21 PM PDT 24 12839109612 ps
T304 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1386068440 Jul 28 07:24:36 PM PDT 24 Jul 28 08:18:15 PM PDT 24 13083971200 ps
T305 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.495233495 Jul 28 07:24:50 PM PDT 24 Jul 28 07:24:56 PM PDT 24 100258881 ps
T24 /workspace/coverage/default/0.rom_ctrl_sec_cm.627928738 Jul 28 07:23:48 PM PDT 24 Jul 28 07:25:32 PM PDT 24 333932646 ps
T306 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3194333698 Jul 28 07:24:38 PM PDT 24 Jul 28 07:27:12 PM PDT 24 8841434479 ps
T307 /workspace/coverage/default/21.rom_ctrl_smoke.4284193937 Jul 28 07:24:23 PM PDT 24 Jul 28 07:24:33 PM PDT 24 755642703 ps
T308 /workspace/coverage/default/31.rom_ctrl_smoke.679605168 Jul 28 07:24:34 PM PDT 24 Jul 28 07:24:46 PM PDT 24 1098118062 ps
T309 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4195901900 Jul 28 07:24:52 PM PDT 24 Jul 28 07:27:12 PM PDT 24 2843968475 ps
T310 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1725117881 Jul 28 07:24:33 PM PDT 24 Jul 28 07:24:39 PM PDT 24 423039305 ps
T311 /workspace/coverage/default/27.rom_ctrl_alert_test.206478735 Jul 28 07:24:30 PM PDT 24 Jul 28 07:24:36 PM PDT 24 571486205 ps
T312 /workspace/coverage/default/1.rom_ctrl_smoke.3679965359 Jul 28 07:23:47 PM PDT 24 Jul 28 07:23:59 PM PDT 24 949985807 ps
T313 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2410099390 Jul 28 07:24:15 PM PDT 24 Jul 28 07:24:21 PM PDT 24 213619549 ps
T314 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.209715974 Jul 28 07:23:43 PM PDT 24 Jul 28 07:23:49 PM PDT 24 375738676 ps
T315 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3061899360 Jul 28 07:24:54 PM PDT 24 Jul 28 07:26:55 PM PDT 24 39248072445 ps
T316 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.588560831 Jul 28 07:24:32 PM PDT 24 Jul 28 07:26:21 PM PDT 24 6683423601 ps
T317 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.233059480 Jul 28 07:24:19 PM PDT 24 Jul 28 07:24:25 PM PDT 24 559355151 ps
T318 /workspace/coverage/default/7.rom_ctrl_smoke.3974771257 Jul 28 07:24:00 PM PDT 24 Jul 28 07:24:10 PM PDT 24 695624200 ps
T319 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3772223521 Jul 28 07:24:22 PM PDT 24 Jul 28 07:25:45 PM PDT 24 6119207338 ps
T320 /workspace/coverage/default/30.rom_ctrl_alert_test.1002130952 Jul 28 07:24:37 PM PDT 24 Jul 28 07:24:43 PM PDT 24 251739798 ps
T321 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2923148381 Jul 28 07:23:49 PM PDT 24 Jul 28 07:26:29 PM PDT 24 13315902874 ps
T322 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2701638713 Jul 28 07:24:12 PM PDT 24 Jul 28 07:25:31 PM PDT 24 1443827931 ps
T323 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2651950055 Jul 28 07:24:09 PM PDT 24 Jul 28 07:26:43 PM PDT 24 13931768776 ps
T324 /workspace/coverage/default/46.rom_ctrl_stress_all.2094389593 Jul 28 07:25:02 PM PDT 24 Jul 28 07:25:21 PM PDT 24 810806716 ps
T325 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3670770162 Jul 28 07:24:51 PM PDT 24 Jul 28 07:26:50 PM PDT 24 8005497586 ps
T326 /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2840347547 Jul 28 07:24:41 PM PDT 24 Jul 28 09:30:10 PM PDT 24 36392222627 ps
T327 /workspace/coverage/default/5.rom_ctrl_smoke.3638479248 Jul 28 07:23:56 PM PDT 24 Jul 28 07:24:05 PM PDT 24 186529276 ps
T328 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1049036945 Jul 28 07:24:18 PM PDT 24 Jul 28 07:26:20 PM PDT 24 3448521067 ps
T329 /workspace/coverage/default/8.rom_ctrl_smoke.3799016041 Jul 28 07:24:01 PM PDT 24 Jul 28 07:24:12 PM PDT 24 187415201 ps
T16 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1489880924 Jul 28 07:23:49 PM PDT 24 Jul 28 08:42:22 PM PDT 24 250432230881 ps
T330 /workspace/coverage/default/26.rom_ctrl_stress_all.3109324796 Jul 28 07:24:31 PM PDT 24 Jul 28 07:24:56 PM PDT 24 572690060 ps
T28 /workspace/coverage/default/2.rom_ctrl_sec_cm.3011535058 Jul 28 07:23:48 PM PDT 24 Jul 28 07:25:32 PM PDT 24 617991432 ps
T331 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.693434172 Jul 28 07:24:30 PM PDT 24 Jul 28 07:24:41 PM PDT 24 256619560 ps
T332 /workspace/coverage/default/8.rom_ctrl_stress_all.3783525309 Jul 28 07:24:01 PM PDT 24 Jul 28 07:24:15 PM PDT 24 338815240 ps
T333 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1877867669 Jul 28 07:24:48 PM PDT 24 Jul 28 07:24:55 PM PDT 24 136281586 ps
T334 /workspace/coverage/default/11.rom_ctrl_smoke.3333296150 Jul 28 07:24:07 PM PDT 24 Jul 28 07:24:17 PM PDT 24 180974753 ps
T335 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2377313441 Jul 28 07:23:59 PM PDT 24 Jul 28 07:26:31 PM PDT 24 2953871744 ps
T336 /workspace/coverage/default/47.rom_ctrl_stress_all.894764516 Jul 28 07:25:03 PM PDT 24 Jul 28 07:25:15 PM PDT 24 627037476 ps
T337 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1813452743 Jul 28 07:24:54 PM PDT 24 Jul 28 07:26:18 PM PDT 24 9112822979 ps
T338 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1643718879 Jul 28 07:24:14 PM PDT 24 Jul 28 07:24:20 PM PDT 24 142644260 ps
T339 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2517571411 Jul 28 07:24:49 PM PDT 24 Jul 28 07:27:05 PM PDT 24 10972593647 ps
T340 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1678258491 Jul 28 07:25:02 PM PDT 24 Jul 28 07:26:20 PM PDT 24 12237055913 ps
T341 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.578113092 Jul 28 07:24:03 PM PDT 24 Jul 28 07:24:10 PM PDT 24 143633757 ps
T342 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2098317108 Jul 28 07:23:52 PM PDT 24 Jul 28 07:23:58 PM PDT 24 270118485 ps
T343 /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3394547237 Jul 28 07:24:35 PM PDT 24 Jul 28 08:45:08 PM PDT 24 480821142716 ps
T29 /workspace/coverage/default/1.rom_ctrl_sec_cm.3627156499 Jul 28 07:23:51 PM PDT 24 Jul 28 07:24:44 PM PDT 24 411580494 ps
T344 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4107859837 Jul 28 07:25:04 PM PDT 24 Jul 28 07:27:08 PM PDT 24 4183145135 ps
T345 /workspace/coverage/default/20.rom_ctrl_stress_all.4132175534 Jul 28 07:24:22 PM PDT 24 Jul 28 07:24:38 PM PDT 24 334610641 ps
T346 /workspace/coverage/default/26.rom_ctrl_smoke.3254822909 Jul 28 07:24:32 PM PDT 24 Jul 28 07:24:44 PM PDT 24 396235423 ps
T347 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3358563726 Jul 28 07:24:23 PM PDT 24 Jul 28 07:24:34 PM PDT 24 995625997 ps
T348 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1276121403 Jul 28 07:24:31 PM PDT 24 Jul 28 07:24:42 PM PDT 24 261662379 ps
T349 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1254604340 Jul 28 07:24:19 PM PDT 24 Jul 28 07:26:17 PM PDT 24 2526778969 ps
T350 /workspace/coverage/default/18.rom_ctrl_stress_all.2834214836 Jul 28 07:24:20 PM PDT 24 Jul 28 07:24:27 PM PDT 24 264917847 ps
T351 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1796376642 Jul 28 07:24:05 PM PDT 24 Jul 28 07:26:20 PM PDT 24 9562414598 ps
T352 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2486646351 Jul 28 07:24:32 PM PDT 24 Jul 28 07:26:47 PM PDT 24 13093520457 ps
T353 /workspace/coverage/default/46.rom_ctrl_alert_test.1303323182 Jul 28 07:25:04 PM PDT 24 Jul 28 07:25:09 PM PDT 24 131879042 ps
T354 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.78560567 Jul 28 07:24:06 PM PDT 24 Jul 28 07:24:17 PM PDT 24 509628454 ps
T355 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4163335654 Jul 28 07:23:59 PM PDT 24 Jul 28 07:24:10 PM PDT 24 3557382346 ps
T356 /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2179717536 Jul 28 07:24:52 PM PDT 24 Jul 28 08:31:44 PM PDT 24 99891105221 ps
T357 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2564593667 Jul 28 07:24:38 PM PDT 24 Jul 28 07:24:48 PM PDT 24 618042769 ps
T358 /workspace/coverage/default/39.rom_ctrl_stress_all.2402901225 Jul 28 07:24:50 PM PDT 24 Jul 28 07:25:07 PM PDT 24 312286000 ps
T359 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1827408761 Jul 28 07:24:37 PM PDT 24 Jul 28 07:24:49 PM PDT 24 887711004 ps
T360 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3278930396 Jul 28 07:24:21 PM PDT 24 Jul 28 07:24:28 PM PDT 24 197509099 ps
T361 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3897878252 Jul 28 07:24:36 PM PDT 24 Jul 28 07:27:01 PM PDT 24 8663509084 ps
T362 /workspace/coverage/default/45.rom_ctrl_smoke.1733851603 Jul 28 07:24:59 PM PDT 24 Jul 28 07:25:12 PM PDT 24 523331268 ps
T363 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3314795782 Jul 28 07:24:03 PM PDT 24 Jul 28 07:26:17 PM PDT 24 7282656488 ps
T364 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.4111842496 Jul 28 07:24:54 PM PDT 24 Jul 28 07:25:05 PM PDT 24 262018348 ps
T365 /workspace/coverage/default/14.rom_ctrl_alert_test.1691618303 Jul 28 07:24:13 PM PDT 24 Jul 28 07:24:17 PM PDT 24 89697483 ps
T366 /workspace/coverage/default/43.rom_ctrl_smoke.3890958752 Jul 28 07:24:54 PM PDT 24 Jul 28 07:25:06 PM PDT 24 1032949837 ps
T367 /workspace/coverage/default/33.rom_ctrl_stress_all.2805833574 Jul 28 07:24:35 PM PDT 24 Jul 28 07:24:52 PM PDT 24 717902478 ps
T368 /workspace/coverage/default/17.rom_ctrl_alert_test.2047202335 Jul 28 07:24:19 PM PDT 24 Jul 28 07:24:23 PM PDT 24 333969938 ps
T369 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.4283162021 Jul 28 07:25:06 PM PDT 24 Jul 28 07:28:51 PM PDT 24 25609912272 ps
T370 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2490757243 Jul 28 07:24:15 PM PDT 24 Jul 28 07:24:24 PM PDT 24 176592947 ps
T371 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.476953938 Jul 28 07:24:59 PM PDT 24 Jul 28 07:27:01 PM PDT 24 2188991666 ps
T372 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.925765608 Jul 28 07:24:27 PM PDT 24 Jul 28 07:24:34 PM PDT 24 145775226 ps
T373 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2086044578 Jul 28 07:24:47 PM PDT 24 Jul 28 07:24:58 PM PDT 24 1037601985 ps
T374 /workspace/coverage/default/43.rom_ctrl_stress_all.893687619 Jul 28 07:24:53 PM PDT 24 Jul 28 07:25:17 PM PDT 24 555311459 ps
T375 /workspace/coverage/default/37.rom_ctrl_alert_test.575379291 Jul 28 07:24:46 PM PDT 24 Jul 28 07:24:52 PM PDT 24 168191849 ps
T376 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2882923180 Jul 28 07:23:57 PM PDT 24 Jul 28 07:25:47 PM PDT 24 9417284541 ps
T377 /workspace/coverage/default/2.rom_ctrl_stress_all.477406984 Jul 28 07:23:49 PM PDT 24 Jul 28 07:24:16 PM PDT 24 598406286 ps
T378 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2297668982 Jul 28 07:24:28 PM PDT 24 Jul 28 07:24:33 PM PDT 24 98597109 ps
T379 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.636382845 Jul 28 07:24:18 PM PDT 24 Jul 28 07:24:28 PM PDT 24 173994577 ps
T62 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2892154898 Jul 28 07:17:52 PM PDT 24 Jul 28 07:19:01 PM PDT 24 540692033 ps
T65 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.879305668 Jul 28 07:18:03 PM PDT 24 Jul 28 07:18:08 PM PDT 24 140183722 ps
T66 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2595476519 Jul 28 07:17:16 PM PDT 24 Jul 28 07:17:21 PM PDT 24 88824787 ps
T68 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1953187697 Jul 28 07:17:15 PM PDT 24 Jul 28 07:17:20 PM PDT 24 522419064 ps
T380 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.540214151 Jul 28 07:17:34 PM PDT 24 Jul 28 07:17:42 PM PDT 24 89380855 ps
T96 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3396151963 Jul 28 07:18:00 PM PDT 24 Jul 28 07:18:05 PM PDT 24 107452830 ps
T63 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.49749788 Jul 28 07:17:59 PM PDT 24 Jul 28 07:19:07 PM PDT 24 486179922 ps
T64 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.524183507 Jul 28 07:17:57 PM PDT 24 Jul 28 07:19:07 PM PDT 24 607410034 ps
T111 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3345823387 Jul 28 07:17:16 PM PDT 24 Jul 28 07:18:25 PM PDT 24 1113598768 ps
T381 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4174811333 Jul 28 07:17:53 PM PDT 24 Jul 28 07:18:00 PM PDT 24 640320598 ps
T382 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.545527626 Jul 28 07:18:00 PM PDT 24 Jul 28 07:18:04 PM PDT 24 174902885 ps
T97 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1977771124 Jul 28 07:17:15 PM PDT 24 Jul 28 07:17:19 PM PDT 24 85979488 ps
T98 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2735161804 Jul 28 07:18:02 PM PDT 24 Jul 28 07:18:09 PM PDT 24 131598625 ps
T383 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3476306109 Jul 28 07:18:01 PM PDT 24 Jul 28 07:18:07 PM PDT 24 572684734 ps
T384 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1425517849 Jul 28 07:17:43 PM PDT 24 Jul 28 07:17:49 PM PDT 24 695633549 ps
T385 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3412341239 Jul 28 07:17:46 PM PDT 24 Jul 28 07:17:55 PM PDT 24 131894741 ps
T102 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3098856475 Jul 28 07:17:33 PM PDT 24 Jul 28 07:17:37 PM PDT 24 88928314 ps
T386 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2590258391 Jul 28 07:17:53 PM PDT 24 Jul 28 07:18:02 PM PDT 24 502209470 ps
T109 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3256138567 Jul 28 07:18:02 PM PDT 24 Jul 28 07:18:39 PM PDT 24 209478778 ps
T69 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.427558560 Jul 28 07:17:11 PM PDT 24 Jul 28 07:17:16 PM PDT 24 92035579 ps
T70 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1363661458 Jul 28 07:17:42 PM PDT 24 Jul 28 07:18:04 PM PDT 24 554165979 ps
T99 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2288163081 Jul 28 07:17:53 PM PDT 24 Jul 28 07:17:59 PM PDT 24 131849990 ps
T387 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3097214941 Jul 28 07:17:32 PM PDT 24 Jul 28 07:17:38 PM PDT 24 154863125 ps
T71 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3608843209 Jul 28 07:17:10 PM PDT 24 Jul 28 07:17:32 PM PDT 24 563571060 ps
T388 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3142313178 Jul 28 07:17:47 PM PDT 24 Jul 28 07:17:59 PM PDT 24 2081295028 ps
T110 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.543136636 Jul 28 07:17:37 PM PDT 24 Jul 28 07:18:14 PM PDT 24 231104553 ps
T389 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1243397841 Jul 28 07:17:36 PM PDT 24 Jul 28 07:17:41 PM PDT 24 883694585 ps
T390 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1394810757 Jul 28 07:17:18 PM PDT 24 Jul 28 07:17:22 PM PDT 24 467347088 ps
T100 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4166398007 Jul 28 07:18:02 PM PDT 24 Jul 28 07:18:07 PM PDT 24 85903133 ps
T112 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.671561856 Jul 28 07:17:53 PM PDT 24 Jul 28 07:19:02 PM PDT 24 2020518497 ps
T391 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.990514197 Jul 28 07:17:44 PM PDT 24 Jul 28 07:17:53 PM PDT 24 479136624 ps
T392 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.996653523 Jul 28 07:17:19 PM PDT 24 Jul 28 07:17:24 PM PDT 24 566726089 ps
T393 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4111536183 Jul 28 07:18:00 PM PDT 24 Jul 28 07:18:07 PM PDT 24 113499469 ps
T394 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4112933373 Jul 28 07:17:21 PM PDT 24 Jul 28 07:17:30 PM PDT 24 260695101 ps
T395 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.528278606 Jul 28 07:17:53 PM PDT 24 Jul 28 07:18:04 PM PDT 24 290199660 ps
T72 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3470505548 Jul 28 07:18:01 PM PDT 24 Jul 28 07:18:20 PM PDT 24 1486607860 ps
T396 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.696576121 Jul 28 07:17:10 PM PDT 24 Jul 28 07:17:14 PM PDT 24 346981023 ps
T101 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2978093427 Jul 28 07:17:36 PM PDT 24 Jul 28 07:17:41 PM PDT 24 130578084 ps
T397 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2604061545 Jul 28 07:17:33 PM PDT 24 Jul 28 07:17:38 PM PDT 24 776817202 ps
T398 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2716119326 Jul 28 07:17:24 PM PDT 24 Jul 28 07:17:29 PM PDT 24 436536923 ps
T73 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1540115007 Jul 28 07:17:11 PM PDT 24 Jul 28 07:17:16 PM PDT 24 1383006364 ps
T74 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3758591008 Jul 28 07:18:01 PM PDT 24 Jul 28 07:18:06 PM PDT 24 517854727 ps
T75 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3014185122 Jul 28 07:17:10 PM PDT 24 Jul 28 07:17:17 PM PDT 24 95117270 ps
T116 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.547402751 Jul 28 07:17:12 PM PDT 24 Jul 28 07:17:49 PM PDT 24 354260057 ps
T399 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.215623962 Jul 28 07:17:56 PM PDT 24 Jul 28 07:18:03 PM PDT 24 285766203 ps
T400 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2592541206 Jul 28 07:18:03 PM PDT 24 Jul 28 07:18:08 PM PDT 24 650875644 ps
T76 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2314975804 Jul 28 07:17:21 PM PDT 24 Jul 28 07:17:26 PM PDT 24 333459630 ps
T77 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1857612479 Jul 28 07:17:52 PM PDT 24 Jul 28 07:17:57 PM PDT 24 346884012 ps
T401 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.229414046 Jul 28 07:17:13 PM PDT 24 Jul 28 07:17:18 PM PDT 24 499759558 ps
T402 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3093695059 Jul 28 07:17:55 PM PDT 24 Jul 28 07:18:00 PM PDT 24 489315738 ps
T403 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2162479152 Jul 28 07:17:15 PM PDT 24 Jul 28 07:17:20 PM PDT 24 444697129 ps
T83 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3782182127 Jul 28 07:17:53 PM PDT 24 Jul 28 07:18:14 PM PDT 24 1061289474 ps
T404 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3072491595 Jul 28 07:17:53 PM PDT 24 Jul 28 07:18:01 PM PDT 24 128823765 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.960432873 Jul 28 07:17:16 PM PDT 24 Jul 28 07:17:21 PM PDT 24 129240075 ps
T406 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4014528137 Jul 28 07:17:52 PM PDT 24 Jul 28 07:17:59 PM PDT 24 970592232 ps
T106 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.60416286 Jul 28 07:17:37 PM PDT 24 Jul 28 07:18:49 PM PDT 24 359039683 ps
T407 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1556564154 Jul 28 07:18:03 PM PDT 24 Jul 28 07:18:10 PM PDT 24 829858895 ps
T84 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.601051286 Jul 28 07:17:15 PM PDT 24 Jul 28 07:17:19 PM PDT 24 136039425 ps
T408 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3478484287 Jul 28 07:17:56 PM PDT 24 Jul 28 07:18:28 PM PDT 24 803254947 ps
T118 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2298331815 Jul 28 07:18:00 PM PDT 24 Jul 28 07:18:38 PM PDT 24 754139600 ps
T85 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2167344224 Jul 28 07:17:34 PM PDT 24 Jul 28 07:18:02 PM PDT 24 1123382311 ps
T409 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1544130540 Jul 28 07:17:55 PM PDT 24 Jul 28 07:18:00 PM PDT 24 94635854 ps
T410 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3140888336 Jul 28 07:18:01 PM PDT 24 Jul 28 07:18:06 PM PDT 24 85828871 ps
T411 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3960322267 Jul 28 07:17:22 PM PDT 24 Jul 28 07:17:30 PM PDT 24 2548084779 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3663425198 Jul 28 07:17:26 PM PDT 24 Jul 28 07:17:32 PM PDT 24 332903485 ps
T115 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.272195204 Jul 28 07:17:28 PM PDT 24 Jul 28 07:18:40 PM PDT 24 566553166 ps
T86 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1626164709 Jul 28 07:17:24 PM PDT 24 Jul 28 07:17:57 PM PDT 24 821862385 ps
T413 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1345651049 Jul 28 07:17:25 PM PDT 24 Jul 28 07:17:31 PM PDT 24 129825577 ps
T414 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1189086672 Jul 28 07:17:57 PM PDT 24 Jul 28 07:18:03 PM PDT 24 518969413 ps
T415 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2009737469 Jul 28 07:17:12 PM PDT 24 Jul 28 07:17:17 PM PDT 24 448637011 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.57336098 Jul 28 07:17:16 PM PDT 24 Jul 28 07:17:44 PM PDT 24 1131866887 ps
T87 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.534276809 Jul 28 07:17:30 PM PDT 24 Jul 28 07:17:57 PM PDT 24 1153297774 ps
T417 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.315702547 Jul 28 07:17:52 PM PDT 24 Jul 28 07:17:58 PM PDT 24 131714816 ps
T418 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3618693749 Jul 28 07:17:28 PM PDT 24 Jul 28 07:17:33 PM PDT 24 256974400 ps
T419 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.271222921 Jul 28 07:18:03 PM PDT 24 Jul 28 07:18:08 PM PDT 24 498544189 ps
T420 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3204349888 Jul 28 07:17:51 PM PDT 24 Jul 28 07:17:56 PM PDT 24 1134410776 ps
T421 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2215162635 Jul 28 07:17:12 PM PDT 24 Jul 28 07:17:18 PM PDT 24 833057969 ps
T422 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1057758908 Jul 28 07:17:56 PM PDT 24 Jul 28 07:18:00 PM PDT 24 179221534 ps
T423 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1840680960 Jul 28 07:18:02 PM PDT 24 Jul 28 07:18:08 PM PDT 24 279119435 ps
T424 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2118427874 Jul 28 07:17:15 PM PDT 24 Jul 28 07:17:20 PM PDT 24 132126418 ps
T107 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2725281169 Jul 28 07:17:34 PM PDT 24 Jul 28 07:18:43 PM PDT 24 271823345 ps
T425 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.424149955 Jul 28 07:17:44 PM PDT 24 Jul 28 07:17:49 PM PDT 24 86471178 ps
T426 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1182267795 Jul 28 07:17:29 PM PDT 24 Jul 28 07:17:51 PM PDT 24 2479127179 ps
T427 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1253294335 Jul 28 07:17:31 PM PDT 24 Jul 28 07:17:35 PM PDT 24 335543580 ps
T428 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2497425813 Jul 28 07:17:46 PM PDT 24 Jul 28 07:17:51 PM PDT 24 153256665 ps
T429 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.753481730 Jul 28 07:17:48 PM PDT 24 Jul 28 07:17:52 PM PDT 24 172513600 ps
T430 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.903914095 Jul 28 07:17:30 PM PDT 24 Jul 28 07:17:34 PM PDT 24 116885059 ps
T431 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2829377613 Jul 28 07:17:29 PM PDT 24 Jul 28 07:17:34 PM PDT 24 256645384 ps
T432 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.785668268 Jul 28 07:17:53 PM PDT 24 Jul 28 07:17:57 PM PDT 24 87126215 ps
T92 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1798061761 Jul 28 07:17:36 PM PDT 24 Jul 28 07:17:41 PM PDT 24 129362580 ps
T108 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1842731154 Jul 28 07:17:09 PM PDT 24 Jul 28 07:18:25 PM PDT 24 592489593 ps
T433 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3062651534 Jul 28 07:17:56 PM PDT 24 Jul 28 07:18:24 PM PDT 24 558785350 ps
T434 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3122390675 Jul 28 07:17:30 PM PDT 24 Jul 28 07:17:38 PM PDT 24 2230298616 ps
T435 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4224520537 Jul 28 07:17:22 PM PDT 24 Jul 28 07:17:27 PM PDT 24 165552810 ps
T436 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1092175774 Jul 28 07:17:13 PM PDT 24 Jul 28 07:17:25 PM PDT 24 1000169401 ps
T88 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3804894028 Jul 28 07:17:42 PM PDT 24 Jul 28 07:18:13 PM PDT 24 3256319983 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2923150130 Jul 28 07:17:18 PM PDT 24 Jul 28 07:17:22 PM PDT 24 89331636 ps
T438 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2011519733 Jul 28 07:17:34 PM PDT 24 Jul 28 07:17:39 PM PDT 24 953599805 ps
T439 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2631245719 Jul 28 07:17:46 PM PDT 24 Jul 28 07:18:08 PM PDT 24 2622154511 ps
T440 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2712739409 Jul 28 07:17:38 PM PDT 24 Jul 28 07:17:43 PM PDT 24 184389366 ps
T441 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3303671602 Jul 28 07:17:19 PM PDT 24 Jul 28 07:17:23 PM PDT 24 87333459 ps
T442 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2765407767 Jul 28 07:17:32 PM PDT 24 Jul 28 07:17:38 PM PDT 24 767332219 ps
T443 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1326867564 Jul 28 07:18:00 PM PDT 24 Jul 28 07:18:05 PM PDT 24 224381634 ps
T93 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4089327316 Jul 28 07:17:54 PM PDT 24 Jul 28 07:18:15 PM PDT 24 1094122439 ps
T444 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2774102938 Jul 28 07:17:46 PM PDT 24 Jul 28 07:17:50 PM PDT 24 336854901 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.833516157 Jul 28 07:17:11 PM PDT 24 Jul 28 07:17:19 PM PDT 24 254977104 ps
T446 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4050244422 Jul 28 07:18:02 PM PDT 24 Jul 28 07:18:08 PM PDT 24 127538310 ps
T447 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3414217028 Jul 28 07:17:39 PM PDT 24 Jul 28 07:17:47 PM PDT 24 377885175 ps
T89 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2404417396 Jul 28 07:18:02 PM PDT 24 Jul 28 07:18:34 PM PDT 24 3594277467 ps
T448 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3628361456 Jul 28 07:17:56 PM PDT 24 Jul 28 07:18:00 PM PDT 24 87019296 ps
T90 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2172409686 Jul 28 07:17:21 PM PDT 24 Jul 28 07:17:48 PM PDT 24 7676533798 ps
T94 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1762411658 Jul 28 07:17:40 PM PDT 24 Jul 28 07:18:27 PM PDT 24 6221572356 ps
T449 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1908936550 Jul 28 07:18:00 PM PDT 24 Jul 28 07:18:05 PM PDT 24 85533333 ps
T450 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2233568697 Jul 28 07:17:40 PM PDT 24 Jul 28 07:17:47 PM PDT 24 591573924 ps
T451 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4122406350 Jul 28 07:17:52 PM PDT 24 Jul 28 07:18:20 PM PDT 24 563954687 ps
T113 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1616074723 Jul 28 07:17:54 PM PDT 24 Jul 28 07:18:31 PM PDT 24 746757189 ps
T452 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2251117911 Jul 28 07:17:37 PM PDT 24 Jul 28 07:17:42 PM PDT 24 179274962 ps
T453 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.779067899 Jul 28 07:18:00 PM PDT 24 Jul 28 07:18:22 PM PDT 24 3289545855 ps
T454 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.526141744 Jul 28 07:17:17 PM PDT 24 Jul 28 07:17:24 PM PDT 24 2236932850 ps
T95 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2666433015 Jul 28 07:17:12 PM PDT 24 Jul 28 07:17:39 PM PDT 24 2240931900 ps
T455 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1140696901 Jul 28 07:18:00 PM PDT 24 Jul 28 07:18:38 PM PDT 24 561015615 ps
T456 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.630745186 Jul 28 07:17:42 PM PDT 24 Jul 28 07:17:47 PM PDT 24 264133940 ps
T457 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3770232312 Jul 28 07:17:33 PM PDT 24 Jul 28 07:17:38 PM PDT 24 127646945 ps
T458 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.412033970 Jul 28 07:17:16 PM PDT 24 Jul 28 07:17:24 PM PDT 24 258460812 ps
T459 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3055658106 Jul 28 07:17:57 PM PDT 24 Jul 28 07:18:04 PM PDT 24 127318525 ps
T460 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1403202647 Jul 28 07:17:22 PM PDT 24 Jul 28 07:18:00 PM PDT 24 265423538 ps
T461 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4085931289 Jul 28 07:17:13 PM PDT 24 Jul 28 07:17:17 PM PDT 24 167794942 ps
T462 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.753063031 Jul 28 07:17:42 PM PDT 24 Jul 28 07:17:46 PM PDT 24 87152296 ps
T463 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.743100588 Jul 28 07:17:29 PM PDT 24 Jul 28 07:17:37 PM PDT 24 108409949 ps
T464 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3448434132 Jul 28 07:17:56 PM PDT 24 Jul 28 07:18:04 PM PDT 24 2485711164 ps
T465 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3328232502 Jul 28 07:17:42 PM PDT 24 Jul 28 07:17:47 PM PDT 24 132357388 ps
T466 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3548713936 Jul 28 07:17:34 PM PDT 24 Jul 28 07:17:43 PM PDT 24 828518769 ps
T467 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2726269566 Jul 28 07:17:16 PM PDT 24 Jul 28 07:17:23 PM PDT 24 498767509 ps
T468 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3756003350 Jul 28 07:17:12 PM PDT 24 Jul 28 07:17:18 PM PDT 24 497055165 ps
T469 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2815230076 Jul 28 07:17:08 PM PDT 24 Jul 28 07:17:12 PM PDT 24 88577369 ps
T117 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3610428056 Jul 28 07:17:28 PM PDT 24 Jul 28 07:18:05 PM PDT 24 432557976 ps
T470 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.720730262 Jul 28 07:17:11 PM PDT 24 Jul 28 07:17:17 PM PDT 24 184334108 ps
T471 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3110357853 Jul 28 07:17:56 PM PDT 24 Jul 28 07:19:03 PM PDT 24 1397543302 ps
T472 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.861955130 Jul 28 07:17:44 PM PDT 24 Jul 28 07:18:21 PM PDT 24 318579697 ps
T473 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.655801424 Jul 28 07:17:13 PM PDT 24 Jul 28 07:17:18 PM PDT 24 495004704 ps
T474 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3683711807 Jul 28 07:17:08 PM PDT 24 Jul 28 07:17:17 PM PDT 24 200865245 ps
T91 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.115779367 Jul 28 07:17:24 PM PDT 24 Jul 28 07:17:30 PM PDT 24 257213058 ps
T475 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3557829253 Jul 28 07:17:32 PM PDT 24 Jul 28 07:17:40 PM PDT 24 923363375 ps
T114 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.673909259 Jul 28 07:17:48 PM PDT 24 Jul 28 07:18:31 PM PDT 24 450214711 ps
T476 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3408580846 Jul 28 07:17:55 PM PDT 24 Jul 28 07:18:03 PM PDT 24 495971516 ps

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2438894070
Short name T6
Test name
Test status
Simulation time 4100522473 ps
CPU time 126.62 seconds
Started Jul 28 07:24:41 PM PDT 24
Finished Jul 28 07:26:48 PM PDT 24
Peak memory 235792 kb
Host smart-26183e8c-a7ba-492d-a313-291e07ffac74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438894070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2438894070
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.480159140
Short name T13
Test name
Test status
Simulation time 18883473613 ps
CPU time 757.94 seconds
Started Jul 28 07:24:02 PM PDT 24
Finished Jul 28 07:36:40 PM PDT 24
Peak memory 236344 kb
Host smart-e9660cac-06ff-4fb9-acdc-63da9320e40c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480159140 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.480159140
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.531718427
Short name T7
Test name
Test status
Simulation time 3185512346 ps
CPU time 157.08 seconds
Started Jul 28 07:25:07 PM PDT 24
Finished Jul 28 07:27:44 PM PDT 24
Peak memory 225172 kb
Host smart-2ac7e856-915b-41b3-a009-56bb5b908857
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531718427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.531718427
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2713488816
Short name T239
Test name
Test status
Simulation time 60741906255 ps
CPU time 179.15 seconds
Started Jul 28 07:24:14 PM PDT 24
Finished Jul 28 07:27:14 PM PDT 24
Peak memory 238260 kb
Host smart-98bc810f-1893-4412-b219-72ef5604815f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713488816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2713488816
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2892154898
Short name T62
Test name
Test status
Simulation time 540692033 ps
CPU time 68.7 seconds
Started Jul 28 07:17:52 PM PDT 24
Finished Jul 28 07:19:01 PM PDT 24
Peak memory 218732 kb
Host smart-0437ea81-8547-461b-90e2-38154b504972
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892154898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2892154898
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1876339875
Short name T103
Test name
Test status
Simulation time 1747267734 ps
CPU time 24.99 seconds
Started Jul 28 07:23:52 PM PDT 24
Finished Jul 28 07:24:17 PM PDT 24
Peak memory 215780 kb
Host smart-7baac12c-ffaf-4569-90d5-481df0c41c09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876339875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1876339875
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2769221079
Short name T10
Test name
Test status
Simulation time 347228205 ps
CPU time 4.35 seconds
Started Jul 28 07:25:02 PM PDT 24
Finished Jul 28 07:25:06 PM PDT 24
Peak memory 211768 kb
Host smart-f9889a50-2423-4143-84fb-fdc68e6cf051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769221079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2769221079
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.575272350
Short name T23
Test name
Test status
Simulation time 757440848 ps
CPU time 99.2 seconds
Started Jul 28 07:23:52 PM PDT 24
Finished Jul 28 07:25:32 PM PDT 24
Peak memory 238776 kb
Host smart-f3d08928-f1d8-45e0-955e-b3f06151a66e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575272350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.575272350
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.534276809
Short name T87
Test name
Test status
Simulation time 1153297774 ps
CPU time 27.07 seconds
Started Jul 28 07:17:30 PM PDT 24
Finished Jul 28 07:17:57 PM PDT 24
Peak memory 210492 kb
Host smart-ab0a0140-a394-4e38-b553-3b2e500a35d9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534276809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.534276809
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.547402751
Short name T116
Test name
Test status
Simulation time 354260057 ps
CPU time 36.16 seconds
Started Jul 28 07:17:12 PM PDT 24
Finished Jul 28 07:17:49 PM PDT 24
Peak memory 218752 kb
Host smart-5b166537-c096-4886-aee0-eae376a5a626
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547402751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.547402751
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3794051255
Short name T119
Test name
Test status
Simulation time 302789664656 ps
CPU time 2542.82 seconds
Started Jul 28 07:24:59 PM PDT 24
Finished Jul 28 08:07:23 PM PDT 24
Peak memory 244604 kb
Host smart-0fd98cbb-c27e-4811-9046-56bb9215af07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794051255 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3794051255
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3608843209
Short name T71
Test name
Test status
Simulation time 563571060 ps
CPU time 21.76 seconds
Started Jul 28 07:17:10 PM PDT 24
Finished Jul 28 07:17:32 PM PDT 24
Peak memory 210624 kb
Host smart-12571109-239d-45ee-af84-1846152d2f55
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608843209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3608843209
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3628943355
Short name T34
Test name
Test status
Simulation time 298015458 ps
CPU time 14.03 seconds
Started Jul 28 07:24:06 PM PDT 24
Finished Jul 28 07:24:20 PM PDT 24
Peak memory 214580 kb
Host smart-f0c8ec75-2ced-44a5-aad8-9e59b16c9ab7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628943355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3628943355
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.455082283
Short name T4
Test name
Test status
Simulation time 1039342186 ps
CPU time 15.98 seconds
Started Jul 28 07:24:27 PM PDT 24
Finished Jul 28 07:24:43 PM PDT 24
Peak memory 212828 kb
Host smart-3982bb2f-3fa8-4a36-b1a1-15374278debe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455082283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.455082283
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.29275281
Short name T216
Test name
Test status
Simulation time 441411998 ps
CPU time 9.44 seconds
Started Jul 28 07:23:45 PM PDT 24
Finished Jul 28 07:23:55 PM PDT 24
Peak memory 211956 kb
Host smart-b91343f5-8fc8-495a-b84b-5b15ccbeb3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29275281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.29275281
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.688508749
Short name T47
Test name
Test status
Simulation time 665842443 ps
CPU time 9.4 seconds
Started Jul 28 07:24:28 PM PDT 24
Finished Jul 28 07:24:38 PM PDT 24
Peak memory 212616 kb
Host smart-bba8ebcc-fb12-435a-bb52-3a5ed16ec67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688508749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.688508749
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1842731154
Short name T108
Test name
Test status
Simulation time 592489593 ps
CPU time 76.62 seconds
Started Jul 28 07:17:09 PM PDT 24
Finished Jul 28 07:18:25 PM PDT 24
Peak memory 213204 kb
Host smart-7ef41329-0646-4399-b71f-e0a2d27ca419
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842731154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1842731154
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1616074723
Short name T113
Test name
Test status
Simulation time 746757189 ps
CPU time 37.09 seconds
Started Jul 28 07:17:54 PM PDT 24
Finished Jul 28 07:18:31 PM PDT 24
Peak memory 212252 kb
Host smart-04bd8daf-375e-42c9-8468-2f7a7975ba93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616074723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1616074723
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1168410894
Short name T12
Test name
Test status
Simulation time 314718273 ps
CPU time 18.8 seconds
Started Jul 28 07:24:27 PM PDT 24
Finished Jul 28 07:24:46 PM PDT 24
Peak memory 217048 kb
Host smart-407646cb-4da4-4753-8a4a-09bc328b2cee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168410894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1168410894
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3985071722
Short name T14
Test name
Test status
Simulation time 598320918549 ps
CPU time 4863.26 seconds
Started Jul 28 07:24:08 PM PDT 24
Finished Jul 28 08:45:12 PM PDT 24
Peak memory 252676 kb
Host smart-95289c8e-99ec-41cd-82ec-a007510cabcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985071722 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3985071722
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3551043308
Short name T194
Test name
Test status
Simulation time 197109204831 ps
CPU time 4087.75 seconds
Started Jul 28 07:24:19 PM PDT 24
Finished Jul 28 08:32:28 PM PDT 24
Peak memory 252808 kb
Host smart-338e100a-fe35-4d34-9069-bd1efecbb1c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551043308 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.3551043308
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.427558560
Short name T69
Test name
Test status
Simulation time 92035579 ps
CPU time 4.28 seconds
Started Jul 28 07:17:11 PM PDT 24
Finished Jul 28 07:17:16 PM PDT 24
Peak memory 210576 kb
Host smart-764f5138-4cc1-48a4-9fc5-6bc45b169ec2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427558560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.427558560
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3756003350
Short name T468
Test name
Test status
Simulation time 497055165 ps
CPU time 5.26 seconds
Started Jul 28 07:17:12 PM PDT 24
Finished Jul 28 07:17:18 PM PDT 24
Peak memory 218736 kb
Host smart-e434668c-7e3c-447f-be19-c77dddcb4052
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756003350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3756003350
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3014185122
Short name T75
Test name
Test status
Simulation time 95117270 ps
CPU time 7.45 seconds
Started Jul 28 07:17:10 PM PDT 24
Finished Jul 28 07:17:17 PM PDT 24
Peak memory 210540 kb
Host smart-753cb91d-ea17-4c6d-bc01-3cac94c1a931
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014185122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3014185122
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.720730262
Short name T470
Test name
Test status
Simulation time 184334108 ps
CPU time 5.4 seconds
Started Jul 28 07:17:11 PM PDT 24
Finished Jul 28 07:17:17 PM PDT 24
Peak memory 218780 kb
Host smart-57fbe201-a0e9-4362-a593-e31fa7c8651f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720730262 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.720730262
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1540115007
Short name T73
Test name
Test status
Simulation time 1383006364 ps
CPU time 5.05 seconds
Started Jul 28 07:17:11 PM PDT 24
Finished Jul 28 07:17:16 PM PDT 24
Peak memory 210456 kb
Host smart-748d4230-d3b0-4b51-9fd8-531769da877d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540115007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1540115007
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2815230076
Short name T469
Test name
Test status
Simulation time 88577369 ps
CPU time 4.16 seconds
Started Jul 28 07:17:08 PM PDT 24
Finished Jul 28 07:17:12 PM PDT 24
Peak memory 210364 kb
Host smart-d72896c9-01f9-4eb9-988a-b31f6af18543
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815230076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2815230076
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.696576121
Short name T396
Test name
Test status
Simulation time 346981023 ps
CPU time 4.54 seconds
Started Jul 28 07:17:10 PM PDT 24
Finished Jul 28 07:17:14 PM PDT 24
Peak memory 210356 kb
Host smart-1ccca614-f155-4fc1-8385-7a25030d963b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696576121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
696576121
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2215162635
Short name T421
Test name
Test status
Simulation time 833057969 ps
CPU time 5.4 seconds
Started Jul 28 07:17:12 PM PDT 24
Finished Jul 28 07:17:18 PM PDT 24
Peak memory 210664 kb
Host smart-9dda56f7-128c-4938-8267-30d994641690
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215162635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2215162635
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3683711807
Short name T474
Test name
Test status
Simulation time 200865245 ps
CPU time 9.04 seconds
Started Jul 28 07:17:08 PM PDT 24
Finished Jul 28 07:17:17 PM PDT 24
Peak memory 218884 kb
Host smart-401f39a0-9a34-4b15-a05b-b62f698a24f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683711807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3683711807
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2118427874
Short name T424
Test name
Test status
Simulation time 132126418 ps
CPU time 4.99 seconds
Started Jul 28 07:17:15 PM PDT 24
Finished Jul 28 07:17:20 PM PDT 24
Peak memory 218728 kb
Host smart-eac33347-2c4a-430c-a5c9-5969ea507ad9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118427874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2118427874
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.229414046
Short name T401
Test name
Test status
Simulation time 499759558 ps
CPU time 5.29 seconds
Started Jul 28 07:17:13 PM PDT 24
Finished Jul 28 07:17:18 PM PDT 24
Peak memory 210572 kb
Host smart-57844705-3c76-4ca9-8fe0-e4ae1660513c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229414046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.229414046
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.833516157
Short name T445
Test name
Test status
Simulation time 254977104 ps
CPU time 8.12 seconds
Started Jul 28 07:17:11 PM PDT 24
Finished Jul 28 07:17:19 PM PDT 24
Peak memory 218684 kb
Host smart-0041a32c-128f-4e6e-b6eb-fa8944113ce8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833516157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.833516157
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.526141744
Short name T454
Test name
Test status
Simulation time 2236932850 ps
CPU time 6.24 seconds
Started Jul 28 07:17:17 PM PDT 24
Finished Jul 28 07:17:24 PM PDT 24
Peak memory 215268 kb
Host smart-d02fec5c-73b0-4f4d-9cf2-905d8caa68e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526141744 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.526141744
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4085931289
Short name T461
Test name
Test status
Simulation time 167794942 ps
CPU time 4.02 seconds
Started Jul 28 07:17:13 PM PDT 24
Finished Jul 28 07:17:17 PM PDT 24
Peak memory 218652 kb
Host smart-359e4325-f0fa-43ea-981e-806c8e033af3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085931289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4085931289
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2009737469
Short name T415
Test name
Test status
Simulation time 448637011 ps
CPU time 4.87 seconds
Started Jul 28 07:17:12 PM PDT 24
Finished Jul 28 07:17:17 PM PDT 24
Peak memory 210460 kb
Host smart-4d97c0e3-9550-4cf2-bcbb-8298b2aa3d0a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009737469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2009737469
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.655801424
Short name T473
Test name
Test status
Simulation time 495004704 ps
CPU time 4.86 seconds
Started Jul 28 07:17:13 PM PDT 24
Finished Jul 28 07:17:18 PM PDT 24
Peak memory 210408 kb
Host smart-98603f51-193b-478b-89ca-f5fe92c2122e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655801424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
655801424
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2666433015
Short name T95
Test name
Test status
Simulation time 2240931900 ps
CPU time 27.35 seconds
Started Jul 28 07:17:12 PM PDT 24
Finished Jul 28 07:17:39 PM PDT 24
Peak memory 210716 kb
Host smart-fd406ab5-5675-4e89-a626-e3dbf5249f36
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666433015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2666433015
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1977771124
Short name T97
Test name
Test status
Simulation time 85979488 ps
CPU time 4.25 seconds
Started Jul 28 07:17:15 PM PDT 24
Finished Jul 28 07:17:19 PM PDT 24
Peak memory 210696 kb
Host smart-1f89ee3b-991f-4e27-997e-dc36de144dda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977771124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1977771124
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1092175774
Short name T436
Test name
Test status
Simulation time 1000169401 ps
CPU time 11.56 seconds
Started Jul 28 07:17:13 PM PDT 24
Finished Jul 28 07:17:25 PM PDT 24
Peak memory 215856 kb
Host smart-8e89172e-9ef4-40ae-b2d5-9ff3f56d829b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092175774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1092175774
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2497425813
Short name T428
Test name
Test status
Simulation time 153256665 ps
CPU time 5.45 seconds
Started Jul 28 07:17:46 PM PDT 24
Finished Jul 28 07:17:51 PM PDT 24
Peak memory 218824 kb
Host smart-bb16963b-5a5f-40a0-b6b9-d3db82c5a145
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497425813 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2497425813
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.753481730
Short name T429
Test name
Test status
Simulation time 172513600 ps
CPU time 4.2 seconds
Started Jul 28 07:17:48 PM PDT 24
Finished Jul 28 07:17:52 PM PDT 24
Peak memory 210572 kb
Host smart-89fa503b-e2e2-476c-9c22-41207186aa0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753481730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.753481730
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3804894028
Short name T88
Test name
Test status
Simulation time 3256319983 ps
CPU time 31.26 seconds
Started Jul 28 07:17:42 PM PDT 24
Finished Jul 28 07:18:13 PM PDT 24
Peak memory 210800 kb
Host smart-a2f4d80f-c2cf-4133-b374-1b25c8db1dd0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804894028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3804894028
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2774102938
Short name T444
Test name
Test status
Simulation time 336854901 ps
CPU time 4.23 seconds
Started Jul 28 07:17:46 PM PDT 24
Finished Jul 28 07:17:50 PM PDT 24
Peak memory 210496 kb
Host smart-39ac0a2f-9589-40c1-b58d-2f0ea33a9024
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774102938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2774102938
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3142313178
Short name T388
Test name
Test status
Simulation time 2081295028 ps
CPU time 11.73 seconds
Started Jul 28 07:17:47 PM PDT 24
Finished Jul 28 07:17:59 PM PDT 24
Peak memory 214836 kb
Host smart-5bda167e-f16c-4237-b0ef-8b81a1abd297
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142313178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3142313178
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.673909259
Short name T114
Test name
Test status
Simulation time 450214711 ps
CPU time 43.02 seconds
Started Jul 28 07:17:48 PM PDT 24
Finished Jul 28 07:18:31 PM PDT 24
Peak memory 213352 kb
Host smart-968f0d7f-f0c9-4820-ab39-e43ceb25d908
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673909259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.673909259
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4174811333
Short name T381
Test name
Test status
Simulation time 640320598 ps
CPU time 6.73 seconds
Started Jul 28 07:17:53 PM PDT 24
Finished Jul 28 07:18:00 PM PDT 24
Peak memory 216264 kb
Host smart-ae4c66b5-15ed-4399-978d-0f4cbc8cc408
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174811333 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4174811333
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1857612479
Short name T77
Test name
Test status
Simulation time 346884012 ps
CPU time 4.2 seconds
Started Jul 28 07:17:52 PM PDT 24
Finished Jul 28 07:17:57 PM PDT 24
Peak memory 218664 kb
Host smart-d07eed45-0a47-4ea4-a76c-be3e9c95aa93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857612479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1857612479
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2631245719
Short name T439
Test name
Test status
Simulation time 2622154511 ps
CPU time 22.22 seconds
Started Jul 28 07:17:46 PM PDT 24
Finished Jul 28 07:18:08 PM PDT 24
Peak memory 210684 kb
Host smart-6de46121-0cfa-4804-8f0a-4687f9f4a92c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631245719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2631245719
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3204349888
Short name T420
Test name
Test status
Simulation time 1134410776 ps
CPU time 4.87 seconds
Started Jul 28 07:17:51 PM PDT 24
Finished Jul 28 07:17:56 PM PDT 24
Peak memory 218788 kb
Host smart-072495a4-0f50-4947-82f3-fd0bfa94332e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204349888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3204349888
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3412341239
Short name T385
Test name
Test status
Simulation time 131894741 ps
CPU time 9.28 seconds
Started Jul 28 07:17:46 PM PDT 24
Finished Jul 28 07:17:55 PM PDT 24
Peak memory 215772 kb
Host smart-17104d34-ac5b-4225-b42e-a4d3d50ca46b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412341239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3412341239
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3256138567
Short name T109
Test name
Test status
Simulation time 209478778 ps
CPU time 37.45 seconds
Started Jul 28 07:18:02 PM PDT 24
Finished Jul 28 07:18:39 PM PDT 24
Peak memory 211972 kb
Host smart-a8379071-0a3a-4b35-b8a0-976a53f28696
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256138567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3256138567
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1840680960
Short name T423
Test name
Test status
Simulation time 279119435 ps
CPU time 5.61 seconds
Started Jul 28 07:18:02 PM PDT 24
Finished Jul 28 07:18:08 PM PDT 24
Peak memory 218836 kb
Host smart-9b2e5b8b-0586-48e3-838a-2b0c61d3eb0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840680960 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1840680960
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.785668268
Short name T432
Test name
Test status
Simulation time 87126215 ps
CPU time 4.09 seconds
Started Jul 28 07:17:53 PM PDT 24
Finished Jul 28 07:17:57 PM PDT 24
Peak memory 210552 kb
Host smart-08bad794-5801-438e-84f4-64d4e6c3ca46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785668268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.785668268
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4089327316
Short name T93
Test name
Test status
Simulation time 1094122439 ps
CPU time 21.6 seconds
Started Jul 28 07:17:54 PM PDT 24
Finished Jul 28 07:18:15 PM PDT 24
Peak memory 210640 kb
Host smart-c7a7bdba-807b-4e6e-aabc-221769380b99
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089327316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.4089327316
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2288163081
Short name T99
Test name
Test status
Simulation time 131849990 ps
CPU time 5.48 seconds
Started Jul 28 07:17:53 PM PDT 24
Finished Jul 28 07:17:59 PM PDT 24
Peak memory 218700 kb
Host smart-d5d01bee-1467-4c63-a6fa-20b2c507f047
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288163081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2288163081
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2590258391
Short name T386
Test name
Test status
Simulation time 502209470 ps
CPU time 9.03 seconds
Started Jul 28 07:17:53 PM PDT 24
Finished Jul 28 07:18:02 PM PDT 24
Peak memory 215856 kb
Host smart-2ffabc98-8528-4658-890a-106f1850511f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590258391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2590258391
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1544130540
Short name T409
Test name
Test status
Simulation time 94635854 ps
CPU time 4.43 seconds
Started Jul 28 07:17:55 PM PDT 24
Finished Jul 28 07:18:00 PM PDT 24
Peak memory 212400 kb
Host smart-55061b32-ea79-418d-a77d-6b1549002ea1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544130540 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1544130540
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1057758908
Short name T422
Test name
Test status
Simulation time 179221534 ps
CPU time 4.13 seconds
Started Jul 28 07:17:56 PM PDT 24
Finished Jul 28 07:18:00 PM PDT 24
Peak memory 210608 kb
Host smart-f01d4287-76b2-41ee-8f44-3e39d0125010
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057758908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1057758908
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3782182127
Short name T83
Test name
Test status
Simulation time 1061289474 ps
CPU time 21.24 seconds
Started Jul 28 07:17:53 PM PDT 24
Finished Jul 28 07:18:14 PM PDT 24
Peak memory 210580 kb
Host smart-51db1c9f-7876-4c75-bda2-4934d9e61d59
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782182127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3782182127
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4014528137
Short name T406
Test name
Test status
Simulation time 970592232 ps
CPU time 6.98 seconds
Started Jul 28 07:17:52 PM PDT 24
Finished Jul 28 07:17:59 PM PDT 24
Peak memory 218756 kb
Host smart-d199a057-718c-490f-a380-73f209723174
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014528137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.4014528137
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3072491595
Short name T404
Test name
Test status
Simulation time 128823765 ps
CPU time 7.44 seconds
Started Jul 28 07:17:53 PM PDT 24
Finished Jul 28 07:18:01 PM PDT 24
Peak memory 214480 kb
Host smart-a7a81630-065f-42b8-afe8-e90206e1dea6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072491595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3072491595
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3110357853
Short name T471
Test name
Test status
Simulation time 1397543302 ps
CPU time 66.21 seconds
Started Jul 28 07:17:56 PM PDT 24
Finished Jul 28 07:19:03 PM PDT 24
Peak memory 213148 kb
Host smart-d05b4f62-d409-471e-a566-1c297bfdddd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110357853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3110357853
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.215623962
Short name T399
Test name
Test status
Simulation time 285766203 ps
CPU time 6.66 seconds
Started Jul 28 07:17:56 PM PDT 24
Finished Jul 28 07:18:03 PM PDT 24
Peak memory 215768 kb
Host smart-dfd99532-bd15-4f3d-a145-bb0bdb1fda69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215623962 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.215623962
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.315702547
Short name T417
Test name
Test status
Simulation time 131714816 ps
CPU time 5.12 seconds
Started Jul 28 07:17:52 PM PDT 24
Finished Jul 28 07:17:58 PM PDT 24
Peak memory 210520 kb
Host smart-6e0511ef-3ab3-413a-bc62-1f9442367fe4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315702547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.315702547
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4122406350
Short name T451
Test name
Test status
Simulation time 563954687 ps
CPU time 27.59 seconds
Started Jul 28 07:17:52 PM PDT 24
Finished Jul 28 07:18:20 PM PDT 24
Peak memory 210620 kb
Host smart-29ad0f43-1cb3-4fdc-a7a4-39c8c74f8cba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122406350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.4122406350
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2735161804
Short name T98
Test name
Test status
Simulation time 131598625 ps
CPU time 6.73 seconds
Started Jul 28 07:18:02 PM PDT 24
Finished Jul 28 07:18:09 PM PDT 24
Peak memory 218744 kb
Host smart-ffec2da5-f4fb-44ec-9ca8-fc655bb9857e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735161804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2735161804
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.528278606
Short name T395
Test name
Test status
Simulation time 290199660 ps
CPU time 10.93 seconds
Started Jul 28 07:17:53 PM PDT 24
Finished Jul 28 07:18:04 PM PDT 24
Peak memory 217000 kb
Host smart-38d96544-3058-43e5-b86c-060ad745c04b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528278606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.528278606
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3476306109
Short name T383
Test name
Test status
Simulation time 572684734 ps
CPU time 5.9 seconds
Started Jul 28 07:18:01 PM PDT 24
Finished Jul 28 07:18:07 PM PDT 24
Peak memory 218784 kb
Host smart-dacc3e88-f89e-40bc-a99e-f85836eb634b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476306109 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3476306109
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4050244422
Short name T446
Test name
Test status
Simulation time 127538310 ps
CPU time 5.07 seconds
Started Jul 28 07:18:02 PM PDT 24
Finished Jul 28 07:18:08 PM PDT 24
Peak memory 210492 kb
Host smart-671736ac-86df-4df9-82dd-0a9ce2e0d6b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050244422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.4050244422
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3062651534
Short name T433
Test name
Test status
Simulation time 558785350 ps
CPU time 27.63 seconds
Started Jul 28 07:17:56 PM PDT 24
Finished Jul 28 07:18:24 PM PDT 24
Peak memory 210708 kb
Host smart-3256c6bc-3195-48b6-8169-1c9e572a8e89
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062651534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3062651534
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3628361456
Short name T448
Test name
Test status
Simulation time 87019296 ps
CPU time 4.4 seconds
Started Jul 28 07:17:56 PM PDT 24
Finished Jul 28 07:18:00 PM PDT 24
Peak memory 210656 kb
Host smart-36b89752-5d64-473c-aac7-2ae56315c2ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628361456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3628361456
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3408580846
Short name T476
Test name
Test status
Simulation time 495971516 ps
CPU time 7.92 seconds
Started Jul 28 07:17:55 PM PDT 24
Finished Jul 28 07:18:03 PM PDT 24
Peak memory 215432 kb
Host smart-6be78663-fc3d-4f9e-adb0-1b22171f4063
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408580846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3408580846
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.524183507
Short name T64
Test name
Test status
Simulation time 607410034 ps
CPU time 70 seconds
Started Jul 28 07:17:57 PM PDT 24
Finished Jul 28 07:19:07 PM PDT 24
Peak memory 212324 kb
Host smart-7b34b739-cd60-4121-932b-646632dbaed5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524183507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.524183507
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2592541206
Short name T400
Test name
Test status
Simulation time 650875644 ps
CPU time 4.85 seconds
Started Jul 28 07:18:03 PM PDT 24
Finished Jul 28 07:18:08 PM PDT 24
Peak memory 218816 kb
Host smart-26e8c4ac-3a36-46bc-9adc-b8fb61e5ae20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592541206 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2592541206
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3093695059
Short name T402
Test name
Test status
Simulation time 489315738 ps
CPU time 4.21 seconds
Started Jul 28 07:17:55 PM PDT 24
Finished Jul 28 07:18:00 PM PDT 24
Peak memory 210596 kb
Host smart-9e4d3637-7198-4547-b957-b8572643e451
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093695059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3093695059
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2404417396
Short name T89
Test name
Test status
Simulation time 3594277467 ps
CPU time 32.54 seconds
Started Jul 28 07:18:02 PM PDT 24
Finished Jul 28 07:18:34 PM PDT 24
Peak memory 210704 kb
Host smart-c93acaaa-64da-4023-8207-fc3ca663d3d1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404417396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2404417396
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1189086672
Short name T414
Test name
Test status
Simulation time 518969413 ps
CPU time 5.23 seconds
Started Jul 28 07:17:57 PM PDT 24
Finished Jul 28 07:18:03 PM PDT 24
Peak memory 218048 kb
Host smart-38583cf3-07d1-4faa-94a6-0273542319f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189086672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1189086672
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3055658106
Short name T459
Test name
Test status
Simulation time 127318525 ps
CPU time 7.08 seconds
Started Jul 28 07:17:57 PM PDT 24
Finished Jul 28 07:18:04 PM PDT 24
Peak memory 218824 kb
Host smart-8e0852ea-f1cd-4210-8416-ee5fc6bf96a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055658106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3055658106
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2298331815
Short name T118
Test name
Test status
Simulation time 754139600 ps
CPU time 37.18 seconds
Started Jul 28 07:18:00 PM PDT 24
Finished Jul 28 07:18:38 PM PDT 24
Peak memory 218744 kb
Host smart-ff4737b7-9bbb-413f-b7b7-7aebbf61caf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298331815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2298331815
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.879305668
Short name T65
Test name
Test status
Simulation time 140183722 ps
CPU time 5.38 seconds
Started Jul 28 07:18:03 PM PDT 24
Finished Jul 28 07:18:08 PM PDT 24
Peak memory 213812 kb
Host smart-2301e54d-5aa7-457e-9e75-b79e2853d7f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879305668 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.879305668
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4166398007
Short name T100
Test name
Test status
Simulation time 85903133 ps
CPU time 4.28 seconds
Started Jul 28 07:18:02 PM PDT 24
Finished Jul 28 07:18:07 PM PDT 24
Peak memory 210556 kb
Host smart-0fd665c7-4546-4a1e-b799-2817d046b40d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166398007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.4166398007
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3478484287
Short name T408
Test name
Test status
Simulation time 803254947 ps
CPU time 32.07 seconds
Started Jul 28 07:17:56 PM PDT 24
Finished Jul 28 07:18:28 PM PDT 24
Peak memory 210688 kb
Host smart-bed82c5c-cbe1-444e-bafe-7f76a772e990
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478484287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3478484287
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.271222921
Short name T419
Test name
Test status
Simulation time 498544189 ps
CPU time 5.3 seconds
Started Jul 28 07:18:03 PM PDT 24
Finished Jul 28 07:18:08 PM PDT 24
Peak memory 218796 kb
Host smart-1bad13d8-71cc-492f-9743-2ea53a36e95b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271222921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.271222921
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3448434132
Short name T464
Test name
Test status
Simulation time 2485711164 ps
CPU time 7.4 seconds
Started Jul 28 07:17:56 PM PDT 24
Finished Jul 28 07:18:04 PM PDT 24
Peak memory 218912 kb
Host smart-2e948994-3eea-4216-965f-6e4cd84e872d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448434132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3448434132
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.671561856
Short name T112
Test name
Test status
Simulation time 2020518497 ps
CPU time 68.22 seconds
Started Jul 28 07:17:53 PM PDT 24
Finished Jul 28 07:19:02 PM PDT 24
Peak memory 212580 kb
Host smart-22a0c2d7-28cf-414d-b382-3fc97305acc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671561856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.671561856
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1326867564
Short name T443
Test name
Test status
Simulation time 224381634 ps
CPU time 5.14 seconds
Started Jul 28 07:18:00 PM PDT 24
Finished Jul 28 07:18:05 PM PDT 24
Peak memory 215512 kb
Host smart-4a2bcd38-814e-4053-ad2c-b2a00e301b13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326867564 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1326867564
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3758591008
Short name T74
Test name
Test status
Simulation time 517854727 ps
CPU time 5.12 seconds
Started Jul 28 07:18:01 PM PDT 24
Finished Jul 28 07:18:06 PM PDT 24
Peak memory 218676 kb
Host smart-a06a384f-bbe0-4c6f-af1b-efe815cb1a65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758591008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3758591008
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.779067899
Short name T453
Test name
Test status
Simulation time 3289545855 ps
CPU time 22.55 seconds
Started Jul 28 07:18:00 PM PDT 24
Finished Jul 28 07:18:22 PM PDT 24
Peak memory 210652 kb
Host smart-c7aef2ec-9ad5-4e21-8d91-47ffc27f9873
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779067899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.779067899
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1908936550
Short name T449
Test name
Test status
Simulation time 85533333 ps
CPU time 4.39 seconds
Started Jul 28 07:18:00 PM PDT 24
Finished Jul 28 07:18:05 PM PDT 24
Peak memory 210636 kb
Host smart-af9441da-d817-421a-8410-54bcb00f678e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908936550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1908936550
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4111536183
Short name T393
Test name
Test status
Simulation time 113499469 ps
CPU time 6.91 seconds
Started Jul 28 07:18:00 PM PDT 24
Finished Jul 28 07:18:07 PM PDT 24
Peak memory 215700 kb
Host smart-2efe2299-2bff-49d6-8505-6c9efda11e38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111536183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4111536183
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1140696901
Short name T455
Test name
Test status
Simulation time 561015615 ps
CPU time 38.05 seconds
Started Jul 28 07:18:00 PM PDT 24
Finished Jul 28 07:18:38 PM PDT 24
Peak memory 218772 kb
Host smart-3e28c4a6-47d9-4509-b47b-7c3724277d61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140696901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1140696901
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.545527626
Short name T382
Test name
Test status
Simulation time 174902885 ps
CPU time 4.43 seconds
Started Jul 28 07:18:00 PM PDT 24
Finished Jul 28 07:18:04 PM PDT 24
Peak memory 212424 kb
Host smart-551b3f28-0ef4-4232-bdb5-7278172ba804
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545527626 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.545527626
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3140888336
Short name T410
Test name
Test status
Simulation time 85828871 ps
CPU time 4.51 seconds
Started Jul 28 07:18:01 PM PDT 24
Finished Jul 28 07:18:06 PM PDT 24
Peak memory 210556 kb
Host smart-2d2d9dd8-f21e-4372-a9f9-83476d7ba28e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140888336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3140888336
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3470505548
Short name T72
Test name
Test status
Simulation time 1486607860 ps
CPU time 18.39 seconds
Started Jul 28 07:18:01 PM PDT 24
Finished Jul 28 07:18:20 PM PDT 24
Peak memory 210688 kb
Host smart-1533dfde-f99f-45e9-9c1e-394fd9251468
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470505548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3470505548
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3396151963
Short name T96
Test name
Test status
Simulation time 107452830 ps
CPU time 4.33 seconds
Started Jul 28 07:18:00 PM PDT 24
Finished Jul 28 07:18:05 PM PDT 24
Peak memory 218324 kb
Host smart-47d68a58-fb64-4735-b798-6f2ec99f621c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396151963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3396151963
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1556564154
Short name T407
Test name
Test status
Simulation time 829858895 ps
CPU time 7.02 seconds
Started Jul 28 07:18:03 PM PDT 24
Finished Jul 28 07:18:10 PM PDT 24
Peak memory 214452 kb
Host smart-66e8b1f0-0e22-472f-8843-784fa7615a6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556564154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1556564154
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.49749788
Short name T63
Test name
Test status
Simulation time 486179922 ps
CPU time 67.01 seconds
Started Jul 28 07:17:59 PM PDT 24
Finished Jul 28 07:19:07 PM PDT 24
Peak memory 218784 kb
Host smart-04e55b19-c0a2-4253-99fa-f1a1acfd438b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49749788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_int
g_err.49749788
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.601051286
Short name T84
Test name
Test status
Simulation time 136039425 ps
CPU time 4.15 seconds
Started Jul 28 07:17:15 PM PDT 24
Finished Jul 28 07:17:19 PM PDT 24
Peak memory 218712 kb
Host smart-34092cc2-67fc-40d0-9f5c-32f8de265762
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601051286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.601051286
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2595476519
Short name T66
Test name
Test status
Simulation time 88824787 ps
CPU time 4.58 seconds
Started Jul 28 07:17:16 PM PDT 24
Finished Jul 28 07:17:21 PM PDT 24
Peak memory 210608 kb
Host smart-170fbb7a-f310-464e-9819-ff514f72f29a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595476519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2595476519
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.412033970
Short name T458
Test name
Test status
Simulation time 258460812 ps
CPU time 7.85 seconds
Started Jul 28 07:17:16 PM PDT 24
Finished Jul 28 07:17:24 PM PDT 24
Peak memory 218740 kb
Host smart-92e7c857-d204-407f-9625-a447540d5a06
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412033970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.412033970
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4224520537
Short name T435
Test name
Test status
Simulation time 165552810 ps
CPU time 5.2 seconds
Started Jul 28 07:17:22 PM PDT 24
Finished Jul 28 07:17:27 PM PDT 24
Peak memory 218848 kb
Host smart-e9e171d5-03da-49f6-93d7-96e474d42fab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224520537 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4224520537
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1953187697
Short name T68
Test name
Test status
Simulation time 522419064 ps
CPU time 5 seconds
Started Jul 28 07:17:15 PM PDT 24
Finished Jul 28 07:17:20 PM PDT 24
Peak memory 218652 kb
Host smart-9321a26f-9df4-4e79-a8d8-d80dab986c9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953187697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1953187697
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2162479152
Short name T403
Test name
Test status
Simulation time 444697129 ps
CPU time 4.9 seconds
Started Jul 28 07:17:15 PM PDT 24
Finished Jul 28 07:17:20 PM PDT 24
Peak memory 210384 kb
Host smart-0d0b96a4-fccd-43ad-b351-f438a8a26093
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162479152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2162479152
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1394810757
Short name T390
Test name
Test status
Simulation time 467347088 ps
CPU time 4.37 seconds
Started Jul 28 07:17:18 PM PDT 24
Finished Jul 28 07:17:22 PM PDT 24
Peak memory 210448 kb
Host smart-3425fe9a-ef7c-469b-8b9f-40601989ed71
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394810757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1394810757
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.57336098
Short name T416
Test name
Test status
Simulation time 1131866887 ps
CPU time 27.31 seconds
Started Jul 28 07:17:16 PM PDT 24
Finished Jul 28 07:17:44 PM PDT 24
Peak memory 210624 kb
Host smart-8766d7f1-9cce-4d99-ad89-8f7e4337d34b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57336098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pass
thru_mem_tl_intg_err.57336098
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.960432873
Short name T405
Test name
Test status
Simulation time 129240075 ps
CPU time 5.07 seconds
Started Jul 28 07:17:16 PM PDT 24
Finished Jul 28 07:17:21 PM PDT 24
Peak memory 210576 kb
Host smart-18a97d3e-2b1d-403a-9762-f43431045c83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960432873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.960432873
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2726269566
Short name T467
Test name
Test status
Simulation time 498767509 ps
CPU time 7.21 seconds
Started Jul 28 07:17:16 PM PDT 24
Finished Jul 28 07:17:23 PM PDT 24
Peak memory 218860 kb
Host smart-da4bea60-5a8b-4602-8281-bc28ddf7e9d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726269566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2726269566
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3345823387
Short name T111
Test name
Test status
Simulation time 1113598768 ps
CPU time 69.27 seconds
Started Jul 28 07:17:16 PM PDT 24
Finished Jul 28 07:18:25 PM PDT 24
Peak memory 212232 kb
Host smart-b20fb50c-50dc-4701-9971-8b849fac07d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345823387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3345823387
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.115779367
Short name T91
Test name
Test status
Simulation time 257213058 ps
CPU time 5.05 seconds
Started Jul 28 07:17:24 PM PDT 24
Finished Jul 28 07:17:30 PM PDT 24
Peak memory 218696 kb
Host smart-83726f5e-b93d-4e2a-a731-ae1ef6563efe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115779367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.115779367
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2923150130
Short name T437
Test name
Test status
Simulation time 89331636 ps
CPU time 4.27 seconds
Started Jul 28 07:17:18 PM PDT 24
Finished Jul 28 07:17:22 PM PDT 24
Peak memory 210508 kb
Host smart-12790413-9931-4ee9-ada5-5b2eee7c6033
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923150130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2923150130
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3960322267
Short name T411
Test name
Test status
Simulation time 2548084779 ps
CPU time 8.23 seconds
Started Jul 28 07:17:22 PM PDT 24
Finished Jul 28 07:17:30 PM PDT 24
Peak memory 218824 kb
Host smart-9bde8ef8-c4d6-4bb5-9e78-760bbf9b6daf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960322267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3960322267
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2716119326
Short name T398
Test name
Test status
Simulation time 436536923 ps
CPU time 4.45 seconds
Started Jul 28 07:17:24 PM PDT 24
Finished Jul 28 07:17:29 PM PDT 24
Peak memory 218804 kb
Host smart-2a28cb83-e346-4641-ac17-9e7747f444fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716119326 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2716119326
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2314975804
Short name T76
Test name
Test status
Simulation time 333459630 ps
CPU time 4.2 seconds
Started Jul 28 07:17:21 PM PDT 24
Finished Jul 28 07:17:26 PM PDT 24
Peak memory 217412 kb
Host smart-9a8f30a4-9289-4c5d-8fa8-275211d20638
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314975804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2314975804
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3303671602
Short name T441
Test name
Test status
Simulation time 87333459 ps
CPU time 4.19 seconds
Started Jul 28 07:17:19 PM PDT 24
Finished Jul 28 07:17:23 PM PDT 24
Peak memory 210412 kb
Host smart-8c64bb2d-257e-4802-9f61-5b95aa0c911f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303671602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3303671602
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.996653523
Short name T392
Test name
Test status
Simulation time 566726089 ps
CPU time 5.03 seconds
Started Jul 28 07:17:19 PM PDT 24
Finished Jul 28 07:17:24 PM PDT 24
Peak memory 210428 kb
Host smart-6983aa28-4a97-47cb-952b-26579ca6aa01
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996653523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
996653523
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2172409686
Short name T90
Test name
Test status
Simulation time 7676533798 ps
CPU time 27.4 seconds
Started Jul 28 07:17:21 PM PDT 24
Finished Jul 28 07:17:48 PM PDT 24
Peak memory 210788 kb
Host smart-007fed74-85d3-4135-b59e-5003d704aab9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172409686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2172409686
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1345651049
Short name T413
Test name
Test status
Simulation time 129825577 ps
CPU time 5.1 seconds
Started Jul 28 07:17:25 PM PDT 24
Finished Jul 28 07:17:31 PM PDT 24
Peak memory 218748 kb
Host smart-6e958238-5bd1-4f53-b9a4-e5790a28de8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345651049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1345651049
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4112933373
Short name T394
Test name
Test status
Simulation time 260695101 ps
CPU time 8.76 seconds
Started Jul 28 07:17:21 PM PDT 24
Finished Jul 28 07:17:30 PM PDT 24
Peak memory 216912 kb
Host smart-8d671ba3-cba1-41f3-b039-0cb77c628e22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112933373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4112933373
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1403202647
Short name T460
Test name
Test status
Simulation time 265423538 ps
CPU time 38.41 seconds
Started Jul 28 07:17:22 PM PDT 24
Finished Jul 28 07:18:00 PM PDT 24
Peak memory 211148 kb
Host smart-dae95911-aece-479f-bc60-dd6ea61b1183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403202647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1403202647
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2829377613
Short name T431
Test name
Test status
Simulation time 256645384 ps
CPU time 5.22 seconds
Started Jul 28 07:17:29 PM PDT 24
Finished Jul 28 07:17:34 PM PDT 24
Peak memory 218672 kb
Host smart-b1d3deaf-d2d7-498b-9248-97935ccf8c7b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829377613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2829377613
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1253294335
Short name T427
Test name
Test status
Simulation time 335543580 ps
CPU time 4.39 seconds
Started Jul 28 07:17:31 PM PDT 24
Finished Jul 28 07:17:35 PM PDT 24
Peak memory 210524 kb
Host smart-419d9ea3-bab3-4e5e-80d4-0775cf8f9801
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253294335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1253294335
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3557829253
Short name T475
Test name
Test status
Simulation time 923363375 ps
CPU time 8.15 seconds
Started Jul 28 07:17:32 PM PDT 24
Finished Jul 28 07:17:40 PM PDT 24
Peak memory 210460 kb
Host smart-13df8510-5445-4e25-9c4a-c5f34d9e0f99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557829253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3557829253
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3097214941
Short name T387
Test name
Test status
Simulation time 154863125 ps
CPU time 5.72 seconds
Started Jul 28 07:17:32 PM PDT 24
Finished Jul 28 07:17:38 PM PDT 24
Peak memory 218860 kb
Host smart-62566fa8-8e24-4afe-a4ce-ccc7d245bb49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097214941 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3097214941
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3098856475
Short name T102
Test name
Test status
Simulation time 88928314 ps
CPU time 4.27 seconds
Started Jul 28 07:17:33 PM PDT 24
Finished Jul 28 07:17:37 PM PDT 24
Peak memory 217632 kb
Host smart-a7e23635-9b01-40a9-bac7-0cbaf424aafe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098856475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3098856475
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3618693749
Short name T418
Test name
Test status
Simulation time 256974400 ps
CPU time 4.75 seconds
Started Jul 28 07:17:28 PM PDT 24
Finished Jul 28 07:17:33 PM PDT 24
Peak memory 210344 kb
Host smart-1ffa5625-a9e1-4ce6-b3b4-fedc4b3a9a46
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618693749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3618693749
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.903914095
Short name T430
Test name
Test status
Simulation time 116885059 ps
CPU time 4.09 seconds
Started Jul 28 07:17:30 PM PDT 24
Finished Jul 28 07:17:34 PM PDT 24
Peak memory 210392 kb
Host smart-408f2034-9ae9-4acb-a9b3-50bb9619408d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903914095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
903914095
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1626164709
Short name T86
Test name
Test status
Simulation time 821862385 ps
CPU time 32.33 seconds
Started Jul 28 07:17:24 PM PDT 24
Finished Jul 28 07:17:57 PM PDT 24
Peak memory 210660 kb
Host smart-19bf9424-98d0-4d2e-83fb-b50d6a13eca0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626164709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1626164709
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3122390675
Short name T434
Test name
Test status
Simulation time 2230298616 ps
CPU time 7.44 seconds
Started Jul 28 07:17:30 PM PDT 24
Finished Jul 28 07:17:38 PM PDT 24
Peak memory 218876 kb
Host smart-ca891253-f27d-4edf-afb3-2fb29487a587
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122390675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3122390675
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3663425198
Short name T412
Test name
Test status
Simulation time 332903485 ps
CPU time 6.11 seconds
Started Jul 28 07:17:26 PM PDT 24
Finished Jul 28 07:17:32 PM PDT 24
Peak memory 215404 kb
Host smart-cf2383e0-21bc-4a01-a4ba-a4da99fbdb3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663425198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3663425198
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3610428056
Short name T117
Test name
Test status
Simulation time 432557976 ps
CPU time 37.15 seconds
Started Jul 28 07:17:28 PM PDT 24
Finished Jul 28 07:18:05 PM PDT 24
Peak memory 218732 kb
Host smart-4feb5faa-3bdb-4134-a20f-30c293be801f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610428056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3610428056
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2765407767
Short name T442
Test name
Test status
Simulation time 767332219 ps
CPU time 6.12 seconds
Started Jul 28 07:17:32 PM PDT 24
Finished Jul 28 07:17:38 PM PDT 24
Peak memory 218848 kb
Host smart-29400f39-4484-440d-a0a4-79c7817baeb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765407767 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2765407767
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2604061545
Short name T397
Test name
Test status
Simulation time 776817202 ps
CPU time 4.92 seconds
Started Jul 28 07:17:33 PM PDT 24
Finished Jul 28 07:17:38 PM PDT 24
Peak memory 210580 kb
Host smart-11e570c4-8dce-4607-9b92-b5e9e0957e45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604061545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2604061545
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3770232312
Short name T457
Test name
Test status
Simulation time 127646945 ps
CPU time 5.01 seconds
Started Jul 28 07:17:33 PM PDT 24
Finished Jul 28 07:17:38 PM PDT 24
Peak memory 210640 kb
Host smart-27bd53e1-1d63-4e20-8975-f7cf12cdf687
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770232312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3770232312
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.743100588
Short name T463
Test name
Test status
Simulation time 108409949 ps
CPU time 7.46 seconds
Started Jul 28 07:17:29 PM PDT 24
Finished Jul 28 07:17:37 PM PDT 24
Peak memory 218820 kb
Host smart-0b1ebb4a-ff95-4510-9100-f7982c3e94fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743100588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.743100588
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.272195204
Short name T115
Test name
Test status
Simulation time 566553166 ps
CPU time 71.32 seconds
Started Jul 28 07:17:28 PM PDT 24
Finished Jul 28 07:18:40 PM PDT 24
Peak memory 218776 kb
Host smart-ed00cfae-efaf-4608-82c4-57af96beb7a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272195204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.272195204
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1243397841
Short name T389
Test name
Test status
Simulation time 883694585 ps
CPU time 4.99 seconds
Started Jul 28 07:17:36 PM PDT 24
Finished Jul 28 07:17:41 PM PDT 24
Peak memory 214984 kb
Host smart-74ee31a2-8937-42b9-b9d2-f99c6302924c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243397841 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1243397841
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2011519733
Short name T438
Test name
Test status
Simulation time 953599805 ps
CPU time 4.96 seconds
Started Jul 28 07:17:34 PM PDT 24
Finished Jul 28 07:17:39 PM PDT 24
Peak memory 210560 kb
Host smart-5674ff58-a87d-40fc-80c4-8199289dda2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011519733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2011519733
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1182267795
Short name T426
Test name
Test status
Simulation time 2479127179 ps
CPU time 21.93 seconds
Started Jul 28 07:17:29 PM PDT 24
Finished Jul 28 07:17:51 PM PDT 24
Peak memory 210728 kb
Host smart-79d6b3a8-54f6-449c-a04e-5247e3769034
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182267795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1182267795
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2978093427
Short name T101
Test name
Test status
Simulation time 130578084 ps
CPU time 5.07 seconds
Started Jul 28 07:17:36 PM PDT 24
Finished Jul 28 07:17:41 PM PDT 24
Peak memory 210664 kb
Host smart-1c51b2ed-ac40-4470-8169-f3cea0ee8215
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978093427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2978093427
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.540214151
Short name T380
Test name
Test status
Simulation time 89380855 ps
CPU time 7.82 seconds
Started Jul 28 07:17:34 PM PDT 24
Finished Jul 28 07:17:42 PM PDT 24
Peak memory 218844 kb
Host smart-8cceee1f-0c26-4bca-af8b-e1c8790ad7fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540214151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.540214151
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.543136636
Short name T110
Test name
Test status
Simulation time 231104553 ps
CPU time 36.91 seconds
Started Jul 28 07:17:37 PM PDT 24
Finished Jul 28 07:18:14 PM PDT 24
Peak memory 218732 kb
Host smart-c7ceb42b-18a3-49f6-b92e-1c86c4df38ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543136636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.543136636
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2233568697
Short name T450
Test name
Test status
Simulation time 591573924 ps
CPU time 6.17 seconds
Started Jul 28 07:17:40 PM PDT 24
Finished Jul 28 07:17:47 PM PDT 24
Peak memory 218912 kb
Host smart-119bae82-01be-43c1-b5f7-0a58d8e06ece
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233568697 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2233568697
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1798061761
Short name T92
Test name
Test status
Simulation time 129362580 ps
CPU time 5.17 seconds
Started Jul 28 07:17:36 PM PDT 24
Finished Jul 28 07:17:41 PM PDT 24
Peak memory 210528 kb
Host smart-99f0dd5a-45f6-43fc-adf5-1dce624d7be4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798061761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1798061761
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2167344224
Short name T85
Test name
Test status
Simulation time 1123382311 ps
CPU time 27.96 seconds
Started Jul 28 07:17:34 PM PDT 24
Finished Jul 28 07:18:02 PM PDT 24
Peak memory 210672 kb
Host smart-1f8abe60-fd3d-4b9f-9ef2-de79dde32626
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167344224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2167344224
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2251117911
Short name T452
Test name
Test status
Simulation time 179274962 ps
CPU time 4.19 seconds
Started Jul 28 07:17:37 PM PDT 24
Finished Jul 28 07:17:42 PM PDT 24
Peak memory 210636 kb
Host smart-2d3885f2-b2dd-4179-84a9-d21895f0aa75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251117911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2251117911
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3548713936
Short name T466
Test name
Test status
Simulation time 828518769 ps
CPU time 8.21 seconds
Started Jul 28 07:17:34 PM PDT 24
Finished Jul 28 07:17:43 PM PDT 24
Peak memory 218836 kb
Host smart-078c2318-cd39-496b-9cd1-cbffeac82299
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548713936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3548713936
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2725281169
Short name T107
Test name
Test status
Simulation time 271823345 ps
CPU time 68.61 seconds
Started Jul 28 07:17:34 PM PDT 24
Finished Jul 28 07:18:43 PM PDT 24
Peak memory 212248 kb
Host smart-6796b604-9479-46ea-a034-c58f017129e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725281169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2725281169
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1425517849
Short name T384
Test name
Test status
Simulation time 695633549 ps
CPU time 5.91 seconds
Started Jul 28 07:17:43 PM PDT 24
Finished Jul 28 07:17:49 PM PDT 24
Peak memory 215312 kb
Host smart-6bfdb0f4-1226-4faa-868d-0cff1b5ce4dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425517849 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1425517849
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2712739409
Short name T440
Test name
Test status
Simulation time 184389366 ps
CPU time 4.18 seconds
Started Jul 28 07:17:38 PM PDT 24
Finished Jul 28 07:17:43 PM PDT 24
Peak memory 217360 kb
Host smart-80c44d3a-bb4b-4f43-9ebd-10e81e76ab20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712739409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2712739409
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1762411658
Short name T94
Test name
Test status
Simulation time 6221572356 ps
CPU time 47.22 seconds
Started Jul 28 07:17:40 PM PDT 24
Finished Jul 28 07:18:27 PM PDT 24
Peak memory 211116 kb
Host smart-652a7c1b-8df6-435f-ac67-5918a2e35ae7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762411658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1762411658
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3328232502
Short name T465
Test name
Test status
Simulation time 132357388 ps
CPU time 4.92 seconds
Started Jul 28 07:17:42 PM PDT 24
Finished Jul 28 07:17:47 PM PDT 24
Peak memory 218812 kb
Host smart-f2fe3291-bace-45a8-92fe-bdce68751877
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328232502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3328232502
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3414217028
Short name T447
Test name
Test status
Simulation time 377885175 ps
CPU time 7.99 seconds
Started Jul 28 07:17:39 PM PDT 24
Finished Jul 28 07:17:47 PM PDT 24
Peak memory 218876 kb
Host smart-821426e9-dbdd-44e8-91f4-466f016460b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414217028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3414217028
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.60416286
Short name T106
Test name
Test status
Simulation time 359039683 ps
CPU time 72.08 seconds
Started Jul 28 07:17:37 PM PDT 24
Finished Jul 28 07:18:49 PM PDT 24
Peak memory 212228 kb
Host smart-04f155d1-a4c3-4f4e-80f2-1e89ea4e2909
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60416286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg
_err.60416286
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.630745186
Short name T456
Test name
Test status
Simulation time 264133940 ps
CPU time 5.28 seconds
Started Jul 28 07:17:42 PM PDT 24
Finished Jul 28 07:17:47 PM PDT 24
Peak memory 214408 kb
Host smart-6b55a03f-d2bd-47f3-9828-e60153729994
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630745186 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.630745186
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.753063031
Short name T462
Test name
Test status
Simulation time 87152296 ps
CPU time 4.2 seconds
Started Jul 28 07:17:42 PM PDT 24
Finished Jul 28 07:17:46 PM PDT 24
Peak memory 218716 kb
Host smart-eb1eadde-94b3-4531-a36c-294c27c4ae4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753063031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.753063031
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1363661458
Short name T70
Test name
Test status
Simulation time 554165979 ps
CPU time 21.94 seconds
Started Jul 28 07:17:42 PM PDT 24
Finished Jul 28 07:18:04 PM PDT 24
Peak memory 210692 kb
Host smart-4e3aedc2-6f2d-43f0-814b-cf71adae11ad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363661458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1363661458
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.424149955
Short name T425
Test name
Test status
Simulation time 86471178 ps
CPU time 4.54 seconds
Started Jul 28 07:17:44 PM PDT 24
Finished Jul 28 07:17:49 PM PDT 24
Peak memory 210648 kb
Host smart-df11eef8-eaab-49c1-adfc-f22890b9aa17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424149955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.424149955
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.990514197
Short name T391
Test name
Test status
Simulation time 479136624 ps
CPU time 9.05 seconds
Started Jul 28 07:17:44 PM PDT 24
Finished Jul 28 07:17:53 PM PDT 24
Peak memory 218848 kb
Host smart-afe0fc08-41d6-4bd5-b555-c435aefa662c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990514197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.990514197
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.861955130
Short name T472
Test name
Test status
Simulation time 318579697 ps
CPU time 36.25 seconds
Started Jul 28 07:17:44 PM PDT 24
Finished Jul 28 07:18:21 PM PDT 24
Peak memory 211244 kb
Host smart-9c88ac7e-bcf3-4eef-a819-7cbd20cb5aa1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861955130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.861955130
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.527121910
Short name T134
Test name
Test status
Simulation time 171673884 ps
CPU time 4.24 seconds
Started Jul 28 07:23:47 PM PDT 24
Finished Jul 28 07:23:51 PM PDT 24
Peak memory 211756 kb
Host smart-c6b6440e-8ba1-4372-8c55-034c36f9d14d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527121910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.527121910
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3557747514
Short name T205
Test name
Test status
Simulation time 1557939497 ps
CPU time 78.34 seconds
Started Jul 28 07:23:45 PM PDT 24
Finished Jul 28 07:25:03 PM PDT 24
Peak memory 237220 kb
Host smart-18f15043-446c-4582-bc6f-1966c9cbe993
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557747514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3557747514
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.209715974
Short name T314
Test name
Test status
Simulation time 375738676 ps
CPU time 5.84 seconds
Started Jul 28 07:23:43 PM PDT 24
Finished Jul 28 07:23:49 PM PDT 24
Peak memory 211936 kb
Host smart-6a245532-affa-4c9d-8862-5da46e813634
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=209715974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.209715974
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.627928738
Short name T24
Test name
Test status
Simulation time 333932646 ps
CPU time 104.62 seconds
Started Jul 28 07:23:48 PM PDT 24
Finished Jul 28 07:25:32 PM PDT 24
Peak memory 237024 kb
Host smart-7b4cbe5e-ca65-45cf-89bc-2fe2b6900fd1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627928738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.627928738
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3561326785
Short name T273
Test name
Test status
Simulation time 187215264 ps
CPU time 10.12 seconds
Started Jul 28 07:23:43 PM PDT 24
Finished Jul 28 07:23:53 PM PDT 24
Peak memory 213172 kb
Host smart-7ac3483b-49f1-4937-8238-b1528b006388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561326785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3561326785
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3070849790
Short name T182
Test name
Test status
Simulation time 1086912842 ps
CPU time 25.66 seconds
Started Jul 28 07:23:44 PM PDT 24
Finished Jul 28 07:24:10 PM PDT 24
Peak memory 214952 kb
Host smart-cfc9e0b1-c05f-419b-9e4a-0e7d8154fa85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070849790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3070849790
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2137890538
Short name T170
Test name
Test status
Simulation time 521607818 ps
CPU time 5.08 seconds
Started Jul 28 07:23:50 PM PDT 24
Finished Jul 28 07:23:56 PM PDT 24
Peak memory 211800 kb
Host smart-d1f22368-b042-4c77-8be6-1c343e2f3542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137890538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2137890538
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3843285171
Short name T303
Test name
Test status
Simulation time 12839109612 ps
CPU time 151.62 seconds
Started Jul 28 07:23:49 PM PDT 24
Finished Jul 28 07:26:21 PM PDT 24
Peak memory 237944 kb
Host smart-7e07bef0-451e-4b6b-bb4e-7338f4fd123b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843285171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3843285171
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2830838118
Short name T142
Test name
Test status
Simulation time 4133262598 ps
CPU time 11.35 seconds
Started Jul 28 07:23:49 PM PDT 24
Finished Jul 28 07:24:01 PM PDT 24
Peak memory 212860 kb
Host smart-f0bcaa20-86bf-4871-aa56-dc2b1f6fbe7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830838118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2830838118
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.365591134
Short name T200
Test name
Test status
Simulation time 101482513 ps
CPU time 5.71 seconds
Started Jul 28 07:23:51 PM PDT 24
Finished Jul 28 07:23:57 PM PDT 24
Peak memory 211952 kb
Host smart-e513e524-0e7b-4d66-a9ae-1aed306447c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=365591134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.365591134
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3627156499
Short name T29
Test name
Test status
Simulation time 411580494 ps
CPU time 53.32 seconds
Started Jul 28 07:23:51 PM PDT 24
Finished Jul 28 07:24:44 PM PDT 24
Peak memory 237576 kb
Host smart-3efa5a51-eeae-442e-b76e-51dcd29a0b47
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627156499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3627156499
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3679965359
Short name T312
Test name
Test status
Simulation time 949985807 ps
CPU time 12.21 seconds
Started Jul 28 07:23:47 PM PDT 24
Finished Jul 28 07:23:59 PM PDT 24
Peak memory 214160 kb
Host smart-431366cf-0036-4bdf-bb93-b8fc19cea109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679965359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3679965359
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.5673689
Short name T204
Test name
Test status
Simulation time 2442349052 ps
CPU time 33.05 seconds
Started Jul 28 07:23:46 PM PDT 24
Finished Jul 28 07:24:19 PM PDT 24
Peak memory 217240 kb
Host smart-d88bef3b-e913-47f5-9294-64c6abfa49f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5673689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.rom_ctrl_stress_all.5673689
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2672300023
Short name T218
Test name
Test status
Simulation time 13271325135 ps
CPU time 619.21 seconds
Started Jul 28 07:23:48 PM PDT 24
Finished Jul 28 07:34:07 PM PDT 24
Peak memory 221768 kb
Host smart-cb141464-b713-4de5-9e80-3778d7f3a9d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672300023 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.2672300023
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1360638293
Short name T145
Test name
Test status
Simulation time 496856240 ps
CPU time 5.09 seconds
Started Jul 28 07:24:05 PM PDT 24
Finished Jul 28 07:24:10 PM PDT 24
Peak memory 211844 kb
Host smart-4d662031-1bb3-413b-a457-a9e1e0cac66a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360638293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1360638293
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2651950055
Short name T323
Test name
Test status
Simulation time 13931768776 ps
CPU time 153.73 seconds
Started Jul 28 07:24:09 PM PDT 24
Finished Jul 28 07:26:43 PM PDT 24
Peak memory 226132 kb
Host smart-948c16d6-a1d9-40cc-8019-c5888c45ec4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651950055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2651950055
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.648227035
Short name T237
Test name
Test status
Simulation time 1001258182 ps
CPU time 11.24 seconds
Started Jul 28 07:24:05 PM PDT 24
Finished Jul 28 07:24:16 PM PDT 24
Peak memory 212644 kb
Host smart-aa5e36bc-3d93-4d9f-a12e-7b85b218cce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648227035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.648227035
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.897106208
Short name T140
Test name
Test status
Simulation time 213161061 ps
CPU time 5.42 seconds
Started Jul 28 07:24:05 PM PDT 24
Finished Jul 28 07:24:11 PM PDT 24
Peak memory 211892 kb
Host smart-00236268-a3a3-46ec-9760-9a3c184f3e65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=897106208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.897106208
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2317679401
Short name T82
Test name
Test status
Simulation time 946193033 ps
CPU time 10.25 seconds
Started Jul 28 07:24:07 PM PDT 24
Finished Jul 28 07:24:17 PM PDT 24
Peak memory 214572 kb
Host smart-eb046ffb-350d-4052-b5e2-b460e995a721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317679401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2317679401
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3636640179
Short name T18
Test name
Test status
Simulation time 2747530464 ps
CPU time 29.8 seconds
Started Jul 28 07:24:07 PM PDT 24
Finished Jul 28 07:24:37 PM PDT 24
Peak memory 217180 kb
Host smart-69e7a4c9-425d-44b5-9d62-1501ec050292
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636640179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3636640179
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.891445708
Short name T289
Test name
Test status
Simulation time 89925074 ps
CPU time 4.32 seconds
Started Jul 28 07:24:10 PM PDT 24
Finished Jul 28 07:24:14 PM PDT 24
Peak memory 211840 kb
Host smart-c9fe4ed9-669c-4c44-ab4d-5a5348908f24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891445708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.891445708
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1896487776
Short name T30
Test name
Test status
Simulation time 16851196164 ps
CPU time 169.4 seconds
Started Jul 28 07:24:07 PM PDT 24
Finished Jul 28 07:26:57 PM PDT 24
Peak memory 214012 kb
Host smart-69209fa1-c69b-4e0c-938f-5f31584ae3f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896487776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1896487776
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3659314075
Short name T180
Test name
Test status
Simulation time 334770887 ps
CPU time 9.33 seconds
Started Jul 28 07:24:07 PM PDT 24
Finished Jul 28 07:24:17 PM PDT 24
Peak memory 212612 kb
Host smart-545e340f-26a8-43f5-9be4-901ab6a8c8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659314075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3659314075
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.6451753
Short name T8
Test name
Test status
Simulation time 366651441 ps
CPU time 6.34 seconds
Started Jul 28 07:24:11 PM PDT 24
Finished Jul 28 07:24:17 PM PDT 24
Peak memory 211948 kb
Host smart-b6b7661d-9a3b-4068-bf5b-04060e5aa598
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=6451753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.6451753
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3333296150
Short name T334
Test name
Test status
Simulation time 180974753 ps
CPU time 10.03 seconds
Started Jul 28 07:24:07 PM PDT 24
Finished Jul 28 07:24:17 PM PDT 24
Peak memory 213612 kb
Host smart-9cd41900-8328-4f91-bf4e-8f2edcc92634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333296150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3333296150
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3004015645
Short name T282
Test name
Test status
Simulation time 2041724102 ps
CPU time 36.73 seconds
Started Jul 28 07:24:04 PM PDT 24
Finished Jul 28 07:24:41 PM PDT 24
Peak memory 219744 kb
Host smart-8189397a-b87b-4813-b000-2c1c289299c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004015645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3004015645
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3584145287
Short name T25
Test name
Test status
Simulation time 175949359 ps
CPU time 4.21 seconds
Started Jul 28 07:24:11 PM PDT 24
Finished Jul 28 07:24:15 PM PDT 24
Peak memory 211792 kb
Host smart-b006ec50-eb79-47e7-947e-b3054805fc1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584145287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3584145287
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2701638713
Short name T322
Test name
Test status
Simulation time 1443827931 ps
CPU time 79.2 seconds
Started Jul 28 07:24:12 PM PDT 24
Finished Jul 28 07:25:31 PM PDT 24
Peak memory 237160 kb
Host smart-d4b26f56-838b-41bc-925c-f3951f108c1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701638713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2701638713
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2490757243
Short name T370
Test name
Test status
Simulation time 176592947 ps
CPU time 9.59 seconds
Started Jul 28 07:24:15 PM PDT 24
Finished Jul 28 07:24:24 PM PDT 24
Peak memory 212876 kb
Host smart-34481ae5-161a-40ea-aef2-8e1543a3b50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490757243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2490757243
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.542390033
Short name T225
Test name
Test status
Simulation time 501930646 ps
CPU time 6.71 seconds
Started Jul 28 07:24:13 PM PDT 24
Finished Jul 28 07:24:20 PM PDT 24
Peak memory 211900 kb
Host smart-2cc50040-2338-4096-8b5a-9a4ce7016079
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=542390033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.542390033
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2357213624
Short name T131
Test name
Test status
Simulation time 188438672 ps
CPU time 10.14 seconds
Started Jul 28 07:24:10 PM PDT 24
Finished Jul 28 07:24:20 PM PDT 24
Peak memory 214436 kb
Host smart-f4708d4b-0f7c-4c51-84ce-76b65832e375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357213624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2357213624
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.134221219
Short name T193
Test name
Test status
Simulation time 6487719021 ps
CPU time 49.41 seconds
Started Jul 28 07:24:09 PM PDT 24
Finished Jul 28 07:24:58 PM PDT 24
Peak memory 219844 kb
Host smart-3a60bf78-9ae1-4dd0-8cf5-366485d69d44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134221219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.134221219
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.549959015
Short name T1
Test name
Test status
Simulation time 132327996 ps
CPU time 5.05 seconds
Started Jul 28 07:24:09 PM PDT 24
Finished Jul 28 07:24:14 PM PDT 24
Peak memory 211748 kb
Host smart-0a5e1341-5712-48bc-a8db-8109d66dd2cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549959015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.549959015
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2549725686
Short name T265
Test name
Test status
Simulation time 190887343 ps
CPU time 9.85 seconds
Started Jul 28 07:24:13 PM PDT 24
Finished Jul 28 07:24:23 PM PDT 24
Peak memory 212668 kb
Host smart-7de94c84-1803-4ebb-8364-058197def7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549725686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2549725686
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1399970826
Short name T56
Test name
Test status
Simulation time 664214341 ps
CPU time 6.74 seconds
Started Jul 28 07:24:14 PM PDT 24
Finished Jul 28 07:24:21 PM PDT 24
Peak memory 211932 kb
Host smart-8e97d587-f84f-4058-9f68-51f3e6be87f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1399970826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1399970826
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3568688946
Short name T46
Test name
Test status
Simulation time 1097287970 ps
CPU time 11.9 seconds
Started Jul 28 07:24:10 PM PDT 24
Finished Jul 28 07:24:22 PM PDT 24
Peak memory 214256 kb
Host smart-f39d23e0-1d7a-4cc5-af72-bc731862467b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568688946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3568688946
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1699966498
Short name T281
Test name
Test status
Simulation time 461994619 ps
CPU time 20.64 seconds
Started Jul 28 07:24:15 PM PDT 24
Finished Jul 28 07:24:36 PM PDT 24
Peak memory 214564 kb
Host smart-e3ef887b-fe14-476e-a0d6-9533881cf2ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699966498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1699966498
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1691618303
Short name T365
Test name
Test status
Simulation time 89697483 ps
CPU time 4.39 seconds
Started Jul 28 07:24:13 PM PDT 24
Finished Jul 28 07:24:17 PM PDT 24
Peak memory 211812 kb
Host smart-723b1442-a015-4700-8ae1-6ea2bf1118c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691618303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1691618303
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2719588391
Short name T153
Test name
Test status
Simulation time 5109325724 ps
CPU time 86.95 seconds
Started Jul 28 07:24:09 PM PDT 24
Finished Jul 28 07:25:36 PM PDT 24
Peak memory 238256 kb
Host smart-abd2cbf3-5c80-4ac0-8bd9-45b68aaa1291
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719588391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2719588391
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1545501533
Short name T214
Test name
Test status
Simulation time 1040238712 ps
CPU time 11.36 seconds
Started Jul 28 07:24:17 PM PDT 24
Finished Jul 28 07:24:29 PM PDT 24
Peak memory 212864 kb
Host smart-06d1020d-4613-415e-ac20-329e07030775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545501533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1545501533
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1428668257
Short name T226
Test name
Test status
Simulation time 98956839 ps
CPU time 5.64 seconds
Started Jul 28 07:24:15 PM PDT 24
Finished Jul 28 07:24:21 PM PDT 24
Peak memory 211904 kb
Host smart-75000a29-85a0-42c4-945f-3162c5279d6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1428668257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1428668257
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3176492168
Short name T279
Test name
Test status
Simulation time 942424869 ps
CPU time 11.64 seconds
Started Jul 28 07:24:15 PM PDT 24
Finished Jul 28 07:24:27 PM PDT 24
Peak memory 214516 kb
Host smart-90f995d4-cce4-42c0-abab-fb2fc8aea4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176492168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3176492168
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3587237066
Short name T223
Test name
Test status
Simulation time 930026608 ps
CPU time 42.39 seconds
Started Jul 28 07:24:11 PM PDT 24
Finished Jul 28 07:24:53 PM PDT 24
Peak memory 219860 kb
Host smart-f4cbdb41-8501-4379-ad38-0f297109adc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587237066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3587237066
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2035933489
Short name T202
Test name
Test status
Simulation time 830249124 ps
CPU time 4.26 seconds
Started Jul 28 07:24:13 PM PDT 24
Finished Jul 28 07:24:18 PM PDT 24
Peak memory 211792 kb
Host smart-82a75116-9bc6-431f-b919-3bd30e9ad1ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035933489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2035933489
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3318800909
Short name T298
Test name
Test status
Simulation time 8052515073 ps
CPU time 74.53 seconds
Started Jul 28 07:24:15 PM PDT 24
Finished Jul 28 07:25:30 PM PDT 24
Peak memory 214128 kb
Host smart-487cbee0-3e9a-4aa1-b2d9-4483394378b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318800909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3318800909
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.937387118
Short name T212
Test name
Test status
Simulation time 1180824531 ps
CPU time 11.38 seconds
Started Jul 28 07:24:13 PM PDT 24
Finished Jul 28 07:24:25 PM PDT 24
Peak memory 212736 kb
Host smart-d34bd919-057b-4916-af0c-9f3281300fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937387118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.937387118
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1643718879
Short name T338
Test name
Test status
Simulation time 142644260 ps
CPU time 6.44 seconds
Started Jul 28 07:24:14 PM PDT 24
Finished Jul 28 07:24:20 PM PDT 24
Peak memory 211936 kb
Host smart-8e221737-913f-4b6e-8b38-846c5b8b8688
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1643718879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1643718879
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3742862571
Short name T78
Test name
Test status
Simulation time 267658142 ps
CPU time 12.47 seconds
Started Jul 28 07:24:15 PM PDT 24
Finished Jul 28 07:24:28 PM PDT 24
Peak memory 214760 kb
Host smart-0f23c25c-bd39-472c-bdd1-c8ebf5d5fe3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742862571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3742862571
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2143089683
Short name T181
Test name
Test status
Simulation time 409700142 ps
CPU time 20.12 seconds
Started Jul 28 07:24:14 PM PDT 24
Finished Jul 28 07:24:34 PM PDT 24
Peak memory 216288 kb
Host smart-adf6312d-dfdd-4ba0-ae4b-41761beba459
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143089683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2143089683
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3246448266
Short name T123
Test name
Test status
Simulation time 500713012 ps
CPU time 5.2 seconds
Started Jul 28 07:24:20 PM PDT 24
Finished Jul 28 07:24:25 PM PDT 24
Peak memory 211844 kb
Host smart-a604e553-5cc1-41d4-87fb-6ace2c08f9c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246448266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3246448266
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3445721789
Short name T42
Test name
Test status
Simulation time 3611856699 ps
CPU time 124.45 seconds
Started Jul 28 07:24:21 PM PDT 24
Finished Jul 28 07:26:25 PM PDT 24
Peak memory 234124 kb
Host smart-e9356793-5dc1-474f-8045-02afa50cb6e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445721789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3445721789
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3944233534
Short name T27
Test name
Test status
Simulation time 511361047 ps
CPU time 11.03 seconds
Started Jul 28 07:24:17 PM PDT 24
Finished Jul 28 07:24:29 PM PDT 24
Peak memory 212812 kb
Host smart-5be03b14-5e5f-41bf-a607-53b8b702db9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944233534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3944233534
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2410099390
Short name T313
Test name
Test status
Simulation time 213619549 ps
CPU time 6.57 seconds
Started Jul 28 07:24:15 PM PDT 24
Finished Jul 28 07:24:21 PM PDT 24
Peak memory 211916 kb
Host smart-fbfc4e63-38c7-4ab6-9bf2-e2dbfd62459f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2410099390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2410099390
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2553856729
Short name T210
Test name
Test status
Simulation time 1061608252 ps
CPU time 11.41 seconds
Started Jul 28 07:24:15 PM PDT 24
Finished Jul 28 07:24:26 PM PDT 24
Peak memory 214020 kb
Host smart-595e7fd1-fc91-42fa-a26b-ae7097f3cddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553856729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2553856729
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1121962297
Short name T240
Test name
Test status
Simulation time 1030320043 ps
CPU time 7.87 seconds
Started Jul 28 07:24:14 PM PDT 24
Finished Jul 28 07:24:22 PM PDT 24
Peak memory 211888 kb
Host smart-ce0ba4f4-bdd7-40f2-9558-fb1566b2ce13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121962297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1121962297
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2047202335
Short name T368
Test name
Test status
Simulation time 333969938 ps
CPU time 4.24 seconds
Started Jul 28 07:24:19 PM PDT 24
Finished Jul 28 07:24:23 PM PDT 24
Peak memory 211788 kb
Host smart-99492385-c16c-40c2-89e0-ad9577bf6fb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047202335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2047202335
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1049036945
Short name T328
Test name
Test status
Simulation time 3448521067 ps
CPU time 121.93 seconds
Started Jul 28 07:24:18 PM PDT 24
Finished Jul 28 07:26:20 PM PDT 24
Peak memory 238216 kb
Host smart-27606852-db24-46bb-9f80-424d36a6fb1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049036945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1049036945
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.636382845
Short name T379
Test name
Test status
Simulation time 173994577 ps
CPU time 9.53 seconds
Started Jul 28 07:24:18 PM PDT 24
Finished Jul 28 07:24:28 PM PDT 24
Peak memory 212620 kb
Host smart-3c74175b-f671-4b51-9a65-5e1340ac5d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636382845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.636382845
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1599461722
Short name T125
Test name
Test status
Simulation time 521016384 ps
CPU time 9.17 seconds
Started Jul 28 07:24:19 PM PDT 24
Finished Jul 28 07:24:28 PM PDT 24
Peak memory 211912 kb
Host smart-bb0e1589-626c-4d71-b119-1b86c449fe91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1599461722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1599461722
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.4087681864
Short name T168
Test name
Test status
Simulation time 941179765 ps
CPU time 12.23 seconds
Started Jul 28 07:24:20 PM PDT 24
Finished Jul 28 07:24:32 PM PDT 24
Peak memory 213072 kb
Host smart-f1587511-0fbf-4e60-80f2-45c68434e1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087681864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.4087681864
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1009595111
Short name T19
Test name
Test status
Simulation time 4969080926 ps
CPU time 23.59 seconds
Started Jul 28 07:24:15 PM PDT 24
Finished Jul 28 07:24:39 PM PDT 24
Peak memory 216316 kb
Host smart-070b1640-3a58-4b02-9c5f-b2d824293d10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009595111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1009595111
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1048239311
Short name T161
Test name
Test status
Simulation time 132721795 ps
CPU time 5.24 seconds
Started Jul 28 07:24:27 PM PDT 24
Finished Jul 28 07:24:32 PM PDT 24
Peak memory 211772 kb
Host smart-cbd342e0-05bc-4f4f-a56f-779f518a68d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048239311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1048239311
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1254604340
Short name T349
Test name
Test status
Simulation time 2526778969 ps
CPU time 118.29 seconds
Started Jul 28 07:24:19 PM PDT 24
Finished Jul 28 07:26:17 PM PDT 24
Peak memory 229020 kb
Host smart-3e34a866-0218-4ab2-939f-e5e9ed38013a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254604340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1254604340
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.4076743601
Short name T220
Test name
Test status
Simulation time 322466195 ps
CPU time 9.65 seconds
Started Jul 28 07:24:22 PM PDT 24
Finished Jul 28 07:24:32 PM PDT 24
Peak memory 212612 kb
Host smart-e0e01e9b-d707-499d-9c72-60451bfaeb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076743601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.4076743601
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.233059480
Short name T317
Test name
Test status
Simulation time 559355151 ps
CPU time 6.44 seconds
Started Jul 28 07:24:19 PM PDT 24
Finished Jul 28 07:24:25 PM PDT 24
Peak memory 211896 kb
Host smart-014bf200-d646-40a7-86ce-082fbd4794e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=233059480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.233059480
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1320619511
Short name T139
Test name
Test status
Simulation time 1029021007 ps
CPU time 11.43 seconds
Started Jul 28 07:24:20 PM PDT 24
Finished Jul 28 07:24:31 PM PDT 24
Peak memory 213488 kb
Host smart-5a99f132-dedb-4473-afdf-7f76a8fb7da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320619511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1320619511
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2834214836
Short name T350
Test name
Test status
Simulation time 264917847 ps
CPU time 7.01 seconds
Started Jul 28 07:24:20 PM PDT 24
Finished Jul 28 07:24:27 PM PDT 24
Peak memory 211752 kb
Host smart-a830fede-17dd-46c9-a3b9-cd8d85bd69cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834214836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2834214836
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2196311132
Short name T250
Test name
Test status
Simulation time 39438375457 ps
CPU time 9053.2 seconds
Started Jul 28 07:24:21 PM PDT 24
Finished Jul 28 09:55:15 PM PDT 24
Peak memory 234140 kb
Host smart-781b1689-e61d-40d5-ad6b-b92aef5f9055
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196311132 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2196311132
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.409797664
Short name T269
Test name
Test status
Simulation time 128350931 ps
CPU time 5.09 seconds
Started Jul 28 07:24:22 PM PDT 24
Finished Jul 28 07:24:27 PM PDT 24
Peak memory 211796 kb
Host smart-a11465d9-b8d6-4636-867d-e1e8b062e83b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409797664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.409797664
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3772223521
Short name T319
Test name
Test status
Simulation time 6119207338 ps
CPU time 82.31 seconds
Started Jul 28 07:24:22 PM PDT 24
Finished Jul 28 07:25:45 PM PDT 24
Peak memory 238328 kb
Host smart-7bc1792c-8ab3-4219-96b7-b5c8046757a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772223521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3772223521
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3358563726
Short name T347
Test name
Test status
Simulation time 995625997 ps
CPU time 11.33 seconds
Started Jul 28 07:24:23 PM PDT 24
Finished Jul 28 07:24:34 PM PDT 24
Peak memory 212668 kb
Host smart-ffd88d29-c19b-42ef-a526-52acb1124e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358563726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3358563726
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1801462182
Short name T276
Test name
Test status
Simulation time 553772520 ps
CPU time 6.54 seconds
Started Jul 28 07:24:28 PM PDT 24
Finished Jul 28 07:24:35 PM PDT 24
Peak memory 211904 kb
Host smart-03698976-b3cc-4a9d-909d-70c3f7ebd259
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1801462182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1801462182
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.530097843
Short name T292
Test name
Test status
Simulation time 2001742896 ps
CPU time 18.53 seconds
Started Jul 28 07:24:24 PM PDT 24
Finished Jul 28 07:24:43 PM PDT 24
Peak memory 212832 kb
Host smart-714e93ec-64da-4551-95fc-6748f02ae222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530097843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.530097843
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.683585396
Short name T288
Test name
Test status
Simulation time 275860478 ps
CPU time 14.45 seconds
Started Jul 28 07:24:27 PM PDT 24
Finished Jul 28 07:24:42 PM PDT 24
Peak memory 214148 kb
Host smart-212d4555-9307-48ad-b7db-ea2c377bdfd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683585396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.683585396
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2644475503
Short name T177
Test name
Test status
Simulation time 522211632 ps
CPU time 5.11 seconds
Started Jul 28 07:23:50 PM PDT 24
Finished Jul 28 07:23:55 PM PDT 24
Peak memory 211820 kb
Host smart-f25ee239-5853-4e41-a744-c562c1b1f6a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644475503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2644475503
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2923148381
Short name T321
Test name
Test status
Simulation time 13315902874 ps
CPU time 159.99 seconds
Started Jul 28 07:23:49 PM PDT 24
Finished Jul 28 07:26:29 PM PDT 24
Peak memory 213112 kb
Host smart-1ddfe3e6-ebb2-46c6-be91-c8c837b11d8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923148381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2923148381
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2680662761
Short name T235
Test name
Test status
Simulation time 779292731 ps
CPU time 11.17 seconds
Started Jul 28 07:23:49 PM PDT 24
Finished Jul 28 07:24:00 PM PDT 24
Peak memory 213052 kb
Host smart-6cf5e663-04ec-4dd0-82a2-edd9829b4764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680662761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2680662761
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2098317108
Short name T342
Test name
Test status
Simulation time 270118485 ps
CPU time 6.07 seconds
Started Jul 28 07:23:52 PM PDT 24
Finished Jul 28 07:23:58 PM PDT 24
Peak memory 211932 kb
Host smart-743a8d77-0a74-406d-84db-8f57e99c9c3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2098317108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2098317108
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3011535058
Short name T28
Test name
Test status
Simulation time 617991432 ps
CPU time 103.15 seconds
Started Jul 28 07:23:48 PM PDT 24
Finished Jul 28 07:25:32 PM PDT 24
Peak memory 240140 kb
Host smart-403434a7-5750-4d08-8ebf-76d1f14d28d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011535058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3011535058
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2730242600
Short name T2
Test name
Test status
Simulation time 183591583 ps
CPU time 10.15 seconds
Started Jul 28 07:23:48 PM PDT 24
Finished Jul 28 07:23:59 PM PDT 24
Peak memory 214560 kb
Host smart-e85f219e-5ed5-4bb1-9c1b-a148a06e1d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730242600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2730242600
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.477406984
Short name T377
Test name
Test status
Simulation time 598406286 ps
CPU time 26.91 seconds
Started Jul 28 07:23:49 PM PDT 24
Finished Jul 28 07:24:16 PM PDT 24
Peak memory 217212 kb
Host smart-22381c65-0671-49aa-a240-47c47de2fc7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477406984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.477406984
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1489880924
Short name T16
Test name
Test status
Simulation time 250432230881 ps
CPU time 4711.97 seconds
Started Jul 28 07:23:49 PM PDT 24
Finished Jul 28 08:42:22 PM PDT 24
Peak memory 248632 kb
Host smart-9b999991-54a5-4b33-b901-922cdb6c2148
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489880924 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1489880924
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2368570624
Short name T129
Test name
Test status
Simulation time 516038449 ps
CPU time 5.01 seconds
Started Jul 28 07:24:23 PM PDT 24
Finished Jul 28 07:24:28 PM PDT 24
Peak memory 211800 kb
Host smart-82ef881b-ccfc-4a0a-91cf-bc8a9cf5b03c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368570624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2368570624
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3575350652
Short name T249
Test name
Test status
Simulation time 2267762368 ps
CPU time 110.64 seconds
Started Jul 28 07:24:21 PM PDT 24
Finished Jul 28 07:26:11 PM PDT 24
Peak memory 214132 kb
Host smart-a4b64d33-5c28-4763-915c-c3384a2bd360
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575350652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3575350652
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2865195492
Short name T256
Test name
Test status
Simulation time 250708907 ps
CPU time 11.21 seconds
Started Jul 28 07:24:21 PM PDT 24
Finished Jul 28 07:24:32 PM PDT 24
Peak memory 212660 kb
Host smart-cdea3685-6130-4bf5-87f8-5bd69e3a23ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865195492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2865195492
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3278930396
Short name T360
Test name
Test status
Simulation time 197509099 ps
CPU time 6.42 seconds
Started Jul 28 07:24:21 PM PDT 24
Finished Jul 28 07:24:28 PM PDT 24
Peak memory 211892 kb
Host smart-7fdec902-4782-48b5-b6cf-ad80fc66a09f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3278930396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3278930396
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.110311879
Short name T207
Test name
Test status
Simulation time 271467822 ps
CPU time 11.86 seconds
Started Jul 28 07:24:20 PM PDT 24
Finished Jul 28 07:24:31 PM PDT 24
Peak memory 213272 kb
Host smart-3127f59d-dd3f-46e4-831a-f01b3cb5ad39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110311879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.110311879
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.4132175534
Short name T345
Test name
Test status
Simulation time 334610641 ps
CPU time 16.1 seconds
Started Jul 28 07:24:22 PM PDT 24
Finished Jul 28 07:24:38 PM PDT 24
Peak memory 214448 kb
Host smart-a185ad34-7b5c-47a4-b6e5-9ebfec431849
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132175534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.4132175534
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.4205594906
Short name T51
Test name
Test status
Simulation time 56185503131 ps
CPU time 2058.95 seconds
Started Jul 28 07:24:22 PM PDT 24
Finished Jul 28 07:58:41 PM PDT 24
Peak memory 237380 kb
Host smart-56ad20f0-e602-4443-8427-6fe037ae6c52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205594906 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.4205594906
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.6708939
Short name T221
Test name
Test status
Simulation time 87434119 ps
CPU time 4.3 seconds
Started Jul 28 07:24:28 PM PDT 24
Finished Jul 28 07:24:33 PM PDT 24
Peak memory 211812 kb
Host smart-73fe5c84-e53a-4cdf-97b1-96b8765a1953
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6708939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.6708939
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2631247536
Short name T38
Test name
Test status
Simulation time 1668939024 ps
CPU time 112.46 seconds
Started Jul 28 07:24:28 PM PDT 24
Finished Jul 28 07:26:20 PM PDT 24
Peak memory 228672 kb
Host smart-140a2944-0cfb-4ed5-bc9d-371dca00ea32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631247536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2631247536
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2297668982
Short name T378
Test name
Test status
Simulation time 98597109 ps
CPU time 5.68 seconds
Started Jul 28 07:24:28 PM PDT 24
Finished Jul 28 07:24:33 PM PDT 24
Peak memory 211904 kb
Host smart-9be081b4-2e6f-4385-922b-5c9dc0338ff6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2297668982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2297668982
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.4284193937
Short name T307
Test name
Test status
Simulation time 755642703 ps
CPU time 10.31 seconds
Started Jul 28 07:24:23 PM PDT 24
Finished Jul 28 07:24:33 PM PDT 24
Peak memory 213944 kb
Host smart-07ed3339-94dd-4a29-8f94-519c7face525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284193937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.4284193937
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3028946964
Short name T244
Test name
Test status
Simulation time 459865154 ps
CPU time 20.45 seconds
Started Jul 28 07:24:28 PM PDT 24
Finished Jul 28 07:24:48 PM PDT 24
Peak memory 215988 kb
Host smart-46db2945-1319-4a3a-a948-65e01db4c894
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028946964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3028946964
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1336401045
Short name T57
Test name
Test status
Simulation time 86718657 ps
CPU time 4.21 seconds
Started Jul 28 07:24:26 PM PDT 24
Finished Jul 28 07:24:30 PM PDT 24
Peak memory 211792 kb
Host smart-bde410d2-cf67-4727-adcd-77dc11db40bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336401045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1336401045
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2723828317
Short name T286
Test name
Test status
Simulation time 7838017415 ps
CPU time 81.86 seconds
Started Jul 28 07:24:30 PM PDT 24
Finished Jul 28 07:25:52 PM PDT 24
Peak memory 235196 kb
Host smart-a697a169-cea1-46c9-9e8d-4a93f9f31abe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723828317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2723828317
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1563054494
Short name T280
Test name
Test status
Simulation time 142673512 ps
CPU time 6.28 seconds
Started Jul 28 07:24:32 PM PDT 24
Finished Jul 28 07:24:39 PM PDT 24
Peak memory 211912 kb
Host smart-921914ce-21f8-4b26-aed8-80989a940d80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1563054494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1563054494
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2119670396
Short name T156
Test name
Test status
Simulation time 264681973 ps
CPU time 11.62 seconds
Started Jul 28 07:24:27 PM PDT 24
Finished Jul 28 07:24:39 PM PDT 24
Peak memory 214156 kb
Host smart-f1eb531d-c9d9-4b2d-bd4f-d59072b2cce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119670396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2119670396
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1580159605
Short name T151
Test name
Test status
Simulation time 127513055 ps
CPU time 5.08 seconds
Started Jul 28 07:24:29 PM PDT 24
Finished Jul 28 07:24:34 PM PDT 24
Peak memory 211820 kb
Host smart-a08fa6b2-c02a-4a22-b3c1-6d9eab7ff44a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580159605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1580159605
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2847655031
Short name T39
Test name
Test status
Simulation time 8718159910 ps
CPU time 109.91 seconds
Started Jul 28 07:24:28 PM PDT 24
Finished Jul 28 07:26:18 PM PDT 24
Peak memory 234708 kb
Host smart-24077a0d-18dc-4e8b-a551-82d33a1d3358
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847655031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2847655031
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.693434172
Short name T331
Test name
Test status
Simulation time 256619560 ps
CPU time 11.23 seconds
Started Jul 28 07:24:30 PM PDT 24
Finished Jul 28 07:24:41 PM PDT 24
Peak memory 212608 kb
Host smart-a14e3d97-f004-42bc-97ba-ba65e6492018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693434172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.693434172
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2709532626
Short name T33
Test name
Test status
Simulation time 410549241 ps
CPU time 5.99 seconds
Started Jul 28 07:24:32 PM PDT 24
Finished Jul 28 07:24:38 PM PDT 24
Peak memory 211900 kb
Host smart-44164227-a0d4-4ceb-8ce0-90113d66e868
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2709532626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2709532626
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2314821037
Short name T209
Test name
Test status
Simulation time 512463510 ps
CPU time 11.85 seconds
Started Jul 28 07:24:27 PM PDT 24
Finished Jul 28 07:24:39 PM PDT 24
Peak memory 214500 kb
Host smart-d5a7c1d5-9f29-4dfb-83d0-8df5f22107a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314821037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2314821037
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.4071644107
Short name T291
Test name
Test status
Simulation time 1067193510 ps
CPU time 16.47 seconds
Started Jul 28 07:24:26 PM PDT 24
Finished Jul 28 07:24:43 PM PDT 24
Peak memory 213948 kb
Host smart-3d7ad485-4368-4c51-bed6-438e79c4661f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071644107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.4071644107
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3551438463
Short name T52
Test name
Test status
Simulation time 20680802896 ps
CPU time 875.21 seconds
Started Jul 28 07:24:32 PM PDT 24
Finished Jul 28 07:39:08 PM PDT 24
Peak memory 236360 kb
Host smart-5976bdf4-b9f5-42dd-b32d-7a95a3fcd2dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551438463 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3551438463
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3268523858
Short name T296
Test name
Test status
Simulation time 248779249 ps
CPU time 5.13 seconds
Started Jul 28 07:24:28 PM PDT 24
Finished Jul 28 07:24:34 PM PDT 24
Peak memory 211840 kb
Host smart-380d4e26-06ad-4442-aa66-06f3da2c421d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268523858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3268523858
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.588560831
Short name T316
Test name
Test status
Simulation time 6683423601 ps
CPU time 109.55 seconds
Started Jul 28 07:24:32 PM PDT 24
Finished Jul 28 07:26:21 PM PDT 24
Peak memory 238176 kb
Host smart-a0bb166c-46f5-45cf-bcf8-7caa26c65958
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588560831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.588560831
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3560316048
Short name T44
Test name
Test status
Simulation time 168841932 ps
CPU time 9.42 seconds
Started Jul 28 07:24:29 PM PDT 24
Finished Jul 28 07:24:39 PM PDT 24
Peak memory 212524 kb
Host smart-91dd49a3-e0bc-4dbe-8933-2af52f863d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560316048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3560316048
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1965033119
Short name T211
Test name
Test status
Simulation time 268923312 ps
CPU time 6.19 seconds
Started Jul 28 07:24:30 PM PDT 24
Finished Jul 28 07:24:36 PM PDT 24
Peak memory 211860 kb
Host smart-5492b592-eaab-4d6f-b016-455b020cc768
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1965033119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1965033119
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3592142758
Short name T208
Test name
Test status
Simulation time 178520676 ps
CPU time 10.02 seconds
Started Jul 28 07:24:29 PM PDT 24
Finished Jul 28 07:24:40 PM PDT 24
Peak memory 213744 kb
Host smart-47a51c05-6f0d-4d7c-80ac-ee7440b256e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592142758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3592142758
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2321318
Short name T79
Test name
Test status
Simulation time 3887872248 ps
CPU time 17.27 seconds
Started Jul 28 07:24:30 PM PDT 24
Finished Jul 28 07:24:48 PM PDT 24
Peak memory 216412 kb
Host smart-523fa10f-3d17-4c7c-8bfb-80d9ebb9f9a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.rom_ctrl_stress_all.2321318
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3942806142
Short name T54
Test name
Test status
Simulation time 169237375669 ps
CPU time 2197.7 seconds
Started Jul 28 07:24:32 PM PDT 24
Finished Jul 28 08:01:10 PM PDT 24
Peak memory 238512 kb
Host smart-ff532822-6de5-4e5e-a65a-b53ef188a398
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942806142 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.3942806142
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2082932450
Short name T266
Test name
Test status
Simulation time 1532627428 ps
CPU time 7.72 seconds
Started Jul 28 07:24:32 PM PDT 24
Finished Jul 28 07:24:40 PM PDT 24
Peak memory 211752 kb
Host smart-fc4c9048-dc99-4666-b6da-3b3f75b96a76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082932450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2082932450
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.8423756
Short name T252
Test name
Test status
Simulation time 3085944053 ps
CPU time 151.61 seconds
Started Jul 28 07:24:33 PM PDT 24
Finished Jul 28 07:27:05 PM PDT 24
Peak memory 238232 kb
Host smart-983bd04d-6f34-4982-a62e-a01179547cc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8423756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_s
ig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_cor
rupt_sig_fatal_chk.8423756
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.835927357
Short name T251
Test name
Test status
Simulation time 993896102 ps
CPU time 10.92 seconds
Started Jul 28 07:24:29 PM PDT 24
Finished Jul 28 07:24:40 PM PDT 24
Peak memory 212692 kb
Host smart-4b2b8cc4-4d78-484f-b598-630654c6f4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835927357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.835927357
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1762166222
Short name T199
Test name
Test status
Simulation time 409324137 ps
CPU time 5.49 seconds
Started Jul 28 07:24:30 PM PDT 24
Finished Jul 28 07:24:36 PM PDT 24
Peak memory 211860 kb
Host smart-b3d542c5-3650-4f34-8233-c8d991079de1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1762166222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1762166222
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1891302304
Short name T80
Test name
Test status
Simulation time 19892961981 ps
CPU time 17.37 seconds
Started Jul 28 07:24:28 PM PDT 24
Finished Jul 28 07:24:46 PM PDT 24
Peak memory 215064 kb
Host smart-f4ec649a-dff6-44bf-bf4e-9689ee996d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891302304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1891302304
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3566597463
Short name T243
Test name
Test status
Simulation time 1112189379 ps
CPU time 25.36 seconds
Started Jul 28 07:24:30 PM PDT 24
Finished Jul 28 07:24:55 PM PDT 24
Peak memory 219740 kb
Host smart-7fc039e8-fb20-4601-86e2-adb204f6d164
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566597463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3566597463
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1108707061
Short name T197
Test name
Test status
Simulation time 127355394230 ps
CPU time 920.65 seconds
Started Jul 28 07:24:27 PM PDT 24
Finished Jul 28 07:39:48 PM PDT 24
Peak memory 236368 kb
Host smart-5d65159f-998e-4c81-be82-ec5267496ad7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108707061 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1108707061
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1596503537
Short name T262
Test name
Test status
Simulation time 168436067 ps
CPU time 4.03 seconds
Started Jul 28 07:24:32 PM PDT 24
Finished Jul 28 07:24:36 PM PDT 24
Peak memory 211796 kb
Host smart-161b1f5f-3dbe-40c8-a2ef-fdc529cb062c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596503537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1596503537
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2486646351
Short name T352
Test name
Test status
Simulation time 13093520457 ps
CPU time 134.19 seconds
Started Jul 28 07:24:32 PM PDT 24
Finished Jul 28 07:26:47 PM PDT 24
Peak memory 234196 kb
Host smart-209c22dc-9442-4a28-91ab-8c2c3931f2a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486646351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2486646351
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2515069703
Short name T215
Test name
Test status
Simulation time 350965009 ps
CPU time 9.51 seconds
Started Jul 28 07:24:33 PM PDT 24
Finished Jul 28 07:24:43 PM PDT 24
Peak memory 212724 kb
Host smart-0d8cdea2-7a4d-43de-a1e7-bf75704b0747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515069703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2515069703
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1725117881
Short name T310
Test name
Test status
Simulation time 423039305 ps
CPU time 5.92 seconds
Started Jul 28 07:24:33 PM PDT 24
Finished Jul 28 07:24:39 PM PDT 24
Peak memory 211952 kb
Host smart-1d6c8b18-59ca-42a3-b959-76cbccd6770b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1725117881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1725117881
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3254822909
Short name T346
Test name
Test status
Simulation time 396235423 ps
CPU time 11.76 seconds
Started Jul 28 07:24:32 PM PDT 24
Finished Jul 28 07:24:44 PM PDT 24
Peak memory 212560 kb
Host smart-78a38af9-7c28-4836-87f2-395b30ca19b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254822909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3254822909
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3109324796
Short name T330
Test name
Test status
Simulation time 572690060 ps
CPU time 25.04 seconds
Started Jul 28 07:24:31 PM PDT 24
Finished Jul 28 07:24:56 PM PDT 24
Peak memory 215488 kb
Host smart-88f17718-2394-4ba9-8ffe-071d5c8d8f68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109324796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3109324796
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.206478735
Short name T311
Test name
Test status
Simulation time 571486205 ps
CPU time 5.17 seconds
Started Jul 28 07:24:30 PM PDT 24
Finished Jul 28 07:24:36 PM PDT 24
Peak memory 211956 kb
Host smart-98e75a02-6692-48a4-84b4-b9f9a8df506d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206478735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.206478735
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.564748957
Short name T21
Test name
Test status
Simulation time 16870266432 ps
CPU time 74.5 seconds
Started Jul 28 07:24:32 PM PDT 24
Finished Jul 28 07:25:47 PM PDT 24
Peak memory 213092 kb
Host smart-5dccacfb-0edc-425e-bc2c-3de8b19a7d99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564748957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.564748957
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2320706638
Short name T173
Test name
Test status
Simulation time 510150720 ps
CPU time 11.04 seconds
Started Jul 28 07:24:39 PM PDT 24
Finished Jul 28 07:24:50 PM PDT 24
Peak memory 212856 kb
Host smart-68516311-ce0c-4ed2-8193-59cf97442fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320706638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2320706638
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3331866042
Short name T166
Test name
Test status
Simulation time 375029590 ps
CPU time 5.5 seconds
Started Jul 28 07:24:37 PM PDT 24
Finished Jul 28 07:24:42 PM PDT 24
Peak memory 211844 kb
Host smart-34967688-d902-4fba-8380-a475abe76b29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3331866042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3331866042
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1463600166
Short name T9
Test name
Test status
Simulation time 271480718 ps
CPU time 12.53 seconds
Started Jul 28 07:24:32 PM PDT 24
Finished Jul 28 07:24:45 PM PDT 24
Peak memory 214304 kb
Host smart-f174e074-c930-46e2-ac6f-f07940e0ac14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463600166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1463600166
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.511863956
Short name T126
Test name
Test status
Simulation time 201755571 ps
CPU time 12.17 seconds
Started Jul 28 07:24:32 PM PDT 24
Finished Jul 28 07:24:45 PM PDT 24
Peak memory 214432 kb
Host smart-dc28ede2-dce9-4e8f-b009-39d326119f05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511863956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.511863956
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2754863398
Short name T37
Test name
Test status
Simulation time 165723863 ps
CPU time 4.27 seconds
Started Jul 28 07:24:33 PM PDT 24
Finished Jul 28 07:24:37 PM PDT 24
Peak memory 211844 kb
Host smart-27bb748e-7b9d-4144-ac83-fb56cce6b90d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754863398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2754863398
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3416604740
Short name T41
Test name
Test status
Simulation time 3072914085 ps
CPU time 92.57 seconds
Started Jul 28 07:24:33 PM PDT 24
Finished Jul 28 07:26:07 PM PDT 24
Peak memory 225404 kb
Host smart-4bfa58c3-43fb-4925-aa5a-3a9891a304a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416604740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3416604740
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2564593667
Short name T357
Test name
Test status
Simulation time 618042769 ps
CPU time 9.49 seconds
Started Jul 28 07:24:38 PM PDT 24
Finished Jul 28 07:24:48 PM PDT 24
Peak memory 212768 kb
Host smart-a5388657-5060-436d-a795-7a8016f03c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564593667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2564593667
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.907503525
Short name T233
Test name
Test status
Simulation time 682639740 ps
CPU time 5.26 seconds
Started Jul 28 07:24:34 PM PDT 24
Finished Jul 28 07:24:40 PM PDT 24
Peak memory 211876 kb
Host smart-2608a1cd-b1f7-41c7-9284-78f62cb85df6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=907503525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.907503525
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1798024247
Short name T165
Test name
Test status
Simulation time 950699809 ps
CPU time 11.27 seconds
Started Jul 28 07:24:33 PM PDT 24
Finished Jul 28 07:24:46 PM PDT 24
Peak memory 214348 kb
Host smart-16b65f17-d642-4c68-ba24-3d102d4b5e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798024247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1798024247
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.410101563
Short name T148
Test name
Test status
Simulation time 1480361618 ps
CPU time 21.11 seconds
Started Jul 28 07:24:33 PM PDT 24
Finished Jul 28 07:24:54 PM PDT 24
Peak memory 217292 kb
Host smart-f6b6e92b-ee13-4a8c-bfd3-f37435e0a837
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410101563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.410101563
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2730039373
Short name T48
Test name
Test status
Simulation time 109765241250 ps
CPU time 10518.2 seconds
Started Jul 28 07:24:32 PM PDT 24
Finished Jul 28 10:19:52 PM PDT 24
Peak memory 236424 kb
Host smart-c219e483-a631-49aa-abe4-ccdaeb96f4d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730039373 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2730039373
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3952551239
Short name T264
Test name
Test status
Simulation time 134041414 ps
CPU time 5.18 seconds
Started Jul 28 07:24:34 PM PDT 24
Finished Jul 28 07:24:39 PM PDT 24
Peak memory 211756 kb
Host smart-578153cb-d0f1-4050-9593-052ba0b1f319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952551239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3952551239
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2314719213
Short name T219
Test name
Test status
Simulation time 841531312 ps
CPU time 54.21 seconds
Started Jul 28 07:24:32 PM PDT 24
Finished Jul 28 07:25:27 PM PDT 24
Peak memory 236132 kb
Host smart-395f70a1-e2d0-4944-831e-83f598ff103d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314719213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2314719213
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1276121403
Short name T348
Test name
Test status
Simulation time 261662379 ps
CPU time 11.14 seconds
Started Jul 28 07:24:31 PM PDT 24
Finished Jul 28 07:24:42 PM PDT 24
Peak memory 212612 kb
Host smart-bc685c1a-3973-481f-bc32-2d82d1fb922e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276121403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1276121403
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3233432461
Short name T241
Test name
Test status
Simulation time 196056028 ps
CPU time 5.33 seconds
Started Jul 28 07:24:33 PM PDT 24
Finished Jul 28 07:24:40 PM PDT 24
Peak memory 211928 kb
Host smart-76e4429a-b109-438b-a11c-b0d77bc1ddbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3233432461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3233432461
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.559642825
Short name T178
Test name
Test status
Simulation time 730046006 ps
CPU time 10.41 seconds
Started Jul 28 07:24:38 PM PDT 24
Finished Jul 28 07:24:49 PM PDT 24
Peak memory 214284 kb
Host smart-51158a14-89db-41ea-b881-8ddbd6d3a7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559642825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.559642825
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2337532886
Short name T206
Test name
Test status
Simulation time 525567097 ps
CPU time 9.43 seconds
Started Jul 28 07:24:33 PM PDT 24
Finished Jul 28 07:24:44 PM PDT 24
Peak memory 211920 kb
Host smart-e6a46478-e36b-423f-aed9-59205785b033
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337532886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2337532886
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2288690166
Short name T245
Test name
Test status
Simulation time 179281816 ps
CPU time 5.29 seconds
Started Jul 28 07:23:53 PM PDT 24
Finished Jul 28 07:23:58 PM PDT 24
Peak memory 211804 kb
Host smart-4073ad65-8a4e-4806-8882-a75a0379bc31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288690166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2288690166
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2518454357
Short name T302
Test name
Test status
Simulation time 1231782893 ps
CPU time 69.63 seconds
Started Jul 28 07:23:55 PM PDT 24
Finished Jul 28 07:25:05 PM PDT 24
Peak memory 236344 kb
Host smart-64c13c7f-0d42-4779-ae8d-835662658d66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518454357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2518454357
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.382368364
Short name T275
Test name
Test status
Simulation time 175390643 ps
CPU time 9.41 seconds
Started Jul 28 07:23:53 PM PDT 24
Finished Jul 28 07:24:03 PM PDT 24
Peak memory 212668 kb
Host smart-96e2e775-d5b2-4af9-84b3-b2238421e7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382368364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.382368364
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2383875982
Short name T234
Test name
Test status
Simulation time 455037668 ps
CPU time 6.37 seconds
Started Jul 28 07:23:49 PM PDT 24
Finished Jul 28 07:23:55 PM PDT 24
Peak memory 211892 kb
Host smart-017b4c08-a7ad-4de6-81b6-8c75f84bb447
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2383875982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2383875982
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3443032336
Short name T81
Test name
Test status
Simulation time 595190245 ps
CPU time 12.07 seconds
Started Jul 28 07:23:47 PM PDT 24
Finished Jul 28 07:24:00 PM PDT 24
Peak memory 213960 kb
Host smart-627a56e3-1146-4867-9922-3c69ea238c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443032336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3443032336
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1797964483
Short name T293
Test name
Test status
Simulation time 2433115105 ps
CPU time 19.61 seconds
Started Jul 28 07:23:49 PM PDT 24
Finished Jul 28 07:24:09 PM PDT 24
Peak memory 216992 kb
Host smart-ac67dfb1-e1b8-487d-b2dd-45676d320aaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797964483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1797964483
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2073816017
Short name T15
Test name
Test status
Simulation time 183840348630 ps
CPU time 1665.32 seconds
Started Jul 28 07:23:53 PM PDT 24
Finished Jul 28 07:51:38 PM PDT 24
Peak memory 236260 kb
Host smart-cd0e72e9-54fc-495a-9256-01320f91e893
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073816017 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.2073816017
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1002130952
Short name T320
Test name
Test status
Simulation time 251739798 ps
CPU time 4.98 seconds
Started Jul 28 07:24:37 PM PDT 24
Finished Jul 28 07:24:43 PM PDT 24
Peak memory 211764 kb
Host smart-213d02a5-1fb7-4ffb-9da6-37629b2363e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002130952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1002130952
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3897878252
Short name T361
Test name
Test status
Simulation time 8663509084 ps
CPU time 144.9 seconds
Started Jul 28 07:24:36 PM PDT 24
Finished Jul 28 07:27:01 PM PDT 24
Peak memory 228816 kb
Host smart-2a783d57-dfeb-4bb6-8dcc-57176e828c91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897878252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3897878252
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1490084985
Short name T253
Test name
Test status
Simulation time 1086068475 ps
CPU time 11.22 seconds
Started Jul 28 07:24:30 PM PDT 24
Finished Jul 28 07:24:41 PM PDT 24
Peak memory 212708 kb
Host smart-a617640f-d629-4a18-8810-c3930d3371f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490084985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1490084985
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2407092654
Short name T213
Test name
Test status
Simulation time 99542926 ps
CPU time 5.83 seconds
Started Jul 28 07:24:36 PM PDT 24
Finished Jul 28 07:24:42 PM PDT 24
Peak memory 211812 kb
Host smart-361e2c86-9cb6-4828-a9ab-ea5f8dd3a697
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2407092654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2407092654
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.736254167
Short name T176
Test name
Test status
Simulation time 370854335 ps
CPU time 10.3 seconds
Started Jul 28 07:24:33 PM PDT 24
Finished Jul 28 07:24:43 PM PDT 24
Peak memory 212936 kb
Host smart-c05ee615-d9e7-4293-8c2b-c5d863badfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736254167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.736254167
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1126266268
Short name T283
Test name
Test status
Simulation time 1400194516 ps
CPU time 15.6 seconds
Started Jul 28 07:24:33 PM PDT 24
Finished Jul 28 07:24:50 PM PDT 24
Peak memory 215544 kb
Host smart-3aedfdb1-04c1-46d4-95aa-6584cdd723d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126266268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1126266268
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2533049320
Short name T146
Test name
Test status
Simulation time 86447022 ps
CPU time 4.29 seconds
Started Jul 28 07:24:36 PM PDT 24
Finished Jul 28 07:24:40 PM PDT 24
Peak memory 211796 kb
Host smart-4119e04d-2306-4d96-a8b7-a5e7bdd2d96e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533049320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2533049320
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1184515381
Short name T167
Test name
Test status
Simulation time 30167310924 ps
CPU time 132.46 seconds
Started Jul 28 07:24:32 PM PDT 24
Finished Jul 28 07:26:45 PM PDT 24
Peak memory 238144 kb
Host smart-e28428d2-05ac-4fe8-8114-fcf80b11ef4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184515381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1184515381
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1216640524
Short name T133
Test name
Test status
Simulation time 861728656 ps
CPU time 11.2 seconds
Started Jul 28 07:24:37 PM PDT 24
Finished Jul 28 07:24:48 PM PDT 24
Peak memory 212644 kb
Host smart-a93a16a9-ffdd-40fd-8c50-1256021acd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216640524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1216640524
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.925765608
Short name T372
Test name
Test status
Simulation time 145775226 ps
CPU time 6.48 seconds
Started Jul 28 07:24:27 PM PDT 24
Finished Jul 28 07:24:34 PM PDT 24
Peak memory 212068 kb
Host smart-95f61ce8-eb55-4c41-a1ad-8700f5b4474e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=925765608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.925765608
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.679605168
Short name T308
Test name
Test status
Simulation time 1098118062 ps
CPU time 11.55 seconds
Started Jul 28 07:24:34 PM PDT 24
Finished Jul 28 07:24:46 PM PDT 24
Peak memory 213208 kb
Host smart-6215cce8-f2e5-49a1-8625-b8565140d81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679605168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.679605168
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1657387680
Short name T155
Test name
Test status
Simulation time 473959776 ps
CPU time 22.71 seconds
Started Jul 28 07:24:33 PM PDT 24
Finished Jul 28 07:24:57 PM PDT 24
Peak memory 214132 kb
Host smart-a1864987-a0d4-4581-af3b-8164a7196543
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657387680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1657387680
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3394547237
Short name T343
Test name
Test status
Simulation time 480821142716 ps
CPU time 4832.77 seconds
Started Jul 28 07:24:35 PM PDT 24
Finished Jul 28 08:45:08 PM PDT 24
Peak memory 257564 kb
Host smart-c6acef54-4368-427f-9181-9322029d6d1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394547237 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.3394547237
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1879836287
Short name T295
Test name
Test status
Simulation time 131468035 ps
CPU time 5.19 seconds
Started Jul 28 07:24:36 PM PDT 24
Finished Jul 28 07:24:41 PM PDT 24
Peak memory 211760 kb
Host smart-b374374e-4c9d-437f-93f1-2004e781c585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879836287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1879836287
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.497578371
Short name T143
Test name
Test status
Simulation time 1955504222 ps
CPU time 61.88 seconds
Started Jul 28 07:24:34 PM PDT 24
Finished Jul 28 07:25:36 PM PDT 24
Peak memory 236460 kb
Host smart-e11c4739-2757-4f3a-a4e9-a8374bf4c254
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497578371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.497578371
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1893863658
Short name T174
Test name
Test status
Simulation time 261849402 ps
CPU time 11.22 seconds
Started Jul 28 07:24:39 PM PDT 24
Finished Jul 28 07:24:50 PM PDT 24
Peak memory 212656 kb
Host smart-6f9bba3a-7cfe-4a55-b1b0-e56d61cd00c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893863658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1893863658
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.715385095
Short name T154
Test name
Test status
Simulation time 143527952 ps
CPU time 6.88 seconds
Started Jul 28 07:24:36 PM PDT 24
Finished Jul 28 07:24:43 PM PDT 24
Peak memory 211908 kb
Host smart-1421d318-367d-469d-a179-532ea06f5707
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=715385095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.715385095
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1071106607
Short name T137
Test name
Test status
Simulation time 196499114 ps
CPU time 10.18 seconds
Started Jul 28 07:24:36 PM PDT 24
Finished Jul 28 07:24:46 PM PDT 24
Peak memory 214472 kb
Host smart-f8193bee-25f2-4b0a-956b-ebba8a214c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071106607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1071106607
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1416395491
Short name T297
Test name
Test status
Simulation time 2423393026 ps
CPU time 12.93 seconds
Started Jul 28 07:24:37 PM PDT 24
Finished Jul 28 07:24:50 PM PDT 24
Peak memory 214240 kb
Host smart-aa91da80-a524-43f9-aa57-9b760abbec22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416395491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1416395491
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1892351914
Short name T50
Test name
Test status
Simulation time 71272690008 ps
CPU time 1313.66 seconds
Started Jul 28 07:24:37 PM PDT 24
Finished Jul 28 07:46:31 PM PDT 24
Peak memory 236380 kb
Host smart-94d99344-ec2d-4b08-bb02-a52562a34233
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892351914 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1892351914
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.231367152
Short name T128
Test name
Test status
Simulation time 256646645 ps
CPU time 5.51 seconds
Started Jul 28 07:24:37 PM PDT 24
Finished Jul 28 07:24:42 PM PDT 24
Peak memory 211756 kb
Host smart-6f101f5f-fe80-49d6-8bf6-edb0119eca56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231367152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.231367152
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4153569831
Short name T217
Test name
Test status
Simulation time 1967208875 ps
CPU time 16.53 seconds
Started Jul 28 07:24:36 PM PDT 24
Finished Jul 28 07:24:53 PM PDT 24
Peak memory 212584 kb
Host smart-ad3e2423-b37c-47fe-a53f-6a1304cad689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153569831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.4153569831
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.4292699156
Short name T201
Test name
Test status
Simulation time 561324765 ps
CPU time 6.59 seconds
Started Jul 28 07:24:36 PM PDT 24
Finished Jul 28 07:24:43 PM PDT 24
Peak memory 211912 kb
Host smart-747a600a-dba9-41b6-b042-d3c785e44e66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4292699156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.4292699156
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2251576885
Short name T230
Test name
Test status
Simulation time 180157488 ps
CPU time 10.02 seconds
Started Jul 28 07:24:35 PM PDT 24
Finished Jul 28 07:24:46 PM PDT 24
Peak memory 213816 kb
Host smart-3285822f-8b59-475b-923e-7e2ceba8fcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251576885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2251576885
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2805833574
Short name T367
Test name
Test status
Simulation time 717902478 ps
CPU time 16.42 seconds
Started Jul 28 07:24:35 PM PDT 24
Finished Jul 28 07:24:52 PM PDT 24
Peak memory 215556 kb
Host smart-ab0dc0e2-858c-4446-86ad-b4fcd95e8ccd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805833574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2805833574
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1386068440
Short name T304
Test name
Test status
Simulation time 13083971200 ps
CPU time 3218.48 seconds
Started Jul 28 07:24:36 PM PDT 24
Finished Jul 28 08:18:15 PM PDT 24
Peak memory 236320 kb
Host smart-34dbf597-3b0c-4297-a8e8-aed9040ea6d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386068440 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.1386068440
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1437209783
Short name T150
Test name
Test status
Simulation time 128527737 ps
CPU time 5.11 seconds
Started Jul 28 07:24:41 PM PDT 24
Finished Jul 28 07:24:47 PM PDT 24
Peak memory 211800 kb
Host smart-0004e46b-b95c-4b22-ac24-0aa8e2ab964d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437209783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1437209783
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3194333698
Short name T306
Test name
Test status
Simulation time 8841434479 ps
CPU time 153.14 seconds
Started Jul 28 07:24:38 PM PDT 24
Finished Jul 28 07:27:12 PM PDT 24
Peak memory 238788 kb
Host smart-d6f592d0-32f0-4f5d-ba9b-f64bcf9dbbc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194333698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3194333698
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3184997735
Short name T301
Test name
Test status
Simulation time 168470411 ps
CPU time 9.55 seconds
Started Jul 28 07:24:35 PM PDT 24
Finished Jul 28 07:24:45 PM PDT 24
Peak memory 212952 kb
Host smart-86d64cbe-28fc-4c9c-a03a-24c0b1ca7a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184997735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3184997735
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.888964659
Short name T124
Test name
Test status
Simulation time 96386608 ps
CPU time 5.6 seconds
Started Jul 28 07:24:38 PM PDT 24
Finished Jul 28 07:24:44 PM PDT 24
Peak memory 211940 kb
Host smart-8bf9ae18-1184-4bb0-b5d9-b43c5a18e660
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=888964659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.888964659
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1047852253
Short name T189
Test name
Test status
Simulation time 746669652 ps
CPU time 10.43 seconds
Started Jul 28 07:24:36 PM PDT 24
Finished Jul 28 07:24:47 PM PDT 24
Peak memory 214740 kb
Host smart-fea6ccf5-63e9-4300-b65a-c794550d5605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047852253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1047852253
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.780197505
Short name T246
Test name
Test status
Simulation time 1736982724 ps
CPU time 21.38 seconds
Started Jul 28 07:24:36 PM PDT 24
Finished Jul 28 07:24:57 PM PDT 24
Peak memory 216288 kb
Host smart-ebf8b371-4390-4cf6-afbf-6f78cf6d427f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780197505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.780197505
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3720564507
Short name T203
Test name
Test status
Simulation time 497064708 ps
CPU time 5.32 seconds
Started Jul 28 07:24:39 PM PDT 24
Finished Jul 28 07:24:45 PM PDT 24
Peak memory 211816 kb
Host smart-8ed12617-5fab-469b-8a71-462b8c6b5dc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720564507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3720564507
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3002679658
Short name T258
Test name
Test status
Simulation time 6259296942 ps
CPU time 158.43 seconds
Started Jul 28 07:24:42 PM PDT 24
Finished Jul 28 07:27:20 PM PDT 24
Peak memory 237888 kb
Host smart-5ace1d4f-2bac-42c1-852c-d3ce0c7a1745
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002679658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3002679658
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1827408761
Short name T359
Test name
Test status
Simulation time 887711004 ps
CPU time 11.12 seconds
Started Jul 28 07:24:37 PM PDT 24
Finished Jul 28 07:24:49 PM PDT 24
Peak memory 213280 kb
Host smart-5a7242d3-9dcb-42f7-a07a-bb79deb1662f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827408761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1827408761
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3531334120
Short name T20
Test name
Test status
Simulation time 527753638 ps
CPU time 6.04 seconds
Started Jul 28 07:24:41 PM PDT 24
Finished Jul 28 07:24:47 PM PDT 24
Peak memory 211936 kb
Host smart-d63b260a-164f-482f-b721-7595b32143af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3531334120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3531334120
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3799665401
Short name T277
Test name
Test status
Simulation time 995385318 ps
CPU time 15.95 seconds
Started Jul 28 07:24:40 PM PDT 24
Finished Jul 28 07:24:56 PM PDT 24
Peak memory 213032 kb
Host smart-ba2cd970-e9d6-4f17-ba64-b07e0ba15f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799665401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3799665401
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2639481439
Short name T254
Test name
Test status
Simulation time 724412228 ps
CPU time 21.62 seconds
Started Jul 28 07:24:42 PM PDT 24
Finished Jul 28 07:25:04 PM PDT 24
Peak memory 215208 kb
Host smart-30f24952-2495-42d3-8b76-6c3d9b0ae922
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639481439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2639481439
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2840347547
Short name T326
Test name
Test status
Simulation time 36392222627 ps
CPU time 7528.51 seconds
Started Jul 28 07:24:41 PM PDT 24
Finished Jul 28 09:30:10 PM PDT 24
Peak memory 236332 kb
Host smart-e657addd-cc13-411c-b877-53b1de677434
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840347547 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2840347547
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3089332240
Short name T158
Test name
Test status
Simulation time 461170948 ps
CPU time 4.24 seconds
Started Jul 28 07:24:46 PM PDT 24
Finished Jul 28 07:24:51 PM PDT 24
Peak memory 211820 kb
Host smart-b71f5c64-6e68-4dc4-99f0-d61f9b2a8144
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089332240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3089332240
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3362000210
Short name T160
Test name
Test status
Simulation time 2930709911 ps
CPU time 139.66 seconds
Started Jul 28 07:24:51 PM PDT 24
Finished Jul 28 07:27:11 PM PDT 24
Peak memory 238188 kb
Host smart-f5b44540-73fb-443b-9b76-02489ee6ad72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362000210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3362000210
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2086044578
Short name T373
Test name
Test status
Simulation time 1037601985 ps
CPU time 11.61 seconds
Started Jul 28 07:24:47 PM PDT 24
Finished Jul 28 07:24:58 PM PDT 24
Peak memory 212620 kb
Host smart-b6ccdf64-fcc8-492c-8730-a562e6d0390f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086044578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2086044578
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.4095354742
Short name T144
Test name
Test status
Simulation time 3133936632 ps
CPU time 8.63 seconds
Started Jul 28 07:24:46 PM PDT 24
Finished Jul 28 07:24:54 PM PDT 24
Peak memory 211984 kb
Host smart-b5b36628-60d5-40cd-a528-e925fc72834e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4095354742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.4095354742
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1421050238
Short name T3
Test name
Test status
Simulation time 179605252 ps
CPU time 10.36 seconds
Started Jul 28 07:24:44 PM PDT 24
Finished Jul 28 07:24:54 PM PDT 24
Peak memory 213676 kb
Host smart-82d2ce02-e388-42ad-a470-367342d95005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421050238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1421050238
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3971589437
Short name T222
Test name
Test status
Simulation time 563437216 ps
CPU time 25.98 seconds
Started Jul 28 07:24:44 PM PDT 24
Finished Jul 28 07:25:10 PM PDT 24
Peak memory 215992 kb
Host smart-7405c53b-3c15-4230-bd67-036aa8f9cae7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971589437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3971589437
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2179717536
Short name T356
Test name
Test status
Simulation time 99891105221 ps
CPU time 4010.63 seconds
Started Jul 28 07:24:52 PM PDT 24
Finished Jul 28 08:31:44 PM PDT 24
Peak memory 247476 kb
Host smart-4fdcc831-edb6-4fbe-a55e-a99e0b386548
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179717536 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.2179717536
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.575379291
Short name T375
Test name
Test status
Simulation time 168191849 ps
CPU time 5.18 seconds
Started Jul 28 07:24:46 PM PDT 24
Finished Jul 28 07:24:52 PM PDT 24
Peak memory 211756 kb
Host smart-cf2f538f-dc3a-4b61-bac4-d226439845c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575379291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.575379291
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4195901900
Short name T309
Test name
Test status
Simulation time 2843968475 ps
CPU time 139.76 seconds
Started Jul 28 07:24:52 PM PDT 24
Finished Jul 28 07:27:12 PM PDT 24
Peak memory 213376 kb
Host smart-9a548a72-b77f-4b1e-b754-e54401eb9a73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195901900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.4195901900
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.78868109
Short name T32
Test name
Test status
Simulation time 264327538 ps
CPU time 11.32 seconds
Started Jul 28 07:24:47 PM PDT 24
Finished Jul 28 07:24:59 PM PDT 24
Peak memory 212620 kb
Host smart-cd6cd1fc-7499-487e-bfbf-20bd4f3927e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78868109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.78868109
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1877867669
Short name T333
Test name
Test status
Simulation time 136281586 ps
CPU time 6.28 seconds
Started Jul 28 07:24:48 PM PDT 24
Finished Jul 28 07:24:55 PM PDT 24
Peak memory 211912 kb
Host smart-10df94ec-bfae-4d96-97ba-317237d44efa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1877867669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1877867669
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.653812441
Short name T157
Test name
Test status
Simulation time 724935105 ps
CPU time 9.68 seconds
Started Jul 28 07:24:45 PM PDT 24
Finished Jul 28 07:24:55 PM PDT 24
Peak memory 213792 kb
Host smart-910283a8-1c15-4fe9-9f45-71e9cf1ddfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653812441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.653812441
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3277351925
Short name T172
Test name
Test status
Simulation time 295657413 ps
CPU time 8.16 seconds
Started Jul 28 07:24:51 PM PDT 24
Finished Jul 28 07:25:00 PM PDT 24
Peak memory 211788 kb
Host smart-8b9b8f43-7ebc-42eb-a5e4-087786b00639
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277351925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3277351925
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.4070369940
Short name T185
Test name
Test status
Simulation time 124663911471 ps
CPU time 695.51 seconds
Started Jul 28 07:24:51 PM PDT 24
Finished Jul 28 07:36:27 PM PDT 24
Peak memory 236296 kb
Host smart-d7a52c3a-2e3d-404b-bfbb-6c95f3594228
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070369940 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.4070369940
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1865482293
Short name T5
Test name
Test status
Simulation time 1380134734 ps
CPU time 5.21 seconds
Started Jul 28 07:24:51 PM PDT 24
Finished Jul 28 07:24:56 PM PDT 24
Peak memory 211792 kb
Host smart-8aebac71-66d7-4d4c-9b1f-a7ea6c6f29a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865482293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1865482293
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.407733977
Short name T40
Test name
Test status
Simulation time 13544692963 ps
CPU time 149.67 seconds
Started Jul 28 07:24:46 PM PDT 24
Finished Jul 28 07:27:16 PM PDT 24
Peak memory 235292 kb
Host smart-27da211d-63a6-4e87-b696-0615939d2fa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407733977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.407733977
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.967442450
Short name T26
Test name
Test status
Simulation time 507102916 ps
CPU time 11.14 seconds
Started Jul 28 07:24:44 PM PDT 24
Finished Jul 28 07:24:55 PM PDT 24
Peak memory 212740 kb
Host smart-70e843bd-4e9a-4b8c-9189-36236bd8ff59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967442450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.967442450
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2313397642
Short name T141
Test name
Test status
Simulation time 916927424 ps
CPU time 6.05 seconds
Started Jul 28 07:24:44 PM PDT 24
Finished Jul 28 07:24:50 PM PDT 24
Peak memory 211908 kb
Host smart-56eac676-ba77-479d-b9a6-7b1b2c9ee864
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313397642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2313397642
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1406166414
Short name T260
Test name
Test status
Simulation time 753009941 ps
CPU time 9.96 seconds
Started Jul 28 07:24:44 PM PDT 24
Finished Jul 28 07:24:54 PM PDT 24
Peak memory 214072 kb
Host smart-71d76065-522c-4070-8238-7db09c1c2ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406166414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1406166414
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3130874619
Short name T190
Test name
Test status
Simulation time 1484005635 ps
CPU time 24.07 seconds
Started Jul 28 07:24:46 PM PDT 24
Finished Jul 28 07:25:10 PM PDT 24
Peak memory 217268 kb
Host smart-9665d01b-aa5c-4acb-aefc-916a11d590d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130874619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3130874619
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.325580420
Short name T58
Test name
Test status
Simulation time 171651198 ps
CPU time 4.3 seconds
Started Jul 28 07:24:48 PM PDT 24
Finished Jul 28 07:24:53 PM PDT 24
Peak memory 211728 kb
Host smart-5e58394c-4ce7-4c9d-ab85-a1e2bb28806a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325580420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.325580420
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3670770162
Short name T325
Test name
Test status
Simulation time 8005497586 ps
CPU time 118.25 seconds
Started Jul 28 07:24:51 PM PDT 24
Finished Jul 28 07:26:50 PM PDT 24
Peak memory 238332 kb
Host smart-62fb3cb6-5e7f-4d16-9fba-d21f7cea9d3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670770162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3670770162
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1906915979
Short name T238
Test name
Test status
Simulation time 200071520 ps
CPU time 9.53 seconds
Started Jul 28 07:24:50 PM PDT 24
Finished Jul 28 07:25:00 PM PDT 24
Peak memory 212700 kb
Host smart-f13983da-afbe-4ee3-b2e1-215e1d9f618e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906915979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1906915979
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.495233495
Short name T305
Test name
Test status
Simulation time 100258881 ps
CPU time 5.71 seconds
Started Jul 28 07:24:50 PM PDT 24
Finished Jul 28 07:24:56 PM PDT 24
Peak memory 211892 kb
Host smart-e15f901d-ea9c-4371-86a9-4e2032aa9a7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=495233495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.495233495
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.35977792
Short name T121
Test name
Test status
Simulation time 527355600 ps
CPU time 11.72 seconds
Started Jul 28 07:24:49 PM PDT 24
Finished Jul 28 07:25:00 PM PDT 24
Peak memory 213904 kb
Host smart-95f79239-2f83-4aec-935b-9c4f6e8359ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35977792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.35977792
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2402901225
Short name T358
Test name
Test status
Simulation time 312286000 ps
CPU time 17.6 seconds
Started Jul 28 07:24:50 PM PDT 24
Finished Jul 28 07:25:07 PM PDT 24
Peak memory 214492 kb
Host smart-c6e50d18-5aef-425f-90dd-a2197fb9ba36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402901225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2402901225
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.718443125
Short name T188
Test name
Test status
Simulation time 263509843 ps
CPU time 5.07 seconds
Started Jul 28 07:23:54 PM PDT 24
Finished Jul 28 07:23:59 PM PDT 24
Peak memory 211824 kb
Host smart-41406b05-8b20-4737-a454-5bc9684c4038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718443125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.718443125
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2882923180
Short name T376
Test name
Test status
Simulation time 9417284541 ps
CPU time 110.43 seconds
Started Jul 28 07:23:57 PM PDT 24
Finished Jul 28 07:25:47 PM PDT 24
Peak memory 240288 kb
Host smart-5f0b840d-e79d-4908-bdc3-dd3b97f7b127
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882923180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2882923180
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3177342698
Short name T271
Test name
Test status
Simulation time 255944398 ps
CPU time 11.04 seconds
Started Jul 28 07:23:52 PM PDT 24
Finished Jul 28 07:24:03 PM PDT 24
Peak memory 212732 kb
Host smart-02b3bb19-d541-4c89-94e8-116542c4acfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177342698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3177342698
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3238077631
Short name T257
Test name
Test status
Simulation time 101655729 ps
CPU time 5.72 seconds
Started Jul 28 07:23:53 PM PDT 24
Finished Jul 28 07:23:58 PM PDT 24
Peak memory 211852 kb
Host smart-249b3201-284b-4cc0-b066-728eb987f3f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3238077631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3238077631
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.478819968
Short name T22
Test name
Test status
Simulation time 250963645 ps
CPU time 99.17 seconds
Started Jul 28 07:23:53 PM PDT 24
Finished Jul 28 07:25:32 PM PDT 24
Peak memory 237236 kb
Host smart-4ec8fb36-3e49-46e3-91f5-790944f85929
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478819968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.478819968
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3222667981
Short name T35
Test name
Test status
Simulation time 279491116 ps
CPU time 11.46 seconds
Started Jul 28 07:23:52 PM PDT 24
Finished Jul 28 07:24:03 PM PDT 24
Peak memory 213220 kb
Host smart-60cd9b21-e9e4-40b5-8217-703c5c3dc7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222667981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3222667981
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.55005974
Short name T49
Test name
Test status
Simulation time 182602847153 ps
CPU time 1440.94 seconds
Started Jul 28 07:23:53 PM PDT 24
Finished Jul 28 07:47:54 PM PDT 24
Peak memory 236372 kb
Host smart-9cb73577-fe93-44a7-a688-d59d4572c3d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55005974 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.55005974
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2439835110
Short name T255
Test name
Test status
Simulation time 171364390 ps
CPU time 4.26 seconds
Started Jul 28 07:24:50 PM PDT 24
Finished Jul 28 07:24:54 PM PDT 24
Peak memory 211800 kb
Host smart-ff9a24e0-a38e-4b64-9b52-ca35899e6f50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439835110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2439835110
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2517571411
Short name T339
Test name
Test status
Simulation time 10972593647 ps
CPU time 135.8 seconds
Started Jul 28 07:24:49 PM PDT 24
Finished Jul 28 07:27:05 PM PDT 24
Peak memory 235300 kb
Host smart-90b9d3d1-f299-491b-a621-993fcd524b2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517571411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2517571411
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.616181544
Short name T229
Test name
Test status
Simulation time 1664467792 ps
CPU time 11.64 seconds
Started Jul 28 07:24:48 PM PDT 24
Finished Jul 28 07:25:00 PM PDT 24
Peak memory 212912 kb
Host smart-eafab779-d0d5-4e51-be73-623ca3142b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616181544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.616181544
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1839586794
Short name T195
Test name
Test status
Simulation time 148409825 ps
CPU time 6.98 seconds
Started Jul 28 07:24:50 PM PDT 24
Finished Jul 28 07:24:57 PM PDT 24
Peak memory 211900 kb
Host smart-4149dc50-242f-4b27-a38f-45c5cd348ca1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1839586794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1839586794
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2223009278
Short name T122
Test name
Test status
Simulation time 1441768681 ps
CPU time 11.66 seconds
Started Jul 28 07:24:51 PM PDT 24
Finished Jul 28 07:25:03 PM PDT 24
Peak memory 214180 kb
Host smart-79457927-62a9-45c9-9c8b-76292a88a27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223009278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2223009278
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.848385607
Short name T127
Test name
Test status
Simulation time 739714703 ps
CPU time 25.3 seconds
Started Jul 28 07:24:49 PM PDT 24
Finished Jul 28 07:25:14 PM PDT 24
Peak memory 215880 kb
Host smart-c59f65fd-ec16-4442-a19e-95fdb5bb43ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848385607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.848385607
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2569499238
Short name T267
Test name
Test status
Simulation time 172309138 ps
CPU time 4.15 seconds
Started Jul 28 07:24:54 PM PDT 24
Finished Jul 28 07:24:58 PM PDT 24
Peak memory 211776 kb
Host smart-3d5852c4-b893-442e-847c-20ca7b549beb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569499238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2569499238
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1813452743
Short name T337
Test name
Test status
Simulation time 9112822979 ps
CPU time 83.55 seconds
Started Jul 28 07:24:54 PM PDT 24
Finished Jul 28 07:26:18 PM PDT 24
Peak memory 225804 kb
Host smart-8ac71d12-4642-424d-b813-b471961c121c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813452743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1813452743
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.4111842496
Short name T364
Test name
Test status
Simulation time 262018348 ps
CPU time 11.09 seconds
Started Jul 28 07:24:54 PM PDT 24
Finished Jul 28 07:25:05 PM PDT 24
Peak memory 212652 kb
Host smart-cd0c5957-bfb0-4383-b5d9-ef2b916c2011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111842496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.4111842496
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.313206610
Short name T184
Test name
Test status
Simulation time 98087179 ps
CPU time 5.91 seconds
Started Jul 28 07:24:54 PM PDT 24
Finished Jul 28 07:25:00 PM PDT 24
Peak memory 211916 kb
Host smart-b54e56bb-1fc1-4e4a-9f0c-7cf9cb54bfeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=313206610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.313206610
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.100280789
Short name T274
Test name
Test status
Simulation time 389019685 ps
CPU time 10.06 seconds
Started Jul 28 07:24:50 PM PDT 24
Finished Jul 28 07:25:00 PM PDT 24
Peak memory 213064 kb
Host smart-42471e70-9722-4d12-84e0-0f1f179b93f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100280789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.100280789
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3311437766
Short name T59
Test name
Test status
Simulation time 298880547 ps
CPU time 16.3 seconds
Started Jul 28 07:24:50 PM PDT 24
Finished Jul 28 07:25:06 PM PDT 24
Peak memory 215388 kb
Host smart-6535ef78-4911-41c8-b941-a6722549ab1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311437766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3311437766
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.4026423128
Short name T105
Test name
Test status
Simulation time 67274534530 ps
CPU time 2972.78 seconds
Started Jul 28 07:24:53 PM PDT 24
Finished Jul 28 08:14:27 PM PDT 24
Peak memory 245776 kb
Host smart-a00716e1-99ea-4b0f-aae8-a7f9acf87c5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026423128 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.4026423128
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1146522499
Short name T149
Test name
Test status
Simulation time 893308330 ps
CPU time 5.04 seconds
Started Jul 28 07:24:53 PM PDT 24
Finished Jul 28 07:24:58 PM PDT 24
Peak memory 211748 kb
Host smart-9a673013-1744-40d9-b7e4-873d0476e392
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146522499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1146522499
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3061899360
Short name T315
Test name
Test status
Simulation time 39248072445 ps
CPU time 120.56 seconds
Started Jul 28 07:24:54 PM PDT 24
Finished Jul 28 07:26:55 PM PDT 24
Peak memory 213136 kb
Host smart-fa71854d-991c-42e3-af62-bec930850c0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061899360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3061899360
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3244566793
Short name T136
Test name
Test status
Simulation time 2266291237 ps
CPU time 11.16 seconds
Started Jul 28 07:24:54 PM PDT 24
Finished Jul 28 07:25:05 PM PDT 24
Peak memory 212760 kb
Host smart-cac13bac-b6fa-4125-be5b-d6f2c88500d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244566793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3244566793
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3941270061
Short name T299
Test name
Test status
Simulation time 190748300 ps
CPU time 5.47 seconds
Started Jul 28 07:24:53 PM PDT 24
Finished Jul 28 07:24:59 PM PDT 24
Peak memory 211908 kb
Host smart-6c952e75-f511-4c63-ab51-ae79b1fdd1b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3941270061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3941270061
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.880215504
Short name T268
Test name
Test status
Simulation time 350029436 ps
CPU time 10.3 seconds
Started Jul 28 07:24:57 PM PDT 24
Finished Jul 28 07:25:07 PM PDT 24
Peak memory 214368 kb
Host smart-dc7d5af2-f0a2-49c6-81fa-ecda88eed015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880215504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.880215504
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.591850535
Short name T171
Test name
Test status
Simulation time 581941956 ps
CPU time 25.39 seconds
Started Jul 28 07:24:53 PM PDT 24
Finished Jul 28 07:25:19 PM PDT 24
Peak memory 216268 kb
Host smart-701ad2a9-f9bb-408e-a30d-8feb4a438faf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591850535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.591850535
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.476953938
Short name T371
Test name
Test status
Simulation time 2188991666 ps
CPU time 121.42 seconds
Started Jul 28 07:24:59 PM PDT 24
Finished Jul 28 07:27:01 PM PDT 24
Peak memory 237264 kb
Host smart-b39de0f1-26ba-4136-b221-e01d2a1d2909
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476953938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.476953938
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.82437087
Short name T43
Test name
Test status
Simulation time 177325178 ps
CPU time 10.41 seconds
Started Jul 28 07:24:58 PM PDT 24
Finished Jul 28 07:25:09 PM PDT 24
Peak memory 212664 kb
Host smart-0b7c1795-16f2-4ca9-9b17-7e4580619762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82437087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.82437087
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.954972407
Short name T60
Test name
Test status
Simulation time 140436903 ps
CPU time 6.48 seconds
Started Jul 28 07:25:00 PM PDT 24
Finished Jul 28 07:25:06 PM PDT 24
Peak memory 211904 kb
Host smart-fa93aebf-b8ad-478e-9db0-b929064b33c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=954972407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.954972407
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3890958752
Short name T366
Test name
Test status
Simulation time 1032949837 ps
CPU time 11.93 seconds
Started Jul 28 07:24:54 PM PDT 24
Finished Jul 28 07:25:06 PM PDT 24
Peak memory 214380 kb
Host smart-ac566cf4-9f9d-4041-ad84-b1913099939c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890958752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3890958752
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.893687619
Short name T374
Test name
Test status
Simulation time 555311459 ps
CPU time 24.27 seconds
Started Jul 28 07:24:53 PM PDT 24
Finished Jul 28 07:25:17 PM PDT 24
Peak memory 215220 kb
Host smart-e0a420ac-4500-4593-a693-f3e6cf1dc4a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893687619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.893687619
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1715145600
Short name T67
Test name
Test status
Simulation time 89997192 ps
CPU time 4.3 seconds
Started Jul 28 07:24:59 PM PDT 24
Finished Jul 28 07:25:04 PM PDT 24
Peak memory 211840 kb
Host smart-5a36f33b-021e-4124-acd9-c8f71af67646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715145600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1715145600
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2776093513
Short name T163
Test name
Test status
Simulation time 4033793134 ps
CPU time 112.49 seconds
Started Jul 28 07:24:57 PM PDT 24
Finished Jul 28 07:26:49 PM PDT 24
Peak memory 226136 kb
Host smart-0696ebb5-87aa-4ea1-ba3c-0c2ab2bef9b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776093513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2776093513
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.964374212
Short name T186
Test name
Test status
Simulation time 1310032413 ps
CPU time 11.4 seconds
Started Jul 28 07:24:59 PM PDT 24
Finished Jul 28 07:25:11 PM PDT 24
Peak memory 212580 kb
Host smart-2a1d5d28-9364-43eb-80fe-e598c5abe2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964374212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.964374212
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3159275635
Short name T130
Test name
Test status
Simulation time 139217564 ps
CPU time 6.69 seconds
Started Jul 28 07:24:58 PM PDT 24
Finished Jul 28 07:25:05 PM PDT 24
Peak memory 211944 kb
Host smart-eb78dd6c-d184-411e-9aa8-009f39ee3cb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3159275635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3159275635
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.4118382858
Short name T17
Test name
Test status
Simulation time 795419725 ps
CPU time 10.66 seconds
Started Jul 28 07:25:02 PM PDT 24
Finished Jul 28 07:25:12 PM PDT 24
Peak memory 214280 kb
Host smart-e1967087-7491-4cff-8e03-b3a352cbb034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118382858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.4118382858
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3043406544
Short name T228
Test name
Test status
Simulation time 1118438221 ps
CPU time 15.1 seconds
Started Jul 28 07:24:59 PM PDT 24
Finished Jul 28 07:25:15 PM PDT 24
Peak memory 214548 kb
Host smart-f6cb46b3-f6d5-4a1d-9b70-07558e4e27de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043406544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3043406544
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.698545042
Short name T290
Test name
Test status
Simulation time 495419555 ps
CPU time 7.66 seconds
Started Jul 28 07:25:03 PM PDT 24
Finished Jul 28 07:25:11 PM PDT 24
Peak memory 211764 kb
Host smart-94b28d9a-e25b-41de-937b-70856c0ba182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698545042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.698545042
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4107859837
Short name T344
Test name
Test status
Simulation time 4183145135 ps
CPU time 123.87 seconds
Started Jul 28 07:25:04 PM PDT 24
Finished Jul 28 07:27:08 PM PDT 24
Peak memory 226068 kb
Host smart-d01b6fd0-38d4-4252-98be-db7f5ef9e143
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107859837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4107859837
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.847531009
Short name T242
Test name
Test status
Simulation time 258794895 ps
CPU time 11.16 seconds
Started Jul 28 07:25:02 PM PDT 24
Finished Jul 28 07:25:13 PM PDT 24
Peak memory 212764 kb
Host smart-f8c068c4-ac2b-4f90-bb4b-1311c72a610d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847531009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.847531009
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3388588971
Short name T192
Test name
Test status
Simulation time 680172938 ps
CPU time 6.7 seconds
Started Jul 28 07:25:00 PM PDT 24
Finished Jul 28 07:25:07 PM PDT 24
Peak memory 211916 kb
Host smart-6750931e-eea8-432f-b0b0-f8a4c32707de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3388588971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3388588971
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1733851603
Short name T362
Test name
Test status
Simulation time 523331268 ps
CPU time 12.34 seconds
Started Jul 28 07:24:59 PM PDT 24
Finished Jul 28 07:25:12 PM PDT 24
Peak memory 213940 kb
Host smart-5a708b61-1680-4d1b-8dc0-d5b0f39cd2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733851603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1733851603
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.4164342978
Short name T232
Test name
Test status
Simulation time 375938996 ps
CPU time 21.32 seconds
Started Jul 28 07:25:01 PM PDT 24
Finished Jul 28 07:25:22 PM PDT 24
Peak memory 216028 kb
Host smart-e1e2e39b-5ef6-4f18-8897-0a3ed64e1bf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164342978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.4164342978
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2128521989
Short name T224
Test name
Test status
Simulation time 35212140816 ps
CPU time 7681.99 seconds
Started Jul 28 07:25:05 PM PDT 24
Finished Jul 28 09:33:08 PM PDT 24
Peak memory 228180 kb
Host smart-c0f19050-69ac-4435-8a81-177af4e2b172
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128521989 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2128521989
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1303323182
Short name T353
Test name
Test status
Simulation time 131879042 ps
CPU time 5.13 seconds
Started Jul 28 07:25:04 PM PDT 24
Finished Jul 28 07:25:09 PM PDT 24
Peak memory 211788 kb
Host smart-f60a0dd6-622a-4f37-86ed-4a02d1ea7753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303323182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1303323182
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1919193216
Short name T152
Test name
Test status
Simulation time 2202649521 ps
CPU time 99.72 seconds
Started Jul 28 07:25:01 PM PDT 24
Finished Jul 28 07:26:41 PM PDT 24
Peak memory 238284 kb
Host smart-21a41838-d5c0-4ff2-80ee-82582684a5fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919193216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1919193216
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.816713728
Short name T196
Test name
Test status
Simulation time 169074412 ps
CPU time 9.44 seconds
Started Jul 28 07:25:02 PM PDT 24
Finished Jul 28 07:25:12 PM PDT 24
Peak memory 212788 kb
Host smart-3d1b75da-b24a-4c1b-ad61-8eb0f1058994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816713728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.816713728
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.4079735965
Short name T135
Test name
Test status
Simulation time 381583588 ps
CPU time 5.32 seconds
Started Jul 28 07:25:03 PM PDT 24
Finished Jul 28 07:25:08 PM PDT 24
Peak memory 211940 kb
Host smart-03a4a59b-41b0-4b9d-9636-4096e706849f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4079735965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.4079735965
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.147657096
Short name T272
Test name
Test status
Simulation time 4004124696 ps
CPU time 17.48 seconds
Started Jul 28 07:25:03 PM PDT 24
Finished Jul 28 07:25:21 PM PDT 24
Peak memory 214304 kb
Host smart-c81ff943-3560-43fe-bbe5-7f9e377c1deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147657096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.147657096
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2094389593
Short name T324
Test name
Test status
Simulation time 810806716 ps
CPU time 19.51 seconds
Started Jul 28 07:25:02 PM PDT 24
Finished Jul 28 07:25:21 PM PDT 24
Peak memory 216876 kb
Host smart-31710457-9ec1-4820-bd4d-9d91f8179cd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094389593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2094389593
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3286223443
Short name T236
Test name
Test status
Simulation time 951732844 ps
CPU time 5.26 seconds
Started Jul 28 07:25:06 PM PDT 24
Finished Jul 28 07:25:12 PM PDT 24
Peak memory 211760 kb
Host smart-84721697-4f13-4364-97fa-d0212f719656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286223443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3286223443
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1678258491
Short name T340
Test name
Test status
Simulation time 12237055913 ps
CPU time 78.52 seconds
Started Jul 28 07:25:02 PM PDT 24
Finished Jul 28 07:26:20 PM PDT 24
Peak memory 229028 kb
Host smart-f1a8ff32-2df5-4999-996f-657168b246f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678258491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1678258491
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3974478923
Short name T248
Test name
Test status
Simulation time 1185682255 ps
CPU time 11.01 seconds
Started Jul 28 07:25:06 PM PDT 24
Finished Jul 28 07:25:18 PM PDT 24
Peak memory 212668 kb
Host smart-64165195-44e4-4328-a94c-ff6ed036db74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974478923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3974478923
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1712583532
Short name T162
Test name
Test status
Simulation time 145586693 ps
CPU time 6.5 seconds
Started Jul 28 07:25:02 PM PDT 24
Finished Jul 28 07:25:09 PM PDT 24
Peak memory 211904 kb
Host smart-7de2c788-ece1-4287-8a4a-91835b8aa40b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1712583532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1712583532
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.86311946
Short name T159
Test name
Test status
Simulation time 923886883 ps
CPU time 10.14 seconds
Started Jul 28 07:25:03 PM PDT 24
Finished Jul 28 07:25:13 PM PDT 24
Peak memory 214656 kb
Host smart-9f75f6b2-e68f-4eda-bd5e-96d3d464d9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86311946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.86311946
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.894764516
Short name T336
Test name
Test status
Simulation time 627037476 ps
CPU time 11.99 seconds
Started Jul 28 07:25:03 PM PDT 24
Finished Jul 28 07:25:15 PM PDT 24
Peak memory 214520 kb
Host smart-a026fa28-56d7-4734-bf74-2bc77940ec14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894764516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.894764516
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2834814119
Short name T53
Test name
Test status
Simulation time 86239635308 ps
CPU time 3435.12 seconds
Started Jul 28 07:25:07 PM PDT 24
Finished Jul 28 08:22:23 PM PDT 24
Peak memory 244168 kb
Host smart-16847ece-4bb3-4774-9d1e-f1ad06759128
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834814119 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2834814119
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2291540412
Short name T261
Test name
Test status
Simulation time 87014405 ps
CPU time 4.22 seconds
Started Jul 28 07:25:08 PM PDT 24
Finished Jul 28 07:25:12 PM PDT 24
Peak memory 211756 kb
Host smart-a3156e39-4fe8-45f4-be7e-d588e1079f42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291540412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2291540412
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3058652890
Short name T284
Test name
Test status
Simulation time 338824327 ps
CPU time 11.23 seconds
Started Jul 28 07:25:10 PM PDT 24
Finished Jul 28 07:25:22 PM PDT 24
Peak memory 212688 kb
Host smart-77f1594f-fb59-4290-9a38-d97d0d67b925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058652890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3058652890
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3659092728
Short name T179
Test name
Test status
Simulation time 401159303 ps
CPU time 5.53 seconds
Started Jul 28 07:25:06 PM PDT 24
Finished Jul 28 07:25:12 PM PDT 24
Peak memory 211892 kb
Host smart-b1cd3934-fa5a-4a11-bf0a-893022eea9ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3659092728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3659092728
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.8357237
Short name T287
Test name
Test status
Simulation time 273638483 ps
CPU time 12.12 seconds
Started Jul 28 07:25:07 PM PDT 24
Finished Jul 28 07:25:19 PM PDT 24
Peak memory 214476 kb
Host smart-28316e1c-4658-4d9b-97c3-188bac35b7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8357237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.8357237
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1012672752
Short name T227
Test name
Test status
Simulation time 675469893 ps
CPU time 29.84 seconds
Started Jul 28 07:25:05 PM PDT 24
Finished Jul 28 07:25:35 PM PDT 24
Peak memory 217036 kb
Host smart-ba8de91f-a003-471c-af97-1e6e9cccb45d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012672752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1012672752
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2221482103
Short name T191
Test name
Test status
Simulation time 783431136849 ps
CPU time 2866.75 seconds
Started Jul 28 07:25:09 PM PDT 24
Finished Jul 28 08:12:56 PM PDT 24
Peak memory 244580 kb
Host smart-b142f97f-1f93-4199-8bb1-9738a14e8fde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221482103 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2221482103
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1188862207
Short name T36
Test name
Test status
Simulation time 348083537 ps
CPU time 4.2 seconds
Started Jul 28 07:25:06 PM PDT 24
Finished Jul 28 07:25:10 PM PDT 24
Peak memory 211780 kb
Host smart-b750f30a-db13-4862-9d8c-46432c32a3b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188862207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1188862207
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.4283162021
Short name T369
Test name
Test status
Simulation time 25609912272 ps
CPU time 224.89 seconds
Started Jul 28 07:25:06 PM PDT 24
Finished Jul 28 07:28:51 PM PDT 24
Peak memory 225896 kb
Host smart-949b0d16-734c-4993-8cd9-6b03e374f3a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283162021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.4283162021
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.92217524
Short name T164
Test name
Test status
Simulation time 542842412 ps
CPU time 10.96 seconds
Started Jul 28 07:25:06 PM PDT 24
Finished Jul 28 07:25:17 PM PDT 24
Peak memory 211864 kb
Host smart-17058128-211b-4b0a-a1f7-401404da7ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92217524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.92217524
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.200685273
Short name T11
Test name
Test status
Simulation time 559943916 ps
CPU time 6.26 seconds
Started Jul 28 07:25:09 PM PDT 24
Finished Jul 28 07:25:15 PM PDT 24
Peak memory 211852 kb
Host smart-5d7feaa5-f002-4133-9fe7-92457731e784
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=200685273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.200685273
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3319373100
Short name T169
Test name
Test status
Simulation time 194950784 ps
CPU time 10.53 seconds
Started Jul 28 07:25:07 PM PDT 24
Finished Jul 28 07:25:18 PM PDT 24
Peak memory 214644 kb
Host smart-641b17f5-083c-4590-9fe2-ae372c1d95ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319373100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3319373100
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3747822355
Short name T198
Test name
Test status
Simulation time 806836958 ps
CPU time 22.94 seconds
Started Jul 28 07:25:10 PM PDT 24
Finished Jul 28 07:25:33 PM PDT 24
Peak memory 216148 kb
Host smart-220da668-6c8b-4902-aabb-75ee94c6e24c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747822355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3747822355
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.980894295
Short name T263
Test name
Test status
Simulation time 60300088765 ps
CPU time 2612.23 seconds
Started Jul 28 07:25:05 PM PDT 24
Finished Jul 28 08:08:37 PM PDT 24
Peak memory 243572 kb
Host smart-80864541-8723-4b37-88e6-426d77b7af94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980894295 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.980894295
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3152068101
Short name T132
Test name
Test status
Simulation time 543432069 ps
CPU time 5.15 seconds
Started Jul 28 07:23:59 PM PDT 24
Finished Jul 28 07:24:04 PM PDT 24
Peak memory 211804 kb
Host smart-77cda71b-ee78-4e96-bb8b-c067aa781a97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152068101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3152068101
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3937773028
Short name T300
Test name
Test status
Simulation time 4658544900 ps
CPU time 169.72 seconds
Started Jul 28 07:23:55 PM PDT 24
Finished Jul 28 07:26:45 PM PDT 24
Peak memory 234500 kb
Host smart-c0b1acce-fbbd-46db-be4b-98d1eda93bed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937773028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3937773028
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4163335654
Short name T355
Test name
Test status
Simulation time 3557382346 ps
CPU time 11.38 seconds
Started Jul 28 07:23:59 PM PDT 24
Finished Jul 28 07:24:10 PM PDT 24
Peak memory 212660 kb
Host smart-08135f49-f17d-4ff0-ba37-1f08e7156110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163335654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.4163335654
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3588393944
Short name T247
Test name
Test status
Simulation time 97798841 ps
CPU time 5.73 seconds
Started Jul 28 07:23:56 PM PDT 24
Finished Jul 28 07:24:01 PM PDT 24
Peak memory 211872 kb
Host smart-2953e102-5b4c-4ca3-8eeb-34fcf8820a36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3588393944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3588393944
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3638479248
Short name T327
Test name
Test status
Simulation time 186529276 ps
CPU time 9.7 seconds
Started Jul 28 07:23:56 PM PDT 24
Finished Jul 28 07:24:05 PM PDT 24
Peak memory 214108 kb
Host smart-b2f9d860-148d-40b3-8afb-bcb620bd4193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638479248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3638479248
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2358887674
Short name T231
Test name
Test status
Simulation time 516975432 ps
CPU time 12.13 seconds
Started Jul 28 07:23:58 PM PDT 24
Finished Jul 28 07:24:10 PM PDT 24
Peak memory 214708 kb
Host smart-89de0f20-9397-4426-a89e-13a47d136045
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358887674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2358887674
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2928323148
Short name T175
Test name
Test status
Simulation time 90313524 ps
CPU time 4.47 seconds
Started Jul 28 07:23:58 PM PDT 24
Finished Jul 28 07:24:03 PM PDT 24
Peak memory 211812 kb
Host smart-f8f5d974-3b41-450a-8cc6-179335c51b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928323148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2928323148
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2377313441
Short name T335
Test name
Test status
Simulation time 2953871744 ps
CPU time 152.32 seconds
Started Jul 28 07:23:59 PM PDT 24
Finished Jul 28 07:26:31 PM PDT 24
Peak memory 238264 kb
Host smart-58cc8425-657d-4a71-a307-b2d5b10b0800
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377313441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2377313441
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2525142503
Short name T183
Test name
Test status
Simulation time 257087853 ps
CPU time 11.12 seconds
Started Jul 28 07:23:57 PM PDT 24
Finished Jul 28 07:24:08 PM PDT 24
Peak memory 211920 kb
Host smart-fbc26469-fff1-42eb-a4ce-6e5c48e8febb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525142503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2525142503
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2151054795
Short name T270
Test name
Test status
Simulation time 142197809 ps
CPU time 6.57 seconds
Started Jul 28 07:23:59 PM PDT 24
Finished Jul 28 07:24:05 PM PDT 24
Peak memory 211940 kb
Host smart-f23665aa-ca2a-4383-a903-6bf9fc766191
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2151054795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2151054795
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.363146512
Short name T120
Test name
Test status
Simulation time 791812970 ps
CPU time 9.55 seconds
Started Jul 28 07:23:58 PM PDT 24
Finished Jul 28 07:24:08 PM PDT 24
Peak memory 214736 kb
Host smart-46102d5e-5900-4e74-a774-ca6ef8723de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363146512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.363146512
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1325508016
Short name T55
Test name
Test status
Simulation time 4083223457 ps
CPU time 33.81 seconds
Started Jul 28 07:23:58 PM PDT 24
Finished Jul 28 07:24:32 PM PDT 24
Peak memory 216336 kb
Host smart-ccf6369a-fa28-4985-acba-97cac8d5dae1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325508016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1325508016
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.758242644
Short name T278
Test name
Test status
Simulation time 2063248277 ps
CPU time 7.6 seconds
Started Jul 28 07:24:03 PM PDT 24
Finished Jul 28 07:24:11 PM PDT 24
Peak memory 211808 kb
Host smart-7bb9bb44-99b2-44ea-a769-fa4f5e58db4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758242644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.758242644
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3314795782
Short name T363
Test name
Test status
Simulation time 7282656488 ps
CPU time 133.9 seconds
Started Jul 28 07:24:03 PM PDT 24
Finished Jul 28 07:26:17 PM PDT 24
Peak memory 234176 kb
Host smart-4a92d3c7-8caa-461e-bd60-1f8beb9420c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314795782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3314795782
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.218870718
Short name T138
Test name
Test status
Simulation time 1040711224 ps
CPU time 11.4 seconds
Started Jul 28 07:24:01 PM PDT 24
Finished Jul 28 07:24:13 PM PDT 24
Peak memory 212664 kb
Host smart-7404fa88-627e-4d30-af8d-5566377e6948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218870718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.218870718
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.410823975
Short name T187
Test name
Test status
Simulation time 242096688 ps
CPU time 5.68 seconds
Started Jul 28 07:24:05 PM PDT 24
Finished Jul 28 07:24:11 PM PDT 24
Peak memory 211924 kb
Host smart-f1d50131-b75d-4663-8564-3acdd9f15716
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=410823975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.410823975
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3974771257
Short name T318
Test name
Test status
Simulation time 695624200 ps
CPU time 9.86 seconds
Started Jul 28 07:24:00 PM PDT 24
Finished Jul 28 07:24:10 PM PDT 24
Peak memory 214472 kb
Host smart-cce58105-9f22-46c9-a77d-43ef4d2a1b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974771257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3974771257
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2769883806
Short name T285
Test name
Test status
Simulation time 1611561366 ps
CPU time 38.49 seconds
Started Jul 28 07:24:05 PM PDT 24
Finished Jul 28 07:24:43 PM PDT 24
Peak memory 217408 kb
Host smart-e2467ad7-2475-4a18-8ab6-3c316b4e2b4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769883806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2769883806
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1122270887
Short name T61
Test name
Test status
Simulation time 127975683 ps
CPU time 5.41 seconds
Started Jul 28 07:24:00 PM PDT 24
Finished Jul 28 07:24:05 PM PDT 24
Peak memory 211804 kb
Host smart-ec694343-70c1-495d-96b7-f3f5bb1a544e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122270887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1122270887
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.378613664
Short name T259
Test name
Test status
Simulation time 5144816101 ps
CPU time 112.16 seconds
Started Jul 28 07:24:01 PM PDT 24
Finished Jul 28 07:25:54 PM PDT 24
Peak memory 214036 kb
Host smart-cc20e40d-98f4-46b2-a485-3ea48739740d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378613664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.378613664
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2581781164
Short name T45
Test name
Test status
Simulation time 876506404 ps
CPU time 9.55 seconds
Started Jul 28 07:23:58 PM PDT 24
Finished Jul 28 07:24:08 PM PDT 24
Peak memory 212688 kb
Host smart-f88a54eb-1874-4972-8f25-f634e0c1cde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581781164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2581781164
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.578113092
Short name T341
Test name
Test status
Simulation time 143633757 ps
CPU time 6.62 seconds
Started Jul 28 07:24:03 PM PDT 24
Finished Jul 28 07:24:10 PM PDT 24
Peak memory 211912 kb
Host smart-d9f18b69-8fc4-445b-b9b8-5a6d35bbc734
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=578113092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.578113092
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3799016041
Short name T329
Test name
Test status
Simulation time 187415201 ps
CPU time 10.86 seconds
Started Jul 28 07:24:01 PM PDT 24
Finished Jul 28 07:24:12 PM PDT 24
Peak memory 214624 kb
Host smart-8d50bf15-c111-4e60-8c7c-efb6ed086ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799016041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3799016041
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3783525309
Short name T332
Test name
Test status
Simulation time 338815240 ps
CPU time 13.76 seconds
Started Jul 28 07:24:01 PM PDT 24
Finished Jul 28 07:24:15 PM PDT 24
Peak memory 214724 kb
Host smart-b1ec8cc4-5b7b-4f03-9be1-3bbe95c4a143
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783525309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3783525309
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1362146720
Short name T104
Test name
Test status
Simulation time 1072983286876 ps
CPU time 2438.23 seconds
Started Jul 28 07:24:00 PM PDT 24
Finished Jul 28 08:04:39 PM PDT 24
Peak memory 244584 kb
Host smart-c96ba203-940a-4fda-a4c7-24c92fa3f707
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362146720 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.1362146720
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1294857111
Short name T294
Test name
Test status
Simulation time 258326069 ps
CPU time 5.34 seconds
Started Jul 28 07:24:05 PM PDT 24
Finished Jul 28 07:24:10 PM PDT 24
Peak memory 211784 kb
Host smart-458183af-e79a-4b0a-a4ab-3a589ede6a68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294857111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1294857111
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1796376642
Short name T351
Test name
Test status
Simulation time 9562414598 ps
CPU time 135.72 seconds
Started Jul 28 07:24:05 PM PDT 24
Finished Jul 28 07:26:20 PM PDT 24
Peak memory 234644 kb
Host smart-4f8d7785-7789-45e4-a174-da65b1e2e377
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796376642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1796376642
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.78560567
Short name T354
Test name
Test status
Simulation time 509628454 ps
CPU time 10.93 seconds
Started Jul 28 07:24:06 PM PDT 24
Finished Jul 28 07:24:17 PM PDT 24
Peak memory 212764 kb
Host smart-60d32c12-5593-4180-89a5-7ad0b2c97d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78560567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.78560567
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1506462151
Short name T147
Test name
Test status
Simulation time 98487994 ps
CPU time 5.46 seconds
Started Jul 28 07:24:08 PM PDT 24
Finished Jul 28 07:24:13 PM PDT 24
Peak memory 211916 kb
Host smart-a75e52f3-92db-4ce8-ab17-1b61ace656dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1506462151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1506462151
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2374009083
Short name T31
Test name
Test status
Simulation time 379379729 ps
CPU time 10.75 seconds
Started Jul 28 07:24:01 PM PDT 24
Finished Jul 28 07:24:12 PM PDT 24
Peak memory 214712 kb
Host smart-06faeb9b-7698-451d-b445-b76649478ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374009083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2374009083
Directory /workspace/9.rom_ctrl_smoke/latest
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