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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.29 96.89 91.99 97.67 100.00 98.62 97.45 98.37


Total test records in report: 411
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T294 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.652402519 Jul 29 06:09:45 PM PDT 24 Jul 29 06:09:52 PM PDT 24 136654840 ps
T295 /workspace/coverage/default/42.rom_ctrl_stress_all.1149883450 Jul 29 06:09:56 PM PDT 24 Jul 29 06:10:13 PM PDT 24 694103690 ps
T296 /workspace/coverage/default/28.rom_ctrl_stress_all.376505326 Jul 29 06:09:30 PM PDT 24 Jul 29 06:09:45 PM PDT 24 548035903 ps
T297 /workspace/coverage/default/22.rom_ctrl_stress_all.983977082 Jul 29 06:09:16 PM PDT 24 Jul 29 06:09:33 PM PDT 24 304403158 ps
T298 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1714661935 Jul 29 06:09:12 PM PDT 24 Jul 29 06:09:19 PM PDT 24 704573961 ps
T299 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.725364563 Jul 29 06:09:03 PM PDT 24 Jul 29 06:10:09 PM PDT 24 6994028961 ps
T300 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2931188969 Jul 29 06:09:12 PM PDT 24 Jul 29 06:09:18 PM PDT 24 98994838 ps
T301 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.699734984 Jul 29 06:09:24 PM PDT 24 Jul 29 06:11:32 PM PDT 24 19055360829 ps
T302 /workspace/coverage/default/27.rom_ctrl_alert_test.2281863015 Jul 29 06:09:30 PM PDT 24 Jul 29 06:09:34 PM PDT 24 520598361 ps
T303 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.4293313403 Jul 29 06:09:22 PM PDT 24 Jul 29 06:11:07 PM PDT 24 6618481332 ps
T304 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3871236343 Jul 29 06:08:45 PM PDT 24 Jul 29 06:10:14 PM PDT 24 1562736035 ps
T305 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3787324777 Jul 29 06:09:05 PM PDT 24 Jul 29 06:10:17 PM PDT 24 1270955207 ps
T306 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3345087270 Jul 29 06:09:12 PM PDT 24 Jul 29 06:09:22 PM PDT 24 173754114 ps
T307 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2722791489 Jul 29 06:09:58 PM PDT 24 Jul 29 06:10:08 PM PDT 24 754062049 ps
T308 /workspace/coverage/default/36.rom_ctrl_alert_test.3428074656 Jul 29 06:09:46 PM PDT 24 Jul 29 06:09:50 PM PDT 24 418582285 ps
T309 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3146831565 Jul 29 06:09:58 PM PDT 24 Jul 29 06:13:26 PM PDT 24 15712074230 ps
T109 /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1707136412 Jul 29 06:09:25 PM PDT 24 Jul 29 06:25:02 PM PDT 24 46423766323 ps
T310 /workspace/coverage/default/30.rom_ctrl_stress_all.2044845813 Jul 29 06:09:41 PM PDT 24 Jul 29 06:09:53 PM PDT 24 729802593 ps
T311 /workspace/coverage/default/31.rom_ctrl_alert_test.4194036544 Jul 29 06:09:38 PM PDT 24 Jul 29 06:09:43 PM PDT 24 131649837 ps
T312 /workspace/coverage/default/5.rom_ctrl_stress_all.3001161181 Jul 29 06:09:05 PM PDT 24 Jul 29 06:09:19 PM PDT 24 292404470 ps
T313 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3369892372 Jul 29 06:09:50 PM PDT 24 Jul 29 06:10:00 PM PDT 24 388246647 ps
T314 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1698498310 Jul 29 06:08:58 PM PDT 24 Jul 29 06:10:29 PM PDT 24 6788054047 ps
T315 /workspace/coverage/default/36.rom_ctrl_stress_all.2013091390 Jul 29 06:09:44 PM PDT 24 Jul 29 06:09:55 PM PDT 24 754642723 ps
T316 /workspace/coverage/default/23.rom_ctrl_alert_test.462927514 Jul 29 06:09:23 PM PDT 24 Jul 29 06:09:29 PM PDT 24 132318898 ps
T317 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.454007587 Jul 29 06:09:47 PM PDT 24 Jul 29 06:09:58 PM PDT 24 3107078017 ps
T318 /workspace/coverage/default/8.rom_ctrl_stress_all.1521575693 Jul 29 06:08:59 PM PDT 24 Jul 29 06:09:15 PM PDT 24 1134264796 ps
T319 /workspace/coverage/default/7.rom_ctrl_stress_all.3658789246 Jul 29 06:08:57 PM PDT 24 Jul 29 06:09:08 PM PDT 24 383028928 ps
T320 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.25350879 Jul 29 06:09:39 PM PDT 24 Jul 29 06:09:49 PM PDT 24 694691904 ps
T321 /workspace/coverage/default/26.rom_ctrl_stress_all.832716632 Jul 29 06:09:28 PM PDT 24 Jul 29 06:09:37 PM PDT 24 1242586264 ps
T43 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.509431026 Jul 29 06:09:55 PM PDT 24 Jul 29 06:10:06 PM PDT 24 252986660 ps
T52 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1031687908 Jul 29 07:02:11 PM PDT 24 Jul 29 07:02:47 PM PDT 24 189767575 ps
T55 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3174291605 Jul 29 07:02:55 PM PDT 24 Jul 29 07:03:00 PM PDT 24 128222016 ps
T56 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.32325159 Jul 29 07:02:38 PM PDT 24 Jul 29 07:02:42 PM PDT 24 348422755 ps
T322 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1524391005 Jul 29 07:02:23 PM PDT 24 Jul 29 07:02:28 PM PDT 24 522362069 ps
T53 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3516618501 Jul 29 07:02:55 PM PDT 24 Jul 29 07:04:13 PM PDT 24 639186943 ps
T323 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.350425427 Jul 29 07:02:12 PM PDT 24 Jul 29 07:02:17 PM PDT 24 132693498 ps
T100 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2546563170 Jul 29 07:02:25 PM PDT 24 Jul 29 07:02:32 PM PDT 24 349955710 ps
T324 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.290014368 Jul 29 07:02:55 PM PDT 24 Jul 29 07:03:03 PM PDT 24 509423443 ps
T62 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.854658143 Jul 29 07:02:17 PM PDT 24 Jul 29 07:02:22 PM PDT 24 225047547 ps
T97 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.44496795 Jul 29 07:02:30 PM PDT 24 Jul 29 07:02:36 PM PDT 24 1720764018 ps
T325 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3905637835 Jul 29 07:02:13 PM PDT 24 Jul 29 07:02:18 PM PDT 24 337088132 ps
T326 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1378172443 Jul 29 07:02:11 PM PDT 24 Jul 29 07:02:15 PM PDT 24 85583720 ps
T101 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4166618829 Jul 29 07:02:54 PM PDT 24 Jul 29 07:03:02 PM PDT 24 983490343 ps
T327 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1613922123 Jul 29 07:02:54 PM PDT 24 Jul 29 07:03:00 PM PDT 24 377543887 ps
T54 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2839205447 Jul 29 07:02:30 PM PDT 24 Jul 29 07:03:07 PM PDT 24 521480697 ps
T111 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2249786246 Jul 29 07:02:54 PM PDT 24 Jul 29 07:04:04 PM PDT 24 891720971 ps
T63 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4277213603 Jul 29 07:02:38 PM PDT 24 Jul 29 07:02:43 PM PDT 24 419119115 ps
T328 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1658300308 Jul 29 07:02:12 PM PDT 24 Jul 29 07:02:17 PM PDT 24 1243180532 ps
T114 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2540301780 Jul 29 07:02:45 PM PDT 24 Jul 29 07:03:23 PM PDT 24 230528461 ps
T329 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3104310166 Jul 29 07:02:36 PM PDT 24 Jul 29 07:02:40 PM PDT 24 178862070 ps
T330 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.466986010 Jul 29 07:02:43 PM PDT 24 Jul 29 07:02:49 PM PDT 24 151082175 ps
T64 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1119681010 Jul 29 07:02:31 PM PDT 24 Jul 29 07:02:37 PM PDT 24 501222924 ps
T331 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2796816325 Jul 29 07:02:29 PM PDT 24 Jul 29 07:02:34 PM PDT 24 89178173 ps
T112 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.398573168 Jul 29 07:02:48 PM PDT 24 Jul 29 07:03:30 PM PDT 24 1385956941 ps
T332 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1439113957 Jul 29 07:02:46 PM PDT 24 Jul 29 07:02:55 PM PDT 24 128760650 ps
T102 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4292403166 Jul 29 07:02:40 PM PDT 24 Jul 29 07:02:46 PM PDT 24 130243992 ps
T333 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3746529455 Jul 29 07:02:40 PM PDT 24 Jul 29 07:02:45 PM PDT 24 105429188 ps
T65 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3465782303 Jul 29 07:02:32 PM PDT 24 Jul 29 07:02:40 PM PDT 24 1757879876 ps
T66 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3403610310 Jul 29 07:02:10 PM PDT 24 Jul 29 07:02:19 PM PDT 24 1087420509 ps
T334 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1781927052 Jul 29 07:02:31 PM PDT 24 Jul 29 07:02:39 PM PDT 24 444137023 ps
T335 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1844994279 Jul 29 07:02:42 PM PDT 24 Jul 29 07:02:50 PM PDT 24 560963368 ps
T336 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.428679675 Jul 29 07:02:48 PM PDT 24 Jul 29 07:02:53 PM PDT 24 349530934 ps
T337 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2559281459 Jul 29 07:02:42 PM PDT 24 Jul 29 07:02:47 PM PDT 24 556041459 ps
T98 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3102619229 Jul 29 07:02:23 PM PDT 24 Jul 29 07:02:29 PM PDT 24 129877784 ps
T338 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.204429776 Jul 29 07:02:30 PM PDT 24 Jul 29 07:02:35 PM PDT 24 354661316 ps
T67 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2137133110 Jul 29 07:02:30 PM PDT 24 Jul 29 07:03:02 PM PDT 24 2109612337 ps
T339 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3324131556 Jul 29 07:02:29 PM PDT 24 Jul 29 07:02:35 PM PDT 24 180471752 ps
T68 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2197362634 Jul 29 07:02:13 PM PDT 24 Jul 29 07:02:23 PM PDT 24 507024914 ps
T117 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1335998468 Jul 29 07:02:36 PM PDT 24 Jul 29 07:03:14 PM PDT 24 938600818 ps
T340 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2358711526 Jul 29 07:02:28 PM PDT 24 Jul 29 07:02:33 PM PDT 24 1035316406 ps
T341 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4037509858 Jul 29 07:02:14 PM PDT 24 Jul 29 07:02:20 PM PDT 24 129969389 ps
T69 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2149110197 Jul 29 07:02:16 PM PDT 24 Jul 29 07:02:44 PM PDT 24 2210467254 ps
T115 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1028200360 Jul 29 07:02:55 PM PDT 24 Jul 29 07:04:04 PM PDT 24 248956550 ps
T70 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1475516105 Jul 29 07:02:56 PM PDT 24 Jul 29 07:03:01 PM PDT 24 128179862 ps
T99 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1039055046 Jul 29 07:02:22 PM PDT 24 Jul 29 07:02:26 PM PDT 24 176529685 ps
T342 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.101283896 Jul 29 07:02:42 PM PDT 24 Jul 29 07:02:46 PM PDT 24 90954664 ps
T71 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1840197651 Jul 29 07:02:44 PM PDT 24 Jul 29 07:02:50 PM PDT 24 326846768 ps
T343 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.648921002 Jul 29 07:02:17 PM PDT 24 Jul 29 07:02:22 PM PDT 24 516138504 ps
T344 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2401708568 Jul 29 07:02:13 PM PDT 24 Jul 29 07:02:21 PM PDT 24 92189892 ps
T113 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1369587573 Jul 29 07:02:32 PM PDT 24 Jul 29 07:03:42 PM PDT 24 546710340 ps
T345 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1602516600 Jul 29 07:02:11 PM PDT 24 Jul 29 07:02:17 PM PDT 24 1895479774 ps
T346 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1053151195 Jul 29 07:02:44 PM PDT 24 Jul 29 07:02:54 PM PDT 24 979074204 ps
T347 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.303077461 Jul 29 07:02:44 PM PDT 24 Jul 29 07:02:49 PM PDT 24 96893761 ps
T80 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1273207973 Jul 29 07:02:31 PM PDT 24 Jul 29 07:02:36 PM PDT 24 128483358 ps
T348 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.973460923 Jul 29 07:02:16 PM PDT 24 Jul 29 07:02:25 PM PDT 24 519853644 ps
T120 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.827036437 Jul 29 07:02:46 PM PDT 24 Jul 29 07:03:23 PM PDT 24 152579416 ps
T81 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3720940361 Jul 29 07:02:44 PM PDT 24 Jul 29 07:02:48 PM PDT 24 172739717 ps
T349 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3624882390 Jul 29 07:02:47 PM PDT 24 Jul 29 07:02:51 PM PDT 24 85687431 ps
T350 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.353230523 Jul 29 07:02:43 PM PDT 24 Jul 29 07:02:52 PM PDT 24 259116068 ps
T351 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.243105502 Jul 29 07:02:28 PM PDT 24 Jul 29 07:02:33 PM PDT 24 498192012 ps
T82 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.582900316 Jul 29 07:02:17 PM PDT 24 Jul 29 07:02:23 PM PDT 24 249986102 ps
T352 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3517990053 Jul 29 07:02:31 PM PDT 24 Jul 29 07:02:36 PM PDT 24 256093292 ps
T353 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1178201665 Jul 29 07:02:45 PM PDT 24 Jul 29 07:02:50 PM PDT 24 175496178 ps
T354 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3897917267 Jul 29 07:02:12 PM PDT 24 Jul 29 07:02:17 PM PDT 24 128450017 ps
T355 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4042129330 Jul 29 07:02:54 PM PDT 24 Jul 29 07:02:59 PM PDT 24 262348941 ps
T356 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3495091491 Jul 29 07:02:23 PM PDT 24 Jul 29 07:02:28 PM PDT 24 126992913 ps
T357 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.36033529 Jul 29 07:02:31 PM PDT 24 Jul 29 07:02:36 PM PDT 24 86097926 ps
T358 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2733455014 Jul 29 07:02:37 PM PDT 24 Jul 29 07:02:42 PM PDT 24 97011501 ps
T110 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.282888794 Jul 29 07:02:46 PM PDT 24 Jul 29 07:03:05 PM PDT 24 1629710297 ps
T118 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3483167636 Jul 29 07:02:22 PM PDT 24 Jul 29 07:03:36 PM PDT 24 991709994 ps
T359 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1527498572 Jul 29 07:02:37 PM PDT 24 Jul 29 07:03:47 PM PDT 24 437156655 ps
T360 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1394261480 Jul 29 07:02:54 PM PDT 24 Jul 29 07:02:59 PM PDT 24 129088416 ps
T361 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.818839122 Jul 29 07:02:31 PM PDT 24 Jul 29 07:02:36 PM PDT 24 194945303 ps
T362 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2020238798 Jul 29 07:02:33 PM PDT 24 Jul 29 07:02:43 PM PDT 24 529979101 ps
T363 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1181742904 Jul 29 07:02:13 PM PDT 24 Jul 29 07:02:19 PM PDT 24 260270875 ps
T364 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1457035232 Jul 29 07:02:30 PM PDT 24 Jul 29 07:02:38 PM PDT 24 918893170 ps
T85 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.971506806 Jul 29 07:02:53 PM PDT 24 Jul 29 07:02:59 PM PDT 24 262028552 ps
T365 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3828091850 Jul 29 07:02:30 PM PDT 24 Jul 29 07:02:38 PM PDT 24 132608031 ps
T366 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4177621361 Jul 29 07:02:17 PM PDT 24 Jul 29 07:02:54 PM PDT 24 640881829 ps
T86 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.556560615 Jul 29 07:02:11 PM PDT 24 Jul 29 07:02:15 PM PDT 24 89547601 ps
T367 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4240016195 Jul 29 07:02:18 PM PDT 24 Jul 29 07:02:23 PM PDT 24 90163945 ps
T368 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3616563951 Jul 29 07:02:45 PM PDT 24 Jul 29 07:02:51 PM PDT 24 251441528 ps
T83 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3869173701 Jul 29 07:02:40 PM PDT 24 Jul 29 07:02:59 PM PDT 24 2113840800 ps
T369 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3730277743 Jul 29 07:02:14 PM PDT 24 Jul 29 07:02:22 PM PDT 24 498052830 ps
T116 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1210431720 Jul 29 07:02:44 PM PDT 24 Jul 29 07:03:52 PM PDT 24 1317922126 ps
T370 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1362544742 Jul 29 07:02:54 PM PDT 24 Jul 29 07:02:59 PM PDT 24 382152970 ps
T371 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.835412660 Jul 29 07:02:44 PM PDT 24 Jul 29 07:02:49 PM PDT 24 528136849 ps
T84 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2907000897 Jul 29 07:02:50 PM PDT 24 Jul 29 07:03:09 PM PDT 24 4031130455 ps
T372 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4117196226 Jul 29 07:02:48 PM PDT 24 Jul 29 07:02:55 PM PDT 24 831062312 ps
T373 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3548099036 Jul 29 07:02:37 PM PDT 24 Jul 29 07:02:42 PM PDT 24 463322927 ps
T374 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3515618468 Jul 29 07:02:31 PM PDT 24 Jul 29 07:02:36 PM PDT 24 832999653 ps
T375 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1890436658 Jul 29 07:02:31 PM PDT 24 Jul 29 07:03:09 PM PDT 24 727386476 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.539953988 Jul 29 07:02:18 PM PDT 24 Jul 29 07:02:23 PM PDT 24 685965447 ps
T121 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.507552300 Jul 29 07:02:43 PM PDT 24 Jul 29 07:03:20 PM PDT 24 315156278 ps
T377 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2728814761 Jul 29 07:02:32 PM PDT 24 Jul 29 07:02:38 PM PDT 24 828602026 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3412648806 Jul 29 07:02:23 PM PDT 24 Jul 29 07:02:28 PM PDT 24 495234341 ps
T379 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.15106244 Jul 29 07:02:38 PM PDT 24 Jul 29 07:02:44 PM PDT 24 85493050 ps
T380 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2635816904 Jul 29 07:02:29 PM PDT 24 Jul 29 07:02:35 PM PDT 24 262459787 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3451306371 Jul 29 07:02:17 PM PDT 24 Jul 29 07:02:28 PM PDT 24 160275575 ps
T119 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3160573755 Jul 29 07:02:29 PM PDT 24 Jul 29 07:03:38 PM PDT 24 310754624 ps
T382 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4208839459 Jul 29 07:02:45 PM PDT 24 Jul 29 07:02:50 PM PDT 24 271298351 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2044777207 Jul 29 07:02:18 PM PDT 24 Jul 29 07:02:23 PM PDT 24 241936436 ps
T384 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1067866185 Jul 29 07:02:48 PM PDT 24 Jul 29 07:02:55 PM PDT 24 504265446 ps
T385 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.91351833 Jul 29 07:02:28 PM PDT 24 Jul 29 07:02:37 PM PDT 24 181937827 ps
T87 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3614994732 Jul 29 07:02:26 PM PDT 24 Jul 29 07:02:48 PM PDT 24 2253715456 ps
T386 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2972380408 Jul 29 07:02:49 PM PDT 24 Jul 29 07:02:54 PM PDT 24 431771620 ps
T387 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.708257802 Jul 29 07:02:18 PM PDT 24 Jul 29 07:02:24 PM PDT 24 251418434 ps
T388 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1106272248 Jul 29 07:02:23 PM PDT 24 Jul 29 07:03:00 PM PDT 24 700298582 ps
T389 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1796133422 Jul 29 07:02:28 PM PDT 24 Jul 29 07:02:34 PM PDT 24 536941088 ps
T390 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3364025485 Jul 29 07:02:49 PM PDT 24 Jul 29 07:02:54 PM PDT 24 652589918 ps
T391 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.139993460 Jul 29 07:02:29 PM PDT 24 Jul 29 07:02:33 PM PDT 24 335184281 ps
T392 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2155378168 Jul 29 07:02:55 PM PDT 24 Jul 29 07:03:04 PM PDT 24 186334585 ps
T393 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1102029195 Jul 29 07:02:46 PM PDT 24 Jul 29 07:02:50 PM PDT 24 309667211 ps
T394 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.893215086 Jul 29 07:02:32 PM PDT 24 Jul 29 07:02:40 PM PDT 24 145097336 ps
T395 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2241053990 Jul 29 07:02:15 PM PDT 24 Jul 29 07:02:52 PM PDT 24 445854309 ps
T396 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2523505266 Jul 29 07:02:37 PM PDT 24 Jul 29 07:02:44 PM PDT 24 90159809 ps
T397 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3396229141 Jul 29 07:02:28 PM PDT 24 Jul 29 07:02:34 PM PDT 24 489977661 ps
T398 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3500950755 Jul 29 07:02:43 PM PDT 24 Jul 29 07:03:52 PM PDT 24 250937322 ps
T399 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2560068289 Jul 29 07:02:36 PM PDT 24 Jul 29 07:02:44 PM PDT 24 91500800 ps
T400 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1784081166 Jul 29 07:02:25 PM PDT 24 Jul 29 07:02:30 PM PDT 24 405849042 ps
T401 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1258647503 Jul 29 07:02:47 PM PDT 24 Jul 29 07:02:52 PM PDT 24 251526942 ps
T402 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1529055805 Jul 29 07:02:55 PM PDT 24 Jul 29 07:03:01 PM PDT 24 545327363 ps
T403 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.323896077 Jul 29 07:02:28 PM PDT 24 Jul 29 07:02:33 PM PDT 24 132349178 ps
T404 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3787775714 Jul 29 07:02:32 PM PDT 24 Jul 29 07:02:38 PM PDT 24 88215711 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.9255137 Jul 29 07:02:16 PM PDT 24 Jul 29 07:02:24 PM PDT 24 1971894122 ps
T406 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.34500245 Jul 29 07:02:12 PM PDT 24 Jul 29 07:02:21 PM PDT 24 175566214 ps
T407 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3750584042 Jul 29 07:02:13 PM PDT 24 Jul 29 07:02:18 PM PDT 24 129313270 ps
T408 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.462704937 Jul 29 07:02:36 PM PDT 24 Jul 29 07:02:41 PM PDT 24 130610755 ps
T409 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1325175413 Jul 29 07:02:48 PM PDT 24 Jul 29 07:02:55 PM PDT 24 1654500127 ps
T410 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1287541210 Jul 29 07:02:17 PM PDT 24 Jul 29 07:02:24 PM PDT 24 255873754 ps
T411 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.861025675 Jul 29 07:02:45 PM PDT 24 Jul 29 07:02:50 PM PDT 24 163679226 ps

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.76087023
Short name T10
Test name
Test status
Simulation time 20892082435 ps
CPU time 867.02 seconds
Started Jul 29 06:09:23 PM PDT 24
Finished Jul 29 06:23:50 PM PDT 24
Peak memory 236660 kb
Host smart-3a001d40-282e-4fbe-9253-a941186db9fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76087023 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.76087023
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.340451050
Short name T5
Test name
Test status
Simulation time 3173478767 ps
CPU time 156.91 seconds
Started Jul 29 06:08:49 PM PDT 24
Finished Jul 29 06:11:26 PM PDT 24
Peak memory 213388 kb
Host smart-65f8412f-d303-403b-9d88-94c692126173
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340451050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.340451050
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.324290395
Short name T39
Test name
Test status
Simulation time 1431160158 ps
CPU time 96.1 seconds
Started Jul 29 06:09:17 PM PDT 24
Finished Jul 29 06:10:53 PM PDT 24
Peak memory 237952 kb
Host smart-9d60612a-b289-43b9-9220-85b05e375a49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324290395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.324290395
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3516618501
Short name T53
Test name
Test status
Simulation time 639186943 ps
CPU time 77.74 seconds
Started Jul 29 07:02:55 PM PDT 24
Finished Jul 29 07:04:13 PM PDT 24
Peak memory 214256 kb
Host smart-1a41701e-6918-4d00-9076-0f7c92e6f010
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516618501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3516618501
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1858812307
Short name T12
Test name
Test status
Simulation time 163350133803 ps
CPU time 3969.16 seconds
Started Jul 29 06:09:11 PM PDT 24
Finished Jul 29 07:15:20 PM PDT 24
Peak memory 236660 kb
Host smart-ab21c4c4-a570-4d41-8aaf-69e816ff6e1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858812307 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1858812307
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.532419804
Short name T25
Test name
Test status
Simulation time 813337746 ps
CPU time 98.25 seconds
Started Jul 29 06:08:52 PM PDT 24
Finished Jul 29 06:10:30 PM PDT 24
Peak memory 237372 kb
Host smart-63d789e0-4588-46b0-921d-3684e21fec60
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532419804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.532419804
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3497920441
Short name T18
Test name
Test status
Simulation time 288224575 ps
CPU time 18.26 seconds
Started Jul 29 06:09:36 PM PDT 24
Finished Jul 29 06:09:54 PM PDT 24
Peak memory 216184 kb
Host smart-d00cd1d0-b7c2-4309-aec3-ac1d3cdbf6f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497920441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3497920441
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2149110197
Short name T69
Test name
Test status
Simulation time 2210467254 ps
CPU time 27.47 seconds
Started Jul 29 07:02:16 PM PDT 24
Finished Jul 29 07:02:44 PM PDT 24
Peak memory 211500 kb
Host smart-88cecc03-8fda-4329-b5fc-0e2094347ed1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149110197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2149110197
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.398573168
Short name T112
Test name
Test status
Simulation time 1385956941 ps
CPU time 41.86 seconds
Started Jul 29 07:02:48 PM PDT 24
Finished Jul 29 07:03:30 PM PDT 24
Peak memory 214072 kb
Host smart-59353f80-b97d-49cf-b33c-3466f90071d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398573168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.398573168
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3007075943
Short name T123
Test name
Test status
Simulation time 464067695 ps
CPU time 5.06 seconds
Started Jul 29 06:09:57 PM PDT 24
Finished Jul 29 06:10:02 PM PDT 24
Peak memory 212012 kb
Host smart-11f932b6-4c26-42ed-9e0b-d0010219b622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007075943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3007075943
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1946484929
Short name T44
Test name
Test status
Simulation time 250727271 ps
CPU time 11.14 seconds
Started Jul 29 06:09:05 PM PDT 24
Finished Jul 29 06:09:16 PM PDT 24
Peak memory 212984 kb
Host smart-7c9ceb94-ed07-4027-8bcc-65a455ed7996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946484929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1946484929
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3747023076
Short name T264
Test name
Test status
Simulation time 173224313 ps
CPU time 9.56 seconds
Started Jul 29 06:09:09 PM PDT 24
Finished Jul 29 06:09:19 PM PDT 24
Peak memory 212828 kb
Host smart-13dd299f-1434-4306-84be-0a1283e70455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747023076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3747023076
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.509431026
Short name T43
Test name
Test status
Simulation time 252986660 ps
CPU time 11.02 seconds
Started Jul 29 06:09:55 PM PDT 24
Finished Jul 29 06:10:06 PM PDT 24
Peak memory 212964 kb
Host smart-cb696cf7-79d7-496c-b37c-e78767f592ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509431026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.509431026
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3483167636
Short name T118
Test name
Test status
Simulation time 991709994 ps
CPU time 73.06 seconds
Started Jul 29 07:02:22 PM PDT 24
Finished Jul 29 07:03:36 PM PDT 24
Peak memory 214276 kb
Host smart-63c7222c-306e-49bd-9257-1f125f2c9c92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483167636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3483167636
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2907000897
Short name T84
Test name
Test status
Simulation time 4031130455 ps
CPU time 18.45 seconds
Started Jul 29 07:02:50 PM PDT 24
Finished Jul 29 07:03:09 PM PDT 24
Peak memory 211420 kb
Host smart-bc398f54-2b49-4409-ac40-95be699ab1e8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907000897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2907000897
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1473840510
Short name T33
Test name
Test status
Simulation time 2862000394 ps
CPU time 134.56 seconds
Started Jul 29 06:09:11 PM PDT 24
Finished Jul 29 06:11:26 PM PDT 24
Peak memory 213388 kb
Host smart-252070fa-f2c4-4d76-9e14-6ee730b8e25b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473840510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1473840510
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4277213603
Short name T63
Test name
Test status
Simulation time 419119115 ps
CPU time 5.17 seconds
Started Jul 29 07:02:38 PM PDT 24
Finished Jul 29 07:02:43 PM PDT 24
Peak memory 218552 kb
Host smart-551f7ad3-fccc-41ca-9b99-7f35afcc2de8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277213603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4277213603
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.827036437
Short name T120
Test name
Test status
Simulation time 152579416 ps
CPU time 36.64 seconds
Started Jul 29 07:02:46 PM PDT 24
Finished Jul 29 07:03:23 PM PDT 24
Peak memory 211952 kb
Host smart-c67746da-168c-4b03-bb0c-a7e554dca4d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827036437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.827036437
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2249786246
Short name T111
Test name
Test status
Simulation time 891720971 ps
CPU time 70.41 seconds
Started Jul 29 07:02:54 PM PDT 24
Finished Jul 29 07:04:04 PM PDT 24
Peak memory 212024 kb
Host smart-dd0b0ed3-dba5-44e7-895e-f6754fd0ea9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249786246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2249786246
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.774161225
Short name T88
Test name
Test status
Simulation time 136359127 ps
CPU time 6.48 seconds
Started Jul 29 06:09:59 PM PDT 24
Finished Jul 29 06:10:06 PM PDT 24
Peak memory 212180 kb
Host smart-387c4816-06db-4953-9821-20df4f6bba5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=774161225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.774161225
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.4055655145
Short name T51
Test name
Test status
Simulation time 31238074044 ps
CPU time 1136.79 seconds
Started Jul 29 06:08:47 PM PDT 24
Finished Jul 29 06:27:44 PM PDT 24
Peak memory 236704 kb
Host smart-834e51da-6589-4d3f-ba1c-56e722f222af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055655145 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.4055655145
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4037509858
Short name T341
Test name
Test status
Simulation time 129969389 ps
CPU time 5.17 seconds
Started Jul 29 07:02:14 PM PDT 24
Finished Jul 29 07:02:20 PM PDT 24
Peak memory 218456 kb
Host smart-67322841-9e4e-4c58-aa92-9ea110d8b829
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037509858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.4037509858
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1378172443
Short name T326
Test name
Test status
Simulation time 85583720 ps
CPU time 4.52 seconds
Started Jul 29 07:02:11 PM PDT 24
Finished Jul 29 07:02:15 PM PDT 24
Peak memory 211336 kb
Host smart-fda40ab6-0c8c-4cd9-b8a1-b7c353ca1391
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378172443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1378172443
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2401708568
Short name T344
Test name
Test status
Simulation time 92189892 ps
CPU time 7.44 seconds
Started Jul 29 07:02:13 PM PDT 24
Finished Jul 29 07:02:21 PM PDT 24
Peak memory 211352 kb
Host smart-5cdb2dac-f650-4e29-a98f-5cb9328be6b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401708568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2401708568
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1602516600
Short name T345
Test name
Test status
Simulation time 1895479774 ps
CPU time 5.66 seconds
Started Jul 29 07:02:11 PM PDT 24
Finished Jul 29 07:02:17 PM PDT 24
Peak memory 219640 kb
Host smart-23e8ad36-3716-454e-a49a-82b117a07df2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602516600 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1602516600
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3750584042
Short name T407
Test name
Test status
Simulation time 129313270 ps
CPU time 5.07 seconds
Started Jul 29 07:02:13 PM PDT 24
Finished Jul 29 07:02:18 PM PDT 24
Peak memory 211312 kb
Host smart-c9ec3eef-4131-4fda-bfa5-9c85fbe38717
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750584042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3750584042
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3905637835
Short name T325
Test name
Test status
Simulation time 337088132 ps
CPU time 4.22 seconds
Started Jul 29 07:02:13 PM PDT 24
Finished Jul 29 07:02:18 PM PDT 24
Peak memory 211268 kb
Host smart-6b3014d3-6058-4500-b252-60cf394a50ec
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905637835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3905637835
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.350425427
Short name T323
Test name
Test status
Simulation time 132693498 ps
CPU time 5.01 seconds
Started Jul 29 07:02:12 PM PDT 24
Finished Jul 29 07:02:17 PM PDT 24
Peak memory 211216 kb
Host smart-b3ad7aec-f24c-4087-aada-f0276063e528
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350425427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
350425427
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2197362634
Short name T68
Test name
Test status
Simulation time 507024914 ps
CPU time 9.39 seconds
Started Jul 29 07:02:13 PM PDT 24
Finished Jul 29 07:02:23 PM PDT 24
Peak memory 211756 kb
Host smart-af9f0476-4619-4522-b6c5-7309f6aa76e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197362634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2197362634
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.34500245
Short name T406
Test name
Test status
Simulation time 175566214 ps
CPU time 8.4 seconds
Started Jul 29 07:02:12 PM PDT 24
Finished Jul 29 07:02:21 PM PDT 24
Peak memory 219680 kb
Host smart-cde61452-b0b1-4dad-aea2-8ce81b2c3d0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34500245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.34500245
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1031687908
Short name T52
Test name
Test status
Simulation time 189767575 ps
CPU time 36.42 seconds
Started Jul 29 07:02:11 PM PDT 24
Finished Jul 29 07:02:47 PM PDT 24
Peak memory 211608 kb
Host smart-fdd55bed-9594-4419-a90f-cd4f959bc108
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031687908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1031687908
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2044777207
Short name T383
Test name
Test status
Simulation time 241936436 ps
CPU time 5.11 seconds
Started Jul 29 07:02:18 PM PDT 24
Finished Jul 29 07:02:23 PM PDT 24
Peak memory 217920 kb
Host smart-c204a6ab-fdad-446b-9930-5a311bfbefd3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044777207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2044777207
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1181742904
Short name T363
Test name
Test status
Simulation time 260270875 ps
CPU time 5.46 seconds
Started Jul 29 07:02:13 PM PDT 24
Finished Jul 29 07:02:19 PM PDT 24
Peak memory 218132 kb
Host smart-4336ac8f-26e4-4b59-8d3a-0eda56dae393
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181742904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1181742904
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3403610310
Short name T66
Test name
Test status
Simulation time 1087420509 ps
CPU time 8.14 seconds
Started Jul 29 07:02:10 PM PDT 24
Finished Jul 29 07:02:19 PM PDT 24
Peak memory 211312 kb
Host smart-2d7f8bfc-3f38-4c51-b1bd-23e84e8c9102
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403610310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3403610310
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.708257802
Short name T387
Test name
Test status
Simulation time 251418434 ps
CPU time 5.29 seconds
Started Jul 29 07:02:18 PM PDT 24
Finished Jul 29 07:02:24 PM PDT 24
Peak memory 214824 kb
Host smart-ab3cb28a-9c61-4174-80ac-215ac8a3b405
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708257802 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.708257802
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.556560615
Short name T86
Test name
Test status
Simulation time 89547601 ps
CPU time 4.43 seconds
Started Jul 29 07:02:11 PM PDT 24
Finished Jul 29 07:02:15 PM PDT 24
Peak memory 211328 kb
Host smart-bb942996-4c06-4ca3-8489-ac619373f8a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556560615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.556560615
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3897917267
Short name T354
Test name
Test status
Simulation time 128450017 ps
CPU time 5.1 seconds
Started Jul 29 07:02:12 PM PDT 24
Finished Jul 29 07:02:17 PM PDT 24
Peak memory 211252 kb
Host smart-9d55e989-71ad-4373-b2fc-a9778a5978e5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897917267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3897917267
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1658300308
Short name T328
Test name
Test status
Simulation time 1243180532 ps
CPU time 4.98 seconds
Started Jul 29 07:02:12 PM PDT 24
Finished Jul 29 07:02:17 PM PDT 24
Peak memory 211236 kb
Host smart-d90e9eda-fa45-4f9b-bb6a-d5505c754f83
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658300308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1658300308
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1287541210
Short name T410
Test name
Test status
Simulation time 255873754 ps
CPU time 6.72 seconds
Started Jul 29 07:02:17 PM PDT 24
Finished Jul 29 07:02:24 PM PDT 24
Peak memory 211476 kb
Host smart-e3618d63-9b50-478f-bd42-5f335ba0a3f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287541210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1287541210
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3730277743
Short name T369
Test name
Test status
Simulation time 498052830 ps
CPU time 8.53 seconds
Started Jul 29 07:02:14 PM PDT 24
Finished Jul 29 07:02:22 PM PDT 24
Peak memory 219700 kb
Host smart-c09e8aa1-3017-4cff-aded-921717d224ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730277743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3730277743
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2241053990
Short name T395
Test name
Test status
Simulation time 445854309 ps
CPU time 36.53 seconds
Started Jul 29 07:02:15 PM PDT 24
Finished Jul 29 07:02:52 PM PDT 24
Peak memory 219524 kb
Host smart-47346f6a-e906-4011-8061-d55839c786fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241053990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2241053990
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3746529455
Short name T333
Test name
Test status
Simulation time 105429188 ps
CPU time 4.65 seconds
Started Jul 29 07:02:40 PM PDT 24
Finished Jul 29 07:02:45 PM PDT 24
Peak memory 212604 kb
Host smart-9c88af19-d03c-4add-aa06-606e6350eae7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746529455 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3746529455
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3548099036
Short name T373
Test name
Test status
Simulation time 463322927 ps
CPU time 5.32 seconds
Started Jul 29 07:02:37 PM PDT 24
Finished Jul 29 07:02:42 PM PDT 24
Peak memory 211376 kb
Host smart-83be9e63-97e6-45e1-a809-6e264e3d5b2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548099036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3548099036
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2523505266
Short name T396
Test name
Test status
Simulation time 90159809 ps
CPU time 7.12 seconds
Started Jul 29 07:02:37 PM PDT 24
Finished Jul 29 07:02:44 PM PDT 24
Peak memory 216452 kb
Host smart-6e03959b-1c4f-4045-9579-93167c9316b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523505266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2523505266
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1335998468
Short name T117
Test name
Test status
Simulation time 938600818 ps
CPU time 37.54 seconds
Started Jul 29 07:02:36 PM PDT 24
Finished Jul 29 07:03:14 PM PDT 24
Peak memory 213864 kb
Host smart-68292e1f-7907-4b07-9319-9d32d0f4328c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335998468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1335998468
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.303077461
Short name T347
Test name
Test status
Simulation time 96893761 ps
CPU time 5.21 seconds
Started Jul 29 07:02:44 PM PDT 24
Finished Jul 29 07:02:49 PM PDT 24
Peak memory 216156 kb
Host smart-501f8545-0379-4dbc-876d-6dec1110d862
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303077461 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.303077461
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3720940361
Short name T81
Test name
Test status
Simulation time 172739717 ps
CPU time 4.21 seconds
Started Jul 29 07:02:44 PM PDT 24
Finished Jul 29 07:02:48 PM PDT 24
Peak memory 219480 kb
Host smart-c082ecb2-12bc-4a2a-a9b7-aba2e01400ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720940361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3720940361
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1178201665
Short name T353
Test name
Test status
Simulation time 175496178 ps
CPU time 4.25 seconds
Started Jul 29 07:02:45 PM PDT 24
Finished Jul 29 07:02:50 PM PDT 24
Peak memory 211392 kb
Host smart-2c74a99d-5533-453c-960b-7c22641346af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178201665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1178201665
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2560068289
Short name T399
Test name
Test status
Simulation time 91500800 ps
CPU time 7.75 seconds
Started Jul 29 07:02:36 PM PDT 24
Finished Jul 29 07:02:44 PM PDT 24
Peak memory 215484 kb
Host smart-484843f1-a292-41c5-9b2b-667321da331d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560068289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2560068289
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.835412660
Short name T371
Test name
Test status
Simulation time 528136849 ps
CPU time 5.36 seconds
Started Jul 29 07:02:44 PM PDT 24
Finished Jul 29 07:02:49 PM PDT 24
Peak memory 214996 kb
Host smart-ca2804e6-6ffe-40cd-b5fa-8c6e95d01834
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835412660 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.835412660
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3624882390
Short name T349
Test name
Test status
Simulation time 85687431 ps
CPU time 4.26 seconds
Started Jul 29 07:02:47 PM PDT 24
Finished Jul 29 07:02:51 PM PDT 24
Peak memory 211304 kb
Host smart-a9ce7a73-1cf3-442e-9145-7a91766ebcc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624882390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3624882390
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4208839459
Short name T382
Test name
Test status
Simulation time 271298351 ps
CPU time 5.03 seconds
Started Jul 29 07:02:45 PM PDT 24
Finished Jul 29 07:02:50 PM PDT 24
Peak memory 211400 kb
Host smart-e44069ae-a76b-4ee1-88ff-e47c2fc65f1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208839459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.4208839459
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1844994279
Short name T335
Test name
Test status
Simulation time 560963368 ps
CPU time 7.77 seconds
Started Jul 29 07:02:42 PM PDT 24
Finished Jul 29 07:02:50 PM PDT 24
Peak memory 216608 kb
Host smart-3b9a68f7-2f90-4289-89cb-a370566cca57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844994279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1844994279
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3500950755
Short name T398
Test name
Test status
Simulation time 250937322 ps
CPU time 68.92 seconds
Started Jul 29 07:02:43 PM PDT 24
Finished Jul 29 07:03:52 PM PDT 24
Peak memory 213044 kb
Host smart-ea1abb64-94d3-4e46-a1b2-ad4917bb1354
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500950755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3500950755
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.466986010
Short name T330
Test name
Test status
Simulation time 151082175 ps
CPU time 5.86 seconds
Started Jul 29 07:02:43 PM PDT 24
Finished Jul 29 07:02:49 PM PDT 24
Peak memory 219632 kb
Host smart-8e090964-c9cc-474d-8136-62f32feb5863
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466986010 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.466986010
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.101283896
Short name T342
Test name
Test status
Simulation time 90954664 ps
CPU time 4.16 seconds
Started Jul 29 07:02:42 PM PDT 24
Finished Jul 29 07:02:46 PM PDT 24
Peak memory 211312 kb
Host smart-8e4bfa9e-4f97-4e77-a3c2-85dbe6daaa88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101283896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.101283896
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3616563951
Short name T368
Test name
Test status
Simulation time 251441528 ps
CPU time 5.1 seconds
Started Jul 29 07:02:45 PM PDT 24
Finished Jul 29 07:02:51 PM PDT 24
Peak memory 218768 kb
Host smart-c6ea8a42-65dc-42bf-a505-66996c58e5c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616563951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3616563951
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.353230523
Short name T350
Test name
Test status
Simulation time 259116068 ps
CPU time 7.87 seconds
Started Jul 29 07:02:43 PM PDT 24
Finished Jul 29 07:02:52 PM PDT 24
Peak memory 216456 kb
Host smart-2aaad2b7-c0af-43b3-970c-cd530a9c9a54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353230523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.353230523
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2540301780
Short name T114
Test name
Test status
Simulation time 230528461 ps
CPU time 38.4 seconds
Started Jul 29 07:02:45 PM PDT 24
Finished Jul 29 07:03:23 PM PDT 24
Peak memory 212644 kb
Host smart-ecdc517c-2dfa-47b1-8528-c791b0e746ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540301780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2540301780
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2559281459
Short name T337
Test name
Test status
Simulation time 556041459 ps
CPU time 4.91 seconds
Started Jul 29 07:02:42 PM PDT 24
Finished Jul 29 07:02:47 PM PDT 24
Peak memory 215620 kb
Host smart-7db533b8-deff-44eb-a600-9ae3982d81fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559281459 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2559281459
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.861025675
Short name T411
Test name
Test status
Simulation time 163679226 ps
CPU time 4.24 seconds
Started Jul 29 07:02:45 PM PDT 24
Finished Jul 29 07:02:50 PM PDT 24
Peak memory 211288 kb
Host smart-57c6d9f9-22cb-4353-a367-07bdb35ae702
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861025675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.861025675
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.282888794
Short name T110
Test name
Test status
Simulation time 1629710297 ps
CPU time 18.68 seconds
Started Jul 29 07:02:46 PM PDT 24
Finished Jul 29 07:03:05 PM PDT 24
Peak memory 211496 kb
Host smart-dab21d93-061a-46c4-8270-6f9cfe3c315e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282888794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.282888794
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1840197651
Short name T71
Test name
Test status
Simulation time 326846768 ps
CPU time 6.03 seconds
Started Jul 29 07:02:44 PM PDT 24
Finished Jul 29 07:02:50 PM PDT 24
Peak memory 219512 kb
Host smart-7ab530fa-edb6-4201-85b6-e81456b6e3ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840197651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1840197651
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1053151195
Short name T346
Test name
Test status
Simulation time 979074204 ps
CPU time 10.67 seconds
Started Jul 29 07:02:44 PM PDT 24
Finished Jul 29 07:02:54 PM PDT 24
Peak memory 219684 kb
Host smart-354fcee8-aba2-467f-9335-c58aab807396
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053151195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1053151195
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1210431720
Short name T116
Test name
Test status
Simulation time 1317922126 ps
CPU time 67.58 seconds
Started Jul 29 07:02:44 PM PDT 24
Finished Jul 29 07:03:52 PM PDT 24
Peak memory 219576 kb
Host smart-6dbc3ec6-75c3-4025-a1c9-7abda7de9225
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210431720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1210431720
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.428679675
Short name T336
Test name
Test status
Simulation time 349530934 ps
CPU time 4.31 seconds
Started Jul 29 07:02:48 PM PDT 24
Finished Jul 29 07:02:53 PM PDT 24
Peak memory 219560 kb
Host smart-bbc6d07d-57ba-4ef7-a483-b25170d673c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428679675 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.428679675
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1102029195
Short name T393
Test name
Test status
Simulation time 309667211 ps
CPU time 4.19 seconds
Started Jul 29 07:02:46 PM PDT 24
Finished Jul 29 07:02:50 PM PDT 24
Peak memory 219480 kb
Host smart-567b7e91-f72c-4b47-aea8-5db99b28c7bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102029195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1102029195
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1258647503
Short name T401
Test name
Test status
Simulation time 251526942 ps
CPU time 5.03 seconds
Started Jul 29 07:02:47 PM PDT 24
Finished Jul 29 07:02:52 PM PDT 24
Peak memory 211392 kb
Host smart-0c526ce8-2d5f-430a-9532-6db34a069a3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258647503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1258647503
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1439113957
Short name T332
Test name
Test status
Simulation time 128760650 ps
CPU time 9.59 seconds
Started Jul 29 07:02:46 PM PDT 24
Finished Jul 29 07:02:55 PM PDT 24
Peak memory 216844 kb
Host smart-1d8302fe-71e6-4950-91f7-fd6bfecedbae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439113957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1439113957
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.507552300
Short name T121
Test name
Test status
Simulation time 315156278 ps
CPU time 36.13 seconds
Started Jul 29 07:02:43 PM PDT 24
Finished Jul 29 07:03:20 PM PDT 24
Peak memory 213156 kb
Host smart-c91b8271-ebea-4f7e-836f-caa3eafe638f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507552300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.507552300
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2972380408
Short name T386
Test name
Test status
Simulation time 431771620 ps
CPU time 5.02 seconds
Started Jul 29 07:02:49 PM PDT 24
Finished Jul 29 07:02:54 PM PDT 24
Peak memory 216368 kb
Host smart-302ce7e4-e7cf-4797-ac7e-a98b7daac9fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972380408 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2972380408
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3364025485
Short name T390
Test name
Test status
Simulation time 652589918 ps
CPU time 5.05 seconds
Started Jul 29 07:02:49 PM PDT 24
Finished Jul 29 07:02:54 PM PDT 24
Peak memory 211340 kb
Host smart-143653c3-e169-4c48-84a3-2e523d1a96f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364025485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3364025485
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1067866185
Short name T384
Test name
Test status
Simulation time 504265446 ps
CPU time 7.52 seconds
Started Jul 29 07:02:48 PM PDT 24
Finished Jul 29 07:02:55 PM PDT 24
Peak memory 211556 kb
Host smart-51739897-05e7-45a0-bd9e-c1419fbeb36a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067866185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1067866185
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4117196226
Short name T372
Test name
Test status
Simulation time 831062312 ps
CPU time 7.77 seconds
Started Jul 29 07:02:48 PM PDT 24
Finished Jul 29 07:02:55 PM PDT 24
Peak memory 216616 kb
Host smart-80644116-9d6e-4ac8-a126-a5d48b65be87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117196226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.4117196226
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1529055805
Short name T402
Test name
Test status
Simulation time 545327363 ps
CPU time 5.81 seconds
Started Jul 29 07:02:55 PM PDT 24
Finished Jul 29 07:03:01 PM PDT 24
Peak memory 215596 kb
Host smart-a501fe91-6c49-47f6-b6a3-a8afa0bc4802
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529055805 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1529055805
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.971506806
Short name T85
Test name
Test status
Simulation time 262028552 ps
CPU time 5.12 seconds
Started Jul 29 07:02:53 PM PDT 24
Finished Jul 29 07:02:59 PM PDT 24
Peak memory 218388 kb
Host smart-d177b31d-fa48-4f73-8b61-6f4fd010b33a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971506806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.971506806
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4042129330
Short name T355
Test name
Test status
Simulation time 262348941 ps
CPU time 5.19 seconds
Started Jul 29 07:02:54 PM PDT 24
Finished Jul 29 07:02:59 PM PDT 24
Peak memory 218948 kb
Host smart-c17a4165-0d39-42b8-b8ff-3d63f3a2ca15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042129330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.4042129330
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1325175413
Short name T409
Test name
Test status
Simulation time 1654500127 ps
CPU time 6.36 seconds
Started Jul 29 07:02:48 PM PDT 24
Finished Jul 29 07:02:55 PM PDT 24
Peak memory 219680 kb
Host smart-da96d51b-c2fe-4b1e-a6b8-db1bca7ce399
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325175413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1325175413
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1362544742
Short name T370
Test name
Test status
Simulation time 382152970 ps
CPU time 4.5 seconds
Started Jul 29 07:02:54 PM PDT 24
Finished Jul 29 07:02:59 PM PDT 24
Peak memory 219608 kb
Host smart-9f6d14e7-86ce-44ff-92c3-9ea22459541f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362544742 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1362544742
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1475516105
Short name T70
Test name
Test status
Simulation time 128179862 ps
CPU time 5.15 seconds
Started Jul 29 07:02:56 PM PDT 24
Finished Jul 29 07:03:01 PM PDT 24
Peak memory 211344 kb
Host smart-f0c1b7f9-675a-4ef7-bf14-1401b47a9c12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475516105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1475516105
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3174291605
Short name T55
Test name
Test status
Simulation time 128222016 ps
CPU time 5.32 seconds
Started Jul 29 07:02:55 PM PDT 24
Finished Jul 29 07:03:00 PM PDT 24
Peak memory 211320 kb
Host smart-9fc03e65-5469-4e5a-9973-115a9ee09901
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174291605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3174291605
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1613922123
Short name T327
Test name
Test status
Simulation time 377543887 ps
CPU time 6.36 seconds
Started Jul 29 07:02:54 PM PDT 24
Finished Jul 29 07:03:00 PM PDT 24
Peak memory 216360 kb
Host smart-07762d57-f234-4057-91e1-d874203197bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613922123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1613922123
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.290014368
Short name T324
Test name
Test status
Simulation time 509423443 ps
CPU time 7.89 seconds
Started Jul 29 07:02:55 PM PDT 24
Finished Jul 29 07:03:03 PM PDT 24
Peak memory 215300 kb
Host smart-2b621add-e8a5-4029-ac32-6a05b8ae45a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290014368 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.290014368
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4166618829
Short name T101
Test name
Test status
Simulation time 983490343 ps
CPU time 7.83 seconds
Started Jul 29 07:02:54 PM PDT 24
Finished Jul 29 07:03:02 PM PDT 24
Peak memory 211368 kb
Host smart-a9912fe0-8da5-44f7-8c77-b2e3cc72e680
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166618829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.4166618829
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1394261480
Short name T360
Test name
Test status
Simulation time 129088416 ps
CPU time 5.09 seconds
Started Jul 29 07:02:54 PM PDT 24
Finished Jul 29 07:02:59 PM PDT 24
Peak memory 211540 kb
Host smart-b548100e-db6e-4b75-9964-d8b20375fb9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394261480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1394261480
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2155378168
Short name T392
Test name
Test status
Simulation time 186334585 ps
CPU time 8.81 seconds
Started Jul 29 07:02:55 PM PDT 24
Finished Jul 29 07:03:04 PM PDT 24
Peak memory 216488 kb
Host smart-167db8a4-b621-4012-8ba0-1e3bb3b5caa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155378168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2155378168
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1028200360
Short name T115
Test name
Test status
Simulation time 248956550 ps
CPU time 68.46 seconds
Started Jul 29 07:02:55 PM PDT 24
Finished Jul 29 07:04:04 PM PDT 24
Peak memory 219544 kb
Host smart-bcc8aca3-95ff-4232-a3c0-4b116705fbaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028200360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1028200360
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.854658143
Short name T62
Test name
Test status
Simulation time 225047547 ps
CPU time 5.05 seconds
Started Jul 29 07:02:17 PM PDT 24
Finished Jul 29 07:02:22 PM PDT 24
Peak memory 218112 kb
Host smart-be33c9eb-af3b-4e5a-9a0e-259bdc26b91d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854658143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.854658143
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.9255137
Short name T405
Test name
Test status
Simulation time 1971894122 ps
CPU time 7.71 seconds
Started Jul 29 07:02:16 PM PDT 24
Finished Jul 29 07:02:24 PM PDT 24
Peak memory 211496 kb
Host smart-ca4a69be-d80d-43e9-9e62-01ae20dc1830
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9255137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bas
h.9255137
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.973460923
Short name T348
Test name
Test status
Simulation time 519853644 ps
CPU time 8.3 seconds
Started Jul 29 07:02:16 PM PDT 24
Finished Jul 29 07:02:25 PM PDT 24
Peak memory 211300 kb
Host smart-9fa8d27c-cf85-497d-b464-fd9507482591
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973460923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.973460923
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1784081166
Short name T400
Test name
Test status
Simulation time 405849042 ps
CPU time 4.92 seconds
Started Jul 29 07:02:25 PM PDT 24
Finished Jul 29 07:02:30 PM PDT 24
Peak memory 215112 kb
Host smart-713c987b-102e-4226-b349-5369c72e07bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784081166 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1784081166
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.582900316
Short name T82
Test name
Test status
Simulation time 249986102 ps
CPU time 5.15 seconds
Started Jul 29 07:02:17 PM PDT 24
Finished Jul 29 07:02:23 PM PDT 24
Peak memory 218340 kb
Host smart-87dc7dde-7e07-4147-8f32-d94135e961b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582900316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.582900316
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4240016195
Short name T367
Test name
Test status
Simulation time 90163945 ps
CPU time 4.2 seconds
Started Jul 29 07:02:18 PM PDT 24
Finished Jul 29 07:02:23 PM PDT 24
Peak memory 211252 kb
Host smart-fb58c1d2-741a-49b5-a730-d06207e28f27
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240016195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.4240016195
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.648921002
Short name T343
Test name
Test status
Simulation time 516138504 ps
CPU time 5.04 seconds
Started Jul 29 07:02:17 PM PDT 24
Finished Jul 29 07:02:22 PM PDT 24
Peak memory 211224 kb
Host smart-7cd596ca-9f46-41b1-b588-ed484a1dcc78
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648921002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
648921002
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.539953988
Short name T376
Test name
Test status
Simulation time 685965447 ps
CPU time 5.12 seconds
Started Jul 29 07:02:18 PM PDT 24
Finished Jul 29 07:02:23 PM PDT 24
Peak memory 211348 kb
Host smart-9c8e1763-284a-4765-920c-7d892e53aa57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539953988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.539953988
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3451306371
Short name T381
Test name
Test status
Simulation time 160275575 ps
CPU time 11.22 seconds
Started Jul 29 07:02:17 PM PDT 24
Finished Jul 29 07:02:28 PM PDT 24
Peak memory 219692 kb
Host smart-5ea65ecb-418b-45fd-942d-68fef720f5ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451306371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3451306371
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4177621361
Short name T366
Test name
Test status
Simulation time 640881829 ps
CPU time 36.6 seconds
Started Jul 29 07:02:17 PM PDT 24
Finished Jul 29 07:02:54 PM PDT 24
Peak memory 219564 kb
Host smart-b22ae82c-1c89-41a9-a4a4-e70fa69aace2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177621361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.4177621361
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3495091491
Short name T356
Test name
Test status
Simulation time 126992913 ps
CPU time 5.02 seconds
Started Jul 29 07:02:23 PM PDT 24
Finished Jul 29 07:02:28 PM PDT 24
Peak memory 211276 kb
Host smart-199212e0-4cd0-49ac-b301-00f6300e2ebf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495091491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3495091491
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2358711526
Short name T340
Test name
Test status
Simulation time 1035316406 ps
CPU time 4.49 seconds
Started Jul 29 07:02:28 PM PDT 24
Finished Jul 29 07:02:33 PM PDT 24
Peak memory 219516 kb
Host smart-b00bbca0-ae4d-41b5-8605-eb1fe4e111c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358711526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2358711526
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2546563170
Short name T100
Test name
Test status
Simulation time 349955710 ps
CPU time 7.29 seconds
Started Jul 29 07:02:25 PM PDT 24
Finished Jul 29 07:02:32 PM PDT 24
Peak memory 211320 kb
Host smart-3fc1144f-1faa-4afd-b436-d9dd04df1085
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546563170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2546563170
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3412648806
Short name T378
Test name
Test status
Simulation time 495234341 ps
CPU time 4.94 seconds
Started Jul 29 07:02:23 PM PDT 24
Finished Jul 29 07:02:28 PM PDT 24
Peak memory 215852 kb
Host smart-57546983-4241-4faa-8ba7-1980989d117d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412648806 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3412648806
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3102619229
Short name T98
Test name
Test status
Simulation time 129877784 ps
CPU time 5.05 seconds
Started Jul 29 07:02:23 PM PDT 24
Finished Jul 29 07:02:29 PM PDT 24
Peak memory 218276 kb
Host smart-b005f9a3-021b-46b2-b01e-de31ba70fffe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102619229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3102619229
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2796816325
Short name T331
Test name
Test status
Simulation time 89178173 ps
CPU time 4.26 seconds
Started Jul 29 07:02:29 PM PDT 24
Finished Jul 29 07:02:34 PM PDT 24
Peak memory 211220 kb
Host smart-4a37596e-9503-418f-8ecc-20eac07d1b5a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796816325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2796816325
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1524391005
Short name T322
Test name
Test status
Simulation time 522362069 ps
CPU time 5 seconds
Started Jul 29 07:02:23 PM PDT 24
Finished Jul 29 07:02:28 PM PDT 24
Peak memory 211268 kb
Host smart-92a3e5fd-62fe-4761-bca6-ba6fd79dc308
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524391005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1524391005
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1039055046
Short name T99
Test name
Test status
Simulation time 176529685 ps
CPU time 4.27 seconds
Started Jul 29 07:02:22 PM PDT 24
Finished Jul 29 07:02:26 PM PDT 24
Peak memory 219556 kb
Host smart-d4d4e147-f9ae-4bdf-bca7-70fcde9910bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039055046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1039055046
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3828091850
Short name T365
Test name
Test status
Simulation time 132608031 ps
CPU time 7.64 seconds
Started Jul 29 07:02:30 PM PDT 24
Finished Jul 29 07:02:38 PM PDT 24
Peak memory 216608 kb
Host smart-e30102e9-0a87-409c-b2a7-631d7840bd38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828091850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3828091850
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2728814761
Short name T377
Test name
Test status
Simulation time 828602026 ps
CPU time 5.24 seconds
Started Jul 29 07:02:32 PM PDT 24
Finished Jul 29 07:02:38 PM PDT 24
Peak memory 218108 kb
Host smart-462acb41-8c69-4d2c-9c25-3a847b6d94bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728814761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2728814761
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.36033529
Short name T357
Test name
Test status
Simulation time 86097926 ps
CPU time 4.6 seconds
Started Jul 29 07:02:31 PM PDT 24
Finished Jul 29 07:02:36 PM PDT 24
Peak memory 219488 kb
Host smart-740694d9-3855-4f91-8cbd-34dbae1e8f75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36033529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_ba
sh.36033529
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1457035232
Short name T364
Test name
Test status
Simulation time 918893170 ps
CPU time 8.22 seconds
Started Jul 29 07:02:30 PM PDT 24
Finished Jul 29 07:02:38 PM PDT 24
Peak memory 218560 kb
Host smart-91ba8746-8da7-4654-aa09-c29d274de356
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457035232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1457035232
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.818839122
Short name T361
Test name
Test status
Simulation time 194945303 ps
CPU time 4.98 seconds
Started Jul 29 07:02:31 PM PDT 24
Finished Jul 29 07:02:36 PM PDT 24
Peak memory 219620 kb
Host smart-7fdb7dd5-ccd3-4d2f-88bf-de2eb3a0a186
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818839122 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.818839122
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1273207973
Short name T80
Test name
Test status
Simulation time 128483358 ps
CPU time 4.97 seconds
Started Jul 29 07:02:31 PM PDT 24
Finished Jul 29 07:02:36 PM PDT 24
Peak memory 211332 kb
Host smart-22482325-17db-45c6-9b02-e9868252335b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273207973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1273207973
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.243105502
Short name T351
Test name
Test status
Simulation time 498192012 ps
CPU time 5.02 seconds
Started Jul 29 07:02:28 PM PDT 24
Finished Jul 29 07:02:33 PM PDT 24
Peak memory 211236 kb
Host smart-a19c352f-1337-4592-9edd-1ba1de4b19aa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243105502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.243105502
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1796133422
Short name T389
Test name
Test status
Simulation time 536941088 ps
CPU time 5.11 seconds
Started Jul 29 07:02:28 PM PDT 24
Finished Jul 29 07:02:34 PM PDT 24
Peak memory 211272 kb
Host smart-ade978e3-d4e0-47e5-bd55-e309c69732fb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796133422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1796133422
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3614994732
Short name T87
Test name
Test status
Simulation time 2253715456 ps
CPU time 21.6 seconds
Started Jul 29 07:02:26 PM PDT 24
Finished Jul 29 07:02:48 PM PDT 24
Peak memory 211520 kb
Host smart-d16fe474-7dc3-4989-9e2f-09c90ae572ff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614994732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3614994732
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.44496795
Short name T97
Test name
Test status
Simulation time 1720764018 ps
CPU time 5.85 seconds
Started Jul 29 07:02:30 PM PDT 24
Finished Jul 29 07:02:36 PM PDT 24
Peak memory 211580 kb
Host smart-e9c01a21-a773-4ca0-b4cd-925f8bab9901
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44496795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_same_csr_outstanding.44496795
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.91351833
Short name T385
Test name
Test status
Simulation time 181937827 ps
CPU time 8.37 seconds
Started Jul 29 07:02:28 PM PDT 24
Finished Jul 29 07:02:37 PM PDT 24
Peak memory 219700 kb
Host smart-9473e8cd-9b9b-4927-b313-194a29babf5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91351833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.91351833
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1106272248
Short name T388
Test name
Test status
Simulation time 700298582 ps
CPU time 37.05 seconds
Started Jul 29 07:02:23 PM PDT 24
Finished Jul 29 07:03:00 PM PDT 24
Peak memory 211528 kb
Host smart-8f91b535-e5bd-4d03-9115-e0ed4f676bac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106272248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1106272248
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.204429776
Short name T338
Test name
Test status
Simulation time 354661316 ps
CPU time 5.16 seconds
Started Jul 29 07:02:30 PM PDT 24
Finished Jul 29 07:02:35 PM PDT 24
Peak memory 219616 kb
Host smart-85416e92-ecb6-46ff-846f-8547420ca5c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204429776 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.204429776
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.323896077
Short name T403
Test name
Test status
Simulation time 132349178 ps
CPU time 5.12 seconds
Started Jul 29 07:02:28 PM PDT 24
Finished Jul 29 07:02:33 PM PDT 24
Peak memory 218296 kb
Host smart-71821d56-4838-4046-98d0-3ba53f973659
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323896077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.323896077
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.139993460
Short name T391
Test name
Test status
Simulation time 335184281 ps
CPU time 4.37 seconds
Started Jul 29 07:02:29 PM PDT 24
Finished Jul 29 07:02:33 PM PDT 24
Peak memory 219524 kb
Host smart-5e482b3e-3fb9-4a2e-b1c7-0e13e8d8b32e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139993460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.139993460
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2020238798
Short name T362
Test name
Test status
Simulation time 529979101 ps
CPU time 9.51 seconds
Started Jul 29 07:02:33 PM PDT 24
Finished Jul 29 07:02:43 PM PDT 24
Peak memory 219640 kb
Host smart-4368cafe-9832-477a-9e47-729bb914f3fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020238798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2020238798
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1369587573
Short name T113
Test name
Test status
Simulation time 546710340 ps
CPU time 70.27 seconds
Started Jul 29 07:02:32 PM PDT 24
Finished Jul 29 07:03:42 PM PDT 24
Peak memory 213916 kb
Host smart-f237a2c3-fd6c-4a67-81e9-a2f20dd08bae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369587573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1369587573
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3396229141
Short name T397
Test name
Test status
Simulation time 489977661 ps
CPU time 5.57 seconds
Started Jul 29 07:02:28 PM PDT 24
Finished Jul 29 07:02:34 PM PDT 24
Peak memory 214956 kb
Host smart-cbd08e15-64a3-49e3-9465-0dc800412301
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396229141 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3396229141
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3465782303
Short name T65
Test name
Test status
Simulation time 1757879876 ps
CPU time 7.53 seconds
Started Jul 29 07:02:32 PM PDT 24
Finished Jul 29 07:02:40 PM PDT 24
Peak memory 211284 kb
Host smart-040ff0ba-1403-470a-a3da-56b6054bd497
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465782303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3465782303
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3515618468
Short name T374
Test name
Test status
Simulation time 832999653 ps
CPU time 5.14 seconds
Started Jul 29 07:02:31 PM PDT 24
Finished Jul 29 07:02:36 PM PDT 24
Peak memory 211424 kb
Host smart-1348a6fe-39bf-40ed-8cfa-a40fe8229d1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515618468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3515618468
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3787775714
Short name T404
Test name
Test status
Simulation time 88215711 ps
CPU time 6.51 seconds
Started Jul 29 07:02:32 PM PDT 24
Finished Jul 29 07:02:38 PM PDT 24
Peak memory 219636 kb
Host smart-03e0b319-6c56-4156-a435-c401cee82c1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787775714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3787775714
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1890436658
Short name T375
Test name
Test status
Simulation time 727386476 ps
CPU time 37.72 seconds
Started Jul 29 07:02:31 PM PDT 24
Finished Jul 29 07:03:09 PM PDT 24
Peak memory 219524 kb
Host smart-f3766b34-0dd6-4cc6-9d76-338a62d9e07e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890436658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1890436658
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3324131556
Short name T339
Test name
Test status
Simulation time 180471752 ps
CPU time 5.95 seconds
Started Jul 29 07:02:29 PM PDT 24
Finished Jul 29 07:02:35 PM PDT 24
Peak memory 216488 kb
Host smart-6e6c0ffa-5936-47e9-8501-2cdffb26f5ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324131556 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3324131556
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2635816904
Short name T380
Test name
Test status
Simulation time 262459787 ps
CPU time 5.05 seconds
Started Jul 29 07:02:29 PM PDT 24
Finished Jul 29 07:02:35 PM PDT 24
Peak memory 211352 kb
Host smart-9fbf75a6-32b4-47b9-93e7-817361daa719
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635816904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2635816904
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2137133110
Short name T67
Test name
Test status
Simulation time 2109612337 ps
CPU time 31.1 seconds
Started Jul 29 07:02:30 PM PDT 24
Finished Jul 29 07:03:02 PM PDT 24
Peak memory 211392 kb
Host smart-5531a529-5c86-4aca-a340-3009bc541d8e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137133110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2137133110
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1119681010
Short name T64
Test name
Test status
Simulation time 501222924 ps
CPU time 5.02 seconds
Started Jul 29 07:02:31 PM PDT 24
Finished Jul 29 07:02:37 PM PDT 24
Peak memory 218740 kb
Host smart-81c1e82c-3579-4dbd-95cd-a21a28c99b91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119681010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1119681010
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1781927052
Short name T334
Test name
Test status
Simulation time 444137023 ps
CPU time 8.45 seconds
Started Jul 29 07:02:31 PM PDT 24
Finished Jul 29 07:02:39 PM PDT 24
Peak memory 216704 kb
Host smart-5a1388b1-99db-490f-a5ae-61526836cdc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781927052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1781927052
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3160573755
Short name T119
Test name
Test status
Simulation time 310754624 ps
CPU time 69.47 seconds
Started Jul 29 07:02:29 PM PDT 24
Finished Jul 29 07:03:38 PM PDT 24
Peak memory 219484 kb
Host smart-cc6de1d4-338e-47a7-822e-a30591cc3881
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160573755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3160573755
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3104310166
Short name T329
Test name
Test status
Simulation time 178862070 ps
CPU time 4.6 seconds
Started Jul 29 07:02:36 PM PDT 24
Finished Jul 29 07:02:40 PM PDT 24
Peak memory 219548 kb
Host smart-6d9f7a31-2ea3-4fcb-8d98-f6b81d534e25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104310166 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3104310166
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3517990053
Short name T352
Test name
Test status
Simulation time 256093292 ps
CPU time 5.06 seconds
Started Jul 29 07:02:31 PM PDT 24
Finished Jul 29 07:02:36 PM PDT 24
Peak memory 211228 kb
Host smart-54ad9685-9661-40a3-b2b8-27821940177d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517990053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3517990053
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.462704937
Short name T408
Test name
Test status
Simulation time 130610755 ps
CPU time 5.19 seconds
Started Jul 29 07:02:36 PM PDT 24
Finished Jul 29 07:02:41 PM PDT 24
Peak memory 218880 kb
Host smart-8b857635-8439-44b8-93d8-908d7ad8d088
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462704937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.462704937
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.893215086
Short name T394
Test name
Test status
Simulation time 145097336 ps
CPU time 7.7 seconds
Started Jul 29 07:02:32 PM PDT 24
Finished Jul 29 07:02:40 PM PDT 24
Peak memory 216564 kb
Host smart-2c8c51c9-20f5-4c78-b7ae-ad3b2dd6a457
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893215086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.893215086
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2839205447
Short name T54
Test name
Test status
Simulation time 521480697 ps
CPU time 36.51 seconds
Started Jul 29 07:02:30 PM PDT 24
Finished Jul 29 07:03:07 PM PDT 24
Peak memory 211844 kb
Host smart-58fc8a7a-e49c-498e-ac2e-b1c4ccb09f2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839205447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2839205447
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2733455014
Short name T358
Test name
Test status
Simulation time 97011501 ps
CPU time 4.63 seconds
Started Jul 29 07:02:37 PM PDT 24
Finished Jul 29 07:02:42 PM PDT 24
Peak memory 213688 kb
Host smart-87f398b9-4a0f-491f-bcf0-46fe58b9b6c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733455014 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2733455014
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4292403166
Short name T102
Test name
Test status
Simulation time 130243992 ps
CPU time 5.09 seconds
Started Jul 29 07:02:40 PM PDT 24
Finished Jul 29 07:02:46 PM PDT 24
Peak memory 218352 kb
Host smart-caaa55cb-5733-499b-8f80-1b11a70b008a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292403166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.4292403166
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3869173701
Short name T83
Test name
Test status
Simulation time 2113840800 ps
CPU time 18.36 seconds
Started Jul 29 07:02:40 PM PDT 24
Finished Jul 29 07:02:59 PM PDT 24
Peak memory 211404 kb
Host smart-48b86fa8-600e-47e6-9825-4e442a0e2e9a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869173701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3869173701
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.32325159
Short name T56
Test name
Test status
Simulation time 348422755 ps
CPU time 4.31 seconds
Started Jul 29 07:02:38 PM PDT 24
Finished Jul 29 07:02:42 PM PDT 24
Peak memory 211408 kb
Host smart-2b7c76bc-ed18-4e96-b356-10db93fba827
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32325159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctr
l_same_csr_outstanding.32325159
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.15106244
Short name T379
Test name
Test status
Simulation time 85493050 ps
CPU time 6.21 seconds
Started Jul 29 07:02:38 PM PDT 24
Finished Jul 29 07:02:44 PM PDT 24
Peak memory 219704 kb
Host smart-1767baf3-b822-4025-8ad5-682088013051
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15106244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.15106244
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1527498572
Short name T359
Test name
Test status
Simulation time 437156655 ps
CPU time 69.56 seconds
Started Jul 29 07:02:37 PM PDT 24
Finished Jul 29 07:03:47 PM PDT 24
Peak memory 219736 kb
Host smart-ecf944ba-73ca-4cb2-a710-33ed7fddf1f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527498572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1527498572
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3139770002
Short name T57
Test name
Test status
Simulation time 255029549 ps
CPU time 5.09 seconds
Started Jul 29 06:08:46 PM PDT 24
Finished Jul 29 06:08:51 PM PDT 24
Peak memory 212052 kb
Host smart-32d5c4e6-ad74-4207-b72c-8ff44c4986af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139770002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3139770002
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3871236343
Short name T304
Test name
Test status
Simulation time 1562736035 ps
CPU time 89.02 seconds
Started Jul 29 06:08:45 PM PDT 24
Finished Jul 29 06:10:14 PM PDT 24
Peak memory 238396 kb
Host smart-35bb083c-da0c-42c3-b1f8-29410ccb4d7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871236343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3871236343
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2164060906
Short name T194
Test name
Test status
Simulation time 334835071 ps
CPU time 9.69 seconds
Started Jul 29 06:08:45 PM PDT 24
Finished Jul 29 06:08:55 PM PDT 24
Peak memory 212996 kb
Host smart-661be467-b0e9-44a0-aa93-c7d6d71e57c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164060906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2164060906
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.906231663
Short name T241
Test name
Test status
Simulation time 138068480 ps
CPU time 6.26 seconds
Started Jul 29 06:08:48 PM PDT 24
Finished Jul 29 06:08:55 PM PDT 24
Peak memory 212140 kb
Host smart-bf3d53f9-6def-459b-8332-61ce25175fc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=906231663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.906231663
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2058570034
Short name T22
Test name
Test status
Simulation time 288841084 ps
CPU time 102.33 seconds
Started Jul 29 06:08:48 PM PDT 24
Finished Jul 29 06:10:31 PM PDT 24
Peak memory 237332 kb
Host smart-9c470025-bb6c-40af-928b-4fec3e2e7c2a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058570034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2058570034
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.620133395
Short name T268
Test name
Test status
Simulation time 196536199 ps
CPU time 5.54 seconds
Started Jul 29 06:08:45 PM PDT 24
Finished Jul 29 06:08:51 PM PDT 24
Peak memory 212420 kb
Host smart-f38d33e3-c057-48aa-9763-f789061b2569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620133395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.620133395
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3526458259
Short name T223
Test name
Test status
Simulation time 1846369546 ps
CPU time 20.3 seconds
Started Jul 29 06:08:45 PM PDT 24
Finished Jul 29 06:09:06 PM PDT 24
Peak memory 216112 kb
Host smart-c6796860-ea2c-498f-99af-53c0bae44c69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526458259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3526458259
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1035984860
Short name T225
Test name
Test status
Simulation time 501237857 ps
CPU time 5.1 seconds
Started Jul 29 06:08:49 PM PDT 24
Finished Jul 29 06:08:55 PM PDT 24
Peak memory 212036 kb
Host smart-8994c5cf-9bcc-44a1-a160-cf47a72962b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035984860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1035984860
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.910879728
Short name T238
Test name
Test status
Simulation time 3394937304 ps
CPU time 88.57 seconds
Started Jul 29 06:08:49 PM PDT 24
Finished Jul 29 06:10:18 PM PDT 24
Peak memory 238388 kb
Host smart-b8e6654e-2282-4fd5-853f-342972066b0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910879728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.910879728
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3340994595
Short name T210
Test name
Test status
Simulation time 257374501 ps
CPU time 11.36 seconds
Started Jul 29 06:08:47 PM PDT 24
Finished Jul 29 06:08:59 PM PDT 24
Peak memory 213808 kb
Host smart-14cf6882-a0de-4fec-81b9-ac9fdf6cbeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340994595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3340994595
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1666941501
Short name T291
Test name
Test status
Simulation time 539699926 ps
CPU time 6.68 seconds
Started Jul 29 06:08:49 PM PDT 24
Finished Jul 29 06:08:56 PM PDT 24
Peak memory 212140 kb
Host smart-d2156dea-379f-475c-b145-a89cea579295
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1666941501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1666941501
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1114617456
Short name T20
Test name
Test status
Simulation time 586038097 ps
CPU time 102.03 seconds
Started Jul 29 06:08:49 PM PDT 24
Finished Jul 29 06:10:32 PM PDT 24
Peak memory 238072 kb
Host smart-2bda924c-21aa-4086-ac7d-af96b934c3cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114617456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1114617456
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1572746041
Short name T288
Test name
Test status
Simulation time 2580629580 ps
CPU time 6.22 seconds
Started Jul 29 06:08:47 PM PDT 24
Finished Jul 29 06:08:53 PM PDT 24
Peak memory 212304 kb
Host smart-624d300a-97d9-41a2-ad72-2086bd9bb285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572746041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1572746041
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1691030249
Short name T290
Test name
Test status
Simulation time 279735150 ps
CPU time 15.69 seconds
Started Jul 29 06:08:47 PM PDT 24
Finished Jul 29 06:09:03 PM PDT 24
Peak memory 212888 kb
Host smart-c11c5cd4-54aa-4a36-9cb5-dc0f457c81e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691030249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1691030249
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1216877406
Short name T49
Test name
Test status
Simulation time 21519875757 ps
CPU time 902.02 seconds
Started Jul 29 06:08:48 PM PDT 24
Finished Jul 29 06:23:50 PM PDT 24
Peak memory 236668 kb
Host smart-65b15280-cfd2-4fdf-89f6-c77f79287ffb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216877406 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.1216877406
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2411684728
Short name T134
Test name
Test status
Simulation time 128432751 ps
CPU time 5.28 seconds
Started Jul 29 06:09:03 PM PDT 24
Finished Jul 29 06:09:09 PM PDT 24
Peak memory 212112 kb
Host smart-43a72f83-d8bb-49e5-a4d9-bbd2fa7917d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411684728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2411684728
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.725364563
Short name T299
Test name
Test status
Simulation time 6994028961 ps
CPU time 65.75 seconds
Started Jul 29 06:09:03 PM PDT 24
Finished Jul 29 06:10:09 PM PDT 24
Peak memory 229212 kb
Host smart-9a36cc11-6104-4849-8f2d-85d4048abe6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725364563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.725364563
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2875453972
Short name T270
Test name
Test status
Simulation time 281477298 ps
CPU time 6.71 seconds
Started Jul 29 06:09:06 PM PDT 24
Finished Jul 29 06:09:13 PM PDT 24
Peak memory 212164 kb
Host smart-e4ef704a-7517-44f6-9b8a-53caa12db7b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2875453972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2875453972
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3670576643
Short name T104
Test name
Test status
Simulation time 1632536081 ps
CPU time 18.86 seconds
Started Jul 29 06:09:07 PM PDT 24
Finished Jul 29 06:09:26 PM PDT 24
Peak memory 214568 kb
Host smart-0feb7049-d510-45f2-b22d-a7aa4954847c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670576643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3670576643
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1761797174
Short name T141
Test name
Test status
Simulation time 153853944 ps
CPU time 4.2 seconds
Started Jul 29 06:09:05 PM PDT 24
Finished Jul 29 06:09:09 PM PDT 24
Peak memory 212020 kb
Host smart-e949fe58-78c2-4233-82a8-da56e9110f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761797174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1761797174
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3787324777
Short name T305
Test name
Test status
Simulation time 1270955207 ps
CPU time 72.31 seconds
Started Jul 29 06:09:05 PM PDT 24
Finished Jul 29 06:10:17 PM PDT 24
Peak memory 237340 kb
Host smart-1c9271c9-6edb-44b1-9a7e-8ed58f2eb621
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787324777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3787324777
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3463133451
Short name T152
Test name
Test status
Simulation time 251243260 ps
CPU time 11.1 seconds
Started Jul 29 06:09:03 PM PDT 24
Finished Jul 29 06:09:14 PM PDT 24
Peak memory 212852 kb
Host smart-bd138073-30ab-4de9-9875-ffb1708c3f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463133451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3463133451
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2821459711
Short name T261
Test name
Test status
Simulation time 552246445 ps
CPU time 6.24 seconds
Started Jul 29 06:09:02 PM PDT 24
Finished Jul 29 06:09:09 PM PDT 24
Peak memory 212180 kb
Host smart-b0195c6d-b376-4bcc-94cb-eb557b3534d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2821459711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2821459711
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2431650920
Short name T213
Test name
Test status
Simulation time 758217226 ps
CPU time 12.21 seconds
Started Jul 29 06:09:03 PM PDT 24
Finished Jul 29 06:09:15 PM PDT 24
Peak memory 215268 kb
Host smart-46c0db69-8cc9-496c-b214-d53ba14ccef7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431650920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2431650920
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1569643766
Short name T182
Test name
Test status
Simulation time 261402676 ps
CPU time 5.11 seconds
Started Jul 29 06:09:11 PM PDT 24
Finished Jul 29 06:09:16 PM PDT 24
Peak memory 212000 kb
Host smart-e0c9097a-23ea-470b-9ad8-b1ef545e8fc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569643766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1569643766
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1744353959
Short name T214
Test name
Test status
Simulation time 10273216276 ps
CPU time 124.59 seconds
Started Jul 29 06:09:02 PM PDT 24
Finished Jul 29 06:11:07 PM PDT 24
Peak memory 238440 kb
Host smart-71977d0c-6b45-4a13-818e-1556e3cb82c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744353959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1744353959
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.376933477
Short name T27
Test name
Test status
Simulation time 1149782794 ps
CPU time 5.6 seconds
Started Jul 29 06:09:05 PM PDT 24
Finished Jul 29 06:09:10 PM PDT 24
Peak memory 212152 kb
Host smart-f78bee49-d1dd-45d7-9d41-45f878b5bba3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=376933477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.376933477
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.738875186
Short name T227
Test name
Test status
Simulation time 440407281 ps
CPU time 12.24 seconds
Started Jul 29 06:09:08 PM PDT 24
Finished Jul 29 06:09:21 PM PDT 24
Peak memory 213408 kb
Host smart-779354d6-4aad-487c-a817-6a5ccfca6ef4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738875186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.738875186
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1660927679
Short name T209
Test name
Test status
Simulation time 175747831 ps
CPU time 4.15 seconds
Started Jul 29 06:09:10 PM PDT 24
Finished Jul 29 06:09:14 PM PDT 24
Peak memory 211968 kb
Host smart-0feaf2c2-dff8-4ed5-9d26-4f600b5d766c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660927679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1660927679
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.564474716
Short name T206
Test name
Test status
Simulation time 44088156195 ps
CPU time 192.81 seconds
Started Jul 29 06:09:10 PM PDT 24
Finished Jul 29 06:12:23 PM PDT 24
Peak memory 214400 kb
Host smart-2eb6aead-dc9c-43e0-ab55-227c762e6337
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564474716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.564474716
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.374676190
Short name T125
Test name
Test status
Simulation time 1778114192 ps
CPU time 11.43 seconds
Started Jul 29 06:09:13 PM PDT 24
Finished Jul 29 06:09:25 PM PDT 24
Peak memory 212884 kb
Host smart-07e09b51-0979-44cc-9a1d-fc1e7f7a6265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374676190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.374676190
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2931188969
Short name T300
Test name
Test status
Simulation time 98994838 ps
CPU time 5.57 seconds
Started Jul 29 06:09:12 PM PDT 24
Finished Jul 29 06:09:18 PM PDT 24
Peak memory 212156 kb
Host smart-766a4f13-a3da-40a7-abf9-0c2dfe74191b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2931188969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2931188969
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.818153264
Short name T278
Test name
Test status
Simulation time 303560632 ps
CPU time 12.62 seconds
Started Jul 29 06:09:11 PM PDT 24
Finished Jul 29 06:09:24 PM PDT 24
Peak memory 214404 kb
Host smart-25211347-d9ef-4b91-8f42-e3e1a34ed728
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818153264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.818153264
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.4033574789
Short name T212
Test name
Test status
Simulation time 171704102 ps
CPU time 4.25 seconds
Started Jul 29 06:09:15 PM PDT 24
Finished Jul 29 06:09:19 PM PDT 24
Peak memory 212052 kb
Host smart-fb282067-6d9a-42bc-b419-4fbdfeffc645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033574789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.4033574789
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3965565046
Short name T172
Test name
Test status
Simulation time 175056886 ps
CPU time 9.42 seconds
Started Jul 29 06:09:10 PM PDT 24
Finished Jul 29 06:09:20 PM PDT 24
Peak memory 212880 kb
Host smart-3451e632-9045-4291-b138-2fad6370a957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965565046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3965565046
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3065745709
Short name T168
Test name
Test status
Simulation time 271633040 ps
CPU time 6.24 seconds
Started Jul 29 06:09:09 PM PDT 24
Finished Jul 29 06:09:16 PM PDT 24
Peak memory 212120 kb
Host smart-2e078a11-06df-494b-ad39-daf2e696d3c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3065745709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3065745709
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.431331311
Short name T187
Test name
Test status
Simulation time 290391779 ps
CPU time 14.17 seconds
Started Jul 29 06:09:12 PM PDT 24
Finished Jul 29 06:09:27 PM PDT 24
Peak memory 213448 kb
Host smart-b0dec1fb-f4a9-40de-bd6b-e9ebce04afef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431331311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.431331311
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.163608191
Short name T174
Test name
Test status
Simulation time 169266235 ps
CPU time 4.42 seconds
Started Jul 29 06:09:11 PM PDT 24
Finished Jul 29 06:09:16 PM PDT 24
Peak memory 212048 kb
Host smart-486df9d9-867d-4e7e-9313-188075920ad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163608191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.163608191
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.301585480
Short name T19
Test name
Test status
Simulation time 8544930999 ps
CPU time 114.81 seconds
Started Jul 29 06:09:12 PM PDT 24
Finished Jul 29 06:11:07 PM PDT 24
Peak memory 239216 kb
Host smart-be2b2b57-34c4-478f-a146-8696fd16d44a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301585480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.301585480
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2428124321
Short name T176
Test name
Test status
Simulation time 4127277056 ps
CPU time 11.18 seconds
Started Jul 29 06:09:15 PM PDT 24
Finished Jul 29 06:09:26 PM PDT 24
Peak memory 213032 kb
Host smart-23d76cb1-a991-4f17-bfa4-f62aebbc08fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428124321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2428124321
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.4112081971
Short name T267
Test name
Test status
Simulation time 96037463 ps
CPU time 5.38 seconds
Started Jul 29 06:09:15 PM PDT 24
Finished Jul 29 06:09:20 PM PDT 24
Peak memory 212176 kb
Host smart-c1442e1a-a18d-482a-a10b-e3cba611cedd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4112081971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.4112081971
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1646093629
Short name T76
Test name
Test status
Simulation time 444999700 ps
CPU time 21 seconds
Started Jul 29 06:09:12 PM PDT 24
Finished Jul 29 06:09:34 PM PDT 24
Peak memory 214708 kb
Host smart-452ea768-307f-4a85-8cbf-b41ba1343096
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646093629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1646093629
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.228815334
Short name T7
Test name
Test status
Simulation time 129603898 ps
CPU time 5.32 seconds
Started Jul 29 06:09:12 PM PDT 24
Finished Jul 29 06:09:17 PM PDT 24
Peak memory 212028 kb
Host smart-0c4a1567-3406-42dc-9c13-77e14bd9b215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228815334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.228815334
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1480661373
Short name T265
Test name
Test status
Simulation time 2262258975 ps
CPU time 97.28 seconds
Started Jul 29 06:09:11 PM PDT 24
Finished Jul 29 06:10:48 PM PDT 24
Peak memory 214500 kb
Host smart-b15fe1c8-bbee-4e66-905e-0c9e04cd8dfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480661373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1480661373
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3345087270
Short name T306
Test name
Test status
Simulation time 173754114 ps
CPU time 9.8 seconds
Started Jul 29 06:09:12 PM PDT 24
Finished Jul 29 06:09:22 PM PDT 24
Peak memory 212888 kb
Host smart-ef729ebe-381b-44bc-af8c-5e0f3a1f761f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345087270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3345087270
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3392133559
Short name T105
Test name
Test status
Simulation time 236917386 ps
CPU time 5.65 seconds
Started Jul 29 06:09:12 PM PDT 24
Finished Jul 29 06:09:18 PM PDT 24
Peak memory 212184 kb
Host smart-02e35972-1dc6-477a-9a16-67bcbed716c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3392133559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3392133559
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3344459120
Short name T155
Test name
Test status
Simulation time 213083605 ps
CPU time 13.67 seconds
Started Jul 29 06:09:10 PM PDT 24
Finished Jul 29 06:09:24 PM PDT 24
Peak memory 213988 kb
Host smart-dcc52513-a248-463b-94c1-3fafc03f7fc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344459120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3344459120
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.559402010
Short name T130
Test name
Test status
Simulation time 523300404 ps
CPU time 5.15 seconds
Started Jul 29 06:09:17 PM PDT 24
Finished Jul 29 06:09:22 PM PDT 24
Peak memory 212044 kb
Host smart-55dd1e01-71eb-4131-8c2b-7eaf965aeb5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559402010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.559402010
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.314251863
Short name T233
Test name
Test status
Simulation time 1467595493 ps
CPU time 69.69 seconds
Started Jul 29 06:09:09 PM PDT 24
Finished Jul 29 06:10:19 PM PDT 24
Peak memory 213340 kb
Host smart-e9b8d558-5091-44f8-83cd-eaaa8a2d5e36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314251863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.314251863
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.306072961
Short name T247
Test name
Test status
Simulation time 250198915 ps
CPU time 11.23 seconds
Started Jul 29 06:09:12 PM PDT 24
Finished Jul 29 06:09:24 PM PDT 24
Peak memory 213140 kb
Host smart-d1f0fcab-42c3-41f3-afec-b11e956aca2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306072961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.306072961
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1714661935
Short name T298
Test name
Test status
Simulation time 704573961 ps
CPU time 6.61 seconds
Started Jul 29 06:09:12 PM PDT 24
Finished Jul 29 06:09:19 PM PDT 24
Peak memory 212052 kb
Host smart-695463df-b669-416c-8dfb-eb7db1996eb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1714661935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1714661935
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2408461523
Short name T135
Test name
Test status
Simulation time 150634964 ps
CPU time 11.01 seconds
Started Jul 29 06:09:09 PM PDT 24
Finished Jul 29 06:09:20 PM PDT 24
Peak memory 212112 kb
Host smart-b8d1ca92-ee1a-4ff1-b255-4bed7ac81072
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408461523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2408461523
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3053200865
Short name T293
Test name
Test status
Simulation time 132810567 ps
CPU time 5.16 seconds
Started Jul 29 06:09:18 PM PDT 24
Finished Jul 29 06:09:23 PM PDT 24
Peak memory 212060 kb
Host smart-25f59134-9f10-4aa0-ba8d-cd2b977fa3aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053200865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3053200865
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.648655011
Short name T92
Test name
Test status
Simulation time 8396864588 ps
CPU time 140.8 seconds
Started Jul 29 06:09:16 PM PDT 24
Finished Jul 29 06:11:37 PM PDT 24
Peak memory 225676 kb
Host smart-44453839-cd61-4c61-9e6e-a3618203963b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648655011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.648655011
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3166786248
Short name T162
Test name
Test status
Simulation time 170366442 ps
CPU time 9.39 seconds
Started Jul 29 06:09:22 PM PDT 24
Finished Jul 29 06:09:32 PM PDT 24
Peak memory 212908 kb
Host smart-14febfe4-d340-40fd-b827-67caf221ad4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166786248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3166786248
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2559797389
Short name T16
Test name
Test status
Simulation time 518572070 ps
CPU time 6.31 seconds
Started Jul 29 06:09:17 PM PDT 24
Finished Jul 29 06:09:24 PM PDT 24
Peak memory 212148 kb
Host smart-7f03efd5-5fb7-477d-96a7-8a61ba819f85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2559797389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2559797389
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1475949223
Short name T179
Test name
Test status
Simulation time 330520177 ps
CPU time 19.4 seconds
Started Jul 29 06:09:18 PM PDT 24
Finished Jul 29 06:09:37 PM PDT 24
Peak memory 215620 kb
Host smart-37bc80de-b987-49d2-9e48-e31ba95e568f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475949223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1475949223
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.11292694
Short name T257
Test name
Test status
Simulation time 928068430 ps
CPU time 4.25 seconds
Started Jul 29 06:09:16 PM PDT 24
Finished Jul 29 06:09:21 PM PDT 24
Peak memory 212048 kb
Host smart-ea5898bf-56f3-4cbb-84d2-7b37263023ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11292694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.11292694
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3416250021
Short name T122
Test name
Test status
Simulation time 2509172481 ps
CPU time 104.71 seconds
Started Jul 29 06:09:16 PM PDT 24
Finished Jul 29 06:11:00 PM PDT 24
Peak memory 225320 kb
Host smart-4761f2a9-1012-4b04-bccc-d3f6acaafddb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416250021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3416250021
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.465131052
Short name T41
Test name
Test status
Simulation time 722722539 ps
CPU time 9.43 seconds
Started Jul 29 06:09:15 PM PDT 24
Finished Jul 29 06:09:24 PM PDT 24
Peak memory 212972 kb
Host smart-b746535a-79b6-4a95-8328-d80d03d7a8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465131052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.465131052
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1922765645
Short name T103
Test name
Test status
Simulation time 548813910 ps
CPU time 6.4 seconds
Started Jul 29 06:09:17 PM PDT 24
Finished Jul 29 06:09:23 PM PDT 24
Peak memory 212208 kb
Host smart-4a33b027-c769-498d-aab8-d93185f5009c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1922765645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1922765645
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1476441139
Short name T72
Test name
Test status
Simulation time 307814156 ps
CPU time 6.8 seconds
Started Jul 29 06:09:18 PM PDT 24
Finished Jul 29 06:09:25 PM PDT 24
Peak memory 212096 kb
Host smart-ab240f1c-9247-4e19-b986-c7777520006b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476441139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1476441139
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2450306177
Short name T60
Test name
Test status
Simulation time 86603410 ps
CPU time 4.17 seconds
Started Jul 29 06:08:51 PM PDT 24
Finished Jul 29 06:08:55 PM PDT 24
Peak memory 212024 kb
Host smart-7292fe8c-b9b8-41cf-a0c0-0c24ed532465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450306177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2450306177
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3707409773
Short name T151
Test name
Test status
Simulation time 4451468625 ps
CPU time 109.12 seconds
Started Jul 29 06:08:47 PM PDT 24
Finished Jul 29 06:10:36 PM PDT 24
Peak memory 228580 kb
Host smart-cc793633-b78e-4f1a-8805-9a2b45d2ae5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707409773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3707409773
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4164816402
Short name T211
Test name
Test status
Simulation time 1037923289 ps
CPU time 11.18 seconds
Started Jul 29 06:08:46 PM PDT 24
Finished Jul 29 06:08:57 PM PDT 24
Peak memory 212872 kb
Host smart-f23ba28c-0ce8-4d92-8c1c-c40033e67783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164816402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.4164816402
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3620344924
Short name T126
Test name
Test status
Simulation time 801532380 ps
CPU time 6.79 seconds
Started Jul 29 06:08:44 PM PDT 24
Finished Jul 29 06:08:51 PM PDT 24
Peak memory 212156 kb
Host smart-5d7790ec-81ba-4b0e-9992-250e81e49168
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3620344924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3620344924
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2392352753
Short name T21
Test name
Test status
Simulation time 246265205 ps
CPU time 53.18 seconds
Started Jul 29 06:08:46 PM PDT 24
Finished Jul 29 06:09:39 PM PDT 24
Peak memory 237480 kb
Host smart-837b5b0f-c1a8-442a-8146-6692e520494b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392352753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2392352753
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.4262382607
Short name T221
Test name
Test status
Simulation time 1115960607 ps
CPU time 6.32 seconds
Started Jul 29 06:08:46 PM PDT 24
Finished Jul 29 06:08:52 PM PDT 24
Peak memory 212220 kb
Host smart-232b12e5-3d95-4f4f-82c8-8c7080ff7ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262382607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.4262382607
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2958540979
Short name T272
Test name
Test status
Simulation time 2546467958 ps
CPU time 8.48 seconds
Started Jul 29 06:08:51 PM PDT 24
Finished Jul 29 06:09:00 PM PDT 24
Peak memory 213244 kb
Host smart-b1115766-0f68-434b-bd4c-1173d1a3ab91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958540979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2958540979
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2003418427
Short name T158
Test name
Test status
Simulation time 127744085 ps
CPU time 5.21 seconds
Started Jul 29 06:09:15 PM PDT 24
Finished Jul 29 06:09:20 PM PDT 24
Peak memory 212036 kb
Host smart-e90e6090-2a94-479e-bd46-8f24c1533e3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003418427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2003418427
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2674644797
Short name T248
Test name
Test status
Simulation time 252261215 ps
CPU time 11.35 seconds
Started Jul 29 06:09:16 PM PDT 24
Finished Jul 29 06:09:27 PM PDT 24
Peak memory 212808 kb
Host smart-412da86c-9205-41aa-bccd-e38095603130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674644797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2674644797
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1136340265
Short name T91
Test name
Test status
Simulation time 137525451 ps
CPU time 6.47 seconds
Started Jul 29 06:09:18 PM PDT 24
Finished Jul 29 06:09:25 PM PDT 24
Peak memory 212192 kb
Host smart-88520b44-6f63-4329-948d-0dc04fc52b20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1136340265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1136340265
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1682379191
Short name T139
Test name
Test status
Simulation time 424744344 ps
CPU time 19.42 seconds
Started Jul 29 06:09:24 PM PDT 24
Finished Jul 29 06:09:43 PM PDT 24
Peak memory 217364 kb
Host smart-b0e686da-e3af-4ec2-807d-5bd21e03de1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682379191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1682379191
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1346649676
Short name T259
Test name
Test status
Simulation time 608387303899 ps
CPU time 4806.06 seconds
Started Jul 29 06:09:16 PM PDT 24
Finished Jul 29 07:29:23 PM PDT 24
Peak memory 253012 kb
Host smart-9f0330bc-168f-4794-a8df-c7b48d9a300b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346649676 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1346649676
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2948163338
Short name T230
Test name
Test status
Simulation time 99827867 ps
CPU time 4.31 seconds
Started Jul 29 06:09:17 PM PDT 24
Finished Jul 29 06:09:21 PM PDT 24
Peak memory 212024 kb
Host smart-3e7f0555-7c31-4a59-b66c-bcf36480767a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948163338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2948163338
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.4293313403
Short name T303
Test name
Test status
Simulation time 6618481332 ps
CPU time 105.06 seconds
Started Jul 29 06:09:22 PM PDT 24
Finished Jul 29 06:11:07 PM PDT 24
Peak memory 227312 kb
Host smart-f7a6a23c-d557-40b2-a609-c5f00e2f5fb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293313403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.4293313403
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3266069845
Short name T192
Test name
Test status
Simulation time 996339950 ps
CPU time 11.37 seconds
Started Jul 29 06:09:16 PM PDT 24
Finished Jul 29 06:09:27 PM PDT 24
Peak memory 212848 kb
Host smart-bee737dd-e528-4d56-8b25-69f23dffd9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266069845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3266069845
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3671216795
Short name T275
Test name
Test status
Simulation time 195603839 ps
CPU time 5.55 seconds
Started Jul 29 06:09:17 PM PDT 24
Finished Jul 29 06:09:23 PM PDT 24
Peak memory 212092 kb
Host smart-1d813196-6658-4e40-8317-e30a8d6b651a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3671216795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3671216795
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.170923167
Short name T77
Test name
Test status
Simulation time 848796427 ps
CPU time 15.32 seconds
Started Jul 29 06:09:18 PM PDT 24
Finished Jul 29 06:09:33 PM PDT 24
Peak memory 214772 kb
Host smart-c6bcf687-b1e5-4db5-af50-f0fafb4ca8b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170923167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.170923167
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1581951960
Short name T48
Test name
Test status
Simulation time 50027480382 ps
CPU time 2001.15 seconds
Started Jul 29 06:09:18 PM PDT 24
Finished Jul 29 06:42:40 PM PDT 24
Peak memory 240644 kb
Host smart-16a730ec-a139-4a8b-a0ab-b4655985ddc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581951960 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.1581951960
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2191566537
Short name T2
Test name
Test status
Simulation time 126332938 ps
CPU time 5.09 seconds
Started Jul 29 06:09:23 PM PDT 24
Finished Jul 29 06:09:28 PM PDT 24
Peak memory 211964 kb
Host smart-ff141541-f5f3-4252-b9c2-cb010eb1c12a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191566537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2191566537
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1212106098
Short name T243
Test name
Test status
Simulation time 2117436768 ps
CPU time 128.52 seconds
Started Jul 29 06:09:14 PM PDT 24
Finished Jul 29 06:11:23 PM PDT 24
Peak memory 236464 kb
Host smart-0f7d5eac-cf68-453c-a242-47565ceea0dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212106098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1212106098
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2821069264
Short name T142
Test name
Test status
Simulation time 1040880827 ps
CPU time 11.21 seconds
Started Jul 29 06:09:23 PM PDT 24
Finished Jul 29 06:09:34 PM PDT 24
Peak memory 213432 kb
Host smart-70a94260-daaa-4a5b-8901-3d2081cd75cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821069264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2821069264
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1765499738
Short name T145
Test name
Test status
Simulation time 277523261 ps
CPU time 6.33 seconds
Started Jul 29 06:09:16 PM PDT 24
Finished Jul 29 06:09:23 PM PDT 24
Peak memory 212120 kb
Host smart-525cb24c-c92a-4873-b26e-280d6f0921f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1765499738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1765499738
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.983977082
Short name T297
Test name
Test status
Simulation time 304403158 ps
CPU time 16.62 seconds
Started Jul 29 06:09:16 PM PDT 24
Finished Jul 29 06:09:33 PM PDT 24
Peak memory 214392 kb
Host smart-174d291d-0f08-4995-8679-64331d01d20f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983977082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.983977082
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.4289703822
Short name T45
Test name
Test status
Simulation time 113069989984 ps
CPU time 2270.62 seconds
Started Jul 29 06:09:23 PM PDT 24
Finished Jul 29 06:47:14 PM PDT 24
Peak memory 238228 kb
Host smart-9463f969-c7d5-4d7f-b1f9-f7e79beb3d81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289703822 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.4289703822
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.462927514
Short name T316
Test name
Test status
Simulation time 132318898 ps
CPU time 5.35 seconds
Started Jul 29 06:09:23 PM PDT 24
Finished Jul 29 06:09:29 PM PDT 24
Peak memory 212184 kb
Host smart-d4419a8e-ea5a-484b-acc2-68d69fc7ff2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462927514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.462927514
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3042516649
Short name T40
Test name
Test status
Simulation time 5375660766 ps
CPU time 155.61 seconds
Started Jul 29 06:09:22 PM PDT 24
Finished Jul 29 06:11:57 PM PDT 24
Peak memory 238448 kb
Host smart-95a7e3b1-aee0-4973-9dd1-861d5dc1b3a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042516649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3042516649
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1088291978
Short name T146
Test name
Test status
Simulation time 170060104 ps
CPU time 9.57 seconds
Started Jul 29 06:09:24 PM PDT 24
Finished Jul 29 06:09:34 PM PDT 24
Peak memory 213072 kb
Host smart-1afd64fc-def8-42d3-81a9-acc0b96e4f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088291978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1088291978
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.4117092487
Short name T180
Test name
Test status
Simulation time 280254669 ps
CPU time 6.5 seconds
Started Jul 29 06:09:25 PM PDT 24
Finished Jul 29 06:09:32 PM PDT 24
Peak memory 212084 kb
Host smart-a3e1e2bd-29f6-4f38-a088-162d1c0c4f3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4117092487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.4117092487
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3568620809
Short name T4
Test name
Test status
Simulation time 1185834085 ps
CPU time 16.39 seconds
Started Jul 29 06:09:23 PM PDT 24
Finished Jul 29 06:09:39 PM PDT 24
Peak memory 215252 kb
Host smart-1fcdcd62-7677-41e3-b4f4-925082b4e882
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568620809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3568620809
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1707136412
Short name T109
Test name
Test status
Simulation time 46423766323 ps
CPU time 936.36 seconds
Started Jul 29 06:09:25 PM PDT 24
Finished Jul 29 06:25:02 PM PDT 24
Peak memory 236644 kb
Host smart-7545fa1f-3e54-4ff2-a6d5-87d4dac80450
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707136412 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1707136412
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2050294934
Short name T159
Test name
Test status
Simulation time 497139455 ps
CPU time 5.05 seconds
Started Jul 29 06:09:24 PM PDT 24
Finished Jul 29 06:09:29 PM PDT 24
Peak memory 211992 kb
Host smart-b353a417-f4c2-4996-8c7b-6bca42e5b7b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050294934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2050294934
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.276409630
Short name T37
Test name
Test status
Simulation time 7602113317 ps
CPU time 109.57 seconds
Started Jul 29 06:09:21 PM PDT 24
Finished Jul 29 06:11:11 PM PDT 24
Peak memory 238472 kb
Host smart-815577fd-040b-459d-95eb-bd96d6f7e2a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276409630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.276409630
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1099282673
Short name T32
Test name
Test status
Simulation time 1043841884 ps
CPU time 11.28 seconds
Started Jul 29 06:09:25 PM PDT 24
Finished Jul 29 06:09:36 PM PDT 24
Peak memory 213420 kb
Host smart-faed78ac-e0cb-454e-9b21-706f3fabe22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099282673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1099282673
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2995060531
Short name T260
Test name
Test status
Simulation time 185983247 ps
CPU time 5.62 seconds
Started Jul 29 06:09:24 PM PDT 24
Finished Jul 29 06:09:29 PM PDT 24
Peak memory 212156 kb
Host smart-8167307d-63ed-4c69-80b7-c3a7c25d1dc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995060531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2995060531
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1281613047
Short name T262
Test name
Test status
Simulation time 252489454 ps
CPU time 5.89 seconds
Started Jul 29 06:09:25 PM PDT 24
Finished Jul 29 06:09:31 PM PDT 24
Peak memory 212060 kb
Host smart-a1cb397e-1cad-4e8b-8a56-07783ffbb9a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281613047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1281613047
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.4047716710
Short name T58
Test name
Test status
Simulation time 87498913 ps
CPU time 4.19 seconds
Started Jul 29 06:09:25 PM PDT 24
Finished Jul 29 06:09:29 PM PDT 24
Peak memory 212012 kb
Host smart-80784332-a369-4388-94d2-63e7e701df8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047716710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.4047716710
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.699734984
Short name T301
Test name
Test status
Simulation time 19055360829 ps
CPU time 127.26 seconds
Started Jul 29 06:09:24 PM PDT 24
Finished Jul 29 06:11:32 PM PDT 24
Peak memory 213448 kb
Host smart-c68541b1-a274-499d-9126-85e65c64042e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699734984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.699734984
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.4070865721
Short name T251
Test name
Test status
Simulation time 994822075 ps
CPU time 16.28 seconds
Started Jul 29 06:09:23 PM PDT 24
Finished Jul 29 06:09:39 PM PDT 24
Peak memory 213232 kb
Host smart-7ee79b9c-fcc1-469e-8006-b7c1c903246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070865721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.4070865721
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3174370502
Short name T205
Test name
Test status
Simulation time 370037974 ps
CPU time 5.46 seconds
Started Jul 29 06:09:25 PM PDT 24
Finished Jul 29 06:09:31 PM PDT 24
Peak memory 212220 kb
Host smart-da783e44-5006-44ae-b116-8593c91eb068
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3174370502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3174370502
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2766799693
Short name T14
Test name
Test status
Simulation time 243385746 ps
CPU time 12.03 seconds
Started Jul 29 06:09:24 PM PDT 24
Finished Jul 29 06:09:36 PM PDT 24
Peak memory 214232 kb
Host smart-cceed323-a11d-4420-9fe4-eb62849ee93a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766799693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2766799693
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3228094727
Short name T23
Test name
Test status
Simulation time 332613326 ps
CPU time 4.19 seconds
Started Jul 29 06:09:30 PM PDT 24
Finished Jul 29 06:09:34 PM PDT 24
Peak memory 212064 kb
Host smart-9be9feaa-cc12-499c-bcc2-1326a0a4540e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228094727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3228094727
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.319248752
Short name T160
Test name
Test status
Simulation time 1949498651 ps
CPU time 79.94 seconds
Started Jul 29 06:09:27 PM PDT 24
Finished Jul 29 06:10:47 PM PDT 24
Peak memory 213324 kb
Host smart-a4348de3-2e44-4626-a74d-8438ea9ac0f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319248752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.319248752
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.205933713
Short name T140
Test name
Test status
Simulation time 920151480 ps
CPU time 11.01 seconds
Started Jul 29 06:09:30 PM PDT 24
Finished Jul 29 06:09:41 PM PDT 24
Peak memory 212840 kb
Host smart-3281e0d5-b286-43a2-94f3-51b1cf777025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205933713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.205933713
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.4155650576
Short name T143
Test name
Test status
Simulation time 578827931 ps
CPU time 6.43 seconds
Started Jul 29 06:09:30 PM PDT 24
Finished Jul 29 06:09:36 PM PDT 24
Peak memory 212160 kb
Host smart-1dc3746f-eb90-4888-a1e7-30ae7a34206b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4155650576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.4155650576
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.832716632
Short name T321
Test name
Test status
Simulation time 1242586264 ps
CPU time 8.56 seconds
Started Jul 29 06:09:28 PM PDT 24
Finished Jul 29 06:09:37 PM PDT 24
Peak memory 212936 kb
Host smart-ed2aa361-a8a6-41a7-b9aa-9f344ae2b475
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832716632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.832716632
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2762831513
Short name T263
Test name
Test status
Simulation time 9196862253 ps
CPU time 2562.68 seconds
Started Jul 29 06:09:29 PM PDT 24
Finished Jul 29 06:52:12 PM PDT 24
Peak memory 224152 kb
Host smart-0051c844-0fdc-476a-9352-54a56d971b04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762831513 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.2762831513
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2281863015
Short name T302
Test name
Test status
Simulation time 520598361 ps
CPU time 4.12 seconds
Started Jul 29 06:09:30 PM PDT 24
Finished Jul 29 06:09:34 PM PDT 24
Peak memory 212056 kb
Host smart-ad9f745b-6194-4aed-aa6c-30e5edb562f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281863015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2281863015
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1047323657
Short name T38
Test name
Test status
Simulation time 19903549055 ps
CPU time 121.07 seconds
Started Jul 29 06:09:27 PM PDT 24
Finished Jul 29 06:11:29 PM PDT 24
Peak memory 229312 kb
Host smart-b8537ef4-ebb1-42c0-8cf8-7ec52944c40d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047323657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1047323657
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1166527214
Short name T207
Test name
Test status
Simulation time 1037255257 ps
CPU time 11.09 seconds
Started Jul 29 06:09:30 PM PDT 24
Finished Jul 29 06:09:41 PM PDT 24
Peak memory 212988 kb
Host smart-74c61f8d-f563-4022-a33f-022a0712b122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166527214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1166527214
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2948825087
Short name T282
Test name
Test status
Simulation time 302188353 ps
CPU time 6.35 seconds
Started Jul 29 06:09:28 PM PDT 24
Finished Jul 29 06:09:34 PM PDT 24
Peak memory 212332 kb
Host smart-ee48aaba-8a2f-4f9d-85d2-885b7a9ffca4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2948825087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2948825087
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2389160321
Short name T94
Test name
Test status
Simulation time 294443888 ps
CPU time 15.24 seconds
Started Jul 29 06:09:30 PM PDT 24
Finished Jul 29 06:09:46 PM PDT 24
Peak memory 215444 kb
Host smart-1a0a0098-423e-4c9f-bfd2-8ee956766691
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389160321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2389160321
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.4023854672
Short name T29
Test name
Test status
Simulation time 85751348 ps
CPU time 4.45 seconds
Started Jul 29 06:09:35 PM PDT 24
Finished Jul 29 06:09:40 PM PDT 24
Peak memory 212048 kb
Host smart-958082e2-7586-4945-9ed9-ca4263ddfc2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023854672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.4023854672
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2489233798
Short name T36
Test name
Test status
Simulation time 2317066083 ps
CPU time 124.59 seconds
Started Jul 29 06:09:27 PM PDT 24
Finished Jul 29 06:11:32 PM PDT 24
Peak memory 237448 kb
Host smart-39535f98-1868-4a57-b9a9-8974c660684c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489233798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2489233798
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2093210360
Short name T277
Test name
Test status
Simulation time 3655270432 ps
CPU time 15.69 seconds
Started Jul 29 06:09:29 PM PDT 24
Finished Jul 29 06:09:45 PM PDT 24
Peak memory 213024 kb
Host smart-7897b7c7-8bf3-44f4-9d46-d599ec48124b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093210360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2093210360
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.528027384
Short name T127
Test name
Test status
Simulation time 1127979903 ps
CPU time 5.4 seconds
Started Jul 29 06:09:30 PM PDT 24
Finished Jul 29 06:09:35 PM PDT 24
Peak memory 212172 kb
Host smart-5be5ba96-1f88-45d6-a0e9-0897b6fdfa99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=528027384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.528027384
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.376505326
Short name T296
Test name
Test status
Simulation time 548035903 ps
CPU time 15.18 seconds
Started Jul 29 06:09:30 PM PDT 24
Finished Jul 29 06:09:45 PM PDT 24
Peak memory 213420 kb
Host smart-d84fb8a5-fba0-4f04-95ef-b0b539a60ec8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376505326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.376505326
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3440818812
Short name T90
Test name
Test status
Simulation time 132431826 ps
CPU time 5.19 seconds
Started Jul 29 06:09:37 PM PDT 24
Finished Jul 29 06:09:42 PM PDT 24
Peak memory 212024 kb
Host smart-0233b356-c8f5-43a3-80f5-418a98e3dc1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440818812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3440818812
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.606167883
Short name T292
Test name
Test status
Simulation time 25042295735 ps
CPU time 129.76 seconds
Started Jul 29 06:09:36 PM PDT 24
Finished Jul 29 06:11:46 PM PDT 24
Peak memory 239912 kb
Host smart-a4c925b5-c487-4501-bf5b-cf7088c0d21f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606167883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.606167883
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2033266972
Short name T208
Test name
Test status
Simulation time 215721931 ps
CPU time 9.41 seconds
Started Jul 29 06:09:37 PM PDT 24
Finished Jul 29 06:09:47 PM PDT 24
Peak memory 212848 kb
Host smart-850aca42-ea56-436c-8bf6-94c111484964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033266972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2033266972
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1068492769
Short name T181
Test name
Test status
Simulation time 96964172 ps
CPU time 5.66 seconds
Started Jul 29 06:09:36 PM PDT 24
Finished Jul 29 06:09:42 PM PDT 24
Peak memory 212140 kb
Host smart-50a35ffb-4d0c-496c-98c9-ff6ecfb24461
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1068492769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1068492769
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.845583986
Short name T255
Test name
Test status
Simulation time 128573933 ps
CPU time 5.07 seconds
Started Jul 29 06:08:53 PM PDT 24
Finished Jul 29 06:08:58 PM PDT 24
Peak memory 212028 kb
Host smart-8b198b93-b9c1-4794-8ae6-681d606d2657
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845583986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.845583986
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1612204394
Short name T124
Test name
Test status
Simulation time 676817361 ps
CPU time 11.29 seconds
Started Jul 29 06:08:51 PM PDT 24
Finished Jul 29 06:09:03 PM PDT 24
Peak memory 213176 kb
Host smart-c1a93ad9-f7e7-44ed-8927-5977404487d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612204394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1612204394
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.83534520
Short name T188
Test name
Test status
Simulation time 815262118 ps
CPU time 6.35 seconds
Started Jul 29 06:08:52 PM PDT 24
Finished Jul 29 06:08:59 PM PDT 24
Peak memory 212144 kb
Host smart-72b8d279-1979-4b2c-8fc6-785ca56c4c02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=83534520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.83534520
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2401420830
Short name T26
Test name
Test status
Simulation time 503050419 ps
CPU time 58.34 seconds
Started Jul 29 06:08:52 PM PDT 24
Finished Jul 29 06:09:50 PM PDT 24
Peak memory 238596 kb
Host smart-513d9e04-4977-4789-8ae6-41863e87d761
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401420830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2401420830
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3967533609
Short name T218
Test name
Test status
Simulation time 370527378 ps
CPU time 5.71 seconds
Started Jul 29 06:08:54 PM PDT 24
Finished Jul 29 06:09:00 PM PDT 24
Peak memory 212204 kb
Host smart-b3c333f9-0c85-4a56-88ba-531da908ff84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967533609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3967533609
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1958886543
Short name T285
Test name
Test status
Simulation time 166588276 ps
CPU time 10.08 seconds
Started Jul 29 06:08:50 PM PDT 24
Finished Jul 29 06:09:00 PM PDT 24
Peak memory 212784 kb
Host smart-79941097-a7ec-4458-ad20-d9e1851dcd5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958886543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1958886543
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1507655750
Short name T148
Test name
Test status
Simulation time 132119294 ps
CPU time 5.23 seconds
Started Jul 29 06:09:36 PM PDT 24
Finished Jul 29 06:09:41 PM PDT 24
Peak memory 212028 kb
Host smart-52fe8a68-3db8-4943-b4d0-b51f40e32865
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507655750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1507655750
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2260738927
Short name T224
Test name
Test status
Simulation time 4441415319 ps
CPU time 116.99 seconds
Started Jul 29 06:09:36 PM PDT 24
Finished Jul 29 06:11:34 PM PDT 24
Peak memory 229396 kb
Host smart-faf1c251-9de7-49b9-baa2-d901d1acddd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260738927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2260738927
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2711741889
Short name T8
Test name
Test status
Simulation time 2088375431 ps
CPU time 9.77 seconds
Started Jul 29 06:09:34 PM PDT 24
Finished Jul 29 06:09:44 PM PDT 24
Peak memory 213340 kb
Host smart-2476f701-c1ed-4f33-9905-61badb40346b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711741889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2711741889
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2439524796
Short name T107
Test name
Test status
Simulation time 522590255 ps
CPU time 6.18 seconds
Started Jul 29 06:09:34 PM PDT 24
Finished Jul 29 06:09:40 PM PDT 24
Peak memory 212092 kb
Host smart-26cd8beb-a280-4d22-a023-238781f23f90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2439524796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2439524796
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2044845813
Short name T310
Test name
Test status
Simulation time 729802593 ps
CPU time 11.56 seconds
Started Jul 29 06:09:41 PM PDT 24
Finished Jul 29 06:09:53 PM PDT 24
Peak memory 213460 kb
Host smart-d265001f-df97-4d85-9f3c-5adc89b95cba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044845813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2044845813
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.4194036544
Short name T311
Test name
Test status
Simulation time 131649837 ps
CPU time 5 seconds
Started Jul 29 06:09:38 PM PDT 24
Finished Jul 29 06:09:43 PM PDT 24
Peak memory 212040 kb
Host smart-a8d1d4ba-bbba-4e2c-b7c4-9ebdca434d87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194036544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4194036544
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4269994496
Short name T161
Test name
Test status
Simulation time 6430621168 ps
CPU time 110.64 seconds
Started Jul 29 06:09:41 PM PDT 24
Finished Jul 29 06:11:32 PM PDT 24
Peak memory 235444 kb
Host smart-ba1b4598-329f-40c3-b13f-3de8c056f37a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269994496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.4269994496
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.25350879
Short name T320
Test name
Test status
Simulation time 694691904 ps
CPU time 9.81 seconds
Started Jul 29 06:09:39 PM PDT 24
Finished Jul 29 06:09:49 PM PDT 24
Peak memory 212920 kb
Host smart-f71eb306-e990-4e5b-a837-b0ab1684a324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25350879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.25350879
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1053211992
Short name T283
Test name
Test status
Simulation time 286173410 ps
CPU time 6.84 seconds
Started Jul 29 06:09:41 PM PDT 24
Finished Jul 29 06:09:48 PM PDT 24
Peak memory 212136 kb
Host smart-45125ce6-39ad-497e-b7d5-d964cb18fac3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1053211992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1053211992
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1556248922
Short name T167
Test name
Test status
Simulation time 233397329 ps
CPU time 5.97 seconds
Started Jul 29 06:09:35 PM PDT 24
Finished Jul 29 06:09:41 PM PDT 24
Peak memory 212072 kb
Host smart-42509480-cf14-4ee6-9c8c-39a5de992788
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556248922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1556248922
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1196163375
Short name T128
Test name
Test status
Simulation time 128002321 ps
CPU time 5.14 seconds
Started Jul 29 06:09:40 PM PDT 24
Finished Jul 29 06:09:45 PM PDT 24
Peak memory 212224 kb
Host smart-559ff153-6636-4877-aff8-c70c052c7fed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196163375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1196163375
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3506843691
Short name T9
Test name
Test status
Simulation time 1901196932 ps
CPU time 102.13 seconds
Started Jul 29 06:09:40 PM PDT 24
Finished Jul 29 06:11:22 PM PDT 24
Peak memory 237268 kb
Host smart-a0d4f745-bc7f-4580-bf19-d7835e7a573e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506843691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3506843691
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4144158081
Short name T245
Test name
Test status
Simulation time 524723187 ps
CPU time 11.17 seconds
Started Jul 29 06:09:41 PM PDT 24
Finished Jul 29 06:09:52 PM PDT 24
Peak memory 212956 kb
Host smart-5266cb6c-a8c2-4770-871c-35b2acf092e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144158081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.4144158081
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1142934949
Short name T177
Test name
Test status
Simulation time 349916529 ps
CPU time 6.53 seconds
Started Jul 29 06:09:41 PM PDT 24
Finished Jul 29 06:09:47 PM PDT 24
Peak memory 212156 kb
Host smart-55c79db1-5be4-400f-8102-c38c8df0eda8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1142934949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1142934949
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.751303668
Short name T239
Test name
Test status
Simulation time 1674554452 ps
CPU time 20 seconds
Started Jul 29 06:09:41 PM PDT 24
Finished Jul 29 06:10:01 PM PDT 24
Peak memory 214220 kb
Host smart-26a7658a-8046-4bee-9343-15c0b5bfc423
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751303668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.751303668
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1711879272
Short name T271
Test name
Test status
Simulation time 269207964 ps
CPU time 4.3 seconds
Started Jul 29 06:09:40 PM PDT 24
Finished Jul 29 06:09:45 PM PDT 24
Peak memory 212076 kb
Host smart-ca9db8e2-a027-495f-b744-99e9b3ac0e43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711879272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1711879272
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1370343436
Short name T150
Test name
Test status
Simulation time 4746136378 ps
CPU time 140.36 seconds
Started Jul 29 06:09:40 PM PDT 24
Finished Jul 29 06:12:00 PM PDT 24
Peak memory 238428 kb
Host smart-9c22146f-8741-414a-91dd-a39954b9b268
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370343436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1370343436
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4279365896
Short name T215
Test name
Test status
Simulation time 263349857 ps
CPU time 11.6 seconds
Started Jul 29 06:09:40 PM PDT 24
Finished Jul 29 06:09:51 PM PDT 24
Peak memory 212936 kb
Host smart-be90e772-6fd8-4b6b-93a9-07e69c494b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279365896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.4279365896
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3520001033
Short name T132
Test name
Test status
Simulation time 850120243 ps
CPU time 5.65 seconds
Started Jul 29 06:09:41 PM PDT 24
Finished Jul 29 06:09:47 PM PDT 24
Peak memory 212096 kb
Host smart-7f345418-afb7-432a-a3d3-08eee63c28bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3520001033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3520001033
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.704496492
Short name T216
Test name
Test status
Simulation time 1070160932 ps
CPU time 15.2 seconds
Started Jul 29 06:09:41 PM PDT 24
Finished Jul 29 06:09:56 PM PDT 24
Peak memory 214392 kb
Host smart-b86b29ab-14b4-4135-8c8a-35cce2c8e76b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704496492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.704496492
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.171077774
Short name T266
Test name
Test status
Simulation time 256623132 ps
CPU time 5.08 seconds
Started Jul 29 06:09:46 PM PDT 24
Finished Jul 29 06:09:51 PM PDT 24
Peak memory 212012 kb
Host smart-b562c8bb-42f0-4cf2-bc5f-fc010e3cba31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171077774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.171077774
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3537010379
Short name T256
Test name
Test status
Simulation time 3290205896 ps
CPU time 61.91 seconds
Started Jul 29 06:09:44 PM PDT 24
Finished Jul 29 06:10:46 PM PDT 24
Peak memory 237352 kb
Host smart-2a45d589-0e8d-4a7f-96a3-d6f1ccb3b538
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537010379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3537010379
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1808573030
Short name T3
Test name
Test status
Simulation time 168669587 ps
CPU time 9.52 seconds
Started Jul 29 06:09:45 PM PDT 24
Finished Jul 29 06:09:54 PM PDT 24
Peak memory 212896 kb
Host smart-7d913bcd-69fa-430a-9277-99973dc36770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808573030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1808573030
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2398334713
Short name T191
Test name
Test status
Simulation time 144428128 ps
CPU time 6.81 seconds
Started Jul 29 06:09:46 PM PDT 24
Finished Jul 29 06:09:53 PM PDT 24
Peak memory 212092 kb
Host smart-9699d6f4-d96f-4330-b9e6-5b59a1167226
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2398334713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2398334713
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.197399887
Short name T183
Test name
Test status
Simulation time 292229919 ps
CPU time 13.97 seconds
Started Jul 29 06:09:44 PM PDT 24
Finished Jul 29 06:09:58 PM PDT 24
Peak memory 215844 kb
Host smart-49444d8a-9087-4f21-aec8-00c55eca7f04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197399887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.197399887
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.811404643
Short name T13
Test name
Test status
Simulation time 158530705514 ps
CPU time 1505.22 seconds
Started Jul 29 06:09:46 PM PDT 24
Finished Jul 29 06:34:51 PM PDT 24
Peak memory 234668 kb
Host smart-0d0d7171-6f8d-4402-9c6e-4b1ef4a9c717
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811404643 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.811404643
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.466763961
Short name T131
Test name
Test status
Simulation time 162468086 ps
CPU time 4.17 seconds
Started Jul 29 06:09:44 PM PDT 24
Finished Jul 29 06:09:49 PM PDT 24
Peak memory 212028 kb
Host smart-25c47fd7-deb4-4515-b4f1-f8c205a8da8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466763961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.466763961
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2748355718
Short name T169
Test name
Test status
Simulation time 7915877313 ps
CPU time 215.85 seconds
Started Jul 29 06:09:46 PM PDT 24
Finished Jul 29 06:13:22 PM PDT 24
Peak memory 239456 kb
Host smart-e552e8d5-5418-49c8-95c7-56901123ae17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748355718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2748355718
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.709247268
Short name T89
Test name
Test status
Simulation time 16449583425 ps
CPU time 16.76 seconds
Started Jul 29 06:09:49 PM PDT 24
Finished Jul 29 06:10:06 PM PDT 24
Peak memory 213240 kb
Host smart-f775d8d2-0808-4750-9bcd-836f0584e3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709247268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.709247268
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.510495832
Short name T201
Test name
Test status
Simulation time 100533334 ps
CPU time 5.61 seconds
Started Jul 29 06:09:47 PM PDT 24
Finished Jul 29 06:09:52 PM PDT 24
Peak memory 212132 kb
Host smart-6554a64e-84ee-40b2-9ea5-9d024dfae976
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=510495832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.510495832
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2959586360
Short name T246
Test name
Test status
Simulation time 822936533 ps
CPU time 18.57 seconds
Started Jul 29 06:09:45 PM PDT 24
Finished Jul 29 06:10:04 PM PDT 24
Peak memory 214788 kb
Host smart-57df361a-eb40-436c-8434-294e547ea5c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959586360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2959586360
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3428074656
Short name T308
Test name
Test status
Simulation time 418582285 ps
CPU time 4.27 seconds
Started Jul 29 06:09:46 PM PDT 24
Finished Jul 29 06:09:50 PM PDT 24
Peak memory 212024 kb
Host smart-e6808c28-3829-422c-b9e8-050f0b83c448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428074656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3428074656
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3854528562
Short name T165
Test name
Test status
Simulation time 3543978551 ps
CPU time 227.71 seconds
Started Jul 29 06:09:45 PM PDT 24
Finished Jul 29 06:13:33 PM PDT 24
Peak memory 238412 kb
Host smart-1756ddc1-ca0f-495d-869a-872d3c17bada
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854528562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3854528562
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1152428511
Short name T229
Test name
Test status
Simulation time 347994655 ps
CPU time 9.65 seconds
Started Jul 29 06:09:45 PM PDT 24
Finished Jul 29 06:09:55 PM PDT 24
Peak memory 212824 kb
Host smart-949d7430-2cc9-4536-bd74-97d0ed10631f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152428511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1152428511
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.652402519
Short name T294
Test name
Test status
Simulation time 136654840 ps
CPU time 6.47 seconds
Started Jul 29 06:09:45 PM PDT 24
Finished Jul 29 06:09:52 PM PDT 24
Peak memory 212176 kb
Host smart-093fca5b-88b0-40d5-b6ad-89613818feba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=652402519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.652402519
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2013091390
Short name T315
Test name
Test status
Simulation time 754642723 ps
CPU time 10.3 seconds
Started Jul 29 06:09:44 PM PDT 24
Finished Jul 29 06:09:55 PM PDT 24
Peak memory 212140 kb
Host smart-a59ed830-7f18-44b7-93ae-a26bc0465f62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013091390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2013091390
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1546248996
Short name T35
Test name
Test status
Simulation time 501105575 ps
CPU time 5.15 seconds
Started Jul 29 06:09:44 PM PDT 24
Finished Jul 29 06:09:49 PM PDT 24
Peak memory 212068 kb
Host smart-707f100a-1803-4a6b-97d6-74908ab7ce4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546248996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1546248996
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2969106935
Short name T258
Test name
Test status
Simulation time 10552979329 ps
CPU time 124.95 seconds
Started Jul 29 06:09:46 PM PDT 24
Finished Jul 29 06:11:51 PM PDT 24
Peak memory 238500 kb
Host smart-1c55aa4d-4869-44c5-b3b7-23195adef64d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969106935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2969106935
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.454007587
Short name T317
Test name
Test status
Simulation time 3107078017 ps
CPU time 11.27 seconds
Started Jul 29 06:09:47 PM PDT 24
Finished Jul 29 06:09:58 PM PDT 24
Peak memory 212996 kb
Host smart-a56bc0d4-8509-409b-8a4a-1cafc4414d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454007587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.454007587
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.334228656
Short name T200
Test name
Test status
Simulation time 142892834 ps
CPU time 6.66 seconds
Started Jul 29 06:09:46 PM PDT 24
Finished Jul 29 06:09:53 PM PDT 24
Peak memory 212056 kb
Host smart-8f7fea37-ad0b-4554-b43e-c3976187d267
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=334228656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.334228656
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2969952403
Short name T170
Test name
Test status
Simulation time 1331046632 ps
CPU time 12.84 seconds
Started Jul 29 06:09:48 PM PDT 24
Finished Jul 29 06:10:01 PM PDT 24
Peak memory 214352 kb
Host smart-86ee5650-e1db-4920-9366-566fdb8b1b2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969952403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2969952403
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2373805533
Short name T106
Test name
Test status
Simulation time 348876182 ps
CPU time 4.22 seconds
Started Jul 29 06:09:51 PM PDT 24
Finished Jul 29 06:09:55 PM PDT 24
Peak memory 212036 kb
Host smart-0089b238-fd9e-4985-927a-aed5f0d010d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373805533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2373805533
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3795848765
Short name T34
Test name
Test status
Simulation time 4841478636 ps
CPU time 141.27 seconds
Started Jul 29 06:09:47 PM PDT 24
Finished Jul 29 06:12:09 PM PDT 24
Peak memory 238468 kb
Host smart-0300c20c-982a-413f-8a0f-08b05db32b8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795848765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3795848765
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3297856874
Short name T269
Test name
Test status
Simulation time 667787946 ps
CPU time 9.55 seconds
Started Jul 29 06:09:54 PM PDT 24
Finished Jul 29 06:10:04 PM PDT 24
Peak memory 212900 kb
Host smart-b9f59aaf-950d-492f-ada9-538518dda001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297856874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3297856874
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1620115947
Short name T240
Test name
Test status
Simulation time 347845449 ps
CPU time 5.82 seconds
Started Jul 29 06:09:48 PM PDT 24
Finished Jul 29 06:09:54 PM PDT 24
Peak memory 212152 kb
Host smart-73667881-e177-4abc-a91a-27c1a024595d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1620115947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1620115947
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2916721903
Short name T185
Test name
Test status
Simulation time 1206259059 ps
CPU time 13.22 seconds
Started Jul 29 06:09:46 PM PDT 24
Finished Jul 29 06:09:59 PM PDT 24
Peak memory 214796 kb
Host smart-c002a120-5055-433e-8adb-7d9bb5f6abee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916721903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2916721903
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.837715865
Short name T284
Test name
Test status
Simulation time 172953663 ps
CPU time 4.27 seconds
Started Jul 29 06:09:52 PM PDT 24
Finished Jul 29 06:09:57 PM PDT 24
Peak memory 212068 kb
Host smart-1782d1a0-0b7d-4be1-ad37-b126672ef2f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837715865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.837715865
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.731035603
Short name T198
Test name
Test status
Simulation time 2854177427 ps
CPU time 157.2 seconds
Started Jul 29 06:09:52 PM PDT 24
Finished Jul 29 06:12:29 PM PDT 24
Peak memory 238504 kb
Host smart-97fb5106-82e3-4957-bc96-64effebee79d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731035603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.731035603
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3369892372
Short name T313
Test name
Test status
Simulation time 388246647 ps
CPU time 9.42 seconds
Started Jul 29 06:09:50 PM PDT 24
Finished Jul 29 06:10:00 PM PDT 24
Peak memory 212844 kb
Host smart-c1858540-1957-4df4-8b3c-4f5c382d3c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369892372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3369892372
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2427161759
Short name T190
Test name
Test status
Simulation time 6318678665 ps
CPU time 8.91 seconds
Started Jul 29 06:09:58 PM PDT 24
Finished Jul 29 06:10:07 PM PDT 24
Peak memory 212256 kb
Host smart-c534a28f-9132-4bf6-b9e8-1846ec32a5f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2427161759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2427161759
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1143077054
Short name T166
Test name
Test status
Simulation time 2058233922 ps
CPU time 18.26 seconds
Started Jul 29 06:09:51 PM PDT 24
Finished Jul 29 06:10:09 PM PDT 24
Peak memory 214312 kb
Host smart-8f9fb502-661c-4d26-9459-d1da4aef5d88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143077054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1143077054
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3988320589
Short name T197
Test name
Test status
Simulation time 86255403 ps
CPU time 4.25 seconds
Started Jul 29 06:08:51 PM PDT 24
Finished Jul 29 06:08:55 PM PDT 24
Peak memory 212216 kb
Host smart-ba859f46-071f-4fcc-ba69-79e530afd84a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988320589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3988320589
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3734988071
Short name T274
Test name
Test status
Simulation time 2259387516 ps
CPU time 108.15 seconds
Started Jul 29 06:08:53 PM PDT 24
Finished Jul 29 06:10:41 PM PDT 24
Peak memory 234412 kb
Host smart-40b5624d-3101-4afe-ab2e-6af1fb3b0f52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734988071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3734988071
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1852698301
Short name T42
Test name
Test status
Simulation time 334107412 ps
CPU time 9.63 seconds
Started Jul 29 06:08:52 PM PDT 24
Finished Jul 29 06:09:01 PM PDT 24
Peak memory 212960 kb
Host smart-f5cc04b7-614e-422d-8835-10c8facc024a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852698301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1852698301
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.689670836
Short name T157
Test name
Test status
Simulation time 1356084114 ps
CPU time 6.01 seconds
Started Jul 29 06:08:52 PM PDT 24
Finished Jul 29 06:08:59 PM PDT 24
Peak memory 212124 kb
Host smart-ae125f85-c01a-4da7-b021-92cd1c98c673
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=689670836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.689670836
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.941497791
Short name T15
Test name
Test status
Simulation time 375280410 ps
CPU time 5.45 seconds
Started Jul 29 06:08:51 PM PDT 24
Finished Jul 29 06:08:56 PM PDT 24
Peak memory 212112 kb
Host smart-e53227bd-5d6c-4db9-a7ba-b3843009ac59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941497791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.941497791
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3352654155
Short name T6
Test name
Test status
Simulation time 2394214746 ps
CPU time 24.96 seconds
Started Jul 29 06:08:54 PM PDT 24
Finished Jul 29 06:09:19 PM PDT 24
Peak memory 216692 kb
Host smart-e73f2a4f-64b3-44d9-8bea-b3a9682e7767
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352654155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3352654155
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3839012004
Short name T236
Test name
Test status
Simulation time 87265267308 ps
CPU time 1604.8 seconds
Started Jul 29 06:08:53 PM PDT 24
Finished Jul 29 06:35:38 PM PDT 24
Peak memory 236676 kb
Host smart-06daf1bb-8a1f-4c6a-b48e-c8d2c2760627
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839012004 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.3839012004
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1634124709
Short name T279
Test name
Test status
Simulation time 687984015 ps
CPU time 7.63 seconds
Started Jul 29 06:09:55 PM PDT 24
Finished Jul 29 06:10:02 PM PDT 24
Peak memory 212088 kb
Host smart-c992b143-642c-4d22-b6d2-4ffafb27b3de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634124709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1634124709
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2754670432
Short name T286
Test name
Test status
Simulation time 4858623684 ps
CPU time 116.55 seconds
Started Jul 29 06:09:58 PM PDT 24
Finished Jul 29 06:11:55 PM PDT 24
Peak memory 228188 kb
Host smart-3e0fd7ac-94d5-4b8b-9db2-6b6f0ed8413a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754670432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2754670432
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3207195539
Short name T276
Test name
Test status
Simulation time 496474418 ps
CPU time 11.59 seconds
Started Jul 29 06:09:54 PM PDT 24
Finished Jul 29 06:10:05 PM PDT 24
Peak memory 212988 kb
Host smart-8229df25-4af2-436a-9f3a-fc8e37c36ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207195539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3207195539
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3440632511
Short name T28
Test name
Test status
Simulation time 502830334 ps
CPU time 8.37 seconds
Started Jul 29 06:09:50 PM PDT 24
Finished Jul 29 06:09:59 PM PDT 24
Peak memory 212172 kb
Host smart-dc1bc599-ef8f-4679-84e1-3a29676bf0c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440632511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3440632511
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3985113552
Short name T78
Test name
Test status
Simulation time 1092806871 ps
CPU time 14.7 seconds
Started Jul 29 06:09:55 PM PDT 24
Finished Jul 29 06:10:10 PM PDT 24
Peak memory 213448 kb
Host smart-0f962b53-ccce-4720-9fac-e2966f113189
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985113552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3985113552
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2603840819
Short name T252
Test name
Test status
Simulation time 48817070950 ps
CPU time 1291.04 seconds
Started Jul 29 06:09:52 PM PDT 24
Finished Jul 29 06:31:23 PM PDT 24
Peak memory 236632 kb
Host smart-d07531ff-023e-4998-99f0-942bc14014da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603840819 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.2603840819
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2975522079
Short name T163
Test name
Test status
Simulation time 1132650631 ps
CPU time 5.09 seconds
Started Jul 29 06:09:52 PM PDT 24
Finished Jul 29 06:09:58 PM PDT 24
Peak memory 211968 kb
Host smart-c0ec3a0e-440a-4cce-a893-ebf3ce394660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975522079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2975522079
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1105749555
Short name T175
Test name
Test status
Simulation time 39421408643 ps
CPU time 158.95 seconds
Started Jul 29 06:09:58 PM PDT 24
Finished Jul 29 06:12:37 PM PDT 24
Peak memory 214476 kb
Host smart-0c8d695a-cd60-4fa7-b177-8e8c9bb7e070
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105749555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1105749555
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2722791489
Short name T307
Test name
Test status
Simulation time 754062049 ps
CPU time 9.48 seconds
Started Jul 29 06:09:58 PM PDT 24
Finished Jul 29 06:10:08 PM PDT 24
Peak memory 212816 kb
Host smart-c0b7a295-5102-44af-bec3-24d63036d6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722791489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2722791489
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.291925794
Short name T61
Test name
Test status
Simulation time 382803400 ps
CPU time 5.23 seconds
Started Jul 29 06:09:52 PM PDT 24
Finished Jul 29 06:09:57 PM PDT 24
Peak memory 212136 kb
Host smart-f9e9ee78-fc10-4511-95ea-e92e9550cf39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=291925794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.291925794
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.4163668027
Short name T74
Test name
Test status
Simulation time 576020030 ps
CPU time 24.47 seconds
Started Jul 29 06:09:52 PM PDT 24
Finished Jul 29 06:10:16 PM PDT 24
Peak memory 214820 kb
Host smart-60749297-8b97-4140-8a2c-46cc7820dd16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163668027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.4163668027
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1792450609
Short name T249
Test name
Test status
Simulation time 6001926647 ps
CPU time 72.96 seconds
Started Jul 29 06:09:55 PM PDT 24
Finished Jul 29 06:11:08 PM PDT 24
Peak memory 238460 kb
Host smart-85682e9f-25bd-4230-902b-2240a6229dd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792450609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1792450609
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2442223619
Short name T280
Test name
Test status
Simulation time 595538264 ps
CPU time 9.75 seconds
Started Jul 29 06:09:58 PM PDT 24
Finished Jul 29 06:10:08 PM PDT 24
Peak memory 213040 kb
Host smart-71b5e628-a99e-498e-a8a2-98f2ef90d8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442223619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2442223619
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1822716106
Short name T108
Test name
Test status
Simulation time 109538596 ps
CPU time 5.62 seconds
Started Jul 29 06:09:57 PM PDT 24
Finished Jul 29 06:10:03 PM PDT 24
Peak memory 212116 kb
Host smart-0d09417d-7d18-4b0e-b754-5c4ad908a8ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1822716106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1822716106
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1149883450
Short name T295
Test name
Test status
Simulation time 694103690 ps
CPU time 17 seconds
Started Jul 29 06:09:56 PM PDT 24
Finished Jul 29 06:10:13 PM PDT 24
Peak memory 214796 kb
Host smart-df956a51-1095-42fa-a27b-1c5febb47cf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149883450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1149883450
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3998863575
Short name T93
Test name
Test status
Simulation time 358306030 ps
CPU time 5.07 seconds
Started Jul 29 06:10:00 PM PDT 24
Finished Jul 29 06:10:05 PM PDT 24
Peak memory 211952 kb
Host smart-4ad0168e-7a75-4976-8674-7da8309b4cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998863575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3998863575
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3717712553
Short name T202
Test name
Test status
Simulation time 1629788484 ps
CPU time 96 seconds
Started Jul 29 06:09:58 PM PDT 24
Finished Jul 29 06:11:34 PM PDT 24
Peak memory 237216 kb
Host smart-76fefb5f-95c8-437c-a4f7-6ba93e01d58c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717712553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3717712553
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.578052829
Short name T154
Test name
Test status
Simulation time 496783941 ps
CPU time 5.39 seconds
Started Jul 29 06:09:56 PM PDT 24
Finished Jul 29 06:10:02 PM PDT 24
Peak memory 212092 kb
Host smart-b40bbc63-4233-4aa9-bb85-b51260517b04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=578052829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.578052829
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.8154449
Short name T193
Test name
Test status
Simulation time 492272768 ps
CPU time 8.13 seconds
Started Jul 29 06:09:58 PM PDT 24
Finished Jul 29 06:10:06 PM PDT 24
Peak memory 212068 kb
Host smart-30296bdf-a25e-4369-8db4-b6d6c2e1a547
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8154449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.rom_ctrl_stress_all.8154449
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1833582232
Short name T138
Test name
Test status
Simulation time 479506539 ps
CPU time 5.14 seconds
Started Jul 29 06:09:59 PM PDT 24
Finished Jul 29 06:10:04 PM PDT 24
Peak memory 212028 kb
Host smart-0c5eb5b7-1c10-4a4b-b744-53227da4ccaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833582232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1833582232
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3146831565
Short name T309
Test name
Test status
Simulation time 15712074230 ps
CPU time 207.84 seconds
Started Jul 29 06:09:58 PM PDT 24
Finished Jul 29 06:13:26 PM PDT 24
Peak memory 237524 kb
Host smart-efaf8e3d-3675-4e89-a68a-5e2de479ede9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146831565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3146831565
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.104972822
Short name T184
Test name
Test status
Simulation time 521460334 ps
CPU time 11.28 seconds
Started Jul 29 06:09:59 PM PDT 24
Finished Jul 29 06:10:10 PM PDT 24
Peak memory 212948 kb
Host smart-ec77c180-ab7c-4f8a-a19e-ad78ccf97169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104972822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.104972822
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2397142796
Short name T17
Test name
Test status
Simulation time 373612407 ps
CPU time 5.57 seconds
Started Jul 29 06:09:58 PM PDT 24
Finished Jul 29 06:10:04 PM PDT 24
Peak memory 212136 kb
Host smart-2fc20699-0e45-413e-8933-6bb5c4078f08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2397142796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2397142796
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4181964000
Short name T219
Test name
Test status
Simulation time 6114335518 ps
CPU time 27.92 seconds
Started Jul 29 06:09:55 PM PDT 24
Finished Jul 29 06:10:23 PM PDT 24
Peak memory 216916 kb
Host smart-228444d1-e18f-4f7e-b587-efe4016993e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181964000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4181964000
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2584562214
Short name T153
Test name
Test status
Simulation time 524331624 ps
CPU time 5.04 seconds
Started Jul 29 06:09:56 PM PDT 24
Finished Jul 29 06:10:01 PM PDT 24
Peak memory 212044 kb
Host smart-030d4d5f-550d-4807-b34a-30fdc367d756
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584562214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2584562214
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1578096840
Short name T287
Test name
Test status
Simulation time 8431499140 ps
CPU time 82.59 seconds
Started Jul 29 06:09:55 PM PDT 24
Finished Jul 29 06:11:18 PM PDT 24
Peak memory 228252 kb
Host smart-eb83a769-812c-4833-b9a4-8880c7741ad0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578096840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1578096840
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.685964355
Short name T129
Test name
Test status
Simulation time 255531188 ps
CPU time 11.19 seconds
Started Jul 29 06:10:01 PM PDT 24
Finished Jul 29 06:10:12 PM PDT 24
Peak memory 212880 kb
Host smart-edae1e67-40fa-4ad9-baba-65a4ed211ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685964355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.685964355
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1205221793
Short name T237
Test name
Test status
Simulation time 1141868665 ps
CPU time 17.91 seconds
Started Jul 29 06:09:56 PM PDT 24
Finished Jul 29 06:10:14 PM PDT 24
Peak memory 213736 kb
Host smart-c70f21cc-d13b-4800-8f39-594d0e4faf27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205221793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1205221793
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.578557999
Short name T50
Test name
Test status
Simulation time 124025140302 ps
CPU time 6111.29 seconds
Started Jul 29 06:09:59 PM PDT 24
Finished Jul 29 07:51:51 PM PDT 24
Peak memory 236660 kb
Host smart-be9c3672-94f6-4530-baa8-71bf5b89f208
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578557999 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.578557999
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.252650482
Short name T11
Test name
Test status
Simulation time 90482493 ps
CPU time 4.33 seconds
Started Jul 29 06:09:58 PM PDT 24
Finished Jul 29 06:10:03 PM PDT 24
Peak memory 212000 kb
Host smart-8b854abc-98d0-49eb-95d6-aa431e0290a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252650482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.252650482
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1506392929
Short name T242
Test name
Test status
Simulation time 945341766 ps
CPU time 63.5 seconds
Started Jul 29 06:09:57 PM PDT 24
Finished Jul 29 06:11:01 PM PDT 24
Peak memory 236932 kb
Host smart-b246b51a-ff89-48af-9445-6e0c4d5f961b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506392929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1506392929
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2519713791
Short name T203
Test name
Test status
Simulation time 260582701 ps
CPU time 11.45 seconds
Started Jul 29 06:10:01 PM PDT 24
Finished Jul 29 06:10:13 PM PDT 24
Peak memory 213244 kb
Host smart-18c9aca5-0388-4f72-b98e-c63b7025bb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519713791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2519713791
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2328333665
Short name T95
Test name
Test status
Simulation time 110884200 ps
CPU time 5.71 seconds
Started Jul 29 06:09:58 PM PDT 24
Finished Jul 29 06:10:04 PM PDT 24
Peak memory 212180 kb
Host smart-7436e71a-69fd-4c87-9a8b-ec2149e63eec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2328333665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2328333665
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.375467446
Short name T234
Test name
Test status
Simulation time 168320680 ps
CPU time 8.62 seconds
Started Jul 29 06:09:57 PM PDT 24
Finished Jul 29 06:10:05 PM PDT 24
Peak memory 212208 kb
Host smart-b2fe6b6c-e09d-42ab-a628-cf9fba4ee719
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375467446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.375467446
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.848864024
Short name T96
Test name
Test status
Simulation time 251485153 ps
CPU time 5.14 seconds
Started Jul 29 06:10:03 PM PDT 24
Finished Jul 29 06:10:08 PM PDT 24
Peak memory 211968 kb
Host smart-5cd03ce7-9f54-4377-ac70-4c2d2c0aeb69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848864024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.848864024
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1186493831
Short name T186
Test name
Test status
Simulation time 20231855571 ps
CPU time 174.58 seconds
Started Jul 29 06:09:58 PM PDT 24
Finished Jul 29 06:12:52 PM PDT 24
Peak memory 227460 kb
Host smart-7f18a6cd-2452-409b-942c-181c83c61079
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186493831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1186493831
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4069331840
Short name T24
Test name
Test status
Simulation time 697118938 ps
CPU time 9.35 seconds
Started Jul 29 06:10:02 PM PDT 24
Finished Jul 29 06:10:11 PM PDT 24
Peak memory 212908 kb
Host smart-1b24e91f-8cdb-4877-8ea3-661bb52fa7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069331840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.4069331840
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2164249021
Short name T220
Test name
Test status
Simulation time 272967810 ps
CPU time 6.4 seconds
Started Jul 29 06:09:58 PM PDT 24
Finished Jul 29 06:10:05 PM PDT 24
Peak memory 212176 kb
Host smart-567ba827-b467-49db-824e-9a081bb4dbd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2164249021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2164249021
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2412240470
Short name T75
Test name
Test status
Simulation time 906066209 ps
CPU time 13.28 seconds
Started Jul 29 06:09:59 PM PDT 24
Finished Jul 29 06:10:12 PM PDT 24
Peak memory 215164 kb
Host smart-11d42737-deed-4f61-bfc3-75c9504bf546
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412240470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2412240470
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.44425198
Short name T235
Test name
Test status
Simulation time 171985531 ps
CPU time 4.33 seconds
Started Jul 29 06:10:05 PM PDT 24
Finished Jul 29 06:10:09 PM PDT 24
Peak memory 212084 kb
Host smart-854f00d0-4a9d-449a-be2f-5c4c0eddfb00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44425198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.44425198
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1866877525
Short name T1
Test name
Test status
Simulation time 4209117516 ps
CPU time 212.04 seconds
Started Jul 29 06:10:02 PM PDT 24
Finished Jul 29 06:13:35 PM PDT 24
Peak memory 226188 kb
Host smart-d609258c-7249-425b-bb05-6dd971de441c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866877525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1866877525
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2683439705
Short name T149
Test name
Test status
Simulation time 1042959409 ps
CPU time 11.3 seconds
Started Jul 29 06:10:01 PM PDT 24
Finished Jul 29 06:10:13 PM PDT 24
Peak memory 212820 kb
Host smart-abd2d0dc-c2d3-48a5-872c-b4672c70b361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683439705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2683439705
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.4164478197
Short name T199
Test name
Test status
Simulation time 383876048 ps
CPU time 5.61 seconds
Started Jul 29 06:10:02 PM PDT 24
Finished Jul 29 06:10:08 PM PDT 24
Peak memory 212156 kb
Host smart-8835b989-a699-4e1d-ba6c-a4373992a705
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164478197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.4164478197
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.913083640
Short name T189
Test name
Test status
Simulation time 739940199 ps
CPU time 11.66 seconds
Started Jul 29 06:10:01 PM PDT 24
Finished Jul 29 06:10:13 PM PDT 24
Peak memory 214588 kb
Host smart-b9a31bec-aefa-4642-8f90-8aee175222d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913083640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.913083640
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3817205377
Short name T147
Test name
Test status
Simulation time 363091126 ps
CPU time 4.2 seconds
Started Jul 29 06:10:03 PM PDT 24
Finished Jul 29 06:10:07 PM PDT 24
Peak memory 212024 kb
Host smart-905a29fb-9e5b-4652-a9b8-a7536e8f2a5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817205377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3817205377
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1152557948
Short name T164
Test name
Test status
Simulation time 7554926228 ps
CPU time 84.98 seconds
Started Jul 29 06:10:01 PM PDT 24
Finished Jul 29 06:11:26 PM PDT 24
Peak memory 226416 kb
Host smart-7e87456d-d47f-453e-9092-00ab1602a0e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152557948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1152557948
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1410180915
Short name T231
Test name
Test status
Simulation time 692190558 ps
CPU time 9.49 seconds
Started Jul 29 06:10:02 PM PDT 24
Finished Jul 29 06:10:12 PM PDT 24
Peak memory 212976 kb
Host smart-a2e07c2f-48c8-4851-b353-42b9d60dbcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410180915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1410180915
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.597482558
Short name T289
Test name
Test status
Simulation time 97601089 ps
CPU time 5.72 seconds
Started Jul 29 06:10:03 PM PDT 24
Finished Jul 29 06:10:09 PM PDT 24
Peak memory 212092 kb
Host smart-b7c2675b-c1c1-47d2-b3a5-79becc96c19a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=597482558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.597482558
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3111741875
Short name T204
Test name
Test status
Simulation time 2154002314 ps
CPU time 21.74 seconds
Started Jul 29 06:10:03 PM PDT 24
Finished Jul 29 06:10:25 PM PDT 24
Peak memory 215580 kb
Host smart-e4a7cfe3-e3e3-4e42-bea3-953f062b8d15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111741875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3111741875
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.37317737
Short name T173
Test name
Test status
Simulation time 261763655 ps
CPU time 5.16 seconds
Started Jul 29 06:08:59 PM PDT 24
Finished Jul 29 06:09:04 PM PDT 24
Peak memory 212056 kb
Host smart-ad4633b5-b896-46f0-a015-b62adde9417c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37317737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.37317737
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.678257549
Short name T137
Test name
Test status
Simulation time 4471201986 ps
CPU time 112.02 seconds
Started Jul 29 06:08:58 PM PDT 24
Finished Jul 29 06:10:50 PM PDT 24
Peak memory 238472 kb
Host smart-e7cc84e1-a0f5-419d-a6a1-dcc4e56c88bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678257549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.678257549
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1638888620
Short name T244
Test name
Test status
Simulation time 171691485 ps
CPU time 9.57 seconds
Started Jul 29 06:08:59 PM PDT 24
Finished Jul 29 06:09:08 PM PDT 24
Peak memory 212884 kb
Host smart-94b6af5e-2676-47d7-819b-209edb38b819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638888620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1638888620
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1715648940
Short name T273
Test name
Test status
Simulation time 143687289 ps
CPU time 5.42 seconds
Started Jul 29 06:08:59 PM PDT 24
Finished Jul 29 06:09:05 PM PDT 24
Peak memory 212172 kb
Host smart-f7f6283d-c38d-4343-b963-55a45430e385
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1715648940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1715648940
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2179220835
Short name T228
Test name
Test status
Simulation time 376548176 ps
CPU time 5.56 seconds
Started Jul 29 06:08:53 PM PDT 24
Finished Jul 29 06:08:58 PM PDT 24
Peak memory 212168 kb
Host smart-16413532-ed21-4c7c-89d5-965cf8460f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179220835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2179220835
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3001161181
Short name T312
Test name
Test status
Simulation time 292404470 ps
CPU time 14.27 seconds
Started Jul 29 06:09:05 PM PDT 24
Finished Jul 29 06:09:19 PM PDT 24
Peak memory 215880 kb
Host smart-fcdd027d-9f44-4f3a-b702-9944826c513b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001161181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3001161181
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1709350927
Short name T47
Test name
Test status
Simulation time 44164816483 ps
CPU time 374.65 seconds
Started Jul 29 06:08:57 PM PDT 24
Finished Jul 29 06:15:12 PM PDT 24
Peak memory 234756 kb
Host smart-ac91e6ac-440d-44a6-bbcd-e402698ef15f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709350927 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.1709350927
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.78112157
Short name T226
Test name
Test status
Simulation time 207255310 ps
CPU time 4.21 seconds
Started Jul 29 06:08:58 PM PDT 24
Finished Jul 29 06:09:02 PM PDT 24
Peak memory 212040 kb
Host smart-8be2b013-e53a-4a96-ab56-c275ee9183c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78112157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.78112157
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.543401559
Short name T281
Test name
Test status
Simulation time 16551493380 ps
CPU time 53.76 seconds
Started Jul 29 06:09:04 PM PDT 24
Finished Jul 29 06:09:58 PM PDT 24
Peak memory 229276 kb
Host smart-cce985f4-3b60-462f-8406-456a5e63ca93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543401559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.543401559
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3116085548
Short name T178
Test name
Test status
Simulation time 282932254 ps
CPU time 10.66 seconds
Started Jul 29 06:08:56 PM PDT 24
Finished Jul 29 06:09:07 PM PDT 24
Peak memory 212828 kb
Host smart-244a2d0a-f88a-4838-b2f6-fb0ba6a124cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116085548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3116085548
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.156693680
Short name T222
Test name
Test status
Simulation time 523287193 ps
CPU time 6.24 seconds
Started Jul 29 06:08:58 PM PDT 24
Finished Jul 29 06:09:04 PM PDT 24
Peak memory 212064 kb
Host smart-f41b9d7c-3013-48b3-b7a5-fc45239620a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=156693680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.156693680
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.382879656
Short name T250
Test name
Test status
Simulation time 567550813 ps
CPU time 6.51 seconds
Started Jul 29 06:08:58 PM PDT 24
Finished Jul 29 06:09:05 PM PDT 24
Peak memory 212088 kb
Host smart-9ca5c77c-16d9-4626-bce4-07b9e68a7101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382879656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.382879656
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3353787460
Short name T79
Test name
Test status
Simulation time 189021051 ps
CPU time 12.07 seconds
Started Jul 29 06:08:57 PM PDT 24
Finished Jul 29 06:09:09 PM PDT 24
Peak memory 215240 kb
Host smart-d896f67d-3d43-44a4-a327-2641ac7b845d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353787460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3353787460
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3085369084
Short name T171
Test name
Test status
Simulation time 132840788 ps
CPU time 5.32 seconds
Started Jul 29 06:08:56 PM PDT 24
Finished Jul 29 06:09:01 PM PDT 24
Peak memory 212024 kb
Host smart-a313788a-c965-4d5c-8361-8f0159abe1a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085369084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3085369084
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1698498310
Short name T314
Test name
Test status
Simulation time 6788054047 ps
CPU time 90.59 seconds
Started Jul 29 06:08:58 PM PDT 24
Finished Jul 29 06:10:29 PM PDT 24
Peak memory 214464 kb
Host smart-75a12612-f3a8-457b-9c05-5a181e6e2e37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698498310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1698498310
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2625259669
Short name T156
Test name
Test status
Simulation time 251492235 ps
CPU time 11.1 seconds
Started Jul 29 06:08:58 PM PDT 24
Finished Jul 29 06:09:09 PM PDT 24
Peak memory 212176 kb
Host smart-b7ed407e-a828-4b56-bf53-d11a116aa58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625259669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2625259669
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.73309828
Short name T253
Test name
Test status
Simulation time 339656809 ps
CPU time 6.05 seconds
Started Jul 29 06:09:04 PM PDT 24
Finished Jul 29 06:09:10 PM PDT 24
Peak memory 212172 kb
Host smart-1c1f2009-4b41-4396-acdf-e596d369cc63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=73309828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.73309828
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1855310245
Short name T196
Test name
Test status
Simulation time 101199025 ps
CPU time 5.86 seconds
Started Jul 29 06:09:06 PM PDT 24
Finished Jul 29 06:09:12 PM PDT 24
Peak memory 212172 kb
Host smart-31df4446-e690-4c99-a732-66cb40b3ae72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855310245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1855310245
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3658789246
Short name T319
Test name
Test status
Simulation time 383028928 ps
CPU time 10.51 seconds
Started Jul 29 06:08:57 PM PDT 24
Finished Jul 29 06:09:08 PM PDT 24
Peak memory 215992 kb
Host smart-f8800b2d-2b48-4574-829b-51201784c2df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658789246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3658789246
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3192085282
Short name T46
Test name
Test status
Simulation time 148264497685 ps
CPU time 2824.07 seconds
Started Jul 29 06:08:58 PM PDT 24
Finished Jul 29 06:56:03 PM PDT 24
Peak memory 241660 kb
Host smart-6321aa36-e2d5-4678-a9ed-b6fb60b9c6af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192085282 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3192085282
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4144761452
Short name T59
Test name
Test status
Simulation time 85729144 ps
CPU time 4.28 seconds
Started Jul 29 06:09:05 PM PDT 24
Finished Jul 29 06:09:09 PM PDT 24
Peak memory 212060 kb
Host smart-87b9adb8-8732-493a-96ed-6bfce2ac1330
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144761452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4144761452
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2485026338
Short name T232
Test name
Test status
Simulation time 5983870630 ps
CPU time 148.75 seconds
Started Jul 29 06:08:58 PM PDT 24
Finished Jul 29 06:11:27 PM PDT 24
Peak memory 213880 kb
Host smart-ff13aa24-fc4e-43eb-bd18-8dd9345bd5e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485026338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2485026338
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2374727937
Short name T217
Test name
Test status
Simulation time 2393165669 ps
CPU time 9.51 seconds
Started Jul 29 06:09:07 PM PDT 24
Finished Jul 29 06:09:17 PM PDT 24
Peak memory 213208 kb
Host smart-199c1e85-246d-40e9-a8a1-b67d20d44115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374727937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2374727937
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.21099226
Short name T31
Test name
Test status
Simulation time 363193686 ps
CPU time 5.19 seconds
Started Jul 29 06:09:04 PM PDT 24
Finished Jul 29 06:09:09 PM PDT 24
Peak memory 212172 kb
Host smart-84488678-1d8c-47b2-adce-df8c6b68686b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21099226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.21099226
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3904047689
Short name T136
Test name
Test status
Simulation time 138026097 ps
CPU time 6.51 seconds
Started Jul 29 06:08:58 PM PDT 24
Finished Jul 29 06:09:05 PM PDT 24
Peak memory 212168 kb
Host smart-e5d27960-4a87-466c-ae24-1a71008be8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904047689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3904047689
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1521575693
Short name T318
Test name
Test status
Simulation time 1134264796 ps
CPU time 15.21 seconds
Started Jul 29 06:08:59 PM PDT 24
Finished Jul 29 06:09:15 PM PDT 24
Peak memory 215472 kb
Host smart-087d5d3b-8b22-4bf5-a147-e140eb92cd88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521575693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1521575693
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2189554532
Short name T144
Test name
Test status
Simulation time 85983810 ps
CPU time 4.3 seconds
Started Jul 29 06:09:07 PM PDT 24
Finished Jul 29 06:09:11 PM PDT 24
Peak memory 212000 kb
Host smart-a7276276-e46c-4330-a8c1-bd151c625c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189554532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2189554532
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3998103145
Short name T254
Test name
Test status
Simulation time 2225705750 ps
CPU time 101.32 seconds
Started Jul 29 06:09:02 PM PDT 24
Finished Jul 29 06:10:44 PM PDT 24
Peak memory 213440 kb
Host smart-41cd0d6e-8939-4859-b151-6d83a08d7f51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998103145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3998103145
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2810211135
Short name T30
Test name
Test status
Simulation time 1566843239 ps
CPU time 11.84 seconds
Started Jul 29 06:09:03 PM PDT 24
Finished Jul 29 06:09:14 PM PDT 24
Peak memory 216668 kb
Host smart-1c899524-c2bc-4eb9-9ee7-6c933ba26c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810211135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2810211135
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4264903477
Short name T133
Test name
Test status
Simulation time 567080188 ps
CPU time 6.71 seconds
Started Jul 29 06:09:05 PM PDT 24
Finished Jul 29 06:09:12 PM PDT 24
Peak memory 212196 kb
Host smart-24c4ff53-fb5c-4043-b751-3601e0e00f24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4264903477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4264903477
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2371313301
Short name T195
Test name
Test status
Simulation time 141925005 ps
CPU time 6.52 seconds
Started Jul 29 06:09:04 PM PDT 24
Finished Jul 29 06:09:11 PM PDT 24
Peak memory 212132 kb
Host smart-3710522a-1a0f-4672-8df8-749747d61898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371313301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2371313301
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.831040406
Short name T73
Test name
Test status
Simulation time 369266824 ps
CPU time 11.45 seconds
Started Jul 29 06:09:03 PM PDT 24
Finished Jul 29 06:09:15 PM PDT 24
Peak memory 213252 kb
Host smart-1db29f50-1b84-4bf4-82ad-fbd97430dd19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831040406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.831040406
Directory /workspace/9.rom_ctrl_stress_all/latest
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