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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.28 96.89 92.13 97.67 100.00 98.62 97.30 98.37


Total test records in report: 416
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T294 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.151852056 Jul 31 05:34:25 PM PDT 24 Jul 31 05:34:30 PM PDT 24 99568858 ps
T295 /workspace/coverage/default/26.rom_ctrl_alert_test.1577175486 Jul 31 05:34:39 PM PDT 24 Jul 31 05:34:43 PM PDT 24 88909487 ps
T296 /workspace/coverage/default/29.rom_ctrl_alert_test.1008522944 Jul 31 05:34:45 PM PDT 24 Jul 31 05:34:49 PM PDT 24 90043582 ps
T297 /workspace/coverage/default/20.rom_ctrl_alert_test.4234398379 Jul 31 05:34:36 PM PDT 24 Jul 31 05:34:40 PM PDT 24 334826193 ps
T298 /workspace/coverage/default/1.rom_ctrl_alert_test.3009732515 Jul 31 05:34:10 PM PDT 24 Jul 31 05:34:15 PM PDT 24 285974685 ps
T299 /workspace/coverage/default/12.rom_ctrl_stress_all.792954921 Jul 31 05:34:29 PM PDT 24 Jul 31 05:34:44 PM PDT 24 3738578309 ps
T300 /workspace/coverage/default/1.rom_ctrl_smoke.740300319 Jul 31 05:34:08 PM PDT 24 Jul 31 05:34:14 PM PDT 24 413156857 ps
T301 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.49936376 Jul 31 05:34:19 PM PDT 24 Jul 31 05:34:25 PM PDT 24 414011746 ps
T302 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.478262533 Jul 31 05:35:00 PM PDT 24 Jul 31 05:35:06 PM PDT 24 1159467934 ps
T303 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2220683837 Jul 31 05:34:40 PM PDT 24 Jul 31 05:36:51 PM PDT 24 13779963912 ps
T304 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.608335320 Jul 31 05:34:42 PM PDT 24 Jul 31 05:34:54 PM PDT 24 999482317 ps
T305 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3530550715 Jul 31 05:34:19 PM PDT 24 Jul 31 05:34:31 PM PDT 24 1132584243 ps
T306 /workspace/coverage/default/13.rom_ctrl_stress_all.2894509158 Jul 31 05:34:24 PM PDT 24 Jul 31 05:34:42 PM PDT 24 440557985 ps
T307 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.4139068238 Jul 31 05:34:39 PM PDT 24 Jul 31 05:34:51 PM PDT 24 520862687 ps
T308 /workspace/coverage/default/36.rom_ctrl_alert_test.3390119444 Jul 31 05:34:50 PM PDT 24 Jul 31 05:34:55 PM PDT 24 499461065 ps
T309 /workspace/coverage/default/0.rom_ctrl_alert_test.754903790 Jul 31 05:34:14 PM PDT 24 Jul 31 05:34:18 PM PDT 24 932104999 ps
T310 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2690396672 Jul 31 05:34:14 PM PDT 24 Jul 31 05:34:20 PM PDT 24 191422157 ps
T311 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2453356112 Jul 31 05:34:52 PM PDT 24 Jul 31 05:34:58 PM PDT 24 269846622 ps
T312 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2050327531 Jul 31 05:34:40 PM PDT 24 Jul 31 05:34:45 PM PDT 24 361305058 ps
T48 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1264758001 Jul 31 05:35:13 PM PDT 24 Jul 31 05:35:24 PM PDT 24 1130005750 ps
T313 /workspace/coverage/default/22.rom_ctrl_stress_all.1791574421 Jul 31 05:34:45 PM PDT 24 Jul 31 05:34:53 PM PDT 24 251120461 ps
T314 /workspace/coverage/default/4.rom_ctrl_smoke.1621969787 Jul 31 05:34:15 PM PDT 24 Jul 31 05:34:21 PM PDT 24 825793876 ps
T315 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3804644176 Jul 31 05:34:45 PM PDT 24 Jul 31 05:34:55 PM PDT 24 2081083868 ps
T316 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4084967899 Jul 31 05:34:50 PM PDT 24 Jul 31 05:35:51 PM PDT 24 1097723230 ps
T317 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1717517710 Jul 31 05:34:09 PM PDT 24 Jul 31 05:36:29 PM PDT 24 28172664753 ps
T318 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2222408971 Jul 31 05:34:10 PM PDT 24 Jul 31 05:36:08 PM PDT 24 5186959585 ps
T319 /workspace/coverage/default/45.rom_ctrl_stress_all.3489703104 Jul 31 05:35:10 PM PDT 24 Jul 31 05:35:24 PM PDT 24 2552982161 ps
T320 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3807853186 Jul 31 05:34:28 PM PDT 24 Jul 31 05:36:25 PM PDT 24 6252610935 ps
T321 /workspace/coverage/default/40.rom_ctrl_stress_all.1223251368 Jul 31 05:34:56 PM PDT 24 Jul 31 05:35:14 PM PDT 24 2654270370 ps
T322 /workspace/coverage/default/41.rom_ctrl_stress_all.1512247486 Jul 31 05:35:02 PM PDT 24 Jul 31 05:35:10 PM PDT 24 132979773 ps
T323 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.865626742 Jul 31 05:34:58 PM PDT 24 Jul 31 05:36:58 PM PDT 24 1863863498 ps
T324 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.601772001 Jul 31 05:35:01 PM PDT 24 Jul 31 05:35:10 PM PDT 24 760423916 ps
T325 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.262637073 Jul 31 05:34:38 PM PDT 24 Jul 31 06:19:08 PM PDT 24 128584847573 ps
T326 /workspace/coverage/default/19.rom_ctrl_alert_test.1918704991 Jul 31 05:34:38 PM PDT 24 Jul 31 05:34:43 PM PDT 24 518604568 ps
T327 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3494361331 Jul 31 05:35:12 PM PDT 24 Jul 31 05:35:18 PM PDT 24 833072437 ps
T328 /workspace/coverage/default/24.rom_ctrl_stress_all.3333273014 Jul 31 05:34:41 PM PDT 24 Jul 31 05:34:54 PM PDT 24 825996266 ps
T329 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1430794663 Jul 31 05:35:17 PM PDT 24 Jul 31 05:36:18 PM PDT 24 4104476698 ps
T54 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3923235902 Jul 31 05:12:38 PM PDT 24 Jul 31 05:13:47 PM PDT 24 425243806 ps
T57 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3158246123 Jul 31 05:12:45 PM PDT 24 Jul 31 05:12:50 PM PDT 24 132332815 ps
T58 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2594739063 Jul 31 05:12:37 PM PDT 24 Jul 31 05:12:43 PM PDT 24 497936183 ps
T330 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3164899818 Jul 31 05:12:16 PM PDT 24 Jul 31 05:12:21 PM PDT 24 246391605 ps
T66 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2081624485 Jul 31 05:12:35 PM PDT 24 Jul 31 05:12:44 PM PDT 24 298287177 ps
T331 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4204043352 Jul 31 05:12:29 PM PDT 24 Jul 31 05:12:34 PM PDT 24 521194397 ps
T332 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2979890262 Jul 31 05:12:39 PM PDT 24 Jul 31 05:12:47 PM PDT 24 520652491 ps
T67 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3007505406 Jul 31 05:12:21 PM PDT 24 Jul 31 05:12:25 PM PDT 24 335049111 ps
T55 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1095028842 Jul 31 05:12:37 PM PDT 24 Jul 31 05:13:46 PM PDT 24 2516439498 ps
T333 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2441667099 Jul 31 05:12:25 PM PDT 24 Jul 31 05:12:30 PM PDT 24 602330816 ps
T56 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3292405651 Jul 31 05:12:15 PM PDT 24 Jul 31 05:13:27 PM PDT 24 357497222 ps
T334 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3282560223 Jul 31 05:12:20 PM PDT 24 Jul 31 05:12:26 PM PDT 24 263189929 ps
T68 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1295099996 Jul 31 05:12:21 PM PDT 24 Jul 31 05:12:27 PM PDT 24 734219456 ps
T97 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2304082497 Jul 31 05:12:16 PM PDT 24 Jul 31 05:12:26 PM PDT 24 519923397 ps
T335 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.281714337 Jul 31 05:12:11 PM PDT 24 Jul 31 05:12:18 PM PDT 24 132736443 ps
T336 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1805771857 Jul 31 05:12:38 PM PDT 24 Jul 31 05:12:44 PM PDT 24 532748888 ps
T110 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2878135288 Jul 31 05:12:19 PM PDT 24 Jul 31 05:12:57 PM PDT 24 196925077 ps
T69 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4255925951 Jul 31 05:12:29 PM PDT 24 Jul 31 05:12:47 PM PDT 24 359917377 ps
T337 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3757211921 Jul 31 05:12:48 PM PDT 24 Jul 31 05:12:55 PM PDT 24 261080107 ps
T108 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2918900467 Jul 31 05:12:29 PM PDT 24 Jul 31 05:13:41 PM PDT 24 313160893 ps
T338 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.441994423 Jul 31 05:12:32 PM PDT 24 Jul 31 05:12:41 PM PDT 24 299429866 ps
T339 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4229020266 Jul 31 05:12:33 PM PDT 24 Jul 31 05:13:43 PM PDT 24 419010508 ps
T70 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2991852626 Jul 31 05:12:30 PM PDT 24 Jul 31 05:12:35 PM PDT 24 86148595 ps
T340 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1471678316 Jul 31 05:12:28 PM PDT 24 Jul 31 05:12:33 PM PDT 24 561413000 ps
T341 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1597026792 Jul 31 05:12:30 PM PDT 24 Jul 31 05:12:36 PM PDT 24 101558224 ps
T98 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1812834980 Jul 31 05:12:32 PM PDT 24 Jul 31 05:12:37 PM PDT 24 130411110 ps
T109 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4134814357 Jul 31 05:12:28 PM PDT 24 Jul 31 05:13:41 PM PDT 24 1603351775 ps
T94 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.872437064 Jul 31 05:12:16 PM PDT 24 Jul 31 05:12:20 PM PDT 24 346740637 ps
T95 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.726119288 Jul 31 05:12:15 PM PDT 24 Jul 31 05:12:22 PM PDT 24 455033900 ps
T96 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1927989972 Jul 31 05:12:24 PM PDT 24 Jul 31 05:12:28 PM PDT 24 89834978 ps
T71 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3930661192 Jul 31 05:12:39 PM PDT 24 Jul 31 05:12:43 PM PDT 24 175682297 ps
T342 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.382691529 Jul 31 05:12:41 PM PDT 24 Jul 31 05:12:49 PM PDT 24 173196969 ps
T72 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2307718253 Jul 31 05:12:25 PM PDT 24 Jul 31 05:12:31 PM PDT 24 779224763 ps
T73 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2378518203 Jul 31 05:12:25 PM PDT 24 Jul 31 05:12:30 PM PDT 24 261892143 ps
T74 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3426514994 Jul 31 05:12:58 PM PDT 24 Jul 31 05:13:03 PM PDT 24 134642794 ps
T343 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3529152658 Jul 31 05:12:26 PM PDT 24 Jul 31 05:12:36 PM PDT 24 135472973 ps
T344 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2701461381 Jul 31 05:12:38 PM PDT 24 Jul 31 05:12:42 PM PDT 24 86090683 ps
T345 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.236332232 Jul 31 05:12:56 PM PDT 24 Jul 31 05:13:03 PM PDT 24 554660909 ps
T346 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3900908023 Jul 31 05:12:38 PM PDT 24 Jul 31 05:12:43 PM PDT 24 256619591 ps
T83 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.446721377 Jul 31 05:12:26 PM PDT 24 Jul 31 05:12:32 PM PDT 24 132392405 ps
T347 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2743889796 Jul 31 05:12:29 PM PDT 24 Jul 31 05:12:34 PM PDT 24 523568368 ps
T111 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2671825606 Jul 31 05:12:37 PM PDT 24 Jul 31 05:13:45 PM PDT 24 874157237 ps
T348 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1987084119 Jul 31 05:12:19 PM PDT 24 Jul 31 05:12:24 PM PDT 24 262106076 ps
T349 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2705934081 Jul 31 05:12:35 PM PDT 24 Jul 31 05:12:40 PM PDT 24 396386252 ps
T350 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1502899652 Jul 31 05:12:37 PM PDT 24 Jul 31 05:12:46 PM PDT 24 132148165 ps
T351 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2219707181 Jul 31 05:12:22 PM PDT 24 Jul 31 05:12:31 PM PDT 24 501016780 ps
T84 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3725987338 Jul 31 05:12:42 PM PDT 24 Jul 31 05:13:01 PM PDT 24 2787565724 ps
T85 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1955216886 Jul 31 05:12:38 PM PDT 24 Jul 31 05:12:57 PM PDT 24 2402278733 ps
T352 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.731733987 Jul 31 05:12:34 PM PDT 24 Jul 31 05:12:39 PM PDT 24 96156215 ps
T353 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2801639198 Jul 31 05:12:38 PM PDT 24 Jul 31 05:12:44 PM PDT 24 1107235596 ps
T354 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2875882625 Jul 31 05:12:34 PM PDT 24 Jul 31 05:12:43 PM PDT 24 253276794 ps
T104 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3953187972 Jul 31 05:12:21 PM PDT 24 Jul 31 05:13:28 PM PDT 24 424684668 ps
T355 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4001912962 Jul 31 05:12:13 PM PDT 24 Jul 31 05:12:20 PM PDT 24 132737440 ps
T105 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.70268206 Jul 31 05:12:37 PM PDT 24 Jul 31 05:13:45 PM PDT 24 860262822 ps
T356 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3070583388 Jul 31 05:12:37 PM PDT 24 Jul 31 05:12:41 PM PDT 24 308549729 ps
T357 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.116119445 Jul 31 05:12:41 PM PDT 24 Jul 31 05:12:46 PM PDT 24 401041106 ps
T358 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.105939204 Jul 31 05:12:37 PM PDT 24 Jul 31 05:12:45 PM PDT 24 126099725 ps
T359 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.801050152 Jul 31 05:12:33 PM PDT 24 Jul 31 05:12:39 PM PDT 24 250880801 ps
T86 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4218073243 Jul 31 05:12:46 PM PDT 24 Jul 31 05:12:51 PM PDT 24 500527247 ps
T360 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3651908695 Jul 31 05:12:33 PM PDT 24 Jul 31 05:12:40 PM PDT 24 1768787036 ps
T87 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1908026641 Jul 31 05:12:28 PM PDT 24 Jul 31 05:12:33 PM PDT 24 255030144 ps
T361 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.416177585 Jul 31 05:12:25 PM PDT 24 Jul 31 05:12:30 PM PDT 24 273164404 ps
T362 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1737171793 Jul 31 05:12:31 PM PDT 24 Jul 31 05:12:35 PM PDT 24 101512388 ps
T363 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4030667204 Jul 31 05:12:17 PM PDT 24 Jul 31 05:12:26 PM PDT 24 287660869 ps
T106 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1119593202 Jul 31 05:12:52 PM PDT 24 Jul 31 05:14:07 PM PDT 24 335687340 ps
T364 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.913987737 Jul 31 05:12:40 PM PDT 24 Jul 31 05:12:47 PM PDT 24 363961184 ps
T88 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4251162825 Jul 31 05:12:30 PM PDT 24 Jul 31 05:12:35 PM PDT 24 133047929 ps
T365 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1679839740 Jul 31 05:12:50 PM PDT 24 Jul 31 05:12:54 PM PDT 24 350472680 ps
T102 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1984552505 Jul 31 05:12:36 PM PDT 24 Jul 31 05:13:42 PM PDT 24 885101860 ps
T366 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3756936799 Jul 31 05:12:23 PM PDT 24 Jul 31 05:12:28 PM PDT 24 146340608 ps
T367 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3576219848 Jul 31 05:12:42 PM PDT 24 Jul 31 05:12:49 PM PDT 24 348029437 ps
T368 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4107687008 Jul 31 05:12:50 PM PDT 24 Jul 31 05:12:58 PM PDT 24 1019455888 ps
T369 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2881694781 Jul 31 05:12:22 PM PDT 24 Jul 31 05:12:26 PM PDT 24 355087007 ps
T370 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3490967468 Jul 31 05:12:17 PM PDT 24 Jul 31 05:12:24 PM PDT 24 138800384 ps
T371 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4071178044 Jul 31 05:12:26 PM PDT 24 Jul 31 05:13:03 PM PDT 24 159802820 ps
T372 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1380376091 Jul 31 05:12:31 PM PDT 24 Jul 31 05:12:36 PM PDT 24 828974792 ps
T373 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2693114025 Jul 31 05:12:29 PM PDT 24 Jul 31 05:12:34 PM PDT 24 130912564 ps
T113 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.25948978 Jul 31 05:12:40 PM PDT 24 Jul 31 05:13:18 PM PDT 24 1179886431 ps
T374 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1816472503 Jul 31 05:12:32 PM PDT 24 Jul 31 05:12:37 PM PDT 24 361221936 ps
T375 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2470929828 Jul 31 05:12:09 PM PDT 24 Jul 31 05:12:18 PM PDT 24 260562230 ps
T376 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2687747739 Jul 31 05:12:33 PM PDT 24 Jul 31 05:12:37 PM PDT 24 85867191 ps
T89 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3056570458 Jul 31 05:12:24 PM PDT 24 Jul 31 05:12:29 PM PDT 24 257048236 ps
T377 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2105609751 Jul 31 05:12:23 PM PDT 24 Jul 31 05:12:28 PM PDT 24 346366847 ps
T378 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1748183799 Jul 31 05:12:20 PM PDT 24 Jul 31 05:12:24 PM PDT 24 350656183 ps
T379 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.749446263 Jul 31 05:12:11 PM PDT 24 Jul 31 05:12:16 PM PDT 24 86081881 ps
T380 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2687630214 Jul 31 05:12:05 PM PDT 24 Jul 31 05:12:13 PM PDT 24 167130098 ps
T381 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.90952742 Jul 31 05:12:21 PM PDT 24 Jul 31 05:12:26 PM PDT 24 100587284 ps
T382 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2677168186 Jul 31 05:12:14 PM PDT 24 Jul 31 05:12:18 PM PDT 24 175306566 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2751159882 Jul 31 05:12:33 PM PDT 24 Jul 31 05:12:38 PM PDT 24 333788900 ps
T384 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1649716399 Jul 31 05:12:22 PM PDT 24 Jul 31 05:12:41 PM PDT 24 388098378 ps
T385 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3616505629 Jul 31 05:12:28 PM PDT 24 Jul 31 05:13:36 PM PDT 24 772761654 ps
T386 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1127159132 Jul 31 05:12:30 PM PDT 24 Jul 31 05:12:38 PM PDT 24 1762664557 ps
T387 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.773060838 Jul 31 05:12:12 PM PDT 24 Jul 31 05:12:17 PM PDT 24 132664785 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2734872643 Jul 31 05:12:20 PM PDT 24 Jul 31 05:12:26 PM PDT 24 130435308 ps
T389 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3572664049 Jul 31 05:12:30 PM PDT 24 Jul 31 05:12:36 PM PDT 24 599327591 ps
T390 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2519159051 Jul 31 05:12:40 PM PDT 24 Jul 31 05:12:46 PM PDT 24 252165087 ps
T391 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1614732643 Jul 31 05:12:15 PM PDT 24 Jul 31 05:12:20 PM PDT 24 88991164 ps
T392 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2674068458 Jul 31 05:12:31 PM PDT 24 Jul 31 05:12:40 PM PDT 24 535352544 ps
T393 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2109002263 Jul 31 05:12:29 PM PDT 24 Jul 31 05:12:35 PM PDT 24 140872042 ps
T394 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2876230701 Jul 31 05:12:13 PM PDT 24 Jul 31 05:12:18 PM PDT 24 249616776 ps
T112 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.593177044 Jul 31 05:12:57 PM PDT 24 Jul 31 05:14:07 PM PDT 24 359109184 ps
T395 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3723354566 Jul 31 05:12:38 PM PDT 24 Jul 31 05:12:43 PM PDT 24 135562773 ps
T103 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1080355461 Jul 31 05:12:23 PM PDT 24 Jul 31 05:13:00 PM PDT 24 161855224 ps
T396 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.205139935 Jul 31 05:12:40 PM PDT 24 Jul 31 05:12:45 PM PDT 24 161620308 ps
T397 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.887629708 Jul 31 05:12:20 PM PDT 24 Jul 31 05:12:25 PM PDT 24 140071634 ps
T398 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1165509919 Jul 31 05:12:40 PM PDT 24 Jul 31 05:12:44 PM PDT 24 333003869 ps
T90 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1017560371 Jul 31 05:12:13 PM PDT 24 Jul 31 05:12:19 PM PDT 24 421850181 ps
T399 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4022329805 Jul 31 05:12:26 PM PDT 24 Jul 31 05:12:30 PM PDT 24 88685431 ps
T400 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1531156087 Jul 31 05:12:26 PM PDT 24 Jul 31 05:12:30 PM PDT 24 381081391 ps
T401 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2571202261 Jul 31 05:12:24 PM PDT 24 Jul 31 05:12:34 PM PDT 24 294587008 ps
T107 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3282126528 Jul 31 05:12:13 PM PDT 24 Jul 31 05:13:22 PM PDT 24 241696497 ps
T402 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2091470995 Jul 31 05:12:39 PM PDT 24 Jul 31 05:12:48 PM PDT 24 186727416 ps
T403 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.937936219 Jul 31 05:12:29 PM PDT 24 Jul 31 05:12:39 PM PDT 24 154325815 ps
T404 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3420274116 Jul 31 05:12:21 PM PDT 24 Jul 31 05:12:27 PM PDT 24 522202438 ps
T91 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1673132812 Jul 31 05:12:38 PM PDT 24 Jul 31 05:12:42 PM PDT 24 209237656 ps
T92 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1436865802 Jul 31 05:12:26 PM PDT 24 Jul 31 05:12:34 PM PDT 24 516023867 ps
T405 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2323513687 Jul 31 05:12:16 PM PDT 24 Jul 31 05:12:21 PM PDT 24 193535767 ps
T93 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1592394747 Jul 31 05:12:21 PM PDT 24 Jul 31 05:12:32 PM PDT 24 126822705 ps
T406 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2110672050 Jul 31 05:12:16 PM PDT 24 Jul 31 05:12:22 PM PDT 24 569717299 ps
T407 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3229953513 Jul 31 05:12:28 PM PDT 24 Jul 31 05:12:33 PM PDT 24 521913344 ps
T408 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.198703949 Jul 31 05:12:35 PM PDT 24 Jul 31 05:12:40 PM PDT 24 177693770 ps
T409 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3353246732 Jul 31 05:12:14 PM PDT 24 Jul 31 05:12:20 PM PDT 24 284361646 ps
T410 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3360995524 Jul 31 05:12:35 PM PDT 24 Jul 31 05:12:42 PM PDT 24 1184427120 ps
T411 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.681665684 Jul 31 05:12:15 PM PDT 24 Jul 31 05:12:23 PM PDT 24 91059010 ps
T412 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4137542194 Jul 31 05:12:47 PM PDT 24 Jul 31 05:13:58 PM PDT 24 702007540 ps
T413 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3946007667 Jul 31 05:12:12 PM PDT 24 Jul 31 05:12:17 PM PDT 24 350408132 ps
T414 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4281597255 Jul 31 05:12:37 PM PDT 24 Jul 31 05:13:14 PM PDT 24 2988044401 ps
T415 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1279434649 Jul 31 05:12:12 PM PDT 24 Jul 31 05:12:17 PM PDT 24 134380871 ps
T416 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2128016197 Jul 31 05:12:11 PM PDT 24 Jul 31 05:12:15 PM PDT 24 461595864 ps

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1619129888
Short name T3
Test name
Test status
Simulation time 18543507989 ps
CPU time 7765.74 seconds
Started Jul 31 05:34:30 PM PDT 24
Finished Jul 31 07:43:57 PM PDT 24
Peak memory 235564 kb
Host smart-0ebd2361-f4ce-4ef2-95b1-7c211a79c317
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619129888 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.1619129888
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3241993545
Short name T10
Test name
Test status
Simulation time 2327113005 ps
CPU time 103.93 seconds
Started Jul 31 05:34:30 PM PDT 24
Finished Jul 31 05:36:14 PM PDT 24
Peak memory 213872 kb
Host smart-e9569a4e-4959-4d66-b951-25dce1846e0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241993545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3241993545
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.276154030
Short name T37
Test name
Test status
Simulation time 2572287360 ps
CPU time 130.41 seconds
Started Jul 31 05:34:30 PM PDT 24
Finished Jul 31 05:36:40 PM PDT 24
Peak memory 237400 kb
Host smart-cfba01a1-29cc-4740-86c0-e2a97c0d2d0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276154030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.276154030
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3923235902
Short name T54
Test name
Test status
Simulation time 425243806 ps
CPU time 68.46 seconds
Started Jul 31 05:12:38 PM PDT 24
Finished Jul 31 05:13:47 PM PDT 24
Peak memory 213196 kb
Host smart-b38aefb8-9369-472a-903c-fdaa50286027
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923235902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3923235902
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2238347469
Short name T23
Test name
Test status
Simulation time 368288506 ps
CPU time 53.16 seconds
Started Jul 31 05:34:08 PM PDT 24
Finished Jul 31 05:35:01 PM PDT 24
Peak memory 237360 kb
Host smart-0783b38e-c3bf-4b28-b53b-220cf0aed3c0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238347469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2238347469
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4255925951
Short name T69
Test name
Test status
Simulation time 359917377 ps
CPU time 18.62 seconds
Started Jul 31 05:12:29 PM PDT 24
Finished Jul 31 05:12:47 PM PDT 24
Peak memory 211464 kb
Host smart-5f897301-7504-4ee1-8a5a-bce519a49706
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255925951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.4255925951
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2124822074
Short name T45
Test name
Test status
Simulation time 497356565 ps
CPU time 5.18 seconds
Started Jul 31 05:34:28 PM PDT 24
Finished Jul 31 05:34:33 PM PDT 24
Peak memory 212072 kb
Host smart-24f24e4b-23ef-41fb-94f4-79dc98cd820d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124822074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2124822074
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1161023377
Short name T27
Test name
Test status
Simulation time 64839546781 ps
CPU time 1432.05 seconds
Started Jul 31 05:34:31 PM PDT 24
Finished Jul 31 05:58:23 PM PDT 24
Peak memory 236672 kb
Host smart-be9e3942-e7b6-4b7b-8b7f-fb3845217b5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161023377 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1161023377
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.4020253864
Short name T133
Test name
Test status
Simulation time 1007528884 ps
CPU time 16.82 seconds
Started Jul 31 05:34:34 PM PDT 24
Finished Jul 31 05:34:51 PM PDT 24
Peak memory 212928 kb
Host smart-01b6dcf8-03de-4b13-ab1b-dbabfd90f636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020253864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.4020253864
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.593177044
Short name T112
Test name
Test status
Simulation time 359109184 ps
CPU time 70.59 seconds
Started Jul 31 05:12:57 PM PDT 24
Finished Jul 31 05:14:07 PM PDT 24
Peak memory 212128 kb
Host smart-79fb4845-f6dc-4c0f-8909-08d0492231ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593177044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.593177044
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1364472441
Short name T62
Test name
Test status
Simulation time 590480083 ps
CPU time 14.78 seconds
Started Jul 31 05:34:29 PM PDT 24
Finished Jul 31 05:34:44 PM PDT 24
Peak memory 213756 kb
Host smart-89d7c7b3-9fc0-4f67-b700-2bd5ede320a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364472441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1364472441
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1974682330
Short name T8
Test name
Test status
Simulation time 665679769 ps
CPU time 9.52 seconds
Started Jul 31 05:35:10 PM PDT 24
Finished Jul 31 05:35:20 PM PDT 24
Peak memory 212968 kb
Host smart-285977fc-fc9a-4296-8b5d-29e3fa0c9d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974682330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1974682330
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1264758001
Short name T48
Test name
Test status
Simulation time 1130005750 ps
CPU time 11.03 seconds
Started Jul 31 05:35:13 PM PDT 24
Finished Jul 31 05:35:24 PM PDT 24
Peak memory 213496 kb
Host smart-7ff30813-7b9a-445a-bec9-0148b9956538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264758001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1264758001
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3282126528
Short name T107
Test name
Test status
Simulation time 241696497 ps
CPU time 68.72 seconds
Started Jul 31 05:12:13 PM PDT 24
Finished Jul 31 05:13:22 PM PDT 24
Peak memory 212896 kb
Host smart-a4c57c69-dbe3-42da-8e97-988a01adf253
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282126528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3282126528
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1984552505
Short name T102
Test name
Test status
Simulation time 885101860 ps
CPU time 66.38 seconds
Started Jul 31 05:12:36 PM PDT 24
Finished Jul 31 05:13:42 PM PDT 24
Peak memory 219496 kb
Host smart-2dcbf1e7-a25c-4223-b096-44d1fe965551
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984552505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1984552505
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.172387068
Short name T100
Test name
Test status
Simulation time 27390960622 ps
CPU time 556.18 seconds
Started Jul 31 05:34:09 PM PDT 24
Finished Jul 31 05:43:26 PM PDT 24
Peak memory 236684 kb
Host smart-c73117a1-12ac-438f-abd2-c447d6e988e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172387068 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.172387068
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.4097527482
Short name T13
Test name
Test status
Simulation time 64070378417 ps
CPU time 566.13 seconds
Started Jul 31 05:34:45 PM PDT 24
Finished Jul 31 05:44:11 PM PDT 24
Peak memory 229636 kb
Host smart-437ab304-f1f8-41b6-a05d-6f39113af986
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097527482 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.4097527482
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1049781107
Short name T52
Test name
Test status
Simulation time 30642226415 ps
CPU time 1120.57 seconds
Started Jul 31 05:34:32 PM PDT 24
Finished Jul 31 05:53:13 PM PDT 24
Peak memory 236612 kb
Host smart-bca89649-3d6a-42b4-a84e-3f029427eb71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049781107 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1049781107
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2378518203
Short name T73
Test name
Test status
Simulation time 261892143 ps
CPU time 5.09 seconds
Started Jul 31 05:12:25 PM PDT 24
Finished Jul 31 05:12:30 PM PDT 24
Peak memory 218096 kb
Host smart-5c55fe48-5b80-41c3-ae2c-af7d28a6b821
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378518203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2378518203
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3420274116
Short name T404
Test name
Test status
Simulation time 522202438 ps
CPU time 5.35 seconds
Started Jul 31 05:12:21 PM PDT 24
Finished Jul 31 05:12:27 PM PDT 24
Peak memory 211340 kb
Host smart-73c4f8d0-1326-4fdb-8fd6-6aaf1c436bd9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420274116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3420274116
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2304082497
Short name T97
Test name
Test status
Simulation time 519923397 ps
CPU time 10.66 seconds
Started Jul 31 05:12:16 PM PDT 24
Finished Jul 31 05:12:26 PM PDT 24
Peak memory 219028 kb
Host smart-8b170676-2cfa-40a2-ac78-b430fdf69aba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304082497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2304082497
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1737171793
Short name T362
Test name
Test status
Simulation time 101512388 ps
CPU time 4.69 seconds
Started Jul 31 05:12:31 PM PDT 24
Finished Jul 31 05:12:35 PM PDT 24
Peak memory 213968 kb
Host smart-a56eaacc-07f7-41fb-b9a0-c16f5e649ccc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737171793 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1737171793
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2128016197
Short name T416
Test name
Test status
Simulation time 461595864 ps
CPU time 4.18 seconds
Started Jul 31 05:12:11 PM PDT 24
Finished Jul 31 05:12:15 PM PDT 24
Peak memory 211296 kb
Host smart-55872551-8171-4dcc-8d9b-0c8c3c9bb1bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128016197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2128016197
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3164899818
Short name T330
Test name
Test status
Simulation time 246391605 ps
CPU time 4.89 seconds
Started Jul 31 05:12:16 PM PDT 24
Finished Jul 31 05:12:21 PM PDT 24
Peak memory 211184 kb
Host smart-c3aacaaa-c2ae-4e8e-9d18-6fb1f5473cfd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164899818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3164899818
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.90952742
Short name T381
Test name
Test status
Simulation time 100587284 ps
CPU time 4.2 seconds
Started Jul 31 05:12:21 PM PDT 24
Finished Jul 31 05:12:26 PM PDT 24
Peak memory 211204 kb
Host smart-6b2d8939-ddda-4a06-a919-08e8725eb3e0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90952742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.90952742
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2701461381
Short name T344
Test name
Test status
Simulation time 86090683 ps
CPU time 4.17 seconds
Started Jul 31 05:12:38 PM PDT 24
Finished Jul 31 05:12:42 PM PDT 24
Peak memory 211340 kb
Host smart-6b73b02e-20cd-407c-b815-4422c406a87f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701461381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2701461381
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2875882625
Short name T354
Test name
Test status
Simulation time 253276794 ps
CPU time 8.66 seconds
Started Jul 31 05:12:34 PM PDT 24
Finished Jul 31 05:12:43 PM PDT 24
Peak memory 219680 kb
Host smart-8cc4ff21-587f-4c6a-afae-eb8095f2e538
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875882625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2875882625
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2878135288
Short name T110
Test name
Test status
Simulation time 196925077 ps
CPU time 37.6 seconds
Started Jul 31 05:12:19 PM PDT 24
Finished Jul 31 05:12:57 PM PDT 24
Peak memory 212668 kb
Host smart-91a6bd7d-b970-4bd7-bd0a-d3fa28e1f4e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878135288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2878135288
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2751159882
Short name T383
Test name
Test status
Simulation time 333788900 ps
CPU time 4.27 seconds
Started Jul 31 05:12:33 PM PDT 24
Finished Jul 31 05:12:38 PM PDT 24
Peak memory 219452 kb
Host smart-65d9b13b-201b-4547-abd1-c7b9cbad1c29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751159882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2751159882
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1471678316
Short name T340
Test name
Test status
Simulation time 561413000 ps
CPU time 4.47 seconds
Started Jul 31 05:12:28 PM PDT 24
Finished Jul 31 05:12:33 PM PDT 24
Peak memory 211240 kb
Host smart-8fcd7502-f6ef-4e38-86da-2b9d2bcdf6e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471678316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1471678316
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1017560371
Short name T90
Test name
Test status
Simulation time 421850181 ps
CPU time 5.61 seconds
Started Jul 31 05:12:13 PM PDT 24
Finished Jul 31 05:12:19 PM PDT 24
Peak memory 219456 kb
Host smart-9fe65981-d8ca-4c39-bad2-b729e41472ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017560371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1017560371
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3282560223
Short name T334
Test name
Test status
Simulation time 263189929 ps
CPU time 5.14 seconds
Started Jul 31 05:12:20 PM PDT 24
Finished Jul 31 05:12:26 PM PDT 24
Peak memory 219476 kb
Host smart-0a105903-944b-4353-a4d5-dfe6b9f3906f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282560223 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3282560223
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.749446263
Short name T379
Test name
Test status
Simulation time 86081881 ps
CPU time 4.18 seconds
Started Jul 31 05:12:11 PM PDT 24
Finished Jul 31 05:12:16 PM PDT 24
Peak memory 211232 kb
Host smart-c48d9b43-c800-4169-901b-8171960b62af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749446263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.749446263
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1614732643
Short name T391
Test name
Test status
Simulation time 88991164 ps
CPU time 4.19 seconds
Started Jul 31 05:12:15 PM PDT 24
Finished Jul 31 05:12:20 PM PDT 24
Peak memory 211244 kb
Host smart-c9142268-06ea-48de-9fe8-9ed5993cea6c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614732643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1614732643
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.801050152
Short name T359
Test name
Test status
Simulation time 250880801 ps
CPU time 5.1 seconds
Started Jul 31 05:12:33 PM PDT 24
Finished Jul 31 05:12:39 PM PDT 24
Peak memory 211252 kb
Host smart-e084fba9-1dfd-4100-b326-c6734ac1ac91
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801050152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
801050152
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3490967468
Short name T370
Test name
Test status
Simulation time 138800384 ps
CPU time 7 seconds
Started Jul 31 05:12:17 PM PDT 24
Finished Jul 31 05:12:24 PM PDT 24
Peak memory 211372 kb
Host smart-946d0c7a-908c-4783-846c-ac4676448a24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490967468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3490967468
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2687630214
Short name T380
Test name
Test status
Simulation time 167130098 ps
CPU time 8.12 seconds
Started Jul 31 05:12:05 PM PDT 24
Finished Jul 31 05:12:13 PM PDT 24
Peak memory 219652 kb
Host smart-b3bce235-9368-41b4-aedd-b6c4c83556d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687630214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2687630214
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2674068458
Short name T392
Test name
Test status
Simulation time 535352544 ps
CPU time 8.23 seconds
Started Jul 31 05:12:31 PM PDT 24
Finished Jul 31 05:12:40 PM PDT 24
Peak memory 219600 kb
Host smart-8cde8bd2-4bcb-4f2e-b055-41de0d97e8a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674068458 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2674068458
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1908026641
Short name T87
Test name
Test status
Simulation time 255030144 ps
CPU time 4.32 seconds
Started Jul 31 05:12:28 PM PDT 24
Finished Jul 31 05:12:33 PM PDT 24
Peak memory 219456 kb
Host smart-710e3bad-0631-42b7-a463-ddde1faad7b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908026641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1908026641
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2081624485
Short name T66
Test name
Test status
Simulation time 298287177 ps
CPU time 4.3 seconds
Started Jul 31 05:12:35 PM PDT 24
Finished Jul 31 05:12:44 PM PDT 24
Peak memory 211352 kb
Host smart-3e708bff-63a1-43d8-9f07-e3736454198a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081624485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2081624485
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1502899652
Short name T350
Test name
Test status
Simulation time 132148165 ps
CPU time 9.18 seconds
Started Jul 31 05:12:37 PM PDT 24
Finished Jul 31 05:12:46 PM PDT 24
Peak memory 215632 kb
Host smart-68ed55b4-ef29-48b3-8336-ba67dd251992
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502899652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1502899652
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1080355461
Short name T103
Test name
Test status
Simulation time 161855224 ps
CPU time 36.66 seconds
Started Jul 31 05:12:23 PM PDT 24
Finished Jul 31 05:13:00 PM PDT 24
Peak memory 212104 kb
Host smart-708aa93a-a129-480a-91e8-2e3648d2ef5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080355461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1080355461
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.198703949
Short name T408
Test name
Test status
Simulation time 177693770 ps
CPU time 4.65 seconds
Started Jul 31 05:12:35 PM PDT 24
Finished Jul 31 05:12:40 PM PDT 24
Peak memory 214584 kb
Host smart-7c59c877-d552-4c59-9f0c-f71239f47368
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198703949 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.198703949
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4251162825
Short name T88
Test name
Test status
Simulation time 133047929 ps
CPU time 5.3 seconds
Started Jul 31 05:12:30 PM PDT 24
Finished Jul 31 05:12:35 PM PDT 24
Peak memory 211284 kb
Host smart-3625bebb-6bde-49c3-afdc-0cd68a849e30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251162825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.4251162825
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1295099996
Short name T68
Test name
Test status
Simulation time 734219456 ps
CPU time 5.11 seconds
Started Jul 31 05:12:21 PM PDT 24
Finished Jul 31 05:12:27 PM PDT 24
Peak memory 211288 kb
Host smart-b2289d64-b01d-4db6-97ad-90d887afd08c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295099996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1295099996
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.382691529
Short name T342
Test name
Test status
Simulation time 173196969 ps
CPU time 7.83 seconds
Started Jul 31 05:12:41 PM PDT 24
Finished Jul 31 05:12:49 PM PDT 24
Peak memory 217620 kb
Host smart-07207df0-be81-49db-9683-e9db14ddc838
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382691529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.382691529
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2671825606
Short name T111
Test name
Test status
Simulation time 874157237 ps
CPU time 68.25 seconds
Started Jul 31 05:12:37 PM PDT 24
Finished Jul 31 05:13:45 PM PDT 24
Peak memory 213128 kb
Host smart-c321ccc8-1c83-4ea9-b91c-bc99a2893ffc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671825606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2671825606
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2801639198
Short name T353
Test name
Test status
Simulation time 1107235596 ps
CPU time 5.59 seconds
Started Jul 31 05:12:38 PM PDT 24
Finished Jul 31 05:12:44 PM PDT 24
Peak memory 219660 kb
Host smart-b58d7da2-7b9d-4520-83ed-e40e957fd004
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801639198 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2801639198
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4218073243
Short name T86
Test name
Test status
Simulation time 500527247 ps
CPU time 5.04 seconds
Started Jul 31 05:12:46 PM PDT 24
Finished Jul 31 05:12:51 PM PDT 24
Peak memory 211348 kb
Host smart-a9ba4177-1d02-426a-8124-497e2c447689
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218073243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.4218073243
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2594739063
Short name T58
Test name
Test status
Simulation time 497936183 ps
CPU time 5.24 seconds
Started Jul 31 05:12:37 PM PDT 24
Finished Jul 31 05:12:43 PM PDT 24
Peak memory 211364 kb
Host smart-5213d2fa-f138-44e2-98bb-8d3ba0ad9764
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594739063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2594739063
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3576219848
Short name T367
Test name
Test status
Simulation time 348029437 ps
CPU time 6.24 seconds
Started Jul 31 05:12:42 PM PDT 24
Finished Jul 31 05:12:49 PM PDT 24
Peak memory 219644 kb
Host smart-9c80958f-51cb-498b-9566-874c5ba9db20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576219848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3576219848
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2918900467
Short name T108
Test name
Test status
Simulation time 313160893 ps
CPU time 71.35 seconds
Started Jul 31 05:12:29 PM PDT 24
Finished Jul 31 05:13:41 PM PDT 24
Peak memory 213064 kb
Host smart-f97e5e36-176a-426a-97fd-88239852b5b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918900467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2918900467
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.416177585
Short name T361
Test name
Test status
Simulation time 273164404 ps
CPU time 5.48 seconds
Started Jul 31 05:12:25 PM PDT 24
Finished Jul 31 05:12:30 PM PDT 24
Peak memory 219616 kb
Host smart-9891de30-2cdd-4d7d-be23-1e4008278854
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416177585 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.416177585
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3070583388
Short name T356
Test name
Test status
Simulation time 308549729 ps
CPU time 4.28 seconds
Started Jul 31 05:12:37 PM PDT 24
Finished Jul 31 05:12:41 PM PDT 24
Peak memory 211316 kb
Host smart-464d029d-20ef-4df7-be5a-c98b11f8a7c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070583388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3070583388
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1165509919
Short name T398
Test name
Test status
Simulation time 333003869 ps
CPU time 4.29 seconds
Started Jul 31 05:12:40 PM PDT 24
Finished Jul 31 05:12:44 PM PDT 24
Peak memory 219444 kb
Host smart-835fb854-81e4-443d-8c38-8c2dd68e2f7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165509919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1165509919
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1127159132
Short name T386
Test name
Test status
Simulation time 1762664557 ps
CPU time 8.27 seconds
Started Jul 31 05:12:30 PM PDT 24
Finished Jul 31 05:12:38 PM PDT 24
Peak memory 219708 kb
Host smart-81ebc411-3a6b-44d5-8887-513973a14f8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127159132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1127159132
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4281597255
Short name T414
Test name
Test status
Simulation time 2988044401 ps
CPU time 37.41 seconds
Started Jul 31 05:12:37 PM PDT 24
Finished Jul 31 05:13:14 PM PDT 24
Peak memory 219496 kb
Host smart-0b5eff13-55a4-4842-a046-7c62cd238cda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281597255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.4281597255
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4107687008
Short name T368
Test name
Test status
Simulation time 1019455888 ps
CPU time 7.81 seconds
Started Jul 31 05:12:50 PM PDT 24
Finished Jul 31 05:12:58 PM PDT 24
Peak memory 219604 kb
Host smart-d5db0994-a016-4349-ab18-90c0dcda848e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107687008 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4107687008
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1380376091
Short name T372
Test name
Test status
Simulation time 828974792 ps
CPU time 4.94 seconds
Started Jul 31 05:12:31 PM PDT 24
Finished Jul 31 05:12:36 PM PDT 24
Peak memory 218260 kb
Host smart-3c820d51-40a1-4b14-b41f-841b45a83511
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380376091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1380376091
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1816472503
Short name T374
Test name
Test status
Simulation time 361221936 ps
CPU time 4.26 seconds
Started Jul 31 05:12:32 PM PDT 24
Finished Jul 31 05:12:37 PM PDT 24
Peak memory 211320 kb
Host smart-aca6d39e-47e7-4fc0-84ef-dc12605433bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816472503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1816472503
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.105939204
Short name T358
Test name
Test status
Simulation time 126099725 ps
CPU time 8.02 seconds
Started Jul 31 05:12:37 PM PDT 24
Finished Jul 31 05:12:45 PM PDT 24
Peak memory 219696 kb
Host smart-1c0d85f2-9016-4592-9864-7b8f3a0ba200
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105939204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.105939204
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.205139935
Short name T396
Test name
Test status
Simulation time 161620308 ps
CPU time 5.55 seconds
Started Jul 31 05:12:40 PM PDT 24
Finished Jul 31 05:12:45 PM PDT 24
Peak memory 219616 kb
Host smart-61b4dc91-151d-430b-bb61-c4cecb7b8604
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205139935 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.205139935
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2705934081
Short name T349
Test name
Test status
Simulation time 396386252 ps
CPU time 4.13 seconds
Started Jul 31 05:12:35 PM PDT 24
Finished Jul 31 05:12:40 PM PDT 24
Peak memory 219444 kb
Host smart-99d9a8c7-4fd5-4368-9f77-9314dec401e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705934081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2705934081
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3930661192
Short name T71
Test name
Test status
Simulation time 175682297 ps
CPU time 4.3 seconds
Started Jul 31 05:12:39 PM PDT 24
Finished Jul 31 05:12:43 PM PDT 24
Peak memory 211384 kb
Host smart-a61c5ff8-4362-42cb-89f2-cabbc3adbcc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930661192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3930661192
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3757211921
Short name T337
Test name
Test status
Simulation time 261080107 ps
CPU time 7.17 seconds
Started Jul 31 05:12:48 PM PDT 24
Finished Jul 31 05:12:55 PM PDT 24
Peak memory 219708 kb
Host smart-fa399edc-fc6e-4e13-8a81-289038976d7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757211921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3757211921
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1805771857
Short name T336
Test name
Test status
Simulation time 532748888 ps
CPU time 5.28 seconds
Started Jul 31 05:12:38 PM PDT 24
Finished Jul 31 05:12:44 PM PDT 24
Peak memory 219600 kb
Host smart-3abd69e5-ed6e-4010-a6e8-b35b9979d0fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805771857 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1805771857
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3426514994
Short name T74
Test name
Test status
Simulation time 134642794 ps
CPU time 5.1 seconds
Started Jul 31 05:12:58 PM PDT 24
Finished Jul 31 05:13:03 PM PDT 24
Peak memory 211260 kb
Host smart-09e6d580-027d-479c-802a-f4a33c9c8737
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426514994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3426514994
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2519159051
Short name T390
Test name
Test status
Simulation time 252165087 ps
CPU time 5.18 seconds
Started Jul 31 05:12:40 PM PDT 24
Finished Jul 31 05:12:46 PM PDT 24
Peak memory 211312 kb
Host smart-742eec21-0830-4390-84e4-8da8fccaae8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519159051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2519159051
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2979890262
Short name T332
Test name
Test status
Simulation time 520652491 ps
CPU time 8.14 seconds
Started Jul 31 05:12:39 PM PDT 24
Finished Jul 31 05:12:47 PM PDT 24
Peak memory 216544 kb
Host smart-9ce3d3bc-3fba-4641-84f8-df6191c555cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979890262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2979890262
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1119593202
Short name T106
Test name
Test status
Simulation time 335687340 ps
CPU time 71.19 seconds
Started Jul 31 05:12:52 PM PDT 24
Finished Jul 31 05:14:07 PM PDT 24
Peak memory 213240 kb
Host smart-d5c1d83d-d65b-49e7-83b6-b2f73b73bc68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119593202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1119593202
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1597026792
Short name T341
Test name
Test status
Simulation time 101558224 ps
CPU time 5.61 seconds
Started Jul 31 05:12:30 PM PDT 24
Finished Jul 31 05:12:36 PM PDT 24
Peak memory 219612 kb
Host smart-f5d3d31f-dd71-4eac-a4e9-d17eec86c499
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597026792 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1597026792
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1812834980
Short name T98
Test name
Test status
Simulation time 130411110 ps
CPU time 5.14 seconds
Started Jul 31 05:12:32 PM PDT 24
Finished Jul 31 05:12:37 PM PDT 24
Peak memory 218136 kb
Host smart-8c5c6541-16ab-424a-8461-2a736bea1fe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812834980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1812834980
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1927989972
Short name T96
Test name
Test status
Simulation time 89834978 ps
CPU time 4.26 seconds
Started Jul 31 05:12:24 PM PDT 24
Finished Jul 31 05:12:28 PM PDT 24
Peak memory 211396 kb
Host smart-9588b222-4c88-4ce2-b7bf-b0647c2672af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927989972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1927989972
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.913987737
Short name T364
Test name
Test status
Simulation time 363961184 ps
CPU time 6.48 seconds
Started Jul 31 05:12:40 PM PDT 24
Finished Jul 31 05:12:47 PM PDT 24
Peak memory 219580 kb
Host smart-8b88eeaf-92ad-408b-a9a1-48cf5a1816dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913987737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.913987737
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.70268206
Short name T105
Test name
Test status
Simulation time 860262822 ps
CPU time 67.93 seconds
Started Jul 31 05:12:37 PM PDT 24
Finished Jul 31 05:13:45 PM PDT 24
Peak memory 212980 kb
Host smart-15d20f1b-be29-4285-bda5-8c1e3c855796
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70268206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_int
g_err.70268206
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.731733987
Short name T352
Test name
Test status
Simulation time 96156215 ps
CPU time 4.63 seconds
Started Jul 31 05:12:34 PM PDT 24
Finished Jul 31 05:12:39 PM PDT 24
Peak memory 219564 kb
Host smart-c1055847-29a3-46ea-8ea5-8beec416bee4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731733987 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.731733987
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1679839740
Short name T365
Test name
Test status
Simulation time 350472680 ps
CPU time 4.15 seconds
Started Jul 31 05:12:50 PM PDT 24
Finished Jul 31 05:12:54 PM PDT 24
Peak memory 219412 kb
Host smart-9f03ed64-afcc-48d9-a022-b6ecae3c2822
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679839740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1679839740
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1955216886
Short name T85
Test name
Test status
Simulation time 2402278733 ps
CPU time 18.97 seconds
Started Jul 31 05:12:38 PM PDT 24
Finished Jul 31 05:12:57 PM PDT 24
Peak memory 211416 kb
Host smart-2a37fe68-7832-4941-820f-1b96fb8cb198
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955216886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1955216886
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.236332232
Short name T345
Test name
Test status
Simulation time 554660909 ps
CPU time 6.76 seconds
Started Jul 31 05:12:56 PM PDT 24
Finished Jul 31 05:13:03 PM PDT 24
Peak memory 219452 kb
Host smart-07a4b11f-849e-4c32-8b57-9933a184b7cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236332232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.236332232
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3360995524
Short name T410
Test name
Test status
Simulation time 1184427120 ps
CPU time 7.63 seconds
Started Jul 31 05:12:35 PM PDT 24
Finished Jul 31 05:12:42 PM PDT 24
Peak memory 219568 kb
Host smart-a0513068-cb70-4d64-ad51-2b20035bd5e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360995524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3360995524
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4137542194
Short name T412
Test name
Test status
Simulation time 702007540 ps
CPU time 71.02 seconds
Started Jul 31 05:12:47 PM PDT 24
Finished Jul 31 05:13:58 PM PDT 24
Peak memory 219576 kb
Host smart-92293149-d20b-4d4b-8a71-78d0bfdfe5f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137542194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.4137542194
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.116119445
Short name T357
Test name
Test status
Simulation time 401041106 ps
CPU time 4.79 seconds
Started Jul 31 05:12:41 PM PDT 24
Finished Jul 31 05:12:46 PM PDT 24
Peak memory 215096 kb
Host smart-b5a5398c-c2a2-46e6-9bd4-4c9d0b6b1c3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116119445 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.116119445
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3900908023
Short name T346
Test name
Test status
Simulation time 256619591 ps
CPU time 5.19 seconds
Started Jul 31 05:12:38 PM PDT 24
Finished Jul 31 05:12:43 PM PDT 24
Peak memory 211296 kb
Host smart-36e18a61-7697-472b-81d8-97b1a32f018b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900908023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3900908023
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3725987338
Short name T84
Test name
Test status
Simulation time 2787565724 ps
CPU time 18.88 seconds
Started Jul 31 05:12:42 PM PDT 24
Finished Jul 31 05:13:01 PM PDT 24
Peak memory 211500 kb
Host smart-c6d1b17a-0ae4-4011-8370-1986e14e1768
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725987338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3725987338
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3158246123
Short name T57
Test name
Test status
Simulation time 132332815 ps
CPU time 5.09 seconds
Started Jul 31 05:12:45 PM PDT 24
Finished Jul 31 05:12:50 PM PDT 24
Peak memory 218744 kb
Host smart-4e1e9e90-3974-4636-aeff-13e396c24497
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158246123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3158246123
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2091470995
Short name T402
Test name
Test status
Simulation time 186727416 ps
CPU time 8.47 seconds
Started Jul 31 05:12:39 PM PDT 24
Finished Jul 31 05:12:48 PM PDT 24
Peak memory 216708 kb
Host smart-0206fba5-a861-4cdd-8c91-e79641b22eb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091470995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2091470995
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.25948978
Short name T113
Test name
Test status
Simulation time 1179886431 ps
CPU time 36.98 seconds
Started Jul 31 05:12:40 PM PDT 24
Finished Jul 31 05:13:18 PM PDT 24
Peak memory 212036 kb
Host smart-13fd474b-3ccc-49f7-af67-e996406d36f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25948978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_int
g_err.25948978
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1436865802
Short name T92
Test name
Test status
Simulation time 516023867 ps
CPU time 7.85 seconds
Started Jul 31 05:12:26 PM PDT 24
Finished Jul 31 05:12:34 PM PDT 24
Peak memory 217916 kb
Host smart-f68cd52a-3d54-4ecd-9c68-ff1b0870bba9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436865802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1436865802
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2734872643
Short name T388
Test name
Test status
Simulation time 130435308 ps
CPU time 5.3 seconds
Started Jul 31 05:12:20 PM PDT 24
Finished Jul 31 05:12:26 PM PDT 24
Peak memory 211268 kb
Host smart-cedeef39-5307-4aed-b557-50db997a8b30
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734872643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2734872643
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4001912962
Short name T355
Test name
Test status
Simulation time 132737440 ps
CPU time 6.48 seconds
Started Jul 31 05:12:13 PM PDT 24
Finished Jul 31 05:12:20 PM PDT 24
Peak memory 211320 kb
Host smart-78d515ee-e1ad-4016-b7e1-2f9588f27cc8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001912962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.4001912962
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2441667099
Short name T333
Test name
Test status
Simulation time 602330816 ps
CPU time 5.39 seconds
Started Jul 31 05:12:25 PM PDT 24
Finished Jul 31 05:12:30 PM PDT 24
Peak memory 219604 kb
Host smart-bb805101-6984-467e-9492-d6bd5512851a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441667099 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2441667099
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3353246732
Short name T409
Test name
Test status
Simulation time 284361646 ps
CPU time 4.96 seconds
Started Jul 31 05:12:14 PM PDT 24
Finished Jul 31 05:12:20 PM PDT 24
Peak memory 218036 kb
Host smart-ed91cd96-4c92-48cf-be17-76277989af4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353246732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3353246732
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1279434649
Short name T415
Test name
Test status
Simulation time 134380871 ps
CPU time 4.3 seconds
Started Jul 31 05:12:12 PM PDT 24
Finished Jul 31 05:12:17 PM PDT 24
Peak memory 211192 kb
Host smart-11d516b5-d77f-4457-b4f5-7aa42e5dc48e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279434649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1279434649
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.773060838
Short name T387
Test name
Test status
Simulation time 132664785 ps
CPU time 5.02 seconds
Started Jul 31 05:12:12 PM PDT 24
Finished Jul 31 05:12:17 PM PDT 24
Peak memory 211244 kb
Host smart-e788ce47-e658-4f66-9def-7977bf4abc73
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773060838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
773060838
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1531156087
Short name T400
Test name
Test status
Simulation time 381081391 ps
CPU time 4.31 seconds
Started Jul 31 05:12:26 PM PDT 24
Finished Jul 31 05:12:30 PM PDT 24
Peak memory 211396 kb
Host smart-2b1e191d-7a25-4b29-952e-cb7c90c5a8e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531156087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1531156087
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3529152658
Short name T343
Test name
Test status
Simulation time 135472973 ps
CPU time 9.46 seconds
Started Jul 31 05:12:26 PM PDT 24
Finished Jul 31 05:12:36 PM PDT 24
Peak memory 215340 kb
Host smart-6bf68546-0901-42b8-a617-6758d166145d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529152658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3529152658
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3953187972
Short name T104
Test name
Test status
Simulation time 424684668 ps
CPU time 67.16 seconds
Started Jul 31 05:12:21 PM PDT 24
Finished Jul 31 05:13:28 PM PDT 24
Peak memory 212952 kb
Host smart-7ec4c3eb-641b-4f17-9a8b-854da25d03c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953187972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3953187972
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.446721377
Short name T83
Test name
Test status
Simulation time 132392405 ps
CPU time 5.04 seconds
Started Jul 31 05:12:26 PM PDT 24
Finished Jul 31 05:12:32 PM PDT 24
Peak memory 211200 kb
Host smart-ca612f1f-b1da-4b27-81f7-1308738d8fe7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446721377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.446721377
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3946007667
Short name T413
Test name
Test status
Simulation time 350408132 ps
CPU time 4.55 seconds
Started Jul 31 05:12:12 PM PDT 24
Finished Jul 31 05:12:17 PM PDT 24
Peak memory 219492 kb
Host smart-b4f65d7d-9319-4497-a1a7-c84362519607
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946007667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3946007667
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.681665684
Short name T411
Test name
Test status
Simulation time 91059010 ps
CPU time 7.38 seconds
Started Jul 31 05:12:15 PM PDT 24
Finished Jul 31 05:12:23 PM PDT 24
Peak memory 211228 kb
Host smart-97152e29-8546-4c42-ae92-ada7acde58c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681665684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.681665684
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3723354566
Short name T395
Test name
Test status
Simulation time 135562773 ps
CPU time 5.29 seconds
Started Jul 31 05:12:38 PM PDT 24
Finished Jul 31 05:12:43 PM PDT 24
Peak memory 214952 kb
Host smart-15e091ee-8291-4202-a238-1e48c0714f60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723354566 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3723354566
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2876230701
Short name T394
Test name
Test status
Simulation time 249616776 ps
CPU time 4.97 seconds
Started Jul 31 05:12:13 PM PDT 24
Finished Jul 31 05:12:18 PM PDT 24
Peak memory 218652 kb
Host smart-d99ccef3-f69b-422c-82d1-ad99dfa53507
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876230701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2876230701
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4022329805
Short name T399
Test name
Test status
Simulation time 88685431 ps
CPU time 4.29 seconds
Started Jul 31 05:12:26 PM PDT 24
Finished Jul 31 05:12:30 PM PDT 24
Peak memory 211224 kb
Host smart-812140cf-fd5f-47a0-8132-37180c0a98d4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022329805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.4022329805
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2743889796
Short name T347
Test name
Test status
Simulation time 523568368 ps
CPU time 4.89 seconds
Started Jul 31 05:12:29 PM PDT 24
Finished Jul 31 05:12:34 PM PDT 24
Peak memory 211192 kb
Host smart-da130d96-a8b1-47cd-8ea9-76636823f91b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743889796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2743889796
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.726119288
Short name T95
Test name
Test status
Simulation time 455033900 ps
CPU time 6.74 seconds
Started Jul 31 05:12:15 PM PDT 24
Finished Jul 31 05:12:22 PM PDT 24
Peak memory 211392 kb
Host smart-5fbc09cb-6ece-470e-bafa-27eae48b775a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726119288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.726119288
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2571202261
Short name T401
Test name
Test status
Simulation time 294587008 ps
CPU time 10.34 seconds
Started Jul 31 05:12:24 PM PDT 24
Finished Jul 31 05:12:34 PM PDT 24
Peak memory 216404 kb
Host smart-af3fcbcd-78ea-43ef-b415-86d3db8d022e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571202261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2571202261
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3292405651
Short name T56
Test name
Test status
Simulation time 357497222 ps
CPU time 71.66 seconds
Started Jul 31 05:12:15 PM PDT 24
Finished Jul 31 05:13:27 PM PDT 24
Peak memory 213256 kb
Host smart-fb5515f1-fea9-4f67-9755-8ea57eac2066
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292405651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3292405651
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2677168186
Short name T382
Test name
Test status
Simulation time 175306566 ps
CPU time 4.14 seconds
Started Jul 31 05:12:14 PM PDT 24
Finished Jul 31 05:12:18 PM PDT 24
Peak memory 211280 kb
Host smart-fcb0e1d0-6ac6-49f5-bc71-cd6a26929ff6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677168186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2677168186
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1592394747
Short name T93
Test name
Test status
Simulation time 126822705 ps
CPU time 5.5 seconds
Started Jul 31 05:12:21 PM PDT 24
Finished Jul 31 05:12:32 PM PDT 24
Peak memory 218092 kb
Host smart-c606ec48-32f8-487e-80b1-49bd0688fa9c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592394747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1592394747
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4030667204
Short name T363
Test name
Test status
Simulation time 287660869 ps
CPU time 8.39 seconds
Started Jul 31 05:12:17 PM PDT 24
Finished Jul 31 05:12:26 PM PDT 24
Peak memory 211272 kb
Host smart-08ce4733-0e1f-4a86-b185-8ba3bba81168
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030667204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4030667204
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2109002263
Short name T393
Test name
Test status
Simulation time 140872042 ps
CPU time 5.76 seconds
Started Jul 31 05:12:29 PM PDT 24
Finished Jul 31 05:12:35 PM PDT 24
Peak memory 219636 kb
Host smart-4b5b764c-aa90-492a-9fd4-9a9196298da7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109002263 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2109002263
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3056570458
Short name T89
Test name
Test status
Simulation time 257048236 ps
CPU time 5.03 seconds
Started Jul 31 05:12:24 PM PDT 24
Finished Jul 31 05:12:29 PM PDT 24
Peak memory 218276 kb
Host smart-caf8489d-0061-4778-9f93-6150b0f0c119
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056570458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3056570458
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4204043352
Short name T331
Test name
Test status
Simulation time 521194397 ps
CPU time 4.94 seconds
Started Jul 31 05:12:29 PM PDT 24
Finished Jul 31 05:12:34 PM PDT 24
Peak memory 211084 kb
Host smart-7f718b7d-e1e4-438d-bbe7-04db336db027
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204043352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.4204043352
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2105609751
Short name T377
Test name
Test status
Simulation time 346366847 ps
CPU time 4.17 seconds
Started Jul 31 05:12:23 PM PDT 24
Finished Jul 31 05:12:28 PM PDT 24
Peak memory 211256 kb
Host smart-52551b92-98e9-42b9-b117-0de1092d88ee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105609751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2105609751
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2110672050
Short name T406
Test name
Test status
Simulation time 569717299 ps
CPU time 5.05 seconds
Started Jul 31 05:12:16 PM PDT 24
Finished Jul 31 05:12:22 PM PDT 24
Peak memory 218528 kb
Host smart-97f31acc-4950-4679-bc7d-b0b6f22b45a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110672050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2110672050
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.937936219
Short name T403
Test name
Test status
Simulation time 154325815 ps
CPU time 10 seconds
Started Jul 31 05:12:29 PM PDT 24
Finished Jul 31 05:12:39 PM PDT 24
Peak memory 219616 kb
Host smart-59fb3210-9d13-4611-8703-d322178fd6d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937936219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.937936219
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4229020266
Short name T339
Test name
Test status
Simulation time 419010508 ps
CPU time 69.24 seconds
Started Jul 31 05:12:33 PM PDT 24
Finished Jul 31 05:13:43 PM PDT 24
Peak memory 219684 kb
Host smart-6651cf3c-d592-48ce-a76f-5ec5bfcf269e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229020266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.4229020266
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.887629708
Short name T397
Test name
Test status
Simulation time 140071634 ps
CPU time 5.62 seconds
Started Jul 31 05:12:20 PM PDT 24
Finished Jul 31 05:12:25 PM PDT 24
Peak memory 215668 kb
Host smart-297131d9-e248-4511-a601-8a925d7a34e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887629708 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.887629708
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3229953513
Short name T407
Test name
Test status
Simulation time 521913344 ps
CPU time 4.91 seconds
Started Jul 31 05:12:28 PM PDT 24
Finished Jul 31 05:12:33 PM PDT 24
Peak memory 211292 kb
Host smart-e9e04f62-4a0b-414c-bd4b-60a448ece71c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229953513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3229953513
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1649716399
Short name T384
Test name
Test status
Simulation time 388098378 ps
CPU time 19.07 seconds
Started Jul 31 05:12:22 PM PDT 24
Finished Jul 31 05:12:41 PM PDT 24
Peak memory 211308 kb
Host smart-bd1bf609-0936-425a-9661-0431268b84af
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649716399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1649716399
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1748183799
Short name T378
Test name
Test status
Simulation time 350656183 ps
CPU time 4.17 seconds
Started Jul 31 05:12:20 PM PDT 24
Finished Jul 31 05:12:24 PM PDT 24
Peak memory 219468 kb
Host smart-c395f853-2dc4-4053-87aa-05fe1528f9b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748183799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1748183799
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2470929828
Short name T375
Test name
Test status
Simulation time 260562230 ps
CPU time 8.52 seconds
Started Jul 31 05:12:09 PM PDT 24
Finished Jul 31 05:12:18 PM PDT 24
Peak memory 219696 kb
Host smart-28cad3e3-e248-4d59-9a29-bfe9e70dc087
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470929828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2470929828
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3756936799
Short name T366
Test name
Test status
Simulation time 146340608 ps
CPU time 5.81 seconds
Started Jul 31 05:12:23 PM PDT 24
Finished Jul 31 05:12:28 PM PDT 24
Peak memory 219564 kb
Host smart-2b6ed754-8ba3-43c9-b78f-9acddf33ec3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756936799 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3756936799
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2307718253
Short name T72
Test name
Test status
Simulation time 779224763 ps
CPU time 5.05 seconds
Started Jul 31 05:12:25 PM PDT 24
Finished Jul 31 05:12:31 PM PDT 24
Peak memory 218576 kb
Host smart-13d1429d-2d1c-4b11-8e4f-1e70fee6e747
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307718253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2307718253
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1987084119
Short name T348
Test name
Test status
Simulation time 262106076 ps
CPU time 5.09 seconds
Started Jul 31 05:12:19 PM PDT 24
Finished Jul 31 05:12:24 PM PDT 24
Peak memory 218584 kb
Host smart-7d1651e7-d38b-4eb2-9f4a-f3b5d2c546a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987084119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1987084119
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3651908695
Short name T360
Test name
Test status
Simulation time 1768787036 ps
CPU time 7.51 seconds
Started Jul 31 05:12:33 PM PDT 24
Finished Jul 31 05:12:40 PM PDT 24
Peak memory 217712 kb
Host smart-383c2bf3-9ea4-4017-a689-bb4c70897cad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651908695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3651908695
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3616505629
Short name T385
Test name
Test status
Simulation time 772761654 ps
CPU time 68.11 seconds
Started Jul 31 05:12:28 PM PDT 24
Finished Jul 31 05:13:36 PM PDT 24
Peak memory 219524 kb
Host smart-8665f469-4a76-4ec7-8be3-d1a76385f1af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616505629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3616505629
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3572664049
Short name T389
Test name
Test status
Simulation time 599327591 ps
CPU time 5.92 seconds
Started Jul 31 05:12:30 PM PDT 24
Finished Jul 31 05:12:36 PM PDT 24
Peak memory 219656 kb
Host smart-9f7d4423-7e5c-4c93-83fe-010834ce01b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572664049 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3572664049
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1673132812
Short name T91
Test name
Test status
Simulation time 209237656 ps
CPU time 4.05 seconds
Started Jul 31 05:12:38 PM PDT 24
Finished Jul 31 05:12:42 PM PDT 24
Peak memory 219364 kb
Host smart-5d24d41c-3328-4652-96b6-23ce59e2dacf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673132812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1673132812
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3007505406
Short name T67
Test name
Test status
Simulation time 335049111 ps
CPU time 4.57 seconds
Started Jul 31 05:12:21 PM PDT 24
Finished Jul 31 05:12:25 PM PDT 24
Peak memory 211352 kb
Host smart-4d0f2cb4-7124-4340-90b4-e27f080e8db9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007505406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3007505406
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.281714337
Short name T335
Test name
Test status
Simulation time 132736443 ps
CPU time 7.06 seconds
Started Jul 31 05:12:11 PM PDT 24
Finished Jul 31 05:12:18 PM PDT 24
Peak memory 215144 kb
Host smart-a4efa66f-987f-4723-b010-b0db02879eaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281714337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.281714337
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4071178044
Short name T371
Test name
Test status
Simulation time 159802820 ps
CPU time 36.75 seconds
Started Jul 31 05:12:26 PM PDT 24
Finished Jul 31 05:13:03 PM PDT 24
Peak memory 211688 kb
Host smart-5e881f53-f7f6-4d11-967f-ef4d8a5c9673
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071178044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.4071178044
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2881694781
Short name T369
Test name
Test status
Simulation time 355087007 ps
CPU time 4.28 seconds
Started Jul 31 05:12:22 PM PDT 24
Finished Jul 31 05:12:26 PM PDT 24
Peak memory 212912 kb
Host smart-57a57dc0-7a10-4f43-96d4-f9bab441e3e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881694781 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2881694781
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2693114025
Short name T373
Test name
Test status
Simulation time 130912564 ps
CPU time 5.04 seconds
Started Jul 31 05:12:29 PM PDT 24
Finished Jul 31 05:12:34 PM PDT 24
Peak memory 211304 kb
Host smart-8a615970-7362-4d98-ba93-e5a6267be300
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693114025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2693114025
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.872437064
Short name T94
Test name
Test status
Simulation time 346740637 ps
CPU time 4.19 seconds
Started Jul 31 05:12:16 PM PDT 24
Finished Jul 31 05:12:20 PM PDT 24
Peak memory 219520 kb
Host smart-3dc7a721-75ee-4ebf-b316-6be2c7194d6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872437064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.872437064
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.441994423
Short name T338
Test name
Test status
Simulation time 299429866 ps
CPU time 8.98 seconds
Started Jul 31 05:12:32 PM PDT 24
Finished Jul 31 05:12:41 PM PDT 24
Peak memory 219628 kb
Host smart-b86de5e3-b58e-4013-bc2d-5dd24779d538
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441994423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.441994423
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4134814357
Short name T109
Test name
Test status
Simulation time 1603351775 ps
CPU time 72.7 seconds
Started Jul 31 05:12:28 PM PDT 24
Finished Jul 31 05:13:41 PM PDT 24
Peak memory 219540 kb
Host smart-e7eecccc-5445-43db-b237-709657338b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134814357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.4134814357
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2323513687
Short name T405
Test name
Test status
Simulation time 193535767 ps
CPU time 4.84 seconds
Started Jul 31 05:12:16 PM PDT 24
Finished Jul 31 05:12:21 PM PDT 24
Peak memory 219620 kb
Host smart-f157d099-017c-4378-90a2-e393aa3d2a0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323513687 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2323513687
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2687747739
Short name T376
Test name
Test status
Simulation time 85867191 ps
CPU time 4.24 seconds
Started Jul 31 05:12:33 PM PDT 24
Finished Jul 31 05:12:37 PM PDT 24
Peak memory 211316 kb
Host smart-270ef479-7159-4748-ad85-68586eebf6ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687747739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2687747739
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2991852626
Short name T70
Test name
Test status
Simulation time 86148595 ps
CPU time 4.53 seconds
Started Jul 31 05:12:30 PM PDT 24
Finished Jul 31 05:12:35 PM PDT 24
Peak memory 211540 kb
Host smart-fa8cbde1-f5c6-4461-921a-6b94eef97e6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991852626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2991852626
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2219707181
Short name T351
Test name
Test status
Simulation time 501016780 ps
CPU time 8.97 seconds
Started Jul 31 05:12:22 PM PDT 24
Finished Jul 31 05:12:31 PM PDT 24
Peak memory 216652 kb
Host smart-9ad11e84-5b6e-4fa6-91e7-5c92d2de27de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219707181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2219707181
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1095028842
Short name T55
Test name
Test status
Simulation time 2516439498 ps
CPU time 68.34 seconds
Started Jul 31 05:12:37 PM PDT 24
Finished Jul 31 05:13:46 PM PDT 24
Peak memory 213136 kb
Host smart-a220e751-81b7-4195-a0bc-04460b15eaf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095028842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1095028842
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.754903790
Short name T309
Test name
Test status
Simulation time 932104999 ps
CPU time 4.36 seconds
Started Jul 31 05:34:14 PM PDT 24
Finished Jul 31 05:34:18 PM PDT 24
Peak memory 212036 kb
Host smart-1676d20b-759f-4105-81d1-0f50237b7d17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754903790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.754903790
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1717517710
Short name T317
Test name
Test status
Simulation time 28172664753 ps
CPU time 139.87 seconds
Started Jul 31 05:34:09 PM PDT 24
Finished Jul 31 05:36:29 PM PDT 24
Peak memory 238208 kb
Host smart-5af9eb17-adef-40f5-a27b-b00d78126181
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717517710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1717517710
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1336981479
Short name T176
Test name
Test status
Simulation time 341350068 ps
CPU time 9.67 seconds
Started Jul 31 05:34:13 PM PDT 24
Finished Jul 31 05:34:23 PM PDT 24
Peak memory 212892 kb
Host smart-0dbc4248-ffa9-466c-9934-f9246d30c1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336981479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1336981479
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.529599182
Short name T7
Test name
Test status
Simulation time 193337528 ps
CPU time 5.81 seconds
Started Jul 31 05:34:09 PM PDT 24
Finished Jul 31 05:34:15 PM PDT 24
Peak memory 212140 kb
Host smart-9ff37a06-8d35-4ea7-9b99-75226608ef96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=529599182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.529599182
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2883778987
Short name T22
Test name
Test status
Simulation time 404563815 ps
CPU time 103.34 seconds
Started Jul 31 05:34:08 PM PDT 24
Finished Jul 31 05:35:51 PM PDT 24
Peak memory 237368 kb
Host smart-3b84732a-84fa-438b-a241-4f8d4dc95533
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883778987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2883778987
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1480955619
Short name T211
Test name
Test status
Simulation time 386508914 ps
CPU time 5.61 seconds
Started Jul 31 05:34:12 PM PDT 24
Finished Jul 31 05:34:18 PM PDT 24
Peak memory 211696 kb
Host smart-8e53a596-0876-4d8e-a88c-30084112bd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480955619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1480955619
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.128163535
Short name T181
Test name
Test status
Simulation time 1677816138 ps
CPU time 21.21 seconds
Started Jul 31 05:34:12 PM PDT 24
Finished Jul 31 05:34:34 PM PDT 24
Peak memory 217048 kb
Host smart-67538992-aa45-40cd-8659-51c5c71780aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128163535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.128163535
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3009732515
Short name T298
Test name
Test status
Simulation time 285974685 ps
CPU time 5.22 seconds
Started Jul 31 05:34:10 PM PDT 24
Finished Jul 31 05:34:15 PM PDT 24
Peak memory 212052 kb
Host smart-db168f2d-b7c7-4e95-aab3-693e94f2ca51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009732515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3009732515
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1584012626
Short name T180
Test name
Test status
Simulation time 7794739727 ps
CPU time 101.18 seconds
Started Jul 31 05:34:09 PM PDT 24
Finished Jul 31 05:35:50 PM PDT 24
Peak memory 214464 kb
Host smart-481adf27-4ec6-4048-9f85-d28e7da06a54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584012626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1584012626
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1761594694
Short name T35
Test name
Test status
Simulation time 251271073 ps
CPU time 11.22 seconds
Started Jul 31 05:34:09 PM PDT 24
Finished Jul 31 05:34:20 PM PDT 24
Peak memory 212852 kb
Host smart-0d33afc0-c446-4681-a230-c3d83836cfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761594694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1761594694
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.985097558
Short name T155
Test name
Test status
Simulation time 541080809 ps
CPU time 6.94 seconds
Started Jul 31 05:34:13 PM PDT 24
Finished Jul 31 05:34:20 PM PDT 24
Peak memory 212128 kb
Host smart-ff2a0e3c-3ca1-425c-865a-60a5a9977c09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=985097558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.985097558
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2938314492
Short name T25
Test name
Test status
Simulation time 813394892 ps
CPU time 53.21 seconds
Started Jul 31 05:34:09 PM PDT 24
Finished Jul 31 05:35:02 PM PDT 24
Peak memory 237344 kb
Host smart-a149564b-7972-4d94-a72b-33ee17d9a816
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938314492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2938314492
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.740300319
Short name T300
Test name
Test status
Simulation time 413156857 ps
CPU time 5.65 seconds
Started Jul 31 05:34:08 PM PDT 24
Finished Jul 31 05:34:14 PM PDT 24
Peak memory 212376 kb
Host smart-90d7ce9d-2c14-4b9c-bbe0-30e998bd42c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740300319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.740300319
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1959849919
Short name T175
Test name
Test status
Simulation time 99433750 ps
CPU time 8.19 seconds
Started Jul 31 05:34:09 PM PDT 24
Finished Jul 31 05:34:17 PM PDT 24
Peak memory 212096 kb
Host smart-9ee06649-cfff-4c91-a694-baf7caa67d92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959849919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1959849919
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2040996413
Short name T4
Test name
Test status
Simulation time 175671081 ps
CPU time 4.31 seconds
Started Jul 31 05:34:25 PM PDT 24
Finished Jul 31 05:34:29 PM PDT 24
Peak memory 212020 kb
Host smart-15e4b624-484a-4095-a2fa-ec3fbaeb86fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040996413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2040996413
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3519431986
Short name T164
Test name
Test status
Simulation time 40116984842 ps
CPU time 175.42 seconds
Started Jul 31 05:34:23 PM PDT 24
Finished Jul 31 05:37:19 PM PDT 24
Peak memory 213632 kb
Host smart-2aeaef07-78f6-48ba-bd14-b03e4c62e5a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519431986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3519431986
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2789061234
Short name T217
Test name
Test status
Simulation time 491573422 ps
CPU time 11.22 seconds
Started Jul 31 05:34:27 PM PDT 24
Finished Jul 31 05:34:38 PM PDT 24
Peak memory 212864 kb
Host smart-804cb963-4d95-4ced-9689-b30bb8ac0843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789061234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2789061234
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1776449987
Short name T125
Test name
Test status
Simulation time 598491775 ps
CPU time 6.64 seconds
Started Jul 31 05:34:23 PM PDT 24
Finished Jul 31 05:34:30 PM PDT 24
Peak memory 212152 kb
Host smart-f9ada1fd-87bf-4bca-b227-40a2815a54ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1776449987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1776449987
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4211095693
Short name T231
Test name
Test status
Simulation time 742698821 ps
CPU time 12.94 seconds
Started Jul 31 05:34:28 PM PDT 24
Finished Jul 31 05:34:41 PM PDT 24
Peak memory 214852 kb
Host smart-fcf60f2e-27e4-4c9a-9537-92d2e66d2843
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211095693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.4211095693
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3807853186
Short name T320
Test name
Test status
Simulation time 6252610935 ps
CPU time 117.04 seconds
Started Jul 31 05:34:28 PM PDT 24
Finished Jul 31 05:36:25 PM PDT 24
Peak memory 235428 kb
Host smart-8f3da1cb-b1e3-49f4-99bc-27427f4ae24e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807853186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3807853186
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2944666786
Short name T255
Test name
Test status
Simulation time 179138675 ps
CPU time 9.82 seconds
Started Jul 31 05:34:25 PM PDT 24
Finished Jul 31 05:34:35 PM PDT 24
Peak memory 212852 kb
Host smart-f7abb239-53d5-43c2-b4ee-6178b51c707f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944666786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2944666786
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2414607258
Short name T166
Test name
Test status
Simulation time 265828203 ps
CPU time 6.6 seconds
Started Jul 31 05:34:27 PM PDT 24
Finished Jul 31 05:34:34 PM PDT 24
Peak memory 212168 kb
Host smart-21fe284e-b055-4833-b08c-6c5c740a8bfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2414607258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2414607258
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3605591072
Short name T223
Test name
Test status
Simulation time 527344851 ps
CPU time 11.19 seconds
Started Jul 31 05:34:29 PM PDT 24
Finished Jul 31 05:34:40 PM PDT 24
Peak memory 212124 kb
Host smart-b532dc39-3a03-41df-ac80-7d7f77d6d666
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605591072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3605591072
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2196026081
Short name T222
Test name
Test status
Simulation time 19996459864 ps
CPU time 875.46 seconds
Started Jul 31 05:34:25 PM PDT 24
Finished Jul 31 05:49:00 PM PDT 24
Peak memory 236672 kb
Host smart-bf6402a8-ea36-458d-a377-6323273668ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196026081 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2196026081
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3859293605
Short name T44
Test name
Test status
Simulation time 252532230 ps
CPU time 5.19 seconds
Started Jul 31 05:34:27 PM PDT 24
Finished Jul 31 05:34:32 PM PDT 24
Peak memory 211960 kb
Host smart-92e14b65-3d70-451c-9d17-2cdc41e8c3a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859293605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3859293605
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1728607531
Short name T213
Test name
Test status
Simulation time 7203986011 ps
CPU time 132.73 seconds
Started Jul 31 05:34:25 PM PDT 24
Finished Jul 31 05:36:38 PM PDT 24
Peak memory 238532 kb
Host smart-c76fa2c9-c190-4c6f-a883-8b8a41558b32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728607531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1728607531
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1306708931
Short name T150
Test name
Test status
Simulation time 521889889 ps
CPU time 11.31 seconds
Started Jul 31 05:34:23 PM PDT 24
Finished Jul 31 05:34:34 PM PDT 24
Peak memory 212120 kb
Host smart-c271100d-b885-426c-8c57-9e9e95999017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306708931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1306708931
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.151852056
Short name T294
Test name
Test status
Simulation time 99568858 ps
CPU time 5.63 seconds
Started Jul 31 05:34:25 PM PDT 24
Finished Jul 31 05:34:30 PM PDT 24
Peak memory 212112 kb
Host smart-a8ec3ce1-6e32-442e-b7c1-0bf44c56d200
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=151852056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.151852056
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.792954921
Short name T299
Test name
Test status
Simulation time 3738578309 ps
CPU time 14.53 seconds
Started Jul 31 05:34:29 PM PDT 24
Finished Jul 31 05:34:44 PM PDT 24
Peak memory 214364 kb
Host smart-eedd63e2-3f58-4fab-ac30-b8825f5f18f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792954921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.792954921
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1944242093
Short name T122
Test name
Test status
Simulation time 85640044 ps
CPU time 4.3 seconds
Started Jul 31 05:34:28 PM PDT 24
Finished Jul 31 05:34:32 PM PDT 24
Peak memory 212060 kb
Host smart-1ba4244b-b217-4f3d-99f5-aa23a435ac15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944242093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1944242093
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.42256849
Short name T184
Test name
Test status
Simulation time 4637290193 ps
CPU time 85.77 seconds
Started Jul 31 05:34:28 PM PDT 24
Finished Jul 31 05:35:54 PM PDT 24
Peak memory 238504 kb
Host smart-6c395445-425a-4bd7-8d90-4b0f3e3ab57f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42256849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_co
rrupt_sig_fatal_chk.42256849
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.56693855
Short name T145
Test name
Test status
Simulation time 1773430365 ps
CPU time 11.33 seconds
Started Jul 31 05:34:27 PM PDT 24
Finished Jul 31 05:34:38 PM PDT 24
Peak memory 212928 kb
Host smart-9616e076-6921-4e23-b2f7-4e2db8cc0806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56693855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.56693855
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.880678489
Short name T230
Test name
Test status
Simulation time 142198747 ps
CPU time 6.54 seconds
Started Jul 31 05:34:24 PM PDT 24
Finished Jul 31 05:34:30 PM PDT 24
Peak memory 212148 kb
Host smart-c2d2dc19-377d-459c-9229-fb5f7a5f5333
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=880678489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.880678489
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2894509158
Short name T306
Test name
Test status
Simulation time 440557985 ps
CPU time 18.25 seconds
Started Jul 31 05:34:24 PM PDT 24
Finished Jul 31 05:34:42 PM PDT 24
Peak memory 217200 kb
Host smart-16ff237d-e822-441e-a4d1-cf8c75087c58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894509158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2894509158
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3200107554
Short name T202
Test name
Test status
Simulation time 48201718640 ps
CPU time 1841.14 seconds
Started Jul 31 05:34:28 PM PDT 24
Finished Jul 31 06:05:09 PM PDT 24
Peak memory 236692 kb
Host smart-0b09785e-bb5d-45d9-864e-925c5e9c5b0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200107554 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3200107554
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2709856698
Short name T169
Test name
Test status
Simulation time 150157194 ps
CPU time 5.14 seconds
Started Jul 31 05:34:30 PM PDT 24
Finished Jul 31 05:34:36 PM PDT 24
Peak memory 212032 kb
Host smart-fe789905-e663-4c4a-80a4-030c3fd23a5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709856698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2709856698
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.767151668
Short name T177
Test name
Test status
Simulation time 489777081 ps
CPU time 9.51 seconds
Started Jul 31 05:34:31 PM PDT 24
Finished Jul 31 05:34:41 PM PDT 24
Peak memory 212892 kb
Host smart-0cb05502-3f1e-4ea7-83fe-d87947101a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767151668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.767151668
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2165748560
Short name T65
Test name
Test status
Simulation time 271805967 ps
CPU time 6.35 seconds
Started Jul 31 05:34:30 PM PDT 24
Finished Jul 31 05:34:37 PM PDT 24
Peak memory 212128 kb
Host smart-5e9ebcc6-5b2a-47f7-b793-dd2618df0052
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2165748560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2165748560
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1017406610
Short name T127
Test name
Test status
Simulation time 199686792 ps
CPU time 8.52 seconds
Started Jul 31 05:34:28 PM PDT 24
Finished Jul 31 05:34:37 PM PDT 24
Peak memory 212000 kb
Host smart-b33566b3-aed7-4a9c-9aaa-dd4909397802
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017406610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1017406610
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2129807551
Short name T1
Test name
Test status
Simulation time 349586603 ps
CPU time 4.35 seconds
Started Jul 31 05:34:30 PM PDT 24
Finished Jul 31 05:34:35 PM PDT 24
Peak memory 211976 kb
Host smart-26ad0fb1-35ff-4c50-a38b-deb580490a28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129807551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2129807551
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3415757030
Short name T236
Test name
Test status
Simulation time 3972770876 ps
CPU time 153.69 seconds
Started Jul 31 05:34:28 PM PDT 24
Finished Jul 31 05:37:02 PM PDT 24
Peak memory 239964 kb
Host smart-b71ec560-9900-4883-a776-566bec493ad6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415757030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3415757030
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2058801891
Short name T139
Test name
Test status
Simulation time 352012456 ps
CPU time 9.7 seconds
Started Jul 31 05:34:33 PM PDT 24
Finished Jul 31 05:34:43 PM PDT 24
Peak memory 212932 kb
Host smart-16244ae3-79f5-4112-9e2f-03e02fb00742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058801891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2058801891
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2849363027
Short name T267
Test name
Test status
Simulation time 137043952 ps
CPU time 6.43 seconds
Started Jul 31 05:34:31 PM PDT 24
Finished Jul 31 05:34:37 PM PDT 24
Peak memory 212136 kb
Host smart-2e0bc50a-297f-4c0e-87c9-0698fbf9e4f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2849363027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2849363027
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2040391179
Short name T201
Test name
Test status
Simulation time 114344925 ps
CPU time 8.65 seconds
Started Jul 31 05:34:31 PM PDT 24
Finished Jul 31 05:34:40 PM PDT 24
Peak memory 212084 kb
Host smart-5eb0a0ce-0a69-4272-b783-5952b645e040
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040391179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2040391179
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.486404382
Short name T173
Test name
Test status
Simulation time 519949002 ps
CPU time 5.4 seconds
Started Jul 31 05:34:29 PM PDT 24
Finished Jul 31 05:34:34 PM PDT 24
Peak memory 212052 kb
Host smart-17247bf0-7c6d-419b-aa27-c4cb6c347660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486404382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.486404382
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1901178995
Short name T214
Test name
Test status
Simulation time 10713435113 ps
CPU time 134.57 seconds
Started Jul 31 05:34:29 PM PDT 24
Finished Jul 31 05:36:44 PM PDT 24
Peak memory 235848 kb
Host smart-649646bb-68c2-47b0-9344-f955ab9ddb41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901178995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1901178995
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3653135590
Short name T219
Test name
Test status
Simulation time 1001057883 ps
CPU time 11.11 seconds
Started Jul 31 05:34:31 PM PDT 24
Finished Jul 31 05:34:42 PM PDT 24
Peak memory 212928 kb
Host smart-1a3ac56a-1ad8-4b41-b02c-88fec51cbc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653135590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3653135590
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.964162989
Short name T161
Test name
Test status
Simulation time 381584096 ps
CPU time 5.92 seconds
Started Jul 31 05:34:31 PM PDT 24
Finished Jul 31 05:34:37 PM PDT 24
Peak memory 212160 kb
Host smart-492036a9-c40b-43fc-8e5b-4233e12df7b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=964162989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.964162989
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.631046472
Short name T53
Test name
Test status
Simulation time 14418684870 ps
CPU time 6045.92 seconds
Started Jul 31 05:34:31 PM PDT 24
Finished Jul 31 07:15:17 PM PDT 24
Peak memory 224764 kb
Host smart-d7ce7f13-0177-49c4-8bc3-9722ea600b38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631046472 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.631046472
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2478557181
Short name T141
Test name
Test status
Simulation time 147333282 ps
CPU time 5.18 seconds
Started Jul 31 05:34:29 PM PDT 24
Finished Jul 31 05:34:34 PM PDT 24
Peak memory 212080 kb
Host smart-87f40a35-faf5-4b50-93d0-5d7f570d6477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478557181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2478557181
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.668725436
Short name T268
Test name
Test status
Simulation time 17146001909 ps
CPU time 217.86 seconds
Started Jul 31 05:34:31 PM PDT 24
Finished Jul 31 05:38:09 PM PDT 24
Peak memory 238444 kb
Host smart-429c8980-838a-4d5d-9dd6-497be0981084
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668725436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.668725436
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3473070475
Short name T243
Test name
Test status
Simulation time 261083743 ps
CPU time 11.09 seconds
Started Jul 31 05:34:32 PM PDT 24
Finished Jul 31 05:34:43 PM PDT 24
Peak memory 212900 kb
Host smart-306208b6-767c-4eba-8bda-79781b5d372f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473070475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3473070475
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1954106121
Short name T273
Test name
Test status
Simulation time 340259061 ps
CPU time 6.18 seconds
Started Jul 31 05:34:33 PM PDT 24
Finished Jul 31 05:34:40 PM PDT 24
Peak memory 212188 kb
Host smart-758c3be1-4127-4f75-9d05-842107df82b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1954106121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1954106121
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1051131583
Short name T212
Test name
Test status
Simulation time 1230887692 ps
CPU time 14.06 seconds
Started Jul 31 05:34:31 PM PDT 24
Finished Jul 31 05:34:45 PM PDT 24
Peak memory 214528 kb
Host smart-9fc13ca3-5e3e-4cd0-bfcf-6607adc9000b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051131583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1051131583
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.612105171
Short name T30
Test name
Test status
Simulation time 135083207 ps
CPU time 5.15 seconds
Started Jul 31 05:34:30 PM PDT 24
Finished Jul 31 05:34:35 PM PDT 24
Peak memory 212064 kb
Host smart-6ac7decf-9ff5-41d7-854b-cfbafdcb77a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612105171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.612105171
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.109285035
Short name T207
Test name
Test status
Simulation time 225240830 ps
CPU time 9.54 seconds
Started Jul 31 05:34:31 PM PDT 24
Finished Jul 31 05:34:40 PM PDT 24
Peak memory 213032 kb
Host smart-31f5c78f-547e-44bc-977e-40ecc8e74167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109285035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.109285035
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2017045747
Short name T114
Test name
Test status
Simulation time 199487159 ps
CPU time 6.78 seconds
Started Jul 31 05:34:30 PM PDT 24
Finished Jul 31 05:34:37 PM PDT 24
Peak memory 212192 kb
Host smart-87a0da1c-5d06-4876-8554-6e47371f1498
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2017045747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2017045747
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3217803902
Short name T75
Test name
Test status
Simulation time 293407448 ps
CPU time 15.95 seconds
Started Jul 31 05:34:33 PM PDT 24
Finished Jul 31 05:34:49 PM PDT 24
Peak memory 213264 kb
Host smart-49609f2a-a07e-4772-9e78-9061ec67b90f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217803902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3217803902
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1918704991
Short name T326
Test name
Test status
Simulation time 518604568 ps
CPU time 5.21 seconds
Started Jul 31 05:34:38 PM PDT 24
Finished Jul 31 05:34:43 PM PDT 24
Peak memory 212008 kb
Host smart-5e61223e-ca6d-4486-82a6-8b737ce7a06b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918704991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1918704991
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1778424256
Short name T197
Test name
Test status
Simulation time 9668521850 ps
CPU time 132.49 seconds
Started Jul 31 05:34:34 PM PDT 24
Finished Jul 31 05:36:46 PM PDT 24
Peak memory 234848 kb
Host smart-30454025-7852-4c45-ab83-463b187dc7ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778424256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1778424256
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1974066647
Short name T119
Test name
Test status
Simulation time 259993379 ps
CPU time 10.97 seconds
Started Jul 31 05:34:46 PM PDT 24
Finished Jul 31 05:34:57 PM PDT 24
Peak memory 212908 kb
Host smart-0dc7a9b1-6f53-4fae-bc1f-1601ccfa69f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974066647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1974066647
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2001051021
Short name T285
Test name
Test status
Simulation time 140181425 ps
CPU time 6.3 seconds
Started Jul 31 05:34:36 PM PDT 24
Finished Jul 31 05:34:42 PM PDT 24
Peak memory 212156 kb
Host smart-3cd5d3dd-f52a-46ed-bb50-f767337d4a6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2001051021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2001051021
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.633219509
Short name T209
Test name
Test status
Simulation time 283315568 ps
CPU time 16.06 seconds
Started Jul 31 05:34:38 PM PDT 24
Finished Jul 31 05:34:54 PM PDT 24
Peak memory 215692 kb
Host smart-79849a8f-ea49-4fbc-aecf-6333887b19c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633219509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.633219509
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.4277230892
Short name T198
Test name
Test status
Simulation time 33127607366 ps
CPU time 2384.68 seconds
Started Jul 31 05:34:35 PM PDT 24
Finished Jul 31 06:14:20 PM PDT 24
Peak memory 236648 kb
Host smart-60b21541-e32b-4e23-9c6f-d299a8da530b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277230892 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.4277230892
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3207330508
Short name T134
Test name
Test status
Simulation time 126511942 ps
CPU time 5.22 seconds
Started Jul 31 05:34:12 PM PDT 24
Finished Jul 31 05:34:18 PM PDT 24
Peak memory 211960 kb
Host smart-8008f4d3-8ff4-4a4f-88a2-ef4a007b1422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207330508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3207330508
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2222408971
Short name T318
Test name
Test status
Simulation time 5186959585 ps
CPU time 117.72 seconds
Started Jul 31 05:34:10 PM PDT 24
Finished Jul 31 05:36:08 PM PDT 24
Peak memory 238416 kb
Host smart-45789efe-eb00-498a-856b-4911f60106ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222408971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2222408971
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3776651335
Short name T224
Test name
Test status
Simulation time 758085297 ps
CPU time 9.78 seconds
Started Jul 31 05:34:09 PM PDT 24
Finished Jul 31 05:34:18 PM PDT 24
Peak memory 212888 kb
Host smart-9df91388-f09c-404f-882e-178968636851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776651335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3776651335
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4094824090
Short name T234
Test name
Test status
Simulation time 101146179 ps
CPU time 6 seconds
Started Jul 31 05:34:10 PM PDT 24
Finished Jul 31 05:34:16 PM PDT 24
Peak memory 212172 kb
Host smart-875d910b-aa89-4435-b1ca-b16b6b1daf86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4094824090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.4094824090
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.336890599
Short name T135
Test name
Test status
Simulation time 1776775369 ps
CPU time 8.99 seconds
Started Jul 31 05:34:10 PM PDT 24
Finished Jul 31 05:34:20 PM PDT 24
Peak memory 212168 kb
Host smart-c68a74d0-335a-4c3a-b94f-546818d5289c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336890599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.336890599
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1071634606
Short name T228
Test name
Test status
Simulation time 225951324 ps
CPU time 14.24 seconds
Started Jul 31 05:34:13 PM PDT 24
Finished Jul 31 05:34:27 PM PDT 24
Peak memory 214588 kb
Host smart-6a633eee-2b5c-4649-bff6-664d5fe01396
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071634606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1071634606
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.4234398379
Short name T297
Test name
Test status
Simulation time 334826193 ps
CPU time 4.29 seconds
Started Jul 31 05:34:36 PM PDT 24
Finished Jul 31 05:34:40 PM PDT 24
Peak memory 212076 kb
Host smart-184387c9-a045-4dc8-94f5-03c0255731e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234398379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.4234398379
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3405431717
Short name T245
Test name
Test status
Simulation time 3373078392 ps
CPU time 102.26 seconds
Started Jul 31 05:34:38 PM PDT 24
Finished Jul 31 05:36:20 PM PDT 24
Peak memory 214468 kb
Host smart-a41b9c9c-e44d-41e6-92c4-d2bd1151b6c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405431717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3405431717
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2367005768
Short name T270
Test name
Test status
Simulation time 143103645 ps
CPU time 6.45 seconds
Started Jul 31 05:34:36 PM PDT 24
Finished Jul 31 05:34:43 PM PDT 24
Peak memory 212064 kb
Host smart-3aa69a4d-b4f0-47fc-96b3-2ff4e2ea815c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2367005768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2367005768
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.547750789
Short name T14
Test name
Test status
Simulation time 419853521 ps
CPU time 12.5 seconds
Started Jul 31 05:34:34 PM PDT 24
Finished Jul 31 05:34:47 PM PDT 24
Peak memory 214964 kb
Host smart-5eb63803-cc9b-47be-ae35-be1030dcd787
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547750789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.547750789
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.312551484
Short name T257
Test name
Test status
Simulation time 75842614726 ps
CPU time 1170.09 seconds
Started Jul 31 05:34:45 PM PDT 24
Finished Jul 31 05:54:16 PM PDT 24
Peak memory 229068 kb
Host smart-980ebd0c-68c3-4713-84ec-c4f6ca303540
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312551484 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.312551484
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3704309001
Short name T206
Test name
Test status
Simulation time 261551883 ps
CPU time 5.02 seconds
Started Jul 31 05:34:45 PM PDT 24
Finished Jul 31 05:34:51 PM PDT 24
Peak memory 212048 kb
Host smart-d4f80768-8d88-46f6-aa51-2835b407c0fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704309001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3704309001
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2265513067
Short name T291
Test name
Test status
Simulation time 53321642720 ps
CPU time 136.32 seconds
Started Jul 31 05:34:35 PM PDT 24
Finished Jul 31 05:36:51 PM PDT 24
Peak memory 238428 kb
Host smart-87e5d08d-a364-4376-9a0d-dc07b36d2382
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265513067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2265513067
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1866305691
Short name T43
Test name
Test status
Simulation time 170861108 ps
CPU time 9.29 seconds
Started Jul 31 05:34:46 PM PDT 24
Finished Jul 31 05:34:55 PM PDT 24
Peak memory 213052 kb
Host smart-ad7d0c09-7658-4808-bdb3-503bc34cc5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866305691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1866305691
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.615206513
Short name T288
Test name
Test status
Simulation time 358622526 ps
CPU time 5.64 seconds
Started Jul 31 05:34:36 PM PDT 24
Finished Jul 31 05:34:42 PM PDT 24
Peak memory 212156 kb
Host smart-9601bea5-50f3-4182-9b43-676b3f9cbdb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=615206513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.615206513
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.926370528
Short name T61
Test name
Test status
Simulation time 782683995 ps
CPU time 11.8 seconds
Started Jul 31 05:34:35 PM PDT 24
Finished Jul 31 05:34:47 PM PDT 24
Peak memory 212460 kb
Host smart-de3faaeb-636e-46e0-9b62-1a3e86966a99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926370528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.926370528
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1403280375
Short name T60
Test name
Test status
Simulation time 522329581 ps
CPU time 4.22 seconds
Started Jul 31 05:34:42 PM PDT 24
Finished Jul 31 05:34:46 PM PDT 24
Peak memory 211932 kb
Host smart-afc87de9-fe08-4ae3-8150-237f807db2c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403280375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1403280375
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2006394907
Short name T41
Test name
Test status
Simulation time 1184989932 ps
CPU time 72.39 seconds
Started Jul 31 05:34:36 PM PDT 24
Finished Jul 31 05:35:49 PM PDT 24
Peak memory 237632 kb
Host smart-d33978cb-af05-412e-827a-99a1e0d6c66d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006394907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2006394907
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2416057257
Short name T293
Test name
Test status
Simulation time 262485585 ps
CPU time 10.84 seconds
Started Jul 31 05:34:45 PM PDT 24
Finished Jul 31 05:34:56 PM PDT 24
Peak memory 212932 kb
Host smart-f44b00e6-bc16-49b2-806d-5aaf3c396adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416057257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2416057257
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2021582236
Short name T5
Test name
Test status
Simulation time 153921201 ps
CPU time 6.22 seconds
Started Jul 31 05:34:38 PM PDT 24
Finished Jul 31 05:34:44 PM PDT 24
Peak memory 212140 kb
Host smart-9f383781-ce74-454d-9973-89e04b1635b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2021582236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2021582236
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1791574421
Short name T313
Test name
Test status
Simulation time 251120461 ps
CPU time 7.89 seconds
Started Jul 31 05:34:45 PM PDT 24
Finished Jul 31 05:34:53 PM PDT 24
Peak memory 212108 kb
Host smart-a3a7496b-cb88-4718-8548-fbc9e72cb917
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791574421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1791574421
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2600682993
Short name T9
Test name
Test status
Simulation time 15491509902 ps
CPU time 4941.85 seconds
Started Jul 31 05:34:39 PM PDT 24
Finished Jul 31 06:57:01 PM PDT 24
Peak memory 228484 kb
Host smart-3d18ce98-35c3-40ca-94d2-0954e411bb5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600682993 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2600682993
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.533110743
Short name T170
Test name
Test status
Simulation time 273228590 ps
CPU time 4.98 seconds
Started Jul 31 05:34:43 PM PDT 24
Finished Jul 31 05:34:48 PM PDT 24
Peak memory 212080 kb
Host smart-c73e5a95-e19d-42d6-8dd0-389c61edc643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533110743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.533110743
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.936563716
Short name T153
Test name
Test status
Simulation time 1775866294 ps
CPU time 81.14 seconds
Started Jul 31 05:34:42 PM PDT 24
Finished Jul 31 05:36:04 PM PDT 24
Peak memory 228120 kb
Host smart-3274364d-43f8-4e56-a904-85c875e3b561
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936563716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.936563716
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2793335303
Short name T147
Test name
Test status
Simulation time 917555558 ps
CPU time 10.84 seconds
Started Jul 31 05:34:47 PM PDT 24
Finished Jul 31 05:34:58 PM PDT 24
Peak memory 212180 kb
Host smart-885752b1-d9ab-4815-ab40-7f842acf6269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793335303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2793335303
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1937270037
Short name T151
Test name
Test status
Simulation time 253562111 ps
CPU time 5.36 seconds
Started Jul 31 05:34:40 PM PDT 24
Finished Jul 31 05:34:45 PM PDT 24
Peak memory 212148 kb
Host smart-489825a7-d4c7-4287-903e-f6fbff73b9ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1937270037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1937270037
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.81364333
Short name T80
Test name
Test status
Simulation time 311449497 ps
CPU time 13.67 seconds
Started Jul 31 05:34:40 PM PDT 24
Finished Jul 31 05:34:54 PM PDT 24
Peak memory 213272 kb
Host smart-a648f90c-1738-4e57-a46c-211f30e3ed79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81364333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 23.rom_ctrl_stress_all.81364333
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.439622408
Short name T225
Test name
Test status
Simulation time 207468032415 ps
CPU time 2091.66 seconds
Started Jul 31 05:34:40 PM PDT 24
Finished Jul 31 06:09:32 PM PDT 24
Peak memory 247728 kb
Host smart-758a0d88-181f-4eb4-a87b-0616b034d46c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439622408 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.439622408
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.473101250
Short name T271
Test name
Test status
Simulation time 594289418 ps
CPU time 5.23 seconds
Started Jul 31 05:34:38 PM PDT 24
Finished Jul 31 05:34:43 PM PDT 24
Peak memory 212056 kb
Host smart-33a8cdde-87d7-470d-83a0-e72727f05f83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473101250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.473101250
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2333481631
Short name T40
Test name
Test status
Simulation time 1870764381 ps
CPU time 101.73 seconds
Started Jul 31 05:34:42 PM PDT 24
Finished Jul 31 05:36:24 PM PDT 24
Peak memory 237324 kb
Host smart-fe99e23f-4b15-4f33-9934-d9b8df27446d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333481631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2333481631
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.303593002
Short name T249
Test name
Test status
Simulation time 507203203 ps
CPU time 11.21 seconds
Started Jul 31 05:34:42 PM PDT 24
Finished Jul 31 05:34:54 PM PDT 24
Peak memory 212540 kb
Host smart-4e2cef11-b5e4-40bb-a23d-b0faddb3f489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303593002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.303593002
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.278985174
Short name T29
Test name
Test status
Simulation time 394339332 ps
CPU time 5.64 seconds
Started Jul 31 05:34:39 PM PDT 24
Finished Jul 31 05:34:45 PM PDT 24
Peak memory 212172 kb
Host smart-3bd9b138-c721-476d-9f90-736352e68de1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=278985174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.278985174
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3333273014
Short name T328
Test name
Test status
Simulation time 825996266 ps
CPU time 13.64 seconds
Started Jul 31 05:34:41 PM PDT 24
Finished Jul 31 05:34:54 PM PDT 24
Peak memory 213052 kb
Host smart-256159b2-7c62-4f6d-a822-7f595761bb44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333273014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3333273014
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3112960417
Short name T120
Test name
Test status
Simulation time 85638449 ps
CPU time 4.32 seconds
Started Jul 31 05:34:39 PM PDT 24
Finished Jul 31 05:34:43 PM PDT 24
Peak memory 212044 kb
Host smart-176b285c-d663-42b4-8841-3f72c8dfe184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112960417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3112960417
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.4157542685
Short name T20
Test name
Test status
Simulation time 9541613809 ps
CPU time 103.03 seconds
Started Jul 31 05:34:44 PM PDT 24
Finished Jul 31 05:36:27 PM PDT 24
Peak memory 226376 kb
Host smart-56a94c81-ec36-476c-95d0-0f248e8ac53e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157542685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.4157542685
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.4139068238
Short name T307
Test name
Test status
Simulation time 520862687 ps
CPU time 11.31 seconds
Started Jul 31 05:34:39 PM PDT 24
Finished Jul 31 05:34:51 PM PDT 24
Peak memory 212848 kb
Host smart-a0e205ee-87d8-44f2-996c-014afd0efa29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139068238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.4139068238
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2050327531
Short name T312
Test name
Test status
Simulation time 361305058 ps
CPU time 5.49 seconds
Started Jul 31 05:34:40 PM PDT 24
Finished Jul 31 05:34:45 PM PDT 24
Peak memory 212180 kb
Host smart-30276bc7-d971-429b-8902-bb48cf45143d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2050327531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2050327531
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.4036995955
Short name T250
Test name
Test status
Simulation time 261700851 ps
CPU time 14.04 seconds
Started Jul 31 05:34:42 PM PDT 24
Finished Jul 31 05:34:56 PM PDT 24
Peak memory 212084 kb
Host smart-066445e3-ea62-4cda-ab34-c9b565cfefcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036995955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.4036995955
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1577175486
Short name T295
Test name
Test status
Simulation time 88909487 ps
CPU time 4.36 seconds
Started Jul 31 05:34:39 PM PDT 24
Finished Jul 31 05:34:43 PM PDT 24
Peak memory 212032 kb
Host smart-61bea8c9-052a-49d7-a922-cbbb8cdcbb3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577175486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1577175486
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2220683837
Short name T303
Test name
Test status
Simulation time 13779963912 ps
CPU time 131.26 seconds
Started Jul 31 05:34:40 PM PDT 24
Finished Jul 31 05:36:51 PM PDT 24
Peak memory 239496 kb
Host smart-4ac9031f-d85b-41a7-9aa6-db83ff3420f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220683837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2220683837
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1044127897
Short name T216
Test name
Test status
Simulation time 520925339 ps
CPU time 11.19 seconds
Started Jul 31 05:34:42 PM PDT 24
Finished Jul 31 05:34:54 PM PDT 24
Peak memory 212840 kb
Host smart-ce7b2615-55d3-45b7-bc0f-03c448c5b0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044127897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1044127897
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1686479728
Short name T284
Test name
Test status
Simulation time 139447377 ps
CPU time 6.39 seconds
Started Jul 31 05:34:39 PM PDT 24
Finished Jul 31 05:34:45 PM PDT 24
Peak memory 212180 kb
Host smart-a95c6d1c-3f01-4b99-8f0e-6dd580e188db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1686479728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1686479728
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.424470629
Short name T18
Test name
Test status
Simulation time 1514887433 ps
CPU time 23.89 seconds
Started Jul 31 05:34:44 PM PDT 24
Finished Jul 31 05:35:08 PM PDT 24
Peak memory 216972 kb
Host smart-94280864-0229-422d-9bca-819f1f00c472
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424470629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.424470629
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.262637073
Short name T325
Test name
Test status
Simulation time 128584847573 ps
CPU time 2669.74 seconds
Started Jul 31 05:34:38 PM PDT 24
Finished Jul 31 06:19:08 PM PDT 24
Peak memory 244896 kb
Host smart-f6d24a63-bee6-4666-8e62-a55728f37594
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262637073 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.262637073
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2178453988
Short name T200
Test name
Test status
Simulation time 160161864 ps
CPU time 4.33 seconds
Started Jul 31 05:34:42 PM PDT 24
Finished Jul 31 05:34:47 PM PDT 24
Peak memory 212012 kb
Host smart-f2f0335e-10cd-4c9c-9123-e4b7758abe5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178453988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2178453988
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.254660567
Short name T218
Test name
Test status
Simulation time 7931809885 ps
CPU time 142.43 seconds
Started Jul 31 05:34:40 PM PDT 24
Finished Jul 31 05:37:03 PM PDT 24
Peak memory 233704 kb
Host smart-08148a48-42e0-41bf-8dc0-2200ab5bd900
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254660567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.254660567
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3289797054
Short name T2
Test name
Test status
Simulation time 512466393 ps
CPU time 11.33 seconds
Started Jul 31 05:34:43 PM PDT 24
Finished Jul 31 05:34:55 PM PDT 24
Peak memory 213368 kb
Host smart-2e8f6593-d774-4345-8ba1-26f5b156f54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289797054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3289797054
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2934224824
Short name T246
Test name
Test status
Simulation time 196946214 ps
CPU time 5.48 seconds
Started Jul 31 05:34:40 PM PDT 24
Finished Jul 31 05:34:46 PM PDT 24
Peak memory 212120 kb
Host smart-63b53a89-fe3d-4349-80d5-2848298bb7de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2934224824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2934224824
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.4167004310
Short name T79
Test name
Test status
Simulation time 624706005 ps
CPU time 9.2 seconds
Started Jul 31 05:34:41 PM PDT 24
Finished Jul 31 05:34:51 PM PDT 24
Peak memory 212316 kb
Host smart-f218ded2-4d15-4686-882a-e8eafb9a45a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167004310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.4167004310
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.653484493
Short name T251
Test name
Test status
Simulation time 33097015532 ps
CPU time 369.3 seconds
Started Jul 31 05:34:40 PM PDT 24
Finished Jul 31 05:40:49 PM PDT 24
Peak memory 234160 kb
Host smart-1cb23961-0bf5-4d76-a39d-a3fda5ec58c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653484493 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.653484493
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3993201295
Short name T237
Test name
Test status
Simulation time 1831787872 ps
CPU time 7.78 seconds
Started Jul 31 05:34:43 PM PDT 24
Finished Jul 31 05:34:51 PM PDT 24
Peak memory 212032 kb
Host smart-e8f347d7-ae4b-4123-946d-6975a715be90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993201295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3993201295
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1208547548
Short name T238
Test name
Test status
Simulation time 2694852419 ps
CPU time 150.47 seconds
Started Jul 31 05:34:43 PM PDT 24
Finished Jul 31 05:37:14 PM PDT 24
Peak memory 225244 kb
Host smart-d693c89d-0d1f-4c0a-bf15-a49c0105c1d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208547548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1208547548
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.608335320
Short name T304
Test name
Test status
Simulation time 999482317 ps
CPU time 11.23 seconds
Started Jul 31 05:34:42 PM PDT 24
Finished Jul 31 05:34:54 PM PDT 24
Peak memory 212220 kb
Host smart-695412c3-434f-4c0d-a4bb-a095fd0a5808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608335320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.608335320
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2054569669
Short name T182
Test name
Test status
Simulation time 140421254 ps
CPU time 6.48 seconds
Started Jul 31 05:34:43 PM PDT 24
Finished Jul 31 05:34:50 PM PDT 24
Peak memory 212184 kb
Host smart-7c343f0f-26e5-46f1-8e13-43dbc1e57ef7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2054569669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2054569669
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3947286966
Short name T277
Test name
Test status
Simulation time 281297985 ps
CPU time 14.69 seconds
Started Jul 31 05:34:42 PM PDT 24
Finished Jul 31 05:34:57 PM PDT 24
Peak memory 214904 kb
Host smart-5ed74618-30b6-4bc4-93e7-bac3ae1145ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947286966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3947286966
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.592764589
Short name T210
Test name
Test status
Simulation time 525350230590 ps
CPU time 2528.79 seconds
Started Jul 31 05:34:44 PM PDT 24
Finished Jul 31 06:16:53 PM PDT 24
Peak memory 240068 kb
Host smart-b31db6af-2ae3-4b65-87ce-5c8b938599df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592764589 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.592764589
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1008522944
Short name T296
Test name
Test status
Simulation time 90043582 ps
CPU time 4.37 seconds
Started Jul 31 05:34:45 PM PDT 24
Finished Jul 31 05:34:49 PM PDT 24
Peak memory 212052 kb
Host smart-419e4871-9691-485c-8e2d-248f01dbe500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008522944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1008522944
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2416496444
Short name T174
Test name
Test status
Simulation time 973986953 ps
CPU time 65.05 seconds
Started Jul 31 05:34:44 PM PDT 24
Finished Jul 31 05:35:49 PM PDT 24
Peak memory 236988 kb
Host smart-60938bd4-bd8e-4c68-98ed-ac926cbcb571
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416496444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2416496444
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3528304139
Short name T6
Test name
Test status
Simulation time 257020279 ps
CPU time 10.98 seconds
Started Jul 31 05:34:45 PM PDT 24
Finished Jul 31 05:34:56 PM PDT 24
Peak memory 212876 kb
Host smart-8cdd4239-2108-4314-9fe2-ae1cf7f027e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528304139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3528304139
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2311044663
Short name T203
Test name
Test status
Simulation time 137766609 ps
CPU time 6.55 seconds
Started Jul 31 05:34:44 PM PDT 24
Finished Jul 31 05:34:51 PM PDT 24
Peak memory 212144 kb
Host smart-11135bb4-a95c-4285-9a61-25dbfc1b5996
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2311044663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2311044663
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3689337619
Short name T78
Test name
Test status
Simulation time 284562293 ps
CPU time 12.68 seconds
Started Jul 31 05:34:40 PM PDT 24
Finished Jul 31 05:34:52 PM PDT 24
Peak memory 214780 kb
Host smart-86aecbf8-05f5-4567-8765-388b466aeda7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689337619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3689337619
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2692358621
Short name T33
Test name
Test status
Simulation time 105935935987 ps
CPU time 769.76 seconds
Started Jul 31 05:34:45 PM PDT 24
Finished Jul 31 05:47:35 PM PDT 24
Peak memory 236676 kb
Host smart-8a3b11c4-a24b-49e2-b7ec-a9ab40f41b0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692358621 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.2692358621
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1965867256
Short name T117
Test name
Test status
Simulation time 336620369 ps
CPU time 4.33 seconds
Started Jul 31 05:34:15 PM PDT 24
Finished Jul 31 05:34:20 PM PDT 24
Peak memory 212024 kb
Host smart-1741bddf-d7f2-4edb-86f4-998a17c1cc43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965867256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1965867256
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3709057074
Short name T42
Test name
Test status
Simulation time 10907021025 ps
CPU time 87.27 seconds
Started Jul 31 05:34:17 PM PDT 24
Finished Jul 31 05:35:44 PM PDT 24
Peak memory 229256 kb
Host smart-cd2caa94-5ade-49b4-9e8f-18b79bbd7acd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709057074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3709057074
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.848220242
Short name T264
Test name
Test status
Simulation time 176895116 ps
CPU time 9.98 seconds
Started Jul 31 05:34:14 PM PDT 24
Finished Jul 31 05:34:24 PM PDT 24
Peak memory 213012 kb
Host smart-ffef7213-7cf1-4cf9-a1b0-4f63e92ec2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848220242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.848220242
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3622314615
Short name T99
Test name
Test status
Simulation time 504802106 ps
CPU time 9.12 seconds
Started Jul 31 05:34:16 PM PDT 24
Finished Jul 31 05:34:25 PM PDT 24
Peak memory 212064 kb
Host smart-be0482bd-2c57-42c8-a6e8-5d6b431ee17b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3622314615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3622314615
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1425595814
Short name T24
Test name
Test status
Simulation time 638238051 ps
CPU time 52.57 seconds
Started Jul 31 05:34:14 PM PDT 24
Finished Jul 31 05:35:07 PM PDT 24
Peak memory 237368 kb
Host smart-26ba08fe-aad2-46bd-a44c-07eae19f76cd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425595814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1425595814
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.222318709
Short name T148
Test name
Test status
Simulation time 120048133 ps
CPU time 5.77 seconds
Started Jul 31 05:34:09 PM PDT 24
Finished Jul 31 05:34:14 PM PDT 24
Peak memory 212152 kb
Host smart-0c3b9ffd-f18f-44ba-8a54-fab19d7283c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222318709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.222318709
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3039979592
Short name T199
Test name
Test status
Simulation time 290914280 ps
CPU time 14.76 seconds
Started Jul 31 05:34:08 PM PDT 24
Finished Jul 31 05:34:23 PM PDT 24
Peak memory 215492 kb
Host smart-c18f9ee5-24d0-444b-862a-cdb0a386f64d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039979592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3039979592
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.333409344
Short name T50
Test name
Test status
Simulation time 52885923320 ps
CPU time 2108.44 seconds
Started Jul 31 05:34:15 PM PDT 24
Finished Jul 31 06:09:24 PM PDT 24
Peak memory 236656 kb
Host smart-a6423af8-d9a5-4ab3-b233-60e4034bc2d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333409344 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.333409344
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.619730767
Short name T215
Test name
Test status
Simulation time 520715191 ps
CPU time 5.12 seconds
Started Jul 31 05:34:45 PM PDT 24
Finished Jul 31 05:34:50 PM PDT 24
Peak memory 212080 kb
Host smart-4047f808-b062-4a26-bf67-bd5762248fb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619730767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.619730767
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.650221070
Short name T39
Test name
Test status
Simulation time 9240839914 ps
CPU time 128.79 seconds
Started Jul 31 05:34:47 PM PDT 24
Finished Jul 31 05:36:56 PM PDT 24
Peak memory 213392 kb
Host smart-7725ec75-9d7f-4666-acfa-b26f81d3cf9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650221070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.650221070
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4108314271
Short name T205
Test name
Test status
Simulation time 1130286249 ps
CPU time 11.16 seconds
Started Jul 31 05:34:44 PM PDT 24
Finished Jul 31 05:34:56 PM PDT 24
Peak memory 212928 kb
Host smart-2b274506-b90b-48de-8ac8-478f7b131294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108314271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4108314271
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3258005619
Short name T136
Test name
Test status
Simulation time 765772069 ps
CPU time 5.58 seconds
Started Jul 31 05:34:45 PM PDT 24
Finished Jul 31 05:34:51 PM PDT 24
Peak memory 212144 kb
Host smart-5a0d69f9-9c01-4f5e-8588-88a018f635f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3258005619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3258005619
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.4145380503
Short name T272
Test name
Test status
Simulation time 1602919523 ps
CPU time 19 seconds
Started Jul 31 05:34:47 PM PDT 24
Finished Jul 31 05:35:06 PM PDT 24
Peak memory 215036 kb
Host smart-1597ee8f-4a5e-48a3-8998-5a9e7c1a945e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145380503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.4145380503
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2214274865
Short name T227
Test name
Test status
Simulation time 131251377 ps
CPU time 5.22 seconds
Started Jul 31 05:34:45 PM PDT 24
Finished Jul 31 05:34:50 PM PDT 24
Peak memory 212064 kb
Host smart-f511e6bd-00af-41f8-8c80-586439dd39aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214274865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2214274865
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.188152399
Short name T123
Test name
Test status
Simulation time 5695115148 ps
CPU time 97.97 seconds
Started Jul 31 05:34:45 PM PDT 24
Finished Jul 31 05:36:23 PM PDT 24
Peak memory 226240 kb
Host smart-ead94bf5-322f-49aa-9758-82d1307ccc40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188152399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.188152399
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3804644176
Short name T315
Test name
Test status
Simulation time 2081083868 ps
CPU time 9.7 seconds
Started Jul 31 05:34:45 PM PDT 24
Finished Jul 31 05:34:55 PM PDT 24
Peak memory 212908 kb
Host smart-82dca934-4150-43df-8d6d-2674f6df0591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804644176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3804644176
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3404518117
Short name T280
Test name
Test status
Simulation time 192790948 ps
CPU time 5.65 seconds
Started Jul 31 05:34:44 PM PDT 24
Finished Jul 31 05:34:50 PM PDT 24
Peak memory 212152 kb
Host smart-4032f797-a513-41b6-ad30-f77edc197c3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3404518117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3404518117
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2804138832
Short name T232
Test name
Test status
Simulation time 146880074 ps
CPU time 9.54 seconds
Started Jul 31 05:34:45 PM PDT 24
Finished Jul 31 05:34:55 PM PDT 24
Peak memory 212108 kb
Host smart-1471a769-c74b-4faf-9dd7-479923a7f1b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804138832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2804138832
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2662072011
Short name T126
Test name
Test status
Simulation time 117319140 ps
CPU time 4.15 seconds
Started Jul 31 05:34:45 PM PDT 24
Finished Jul 31 05:34:49 PM PDT 24
Peak memory 212060 kb
Host smart-e54b3b44-5a2d-4e0d-aed9-17feb5ced131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662072011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2662072011
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1175177821
Short name T38
Test name
Test status
Simulation time 57945874268 ps
CPU time 169.54 seconds
Started Jul 31 05:34:45 PM PDT 24
Finished Jul 31 05:37:35 PM PDT 24
Peak memory 226592 kb
Host smart-392c9fec-c52d-4e59-9d0d-adc1809b0ee6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175177821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1175177821
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.682451978
Short name T195
Test name
Test status
Simulation time 251578715 ps
CPU time 10.83 seconds
Started Jul 31 05:34:43 PM PDT 24
Finished Jul 31 05:34:54 PM PDT 24
Peak memory 213104 kb
Host smart-5e141b77-e6de-42e1-a512-bdfc888f02c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682451978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.682451978
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3703064648
Short name T190
Test name
Test status
Simulation time 191090319 ps
CPU time 5.59 seconds
Started Jul 31 05:34:47 PM PDT 24
Finished Jul 31 05:34:53 PM PDT 24
Peak memory 212136 kb
Host smart-d5397d34-2007-4ddc-90b1-bd07cf5be193
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3703064648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3703064648
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2272196264
Short name T131
Test name
Test status
Simulation time 699125399 ps
CPU time 11.86 seconds
Started Jul 31 05:34:47 PM PDT 24
Finished Jul 31 05:34:59 PM PDT 24
Peak memory 212372 kb
Host smart-f6593883-7d0d-4733-99c1-83078a2de965
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272196264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2272196264
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2510721452
Short name T11
Test name
Test status
Simulation time 64911636474 ps
CPU time 697.43 seconds
Started Jul 31 05:34:45 PM PDT 24
Finished Jul 31 05:46:23 PM PDT 24
Peak memory 231072 kb
Host smart-549d1d7d-8525-4f8f-b34f-2e5735eccc27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510721452 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.2510721452
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.4111446635
Short name T208
Test name
Test status
Simulation time 96927150 ps
CPU time 4.37 seconds
Started Jul 31 05:34:45 PM PDT 24
Finished Jul 31 05:34:50 PM PDT 24
Peak memory 211976 kb
Host smart-44c48d6d-c7b3-421b-90b1-19ce6d4559c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111446635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.4111446635
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.53047771
Short name T278
Test name
Test status
Simulation time 7431380016 ps
CPU time 108.81 seconds
Started Jul 31 05:34:45 PM PDT 24
Finished Jul 31 05:36:34 PM PDT 24
Peak memory 238296 kb
Host smart-3a4ea14c-d7cd-4673-afb3-aa2b5c8179eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53047771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_co
rrupt_sig_fatal_chk.53047771
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1712111752
Short name T49
Test name
Test status
Simulation time 176427010 ps
CPU time 9.75 seconds
Started Jul 31 05:34:47 PM PDT 24
Finished Jul 31 05:34:57 PM PDT 24
Peak memory 214892 kb
Host smart-3e23fb88-018e-4ec2-b9a5-595ac44340ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712111752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1712111752
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.907218132
Short name T265
Test name
Test status
Simulation time 97275811 ps
CPU time 5.55 seconds
Started Jul 31 05:34:46 PM PDT 24
Finished Jul 31 05:34:52 PM PDT 24
Peak memory 212176 kb
Host smart-6832dd78-4b7e-4880-9fc9-6b699e2ff378
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=907218132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.907218132
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1023934410
Short name T143
Test name
Test status
Simulation time 2110125208 ps
CPU time 23.97 seconds
Started Jul 31 05:34:49 PM PDT 24
Finished Jul 31 05:35:13 PM PDT 24
Peak memory 217076 kb
Host smart-c8ecc597-bb56-46c9-8796-ac146db9a1be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023934410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1023934410
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3747231316
Short name T51
Test name
Test status
Simulation time 25994907702 ps
CPU time 3496.13 seconds
Started Jul 31 05:34:49 PM PDT 24
Finished Jul 31 06:33:06 PM PDT 24
Peak memory 236696 kb
Host smart-27a9c17f-5469-4323-82f3-dc65ae5d4f99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747231316 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.3747231316
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.994326840
Short name T260
Test name
Test status
Simulation time 171949751 ps
CPU time 4.28 seconds
Started Jul 31 05:34:50 PM PDT 24
Finished Jul 31 05:34:55 PM PDT 24
Peak memory 212060 kb
Host smart-de0f62df-53c0-41eb-a8a6-ea3e1137bd16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994326840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.994326840
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3197510035
Short name T47
Test name
Test status
Simulation time 10757614569 ps
CPU time 204.43 seconds
Started Jul 31 05:34:50 PM PDT 24
Finished Jul 31 05:38:14 PM PDT 24
Peak memory 214512 kb
Host smart-9bf1313a-5b26-4884-90c3-3812b5c14d1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197510035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3197510035
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3924709006
Short name T130
Test name
Test status
Simulation time 240087515 ps
CPU time 9.52 seconds
Started Jul 31 05:34:53 PM PDT 24
Finished Jul 31 05:35:03 PM PDT 24
Peak memory 213004 kb
Host smart-b03a2b56-c86d-4470-b56c-69606db2eb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924709006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3924709006
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2137489862
Short name T121
Test name
Test status
Simulation time 328701839 ps
CPU time 5.5 seconds
Started Jul 31 05:34:50 PM PDT 24
Finished Jul 31 05:34:55 PM PDT 24
Peak memory 212180 kb
Host smart-9069b705-0ac0-4b05-8d22-9332d4257d3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2137489862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2137489862
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1164411596
Short name T253
Test name
Test status
Simulation time 2284780748 ps
CPU time 25.62 seconds
Started Jul 31 05:34:47 PM PDT 24
Finished Jul 31 05:35:13 PM PDT 24
Peak memory 216644 kb
Host smart-4e67a2fa-944d-4c6b-8f1b-bb4bf03e2864
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164411596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1164411596
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.387565462
Short name T15
Test name
Test status
Simulation time 85112590895 ps
CPU time 3469.88 seconds
Started Jul 31 05:34:50 PM PDT 24
Finished Jul 31 06:32:40 PM PDT 24
Peak memory 245592 kb
Host smart-e4c00454-44c6-4109-8542-38a1f5f893c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387565462 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.387565462
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1956432638
Short name T157
Test name
Test status
Simulation time 131104447 ps
CPU time 5.21 seconds
Started Jul 31 05:34:53 PM PDT 24
Finished Jul 31 05:34:58 PM PDT 24
Peak memory 212024 kb
Host smart-4aa6c3da-24d4-4a3b-ad1d-64cbf88de792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956432638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1956432638
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4084967899
Short name T316
Test name
Test status
Simulation time 1097723230 ps
CPU time 60.25 seconds
Started Jul 31 05:34:50 PM PDT 24
Finished Jul 31 05:35:51 PM PDT 24
Peak memory 212616 kb
Host smart-3ba65803-13e6-4294-9a2d-84e58d5074b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084967899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.4084967899
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1831458969
Short name T252
Test name
Test status
Simulation time 250770592 ps
CPU time 11.24 seconds
Started Jul 31 05:34:53 PM PDT 24
Finished Jul 31 05:35:04 PM PDT 24
Peak memory 212856 kb
Host smart-886f36db-981b-417f-bcd4-62daf0b9f266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831458969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1831458969
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2453356112
Short name T311
Test name
Test status
Simulation time 269846622 ps
CPU time 6.26 seconds
Started Jul 31 05:34:52 PM PDT 24
Finished Jul 31 05:34:58 PM PDT 24
Peak memory 212220 kb
Host smart-9ec3abf7-1ee4-4c20-9b68-418b43aa310f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2453356112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2453356112
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3077077223
Short name T292
Test name
Test status
Simulation time 286806167 ps
CPU time 13.51 seconds
Started Jul 31 05:34:51 PM PDT 24
Finished Jul 31 05:35:05 PM PDT 24
Peak memory 215200 kb
Host smart-fd3065a6-2077-46d6-ae21-0f1a9fb6aeb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077077223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3077077223
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3390119444
Short name T308
Test name
Test status
Simulation time 499461065 ps
CPU time 5.11 seconds
Started Jul 31 05:34:50 PM PDT 24
Finished Jul 31 05:34:55 PM PDT 24
Peak memory 212060 kb
Host smart-7b9da658-dbec-47bc-93fe-e0cc89401b2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390119444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3390119444
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2646225321
Short name T254
Test name
Test status
Simulation time 1819397373 ps
CPU time 78.06 seconds
Started Jul 31 05:34:53 PM PDT 24
Finished Jul 31 05:36:11 PM PDT 24
Peak memory 225208 kb
Host smart-986938b2-1954-466e-b72a-2cfc3d834e0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646225321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2646225321
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1349874239
Short name T159
Test name
Test status
Simulation time 260049596 ps
CPU time 11.29 seconds
Started Jul 31 05:34:50 PM PDT 24
Finished Jul 31 05:35:02 PM PDT 24
Peak memory 213048 kb
Host smart-46048747-4dd9-406c-a661-075ef6e91b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349874239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1349874239
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1577930821
Short name T248
Test name
Test status
Simulation time 372265817 ps
CPU time 5.55 seconds
Started Jul 31 05:34:52 PM PDT 24
Finished Jul 31 05:34:58 PM PDT 24
Peak memory 212220 kb
Host smart-1267a5b0-acb1-45cb-98ce-2e17da69a968
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1577930821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1577930821
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2160017789
Short name T240
Test name
Test status
Simulation time 120038311 ps
CPU time 7.48 seconds
Started Jul 31 05:34:51 PM PDT 24
Finished Jul 31 05:34:58 PM PDT 24
Peak memory 211992 kb
Host smart-4a93100a-9a6f-468d-9e87-a5111e20a447
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160017789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2160017789
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2666909220
Short name T64
Test name
Test status
Simulation time 565664225 ps
CPU time 5 seconds
Started Jul 31 05:34:54 PM PDT 24
Finished Jul 31 05:34:59 PM PDT 24
Peak memory 212044 kb
Host smart-0f60858f-0a0b-4e1a-be51-faee86fa5f78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666909220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2666909220
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.865626742
Short name T323
Test name
Test status
Simulation time 1863863498 ps
CPU time 119.94 seconds
Started Jul 31 05:34:58 PM PDT 24
Finished Jul 31 05:36:58 PM PDT 24
Peak memory 240172 kb
Host smart-79270c21-a5c7-4e3b-b5bf-84ee054a6916
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865626742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.865626742
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1004959668
Short name T221
Test name
Test status
Simulation time 1381093760 ps
CPU time 9.42 seconds
Started Jul 31 05:34:54 PM PDT 24
Finished Jul 31 05:35:04 PM PDT 24
Peak memory 212956 kb
Host smart-89ab7b53-86f0-4ed0-878b-117849f66cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004959668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1004959668
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2843427961
Short name T193
Test name
Test status
Simulation time 449227629 ps
CPU time 5.64 seconds
Started Jul 31 05:34:51 PM PDT 24
Finished Jul 31 05:34:57 PM PDT 24
Peak memory 212172 kb
Host smart-4817c46f-53cf-4fa1-9aa6-2e9c0a705567
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2843427961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2843427961
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2610373557
Short name T279
Test name
Test status
Simulation time 285556534 ps
CPU time 15.2 seconds
Started Jul 31 05:34:52 PM PDT 24
Finished Jul 31 05:35:08 PM PDT 24
Peak memory 212740 kb
Host smart-5a7a39ca-2342-4396-86af-b0b1fa8a6667
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610373557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2610373557
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1728795675
Short name T274
Test name
Test status
Simulation time 520653098 ps
CPU time 5.17 seconds
Started Jul 31 05:34:59 PM PDT 24
Finished Jul 31 05:35:05 PM PDT 24
Peak memory 211960 kb
Host smart-1d2cedb4-8fc6-46b8-9dba-453805e49844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728795675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1728795675
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1950196305
Short name T204
Test name
Test status
Simulation time 3523010117 ps
CPU time 117.27 seconds
Started Jul 31 05:34:55 PM PDT 24
Finished Jul 31 05:36:53 PM PDT 24
Peak memory 238464 kb
Host smart-64fa4318-d3c8-4bce-b172-5062426e38a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950196305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1950196305
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.601772001
Short name T324
Test name
Test status
Simulation time 760423916 ps
CPU time 9.57 seconds
Started Jul 31 05:35:01 PM PDT 24
Finished Jul 31 05:35:10 PM PDT 24
Peak memory 212852 kb
Host smart-0adbaeba-712a-4f23-8efb-b3ade45bbf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601772001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.601772001
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3881494796
Short name T258
Test name
Test status
Simulation time 199303839 ps
CPU time 5.8 seconds
Started Jul 31 05:34:59 PM PDT 24
Finished Jul 31 05:35:05 PM PDT 24
Peak memory 212156 kb
Host smart-ff4dbb85-0ddf-4984-b17a-f5ac2df22b39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3881494796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3881494796
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.476787977
Short name T34
Test name
Test status
Simulation time 772255703 ps
CPU time 22.59 seconds
Started Jul 31 05:35:00 PM PDT 24
Finished Jul 31 05:35:22 PM PDT 24
Peak memory 216260 kb
Host smart-30d5a912-7779-47c2-875e-01a5235a3607
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476787977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.476787977
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.4143976514
Short name T185
Test name
Test status
Simulation time 542661066 ps
CPU time 5.08 seconds
Started Jul 31 05:34:56 PM PDT 24
Finished Jul 31 05:35:01 PM PDT 24
Peak memory 212076 kb
Host smart-d8fa41e0-af6b-4793-a56e-cf29659c5e5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143976514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.4143976514
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1384153828
Short name T281
Test name
Test status
Simulation time 6622445880 ps
CPU time 101.32 seconds
Started Jul 31 05:34:55 PM PDT 24
Finished Jul 31 05:36:37 PM PDT 24
Peak memory 238460 kb
Host smart-04f53dc6-1a34-4c25-bece-107ceba6a482
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384153828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1384153828
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1577593286
Short name T183
Test name
Test status
Simulation time 261716561 ps
CPU time 11.54 seconds
Started Jul 31 05:34:57 PM PDT 24
Finished Jul 31 05:35:09 PM PDT 24
Peak memory 212872 kb
Host smart-51fbd909-8a98-4cef-adc4-dbe69882d1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577593286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1577593286
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1610515501
Short name T128
Test name
Test status
Simulation time 139592582 ps
CPU time 6.73 seconds
Started Jul 31 05:34:55 PM PDT 24
Finished Jul 31 05:35:02 PM PDT 24
Peak memory 212180 kb
Host smart-acd2dc14-8b4e-4406-8ad6-82eb47bdd616
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1610515501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1610515501
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3050352011
Short name T247
Test name
Test status
Simulation time 2269662231 ps
CPU time 14.14 seconds
Started Jul 31 05:34:57 PM PDT 24
Finished Jul 31 05:35:11 PM PDT 24
Peak memory 214076 kb
Host smart-2bd38245-fcd7-4177-b47d-17f000588e3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050352011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3050352011
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.239016139
Short name T101
Test name
Test status
Simulation time 18192351977 ps
CPU time 762.56 seconds
Started Jul 31 05:34:59 PM PDT 24
Finished Jul 31 05:47:42 PM PDT 24
Peak memory 229572 kb
Host smart-11e82aee-1b18-4d4a-8064-068f18dacac5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239016139 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.239016139
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2587404427
Short name T160
Test name
Test status
Simulation time 639482519 ps
CPU time 4.18 seconds
Started Jul 31 05:34:13 PM PDT 24
Finished Jul 31 05:34:18 PM PDT 24
Peak memory 212064 kb
Host smart-cfaf223a-7ab4-4c22-9f89-484b72d5991c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587404427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2587404427
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3754735339
Short name T241
Test name
Test status
Simulation time 6599935313 ps
CPU time 111.1 seconds
Started Jul 31 05:34:13 PM PDT 24
Finished Jul 31 05:36:04 PM PDT 24
Peak memory 239192 kb
Host smart-28ee2047-9909-46aa-9375-3f7addca16ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754735339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3754735339
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3942068139
Short name T239
Test name
Test status
Simulation time 694804506 ps
CPU time 9.74 seconds
Started Jul 31 05:34:15 PM PDT 24
Finished Jul 31 05:34:25 PM PDT 24
Peak memory 212864 kb
Host smart-0693c9cf-abee-4073-8504-92aeab46486b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942068139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3942068139
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2813645275
Short name T115
Test name
Test status
Simulation time 1336625654 ps
CPU time 6.39 seconds
Started Jul 31 05:34:15 PM PDT 24
Finished Jul 31 05:34:21 PM PDT 24
Peak memory 212184 kb
Host smart-6db8b65a-ed5d-4793-9d53-ff1cc3fc7512
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2813645275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2813645275
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2423621265
Short name T26
Test name
Test status
Simulation time 766712941 ps
CPU time 53.7 seconds
Started Jul 31 05:34:14 PM PDT 24
Finished Jul 31 05:35:08 PM PDT 24
Peak memory 237356 kb
Host smart-70f201d8-787e-4f01-be42-f7b1a6c2d042
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423621265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2423621265
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1621969787
Short name T314
Test name
Test status
Simulation time 825793876 ps
CPU time 5.31 seconds
Started Jul 31 05:34:15 PM PDT 24
Finished Jul 31 05:34:21 PM PDT 24
Peak memory 212180 kb
Host smart-cb2ca860-42f4-48fc-9a1d-3c6e72cbc598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621969787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1621969787
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2297939428
Short name T163
Test name
Test status
Simulation time 381569508 ps
CPU time 11.59 seconds
Started Jul 31 05:34:19 PM PDT 24
Finished Jul 31 05:34:30 PM PDT 24
Peak memory 214392 kb
Host smart-b2505197-661f-4f9b-9fbb-e97f9ff45898
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297939428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2297939428
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1912530217
Short name T19
Test name
Test status
Simulation time 128059778 ps
CPU time 5.2 seconds
Started Jul 31 05:35:02 PM PDT 24
Finished Jul 31 05:35:07 PM PDT 24
Peak memory 212036 kb
Host smart-1a70b68b-3fb3-42f2-af4c-da6b7f341587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912530217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1912530217
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2491549799
Short name T186
Test name
Test status
Simulation time 30000222210 ps
CPU time 117.96 seconds
Started Jul 31 05:35:00 PM PDT 24
Finished Jul 31 05:36:58 PM PDT 24
Peak memory 213472 kb
Host smart-aa3f326b-a65d-4114-898f-b5852795ed52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491549799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2491549799
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2984489397
Short name T192
Test name
Test status
Simulation time 262205920 ps
CPU time 11.33 seconds
Started Jul 31 05:35:03 PM PDT 24
Finished Jul 31 05:35:14 PM PDT 24
Peak memory 212876 kb
Host smart-ce8b50e2-d6e4-424a-853c-e768bc21e485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984489397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2984489397
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.465767246
Short name T28
Test name
Test status
Simulation time 1638237268 ps
CPU time 6.48 seconds
Started Jul 31 05:34:59 PM PDT 24
Finished Jul 31 05:35:06 PM PDT 24
Peak memory 212160 kb
Host smart-f7b0c91c-9268-40ff-9b37-0dfb33171505
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=465767246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.465767246
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1223251368
Short name T321
Test name
Test status
Simulation time 2654270370 ps
CPU time 17.61 seconds
Started Jul 31 05:34:56 PM PDT 24
Finished Jul 31 05:35:14 PM PDT 24
Peak memory 216020 kb
Host smart-3f08fddb-7db6-4211-9f19-7f3c65174160
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223251368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1223251368
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2650511976
Short name T59
Test name
Test status
Simulation time 239994184 ps
CPU time 4.4 seconds
Started Jul 31 05:35:00 PM PDT 24
Finished Jul 31 05:35:04 PM PDT 24
Peak memory 212056 kb
Host smart-ba48e522-db56-463c-b686-a47faeebaa01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650511976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2650511976
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3110575305
Short name T168
Test name
Test status
Simulation time 18766287252 ps
CPU time 80.09 seconds
Started Jul 31 05:35:00 PM PDT 24
Finished Jul 31 05:36:20 PM PDT 24
Peak memory 213460 kb
Host smart-5559fd18-1b6e-472a-b573-1f0040a37d4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110575305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3110575305
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.4016701295
Short name T226
Test name
Test status
Simulation time 923103703 ps
CPU time 11.46 seconds
Started Jul 31 05:35:00 PM PDT 24
Finished Jul 31 05:35:12 PM PDT 24
Peak memory 212884 kb
Host smart-d233e4e8-96bd-48c3-ad8e-ba472d3f332f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016701295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.4016701295
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1886022559
Short name T116
Test name
Test status
Simulation time 137850957 ps
CPU time 6.62 seconds
Started Jul 31 05:35:02 PM PDT 24
Finished Jul 31 05:35:09 PM PDT 24
Peak memory 212132 kb
Host smart-6971498a-22a7-4b23-9f7e-cd4be71085f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886022559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1886022559
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1512247486
Short name T322
Test name
Test status
Simulation time 132979773 ps
CPU time 7.66 seconds
Started Jul 31 05:35:02 PM PDT 24
Finished Jul 31 05:35:10 PM PDT 24
Peak memory 212080 kb
Host smart-e52c36dc-b2c3-48d6-a436-90c4a18f871b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512247486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1512247486
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.480412142
Short name T289
Test name
Test status
Simulation time 131271003 ps
CPU time 5.24 seconds
Started Jul 31 05:35:10 PM PDT 24
Finished Jul 31 05:35:15 PM PDT 24
Peak memory 211936 kb
Host smart-d44cb6c4-0842-49b4-8eb7-3b8c9045d71f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480412142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.480412142
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.151331768
Short name T21
Test name
Test status
Simulation time 3649204532 ps
CPU time 80.19 seconds
Started Jul 31 05:35:02 PM PDT 24
Finished Jul 31 05:36:22 PM PDT 24
Peak memory 228208 kb
Host smart-b36252da-5fe2-4fc4-aa9b-50a8df4deb27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151331768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.151331768
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1491014278
Short name T244
Test name
Test status
Simulation time 521828871 ps
CPU time 11.42 seconds
Started Jul 31 05:35:08 PM PDT 24
Finished Jul 31 05:35:19 PM PDT 24
Peak memory 212828 kb
Host smart-d473e601-0229-4ac0-aac5-8514fb66ec07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491014278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1491014278
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.478262533
Short name T302
Test name
Test status
Simulation time 1159467934 ps
CPU time 5.98 seconds
Started Jul 31 05:35:00 PM PDT 24
Finished Jul 31 05:35:06 PM PDT 24
Peak memory 212192 kb
Host smart-e156dc83-a0fa-4ce5-8c21-f6a94dbde033
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=478262533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.478262533
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4007218154
Short name T189
Test name
Test status
Simulation time 2026799794 ps
CPU time 18.39 seconds
Started Jul 31 05:35:00 PM PDT 24
Finished Jul 31 05:35:18 PM PDT 24
Peak memory 214488 kb
Host smart-6fa5d6f3-a96a-486d-90c7-371caa28bee8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007218154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4007218154
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.581424524
Short name T235
Test name
Test status
Simulation time 35537399782 ps
CPU time 1388 seconds
Started Jul 31 05:35:12 PM PDT 24
Finished Jul 31 05:58:20 PM PDT 24
Peak memory 238212 kb
Host smart-eb47755c-ef06-44d8-9863-dbd21cbed706
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581424524 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.581424524
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.420482448
Short name T178
Test name
Test status
Simulation time 132839379 ps
CPU time 5.24 seconds
Started Jul 31 05:35:13 PM PDT 24
Finished Jul 31 05:35:18 PM PDT 24
Peak memory 212072 kb
Host smart-e4a8a996-2b38-4db0-bb50-5ce97ab591db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420482448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.420482448
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1160246352
Short name T152
Test name
Test status
Simulation time 1474492760 ps
CPU time 90.58 seconds
Started Jul 31 05:35:10 PM PDT 24
Finished Jul 31 05:36:41 PM PDT 24
Peak memory 229052 kb
Host smart-44562c20-8925-421c-a22c-3048c10cad12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160246352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1160246352
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4264015953
Short name T167
Test name
Test status
Simulation time 696905305 ps
CPU time 9.57 seconds
Started Jul 31 05:35:12 PM PDT 24
Finished Jul 31 05:35:21 PM PDT 24
Peak memory 213008 kb
Host smart-b4463301-bb32-4d55-b3ff-149de6a178df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264015953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4264015953
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1153268392
Short name T283
Test name
Test status
Simulation time 135441107 ps
CPU time 6.3 seconds
Started Jul 31 05:35:12 PM PDT 24
Finished Jul 31 05:35:19 PM PDT 24
Peak memory 212172 kb
Host smart-13d15b0e-a116-4d20-846a-c3854a463790
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1153268392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1153268392
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3777532772
Short name T275
Test name
Test status
Simulation time 1132011346 ps
CPU time 24.13 seconds
Started Jul 31 05:35:10 PM PDT 24
Finished Jul 31 05:35:35 PM PDT 24
Peak memory 217280 kb
Host smart-77ac9417-80cb-43d2-a4d8-4ccaf22028d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777532772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3777532772
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2638517322
Short name T162
Test name
Test status
Simulation time 129363799 ps
CPU time 5.13 seconds
Started Jul 31 05:35:12 PM PDT 24
Finished Jul 31 05:35:17 PM PDT 24
Peak memory 212064 kb
Host smart-4b4f580b-5858-45d9-b159-2f0b81f068a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638517322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2638517322
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.712843941
Short name T129
Test name
Test status
Simulation time 7345003289 ps
CPU time 80.37 seconds
Started Jul 31 05:35:10 PM PDT 24
Finished Jul 31 05:36:30 PM PDT 24
Peak memory 213436 kb
Host smart-246ee407-96c9-4709-b67c-06109614f94d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712843941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.712843941
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.4069651251
Short name T154
Test name
Test status
Simulation time 997353011 ps
CPU time 11.61 seconds
Started Jul 31 05:35:12 PM PDT 24
Finished Jul 31 05:35:24 PM PDT 24
Peak memory 213012 kb
Host smart-b20dc492-08f5-4c32-82d7-94bc94ae6129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069651251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.4069651251
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.245640705
Short name T165
Test name
Test status
Simulation time 1333291572 ps
CPU time 6.5 seconds
Started Jul 31 05:35:11 PM PDT 24
Finished Jul 31 05:35:17 PM PDT 24
Peak memory 212164 kb
Host smart-e26101c1-651d-47e0-b17c-f8fb230e8ccf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=245640705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.245640705
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1509718930
Short name T76
Test name
Test status
Simulation time 419414443 ps
CPU time 18.22 seconds
Started Jul 31 05:35:10 PM PDT 24
Finished Jul 31 05:35:29 PM PDT 24
Peak memory 215888 kb
Host smart-b4f03a3f-4fa9-4629-b8f3-debe0ae63b6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509718930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1509718930
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.812600421
Short name T156
Test name
Test status
Simulation time 440198646 ps
CPU time 4.35 seconds
Started Jul 31 05:35:12 PM PDT 24
Finished Jul 31 05:35:16 PM PDT 24
Peak memory 212072 kb
Host smart-fc7ecf47-4cbc-4715-af5f-f1993772a307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812600421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.812600421
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3238591971
Short name T16
Test name
Test status
Simulation time 7396826769 ps
CPU time 115.93 seconds
Started Jul 31 05:35:14 PM PDT 24
Finished Jul 31 05:37:10 PM PDT 24
Peak memory 238388 kb
Host smart-5940ba7a-9820-4a8c-a1d7-e0d6c8de6d0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238591971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3238591971
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2170904127
Short name T17
Test name
Test status
Simulation time 102055130 ps
CPU time 5.7 seconds
Started Jul 31 05:35:11 PM PDT 24
Finished Jul 31 05:35:17 PM PDT 24
Peak memory 212168 kb
Host smart-cc6c4473-e7a6-4d55-aaed-9f0626bfce06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2170904127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2170904127
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3489703104
Short name T319
Test name
Test status
Simulation time 2552982161 ps
CPU time 13.06 seconds
Started Jul 31 05:35:10 PM PDT 24
Finished Jul 31 05:35:24 PM PDT 24
Peak memory 213872 kb
Host smart-9a5b7489-974f-4ddd-b79c-931e16d229f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489703104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3489703104
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1707951480
Short name T194
Test name
Test status
Simulation time 236247074 ps
CPU time 4.97 seconds
Started Jul 31 05:35:12 PM PDT 24
Finished Jul 31 05:35:17 PM PDT 24
Peak memory 211988 kb
Host smart-52c8b87c-820d-458b-b833-f305d33611e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707951480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1707951480
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4153225632
Short name T171
Test name
Test status
Simulation time 6536743018 ps
CPU time 89.7 seconds
Started Jul 31 05:35:13 PM PDT 24
Finished Jul 31 05:36:43 PM PDT 24
Peak memory 238596 kb
Host smart-381a40f3-4f44-4d55-8ee5-8cfcbec7934f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153225632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4153225632
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3849503823
Short name T276
Test name
Test status
Simulation time 138598121 ps
CPU time 6.34 seconds
Started Jul 31 05:35:10 PM PDT 24
Finished Jul 31 05:35:16 PM PDT 24
Peak memory 212192 kb
Host smart-3af7774c-fe89-46f2-883f-f714903d7824
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3849503823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3849503823
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3124456163
Short name T172
Test name
Test status
Simulation time 2028706324 ps
CPU time 20.79 seconds
Started Jul 31 05:35:10 PM PDT 24
Finished Jul 31 05:35:32 PM PDT 24
Peak memory 213820 kb
Host smart-ebf4b757-17ec-4fa7-9fe0-67a8f932c480
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124456163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3124456163
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1281914207
Short name T191
Test name
Test status
Simulation time 87436194 ps
CPU time 4.48 seconds
Started Jul 31 05:35:17 PM PDT 24
Finished Jul 31 05:35:22 PM PDT 24
Peak memory 212040 kb
Host smart-85ab8c77-2489-4337-8309-4d21300ca9cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281914207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1281914207
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1637544845
Short name T266
Test name
Test status
Simulation time 13535865316 ps
CPU time 150.98 seconds
Started Jul 31 05:35:16 PM PDT 24
Finished Jul 31 05:37:47 PM PDT 24
Peak memory 214464 kb
Host smart-ac5c044e-f3cf-4217-8602-c6233b56baaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637544845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1637544845
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1388419434
Short name T146
Test name
Test status
Simulation time 1027982619 ps
CPU time 15.93 seconds
Started Jul 31 05:35:12 PM PDT 24
Finished Jul 31 05:35:28 PM PDT 24
Peak memory 213148 kb
Host smart-83b56eb7-7d24-4f8c-8390-c6a93c734a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388419434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1388419434
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3494361331
Short name T327
Test name
Test status
Simulation time 833072437 ps
CPU time 5.44 seconds
Started Jul 31 05:35:12 PM PDT 24
Finished Jul 31 05:35:18 PM PDT 24
Peak memory 212064 kb
Host smart-92c56f45-45d2-440e-b93d-f99b09b231ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3494361331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3494361331
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.870346631
Short name T137
Test name
Test status
Simulation time 318083884 ps
CPU time 16.12 seconds
Started Jul 31 05:35:13 PM PDT 24
Finished Jul 31 05:35:29 PM PDT 24
Peak memory 214300 kb
Host smart-53546c2a-a12d-4dc8-b7ef-d9ef287f617b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870346631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.870346631
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2014245083
Short name T187
Test name
Test status
Simulation time 202543499 ps
CPU time 5.3 seconds
Started Jul 31 05:35:14 PM PDT 24
Finished Jul 31 05:35:19 PM PDT 24
Peak memory 212044 kb
Host smart-b8e9ca43-d669-4404-88b7-847fcbd82dab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014245083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2014245083
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3397150551
Short name T229
Test name
Test status
Simulation time 8991051939 ps
CPU time 129.71 seconds
Started Jul 31 05:35:16 PM PDT 24
Finished Jul 31 05:37:26 PM PDT 24
Peak memory 238576 kb
Host smart-c565f894-04f0-481f-8a0b-c004cbacadb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397150551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3397150551
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.439514926
Short name T46
Test name
Test status
Simulation time 334582872 ps
CPU time 9.7 seconds
Started Jul 31 05:35:13 PM PDT 24
Finished Jul 31 05:35:23 PM PDT 24
Peak memory 212856 kb
Host smart-d763c1b6-c2d3-4bf9-961a-e97dfa244c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439514926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.439514926
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3564235299
Short name T142
Test name
Test status
Simulation time 102419972 ps
CPU time 5.4 seconds
Started Jul 31 05:35:13 PM PDT 24
Finished Jul 31 05:35:19 PM PDT 24
Peak memory 212092 kb
Host smart-9916ab18-e443-4e19-9c1b-2bfae054c5f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3564235299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3564235299
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1590443185
Short name T82
Test name
Test status
Simulation time 197655416 ps
CPU time 10.61 seconds
Started Jul 31 05:35:15 PM PDT 24
Finished Jul 31 05:35:26 PM PDT 24
Peak memory 213952 kb
Host smart-53d4c95d-ce92-4d70-a6f5-497b46a7bfb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590443185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1590443185
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.701908307
Short name T263
Test name
Test status
Simulation time 504889340 ps
CPU time 5.26 seconds
Started Jul 31 05:35:23 PM PDT 24
Finished Jul 31 05:35:28 PM PDT 24
Peak memory 212052 kb
Host smart-3482d49a-8d85-467c-9f18-50bee59b57d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701908307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.701908307
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1430794663
Short name T329
Test name
Test status
Simulation time 4104476698 ps
CPU time 61.72 seconds
Started Jul 31 05:35:17 PM PDT 24
Finished Jul 31 05:36:18 PM PDT 24
Peak memory 213436 kb
Host smart-ea7e3a73-4db0-491c-80b8-c254eb05e76b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430794663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1430794663
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.924535372
Short name T124
Test name
Test status
Simulation time 995292047 ps
CPU time 11.63 seconds
Started Jul 31 05:35:12 PM PDT 24
Finished Jul 31 05:35:24 PM PDT 24
Peak memory 212148 kb
Host smart-034cd20e-5ab1-4e2d-8c7b-dc165cbd704e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924535372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.924535372
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3186172807
Short name T118
Test name
Test status
Simulation time 139950788 ps
CPU time 6.9 seconds
Started Jul 31 05:35:13 PM PDT 24
Finished Jul 31 05:35:20 PM PDT 24
Peak memory 212128 kb
Host smart-7fc0e523-8467-4e2a-b7b6-c5aece20932a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3186172807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3186172807
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3983199822
Short name T158
Test name
Test status
Simulation time 1488084263 ps
CPU time 13.15 seconds
Started Jul 31 05:35:15 PM PDT 24
Finished Jul 31 05:35:29 PM PDT 24
Peak memory 213208 kb
Host smart-0ce1f142-e5c3-4c00-bf86-58e70fb512d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983199822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3983199822
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.878540742
Short name T179
Test name
Test status
Simulation time 504449490 ps
CPU time 7.46 seconds
Started Jul 31 05:34:15 PM PDT 24
Finished Jul 31 05:34:23 PM PDT 24
Peak memory 212068 kb
Host smart-91e7b23a-ff16-4371-8387-f619e7125abc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878540742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.878540742
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2934020800
Short name T149
Test name
Test status
Simulation time 1244288401 ps
CPU time 79.64 seconds
Started Jul 31 05:34:15 PM PDT 24
Finished Jul 31 05:35:35 PM PDT 24
Peak memory 212664 kb
Host smart-c6a1b0ed-7f59-4ef1-80a0-edf33fc93293
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934020800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2934020800
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2375134710
Short name T269
Test name
Test status
Simulation time 252548424 ps
CPU time 11.54 seconds
Started Jul 31 05:34:15 PM PDT 24
Finished Jul 31 05:34:26 PM PDT 24
Peak memory 212948 kb
Host smart-17f5250a-111c-4bed-8cdc-a88fcec54815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375134710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2375134710
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2690396672
Short name T310
Test name
Test status
Simulation time 191422157 ps
CPU time 5.6 seconds
Started Jul 31 05:34:14 PM PDT 24
Finished Jul 31 05:34:20 PM PDT 24
Peak memory 212156 kb
Host smart-d6d64767-db1f-44f6-ad35-c8ac0f741769
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2690396672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2690396672
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1053914200
Short name T286
Test name
Test status
Simulation time 369088502 ps
CPU time 5.62 seconds
Started Jul 31 05:34:15 PM PDT 24
Finished Jul 31 05:34:21 PM PDT 24
Peak memory 212152 kb
Host smart-654c5d02-8041-44ec-bc12-6027f5b9220e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053914200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1053914200
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2986503540
Short name T262
Test name
Test status
Simulation time 352364945 ps
CPU time 9.08 seconds
Started Jul 31 05:34:14 PM PDT 24
Finished Jul 31 05:34:23 PM PDT 24
Peak memory 212128 kb
Host smart-6a6dadde-f6de-4064-ab9c-32df64b8ebc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986503540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2986503540
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1666645369
Short name T31
Test name
Test status
Simulation time 463960051 ps
CPU time 4.42 seconds
Started Jul 31 05:34:19 PM PDT 24
Finished Jul 31 05:34:24 PM PDT 24
Peak memory 212072 kb
Host smart-4ad00a8f-9373-4ee0-9f79-e1b907ff535f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666645369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1666645369
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2805722862
Short name T290
Test name
Test status
Simulation time 5681354156 ps
CPU time 129.91 seconds
Started Jul 31 05:34:20 PM PDT 24
Finished Jul 31 05:36:30 PM PDT 24
Peak memory 238404 kb
Host smart-4e065b88-42c1-4645-9dcc-fd13cc50d4c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805722862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2805722862
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1269508765
Short name T140
Test name
Test status
Simulation time 994632263 ps
CPU time 11.36 seconds
Started Jul 31 05:34:21 PM PDT 24
Finished Jul 31 05:34:33 PM PDT 24
Peak memory 212904 kb
Host smart-df0ae55a-6f13-4fb5-ba00-3f75199a3e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269508765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1269508765
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2942636929
Short name T220
Test name
Test status
Simulation time 206253163 ps
CPU time 6.49 seconds
Started Jul 31 05:34:21 PM PDT 24
Finished Jul 31 05:34:27 PM PDT 24
Peak memory 212132 kb
Host smart-9136d920-09c3-47b7-845f-2db5183e23cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2942636929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2942636929
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1913126421
Short name T256
Test name
Test status
Simulation time 283845307 ps
CPU time 6.29 seconds
Started Jul 31 05:34:25 PM PDT 24
Finished Jul 31 05:34:32 PM PDT 24
Peak memory 212180 kb
Host smart-aa364a49-9918-4a47-bd95-4c85904cfe0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913126421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1913126421
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.4222103898
Short name T77
Test name
Test status
Simulation time 3013775946 ps
CPU time 15.55 seconds
Started Jul 31 05:34:21 PM PDT 24
Finished Jul 31 05:34:36 PM PDT 24
Peak memory 214416 kb
Host smart-3b7b0d67-88f7-468b-a482-deaada871ab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222103898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.4222103898
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3513694095
Short name T282
Test name
Test status
Simulation time 1558897813 ps
CPU time 5.07 seconds
Started Jul 31 05:34:24 PM PDT 24
Finished Jul 31 05:34:29 PM PDT 24
Peak memory 212036 kb
Host smart-cecd9265-e33c-4fda-8e6d-f1b8e629d267
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513694095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3513694095
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1291582105
Short name T233
Test name
Test status
Simulation time 7938955730 ps
CPU time 83.44 seconds
Started Jul 31 05:34:20 PM PDT 24
Finished Jul 31 05:35:43 PM PDT 24
Peak memory 225328 kb
Host smart-96447889-27ab-4052-8eb0-0592a33f545f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291582105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1291582105
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2921041193
Short name T32
Test name
Test status
Simulation time 175103222 ps
CPU time 10.17 seconds
Started Jul 31 05:34:18 PM PDT 24
Finished Jul 31 05:34:28 PM PDT 24
Peak memory 213012 kb
Host smart-c5e557af-0e86-4ee3-8aad-4ca306680b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921041193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2921041193
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.49936376
Short name T301
Test name
Test status
Simulation time 414011746 ps
CPU time 5.85 seconds
Started Jul 31 05:34:19 PM PDT 24
Finished Jul 31 05:34:25 PM PDT 24
Peak memory 212132 kb
Host smart-406010bf-4028-4c88-980e-387a980575e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=49936376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.49936376
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2063985965
Short name T12
Test name
Test status
Simulation time 540918912 ps
CPU time 6.35 seconds
Started Jul 31 05:34:22 PM PDT 24
Finished Jul 31 05:34:28 PM PDT 24
Peak memory 212200 kb
Host smart-de71eb78-543f-4f31-a76d-5f91560fb787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063985965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2063985965
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.778905409
Short name T63
Test name
Test status
Simulation time 1124676372 ps
CPU time 15.11 seconds
Started Jul 31 05:34:20 PM PDT 24
Finished Jul 31 05:34:35 PM PDT 24
Peak memory 215364 kb
Host smart-9e3c6298-ca6b-4c7e-a84b-a7beb8cd8cb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778905409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.778905409
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2428970840
Short name T196
Test name
Test status
Simulation time 138234876 ps
CPU time 4.32 seconds
Started Jul 31 05:34:22 PM PDT 24
Finished Jul 31 05:34:26 PM PDT 24
Peak memory 212064 kb
Host smart-d36fa820-d4f6-48a3-b655-90ae055d3b1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428970840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2428970840
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.175592389
Short name T36
Test name
Test status
Simulation time 6298748169 ps
CPU time 218.08 seconds
Started Jul 31 05:34:21 PM PDT 24
Finished Jul 31 05:37:59 PM PDT 24
Peak memory 235996 kb
Host smart-83a411c1-53f8-4dd2-b438-7550f01a9b13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175592389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.175592389
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3530550715
Short name T305
Test name
Test status
Simulation time 1132584243 ps
CPU time 11.47 seconds
Started Jul 31 05:34:19 PM PDT 24
Finished Jul 31 05:34:31 PM PDT 24
Peak memory 212896 kb
Host smart-08e67c5e-8c50-49a7-ae45-ee3150814977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530550715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3530550715
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.4073148740
Short name T138
Test name
Test status
Simulation time 99141967 ps
CPU time 5.9 seconds
Started Jul 31 05:34:18 PM PDT 24
Finished Jul 31 05:34:25 PM PDT 24
Peak memory 212128 kb
Host smart-6605e6a7-2499-4124-942d-6532cd43059a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4073148740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.4073148740
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2002339772
Short name T81
Test name
Test status
Simulation time 104311954 ps
CPU time 5.74 seconds
Started Jul 31 05:34:21 PM PDT 24
Finished Jul 31 05:34:26 PM PDT 24
Peak memory 212180 kb
Host smart-45274063-7da4-4a11-a421-4bf0e626fb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002339772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2002339772
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.599551244
Short name T132
Test name
Test status
Simulation time 178696745 ps
CPU time 12.2 seconds
Started Jul 31 05:34:22 PM PDT 24
Finished Jul 31 05:34:34 PM PDT 24
Peak memory 212272 kb
Host smart-4d184fe0-5dfa-417a-a3d9-f526fa6ef098
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599551244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.599551244
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.442521044
Short name T144
Test name
Test status
Simulation time 136718875 ps
CPU time 4.32 seconds
Started Jul 31 05:34:25 PM PDT 24
Finished Jul 31 05:34:29 PM PDT 24
Peak memory 212072 kb
Host smart-b4bb8b16-51a2-402b-8d2e-4397f268559d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442521044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.442521044
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1388227439
Short name T242
Test name
Test status
Simulation time 2593766305 ps
CPU time 106.28 seconds
Started Jul 31 05:34:20 PM PDT 24
Finished Jul 31 05:36:07 PM PDT 24
Peak memory 229248 kb
Host smart-8ede5769-2fa4-4a99-a4df-2db0f36b62dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388227439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1388227439
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2908306514
Short name T287
Test name
Test status
Simulation time 196800314 ps
CPU time 10.05 seconds
Started Jul 31 05:34:20 PM PDT 24
Finished Jul 31 05:34:30 PM PDT 24
Peak memory 212824 kb
Host smart-627e8d9b-6772-4549-9b26-b3d581e1c1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908306514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2908306514
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2304247484
Short name T259
Test name
Test status
Simulation time 96951118 ps
CPU time 5.69 seconds
Started Jul 31 05:34:21 PM PDT 24
Finished Jul 31 05:34:27 PM PDT 24
Peak memory 212156 kb
Host smart-644557f8-b4e4-49a2-8cc4-6ddb66adcb50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2304247484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2304247484
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1042097595
Short name T188
Test name
Test status
Simulation time 188325529 ps
CPU time 5.2 seconds
Started Jul 31 05:34:18 PM PDT 24
Finished Jul 31 05:34:23 PM PDT 24
Peak memory 212284 kb
Host smart-c92cf893-6699-4e0f-800b-c99e7ef6125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042097595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1042097595
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1793712719
Short name T261
Test name
Test status
Simulation time 140764103 ps
CPU time 11.63 seconds
Started Jul 31 05:34:21 PM PDT 24
Finished Jul 31 05:34:32 PM PDT 24
Peak memory 212080 kb
Host smart-2ec9de74-1275-44ae-9171-3ea600409575
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793712719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1793712719
Directory /workspace/9.rom_ctrl_stress_all/latest
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