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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.19 96.89 91.85 97.67 100.00 98.28 97.30 98.37


Total test records in report: 414
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T290 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2912453758 Aug 01 06:09:12 PM PDT 24 Aug 01 06:09:18 PM PDT 24 271599093 ps
T291 /workspace/coverage/default/13.rom_ctrl_alert_test.3036478240 Aug 01 06:09:19 PM PDT 24 Aug 01 06:09:24 PM PDT 24 126447809 ps
T292 /workspace/coverage/default/21.rom_ctrl_stress_all.515449325 Aug 01 06:09:20 PM PDT 24 Aug 01 06:09:39 PM PDT 24 1710540814 ps
T293 /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3558422133 Aug 01 06:09:39 PM PDT 24 Aug 01 06:20:31 PM PDT 24 50461471910 ps
T294 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2809643028 Aug 01 06:09:40 PM PDT 24 Aug 01 06:09:47 PM PDT 24 146368662 ps
T295 /workspace/coverage/default/18.rom_ctrl_alert_test.4125002734 Aug 01 06:09:19 PM PDT 24 Aug 01 06:09:24 PM PDT 24 110354426 ps
T296 /workspace/coverage/default/38.rom_ctrl_alert_test.2535848567 Aug 01 06:09:42 PM PDT 24 Aug 01 06:09:46 PM PDT 24 88885525 ps
T297 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.874019369 Aug 01 06:09:41 PM PDT 24 Aug 01 06:11:36 PM PDT 24 3896713281 ps
T298 /workspace/coverage/default/4.rom_ctrl_smoke.2622038974 Aug 01 06:09:13 PM PDT 24 Aug 01 06:09:19 PM PDT 24 217647166 ps
T299 /workspace/coverage/default/28.rom_ctrl_stress_all.1539675534 Aug 01 06:09:32 PM PDT 24 Aug 01 06:09:46 PM PDT 24 441105912 ps
T300 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4057412381 Aug 01 06:09:42 PM PDT 24 Aug 01 06:09:54 PM PDT 24 1770157262 ps
T301 /workspace/coverage/default/43.rom_ctrl_stress_all.3614161888 Aug 01 06:09:53 PM PDT 24 Aug 01 06:10:07 PM PDT 24 3273304669 ps
T302 /workspace/coverage/default/9.rom_ctrl_smoke.944623665 Aug 01 06:09:16 PM PDT 24 Aug 01 06:09:23 PM PDT 24 552738606 ps
T303 /workspace/coverage/default/4.rom_ctrl_stress_all.2720170954 Aug 01 06:09:17 PM PDT 24 Aug 01 06:09:36 PM PDT 24 1899473635 ps
T304 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3082838423 Aug 01 06:09:54 PM PDT 24 Aug 01 06:10:00 PM PDT 24 198307676 ps
T305 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3835075070 Aug 01 06:09:32 PM PDT 24 Aug 01 06:12:11 PM PDT 24 5082102563 ps
T306 /workspace/coverage/default/1.rom_ctrl_alert_test.1997963116 Aug 01 06:09:10 PM PDT 24 Aug 01 06:09:15 PM PDT 24 898088563 ps
T307 /workspace/coverage/default/3.rom_ctrl_alert_test.2293016705 Aug 01 06:09:11 PM PDT 24 Aug 01 06:09:15 PM PDT 24 693552870 ps
T308 /workspace/coverage/default/34.rom_ctrl_alert_test.3951082851 Aug 01 06:09:47 PM PDT 24 Aug 01 06:09:52 PM PDT 24 132095839 ps
T309 /workspace/coverage/default/26.rom_ctrl_alert_test.2700552236 Aug 01 06:09:37 PM PDT 24 Aug 01 06:09:41 PM PDT 24 87322128 ps
T310 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3943485565 Aug 01 06:09:42 PM PDT 24 Aug 01 06:09:48 PM PDT 24 531034272 ps
T311 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2064231424 Aug 01 06:09:21 PM PDT 24 Aug 01 06:09:28 PM PDT 24 143647354 ps
T312 /workspace/coverage/default/32.rom_ctrl_alert_test.2742056222 Aug 01 06:09:40 PM PDT 24 Aug 01 06:09:45 PM PDT 24 175691649 ps
T313 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.907899539 Aug 01 06:10:00 PM PDT 24 Aug 01 06:10:11 PM PDT 24 1126945749 ps
T314 /workspace/coverage/default/10.rom_ctrl_alert_test.2209396250 Aug 01 06:09:25 PM PDT 24 Aug 01 06:09:30 PM PDT 24 255742365 ps
T315 /workspace/coverage/default/43.rom_ctrl_alert_test.3389344169 Aug 01 06:09:53 PM PDT 24 Aug 01 06:09:59 PM PDT 24 130656650 ps
T316 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2369694169 Aug 01 06:09:52 PM PDT 24 Aug 01 06:10:03 PM PDT 24 261698963 ps
T317 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.24233135 Aug 01 06:09:57 PM PDT 24 Aug 01 06:12:03 PM PDT 24 2598759939 ps
T318 /workspace/coverage/default/1.rom_ctrl_stress_all.1762125438 Aug 01 06:09:00 PM PDT 24 Aug 01 06:09:17 PM PDT 24 422291367 ps
T319 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1038968810 Aug 01 06:09:28 PM PDT 24 Aug 01 06:09:38 PM PDT 24 640187082 ps
T320 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.288682983 Aug 01 06:09:36 PM PDT 24 Aug 01 06:09:45 PM PDT 24 336810986 ps
T321 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2010207213 Aug 01 06:09:51 PM PDT 24 Aug 01 06:11:39 PM PDT 24 2726274641 ps
T322 /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.614710052 Aug 01 06:09:30 PM PDT 24 Aug 01 07:08:33 PM PDT 24 352664791582 ps
T323 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.664746536 Aug 01 06:10:23 PM PDT 24 Aug 01 06:10:30 PM PDT 24 86425137 ps
T72 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1363009738 Aug 01 06:10:26 PM PDT 24 Aug 01 06:11:39 PM PDT 24 310882303 ps
T77 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2388160559 Aug 01 06:10:10 PM PDT 24 Aug 01 06:10:16 PM PDT 24 126775519 ps
T78 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4283163876 Aug 01 06:10:23 PM PDT 24 Aug 01 06:10:29 PM PDT 24 95625592 ps
T80 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2104459744 Aug 01 06:10:13 PM PDT 24 Aug 01 06:10:32 PM PDT 24 3592892621 ps
T324 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1467747419 Aug 01 06:10:07 PM PDT 24 Aug 01 06:10:12 PM PDT 24 86232685 ps
T102 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1441293004 Aug 01 06:10:09 PM PDT 24 Aug 01 06:10:13 PM PDT 24 1381936240 ps
T81 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4147845775 Aug 01 06:10:09 PM PDT 24 Aug 01 06:10:28 PM PDT 24 1331103717 ps
T325 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2490990204 Aug 01 06:10:07 PM PDT 24 Aug 01 06:10:12 PM PDT 24 128910502 ps
T326 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.980061130 Aug 01 06:10:10 PM PDT 24 Aug 01 06:10:14 PM PDT 24 1380654083 ps
T327 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1924555000 Aug 01 06:10:14 PM PDT 24 Aug 01 06:10:19 PM PDT 24 95029258 ps
T73 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2944823149 Aug 01 06:10:25 PM PDT 24 Aug 01 06:11:02 PM PDT 24 323418176 ps
T103 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4226216483 Aug 01 06:10:11 PM PDT 24 Aug 01 06:10:16 PM PDT 24 132146543 ps
T107 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2003635587 Aug 01 06:10:12 PM PDT 24 Aug 01 06:10:16 PM PDT 24 191035734 ps
T82 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1030234660 Aug 01 06:10:11 PM PDT 24 Aug 01 06:10:16 PM PDT 24 336461538 ps
T74 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1070523974 Aug 01 06:10:23 PM PDT 24 Aug 01 06:11:33 PM PDT 24 987468971 ps
T104 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4009395564 Aug 01 06:10:24 PM PDT 24 Aug 01 06:10:30 PM PDT 24 127470034 ps
T328 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.712655978 Aug 01 06:10:09 PM PDT 24 Aug 01 06:10:17 PM PDT 24 1048336979 ps
T83 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1945004249 Aug 01 06:10:12 PM PDT 24 Aug 01 06:10:20 PM PDT 24 5455488326 ps
T329 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2254780209 Aug 01 06:10:27 PM PDT 24 Aug 01 06:10:33 PM PDT 24 419073672 ps
T330 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4282571069 Aug 01 06:10:25 PM PDT 24 Aug 01 06:10:35 PM PDT 24 1003157373 ps
T105 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3936611475 Aug 01 06:10:26 PM PDT 24 Aug 01 06:10:31 PM PDT 24 126903185 ps
T331 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2064066906 Aug 01 06:10:14 PM PDT 24 Aug 01 06:10:18 PM PDT 24 86116314 ps
T332 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2244619042 Aug 01 06:10:09 PM PDT 24 Aug 01 06:10:15 PM PDT 24 347692880 ps
T333 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1578905362 Aug 01 06:10:23 PM PDT 24 Aug 01 06:10:29 PM PDT 24 165035122 ps
T334 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3015702929 Aug 01 06:10:10 PM PDT 24 Aug 01 06:10:17 PM PDT 24 521993337 ps
T335 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3695449001 Aug 01 06:10:13 PM PDT 24 Aug 01 06:10:20 PM PDT 24 274554131 ps
T336 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.899347380 Aug 01 06:10:21 PM PDT 24 Aug 01 06:10:29 PM PDT 24 127270360 ps
T337 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.434962557 Aug 01 06:10:23 PM PDT 24 Aug 01 06:10:29 PM PDT 24 562808089 ps
T106 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3554787676 Aug 01 06:10:16 PM PDT 24 Aug 01 06:10:21 PM PDT 24 255339082 ps
T84 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2919474922 Aug 01 06:10:28 PM PDT 24 Aug 01 06:10:33 PM PDT 24 346601889 ps
T109 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.626532897 Aug 01 06:10:21 PM PDT 24 Aug 01 06:11:31 PM PDT 24 330647702 ps
T85 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.943709379 Aug 01 06:10:12 PM PDT 24 Aug 01 06:10:18 PM PDT 24 157589378 ps
T338 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.91667265 Aug 01 06:10:13 PM PDT 24 Aug 01 06:10:19 PM PDT 24 127282373 ps
T115 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2723956788 Aug 01 06:10:14 PM PDT 24 Aug 01 06:11:22 PM PDT 24 471374045 ps
T110 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3088986775 Aug 01 06:10:14 PM PDT 24 Aug 01 06:10:51 PM PDT 24 710249491 ps
T86 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2652330192 Aug 01 06:10:11 PM PDT 24 Aug 01 06:10:15 PM PDT 24 168173812 ps
T87 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1292081327 Aug 01 06:10:22 PM PDT 24 Aug 01 06:10:27 PM PDT 24 174834579 ps
T339 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3797142438 Aug 01 06:09:56 PM PDT 24 Aug 01 06:10:04 PM PDT 24 365127917 ps
T340 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1373951363 Aug 01 06:10:09 PM PDT 24 Aug 01 06:10:16 PM PDT 24 86094028 ps
T341 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3101492335 Aug 01 06:10:23 PM PDT 24 Aug 01 06:10:29 PM PDT 24 496624512 ps
T342 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3607619193 Aug 01 06:10:29 PM PDT 24 Aug 01 06:10:33 PM PDT 24 181126090 ps
T343 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2959855903 Aug 01 06:10:23 PM PDT 24 Aug 01 06:10:31 PM PDT 24 497751861 ps
T88 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3644147461 Aug 01 06:10:29 PM PDT 24 Aug 01 06:10:57 PM PDT 24 570806146 ps
T344 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.524969528 Aug 01 06:10:08 PM PDT 24 Aug 01 06:10:14 PM PDT 24 99759301 ps
T345 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1326025085 Aug 01 06:10:23 PM PDT 24 Aug 01 06:10:29 PM PDT 24 132709225 ps
T94 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3163360283 Aug 01 06:10:10 PM PDT 24 Aug 01 06:10:16 PM PDT 24 371812019 ps
T346 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.859303180 Aug 01 06:10:23 PM PDT 24 Aug 01 06:10:28 PM PDT 24 137006126 ps
T347 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2658044630 Aug 01 06:10:21 PM PDT 24 Aug 01 06:10:26 PM PDT 24 415288734 ps
T348 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3006060723 Aug 01 06:10:07 PM PDT 24 Aug 01 06:10:12 PM PDT 24 543646403 ps
T95 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2051152293 Aug 01 06:10:13 PM PDT 24 Aug 01 06:10:21 PM PDT 24 135713330 ps
T349 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3988517539 Aug 01 06:10:09 PM PDT 24 Aug 01 06:10:18 PM PDT 24 1068527618 ps
T112 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.959312229 Aug 01 06:10:15 PM PDT 24 Aug 01 06:11:28 PM PDT 24 718165730 ps
T350 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1607000032 Aug 01 06:09:53 PM PDT 24 Aug 01 06:10:02 PM PDT 24 177781976 ps
T351 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1059896469 Aug 01 06:10:15 PM PDT 24 Aug 01 06:10:19 PM PDT 24 690199398 ps
T96 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2986050675 Aug 01 06:10:36 PM PDT 24 Aug 01 06:10:41 PM PDT 24 285634127 ps
T352 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2217851745 Aug 01 06:10:19 PM PDT 24 Aug 01 06:10:29 PM PDT 24 444827620 ps
T353 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3722360487 Aug 01 06:09:58 PM PDT 24 Aug 01 06:10:25 PM PDT 24 2255458278 ps
T354 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1084972306 Aug 01 06:10:22 PM PDT 24 Aug 01 06:10:30 PM PDT 24 114429768 ps
T117 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3715794349 Aug 01 06:10:24 PM PDT 24 Aug 01 06:11:08 PM PDT 24 489806931 ps
T355 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1983652826 Aug 01 06:10:10 PM PDT 24 Aug 01 06:10:16 PM PDT 24 127765428 ps
T356 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.631943194 Aug 01 06:10:09 PM PDT 24 Aug 01 06:11:20 PM PDT 24 2519053593 ps
T357 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2367104684 Aug 01 06:10:10 PM PDT 24 Aug 01 06:10:15 PM PDT 24 86282974 ps
T358 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1040632374 Aug 01 06:10:08 PM PDT 24 Aug 01 06:10:14 PM PDT 24 91747147 ps
T359 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1274643617 Aug 01 06:10:14 PM PDT 24 Aug 01 06:10:20 PM PDT 24 131257579 ps
T360 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.590990663 Aug 01 06:10:15 PM PDT 24 Aug 01 06:11:23 PM PDT 24 942499783 ps
T361 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4063360251 Aug 01 06:10:18 PM PDT 24 Aug 01 06:10:23 PM PDT 24 1759127146 ps
T362 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2643686972 Aug 01 06:10:10 PM PDT 24 Aug 01 06:10:14 PM PDT 24 175467995 ps
T363 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.84502770 Aug 01 06:10:09 PM PDT 24 Aug 01 06:10:16 PM PDT 24 89041172 ps
T364 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2115606035 Aug 01 06:10:08 PM PDT 24 Aug 01 06:10:13 PM PDT 24 404641815 ps
T365 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.100770725 Aug 01 06:10:27 PM PDT 24 Aug 01 06:10:31 PM PDT 24 278361105 ps
T366 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1340677372 Aug 01 06:10:40 PM PDT 24 Aug 01 06:10:44 PM PDT 24 437177386 ps
T367 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2213477887 Aug 01 06:10:17 PM PDT 24 Aug 01 06:10:23 PM PDT 24 622273052 ps
T368 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3791542493 Aug 01 06:10:18 PM PDT 24 Aug 01 06:10:23 PM PDT 24 149658428 ps
T369 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4050078148 Aug 01 06:10:23 PM PDT 24 Aug 01 06:10:28 PM PDT 24 95565728 ps
T370 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2573707214 Aug 01 06:10:17 PM PDT 24 Aug 01 06:10:21 PM PDT 24 333772058 ps
T371 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.497539639 Aug 01 06:10:10 PM PDT 24 Aug 01 06:10:47 PM PDT 24 311807822 ps
T372 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2805667837 Aug 01 06:10:09 PM PDT 24 Aug 01 06:10:17 PM PDT 24 834171128 ps
T373 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1318552097 Aug 01 06:10:25 PM PDT 24 Aug 01 06:10:32 PM PDT 24 577958476 ps
T374 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2916474911 Aug 01 06:10:11 PM PDT 24 Aug 01 06:10:17 PM PDT 24 1140276926 ps
T111 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1640832095 Aug 01 06:10:14 PM PDT 24 Aug 01 06:10:51 PM PDT 24 962405926 ps
T375 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2624914411 Aug 01 06:10:09 PM PDT 24 Aug 01 06:10:14 PM PDT 24 496242176 ps
T376 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3732104240 Aug 01 06:10:38 PM PDT 24 Aug 01 06:10:44 PM PDT 24 289439008 ps
T377 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1662018740 Aug 01 06:10:15 PM PDT 24 Aug 01 06:10:21 PM PDT 24 287085761 ps
T378 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.147017588 Aug 01 06:10:19 PM PDT 24 Aug 01 06:10:24 PM PDT 24 132940400 ps
T379 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1940781364 Aug 01 06:10:16 PM PDT 24 Aug 01 06:10:21 PM PDT 24 249153362 ps
T380 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1956622380 Aug 01 06:10:14 PM PDT 24 Aug 01 06:10:18 PM PDT 24 114787586 ps
T381 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2134441675 Aug 01 06:10:09 PM PDT 24 Aug 01 06:10:15 PM PDT 24 151046695 ps
T108 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1087205553 Aug 01 06:10:17 PM PDT 24 Aug 01 06:10:28 PM PDT 24 305541473 ps
T382 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2637131707 Aug 01 06:10:29 PM PDT 24 Aug 01 06:10:37 PM PDT 24 132915412 ps
T383 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3995730315 Aug 01 06:09:54 PM PDT 24 Aug 01 06:09:59 PM PDT 24 957817447 ps
T384 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2700234121 Aug 01 06:10:14 PM PDT 24 Aug 01 06:10:20 PM PDT 24 971346971 ps
T98 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2167832648 Aug 01 06:10:14 PM PDT 24 Aug 01 06:10:19 PM PDT 24 87237743 ps
T385 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1141422496 Aug 01 06:10:24 PM PDT 24 Aug 01 06:10:28 PM PDT 24 88032427 ps
T386 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3171518652 Aug 01 06:10:13 PM PDT 24 Aug 01 06:10:21 PM PDT 24 358674203 ps
T387 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3159432750 Aug 01 06:10:11 PM PDT 24 Aug 01 06:10:19 PM PDT 24 491183838 ps
T388 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2485547687 Aug 01 06:10:13 PM PDT 24 Aug 01 06:10:21 PM PDT 24 92020301 ps
T389 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1012157358 Aug 01 06:10:18 PM PDT 24 Aug 01 06:10:26 PM PDT 24 521555222 ps
T99 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.319352593 Aug 01 06:10:15 PM PDT 24 Aug 01 06:10:36 PM PDT 24 550976690 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2452218753 Aug 01 06:10:09 PM PDT 24 Aug 01 06:10:14 PM PDT 24 131183977 ps
T391 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1900919735 Aug 01 06:10:21 PM PDT 24 Aug 01 06:10:26 PM PDT 24 85669057 ps
T392 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4238327953 Aug 01 06:10:26 PM PDT 24 Aug 01 06:10:36 PM PDT 24 284236767 ps
T393 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1713558045 Aug 01 06:10:27 PM PDT 24 Aug 01 06:11:06 PM PDT 24 622777784 ps
T394 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2827816815 Aug 01 06:10:26 PM PDT 24 Aug 01 06:10:33 PM PDT 24 533279741 ps
T395 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.48196092 Aug 01 06:10:17 PM PDT 24 Aug 01 06:10:35 PM PDT 24 377462988 ps
T118 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1928562339 Aug 01 06:10:23 PM PDT 24 Aug 01 06:11:32 PM PDT 24 249430752 ps
T396 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.544979013 Aug 01 06:10:24 PM PDT 24 Aug 01 06:10:28 PM PDT 24 332813073 ps
T114 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1057640501 Aug 01 06:10:08 PM PDT 24 Aug 01 06:11:28 PM PDT 24 659500869 ps
T397 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3202047415 Aug 01 06:10:13 PM PDT 24 Aug 01 06:10:18 PM PDT 24 132494790 ps
T101 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1198229113 Aug 01 06:10:24 PM PDT 24 Aug 01 06:10:28 PM PDT 24 88825403 ps
T398 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3194361117 Aug 01 06:10:13 PM PDT 24 Aug 01 06:10:19 PM PDT 24 467629166 ps
T399 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1501945761 Aug 01 06:10:18 PM PDT 24 Aug 01 06:10:23 PM PDT 24 538477245 ps
T400 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.650809411 Aug 01 06:10:11 PM PDT 24 Aug 01 06:10:15 PM PDT 24 87479164 ps
T97 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3449137230 Aug 01 06:10:17 PM PDT 24 Aug 01 06:10:21 PM PDT 24 129304612 ps
T401 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3450041483 Aug 01 06:10:26 PM PDT 24 Aug 01 06:10:31 PM PDT 24 700105576 ps
T402 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3784186869 Aug 01 06:10:24 PM PDT 24 Aug 01 06:10:33 PM PDT 24 262945004 ps
T116 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2890425062 Aug 01 06:10:12 PM PDT 24 Aug 01 06:11:21 PM PDT 24 1061494959 ps
T403 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3797015151 Aug 01 06:09:55 PM PDT 24 Aug 01 06:11:05 PM PDT 24 1166946722 ps
T404 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.911432991 Aug 01 06:10:06 PM PDT 24 Aug 01 06:10:10 PM PDT 24 333088615 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4276685230 Aug 01 06:10:09 PM PDT 24 Aug 01 06:10:46 PM PDT 24 1261134047 ps
T406 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2809414313 Aug 01 06:10:26 PM PDT 24 Aug 01 06:10:36 PM PDT 24 661507380 ps
T407 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4235379217 Aug 01 06:10:23 PM PDT 24 Aug 01 06:11:00 PM PDT 24 193124758 ps
T408 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3772992765 Aug 01 06:10:15 PM PDT 24 Aug 01 06:10:24 PM PDT 24 234589876 ps
T409 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2211198164 Aug 01 06:10:15 PM PDT 24 Aug 01 06:10:20 PM PDT 24 378438323 ps
T410 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.432220264 Aug 01 06:10:09 PM PDT 24 Aug 01 06:10:15 PM PDT 24 143061115 ps
T411 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1258013543 Aug 01 06:10:08 PM PDT 24 Aug 01 06:10:13 PM PDT 24 131955340 ps
T412 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.455793927 Aug 01 06:10:21 PM PDT 24 Aug 01 06:10:26 PM PDT 24 1037675556 ps
T413 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.505012745 Aug 01 06:09:56 PM PDT 24 Aug 01 06:10:04 PM PDT 24 2048983213 ps
T414 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4041533327 Aug 01 06:10:25 PM PDT 24 Aug 01 06:10:30 PM PDT 24 133110229 ps
T113 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2849472494 Aug 01 06:10:29 PM PDT 24 Aug 01 06:11:42 PM PDT 24 364513113 ps
T100 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1595152552 Aug 01 06:10:12 PM PDT 24 Aug 01 06:10:18 PM PDT 24 255159652 ps

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.443269139
Short name T4
Test name
Test status
Simulation time 317075812 ps
CPU time 15.8 seconds
Started Aug 01 06:09:28 PM PDT 24
Finished Aug 01 06:09:44 PM PDT 24
Peak memory 214284 kb
Host smart-af144831-d407-4f68-98e7-33988b205ff6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443269139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.443269139
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2207001428
Short name T15
Test name
Test status
Simulation time 530539768620 ps
CPU time 3505.98 seconds
Started Aug 01 06:09:17 PM PDT 24
Finished Aug 01 07:07:43 PM PDT 24
Peak memory 245100 kb
Host smart-55fc60de-cfec-426c-869e-2884358ee6a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207001428 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2207001428
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.226155371
Short name T20
Test name
Test status
Simulation time 10724678299 ps
CPU time 129.19 seconds
Started Aug 01 06:09:51 PM PDT 24
Finished Aug 01 06:12:01 PM PDT 24
Peak memory 234812 kb
Host smart-74b13ebd-5b72-4ce3-8bbf-b03fe966854a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226155371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.226155371
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2023802970
Short name T56
Test name
Test status
Simulation time 7382734290 ps
CPU time 170.57 seconds
Started Aug 01 06:09:27 PM PDT 24
Finished Aug 01 06:12:18 PM PDT 24
Peak memory 214516 kb
Host smart-c114ae72-e8dc-4971-ba94-e4fd57ed8fc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023802970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2023802970
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1070523974
Short name T74
Test name
Test status
Simulation time 987468971 ps
CPU time 69.47 seconds
Started Aug 01 06:10:23 PM PDT 24
Finished Aug 01 06:11:33 PM PDT 24
Peak memory 213116 kb
Host smart-6794d600-e24c-4220-a3b8-f2e865188cbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070523974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1070523974
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.896776425
Short name T12
Test name
Test status
Simulation time 131484843 ps
CPU time 5.09 seconds
Started Aug 01 06:09:43 PM PDT 24
Finished Aug 01 06:09:48 PM PDT 24
Peak memory 212016 kb
Host smart-d4fe85ab-8f77-45ea-887b-3d3d8c3ac562
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896776425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.896776425
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2494843626
Short name T138
Test name
Test status
Simulation time 426423647 ps
CPU time 17.19 seconds
Started Aug 01 06:09:26 PM PDT 24
Finished Aug 01 06:09:43 PM PDT 24
Peak memory 216180 kb
Host smart-b3f4143f-eb76-403d-8d1a-a73e48099c2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494843626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2494843626
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.952001050
Short name T33
Test name
Test status
Simulation time 4148861888 ps
CPU time 10.96 seconds
Started Aug 01 06:09:19 PM PDT 24
Finished Aug 01 06:09:30 PM PDT 24
Peak memory 213068 kb
Host smart-4f880963-972c-445a-b613-b547dec7be75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952001050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.952001050
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1423601108
Short name T29
Test name
Test status
Simulation time 939669630 ps
CPU time 61.15 seconds
Started Aug 01 06:08:59 PM PDT 24
Finished Aug 01 06:10:00 PM PDT 24
Peak memory 241384 kb
Host smart-c5dbf237-e11c-4a6c-ac5b-6b8a71b20c4a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423601108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1423601108
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2104459744
Short name T80
Test name
Test status
Simulation time 3592892621 ps
CPU time 18.25 seconds
Started Aug 01 06:10:13 PM PDT 24
Finished Aug 01 06:10:32 PM PDT 24
Peak memory 211440 kb
Host smart-452e3f30-d5d3-4f7d-8405-f8c69eae5b08
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104459744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2104459744
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3688575797
Short name T34
Test name
Test status
Simulation time 497501864 ps
CPU time 11.35 seconds
Started Aug 01 06:09:47 PM PDT 24
Finished Aug 01 06:09:58 PM PDT 24
Peak memory 212876 kb
Host smart-3ad3732f-ea9e-4a21-9836-b033142f7967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688575797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3688575797
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3088986775
Short name T110
Test name
Test status
Simulation time 710249491 ps
CPU time 36.88 seconds
Started Aug 01 06:10:14 PM PDT 24
Finished Aug 01 06:10:51 PM PDT 24
Peak memory 211664 kb
Host smart-79215718-c144-48d0-a8f0-402d4396be22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088986775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3088986775
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1057640501
Short name T114
Test name
Test status
Simulation time 659500869 ps
CPU time 79.54 seconds
Started Aug 01 06:10:08 PM PDT 24
Finished Aug 01 06:11:28 PM PDT 24
Peak memory 214148 kb
Host smart-9406c782-b60c-4df1-9bce-a22804458415
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057640501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1057640501
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2226273400
Short name T19
Test name
Test status
Simulation time 17676573721 ps
CPU time 743.92 seconds
Started Aug 01 06:09:57 PM PDT 24
Finished Aug 01 06:22:22 PM PDT 24
Peak memory 236592 kb
Host smart-4d052a4f-fd2a-4acf-9cad-adf71d06afc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226273400 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2226273400
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4147845775
Short name T81
Test name
Test status
Simulation time 1331103717 ps
CPU time 18.28 seconds
Started Aug 01 06:10:09 PM PDT 24
Finished Aug 01 06:10:28 PM PDT 24
Peak memory 211412 kb
Host smart-f4e3e42a-b631-46df-84e5-d81cd42ebb0c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147845775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4147845775
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2849472494
Short name T113
Test name
Test status
Simulation time 364513113 ps
CPU time 72.65 seconds
Started Aug 01 06:10:29 PM PDT 24
Finished Aug 01 06:11:42 PM PDT 24
Peak memory 213912 kb
Host smart-cf9899fe-601a-4062-b342-b45d7c793a31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849472494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2849472494
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3644147461
Short name T88
Test name
Test status
Simulation time 570806146 ps
CPU time 27.85 seconds
Started Aug 01 06:10:29 PM PDT 24
Finished Aug 01 06:10:57 PM PDT 24
Peak memory 211408 kb
Host smart-801b5520-e4fe-4cb1-8623-f49d9ba391ea
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644147461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3644147461
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3324172916
Short name T207
Test name
Test status
Simulation time 1983242389 ps
CPU time 16.6 seconds
Started Aug 01 06:08:56 PM PDT 24
Finished Aug 01 06:09:12 PM PDT 24
Peak memory 212840 kb
Host smart-186da78d-09d3-4138-854b-2d9fe4a01fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324172916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3324172916
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2157969848
Short name T14
Test name
Test status
Simulation time 260270952 ps
CPU time 5.58 seconds
Started Aug 01 06:09:11 PM PDT 24
Finished Aug 01 06:09:16 PM PDT 24
Peak memory 212028 kb
Host smart-6ba249e4-ebd6-4c76-a589-4d709ad9598d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2157969848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2157969848
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.881969187
Short name T76
Test name
Test status
Simulation time 99978587 ps
CPU time 5.6 seconds
Started Aug 01 06:08:59 PM PDT 24
Finished Aug 01 06:09:04 PM PDT 24
Peak memory 212160 kb
Host smart-7e8457fd-86bb-4612-b38d-2c1dd71fa507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881969187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.881969187
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2652330192
Short name T86
Test name
Test status
Simulation time 168173812 ps
CPU time 4.32 seconds
Started Aug 01 06:10:11 PM PDT 24
Finished Aug 01 06:10:15 PM PDT 24
Peak memory 218304 kb
Host smart-d0c19d46-1d4a-4c03-acdb-72ea0452f9c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652330192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2652330192
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1258013543
Short name T411
Test name
Test status
Simulation time 131955340 ps
CPU time 5.41 seconds
Started Aug 01 06:10:08 PM PDT 24
Finished Aug 01 06:10:13 PM PDT 24
Peak memory 217868 kb
Host smart-424f17be-219c-41ae-8035-f85c8cae39ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258013543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1258013543
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3797142438
Short name T339
Test name
Test status
Simulation time 365127917 ps
CPU time 7.64 seconds
Started Aug 01 06:09:56 PM PDT 24
Finished Aug 01 06:10:04 PM PDT 24
Peak memory 211292 kb
Host smart-6a727f43-a20a-492a-9482-6112e04a680f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797142438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3797142438
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3988517539
Short name T349
Test name
Test status
Simulation time 1068527618 ps
CPU time 8.31 seconds
Started Aug 01 06:10:09 PM PDT 24
Finished Aug 01 06:10:18 PM PDT 24
Peak memory 219628 kb
Host smart-ed98f01a-bef2-4192-9a29-c330855cbcb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988517539 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3988517539
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2003635587
Short name T107
Test name
Test status
Simulation time 191035734 ps
CPU time 4.18 seconds
Started Aug 01 06:10:12 PM PDT 24
Finished Aug 01 06:10:16 PM PDT 24
Peak memory 219452 kb
Host smart-d945efc3-36b5-48a9-a7c8-afa11c96ecce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003635587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2003635587
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3995730315
Short name T383
Test name
Test status
Simulation time 957817447 ps
CPU time 4.95 seconds
Started Aug 01 06:09:54 PM PDT 24
Finished Aug 01 06:09:59 PM PDT 24
Peak memory 211136 kb
Host smart-5885b7e0-88c7-4d27-944a-c3de8e2f4c14
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995730315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3995730315
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.505012745
Short name T413
Test name
Test status
Simulation time 2048983213 ps
CPU time 7.59 seconds
Started Aug 01 06:09:56 PM PDT 24
Finished Aug 01 06:10:04 PM PDT 24
Peak memory 211192 kb
Host smart-3b0bb0de-7d4f-43dc-8899-b28d75c19424
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505012745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
505012745
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3722360487
Short name T353
Test name
Test status
Simulation time 2255458278 ps
CPU time 27.62 seconds
Started Aug 01 06:09:58 PM PDT 24
Finished Aug 01 06:10:25 PM PDT 24
Peak memory 211504 kb
Host smart-064cc7f4-18c3-4676-ab3c-11e58c725e31
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722360487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3722360487
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2805667837
Short name T372
Test name
Test status
Simulation time 834171128 ps
CPU time 6.89 seconds
Started Aug 01 06:10:09 PM PDT 24
Finished Aug 01 06:10:17 PM PDT 24
Peak memory 219488 kb
Host smart-4a44c59f-f35d-4125-9db3-40bc2947d5dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805667837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2805667837
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1607000032
Short name T350
Test name
Test status
Simulation time 177781976 ps
CPU time 8.29 seconds
Started Aug 01 06:09:53 PM PDT 24
Finished Aug 01 06:10:02 PM PDT 24
Peak memory 219568 kb
Host smart-27d3685b-3ec5-4499-a1db-89a5259db155
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607000032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1607000032
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3797015151
Short name T403
Test name
Test status
Simulation time 1166946722 ps
CPU time 69.48 seconds
Started Aug 01 06:09:55 PM PDT 24
Finished Aug 01 06:11:05 PM PDT 24
Peak memory 219484 kb
Host smart-fc033bcd-ce54-4fd8-bed6-9b7c5f0a186d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797015151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3797015151
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1595152552
Short name T100
Test name
Test status
Simulation time 255159652 ps
CPU time 5.12 seconds
Started Aug 01 06:10:12 PM PDT 24
Finished Aug 01 06:10:18 PM PDT 24
Peak memory 217952 kb
Host smart-8ca7bda1-5c04-4278-bdbe-0453a3402aca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595152552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1595152552
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3202047415
Short name T397
Test name
Test status
Simulation time 132494790 ps
CPU time 5.07 seconds
Started Aug 01 06:10:13 PM PDT 24
Finished Aug 01 06:10:18 PM PDT 24
Peak memory 219444 kb
Host smart-1b59d9b0-b5c9-455d-a46c-49e751caab61
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202047415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3202047415
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3171518652
Short name T386
Test name
Test status
Simulation time 358674203 ps
CPU time 7.14 seconds
Started Aug 01 06:10:13 PM PDT 24
Finished Aug 01 06:10:21 PM PDT 24
Peak memory 211312 kb
Host smart-2fa17610-a0f3-46fc-be07-a50f7d811640
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171518652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3171518652
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.524969528
Short name T344
Test name
Test status
Simulation time 99759301 ps
CPU time 5.41 seconds
Started Aug 01 06:10:08 PM PDT 24
Finished Aug 01 06:10:14 PM PDT 24
Peak memory 216556 kb
Host smart-79e6302e-c127-4cde-b66f-d4850b009053
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524969528 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.524969528
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.911432991
Short name T404
Test name
Test status
Simulation time 333088615 ps
CPU time 4.24 seconds
Started Aug 01 06:10:06 PM PDT 24
Finished Aug 01 06:10:10 PM PDT 24
Peak memory 218592 kb
Host smart-41dc6525-0c96-4e53-86e0-6088e8d1dc2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911432991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.911432991
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1983652826
Short name T355
Test name
Test status
Simulation time 127765428 ps
CPU time 4.91 seconds
Started Aug 01 06:10:10 PM PDT 24
Finished Aug 01 06:10:16 PM PDT 24
Peak memory 211176 kb
Host smart-7bd802cd-4a7a-491b-ac53-a1527f5b5652
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983652826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1983652826
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.650809411
Short name T400
Test name
Test status
Simulation time 87479164 ps
CPU time 4.14 seconds
Started Aug 01 06:10:11 PM PDT 24
Finished Aug 01 06:10:15 PM PDT 24
Peak memory 211196 kb
Host smart-2c352034-9bac-47f2-bee7-91fbaa11d710
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650809411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
650809411
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2388160559
Short name T77
Test name
Test status
Simulation time 126775519 ps
CPU time 5.31 seconds
Started Aug 01 06:10:10 PM PDT 24
Finished Aug 01 06:10:16 PM PDT 24
Peak memory 211324 kb
Host smart-b03e808e-8574-49d2-9b43-906545d656db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388160559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2388160559
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3772992765
Short name T408
Test name
Test status
Simulation time 234589876 ps
CPU time 8.64 seconds
Started Aug 01 06:10:15 PM PDT 24
Finished Aug 01 06:10:24 PM PDT 24
Peak memory 219628 kb
Host smart-951b052e-ff1d-410a-8125-76977d528629
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772992765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3772992765
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1640832095
Short name T111
Test name
Test status
Simulation time 962405926 ps
CPU time 36.17 seconds
Started Aug 01 06:10:14 PM PDT 24
Finished Aug 01 06:10:51 PM PDT 24
Peak memory 219464 kb
Host smart-7481c2fa-edcc-4e3a-a295-93c83e6131e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640832095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1640832095
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2213477887
Short name T367
Test name
Test status
Simulation time 622273052 ps
CPU time 5.92 seconds
Started Aug 01 06:10:17 PM PDT 24
Finished Aug 01 06:10:23 PM PDT 24
Peak memory 219528 kb
Host smart-8a0647b6-9d83-4685-abb6-7c96fe3826d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213477887 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2213477887
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3449137230
Short name T97
Test name
Test status
Simulation time 129304612 ps
CPU time 4.17 seconds
Started Aug 01 06:10:17 PM PDT 24
Finished Aug 01 06:10:21 PM PDT 24
Peak memory 218684 kb
Host smart-db43f046-ba9b-463b-bce1-4c58768922e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449137230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3449137230
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1059896469
Short name T351
Test name
Test status
Simulation time 690199398 ps
CPU time 4.27 seconds
Started Aug 01 06:10:15 PM PDT 24
Finished Aug 01 06:10:19 PM PDT 24
Peak memory 211328 kb
Host smart-7cf3cd49-2ebb-4fd4-95a4-a75883cbea1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059896469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1059896469
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.899347380
Short name T336
Test name
Test status
Simulation time 127270360 ps
CPU time 8.19 seconds
Started Aug 01 06:10:21 PM PDT 24
Finished Aug 01 06:10:29 PM PDT 24
Peak memory 217632 kb
Host smart-ca044c5d-e048-48f6-ad4b-ba412e479372
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899347380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.899347380
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.590990663
Short name T360
Test name
Test status
Simulation time 942499783 ps
CPU time 68.26 seconds
Started Aug 01 06:10:15 PM PDT 24
Finished Aug 01 06:11:23 PM PDT 24
Peak memory 219528 kb
Host smart-c5762636-de35-4c04-b79c-c03bb3190e7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590990663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.590990663
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3194361117
Short name T398
Test name
Test status
Simulation time 467629166 ps
CPU time 5.9 seconds
Started Aug 01 06:10:13 PM PDT 24
Finished Aug 01 06:10:19 PM PDT 24
Peak memory 219504 kb
Host smart-5d21bb7d-805a-46aa-ae72-c4fe6396269c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194361117 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3194361117
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1956622380
Short name T380
Test name
Test status
Simulation time 114787586 ps
CPU time 4.17 seconds
Started Aug 01 06:10:14 PM PDT 24
Finished Aug 01 06:10:18 PM PDT 24
Peak memory 218504 kb
Host smart-d2c1a3ff-4cf7-4545-8a7a-fb9330ca69f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956622380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1956622380
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1501945761
Short name T399
Test name
Test status
Simulation time 538477245 ps
CPU time 4.96 seconds
Started Aug 01 06:10:18 PM PDT 24
Finished Aug 01 06:10:23 PM PDT 24
Peak memory 218588 kb
Host smart-4c2bd084-a138-48a3-8bf5-5d603026abd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501945761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1501945761
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2217851745
Short name T352
Test name
Test status
Simulation time 444827620 ps
CPU time 9.3 seconds
Started Aug 01 06:10:19 PM PDT 24
Finished Aug 01 06:10:29 PM PDT 24
Peak memory 216404 kb
Host smart-06ee11df-6128-4db5-960c-7556e89b1ea3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217851745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2217851745
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.859303180
Short name T346
Test name
Test status
Simulation time 137006126 ps
CPU time 5.11 seconds
Started Aug 01 06:10:23 PM PDT 24
Finished Aug 01 06:10:28 PM PDT 24
Peak memory 213004 kb
Host smart-0992117a-dfb9-4c09-b44a-4b9870171b5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859303180 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.859303180
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4041533327
Short name T414
Test name
Test status
Simulation time 133110229 ps
CPU time 4.96 seconds
Started Aug 01 06:10:25 PM PDT 24
Finished Aug 01 06:10:30 PM PDT 24
Peak memory 211268 kb
Host smart-83363251-2623-48d9-a476-3ae077f675f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041533327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.4041533327
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2827816815
Short name T394
Test name
Test status
Simulation time 533279741 ps
CPU time 6.92 seconds
Started Aug 01 06:10:26 PM PDT 24
Finished Aug 01 06:10:33 PM PDT 24
Peak memory 211348 kb
Host smart-e8d7c0fb-9a3a-4ad9-af43-aab1a6b6dd74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827816815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2827816815
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2809414313
Short name T406
Test name
Test status
Simulation time 661507380 ps
CPU time 10.36 seconds
Started Aug 01 06:10:26 PM PDT 24
Finished Aug 01 06:10:36 PM PDT 24
Peak memory 219560 kb
Host smart-c0b96e33-cdae-497c-b4b9-d51fd8f3ab76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809414313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2809414313
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4235379217
Short name T407
Test name
Test status
Simulation time 193124758 ps
CPU time 36.83 seconds
Started Aug 01 06:10:23 PM PDT 24
Finished Aug 01 06:11:00 PM PDT 24
Peak memory 211660 kb
Host smart-48054f30-bca1-44dd-8112-e84a5df072a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235379217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.4235379217
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3101492335
Short name T341
Test name
Test status
Simulation time 496624512 ps
CPU time 5.81 seconds
Started Aug 01 06:10:23 PM PDT 24
Finished Aug 01 06:10:29 PM PDT 24
Peak memory 219804 kb
Host smart-0dd0b43d-4138-4034-9444-2c89d8d83118
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101492335 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3101492335
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3936611475
Short name T105
Test name
Test status
Simulation time 126903185 ps
CPU time 5.13 seconds
Started Aug 01 06:10:26 PM PDT 24
Finished Aug 01 06:10:31 PM PDT 24
Peak memory 218048 kb
Host smart-78e93ca7-7781-449d-af22-ee4177a4e29b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936611475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3936611475
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4283163876
Short name T78
Test name
Test status
Simulation time 95625592 ps
CPU time 6.09 seconds
Started Aug 01 06:10:23 PM PDT 24
Finished Aug 01 06:10:29 PM PDT 24
Peak memory 211344 kb
Host smart-b25bfa88-30b5-4bd3-a9d8-73df07f3a8ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283163876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.4283163876
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1084972306
Short name T354
Test name
Test status
Simulation time 114429768 ps
CPU time 7.03 seconds
Started Aug 01 06:10:22 PM PDT 24
Finished Aug 01 06:10:30 PM PDT 24
Peak memory 214920 kb
Host smart-9e97fbfc-1376-4a99-b5b5-acdd6d7af42e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084972306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1084972306
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1928562339
Short name T118
Test name
Test status
Simulation time 249430752 ps
CPU time 68.96 seconds
Started Aug 01 06:10:23 PM PDT 24
Finished Aug 01 06:11:32 PM PDT 24
Peak memory 213204 kb
Host smart-ab038328-e3d9-44ef-a25b-fec791a1c004
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928562339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1928562339
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4050078148
Short name T369
Test name
Test status
Simulation time 95565728 ps
CPU time 4.83 seconds
Started Aug 01 06:10:23 PM PDT 24
Finished Aug 01 06:10:28 PM PDT 24
Peak memory 216124 kb
Host smart-a56d7dbf-3197-41a1-87aa-5599198398be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050078148 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4050078148
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.100770725
Short name T365
Test name
Test status
Simulation time 278361105 ps
CPU time 4.15 seconds
Started Aug 01 06:10:27 PM PDT 24
Finished Aug 01 06:10:31 PM PDT 24
Peak memory 211264 kb
Host smart-01b0fdf3-cf36-40c0-b92e-6792624ac4f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100770725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.100770725
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3450041483
Short name T401
Test name
Test status
Simulation time 700105576 ps
CPU time 4.33 seconds
Started Aug 01 06:10:26 PM PDT 24
Finished Aug 01 06:10:31 PM PDT 24
Peak memory 219484 kb
Host smart-f4df4832-07db-40d9-a418-5c248dd2d7ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450041483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3450041483
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.664746536
Short name T323
Test name
Test status
Simulation time 86425137 ps
CPU time 6.72 seconds
Started Aug 01 06:10:23 PM PDT 24
Finished Aug 01 06:10:30 PM PDT 24
Peak memory 219620 kb
Host smart-6157e7a0-8474-4db3-bc58-e31cda9cb86f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664746536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.664746536
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1713558045
Short name T393
Test name
Test status
Simulation time 622777784 ps
CPU time 38.53 seconds
Started Aug 01 06:10:27 PM PDT 24
Finished Aug 01 06:11:06 PM PDT 24
Peak memory 219508 kb
Host smart-2c07eee6-a553-46ae-a686-d40551f2e5c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713558045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1713558045
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2254780209
Short name T329
Test name
Test status
Simulation time 419073672 ps
CPU time 5.42 seconds
Started Aug 01 06:10:27 PM PDT 24
Finished Aug 01 06:10:33 PM PDT 24
Peak memory 216292 kb
Host smart-2ee2dd1c-0252-4309-9c31-54b6acb15c0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254780209 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2254780209
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1198229113
Short name T101
Test name
Test status
Simulation time 88825403 ps
CPU time 4.22 seconds
Started Aug 01 06:10:24 PM PDT 24
Finished Aug 01 06:10:28 PM PDT 24
Peak memory 211184 kb
Host smart-c383c139-42ff-45a3-8913-d286bacb9e78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198229113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1198229113
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1318552097
Short name T373
Test name
Test status
Simulation time 577958476 ps
CPU time 7.08 seconds
Started Aug 01 06:10:25 PM PDT 24
Finished Aug 01 06:10:32 PM PDT 24
Peak memory 218888 kb
Host smart-05571086-d78f-4aa1-afb3-4e854bd4756f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318552097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1318552097
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2637131707
Short name T382
Test name
Test status
Simulation time 132915412 ps
CPU time 7.79 seconds
Started Aug 01 06:10:29 PM PDT 24
Finished Aug 01 06:10:37 PM PDT 24
Peak memory 217572 kb
Host smart-8369ce7a-0fa6-4e09-bb5b-07e6003b6cdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637131707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2637131707
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2944823149
Short name T73
Test name
Test status
Simulation time 323418176 ps
CPU time 36.53 seconds
Started Aug 01 06:10:25 PM PDT 24
Finished Aug 01 06:11:02 PM PDT 24
Peak memory 211876 kb
Host smart-d8a1d439-6cf3-4508-9682-e5ecbb58a557
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944823149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2944823149
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.434962557
Short name T337
Test name
Test status
Simulation time 562808089 ps
CPU time 5.76 seconds
Started Aug 01 06:10:23 PM PDT 24
Finished Aug 01 06:10:29 PM PDT 24
Peak memory 219584 kb
Host smart-39dff0c9-e9ef-4b27-b1cc-c5b030820d89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434962557 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.434962557
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1326025085
Short name T345
Test name
Test status
Simulation time 132709225 ps
CPU time 5.14 seconds
Started Aug 01 06:10:23 PM PDT 24
Finished Aug 01 06:10:29 PM PDT 24
Peak memory 211312 kb
Host smart-cc04804e-874a-4bd6-868c-44ec6d4cfc54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326025085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1326025085
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4009395564
Short name T104
Test name
Test status
Simulation time 127470034 ps
CPU time 5.08 seconds
Started Aug 01 06:10:24 PM PDT 24
Finished Aug 01 06:10:30 PM PDT 24
Peak memory 211372 kb
Host smart-ff4ab668-2cf8-4b96-93aa-642b3cf19a60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009395564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.4009395564
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2959855903
Short name T343
Test name
Test status
Simulation time 497751861 ps
CPU time 7.86 seconds
Started Aug 01 06:10:23 PM PDT 24
Finished Aug 01 06:10:31 PM PDT 24
Peak memory 216488 kb
Host smart-7562b9c2-ac88-4d40-89dc-19e57880e8ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959855903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2959855903
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3607619193
Short name T342
Test name
Test status
Simulation time 181126090 ps
CPU time 4.36 seconds
Started Aug 01 06:10:29 PM PDT 24
Finished Aug 01 06:10:33 PM PDT 24
Peak memory 219596 kb
Host smart-45ae6821-aa64-4827-808c-4201aaaba63a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607619193 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3607619193
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.544979013
Short name T396
Test name
Test status
Simulation time 332813073 ps
CPU time 4.14 seconds
Started Aug 01 06:10:24 PM PDT 24
Finished Aug 01 06:10:28 PM PDT 24
Peak memory 218532 kb
Host smart-8e3ee529-08f4-4eb5-9744-07dff7352832
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544979013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.544979013
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1141422496
Short name T385
Test name
Test status
Simulation time 88032427 ps
CPU time 4.22 seconds
Started Aug 01 06:10:24 PM PDT 24
Finished Aug 01 06:10:28 PM PDT 24
Peak memory 211316 kb
Host smart-62ed61be-296c-43a5-b9f1-7444bec6d850
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141422496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1141422496
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4282571069
Short name T330
Test name
Test status
Simulation time 1003157373 ps
CPU time 9.85 seconds
Started Aug 01 06:10:25 PM PDT 24
Finished Aug 01 06:10:35 PM PDT 24
Peak memory 216780 kb
Host smart-3f19926b-0ab5-496c-a627-25e108245d71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282571069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.4282571069
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3715794349
Short name T117
Test name
Test status
Simulation time 489806931 ps
CPU time 43.79 seconds
Started Aug 01 06:10:24 PM PDT 24
Finished Aug 01 06:11:08 PM PDT 24
Peak memory 214192 kb
Host smart-f8bcaf55-1c29-4b12-ab22-43eb8a0bd93c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715794349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3715794349
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1578905362
Short name T333
Test name
Test status
Simulation time 165035122 ps
CPU time 5.79 seconds
Started Aug 01 06:10:23 PM PDT 24
Finished Aug 01 06:10:29 PM PDT 24
Peak memory 219536 kb
Host smart-24405971-1817-469e-acbb-74677df1683f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578905362 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1578905362
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1292081327
Short name T87
Test name
Test status
Simulation time 174834579 ps
CPU time 4.26 seconds
Started Aug 01 06:10:22 PM PDT 24
Finished Aug 01 06:10:27 PM PDT 24
Peak memory 211184 kb
Host smart-380124ba-0e90-403f-bb6d-61bac34567c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292081327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1292081327
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2919474922
Short name T84
Test name
Test status
Simulation time 346601889 ps
CPU time 4.21 seconds
Started Aug 01 06:10:28 PM PDT 24
Finished Aug 01 06:10:33 PM PDT 24
Peak memory 211364 kb
Host smart-9940d73d-677a-4727-a87f-2a1ec482d5ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919474922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2919474922
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4238327953
Short name T392
Test name
Test status
Simulation time 284236767 ps
CPU time 9.67 seconds
Started Aug 01 06:10:26 PM PDT 24
Finished Aug 01 06:10:36 PM PDT 24
Peak memory 216476 kb
Host smart-8a32b228-5c73-4287-8041-73dde066f6d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238327953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4238327953
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3732104240
Short name T376
Test name
Test status
Simulation time 289439008 ps
CPU time 5.97 seconds
Started Aug 01 06:10:38 PM PDT 24
Finished Aug 01 06:10:44 PM PDT 24
Peak memory 214856 kb
Host smart-3b4f6166-bef1-4aba-a786-e11d564ec5a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732104240 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3732104240
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2986050675
Short name T96
Test name
Test status
Simulation time 285634127 ps
CPU time 4.99 seconds
Started Aug 01 06:10:36 PM PDT 24
Finished Aug 01 06:10:41 PM PDT 24
Peak memory 211248 kb
Host smart-33d2e1fd-df3e-4f2d-97b5-3e7d0745e037
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986050675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2986050675
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1340677372
Short name T366
Test name
Test status
Simulation time 437177386 ps
CPU time 4.32 seconds
Started Aug 01 06:10:40 PM PDT 24
Finished Aug 01 06:10:44 PM PDT 24
Peak memory 211304 kb
Host smart-a5d3093a-be09-4390-b1e5-a526e87fc542
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340677372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1340677372
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3784186869
Short name T402
Test name
Test status
Simulation time 262945004 ps
CPU time 8.72 seconds
Started Aug 01 06:10:24 PM PDT 24
Finished Aug 01 06:10:33 PM PDT 24
Peak memory 219684 kb
Host smart-37e4d6e9-dfa4-4870-b641-3ed94afebaa4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784186869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3784186869
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1363009738
Short name T72
Test name
Test status
Simulation time 310882303 ps
CPU time 72.51 seconds
Started Aug 01 06:10:26 PM PDT 24
Finished Aug 01 06:11:39 PM PDT 24
Peak memory 219492 kb
Host smart-99146e48-9cec-4f6e-bc79-ee34d4961d5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363009738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1363009738
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3006060723
Short name T348
Test name
Test status
Simulation time 543646403 ps
CPU time 5.09 seconds
Started Aug 01 06:10:07 PM PDT 24
Finished Aug 01 06:10:12 PM PDT 24
Peak memory 217952 kb
Host smart-da98afbe-c35c-45d4-a56d-bebf5d7dd6d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006060723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3006060723
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.712655978
Short name T328
Test name
Test status
Simulation time 1048336979 ps
CPU time 7.91 seconds
Started Aug 01 06:10:09 PM PDT 24
Finished Aug 01 06:10:17 PM PDT 24
Peak memory 217884 kb
Host smart-e13b5272-1207-41c7-8e46-41e0bb72fd95
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712655978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.712655978
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3163360283
Short name T94
Test name
Test status
Simulation time 371812019 ps
CPU time 5.89 seconds
Started Aug 01 06:10:10 PM PDT 24
Finished Aug 01 06:10:16 PM PDT 24
Peak memory 211272 kb
Host smart-fbd05fac-8422-4ec3-946f-1b3d69c3801f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163360283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3163360283
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.432220264
Short name T410
Test name
Test status
Simulation time 143061115 ps
CPU time 5.43 seconds
Started Aug 01 06:10:09 PM PDT 24
Finished Aug 01 06:10:15 PM PDT 24
Peak memory 214752 kb
Host smart-895b38d7-bd59-46c9-b21d-95a914dfae9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432220264 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.432220264
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2211198164
Short name T409
Test name
Test status
Simulation time 378438323 ps
CPU time 4.02 seconds
Started Aug 01 06:10:15 PM PDT 24
Finished Aug 01 06:10:20 PM PDT 24
Peak memory 211272 kb
Host smart-2bf21765-a9f6-4ded-9157-570086a6a88e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211198164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2211198164
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.980061130
Short name T326
Test name
Test status
Simulation time 1380654083 ps
CPU time 4.14 seconds
Started Aug 01 06:10:10 PM PDT 24
Finished Aug 01 06:10:14 PM PDT 24
Peak memory 211000 kb
Host smart-656d31bc-5c24-4305-b761-0d0d86049621
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980061130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.980061130
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2916474911
Short name T374
Test name
Test status
Simulation time 1140276926 ps
CPU time 5.13 seconds
Started Aug 01 06:10:11 PM PDT 24
Finished Aug 01 06:10:17 PM PDT 24
Peak memory 211192 kb
Host smart-70f619a4-1195-4cdf-bb40-2ce87b8c52a6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916474911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2916474911
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1441293004
Short name T102
Test name
Test status
Simulation time 1381936240 ps
CPU time 4.19 seconds
Started Aug 01 06:10:09 PM PDT 24
Finished Aug 01 06:10:13 PM PDT 24
Peak memory 219520 kb
Host smart-38e6c8a8-83af-4492-8c32-9062b4a9fb26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441293004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1441293004
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3015702929
Short name T334
Test name
Test status
Simulation time 521993337 ps
CPU time 7.22 seconds
Started Aug 01 06:10:10 PM PDT 24
Finished Aug 01 06:10:17 PM PDT 24
Peak memory 215300 kb
Host smart-07a6aea9-a818-4837-9281-ef695a522896
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015702929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3015702929
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4276685230
Short name T405
Test name
Test status
Simulation time 1261134047 ps
CPU time 36.79 seconds
Started Aug 01 06:10:09 PM PDT 24
Finished Aug 01 06:10:46 PM PDT 24
Peak memory 211928 kb
Host smart-ae4da192-ce8d-4ee4-b62d-a5ec0b9d15c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276685230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.4276685230
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2167832648
Short name T98
Test name
Test status
Simulation time 87237743 ps
CPU time 4.23 seconds
Started Aug 01 06:10:14 PM PDT 24
Finished Aug 01 06:10:19 PM PDT 24
Peak memory 211268 kb
Host smart-3b060d23-35f1-4282-be6c-bb1d6fbe752b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167832648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2167832648
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2367104684
Short name T357
Test name
Test status
Simulation time 86282974 ps
CPU time 4.43 seconds
Started Aug 01 06:10:10 PM PDT 24
Finished Aug 01 06:10:15 PM PDT 24
Peak memory 211304 kb
Host smart-f442d0d2-abeb-47d2-a1a2-daf7a27f60ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367104684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2367104684
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2051152293
Short name T95
Test name
Test status
Simulation time 135713330 ps
CPU time 8.16 seconds
Started Aug 01 06:10:13 PM PDT 24
Finished Aug 01 06:10:21 PM PDT 24
Peak memory 211304 kb
Host smart-181d5c49-9f3a-4bb4-a62e-96f003c4d504
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051152293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2051152293
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2134441675
Short name T381
Test name
Test status
Simulation time 151046695 ps
CPU time 5.73 seconds
Started Aug 01 06:10:09 PM PDT 24
Finished Aug 01 06:10:15 PM PDT 24
Peak memory 215280 kb
Host smart-6f466997-bfb2-4059-8ee4-b4280484726e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134441675 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2134441675
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1030234660
Short name T82
Test name
Test status
Simulation time 336461538 ps
CPU time 4.22 seconds
Started Aug 01 06:10:11 PM PDT 24
Finished Aug 01 06:10:16 PM PDT 24
Peak memory 211268 kb
Host smart-cdc7ed44-7555-44f4-9ed0-aafdf1c8f5e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030234660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1030234660
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2490990204
Short name T325
Test name
Test status
Simulation time 128910502 ps
CPU time 5.12 seconds
Started Aug 01 06:10:07 PM PDT 24
Finished Aug 01 06:10:12 PM PDT 24
Peak memory 211156 kb
Host smart-5d2480f4-1fbc-48a3-a598-8662e04f856b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490990204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2490990204
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2115606035
Short name T364
Test name
Test status
Simulation time 404641815 ps
CPU time 4.9 seconds
Started Aug 01 06:10:08 PM PDT 24
Finished Aug 01 06:10:13 PM PDT 24
Peak memory 211108 kb
Host smart-a302063e-1d51-463a-b429-418abf5e2eb8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115606035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2115606035
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2643686972
Short name T362
Test name
Test status
Simulation time 175467995 ps
CPU time 4.17 seconds
Started Aug 01 06:10:10 PM PDT 24
Finished Aug 01 06:10:14 PM PDT 24
Peak memory 211304 kb
Host smart-ad01a44c-6801-43ae-a04d-ad4af0761e2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643686972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2643686972
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.84502770
Short name T363
Test name
Test status
Simulation time 89041172 ps
CPU time 6.24 seconds
Started Aug 01 06:10:09 PM PDT 24
Finished Aug 01 06:10:16 PM PDT 24
Peak memory 215436 kb
Host smart-631de2b9-f3b8-42a4-8d16-6c440358b875
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84502770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.84502770
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.943709379
Short name T85
Test name
Test status
Simulation time 157589378 ps
CPU time 5.1 seconds
Started Aug 01 06:10:12 PM PDT 24
Finished Aug 01 06:10:18 PM PDT 24
Peak memory 211284 kb
Host smart-17e0ebc8-50e1-4ee9-beda-aeb764106a99
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943709379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.943709379
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.91667265
Short name T338
Test name
Test status
Simulation time 127282373 ps
CPU time 5.39 seconds
Started Aug 01 06:10:13 PM PDT 24
Finished Aug 01 06:10:19 PM PDT 24
Peak memory 218104 kb
Host smart-85be6d52-a3fb-449e-bb47-5e888324234a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91667265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_ba
sh.91667265
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1040632374
Short name T358
Test name
Test status
Simulation time 91747147 ps
CPU time 5.73 seconds
Started Aug 01 06:10:08 PM PDT 24
Finished Aug 01 06:10:14 PM PDT 24
Peak memory 219080 kb
Host smart-6fc2b3d2-bba6-4002-aef3-bb18e6cd0a0b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040632374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1040632374
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3695449001
Short name T335
Test name
Test status
Simulation time 274554131 ps
CPU time 6.21 seconds
Started Aug 01 06:10:13 PM PDT 24
Finished Aug 01 06:10:20 PM PDT 24
Peak memory 216416 kb
Host smart-1e7d143c-f3c4-43be-a60e-5be2e5d1adce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695449001 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3695449001
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2624914411
Short name T375
Test name
Test status
Simulation time 496242176 ps
CPU time 5.09 seconds
Started Aug 01 06:10:09 PM PDT 24
Finished Aug 01 06:10:14 PM PDT 24
Peak memory 211320 kb
Host smart-4a88dec4-40c5-4589-9d5c-5678ee86b0b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624914411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2624914411
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1467747419
Short name T324
Test name
Test status
Simulation time 86232685 ps
CPU time 4.24 seconds
Started Aug 01 06:10:07 PM PDT 24
Finished Aug 01 06:10:12 PM PDT 24
Peak memory 211196 kb
Host smart-22355e65-d8cb-494b-96d8-4fbe70984e1d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467747419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1467747419
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2452218753
Short name T390
Test name
Test status
Simulation time 131183977 ps
CPU time 4.94 seconds
Started Aug 01 06:10:09 PM PDT 24
Finished Aug 01 06:10:14 PM PDT 24
Peak memory 211176 kb
Host smart-e3c77704-0dff-4c0b-978f-ee714775c2e8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452218753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2452218753
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4226216483
Short name T103
Test name
Test status
Simulation time 132146543 ps
CPU time 4.97 seconds
Started Aug 01 06:10:11 PM PDT 24
Finished Aug 01 06:10:16 PM PDT 24
Peak memory 211344 kb
Host smart-7a7f8703-ae29-4057-b33c-7de118bad085
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226216483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.4226216483
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1373951363
Short name T340
Test name
Test status
Simulation time 86094028 ps
CPU time 6.7 seconds
Started Aug 01 06:10:09 PM PDT 24
Finished Aug 01 06:10:16 PM PDT 24
Peak memory 216300 kb
Host smart-b5789242-6755-49c9-93d1-24ed8726c806
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373951363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1373951363
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.631943194
Short name T356
Test name
Test status
Simulation time 2519053593 ps
CPU time 71.71 seconds
Started Aug 01 06:10:09 PM PDT 24
Finished Aug 01 06:11:20 PM PDT 24
Peak memory 219584 kb
Host smart-11bb0e88-82d0-451e-b14a-29b6d8d79066
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631943194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.631943194
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1662018740
Short name T377
Test name
Test status
Simulation time 287085761 ps
CPU time 6.02 seconds
Started Aug 01 06:10:15 PM PDT 24
Finished Aug 01 06:10:21 PM PDT 24
Peak memory 219568 kb
Host smart-24f389a4-1f31-4656-bf9a-12badc34a66a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662018740 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1662018740
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.455793927
Short name T412
Test name
Test status
Simulation time 1037675556 ps
CPU time 5.08 seconds
Started Aug 01 06:10:21 PM PDT 24
Finished Aug 01 06:10:26 PM PDT 24
Peak memory 211288 kb
Host smart-fc671591-5a49-4288-81c1-bbfb97044aed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455793927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.455793927
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.147017588
Short name T378
Test name
Test status
Simulation time 132940400 ps
CPU time 5.23 seconds
Started Aug 01 06:10:19 PM PDT 24
Finished Aug 01 06:10:24 PM PDT 24
Peak memory 211312 kb
Host smart-c198aced-f376-49e7-a65a-17fdbc9217c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147017588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.147017588
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2244619042
Short name T332
Test name
Test status
Simulation time 347692880 ps
CPU time 6.31 seconds
Started Aug 01 06:10:09 PM PDT 24
Finished Aug 01 06:10:15 PM PDT 24
Peak memory 216516 kb
Host smart-b9d52288-fbbd-430a-a7cc-b582f3d7693d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244619042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2244619042
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.497539639
Short name T371
Test name
Test status
Simulation time 311807822 ps
CPU time 36.33 seconds
Started Aug 01 06:10:10 PM PDT 24
Finished Aug 01 06:10:47 PM PDT 24
Peak memory 213816 kb
Host smart-1f8bda02-edee-4a85-bdec-60785feb69e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497539639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.497539639
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2700234121
Short name T384
Test name
Test status
Simulation time 971346971 ps
CPU time 6.19 seconds
Started Aug 01 06:10:14 PM PDT 24
Finished Aug 01 06:10:20 PM PDT 24
Peak memory 219628 kb
Host smart-e8474409-7d16-4390-9808-9918ee178050
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700234121 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2700234121
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1940781364
Short name T379
Test name
Test status
Simulation time 249153362 ps
CPU time 4.96 seconds
Started Aug 01 06:10:16 PM PDT 24
Finished Aug 01 06:10:21 PM PDT 24
Peak memory 211324 kb
Host smart-c3f0c056-2a3e-4844-bce3-c2360960e480
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940781364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1940781364
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1945004249
Short name T83
Test name
Test status
Simulation time 5455488326 ps
CPU time 7.46 seconds
Started Aug 01 06:10:12 PM PDT 24
Finished Aug 01 06:10:20 PM PDT 24
Peak memory 219068 kb
Host smart-c3c6b848-474f-4d33-8b4f-95b62f54fa6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945004249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1945004249
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1087205553
Short name T108
Test name
Test status
Simulation time 305541473 ps
CPU time 10.13 seconds
Started Aug 01 06:10:17 PM PDT 24
Finished Aug 01 06:10:28 PM PDT 24
Peak memory 219612 kb
Host smart-32644cf7-2f1a-444b-8fb2-3bb6fd73cf48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087205553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1087205553
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.959312229
Short name T112
Test name
Test status
Simulation time 718165730 ps
CPU time 72.63 seconds
Started Aug 01 06:10:15 PM PDT 24
Finished Aug 01 06:11:28 PM PDT 24
Peak memory 213032 kb
Host smart-5500fe6e-d2fb-4100-a318-d47de04c0e05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959312229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.959312229
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1924555000
Short name T327
Test name
Test status
Simulation time 95029258 ps
CPU time 4.63 seconds
Started Aug 01 06:10:14 PM PDT 24
Finished Aug 01 06:10:19 PM PDT 24
Peak memory 213576 kb
Host smart-3895e45b-502b-4f60-916a-de46ad1eb043
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924555000 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1924555000
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2064066906
Short name T331
Test name
Test status
Simulation time 86116314 ps
CPU time 4.26 seconds
Started Aug 01 06:10:14 PM PDT 24
Finished Aug 01 06:10:18 PM PDT 24
Peak memory 211276 kb
Host smart-fe9bd84b-80ee-41c3-842e-ab8a9be43e09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064066906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2064066906
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.319352593
Short name T99
Test name
Test status
Simulation time 550976690 ps
CPU time 21.13 seconds
Started Aug 01 06:10:15 PM PDT 24
Finished Aug 01 06:10:36 PM PDT 24
Peak memory 211368 kb
Host smart-32a86d66-ab95-4510-9580-7629b50e5896
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319352593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.319352593
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3791542493
Short name T368
Test name
Test status
Simulation time 149658428 ps
CPU time 5.13 seconds
Started Aug 01 06:10:18 PM PDT 24
Finished Aug 01 06:10:23 PM PDT 24
Peak memory 211308 kb
Host smart-8a3787f3-de45-4096-9fe7-012de11cf231
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791542493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3791542493
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1012157358
Short name T389
Test name
Test status
Simulation time 521555222 ps
CPU time 7.73 seconds
Started Aug 01 06:10:18 PM PDT 24
Finished Aug 01 06:10:26 PM PDT 24
Peak memory 216676 kb
Host smart-911bcd6a-a001-42ac-8444-5ff399c49eba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012157358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1012157358
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2890425062
Short name T116
Test name
Test status
Simulation time 1061494959 ps
CPU time 69.13 seconds
Started Aug 01 06:10:12 PM PDT 24
Finished Aug 01 06:11:21 PM PDT 24
Peak memory 213064 kb
Host smart-67bd71d7-5eff-47d7-9386-e65e4a486874
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890425062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2890425062
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4063360251
Short name T361
Test name
Test status
Simulation time 1759127146 ps
CPU time 5.31 seconds
Started Aug 01 06:10:18 PM PDT 24
Finished Aug 01 06:10:23 PM PDT 24
Peak memory 219580 kb
Host smart-19ddabd1-3c45-4659-a1ab-a058b13cf62a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063360251 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4063360251
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1274643617
Short name T359
Test name
Test status
Simulation time 131257579 ps
CPU time 5.08 seconds
Started Aug 01 06:10:14 PM PDT 24
Finished Aug 01 06:10:20 PM PDT 24
Peak memory 211304 kb
Host smart-bd16de7a-4990-476b-b07f-166676334fe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274643617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1274643617
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.48196092
Short name T395
Test name
Test status
Simulation time 377462988 ps
CPU time 18.33 seconds
Started Aug 01 06:10:17 PM PDT 24
Finished Aug 01 06:10:35 PM PDT 24
Peak memory 211336 kb
Host smart-83df9aa1-2e10-4a48-ae1d-92e69ea2b2a9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48196092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pass
thru_mem_tl_intg_err.48196092
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3554787676
Short name T106
Test name
Test status
Simulation time 255339082 ps
CPU time 4.84 seconds
Started Aug 01 06:10:16 PM PDT 24
Finished Aug 01 06:10:21 PM PDT 24
Peak memory 211256 kb
Host smart-e6fd4d52-0689-47f3-8f2d-f6fb87099f36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554787676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3554787676
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3159432750
Short name T387
Test name
Test status
Simulation time 491183838 ps
CPU time 8.06 seconds
Started Aug 01 06:10:11 PM PDT 24
Finished Aug 01 06:10:19 PM PDT 24
Peak memory 217004 kb
Host smart-3b8501f4-a79c-4195-aaba-d8cee91b9c38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159432750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3159432750
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.626532897
Short name T109
Test name
Test status
Simulation time 330647702 ps
CPU time 69.4 seconds
Started Aug 01 06:10:21 PM PDT 24
Finished Aug 01 06:11:31 PM PDT 24
Peak memory 219504 kb
Host smart-b86ae3a5-e341-4f22-8da4-00f3d3928623
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626532897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.626532897
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2658044630
Short name T347
Test name
Test status
Simulation time 415288734 ps
CPU time 4.8 seconds
Started Aug 01 06:10:21 PM PDT 24
Finished Aug 01 06:10:26 PM PDT 24
Peak memory 215492 kb
Host smart-1da4b572-4a2e-4d3f-8588-3493a92cb400
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658044630 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2658044630
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2573707214
Short name T370
Test name
Test status
Simulation time 333772058 ps
CPU time 4.03 seconds
Started Aug 01 06:10:17 PM PDT 24
Finished Aug 01 06:10:21 PM PDT 24
Peak memory 211288 kb
Host smart-66d856f2-4c5f-4ecd-ba71-0e75d14243a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573707214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2573707214
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1900919735
Short name T391
Test name
Test status
Simulation time 85669057 ps
CPU time 4.36 seconds
Started Aug 01 06:10:21 PM PDT 24
Finished Aug 01 06:10:26 PM PDT 24
Peak memory 218724 kb
Host smart-0e4870e0-ffa1-445f-8f53-b9e823103342
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900919735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1900919735
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2485547687
Short name T388
Test name
Test status
Simulation time 92020301 ps
CPU time 7.64 seconds
Started Aug 01 06:10:13 PM PDT 24
Finished Aug 01 06:10:21 PM PDT 24
Peak memory 216676 kb
Host smart-d63b8b53-6ce6-4994-92f4-08a20d6196dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485547687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2485547687
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2723956788
Short name T115
Test name
Test status
Simulation time 471374045 ps
CPU time 67.77 seconds
Started Aug 01 06:10:14 PM PDT 24
Finished Aug 01 06:11:22 PM PDT 24
Peak memory 213004 kb
Host smart-794d70bb-da50-4464-a8a8-00d984997d3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723956788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2723956788
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3774322886
Short name T248
Test name
Test status
Simulation time 519464036 ps
CPU time 5.13 seconds
Started Aug 01 06:08:58 PM PDT 24
Finished Aug 01 06:09:04 PM PDT 24
Peak memory 212004 kb
Host smart-c2132f61-151a-4615-9cdd-8ff63cd500a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774322886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3774322886
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1998741998
Short name T180
Test name
Test status
Simulation time 1703338941 ps
CPU time 80.23 seconds
Started Aug 01 06:09:00 PM PDT 24
Finished Aug 01 06:10:20 PM PDT 24
Peak memory 238324 kb
Host smart-fc176183-a760-42fd-ae89-503315b626e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998741998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1998741998
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2876084346
Short name T251
Test name
Test status
Simulation time 410846731 ps
CPU time 5.39 seconds
Started Aug 01 06:08:57 PM PDT 24
Finished Aug 01 06:09:03 PM PDT 24
Peak memory 212124 kb
Host smart-dfc1517b-bdb2-46fa-ab7f-51653130734c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2876084346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2876084346
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1199884956
Short name T205
Test name
Test status
Simulation time 1027933896 ps
CPU time 12.53 seconds
Started Aug 01 06:09:00 PM PDT 24
Finished Aug 01 06:09:13 PM PDT 24
Peak memory 216172 kb
Host smart-44634f14-0804-47ec-b68c-a97d0ea43d56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199884956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1199884956
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1997963116
Short name T306
Test name
Test status
Simulation time 898088563 ps
CPU time 5.22 seconds
Started Aug 01 06:09:10 PM PDT 24
Finished Aug 01 06:09:15 PM PDT 24
Peak memory 212000 kb
Host smart-66c6accb-b9d4-474a-a730-0a13fccb7150
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997963116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1997963116
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2620257576
Short name T185
Test name
Test status
Simulation time 6220185819 ps
CPU time 85.66 seconds
Started Aug 01 06:09:00 PM PDT 24
Finished Aug 01 06:10:26 PM PDT 24
Peak memory 229032 kb
Host smart-20c70f2a-e9a7-4e08-8201-b3f59ac585fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620257576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2620257576
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.941821285
Short name T240
Test name
Test status
Simulation time 255868938 ps
CPU time 11.36 seconds
Started Aug 01 06:08:58 PM PDT 24
Finished Aug 01 06:09:09 PM PDT 24
Peak memory 212864 kb
Host smart-7d0f7f94-3edf-4a30-808a-1336982a258a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941821285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.941821285
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2000976014
Short name T122
Test name
Test status
Simulation time 192086643 ps
CPU time 5.62 seconds
Started Aug 01 06:09:05 PM PDT 24
Finished Aug 01 06:09:11 PM PDT 24
Peak memory 212184 kb
Host smart-2bf22079-274d-4e91-819b-8a440f74798f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2000976014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2000976014
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.4121312903
Short name T35
Test name
Test status
Simulation time 144062676 ps
CPU time 52.05 seconds
Started Aug 01 06:09:01 PM PDT 24
Finished Aug 01 06:09:53 PM PDT 24
Peak memory 237312 kb
Host smart-dd37fcd9-39a0-417c-900e-58e03ff21355
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121312903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.4121312903
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2282455967
Short name T219
Test name
Test status
Simulation time 99788341 ps
CPU time 5.74 seconds
Started Aug 01 06:08:59 PM PDT 24
Finished Aug 01 06:09:05 PM PDT 24
Peak memory 212132 kb
Host smart-16975ec1-19c6-40fa-9a90-85e466f661bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282455967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2282455967
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1762125438
Short name T318
Test name
Test status
Simulation time 422291367 ps
CPU time 17.05 seconds
Started Aug 01 06:09:00 PM PDT 24
Finished Aug 01 06:09:17 PM PDT 24
Peak memory 215044 kb
Host smart-11b7fb7c-7d90-4985-99fc-8cd0ff984038
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762125438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1762125438
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2209396250
Short name T314
Test name
Test status
Simulation time 255742365 ps
CPU time 5.17 seconds
Started Aug 01 06:09:25 PM PDT 24
Finished Aug 01 06:09:30 PM PDT 24
Peak memory 211988 kb
Host smart-528365b5-cb56-46ff-8eef-7714c22f6ff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209396250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2209396250
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2216663986
Short name T43
Test name
Test status
Simulation time 6894838894 ps
CPU time 72.45 seconds
Started Aug 01 06:09:21 PM PDT 24
Finished Aug 01 06:10:34 PM PDT 24
Peak memory 237048 kb
Host smart-3b9efb30-8048-4f95-a46c-6eb198261aaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216663986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2216663986
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1386042491
Short name T5
Test name
Test status
Simulation time 998144994 ps
CPU time 11.24 seconds
Started Aug 01 06:09:19 PM PDT 24
Finished Aug 01 06:09:30 PM PDT 24
Peak memory 212172 kb
Host smart-5461d21d-379d-447e-89a6-66d6c221fa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386042491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1386042491
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3981068247
Short name T254
Test name
Test status
Simulation time 290332766 ps
CPU time 6.54 seconds
Started Aug 01 06:09:09 PM PDT 24
Finished Aug 01 06:09:16 PM PDT 24
Peak memory 212140 kb
Host smart-ff96c709-9a56-4635-b9e3-b99618d90d6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3981068247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3981068247
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1558700221
Short name T90
Test name
Test status
Simulation time 311004215 ps
CPU time 14.31 seconds
Started Aug 01 06:09:17 PM PDT 24
Finished Aug 01 06:09:31 PM PDT 24
Peak memory 214064 kb
Host smart-bce2ad77-80b0-4cd9-a77f-667f9ac18d2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558700221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1558700221
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.4196431960
Short name T192
Test name
Test status
Simulation time 130582112 ps
CPU time 4.97 seconds
Started Aug 01 06:09:17 PM PDT 24
Finished Aug 01 06:09:22 PM PDT 24
Peak memory 211948 kb
Host smart-ffddf141-f59b-43e0-add7-5fe8c348f3ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196431960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.4196431960
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3250271597
Short name T288
Test name
Test status
Simulation time 2760274981 ps
CPU time 83.11 seconds
Started Aug 01 06:09:20 PM PDT 24
Finished Aug 01 06:10:43 PM PDT 24
Peak memory 213464 kb
Host smart-6dd888cf-fc74-45a2-bfc2-8cb193e50806
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250271597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3250271597
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2237917802
Short name T126
Test name
Test status
Simulation time 170168701 ps
CPU time 9.42 seconds
Started Aug 01 06:09:20 PM PDT 24
Finished Aug 01 06:09:29 PM PDT 24
Peak memory 213004 kb
Host smart-b06dc5e3-6b74-455b-bc10-375df731c3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237917802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2237917802
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2803799197
Short name T182
Test name
Test status
Simulation time 209120085 ps
CPU time 13.83 seconds
Started Aug 01 06:09:21 PM PDT 24
Finished Aug 01 06:09:35 PM PDT 24
Peak memory 213436 kb
Host smart-42e46798-e5bd-43e9-b662-62634e6c5cb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803799197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2803799197
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3374830229
Short name T181
Test name
Test status
Simulation time 346540992 ps
CPU time 4.28 seconds
Started Aug 01 06:09:13 PM PDT 24
Finished Aug 01 06:09:18 PM PDT 24
Peak memory 212020 kb
Host smart-b2c21e8f-be84-4faa-a49d-436c9b9804d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374830229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3374830229
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4132698424
Short name T217
Test name
Test status
Simulation time 8346662098 ps
CPU time 85.18 seconds
Started Aug 01 06:09:19 PM PDT 24
Finished Aug 01 06:10:45 PM PDT 24
Peak memory 238468 kb
Host smart-c252e381-7bfe-470f-9316-cb1628ad7307
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132698424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.4132698424
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.848807866
Short name T11
Test name
Test status
Simulation time 671394057 ps
CPU time 9.49 seconds
Started Aug 01 06:09:20 PM PDT 24
Finished Aug 01 06:09:30 PM PDT 24
Peak memory 212904 kb
Host smart-65231799-c2db-42bc-a16d-b71f8a7c5b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848807866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.848807866
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3595165201
Short name T71
Test name
Test status
Simulation time 144321903 ps
CPU time 6.53 seconds
Started Aug 01 06:09:17 PM PDT 24
Finished Aug 01 06:09:24 PM PDT 24
Peak memory 212080 kb
Host smart-442c4bec-3edb-437e-9b2d-bd98dbcd814f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3595165201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3595165201
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.4189817611
Short name T133
Test name
Test status
Simulation time 528634425 ps
CPU time 22.36 seconds
Started Aug 01 06:09:18 PM PDT 24
Finished Aug 01 06:09:40 PM PDT 24
Peak memory 215848 kb
Host smart-c33f9f19-391b-4430-b9e8-3a24dc3cd809
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189817611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.4189817611
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1687052028
Short name T60
Test name
Test status
Simulation time 270454110983 ps
CPU time 10077.4 seconds
Started Aug 01 06:09:14 PM PDT 24
Finished Aug 01 08:57:13 PM PDT 24
Peak memory 236612 kb
Host smart-f3c723d7-896b-4023-bafa-f8bc731064df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687052028 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.1687052028
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3036478240
Short name T291
Test name
Test status
Simulation time 126447809 ps
CPU time 5.04 seconds
Started Aug 01 06:09:19 PM PDT 24
Finished Aug 01 06:09:24 PM PDT 24
Peak memory 212076 kb
Host smart-758d49bb-5e5e-4ff1-a726-445787934af1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036478240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3036478240
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3561925413
Short name T57
Test name
Test status
Simulation time 2318637450 ps
CPU time 112.94 seconds
Started Aug 01 06:09:22 PM PDT 24
Finished Aug 01 06:11:15 PM PDT 24
Peak memory 238464 kb
Host smart-3653daad-b005-405b-8e7a-b52d29475109
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561925413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3561925413
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.793051159
Short name T210
Test name
Test status
Simulation time 252298487 ps
CPU time 11.43 seconds
Started Aug 01 06:09:15 PM PDT 24
Finished Aug 01 06:09:26 PM PDT 24
Peak memory 212800 kb
Host smart-e599d754-54ff-4c1a-a846-10736f37d852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793051159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.793051159
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1853248478
Short name T25
Test name
Test status
Simulation time 534604896 ps
CPU time 6.38 seconds
Started Aug 01 06:09:21 PM PDT 24
Finished Aug 01 06:09:27 PM PDT 24
Peak memory 212160 kb
Host smart-00618f65-ba23-4d49-84d8-d757b64e5c23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853248478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1853248478
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2313006023
Short name T69
Test name
Test status
Simulation time 270327365 ps
CPU time 16.47 seconds
Started Aug 01 06:09:17 PM PDT 24
Finished Aug 01 06:09:34 PM PDT 24
Peak memory 214672 kb
Host smart-ab7bc468-e447-48e8-a76f-74c82de1f630
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313006023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2313006023
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.963947396
Short name T10
Test name
Test status
Simulation time 171842939 ps
CPU time 4.23 seconds
Started Aug 01 06:09:19 PM PDT 24
Finished Aug 01 06:09:23 PM PDT 24
Peak memory 211988 kb
Host smart-b61dfaa3-bbe7-4038-8b5b-7394141fcf53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963947396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.963947396
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.533799499
Short name T27
Test name
Test status
Simulation time 10321571270 ps
CPU time 134.59 seconds
Started Aug 01 06:09:18 PM PDT 24
Finished Aug 01 06:11:33 PM PDT 24
Peak memory 235500 kb
Host smart-da445445-3ae1-4a72-9fba-f9d873e9a053
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533799499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.533799499
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2915133686
Short name T278
Test name
Test status
Simulation time 195786085 ps
CPU time 5.43 seconds
Started Aug 01 06:09:20 PM PDT 24
Finished Aug 01 06:09:26 PM PDT 24
Peak memory 212172 kb
Host smart-7d35d7be-a4a2-4bca-8111-9414410acc24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2915133686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2915133686
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.431616645
Short name T195
Test name
Test status
Simulation time 946519991 ps
CPU time 14.06 seconds
Started Aug 01 06:09:20 PM PDT 24
Finished Aug 01 06:09:34 PM PDT 24
Peak memory 214032 kb
Host smart-13ad1ed6-4e2a-44fb-a690-80a480982a99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431616645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.431616645
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3414551650
Short name T194
Test name
Test status
Simulation time 20184802058 ps
CPU time 8466.54 seconds
Started Aug 01 06:09:16 PM PDT 24
Finished Aug 01 08:30:23 PM PDT 24
Peak memory 236648 kb
Host smart-8a785de3-daaf-4306-a565-f230ed9f83ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414551650 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3414551650
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.737812741
Short name T235
Test name
Test status
Simulation time 183367458 ps
CPU time 4.44 seconds
Started Aug 01 06:09:20 PM PDT 24
Finished Aug 01 06:09:24 PM PDT 24
Peak memory 211976 kb
Host smart-8e9a69c0-0c24-4163-9b22-ba17741d31e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737812741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.737812741
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3766122927
Short name T120
Test name
Test status
Simulation time 5171804802 ps
CPU time 117.36 seconds
Started Aug 01 06:09:26 PM PDT 24
Finished Aug 01 06:11:24 PM PDT 24
Peak memory 215484 kb
Host smart-d9abfbf2-796f-43f4-a5e1-7f0193cf69ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766122927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3766122927
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1759306475
Short name T158
Test name
Test status
Simulation time 1381856487 ps
CPU time 10.91 seconds
Started Aug 01 06:09:27 PM PDT 24
Finished Aug 01 06:09:38 PM PDT 24
Peak memory 212920 kb
Host smart-86d87413-6f08-49fd-a36c-be8cbeb6ce61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759306475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1759306475
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3322148376
Short name T123
Test name
Test status
Simulation time 359929510 ps
CPU time 6.63 seconds
Started Aug 01 06:09:15 PM PDT 24
Finished Aug 01 06:09:22 PM PDT 24
Peak memory 212120 kb
Host smart-4cbb185a-b61c-4779-befe-bf3db231dd09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3322148376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3322148376
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3568078313
Short name T7
Test name
Test status
Simulation time 282225783 ps
CPU time 13.75 seconds
Started Aug 01 06:09:15 PM PDT 24
Finished Aug 01 06:09:29 PM PDT 24
Peak memory 214936 kb
Host smart-ff35c053-9b9c-427c-a037-03d9ac9e8017
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568078313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3568078313
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1600611943
Short name T148
Test name
Test status
Simulation time 133577591 ps
CPU time 5.09 seconds
Started Aug 01 06:09:19 PM PDT 24
Finished Aug 01 06:09:25 PM PDT 24
Peak memory 212028 kb
Host smart-ce845c45-f8fa-484d-bda8-7186f1e03733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600611943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1600611943
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.199729692
Short name T287
Test name
Test status
Simulation time 25740566031 ps
CPU time 131.53 seconds
Started Aug 01 06:09:25 PM PDT 24
Finished Aug 01 06:11:37 PM PDT 24
Peak memory 234712 kb
Host smart-5ae81b2b-4bc8-4d90-8373-10c177b99cd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199729692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.199729692
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2645899362
Short name T242
Test name
Test status
Simulation time 996713981 ps
CPU time 11.6 seconds
Started Aug 01 06:09:25 PM PDT 24
Finished Aug 01 06:09:36 PM PDT 24
Peak memory 212896 kb
Host smart-eb77421f-b7bb-4ad5-b511-662f71db4ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645899362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2645899362
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1398053795
Short name T163
Test name
Test status
Simulation time 142300017 ps
CPU time 6.13 seconds
Started Aug 01 06:09:28 PM PDT 24
Finished Aug 01 06:09:35 PM PDT 24
Peak memory 212168 kb
Host smart-69d13d72-8e1f-4ba6-a462-1072ae881d8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1398053795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1398053795
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.3216425740
Short name T221
Test name
Test status
Simulation time 19574549586 ps
CPU time 9429.18 seconds
Started Aug 01 06:09:24 PM PDT 24
Finished Aug 01 08:46:34 PM PDT 24
Peak memory 236636 kb
Host smart-68c2e168-4efe-46ae-b0f8-8233f22c5960
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216425740 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.3216425740
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.566928278
Short name T206
Test name
Test status
Simulation time 90143148 ps
CPU time 4.26 seconds
Started Aug 01 06:09:20 PM PDT 24
Finished Aug 01 06:09:25 PM PDT 24
Peak memory 212036 kb
Host smart-9f9d4af4-58d2-4ea8-9016-601f5cc3af1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566928278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.566928278
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1592052065
Short name T257
Test name
Test status
Simulation time 6203844352 ps
CPU time 126.08 seconds
Started Aug 01 06:09:17 PM PDT 24
Finished Aug 01 06:11:24 PM PDT 24
Peak memory 226304 kb
Host smart-176985a1-92f7-4bf5-9254-922e92fb6c3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592052065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1592052065
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.638606852
Short name T17
Test name
Test status
Simulation time 498055837 ps
CPU time 11.5 seconds
Started Aug 01 06:09:29 PM PDT 24
Finished Aug 01 06:09:41 PM PDT 24
Peak memory 212968 kb
Host smart-3caf6252-2b65-4b5b-bf34-44fabed45d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638606852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.638606852
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.8834261
Short name T261
Test name
Test status
Simulation time 142284505 ps
CPU time 6.37 seconds
Started Aug 01 06:09:29 PM PDT 24
Finished Aug 01 06:09:35 PM PDT 24
Peak memory 212160 kb
Host smart-d2b6ff0d-3129-46eb-aebc-a3886ebb202e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=8834261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.8834261
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.167977789
Short name T259
Test name
Test status
Simulation time 396589644 ps
CPU time 13.3 seconds
Started Aug 01 06:09:20 PM PDT 24
Finished Aug 01 06:09:33 PM PDT 24
Peak memory 214068 kb
Host smart-a02c39af-9d7b-442c-a36c-59ce2dff1836
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167977789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.167977789
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.4125002734
Short name T295
Test name
Test status
Simulation time 110354426 ps
CPU time 4.3 seconds
Started Aug 01 06:09:19 PM PDT 24
Finished Aug 01 06:09:24 PM PDT 24
Peak memory 212012 kb
Host smart-d884b485-591c-43f0-b0ad-cd0b23091cf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125002734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.4125002734
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2954640001
Short name T51
Test name
Test status
Simulation time 1137016911 ps
CPU time 79.27 seconds
Started Aug 01 06:09:28 PM PDT 24
Finished Aug 01 06:10:48 PM PDT 24
Peak memory 233244 kb
Host smart-8ba4bf1f-8dd2-4ee8-be49-f692e6640b65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954640001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2954640001
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3392646415
Short name T55
Test name
Test status
Simulation time 175714749 ps
CPU time 9.43 seconds
Started Aug 01 06:09:18 PM PDT 24
Finished Aug 01 06:09:28 PM PDT 24
Peak memory 212836 kb
Host smart-c850cf9d-4eb9-418a-b01e-771266bf184f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392646415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3392646415
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1831961635
Short name T13
Test name
Test status
Simulation time 379699000 ps
CPU time 5.29 seconds
Started Aug 01 06:09:27 PM PDT 24
Finished Aug 01 06:09:33 PM PDT 24
Peak memory 212132 kb
Host smart-83cd3ced-b47b-4e96-b4d2-9d2bc2cfa6cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1831961635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1831961635
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2983496584
Short name T127
Test name
Test status
Simulation time 445612242 ps
CPU time 7.59 seconds
Started Aug 01 06:09:20 PM PDT 24
Finished Aug 01 06:09:27 PM PDT 24
Peak memory 211980 kb
Host smart-42554bb5-8910-4cee-832c-25fd1e5585a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983496584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2983496584
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3888564462
Short name T177
Test name
Test status
Simulation time 87385486 ps
CPU time 4.21 seconds
Started Aug 01 06:09:20 PM PDT 24
Finished Aug 01 06:09:25 PM PDT 24
Peak memory 212032 kb
Host smart-e0f887ff-ca01-4642-aa73-0a25934bad14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888564462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3888564462
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.633301268
Short name T52
Test name
Test status
Simulation time 6433037802 ps
CPU time 194.19 seconds
Started Aug 01 06:09:18 PM PDT 24
Finished Aug 01 06:12:32 PM PDT 24
Peak memory 238432 kb
Host smart-0992556f-32de-4b83-811a-05f5af083223
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633301268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.633301268
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3382618493
Short name T197
Test name
Test status
Simulation time 763680407 ps
CPU time 9.81 seconds
Started Aug 01 06:09:18 PM PDT 24
Finished Aug 01 06:09:28 PM PDT 24
Peak memory 212892 kb
Host smart-90ecfbdc-dc0a-4441-b658-e6ee82123cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382618493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3382618493
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3806766543
Short name T215
Test name
Test status
Simulation time 276985064 ps
CPU time 6.57 seconds
Started Aug 01 06:09:26 PM PDT 24
Finished Aug 01 06:09:33 PM PDT 24
Peak memory 212136 kb
Host smart-87e84fca-8fe1-421b-9c5e-3d7d36a02dd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3806766543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3806766543
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3039910239
Short name T271
Test name
Test status
Simulation time 254637256 ps
CPU time 5.14 seconds
Started Aug 01 06:09:12 PM PDT 24
Finished Aug 01 06:09:17 PM PDT 24
Peak memory 212032 kb
Host smart-ec8586aa-62da-4caf-aadf-cbfd481b793b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039910239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3039910239
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2168713273
Short name T49
Test name
Test status
Simulation time 4993129484 ps
CPU time 144.76 seconds
Started Aug 01 06:09:16 PM PDT 24
Finished Aug 01 06:11:41 PM PDT 24
Peak memory 241460 kb
Host smart-07d76f1b-e0a8-49ec-8bc1-3a216dbbb177
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168713273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2168713273
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1153785100
Short name T239
Test name
Test status
Simulation time 264549793 ps
CPU time 11.24 seconds
Started Aug 01 06:09:11 PM PDT 24
Finished Aug 01 06:09:22 PM PDT 24
Peak memory 212968 kb
Host smart-2b3daf99-7ace-4613-ae3c-00d8faabebce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153785100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1153785100
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4065124058
Short name T172
Test name
Test status
Simulation time 623448670 ps
CPU time 5.71 seconds
Started Aug 01 06:09:11 PM PDT 24
Finished Aug 01 06:09:17 PM PDT 24
Peak memory 212088 kb
Host smart-22e206f9-eb98-4726-b571-d14328431649
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4065124058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.4065124058
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3634771382
Short name T31
Test name
Test status
Simulation time 718347734 ps
CPU time 53.13 seconds
Started Aug 01 06:09:08 PM PDT 24
Finished Aug 01 06:10:02 PM PDT 24
Peak memory 237368 kb
Host smart-23060902-6aa7-41af-8a3d-8f1275eafe6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634771382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3634771382
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3071859165
Short name T37
Test name
Test status
Simulation time 803850531 ps
CPU time 5.35 seconds
Started Aug 01 06:09:10 PM PDT 24
Finished Aug 01 06:09:16 PM PDT 24
Peak memory 212308 kb
Host smart-7e5dc162-5fe5-47f7-94c6-f084945b99d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071859165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3071859165
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.572393986
Short name T136
Test name
Test status
Simulation time 305627090 ps
CPU time 12.79 seconds
Started Aug 01 06:09:09 PM PDT 24
Finished Aug 01 06:09:22 PM PDT 24
Peak memory 215056 kb
Host smart-7b7a63e9-d205-4631-836f-c8fde7aa76ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572393986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.572393986
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.410529234
Short name T59
Test name
Test status
Simulation time 28004617308 ps
CPU time 1107.24 seconds
Started Aug 01 06:09:14 PM PDT 24
Finished Aug 01 06:27:41 PM PDT 24
Peak memory 236708 kb
Host smart-86f9fa6b-3cd1-4d60-b469-1783fa9d012c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410529234 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.410529234
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1007561350
Short name T264
Test name
Test status
Simulation time 131513742 ps
CPU time 4.98 seconds
Started Aug 01 06:09:29 PM PDT 24
Finished Aug 01 06:09:34 PM PDT 24
Peak memory 212052 kb
Host smart-e85ef37c-8082-46e4-83bc-2edd0ba7bce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007561350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1007561350
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1466779827
Short name T231
Test name
Test status
Simulation time 6205607673 ps
CPU time 127.69 seconds
Started Aug 01 06:09:21 PM PDT 24
Finished Aug 01 06:11:29 PM PDT 24
Peak memory 238092 kb
Host smart-3b7ed92e-82fe-489f-984e-eaef9d5ff3d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466779827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1466779827
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3442224640
Short name T179
Test name
Test status
Simulation time 253998374 ps
CPU time 11.18 seconds
Started Aug 01 06:09:29 PM PDT 24
Finished Aug 01 06:09:40 PM PDT 24
Peak memory 212892 kb
Host smart-922bbe35-706e-4b02-8314-74e9af7d0bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442224640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3442224640
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2064231424
Short name T311
Test name
Test status
Simulation time 143647354 ps
CPU time 6.89 seconds
Started Aug 01 06:09:21 PM PDT 24
Finished Aug 01 06:09:28 PM PDT 24
Peak memory 212264 kb
Host smart-1866ab45-3456-47a0-99aa-dc127c96def9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2064231424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2064231424
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.965485364
Short name T91
Test name
Test status
Simulation time 414457328 ps
CPU time 21.61 seconds
Started Aug 01 06:09:26 PM PDT 24
Finished Aug 01 06:09:47 PM PDT 24
Peak memory 216376 kb
Host smart-f894786f-ddcf-47c3-9367-f22c00d0c50d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965485364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.965485364
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.4260656084
Short name T61
Test name
Test status
Simulation time 15447305905 ps
CPU time 6171.85 seconds
Started Aug 01 06:09:19 PM PDT 24
Finished Aug 01 07:52:12 PM PDT 24
Peak memory 233304 kb
Host smart-53ffa38d-bc5a-4b03-9923-6fa2cb6298dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260656084 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.4260656084
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2372032247
Short name T1
Test name
Test status
Simulation time 521954127 ps
CPU time 5 seconds
Started Aug 01 06:09:28 PM PDT 24
Finished Aug 01 06:09:33 PM PDT 24
Peak memory 212052 kb
Host smart-e77ef5d7-2168-494c-8228-42f37eca0c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372032247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2372032247
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3521328664
Short name T162
Test name
Test status
Simulation time 15283815597 ps
CPU time 175.49 seconds
Started Aug 01 06:09:28 PM PDT 24
Finished Aug 01 06:12:24 PM PDT 24
Peak memory 226672 kb
Host smart-f24eaec6-92c1-42d9-8afc-4a73e775e899
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521328664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3521328664
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1038968810
Short name T319
Test name
Test status
Simulation time 640187082 ps
CPU time 9.44 seconds
Started Aug 01 06:09:28 PM PDT 24
Finished Aug 01 06:09:38 PM PDT 24
Peak memory 212892 kb
Host smart-9b88a41f-f8f9-4cec-8914-fb8d160ee2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038968810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1038968810
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2834595757
Short name T129
Test name
Test status
Simulation time 552705141 ps
CPU time 6.18 seconds
Started Aug 01 06:09:23 PM PDT 24
Finished Aug 01 06:09:30 PM PDT 24
Peak memory 212140 kb
Host smart-d6e0a9af-80a8-479b-8b20-688030ea76d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2834595757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2834595757
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.515449325
Short name T292
Test name
Test status
Simulation time 1710540814 ps
CPU time 19.3 seconds
Started Aug 01 06:09:20 PM PDT 24
Finished Aug 01 06:09:39 PM PDT 24
Peak memory 216508 kb
Host smart-ea8908e4-fdd2-48aa-9259-cef4b6f9309b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515449325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.515449325
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2774888003
Short name T284
Test name
Test status
Simulation time 24185554750 ps
CPU time 481.72 seconds
Started Aug 01 06:09:20 PM PDT 24
Finished Aug 01 06:17:22 PM PDT 24
Peak memory 228364 kb
Host smart-5bb87629-372a-4a0c-9f4e-f96f29e9cf09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774888003 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2774888003
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.661988431
Short name T233
Test name
Test status
Simulation time 105056598 ps
CPU time 4.19 seconds
Started Aug 01 06:09:35 PM PDT 24
Finished Aug 01 06:09:39 PM PDT 24
Peak memory 212044 kb
Host smart-48812906-e5ab-40ec-b670-c1ac2cec4e9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661988431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.661988431
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3185523123
Short name T262
Test name
Test status
Simulation time 173920466 ps
CPU time 9.57 seconds
Started Aug 01 06:09:28 PM PDT 24
Finished Aug 01 06:09:38 PM PDT 24
Peak memory 213028 kb
Host smart-fde523ca-7f1a-4cb7-885d-83dfde74f3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185523123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3185523123
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1552879359
Short name T246
Test name
Test status
Simulation time 381386947 ps
CPU time 5.31 seconds
Started Aug 01 06:09:26 PM PDT 24
Finished Aug 01 06:09:32 PM PDT 24
Peak memory 212136 kb
Host smart-b4df31db-6749-4df0-9f43-5a79a39cf19c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1552879359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1552879359
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3052791860
Short name T40
Test name
Test status
Simulation time 230508408 ps
CPU time 7.34 seconds
Started Aug 01 06:09:24 PM PDT 24
Finished Aug 01 06:09:31 PM PDT 24
Peak memory 212088 kb
Host smart-98abf455-a8e2-4f2c-b9f8-eeb65c523dd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052791860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3052791860
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1111561891
Short name T204
Test name
Test status
Simulation time 390089421 ps
CPU time 4.95 seconds
Started Aug 01 06:09:32 PM PDT 24
Finished Aug 01 06:09:37 PM PDT 24
Peak memory 212044 kb
Host smart-c9d4129a-37ed-4038-99e0-87f96f7dbb77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111561891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1111561891
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2042642641
Short name T276
Test name
Test status
Simulation time 6035733779 ps
CPU time 95.13 seconds
Started Aug 01 06:09:35 PM PDT 24
Finished Aug 01 06:11:10 PM PDT 24
Peak memory 238328 kb
Host smart-306a5a9e-4bef-4809-9a65-811ef4348289
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042642641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2042642641
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.4218922210
Short name T249
Test name
Test status
Simulation time 2270332233 ps
CPU time 11.4 seconds
Started Aug 01 06:09:29 PM PDT 24
Finished Aug 01 06:09:41 PM PDT 24
Peak memory 212920 kb
Host smart-00beefaf-edae-4ffc-83de-d903013446c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218922210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.4218922210
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3805023466
Short name T143
Test name
Test status
Simulation time 238973574 ps
CPU time 5.41 seconds
Started Aug 01 06:09:31 PM PDT 24
Finished Aug 01 06:09:37 PM PDT 24
Peak memory 212132 kb
Host smart-cd346657-f744-4778-a8de-4a062e3adc77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3805023466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3805023466
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.351243238
Short name T93
Test name
Test status
Simulation time 553537340 ps
CPU time 13.77 seconds
Started Aug 01 06:09:36 PM PDT 24
Finished Aug 01 06:09:50 PM PDT 24
Peak memory 215472 kb
Host smart-8ccee127-0321-4819-9c75-86732bd909dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351243238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.351243238
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2497828068
Short name T64
Test name
Test status
Simulation time 118388935848 ps
CPU time 1199.44 seconds
Started Aug 01 06:09:29 PM PDT 24
Finished Aug 01 06:29:28 PM PDT 24
Peak memory 235188 kb
Host smart-0c8b22a6-97c9-47fc-919f-567e71a45ce7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497828068 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2497828068
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3423269514
Short name T67
Test name
Test status
Simulation time 499912843 ps
CPU time 5.02 seconds
Started Aug 01 06:09:31 PM PDT 24
Finished Aug 01 06:09:36 PM PDT 24
Peak memory 211976 kb
Host smart-fc5d7c45-6476-43c9-ae4b-c8346eeb5a0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423269514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3423269514
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3068526610
Short name T193
Test name
Test status
Simulation time 47517909441 ps
CPU time 161.4 seconds
Started Aug 01 06:09:38 PM PDT 24
Finished Aug 01 06:12:20 PM PDT 24
Peak memory 229212 kb
Host smart-195702f9-4b66-47af-8f38-cc8e1d6ba23f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068526610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3068526610
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2680829191
Short name T132
Test name
Test status
Simulation time 279304025 ps
CPU time 11.49 seconds
Started Aug 01 06:09:28 PM PDT 24
Finished Aug 01 06:09:39 PM PDT 24
Peak memory 212920 kb
Host smart-1bb2b297-c30d-4cf9-b2cd-d809fea3ae29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680829191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2680829191
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.507164805
Short name T203
Test name
Test status
Simulation time 166979665 ps
CPU time 6.28 seconds
Started Aug 01 06:09:34 PM PDT 24
Finished Aug 01 06:09:41 PM PDT 24
Peak memory 212004 kb
Host smart-7ddef3f6-509c-41c8-a9c7-8d8f33e0f612
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=507164805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.507164805
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3125112849
Short name T45
Test name
Test status
Simulation time 625934312 ps
CPU time 18.01 seconds
Started Aug 01 06:09:35 PM PDT 24
Finished Aug 01 06:09:53 PM PDT 24
Peak memory 214676 kb
Host smart-60df54db-de3b-40db-a4ff-dd63514127f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125112849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3125112849
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.614710052
Short name T322
Test name
Test status
Simulation time 352664791582 ps
CPU time 3542.59 seconds
Started Aug 01 06:09:30 PM PDT 24
Finished Aug 01 07:08:33 PM PDT 24
Peak memory 253032 kb
Host smart-6f9a4897-ca5f-429e-8b02-0fe1c517abe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614710052 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.614710052
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1178944079
Short name T270
Test name
Test status
Simulation time 138089757 ps
CPU time 5.28 seconds
Started Aug 01 06:09:28 PM PDT 24
Finished Aug 01 06:09:34 PM PDT 24
Peak memory 212032 kb
Host smart-69d0477c-137e-443f-aaed-aa37a280ecac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178944079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1178944079
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3928643443
Short name T234
Test name
Test status
Simulation time 2431702404 ps
CPU time 102.92 seconds
Started Aug 01 06:09:36 PM PDT 24
Finished Aug 01 06:11:19 PM PDT 24
Peak memory 228960 kb
Host smart-ce99cef3-eda4-4c5c-9afc-a6bade1da666
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928643443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3928643443
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.288682983
Short name T320
Test name
Test status
Simulation time 336810986 ps
CPU time 9.52 seconds
Started Aug 01 06:09:36 PM PDT 24
Finished Aug 01 06:09:45 PM PDT 24
Peak memory 212892 kb
Host smart-d06adda1-ef51-4cb6-8944-5f16dc13cf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288682983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.288682983
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1421678563
Short name T263
Test name
Test status
Simulation time 378275875 ps
CPU time 5.37 seconds
Started Aug 01 06:09:29 PM PDT 24
Finished Aug 01 06:09:35 PM PDT 24
Peak memory 212084 kb
Host smart-2e205d51-bc8c-48fe-9d05-11d6c6eecf69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1421678563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1421678563
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3567961907
Short name T128
Test name
Test status
Simulation time 2740753729 ps
CPU time 10.41 seconds
Started Aug 01 06:09:30 PM PDT 24
Finished Aug 01 06:09:40 PM PDT 24
Peak memory 215176 kb
Host smart-97c8b254-7da4-442d-94ce-337724116a17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567961907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3567961907
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1815293798
Short name T62
Test name
Test status
Simulation time 36599321316 ps
CPU time 1517.59 seconds
Started Aug 01 06:09:30 PM PDT 24
Finished Aug 01 06:34:48 PM PDT 24
Peak memory 236620 kb
Host smart-63db3bb9-94b6-4984-a0c8-05db4095bd37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815293798 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1815293798
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2700552236
Short name T309
Test name
Test status
Simulation time 87322128 ps
CPU time 4.34 seconds
Started Aug 01 06:09:37 PM PDT 24
Finished Aug 01 06:09:41 PM PDT 24
Peak memory 212040 kb
Host smart-e31423aa-5ac3-448c-bf7f-aa91995a32ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700552236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2700552236
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.874019369
Short name T297
Test name
Test status
Simulation time 3896713281 ps
CPU time 114.99 seconds
Started Aug 01 06:09:41 PM PDT 24
Finished Aug 01 06:11:36 PM PDT 24
Peak memory 238452 kb
Host smart-fbd68a5c-2bee-4e9c-b6ee-ec7c7ff1c42d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874019369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.874019369
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.412045591
Short name T212
Test name
Test status
Simulation time 699651416 ps
CPU time 9.54 seconds
Started Aug 01 06:09:34 PM PDT 24
Finished Aug 01 06:09:44 PM PDT 24
Peak memory 212912 kb
Host smart-9bf8eabc-7644-48f7-b565-5f71e4b03654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412045591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.412045591
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.428783253
Short name T228
Test name
Test status
Simulation time 374017653 ps
CPU time 5.7 seconds
Started Aug 01 06:09:30 PM PDT 24
Finished Aug 01 06:09:35 PM PDT 24
Peak memory 212108 kb
Host smart-d329792f-f06d-4fea-98b0-8c129091c2a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=428783253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.428783253
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.570705802
Short name T21
Test name
Test status
Simulation time 1174314887 ps
CPU time 16.1 seconds
Started Aug 01 06:09:33 PM PDT 24
Finished Aug 01 06:09:50 PM PDT 24
Peak memory 215432 kb
Host smart-76f67800-48eb-48a5-8578-e226055082ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570705802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.570705802
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2881599298
Short name T272
Test name
Test status
Simulation time 132049677 ps
CPU time 5.14 seconds
Started Aug 01 06:09:29 PM PDT 24
Finished Aug 01 06:09:35 PM PDT 24
Peak memory 211972 kb
Host smart-dc08911f-5160-4e44-b6b5-c67bdbbbfa6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881599298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2881599298
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1969512124
Short name T255
Test name
Test status
Simulation time 5275846412 ps
CPU time 124.43 seconds
Started Aug 01 06:09:38 PM PDT 24
Finished Aug 01 06:11:43 PM PDT 24
Peak memory 230648 kb
Host smart-ec7e3524-0d16-447e-9b00-8a0d8ca4e7af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969512124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1969512124
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2612081052
Short name T260
Test name
Test status
Simulation time 1287534446 ps
CPU time 9.62 seconds
Started Aug 01 06:09:31 PM PDT 24
Finished Aug 01 06:09:41 PM PDT 24
Peak memory 213424 kb
Host smart-a423097d-0bc2-4d5d-a4a3-1a38c4db10f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612081052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2612081052
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.658696492
Short name T244
Test name
Test status
Simulation time 562643119 ps
CPU time 6.52 seconds
Started Aug 01 06:09:38 PM PDT 24
Finished Aug 01 06:09:45 PM PDT 24
Peak memory 212344 kb
Host smart-b48e9bd4-9bef-4a4b-b812-5b35959bfd99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=658696492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.658696492
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3448154105
Short name T150
Test name
Test status
Simulation time 540841004 ps
CPU time 13.35 seconds
Started Aug 01 06:09:37 PM PDT 24
Finished Aug 01 06:09:51 PM PDT 24
Peak memory 213996 kb
Host smart-6039a168-2f4a-4fb2-af29-8731b112c005
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448154105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3448154105
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1081615801
Short name T147
Test name
Test status
Simulation time 448786153 ps
CPU time 5.05 seconds
Started Aug 01 06:09:37 PM PDT 24
Finished Aug 01 06:09:42 PM PDT 24
Peak memory 212020 kb
Host smart-0608e464-c5ec-43b0-bccf-38e330b43776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081615801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1081615801
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3835075070
Short name T305
Test name
Test status
Simulation time 5082102563 ps
CPU time 158.71 seconds
Started Aug 01 06:09:32 PM PDT 24
Finished Aug 01 06:12:11 PM PDT 24
Peak memory 226004 kb
Host smart-2e7590f7-5598-4a7f-9588-b1e4f5ca7186
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835075070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3835075070
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1669709758
Short name T279
Test name
Test status
Simulation time 619336658 ps
CPU time 9.37 seconds
Started Aug 01 06:09:31 PM PDT 24
Finished Aug 01 06:09:41 PM PDT 24
Peak memory 212836 kb
Host smart-f55e3018-b1b3-4878-95e4-f85edc44ccd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669709758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1669709758
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1138858396
Short name T155
Test name
Test status
Simulation time 145577263 ps
CPU time 6.8 seconds
Started Aug 01 06:09:36 PM PDT 24
Finished Aug 01 06:09:43 PM PDT 24
Peak memory 212040 kb
Host smart-94bd173f-ec66-42da-9af0-3abdbae93967
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1138858396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1138858396
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1539675534
Short name T299
Test name
Test status
Simulation time 441105912 ps
CPU time 14 seconds
Started Aug 01 06:09:32 PM PDT 24
Finished Aug 01 06:09:46 PM PDT 24
Peak memory 214456 kb
Host smart-0b265e77-6113-44e8-93fa-b1a4b3b33394
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539675534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1539675534
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1784622522
Short name T222
Test name
Test status
Simulation time 24074571944 ps
CPU time 991.31 seconds
Started Aug 01 06:09:30 PM PDT 24
Finished Aug 01 06:26:01 PM PDT 24
Peak memory 236644 kb
Host smart-cab283fb-6b70-4ab0-9a9f-7033e61a22ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784622522 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1784622522
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1245925197
Short name T149
Test name
Test status
Simulation time 138234655 ps
CPU time 5.15 seconds
Started Aug 01 06:09:42 PM PDT 24
Finished Aug 01 06:09:47 PM PDT 24
Peak memory 211992 kb
Host smart-0ad6fb22-e73f-4e69-9e96-a9373c455ca5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245925197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1245925197
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3146598221
Short name T226
Test name
Test status
Simulation time 2022355835 ps
CPU time 76.64 seconds
Started Aug 01 06:09:29 PM PDT 24
Finished Aug 01 06:10:46 PM PDT 24
Peak memory 229092 kb
Host smart-fdb549a9-f433-40e5-907b-91c742c8c139
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146598221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3146598221
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2364205951
Short name T32
Test name
Test status
Simulation time 1126325655 ps
CPU time 11.29 seconds
Started Aug 01 06:09:30 PM PDT 24
Finished Aug 01 06:09:42 PM PDT 24
Peak memory 212804 kb
Host smart-fc3e6b15-54c2-4fd1-885d-41c181d3f1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364205951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2364205951
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2811257870
Short name T144
Test name
Test status
Simulation time 99465862 ps
CPU time 5.83 seconds
Started Aug 01 06:09:37 PM PDT 24
Finished Aug 01 06:09:43 PM PDT 24
Peak memory 212084 kb
Host smart-65046cd4-e1a7-4336-83e3-e3ef77185a16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2811257870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2811257870
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2277901635
Short name T191
Test name
Test status
Simulation time 245336560 ps
CPU time 9.34 seconds
Started Aug 01 06:09:31 PM PDT 24
Finished Aug 01 06:09:40 PM PDT 24
Peak memory 212040 kb
Host smart-7167ede6-7316-4686-9d74-f3dcd512d394
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277901635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2277901635
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2293016705
Short name T307
Test name
Test status
Simulation time 693552870 ps
CPU time 4.21 seconds
Started Aug 01 06:09:11 PM PDT 24
Finished Aug 01 06:09:15 PM PDT 24
Peak memory 212004 kb
Host smart-021e7673-ee76-4f91-9e88-c216f6097667
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293016705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2293016705
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.472931141
Short name T199
Test name
Test status
Simulation time 2254816291 ps
CPU time 135.97 seconds
Started Aug 01 06:09:14 PM PDT 24
Finished Aug 01 06:11:30 PM PDT 24
Peak memory 237368 kb
Host smart-d0e3f423-272e-4dd9-9c15-50a612bbc0b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472931141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.472931141
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3543265538
Short name T54
Test name
Test status
Simulation time 335601802 ps
CPU time 9.45 seconds
Started Aug 01 06:09:12 PM PDT 24
Finished Aug 01 06:09:22 PM PDT 24
Peak memory 212860 kb
Host smart-4ba1f62a-02ca-4626-a5ab-20bf17b0f5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543265538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3543265538
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2323903013
Short name T174
Test name
Test status
Simulation time 96663408 ps
CPU time 6.18 seconds
Started Aug 01 06:09:10 PM PDT 24
Finished Aug 01 06:09:16 PM PDT 24
Peak memory 212072 kb
Host smart-1d678a8b-5122-430b-aa34-d72b887e3235
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2323903013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2323903013
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1346520607
Short name T30
Test name
Test status
Simulation time 391793142 ps
CPU time 57.76 seconds
Started Aug 01 06:09:08 PM PDT 24
Finished Aug 01 06:10:06 PM PDT 24
Peak memory 238416 kb
Host smart-12da53b1-45d4-4fc4-aff7-52df4c0e0dfe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346520607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1346520607
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1285891517
Short name T268
Test name
Test status
Simulation time 101584741 ps
CPU time 5.51 seconds
Started Aug 01 06:09:09 PM PDT 24
Finished Aug 01 06:09:15 PM PDT 24
Peak memory 212148 kb
Host smart-0d6c90a1-f27d-4107-be62-666f616afe33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285891517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1285891517
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.4018970842
Short name T223
Test name
Test status
Simulation time 527325643 ps
CPU time 9.14 seconds
Started Aug 01 06:09:13 PM PDT 24
Finished Aug 01 06:09:23 PM PDT 24
Peak memory 212040 kb
Host smart-f4f95b00-7b67-4989-b23e-4fdb34bbbf08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018970842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.4018970842
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.291676704
Short name T232
Test name
Test status
Simulation time 122060109677 ps
CPU time 9770.59 seconds
Started Aug 01 06:09:09 PM PDT 24
Finished Aug 01 08:52:01 PM PDT 24
Peak memory 237644 kb
Host smart-82f38369-2e61-4d74-ab36-9c09bb6aab43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291676704 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.291676704
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3526546903
Short name T131
Test name
Test status
Simulation time 289576399 ps
CPU time 4.29 seconds
Started Aug 01 06:09:42 PM PDT 24
Finished Aug 01 06:09:47 PM PDT 24
Peak memory 212016 kb
Host smart-014bb946-3ea7-4c47-a5d5-83749a77be0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526546903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3526546903
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3032847629
Short name T160
Test name
Test status
Simulation time 8296789305 ps
CPU time 132.86 seconds
Started Aug 01 06:09:42 PM PDT 24
Finished Aug 01 06:11:55 PM PDT 24
Peak memory 238568 kb
Host smart-5671dfc8-95e9-4a4a-8ca2-45dfec910e8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032847629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3032847629
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1306520334
Short name T250
Test name
Test status
Simulation time 254529994 ps
CPU time 11.81 seconds
Started Aug 01 06:09:40 PM PDT 24
Finished Aug 01 06:09:52 PM PDT 24
Peak memory 213316 kb
Host smart-e1c62a04-90a9-4ae4-b89b-8ae4a5d79dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306520334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1306520334
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2809643028
Short name T294
Test name
Test status
Simulation time 146368662 ps
CPU time 6.64 seconds
Started Aug 01 06:09:40 PM PDT 24
Finished Aug 01 06:09:47 PM PDT 24
Peak memory 212056 kb
Host smart-d4253b33-30e1-472c-8630-e103ad0b8c4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809643028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2809643028
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3146131689
Short name T139
Test name
Test status
Simulation time 135991516 ps
CPU time 11.28 seconds
Started Aug 01 06:09:45 PM PDT 24
Finished Aug 01 06:09:56 PM PDT 24
Peak memory 212000 kb
Host smart-a022d441-3386-47bb-8d9b-b041e098a638
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146131689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3146131689
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.746003315
Short name T65
Test name
Test status
Simulation time 88268283516 ps
CPU time 879.13 seconds
Started Aug 01 06:09:39 PM PDT 24
Finished Aug 01 06:24:18 PM PDT 24
Peak memory 236628 kb
Host smart-305c5554-6780-47ff-896d-d6edfbcac6df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746003315 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.746003315
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3008755695
Short name T283
Test name
Test status
Simulation time 333785687 ps
CPU time 4.21 seconds
Started Aug 01 06:09:39 PM PDT 24
Finished Aug 01 06:09:44 PM PDT 24
Peak memory 211948 kb
Host smart-cc9af54f-abc1-4905-8cda-7fb676e4cee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008755695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3008755695
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3651577151
Short name T280
Test name
Test status
Simulation time 2456058860 ps
CPU time 153.46 seconds
Started Aug 01 06:09:40 PM PDT 24
Finished Aug 01 06:12:13 PM PDT 24
Peak memory 233244 kb
Host smart-bcd029f0-49ff-4b11-83cc-40884d63a45a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651577151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3651577151
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.34851613
Short name T183
Test name
Test status
Simulation time 256097517 ps
CPU time 11.58 seconds
Started Aug 01 06:09:40 PM PDT 24
Finished Aug 01 06:09:52 PM PDT 24
Peak memory 212756 kb
Host smart-ddb06e46-8a6b-47a0-a192-547445934fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34851613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.34851613
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.74741846
Short name T176
Test name
Test status
Simulation time 95148088 ps
CPU time 5.46 seconds
Started Aug 01 06:09:43 PM PDT 24
Finished Aug 01 06:09:49 PM PDT 24
Peak memory 212184 kb
Host smart-26eeac46-9000-4774-820a-7e2e045a70b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74741846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.74741846
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.63199441
Short name T200
Test name
Test status
Simulation time 615372949 ps
CPU time 15.83 seconds
Started Aug 01 06:09:43 PM PDT 24
Finished Aug 01 06:09:59 PM PDT 24
Peak memory 215916 kb
Host smart-dc9f4c31-7a0e-4ec2-89fc-e4c9bd622b3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63199441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 31.rom_ctrl_stress_all.63199441
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2742056222
Short name T312
Test name
Test status
Simulation time 175691649 ps
CPU time 4.3 seconds
Started Aug 01 06:09:40 PM PDT 24
Finished Aug 01 06:09:45 PM PDT 24
Peak memory 212016 kb
Host smart-3e99fb5e-e707-4f05-91b0-eab9efc63201
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742056222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2742056222
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.394682668
Short name T237
Test name
Test status
Simulation time 2978142370 ps
CPU time 153.54 seconds
Started Aug 01 06:09:43 PM PDT 24
Finished Aug 01 06:12:17 PM PDT 24
Peak memory 238464 kb
Host smart-69eb5a03-a529-4099-a938-b53bb732bec2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394682668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.394682668
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4057412381
Short name T300
Test name
Test status
Simulation time 1770157262 ps
CPU time 11.16 seconds
Started Aug 01 06:09:42 PM PDT 24
Finished Aug 01 06:09:54 PM PDT 24
Peak memory 212888 kb
Host smart-f879707a-d99b-4d27-a352-c019207e0625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057412381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.4057412381
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1711839652
Short name T2
Test name
Test status
Simulation time 101814255 ps
CPU time 5.82 seconds
Started Aug 01 06:09:41 PM PDT 24
Finished Aug 01 06:09:47 PM PDT 24
Peak memory 212168 kb
Host smart-a75eddeb-3200-46cb-a1b8-ac9d322fe143
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1711839652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1711839652
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2178187158
Short name T265
Test name
Test status
Simulation time 188180313 ps
CPU time 13.39 seconds
Started Aug 01 06:09:38 PM PDT 24
Finished Aug 01 06:09:52 PM PDT 24
Peak memory 214464 kb
Host smart-628dbb4f-79e4-4d39-9ad6-872086f4b116
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178187158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2178187158
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.533676297
Short name T53
Test name
Test status
Simulation time 488596048 ps
CPU time 4.25 seconds
Started Aug 01 06:09:39 PM PDT 24
Finished Aug 01 06:09:43 PM PDT 24
Peak memory 211980 kb
Host smart-4f6de3b5-ab8d-4a89-a16b-2d015e2edce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533676297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.533676297
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4056860488
Short name T48
Test name
Test status
Simulation time 1973026028 ps
CPU time 114.84 seconds
Started Aug 01 06:09:39 PM PDT 24
Finished Aug 01 06:11:34 PM PDT 24
Peak memory 237320 kb
Host smart-23f79687-d7ff-4586-9f68-e96d6d15d41a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056860488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.4056860488
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3211188318
Short name T227
Test name
Test status
Simulation time 3342660314 ps
CPU time 9.56 seconds
Started Aug 01 06:09:41 PM PDT 24
Finished Aug 01 06:09:51 PM PDT 24
Peak memory 213004 kb
Host smart-94bcef2a-56e7-43d5-967f-d2020fd1e764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211188318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3211188318
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3504320961
Short name T70
Test name
Test status
Simulation time 532313766 ps
CPU time 6.22 seconds
Started Aug 01 06:09:41 PM PDT 24
Finished Aug 01 06:09:48 PM PDT 24
Peak memory 212140 kb
Host smart-ac9f8c9c-f19f-449d-98a6-c942ad14d23b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3504320961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3504320961
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1579776355
Short name T154
Test name
Test status
Simulation time 402933409 ps
CPU time 5.71 seconds
Started Aug 01 06:09:42 PM PDT 24
Finished Aug 01 06:09:48 PM PDT 24
Peak memory 212140 kb
Host smart-4d275b1a-7d47-466b-94fc-bce17eec86c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579776355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1579776355
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3951082851
Short name T308
Test name
Test status
Simulation time 132095839 ps
CPU time 5.14 seconds
Started Aug 01 06:09:47 PM PDT 24
Finished Aug 01 06:09:52 PM PDT 24
Peak memory 212008 kb
Host smart-a66936b3-7caf-45ca-a538-afe0be57d12e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951082851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3951082851
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3917634434
Short name T166
Test name
Test status
Simulation time 13593100838 ps
CPU time 173.77 seconds
Started Aug 01 06:09:38 PM PDT 24
Finished Aug 01 06:12:32 PM PDT 24
Peak memory 234552 kb
Host smart-1fb82c6a-2ed4-4c58-a1cf-c2543344bb00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917634434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3917634434
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1420791290
Short name T168
Test name
Test status
Simulation time 500419694 ps
CPU time 10.97 seconds
Started Aug 01 06:09:40 PM PDT 24
Finished Aug 01 06:09:51 PM PDT 24
Peak memory 212840 kb
Host smart-b90d5025-7858-46e9-bc05-1642d8ce3496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420791290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1420791290
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2636065044
Short name T170
Test name
Test status
Simulation time 681916862 ps
CPU time 6.54 seconds
Started Aug 01 06:09:42 PM PDT 24
Finished Aug 01 06:09:49 PM PDT 24
Peak memory 212124 kb
Host smart-ecd9af36-1db8-44f7-bb78-68256eb95312
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2636065044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2636065044
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2577574195
Short name T92
Test name
Test status
Simulation time 446026503 ps
CPU time 13.6 seconds
Started Aug 01 06:09:42 PM PDT 24
Finished Aug 01 06:09:56 PM PDT 24
Peak memory 214580 kb
Host smart-6b2908bf-4a1b-4886-88bd-f2cf7d07b093
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577574195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2577574195
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.97764735
Short name T156
Test name
Test status
Simulation time 8107912883 ps
CPU time 96.91 seconds
Started Aug 01 06:09:43 PM PDT 24
Finished Aug 01 06:11:20 PM PDT 24
Peak memory 238444 kb
Host smart-6ef57f02-d9b5-4433-bbec-f8cbaaf99a34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97764735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_co
rrupt_sig_fatal_chk.97764735
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1342093723
Short name T214
Test name
Test status
Simulation time 505221388 ps
CPU time 8.52 seconds
Started Aug 01 06:09:40 PM PDT 24
Finished Aug 01 06:09:49 PM PDT 24
Peak memory 212136 kb
Host smart-2b71d8a2-bc8e-41b3-a16f-072d6616150f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1342093723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1342093723
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2151624490
Short name T89
Test name
Test status
Simulation time 292822135 ps
CPU time 14.11 seconds
Started Aug 01 06:09:42 PM PDT 24
Finished Aug 01 06:09:57 PM PDT 24
Peak memory 215772 kb
Host smart-eadb56a4-38bf-4845-9214-f0a765fa78f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151624490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2151624490
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3558422133
Short name T293
Test name
Test status
Simulation time 50461471910 ps
CPU time 650.93 seconds
Started Aug 01 06:09:39 PM PDT 24
Finished Aug 01 06:20:31 PM PDT 24
Peak memory 236644 kb
Host smart-58d6397f-9565-4340-af91-0450da8398b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558422133 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3558422133
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.593273742
Short name T146
Test name
Test status
Simulation time 953138608 ps
CPU time 5.09 seconds
Started Aug 01 06:09:39 PM PDT 24
Finished Aug 01 06:09:44 PM PDT 24
Peak memory 212008 kb
Host smart-21428aec-e933-42cf-aa6f-e7631d93ad1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593273742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.593273742
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.783047492
Short name T47
Test name
Test status
Simulation time 879693512 ps
CPU time 67.09 seconds
Started Aug 01 06:09:47 PM PDT 24
Finished Aug 01 06:10:54 PM PDT 24
Peak memory 229092 kb
Host smart-0c6fb24f-9319-469c-81c5-563edf049a2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783047492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.783047492
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1782372744
Short name T267
Test name
Test status
Simulation time 521929676 ps
CPU time 11.11 seconds
Started Aug 01 06:09:43 PM PDT 24
Finished Aug 01 06:09:54 PM PDT 24
Peak memory 213232 kb
Host smart-a34a8914-3f59-4618-8dd7-7dfc85af65b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782372744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1782372744
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2691569841
Short name T196
Test name
Test status
Simulation time 492031676 ps
CPU time 6.39 seconds
Started Aug 01 06:09:41 PM PDT 24
Finished Aug 01 06:09:48 PM PDT 24
Peak memory 212140 kb
Host smart-64c09518-7470-44c1-8dca-1fd1022232ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2691569841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2691569841
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.407104415
Short name T167
Test name
Test status
Simulation time 313963745 ps
CPU time 18 seconds
Started Aug 01 06:09:44 PM PDT 24
Finished Aug 01 06:10:03 PM PDT 24
Peak memory 216888 kb
Host smart-82f5d39c-0ec0-4b08-96d8-cbb3c2a71767
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407104415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.407104415
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2537379862
Short name T286
Test name
Test status
Simulation time 62897782536 ps
CPU time 1312 seconds
Started Aug 01 06:09:40 PM PDT 24
Finished Aug 01 06:31:32 PM PDT 24
Peak memory 236624 kb
Host smart-b71f699e-1e1d-465a-8a0b-dca38b2c2ef5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537379862 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.2537379862
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2376859827
Short name T38
Test name
Test status
Simulation time 349113248 ps
CPU time 4.31 seconds
Started Aug 01 06:09:41 PM PDT 24
Finished Aug 01 06:09:45 PM PDT 24
Peak memory 212040 kb
Host smart-160bef49-77bf-418e-a5ef-2bb0313e0fed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376859827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2376859827
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.678731412
Short name T256
Test name
Test status
Simulation time 1881002909 ps
CPU time 115.69 seconds
Started Aug 01 06:09:42 PM PDT 24
Finished Aug 01 06:11:37 PM PDT 24
Peak memory 229100 kb
Host smart-eb7eec36-e0e4-44f1-a84e-69b21162d85d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678731412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.678731412
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2152419431
Short name T220
Test name
Test status
Simulation time 263473314 ps
CPU time 11.2 seconds
Started Aug 01 06:09:42 PM PDT 24
Finished Aug 01 06:09:53 PM PDT 24
Peak memory 213012 kb
Host smart-850625b2-551e-4033-ac01-33c1b740ae78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152419431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2152419431
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2203060468
Short name T134
Test name
Test status
Simulation time 100534030 ps
CPU time 5.5 seconds
Started Aug 01 06:09:41 PM PDT 24
Finished Aug 01 06:09:46 PM PDT 24
Peak memory 212044 kb
Host smart-081a1982-df7f-4ae8-a94e-7e407a10d415
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2203060468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2203060468
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3805168562
Short name T141
Test name
Test status
Simulation time 2894670098 ps
CPU time 6.85 seconds
Started Aug 01 06:09:39 PM PDT 24
Finished Aug 01 06:09:46 PM PDT 24
Peak memory 212376 kb
Host smart-7aa2d9fa-54d8-41a4-b5ac-ab8f7067a5ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805168562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3805168562
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2535848567
Short name T296
Test name
Test status
Simulation time 88885525 ps
CPU time 4.38 seconds
Started Aug 01 06:09:42 PM PDT 24
Finished Aug 01 06:09:46 PM PDT 24
Peak memory 212016 kb
Host smart-f43a280f-8726-45e9-bdeb-d46470cc0d8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535848567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2535848567
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1831341
Short name T243
Test name
Test status
Simulation time 7053468050 ps
CPU time 67.68 seconds
Started Aug 01 06:09:47 PM PDT 24
Finished Aug 01 06:10:55 PM PDT 24
Peak memory 233344 kb
Host smart-a7e1acba-f8b7-48b5-af47-de1bc8d236d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_s
ig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_cor
rupt_sig_fatal_chk.1831341
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1083505905
Short name T201
Test name
Test status
Simulation time 574079063 ps
CPU time 9.59 seconds
Started Aug 01 06:09:47 PM PDT 24
Finished Aug 01 06:09:57 PM PDT 24
Peak memory 212940 kb
Host smart-4342b04b-5cc7-4cdb-bc42-7d37957972e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083505905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1083505905
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3943485565
Short name T310
Test name
Test status
Simulation time 531034272 ps
CPU time 6.52 seconds
Started Aug 01 06:09:42 PM PDT 24
Finished Aug 01 06:09:48 PM PDT 24
Peak memory 212040 kb
Host smart-3bcfd4fe-eee3-4130-a5c6-c65feefb0b9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3943485565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3943485565
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1756734281
Short name T178
Test name
Test status
Simulation time 1922419489 ps
CPU time 16.83 seconds
Started Aug 01 06:09:40 PM PDT 24
Finished Aug 01 06:09:57 PM PDT 24
Peak memory 214180 kb
Host smart-d54b1829-feb6-441a-97e4-bf1ef39b0079
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756734281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1756734281
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3014144019
Short name T152
Test name
Test status
Simulation time 504008617 ps
CPU time 5.18 seconds
Started Aug 01 06:09:51 PM PDT 24
Finished Aug 01 06:09:56 PM PDT 24
Peak memory 211972 kb
Host smart-2239a632-34db-4050-a5ce-cab38dc75fb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014144019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3014144019
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2844555730
Short name T28
Test name
Test status
Simulation time 1840182996 ps
CPU time 135.15 seconds
Started Aug 01 06:09:40 PM PDT 24
Finished Aug 01 06:11:55 PM PDT 24
Peak memory 238336 kb
Host smart-662472d9-64bb-4107-b585-702c6e80473e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844555730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2844555730
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2668078520
Short name T282
Test name
Test status
Simulation time 366372287 ps
CPU time 11.2 seconds
Started Aug 01 06:09:45 PM PDT 24
Finished Aug 01 06:09:56 PM PDT 24
Peak memory 212904 kb
Host smart-3436c5d8-9715-4272-941d-bc1cf263370b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668078520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2668078520
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1886695024
Short name T289
Test name
Test status
Simulation time 530162015 ps
CPU time 6.29 seconds
Started Aug 01 06:09:43 PM PDT 24
Finished Aug 01 06:09:49 PM PDT 24
Peak memory 212184 kb
Host smart-c89432b7-5d40-4bc5-8f91-ddccf4da903c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886695024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1886695024
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2347222868
Short name T229
Test name
Test status
Simulation time 1239798006 ps
CPU time 15.66 seconds
Started Aug 01 06:09:40 PM PDT 24
Finished Aug 01 06:09:56 PM PDT 24
Peak memory 215760 kb
Host smart-6cbd11a3-6975-49c0-8933-f51358e5541b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347222868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2347222868
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2926611996
Short name T224
Test name
Test status
Simulation time 655036994 ps
CPU time 5.25 seconds
Started Aug 01 06:09:10 PM PDT 24
Finished Aug 01 06:09:15 PM PDT 24
Peak memory 212028 kb
Host smart-dfff48dd-0f18-424b-9424-cb3e9856feb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926611996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2926611996
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3406948606
Short name T230
Test name
Test status
Simulation time 45165917401 ps
CPU time 163.07 seconds
Started Aug 01 06:09:10 PM PDT 24
Finished Aug 01 06:11:54 PM PDT 24
Peak memory 238400 kb
Host smart-0fc83ca7-5552-4570-8fa0-890aef57acdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406948606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3406948606
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1614255639
Short name T198
Test name
Test status
Simulation time 253082468 ps
CPU time 11.11 seconds
Started Aug 01 06:09:17 PM PDT 24
Finished Aug 01 06:09:28 PM PDT 24
Peak memory 213360 kb
Host smart-a4178ba6-b464-41c4-845e-27ec449a7d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614255639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1614255639
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2912453758
Short name T290
Test name
Test status
Simulation time 271599093 ps
CPU time 6.28 seconds
Started Aug 01 06:09:12 PM PDT 24
Finished Aug 01 06:09:18 PM PDT 24
Peak memory 212116 kb
Host smart-201af7fd-884d-49e7-a834-9d1ace1b626d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2912453758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2912453758
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3960311161
Short name T36
Test name
Test status
Simulation time 1142256148 ps
CPU time 108.04 seconds
Started Aug 01 06:09:09 PM PDT 24
Finished Aug 01 06:10:57 PM PDT 24
Peak memory 241336 kb
Host smart-56675224-16d5-4a53-9768-8a5194c8aae3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960311161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3960311161
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2622038974
Short name T298
Test name
Test status
Simulation time 217647166 ps
CPU time 5.51 seconds
Started Aug 01 06:09:13 PM PDT 24
Finished Aug 01 06:09:19 PM PDT 24
Peak memory 212108 kb
Host smart-b9e38f77-202e-437a-aa6e-192656271fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622038974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2622038974
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2720170954
Short name T303
Test name
Test status
Simulation time 1899473635 ps
CPU time 19.26 seconds
Started Aug 01 06:09:17 PM PDT 24
Finished Aug 01 06:09:36 PM PDT 24
Peak memory 214840 kb
Host smart-64a3d51f-4720-4338-9cb5-d8528c9c2af7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720170954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2720170954
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2515166802
Short name T189
Test name
Test status
Simulation time 337143038 ps
CPU time 4.3 seconds
Started Aug 01 06:09:53 PM PDT 24
Finished Aug 01 06:09:58 PM PDT 24
Peak memory 211976 kb
Host smart-1b3384ad-e522-4c5b-a58a-093d9c2725c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515166802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2515166802
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2479195279
Short name T58
Test name
Test status
Simulation time 5767438796 ps
CPU time 119.84 seconds
Started Aug 01 06:09:53 PM PDT 24
Finished Aug 01 06:11:54 PM PDT 24
Peak memory 238780 kb
Host smart-13e5d951-a7e7-439b-9820-c223d4900b22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479195279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2479195279
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2737526348
Short name T175
Test name
Test status
Simulation time 1495529219 ps
CPU time 16.25 seconds
Started Aug 01 06:09:55 PM PDT 24
Finished Aug 01 06:10:11 PM PDT 24
Peak memory 212852 kb
Host smart-595911a5-a899-4d0a-aac3-90ec9852bf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737526348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2737526348
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2098373553
Short name T258
Test name
Test status
Simulation time 360771002 ps
CPU time 5.39 seconds
Started Aug 01 06:09:57 PM PDT 24
Finished Aug 01 06:10:02 PM PDT 24
Peak memory 212116 kb
Host smart-edb8ab4b-1114-41ed-842d-38f73e4575e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2098373553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2098373553
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3746995575
Short name T190
Test name
Test status
Simulation time 222580382 ps
CPU time 12.67 seconds
Started Aug 01 06:09:53 PM PDT 24
Finished Aug 01 06:10:06 PM PDT 24
Peak memory 213380 kb
Host smart-08d266b1-5055-483c-8d12-8b1c54ef1686
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746995575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3746995575
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.594753730
Short name T161
Test name
Test status
Simulation time 255987240 ps
CPU time 4.99 seconds
Started Aug 01 06:10:02 PM PDT 24
Finished Aug 01 06:10:07 PM PDT 24
Peak memory 211940 kb
Host smart-02d559b4-9ee0-49f9-bf7d-f40983c09962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594753730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.594753730
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2546672848
Short name T41
Test name
Test status
Simulation time 991329956 ps
CPU time 11.39 seconds
Started Aug 01 06:09:54 PM PDT 24
Finished Aug 01 06:10:05 PM PDT 24
Peak memory 212872 kb
Host smart-68fc7f42-7030-4017-b797-0c1ca202aeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546672848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2546672848
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3082838423
Short name T304
Test name
Test status
Simulation time 198307676 ps
CPU time 5.5 seconds
Started Aug 01 06:09:54 PM PDT 24
Finished Aug 01 06:10:00 PM PDT 24
Peak memory 212344 kb
Host smart-a489904d-a5a8-4ac1-9a50-e141ae22c504
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3082838423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3082838423
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3543874476
Short name T8
Test name
Test status
Simulation time 218852897 ps
CPU time 12.42 seconds
Started Aug 01 06:09:52 PM PDT 24
Finished Aug 01 06:10:05 PM PDT 24
Peak memory 215080 kb
Host smart-0f2bb867-8a2b-4937-bbfc-f61fc2a685c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543874476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3543874476
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4154014644
Short name T79
Test name
Test status
Simulation time 2318151177 ps
CPU time 7.46 seconds
Started Aug 01 06:09:55 PM PDT 24
Finished Aug 01 06:10:03 PM PDT 24
Peak memory 212136 kb
Host smart-87b63def-70f6-48d4-bc70-e248be24e1ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154014644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4154014644
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2010207213
Short name T321
Test name
Test status
Simulation time 2726274641 ps
CPU time 108.22 seconds
Started Aug 01 06:09:51 PM PDT 24
Finished Aug 01 06:11:39 PM PDT 24
Peak memory 238420 kb
Host smart-370f80c1-20d4-4949-8918-d5ece666cdd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010207213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2010207213
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.295347384
Short name T140
Test name
Test status
Simulation time 669994613 ps
CPU time 9.63 seconds
Started Aug 01 06:09:56 PM PDT 24
Finished Aug 01 06:10:06 PM PDT 24
Peak memory 212840 kb
Host smart-33ac142f-aaf5-42de-8500-3e7638c0c603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295347384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.295347384
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1653281284
Short name T281
Test name
Test status
Simulation time 134594356 ps
CPU time 6.14 seconds
Started Aug 01 06:09:52 PM PDT 24
Finished Aug 01 06:09:59 PM PDT 24
Peak memory 212056 kb
Host smart-ee6b9762-54ba-4bd5-aaf1-6a6b2e9f5611
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1653281284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1653281284
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3663317442
Short name T252
Test name
Test status
Simulation time 394559745 ps
CPU time 22.52 seconds
Started Aug 01 06:09:56 PM PDT 24
Finished Aug 01 06:10:18 PM PDT 24
Peak memory 216380 kb
Host smart-b538c8ed-1465-43d6-a019-02ac101879e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663317442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3663317442
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3389344169
Short name T315
Test name
Test status
Simulation time 130656650 ps
CPU time 5.09 seconds
Started Aug 01 06:09:53 PM PDT 24
Finished Aug 01 06:09:59 PM PDT 24
Peak memory 211948 kb
Host smart-bac1ffbd-0a9f-4274-9709-869f9a25e1f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389344169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3389344169
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2393984852
Short name T186
Test name
Test status
Simulation time 15439706370 ps
CPU time 137.46 seconds
Started Aug 01 06:10:02 PM PDT 24
Finished Aug 01 06:12:20 PM PDT 24
Peak memory 228940 kb
Host smart-2b74b701-a822-43ec-b3c8-b66842045c4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393984852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2393984852
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.907899539
Short name T313
Test name
Test status
Simulation time 1126945749 ps
CPU time 11.38 seconds
Started Aug 01 06:10:00 PM PDT 24
Finished Aug 01 06:10:11 PM PDT 24
Peak memory 212872 kb
Host smart-6c14e2d5-6895-4a64-af55-5dc958975632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907899539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.907899539
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.679624691
Short name T218
Test name
Test status
Simulation time 99875173 ps
CPU time 5.84 seconds
Started Aug 01 06:09:53 PM PDT 24
Finished Aug 01 06:09:59 PM PDT 24
Peak memory 212344 kb
Host smart-36409c7a-b00b-4f28-aa4b-e4722d2bff61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=679624691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.679624691
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3614161888
Short name T301
Test name
Test status
Simulation time 3273304669 ps
CPU time 13.47 seconds
Started Aug 01 06:09:53 PM PDT 24
Finished Aug 01 06:10:07 PM PDT 24
Peak memory 215184 kb
Host smart-10a7db2a-9bab-4f3f-b39d-50972ab08668
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614161888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3614161888
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.538053382
Short name T171
Test name
Test status
Simulation time 254593482 ps
CPU time 5.35 seconds
Started Aug 01 06:09:51 PM PDT 24
Finished Aug 01 06:09:57 PM PDT 24
Peak memory 211924 kb
Host smart-60fca6c3-cfc8-4b9b-958b-4a082c6b31b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538053382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.538053382
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.191754986
Short name T119
Test name
Test status
Simulation time 7723688659 ps
CPU time 77.33 seconds
Started Aug 01 06:09:57 PM PDT 24
Finished Aug 01 06:11:15 PM PDT 24
Peak memory 220256 kb
Host smart-8628fbc7-723e-48bb-8a72-feb3622308a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191754986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.191754986
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2426293693
Short name T153
Test name
Test status
Simulation time 499959147 ps
CPU time 11.42 seconds
Started Aug 01 06:09:54 PM PDT 24
Finished Aug 01 06:10:05 PM PDT 24
Peak memory 212868 kb
Host smart-4c3e37fc-9958-4669-8bc9-154e564f47a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426293693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2426293693
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2717644086
Short name T151
Test name
Test status
Simulation time 2008117454 ps
CPU time 8.7 seconds
Started Aug 01 06:09:51 PM PDT 24
Finished Aug 01 06:10:00 PM PDT 24
Peak memory 212116 kb
Host smart-82eb59c0-7492-4478-b807-acd9b5512528
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2717644086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2717644086
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.526588542
Short name T39
Test name
Test status
Simulation time 696315172 ps
CPU time 28.91 seconds
Started Aug 01 06:09:56 PM PDT 24
Finished Aug 01 06:10:25 PM PDT 24
Peak memory 216768 kb
Host smart-6b0b8fa0-445c-4bb1-8610-4a26a04c34b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526588542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.526588542
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2984686741
Short name T277
Test name
Test status
Simulation time 499737767 ps
CPU time 5.16 seconds
Started Aug 01 06:09:51 PM PDT 24
Finished Aug 01 06:09:56 PM PDT 24
Peak memory 212028 kb
Host smart-80ea92bf-ee13-4f13-8e9e-674937050fd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984686741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2984686741
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.24233135
Short name T317
Test name
Test status
Simulation time 2598759939 ps
CPU time 126.18 seconds
Started Aug 01 06:09:57 PM PDT 24
Finished Aug 01 06:12:03 PM PDT 24
Peak memory 238448 kb
Host smart-7a3c9d4c-75f9-4af2-bfe1-9bfe5176f0b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24233135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_co
rrupt_sig_fatal_chk.24233135
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.790763955
Short name T241
Test name
Test status
Simulation time 1132684437 ps
CPU time 11.32 seconds
Started Aug 01 06:09:53 PM PDT 24
Finished Aug 01 06:10:04 PM PDT 24
Peak memory 213256 kb
Host smart-249c47d8-33c9-45f4-92d4-93753239a116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790763955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.790763955
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.727527395
Short name T273
Test name
Test status
Simulation time 141991516 ps
CPU time 6.24 seconds
Started Aug 01 06:09:54 PM PDT 24
Finished Aug 01 06:10:01 PM PDT 24
Peak memory 211340 kb
Host smart-0b15d72a-ca9a-4936-bae3-f495523f3ae7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=727527395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.727527395
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1422115296
Short name T145
Test name
Test status
Simulation time 893508426 ps
CPU time 7.4 seconds
Started Aug 01 06:09:53 PM PDT 24
Finished Aug 01 06:10:01 PM PDT 24
Peak memory 212148 kb
Host smart-817741cd-5464-449a-876d-8ab33b843e94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422115296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1422115296
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2506027226
Short name T130
Test name
Test status
Simulation time 129137086 ps
CPU time 5.29 seconds
Started Aug 01 06:09:52 PM PDT 24
Finished Aug 01 06:09:58 PM PDT 24
Peak memory 211948 kb
Host smart-192e9e1a-054f-41a6-884e-8ec615e5fe52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506027226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2506027226
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1968208979
Short name T50
Test name
Test status
Simulation time 1016830352 ps
CPU time 65.25 seconds
Started Aug 01 06:09:57 PM PDT 24
Finished Aug 01 06:11:02 PM PDT 24
Peak memory 238612 kb
Host smart-3463822a-c4d7-4d64-9d5a-7fbbc2d3e7f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968208979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1968208979
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3130404201
Short name T213
Test name
Test status
Simulation time 171662442 ps
CPU time 9.54 seconds
Started Aug 01 06:09:54 PM PDT 24
Finished Aug 01 06:10:04 PM PDT 24
Peak memory 212940 kb
Host smart-51960e97-f1fc-4572-b7d7-de7097a0b4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130404201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3130404201
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3936317278
Short name T9
Test name
Test status
Simulation time 428564363 ps
CPU time 5.38 seconds
Started Aug 01 06:10:02 PM PDT 24
Finished Aug 01 06:10:07 PM PDT 24
Peak memory 212072 kb
Host smart-e29cbc85-1a59-4aab-8a46-b74db3201918
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3936317278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3936317278
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.235488855
Short name T135
Test name
Test status
Simulation time 1167464619 ps
CPU time 13.85 seconds
Started Aug 01 06:09:52 PM PDT 24
Finished Aug 01 06:10:06 PM PDT 24
Peak memory 214472 kb
Host smart-db413643-008f-4fdd-9fc2-e7e8bb323fe3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235488855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.235488855
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2921903268
Short name T238
Test name
Test status
Simulation time 126642458 ps
CPU time 5.15 seconds
Started Aug 01 06:09:56 PM PDT 24
Finished Aug 01 06:10:01 PM PDT 24
Peak memory 212016 kb
Host smart-ff536856-c915-4cef-8952-dde66be461fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921903268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2921903268
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.640412999
Short name T187
Test name
Test status
Simulation time 2881658449 ps
CPU time 157.04 seconds
Started Aug 01 06:10:02 PM PDT 24
Finished Aug 01 06:12:39 PM PDT 24
Peak memory 238444 kb
Host smart-8319afeb-9ecb-4a26-a933-f6db3760f98d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640412999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.640412999
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.975557025
Short name T137
Test name
Test status
Simulation time 755534422 ps
CPU time 9.63 seconds
Started Aug 01 06:09:58 PM PDT 24
Finished Aug 01 06:10:08 PM PDT 24
Peak memory 213200 kb
Host smart-4db2a905-0590-42cf-a8a2-34677a8b6b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975557025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.975557025
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2665354596
Short name T266
Test name
Test status
Simulation time 394324625 ps
CPU time 5.61 seconds
Started Aug 01 06:09:54 PM PDT 24
Finished Aug 01 06:10:00 PM PDT 24
Peak memory 211340 kb
Host smart-87176f96-4f19-4938-a584-0eb2cd83e641
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2665354596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2665354596
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1491457140
Short name T188
Test name
Test status
Simulation time 209613766 ps
CPU time 14.1 seconds
Started Aug 01 06:10:02 PM PDT 24
Finished Aug 01 06:10:16 PM PDT 24
Peak memory 213508 kb
Host smart-64f17fb7-a9ed-4b3e-97d7-7698331f94bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491457140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1491457140
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3233285781
Short name T46
Test name
Test status
Simulation time 126591680 ps
CPU time 5.02 seconds
Started Aug 01 06:09:55 PM PDT 24
Finished Aug 01 06:10:00 PM PDT 24
Peak memory 212016 kb
Host smart-9499083b-1def-44e4-9e44-7b8b875b4518
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233285781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3233285781
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1053588337
Short name T169
Test name
Test status
Simulation time 28658988034 ps
CPU time 74.8 seconds
Started Aug 01 06:09:53 PM PDT 24
Finished Aug 01 06:11:09 PM PDT 24
Peak memory 238448 kb
Host smart-45fdb486-551d-498a-8b95-acc0eee1bb12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053588337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1053588337
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2369694169
Short name T316
Test name
Test status
Simulation time 261698963 ps
CPU time 11.42 seconds
Started Aug 01 06:09:52 PM PDT 24
Finished Aug 01 06:10:03 PM PDT 24
Peak memory 212848 kb
Host smart-f1f61d2c-63d5-4ef7-8995-707e5af448e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369694169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2369694169
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.909391383
Short name T44
Test name
Test status
Simulation time 560112150 ps
CPU time 6.59 seconds
Started Aug 01 06:09:56 PM PDT 24
Finished Aug 01 06:10:03 PM PDT 24
Peak memory 212112 kb
Host smart-46fa4814-caa6-4b36-a48e-155c597aa333
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=909391383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.909391383
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1200204380
Short name T274
Test name
Test status
Simulation time 1223356946 ps
CPU time 14.15 seconds
Started Aug 01 06:09:54 PM PDT 24
Finished Aug 01 06:10:09 PM PDT 24
Peak memory 216076 kb
Host smart-1508a3ff-4002-4827-83ae-9683cffdf159
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200204380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1200204380
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1295525839
Short name T63
Test name
Test status
Simulation time 87985015286 ps
CPU time 903.66 seconds
Started Aug 01 06:09:55 PM PDT 24
Finished Aug 01 06:24:59 PM PDT 24
Peak memory 236616 kb
Host smart-18f8b55c-afb3-433a-ad43-7b502bbddd1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295525839 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.1295525839
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3927513878
Short name T124
Test name
Test status
Simulation time 695838346 ps
CPU time 5.4 seconds
Started Aug 01 06:09:57 PM PDT 24
Finished Aug 01 06:10:02 PM PDT 24
Peak memory 212020 kb
Host smart-7eaa8f97-f758-415a-8a96-19c1846a22cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927513878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3927513878
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1606781473
Short name T184
Test name
Test status
Simulation time 44089554673 ps
CPU time 175.53 seconds
Started Aug 01 06:09:51 PM PDT 24
Finished Aug 01 06:12:47 PM PDT 24
Peak memory 236556 kb
Host smart-36ad14f2-7fbd-4b37-bdd5-100896cdc0e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606781473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1606781473
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1768217776
Short name T68
Test name
Test status
Simulation time 542919757 ps
CPU time 9.56 seconds
Started Aug 01 06:09:54 PM PDT 24
Finished Aug 01 06:10:04 PM PDT 24
Peak memory 212892 kb
Host smart-5a301843-4496-4925-9eb7-ec3ea14e33f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768217776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1768217776
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2405114071
Short name T24
Test name
Test status
Simulation time 824396455 ps
CPU time 6 seconds
Started Aug 01 06:09:54 PM PDT 24
Finished Aug 01 06:10:00 PM PDT 24
Peak memory 212128 kb
Host smart-968f75fc-038e-4d4e-9892-cb4daf8231c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2405114071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2405114071
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2884496030
Short name T42
Test name
Test status
Simulation time 844926726 ps
CPU time 12.79 seconds
Started Aug 01 06:09:57 PM PDT 24
Finished Aug 01 06:10:10 PM PDT 24
Peak memory 214480 kb
Host smart-812fbaf2-47b3-40b3-86e5-e549d7b4f22a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884496030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2884496030
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.631398852
Short name T18
Test name
Test status
Simulation time 313826155785 ps
CPU time 961.28 seconds
Started Aug 01 06:09:54 PM PDT 24
Finished Aug 01 06:25:55 PM PDT 24
Peak memory 234596 kb
Host smart-66500644-47cc-4921-9507-13a83de7a256
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631398852 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.631398852
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.4164412332
Short name T6
Test name
Test status
Simulation time 4491116712 ps
CPU time 7.24 seconds
Started Aug 01 06:09:14 PM PDT 24
Finished Aug 01 06:09:21 PM PDT 24
Peak memory 212036 kb
Host smart-88a94223-8258-49f6-96bb-b21d47eb401e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164412332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.4164412332
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2272352871
Short name T26
Test name
Test status
Simulation time 1388432181 ps
CPU time 86.95 seconds
Started Aug 01 06:09:10 PM PDT 24
Finished Aug 01 06:10:37 PM PDT 24
Peak memory 213332 kb
Host smart-f8cbec96-5685-41db-bfd5-96d2ab4f4c57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272352871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2272352871
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3451990544
Short name T66
Test name
Test status
Simulation time 500146307 ps
CPU time 11.39 seconds
Started Aug 01 06:09:14 PM PDT 24
Finished Aug 01 06:09:25 PM PDT 24
Peak memory 212844 kb
Host smart-07c90844-6c2c-4c59-bd9b-8c1d8365da0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451990544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3451990544
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2716022038
Short name T173
Test name
Test status
Simulation time 99774123 ps
CPU time 5.77 seconds
Started Aug 01 06:09:18 PM PDT 24
Finished Aug 01 06:09:24 PM PDT 24
Peak memory 212084 kb
Host smart-4a569f52-8c9c-4d5c-b910-b806bda37469
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716022038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2716022038
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3907825240
Short name T22
Test name
Test status
Simulation time 284492608 ps
CPU time 6.29 seconds
Started Aug 01 06:09:14 PM PDT 24
Finished Aug 01 06:09:21 PM PDT 24
Peak memory 211996 kb
Host smart-2718bfb7-2554-461e-ba0e-4665c124f62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907825240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3907825240
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.338873771
Short name T285
Test name
Test status
Simulation time 809576406 ps
CPU time 10.16 seconds
Started Aug 01 06:09:14 PM PDT 24
Finished Aug 01 06:09:24 PM PDT 24
Peak memory 211904 kb
Host smart-e13aa7e4-23b3-40ea-9905-423f0f3d59e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338873771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.338873771
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1572057328
Short name T216
Test name
Test status
Simulation time 350493199 ps
CPU time 4.26 seconds
Started Aug 01 06:09:13 PM PDT 24
Finished Aug 01 06:09:17 PM PDT 24
Peak memory 212032 kb
Host smart-f87ba399-ccf9-4cbf-ba73-7ed9e7b5533a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572057328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1572057328
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.283634487
Short name T209
Test name
Test status
Simulation time 2941369090 ps
CPU time 139.32 seconds
Started Aug 01 06:09:15 PM PDT 24
Finished Aug 01 06:11:35 PM PDT 24
Peak memory 213752 kb
Host smart-a6211306-f34e-48dd-bdbe-ed4dae4a2589
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283634487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.283634487
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3295173027
Short name T165
Test name
Test status
Simulation time 698358790 ps
CPU time 9.65 seconds
Started Aug 01 06:09:12 PM PDT 24
Finished Aug 01 06:09:22 PM PDT 24
Peak memory 212888 kb
Host smart-fa79da43-b828-4106-91e1-12654ddccb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295173027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3295173027
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1735679898
Short name T236
Test name
Test status
Simulation time 1029574466 ps
CPU time 8.82 seconds
Started Aug 01 06:09:10 PM PDT 24
Finished Aug 01 06:09:18 PM PDT 24
Peak memory 212184 kb
Host smart-fa060174-e866-453a-8fd9-6a2062960394
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1735679898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1735679898
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1517717277
Short name T75
Test name
Test status
Simulation time 555588673 ps
CPU time 6.34 seconds
Started Aug 01 06:09:13 PM PDT 24
Finished Aug 01 06:09:20 PM PDT 24
Peak memory 212212 kb
Host smart-b082e3b1-49f2-4103-8a1c-5ca7ec8bf101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517717277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1517717277
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2617209796
Short name T125
Test name
Test status
Simulation time 400372103 ps
CPU time 13.32 seconds
Started Aug 01 06:09:06 PM PDT 24
Finished Aug 01 06:09:20 PM PDT 24
Peak memory 212088 kb
Host smart-6bf12280-e2f2-4ff0-9c8c-5a2cf1307d60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617209796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2617209796
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2595471053
Short name T121
Test name
Test status
Simulation time 591404270 ps
CPU time 7.97 seconds
Started Aug 01 06:09:10 PM PDT 24
Finished Aug 01 06:09:18 PM PDT 24
Peak memory 211996 kb
Host smart-eeb9386d-3e2e-4335-aa9e-b8827c933958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595471053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2595471053
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3577296078
Short name T253
Test name
Test status
Simulation time 8147125428 ps
CPU time 113.88 seconds
Started Aug 01 06:09:10 PM PDT 24
Finished Aug 01 06:11:04 PM PDT 24
Peak memory 237804 kb
Host smart-f89302ec-5b11-4a4f-bc79-ca76b0536351
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577296078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3577296078
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1284037690
Short name T208
Test name
Test status
Simulation time 308485879 ps
CPU time 10.94 seconds
Started Aug 01 06:09:20 PM PDT 24
Finished Aug 01 06:09:31 PM PDT 24
Peak memory 213008 kb
Host smart-26266584-e84c-41b5-a93f-b92c3e036a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284037690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1284037690
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1462274959
Short name T247
Test name
Test status
Simulation time 2207498133 ps
CPU time 6.54 seconds
Started Aug 01 06:09:11 PM PDT 24
Finished Aug 01 06:09:18 PM PDT 24
Peak memory 212232 kb
Host smart-0ba83384-abdc-43b6-a369-dd086cfd0668
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1462274959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1462274959
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.796393043
Short name T16
Test name
Test status
Simulation time 137030951 ps
CPU time 6.36 seconds
Started Aug 01 06:09:12 PM PDT 24
Finished Aug 01 06:09:19 PM PDT 24
Peak memory 212316 kb
Host smart-0e026b86-37cf-4d7f-94a5-99dba7fb08c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796393043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.796393043
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3970933626
Short name T202
Test name
Test status
Simulation time 748007884 ps
CPU time 9.85 seconds
Started Aug 01 06:09:17 PM PDT 24
Finished Aug 01 06:09:27 PM PDT 24
Peak memory 214620 kb
Host smart-01a2c5cd-137a-481a-83b9-87eca5cd7712
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970933626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3970933626
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4027420651
Short name T3
Test name
Test status
Simulation time 85385278 ps
CPU time 4.37 seconds
Started Aug 01 06:09:15 PM PDT 24
Finished Aug 01 06:09:19 PM PDT 24
Peak memory 212032 kb
Host smart-cf319525-5603-417f-895b-4c36a44d0cb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027420651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4027420651
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.999935928
Short name T225
Test name
Test status
Simulation time 6176679480 ps
CPU time 142.05 seconds
Started Aug 01 06:09:10 PM PDT 24
Finished Aug 01 06:11:32 PM PDT 24
Peak memory 238416 kb
Host smart-c5b0d817-ca04-4a66-81b3-0ea0cc183f21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999935928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.999935928
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.596095732
Short name T159
Test name
Test status
Simulation time 251070297 ps
CPU time 11.33 seconds
Started Aug 01 06:09:14 PM PDT 24
Finished Aug 01 06:09:26 PM PDT 24
Peak memory 212812 kb
Host smart-22338f1e-bd56-46b6-95b5-3d8311f2f3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596095732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.596095732
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1439748917
Short name T23
Test name
Test status
Simulation time 136368677 ps
CPU time 6.19 seconds
Started Aug 01 06:09:09 PM PDT 24
Finished Aug 01 06:09:15 PM PDT 24
Peak memory 212128 kb
Host smart-59342490-a7ef-4fde-beea-d298633fe23c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1439748917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1439748917
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2639928403
Short name T275
Test name
Test status
Simulation time 136670538 ps
CPU time 6.21 seconds
Started Aug 01 06:09:13 PM PDT 24
Finished Aug 01 06:09:19 PM PDT 24
Peak memory 212164 kb
Host smart-83fefe42-3046-4b4f-93a5-f7e2dcecc1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639928403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2639928403
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3524309062
Short name T211
Test name
Test status
Simulation time 2227882807 ps
CPU time 26.56 seconds
Started Aug 01 06:09:14 PM PDT 24
Finished Aug 01 06:09:41 PM PDT 24
Peak memory 217788 kb
Host smart-86bee5e7-1aee-4863-af32-a3f30533ce8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524309062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3524309062
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2348655456
Short name T157
Test name
Test status
Simulation time 132753524 ps
CPU time 5.4 seconds
Started Aug 01 06:09:14 PM PDT 24
Finished Aug 01 06:09:20 PM PDT 24
Peak memory 212000 kb
Host smart-5e73916e-ecd1-4de3-9887-42ad46b14437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348655456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2348655456
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1982118254
Short name T142
Test name
Test status
Simulation time 2349456397 ps
CPU time 121.49 seconds
Started Aug 01 06:09:14 PM PDT 24
Finished Aug 01 06:11:16 PM PDT 24
Peak memory 237176 kb
Host smart-83d55023-f7fc-4792-95b1-7b0ec43b36f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982118254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1982118254
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.435565011
Short name T245
Test name
Test status
Simulation time 697591657 ps
CPU time 9.51 seconds
Started Aug 01 06:09:14 PM PDT 24
Finished Aug 01 06:09:24 PM PDT 24
Peak memory 212760 kb
Host smart-72e299a6-aef0-4ba2-8c00-bba709da4a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435565011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.435565011
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2579958036
Short name T164
Test name
Test status
Simulation time 526733459 ps
CPU time 6.21 seconds
Started Aug 01 06:09:24 PM PDT 24
Finished Aug 01 06:09:30 PM PDT 24
Peak memory 212108 kb
Host smart-bca573d2-059e-4d34-9a52-4f5f9ef96dba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2579958036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2579958036
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.944623665
Short name T302
Test name
Test status
Simulation time 552738606 ps
CPU time 6.24 seconds
Started Aug 01 06:09:16 PM PDT 24
Finished Aug 01 06:09:23 PM PDT 24
Peak memory 212052 kb
Host smart-f26b910f-51f7-44f4-bf4c-ac1413d7da8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944623665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.944623665
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1465243037
Short name T269
Test name
Test status
Simulation time 281777871 ps
CPU time 15.06 seconds
Started Aug 01 06:09:14 PM PDT 24
Finished Aug 01 06:09:29 PM PDT 24
Peak memory 213928 kb
Host smart-40a03814-c704-44a9-bf7f-8c169797506e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465243037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1465243037
Directory /workspace/9.rom_ctrl_stress_all/latest
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