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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.19 96.89 91.85 97.67 100.00 98.28 97.30 98.37


Total test records in report: 415
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T294 /workspace/coverage/default/14.rom_ctrl_alert_test.269167403 Aug 02 05:54:59 PM PDT 24 Aug 02 05:55:04 PM PDT 24 262283195 ps
T295 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.851534004 Aug 02 05:55:20 PM PDT 24 Aug 02 05:55:29 PM PDT 24 1277549820 ps
T296 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2124247366 Aug 02 05:54:50 PM PDT 24 Aug 02 05:55:00 PM PDT 24 670629808 ps
T297 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.119009565 Aug 02 05:55:08 PM PDT 24 Aug 02 05:55:14 PM PDT 24 197313065 ps
T298 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.450383498 Aug 02 05:55:22 PM PDT 24 Aug 02 05:55:32 PM PDT 24 169896511 ps
T299 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2651280303 Aug 02 05:54:33 PM PDT 24 Aug 02 05:54:43 PM PDT 24 168579587 ps
T300 /workspace/coverage/default/17.rom_ctrl_alert_test.1951894399 Aug 02 05:54:56 PM PDT 24 Aug 02 05:55:00 PM PDT 24 347040945 ps
T301 /workspace/coverage/default/42.rom_ctrl_stress_all.3277771285 Aug 02 05:55:26 PM PDT 24 Aug 02 05:55:38 PM PDT 24 572439359 ps
T302 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1517658826 Aug 02 05:54:48 PM PDT 24 Aug 02 05:54:59 PM PDT 24 506486758 ps
T303 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4150936191 Aug 02 05:55:19 PM PDT 24 Aug 02 05:55:25 PM PDT 24 540687171 ps
T304 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.591493929 Aug 02 05:55:29 PM PDT 24 Aug 02 05:55:38 PM PDT 24 1943001619 ps
T305 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1670266500 Aug 02 05:55:03 PM PDT 24 Aug 02 05:56:36 PM PDT 24 6070953315 ps
T306 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1449716554 Aug 02 05:55:16 PM PDT 24 Aug 02 05:57:47 PM PDT 24 4465910412 ps
T307 /workspace/coverage/default/38.rom_ctrl_stress_all.2327084493 Aug 02 05:55:19 PM PDT 24 Aug 02 05:55:37 PM PDT 24 325505896 ps
T308 /workspace/coverage/default/34.rom_ctrl_stress_all.2496974874 Aug 02 05:55:20 PM PDT 24 Aug 02 05:55:33 PM PDT 24 220497633 ps
T309 /workspace/coverage/default/9.rom_ctrl_stress_all.1711516151 Aug 02 05:54:49 PM PDT 24 Aug 02 05:54:58 PM PDT 24 862210740 ps
T310 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1244185120 Aug 02 05:55:08 PM PDT 24 Aug 02 05:56:49 PM PDT 24 3401448265 ps
T311 /workspace/coverage/default/41.rom_ctrl_alert_test.3355438396 Aug 02 05:55:31 PM PDT 24 Aug 02 05:55:36 PM PDT 24 89024945 ps
T312 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.403188389 Aug 02 05:55:24 PM PDT 24 Aug 02 05:55:30 PM PDT 24 527225175 ps
T313 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2271926854 Aug 02 05:54:37 PM PDT 24 Aug 02 05:54:44 PM PDT 24 537992166 ps
T314 /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2312519711 Aug 02 05:54:53 PM PDT 24 Aug 02 07:28:39 PM PDT 24 132849133538 ps
T315 /workspace/coverage/default/8.rom_ctrl_smoke.2648177709 Aug 02 05:54:44 PM PDT 24 Aug 02 05:54:51 PM PDT 24 294828393 ps
T316 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.4144797579 Aug 02 05:55:07 PM PDT 24 Aug 02 05:55:18 PM PDT 24 2262871867 ps
T317 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3304408740 Aug 02 05:54:34 PM PDT 24 Aug 02 05:57:46 PM PDT 24 5490107047 ps
T318 /workspace/coverage/default/18.rom_ctrl_alert_test.3207222903 Aug 02 05:54:57 PM PDT 24 Aug 02 05:55:01 PM PDT 24 173076124 ps
T319 /workspace/coverage/default/21.rom_ctrl_stress_all.694695456 Aug 02 05:55:04 PM PDT 24 Aug 02 05:55:12 PM PDT 24 177471087 ps
T320 /workspace/coverage/default/48.rom_ctrl_alert_test.1022621387 Aug 02 05:55:33 PM PDT 24 Aug 02 05:55:37 PM PDT 24 89299481 ps
T321 /workspace/coverage/default/39.rom_ctrl_stress_all.3725374837 Aug 02 05:55:16 PM PDT 24 Aug 02 05:55:35 PM PDT 24 305266309 ps
T322 /workspace/coverage/default/44.rom_ctrl_alert_test.2029147093 Aug 02 05:55:23 PM PDT 24 Aug 02 05:55:28 PM PDT 24 589534932 ps
T323 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.631458023 Aug 02 05:54:53 PM PDT 24 Aug 02 05:56:48 PM PDT 24 2161405996 ps
T324 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3314868971 Aug 02 05:54:44 PM PDT 24 Aug 02 05:54:54 PM PDT 24 330465923 ps
T325 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3948717302 Aug 02 05:55:24 PM PDT 24 Aug 02 05:55:36 PM PDT 24 784549842 ps
T326 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1051770534 Aug 02 05:54:52 PM PDT 24 Aug 02 05:54:59 PM PDT 24 280157747 ps
T327 /workspace/coverage/default/33.rom_ctrl_stress_all.339676179 Aug 02 05:55:16 PM PDT 24 Aug 02 05:55:35 PM PDT 24 458613286 ps
T328 /workspace/coverage/default/14.rom_ctrl_stress_all.1688405999 Aug 02 05:54:51 PM PDT 24 Aug 02 05:55:00 PM PDT 24 305469828 ps
T329 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1291236890 Aug 02 05:54:44 PM PDT 24 Aug 02 05:54:56 PM PDT 24 1253097131 ps
T330 /workspace/coverage/default/4.rom_ctrl_smoke.2994696027 Aug 02 05:54:45 PM PDT 24 Aug 02 05:54:54 PM PDT 24 519908389 ps
T331 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4048519985 Aug 02 05:55:40 PM PDT 24 Aug 02 05:55:47 PM PDT 24 88079740 ps
T332 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2698027464 Aug 02 05:56:06 PM PDT 24 Aug 02 05:56:13 PM PDT 24 262924485 ps
T50 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.927308265 Aug 02 05:56:02 PM PDT 24 Aug 02 05:56:42 PM PDT 24 276692645 ps
T54 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3835680058 Aug 02 05:55:40 PM PDT 24 Aug 02 05:55:46 PM PDT 24 654156995 ps
T55 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1498452048 Aug 02 05:56:18 PM PDT 24 Aug 02 05:56:23 PM PDT 24 594535768 ps
T85 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1496915814 Aug 02 05:55:45 PM PDT 24 Aug 02 05:55:50 PM PDT 24 91632204 ps
T51 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2385120672 Aug 02 05:56:09 PM PDT 24 Aug 02 05:57:18 PM PDT 24 512174963 ps
T91 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1209569584 Aug 02 05:55:57 PM PDT 24 Aug 02 05:56:02 PM PDT 24 498754820 ps
T60 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1652579670 Aug 02 05:55:51 PM PDT 24 Aug 02 05:55:57 PM PDT 24 252149704 ps
T86 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2801773758 Aug 02 05:55:53 PM PDT 24 Aug 02 05:55:58 PM PDT 24 1247562162 ps
T52 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2367447769 Aug 02 05:56:02 PM PDT 24 Aug 02 05:56:40 PM PDT 24 595416141 ps
T333 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2953418519 Aug 02 05:55:41 PM PDT 24 Aug 02 05:55:47 PM PDT 24 671880407 ps
T92 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1870288504 Aug 02 05:55:54 PM PDT 24 Aug 02 05:55:58 PM PDT 24 175317723 ps
T334 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.78969829 Aug 02 05:55:57 PM PDT 24 Aug 02 05:56:07 PM PDT 24 2064497060 ps
T61 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1935769567 Aug 02 05:55:39 PM PDT 24 Aug 02 05:55:45 PM PDT 24 543155981 ps
T100 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1918053224 Aug 02 05:55:53 PM PDT 24 Aug 02 05:57:01 PM PDT 24 442146627 ps
T335 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3094048026 Aug 02 05:55:31 PM PDT 24 Aug 02 05:55:36 PM PDT 24 291159502 ps
T93 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3347571302 Aug 02 05:55:43 PM PDT 24 Aug 02 05:55:48 PM PDT 24 88202940 ps
T87 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2062066663 Aug 02 05:55:48 PM PDT 24 Aug 02 05:55:54 PM PDT 24 98140208 ps
T336 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2786194089 Aug 02 05:55:53 PM PDT 24 Aug 02 05:56:01 PM PDT 24 8172689930 ps
T337 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1607064421 Aug 02 05:55:58 PM PDT 24 Aug 02 05:56:06 PM PDT 24 127914157 ps
T338 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.347788304 Aug 02 05:56:16 PM PDT 24 Aug 02 05:56:20 PM PDT 24 86485442 ps
T339 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3771070602 Aug 02 05:55:50 PM PDT 24 Aug 02 05:55:54 PM PDT 24 334963544 ps
T62 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.992630480 Aug 02 05:55:44 PM PDT 24 Aug 02 05:55:49 PM PDT 24 250326337 ps
T340 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3955747072 Aug 02 05:55:30 PM PDT 24 Aug 02 05:55:37 PM PDT 24 93612823 ps
T63 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2747542795 Aug 02 05:55:55 PM PDT 24 Aug 02 05:56:00 PM PDT 24 520371261 ps
T341 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3358178696 Aug 02 05:55:55 PM PDT 24 Aug 02 05:56:06 PM PDT 24 159111459 ps
T342 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3849299648 Aug 02 05:55:55 PM PDT 24 Aug 02 05:56:14 PM PDT 24 1401316033 ps
T88 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4214410364 Aug 02 05:55:59 PM PDT 24 Aug 02 05:56:03 PM PDT 24 557381301 ps
T343 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.267780939 Aug 02 05:56:10 PM PDT 24 Aug 02 05:56:15 PM PDT 24 374363385 ps
T344 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3198354440 Aug 02 05:55:45 PM PDT 24 Aug 02 05:55:50 PM PDT 24 383263579 ps
T345 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3814691562 Aug 02 05:56:20 PM PDT 24 Aug 02 05:56:28 PM PDT 24 106437538 ps
T101 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1930408596 Aug 02 05:55:47 PM PDT 24 Aug 02 05:56:56 PM PDT 24 492485168 ps
T346 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2738840966 Aug 02 05:55:38 PM PDT 24 Aug 02 05:55:43 PM PDT 24 2486917177 ps
T347 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3363249915 Aug 02 05:55:40 PM PDT 24 Aug 02 05:55:44 PM PDT 24 85653832 ps
T348 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.469309773 Aug 02 05:55:41 PM PDT 24 Aug 02 05:55:46 PM PDT 24 91009255 ps
T349 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3833408347 Aug 02 05:55:47 PM PDT 24 Aug 02 05:55:51 PM PDT 24 444160499 ps
T350 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2176638968 Aug 02 05:55:47 PM PDT 24 Aug 02 05:55:51 PM PDT 24 1193481170 ps
T351 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1742657159 Aug 02 05:55:52 PM PDT 24 Aug 02 05:55:59 PM PDT 24 88212546 ps
T352 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3321737580 Aug 02 05:55:45 PM PDT 24 Aug 02 05:55:54 PM PDT 24 533005292 ps
T353 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3454973711 Aug 02 05:55:54 PM PDT 24 Aug 02 05:55:59 PM PDT 24 100434687 ps
T89 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2782640925 Aug 02 05:55:49 PM PDT 24 Aug 02 05:55:53 PM PDT 24 88906605 ps
T90 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2021791741 Aug 02 05:55:40 PM PDT 24 Aug 02 05:55:44 PM PDT 24 463850529 ps
T354 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1226484683 Aug 02 05:55:37 PM PDT 24 Aug 02 05:55:43 PM PDT 24 1491179686 ps
T64 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3042966549 Aug 02 05:56:03 PM PDT 24 Aug 02 05:56:07 PM PDT 24 350131614 ps
T102 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2457787730 Aug 02 05:55:56 PM PDT 24 Aug 02 05:56:33 PM PDT 24 157840197 ps
T355 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.957158092 Aug 02 05:55:40 PM PDT 24 Aug 02 05:55:45 PM PDT 24 249858315 ps
T356 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2692676870 Aug 02 05:55:36 PM PDT 24 Aug 02 05:55:41 PM PDT 24 336417652 ps
T357 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.466450823 Aug 02 05:55:50 PM PDT 24 Aug 02 05:55:55 PM PDT 24 502521436 ps
T65 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2574338934 Aug 02 05:55:38 PM PDT 24 Aug 02 05:55:47 PM PDT 24 1033247726 ps
T358 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.486786787 Aug 02 05:56:02 PM PDT 24 Aug 02 05:56:06 PM PDT 24 695962689 ps
T359 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.634349957 Aug 02 05:55:49 PM PDT 24 Aug 02 05:55:56 PM PDT 24 126954584 ps
T360 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.322983276 Aug 02 05:55:37 PM PDT 24 Aug 02 05:55:44 PM PDT 24 515836555 ps
T361 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2685525906 Aug 02 05:55:56 PM PDT 24 Aug 02 05:56:01 PM PDT 24 178268143 ps
T362 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1937022820 Aug 02 05:56:01 PM PDT 24 Aug 02 05:56:07 PM PDT 24 996118817 ps
T363 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3941224996 Aug 02 05:56:02 PM PDT 24 Aug 02 05:56:10 PM PDT 24 85621643 ps
T364 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2660927357 Aug 02 05:55:55 PM PDT 24 Aug 02 05:55:59 PM PDT 24 266137997 ps
T365 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1462374395 Aug 02 05:55:50 PM PDT 24 Aug 02 05:55:55 PM PDT 24 132197511 ps
T366 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3711545165 Aug 02 05:56:06 PM PDT 24 Aug 02 05:56:12 PM PDT 24 562924088 ps
T367 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1939467721 Aug 02 05:56:03 PM PDT 24 Aug 02 05:56:10 PM PDT 24 142345409 ps
T368 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1554048628 Aug 02 05:55:50 PM PDT 24 Aug 02 05:55:57 PM PDT 24 93338791 ps
T107 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.525520370 Aug 02 05:56:01 PM PDT 24 Aug 02 05:57:12 PM PDT 24 454449333 ps
T369 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1530686487 Aug 02 05:56:02 PM PDT 24 Aug 02 05:56:10 PM PDT 24 131781407 ps
T103 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1306987538 Aug 02 05:55:46 PM PDT 24 Aug 02 05:56:22 PM PDT 24 631943705 ps
T370 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.750707073 Aug 02 05:55:47 PM PDT 24 Aug 02 05:55:54 PM PDT 24 653119330 ps
T66 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3746908522 Aug 02 05:55:45 PM PDT 24 Aug 02 05:56:08 PM PDT 24 10509565423 ps
T67 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.244682704 Aug 02 05:55:55 PM PDT 24 Aug 02 05:56:00 PM PDT 24 88112588 ps
T68 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3129372879 Aug 02 05:56:08 PM PDT 24 Aug 02 05:56:13 PM PDT 24 348148037 ps
T371 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3806122477 Aug 02 05:55:48 PM PDT 24 Aug 02 05:55:54 PM PDT 24 1388683487 ps
T372 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1067773628 Aug 02 05:56:10 PM PDT 24 Aug 02 05:56:15 PM PDT 24 366510550 ps
T373 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4134269749 Aug 02 05:55:40 PM PDT 24 Aug 02 05:55:46 PM PDT 24 179408194 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.592402337 Aug 02 05:55:48 PM PDT 24 Aug 02 05:55:53 PM PDT 24 502986840 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1582219617 Aug 02 05:55:40 PM PDT 24 Aug 02 05:55:45 PM PDT 24 249862461 ps
T376 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1447888284 Aug 02 05:56:13 PM PDT 24 Aug 02 05:56:49 PM PDT 24 799130822 ps
T377 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3822701242 Aug 02 05:55:57 PM PDT 24 Aug 02 05:56:02 PM PDT 24 462632135 ps
T104 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2341930739 Aug 02 05:55:40 PM PDT 24 Aug 02 05:56:20 PM PDT 24 703858634 ps
T109 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4083272768 Aug 02 05:55:54 PM PDT 24 Aug 02 05:56:31 PM PDT 24 153264953 ps
T378 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2313134396 Aug 02 05:55:53 PM PDT 24 Aug 02 05:56:01 PM PDT 24 250355935 ps
T379 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2406239885 Aug 02 05:56:13 PM PDT 24 Aug 02 05:56:20 PM PDT 24 493889277 ps
T105 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2402952469 Aug 02 05:55:38 PM PDT 24 Aug 02 05:56:50 PM PDT 24 359586338 ps
T97 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.526859495 Aug 02 05:55:46 PM PDT 24 Aug 02 05:55:57 PM PDT 24 146011128 ps
T380 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2601573539 Aug 02 05:56:04 PM PDT 24 Aug 02 05:56:11 PM PDT 24 146752630 ps
T381 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1946524098 Aug 02 05:56:07 PM PDT 24 Aug 02 05:56:13 PM PDT 24 134548695 ps
T78 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1545678391 Aug 02 05:55:47 PM PDT 24 Aug 02 05:55:52 PM PDT 24 88740239 ps
T382 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1113034984 Aug 02 05:56:10 PM PDT 24 Aug 02 05:56:15 PM PDT 24 89247926 ps
T383 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.103544138 Aug 02 05:55:56 PM PDT 24 Aug 02 05:56:33 PM PDT 24 749109119 ps
T108 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.10124539 Aug 02 05:56:09 PM PDT 24 Aug 02 05:56:48 PM PDT 24 6842499251 ps
T384 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1303783348 Aug 02 05:55:35 PM PDT 24 Aug 02 05:55:46 PM PDT 24 505876347 ps
T385 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3512785068 Aug 02 05:55:57 PM PDT 24 Aug 02 05:56:03 PM PDT 24 284811015 ps
T386 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.570078380 Aug 02 05:55:50 PM PDT 24 Aug 02 05:55:54 PM PDT 24 346235694 ps
T387 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.452365667 Aug 02 05:56:01 PM PDT 24 Aug 02 05:56:06 PM PDT 24 252588174 ps
T388 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1195021005 Aug 02 05:56:09 PM PDT 24 Aug 02 05:56:17 PM PDT 24 540396055 ps
T389 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.512820495 Aug 02 05:56:02 PM PDT 24 Aug 02 05:56:06 PM PDT 24 379083359 ps
T390 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2261182533 Aug 02 05:55:52 PM PDT 24 Aug 02 05:55:57 PM PDT 24 169612331 ps
T79 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2479510237 Aug 02 05:55:44 PM PDT 24 Aug 02 05:55:52 PM PDT 24 130116743 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1670426020 Aug 02 05:55:38 PM PDT 24 Aug 02 05:55:43 PM PDT 24 521232298 ps
T80 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1621018993 Aug 02 05:55:39 PM PDT 24 Aug 02 05:55:44 PM PDT 24 512745802 ps
T392 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1570353394 Aug 02 05:55:52 PM PDT 24 Aug 02 05:55:57 PM PDT 24 518778397 ps
T393 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.73213729 Aug 02 05:55:52 PM PDT 24 Aug 02 05:55:58 PM PDT 24 696024573 ps
T394 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3528353877 Aug 02 05:56:08 PM PDT 24 Aug 02 05:56:15 PM PDT 24 311288221 ps
T395 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2728494620 Aug 02 05:56:01 PM PDT 24 Aug 02 05:56:06 PM PDT 24 518063873 ps
T396 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2860372647 Aug 02 05:55:47 PM PDT 24 Aug 02 05:55:52 PM PDT 24 87633247 ps
T397 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3636498048 Aug 02 05:55:45 PM PDT 24 Aug 02 05:56:54 PM PDT 24 273958473 ps
T106 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2912152875 Aug 02 05:55:33 PM PDT 24 Aug 02 05:56:44 PM PDT 24 383274191 ps
T398 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.799940902 Aug 02 05:56:13 PM PDT 24 Aug 02 05:56:21 PM PDT 24 503005594 ps
T110 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3597566616 Aug 02 05:55:57 PM PDT 24 Aug 02 05:56:33 PM PDT 24 144853684 ps
T399 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.815095168 Aug 02 05:56:03 PM PDT 24 Aug 02 05:56:11 PM PDT 24 88499916 ps
T400 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4046800361 Aug 02 05:55:50 PM PDT 24 Aug 02 05:55:54 PM PDT 24 93947407 ps
T401 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3226808980 Aug 02 05:55:46 PM PDT 24 Aug 02 05:55:50 PM PDT 24 222422944 ps
T402 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1148198818 Aug 02 05:55:40 PM PDT 24 Aug 02 05:55:48 PM PDT 24 145145995 ps
T403 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3561273966 Aug 02 05:55:48 PM PDT 24 Aug 02 05:55:54 PM PDT 24 171726432 ps
T404 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1232768438 Aug 02 05:55:58 PM PDT 24 Aug 02 05:56:05 PM PDT 24 520152018 ps
T405 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1329091208 Aug 02 05:56:00 PM PDT 24 Aug 02 05:57:09 PM PDT 24 924536032 ps
T406 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4070852539 Aug 02 05:56:14 PM PDT 24 Aug 02 05:56:42 PM PDT 24 543280316 ps
T407 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1283224720 Aug 02 05:55:39 PM PDT 24 Aug 02 05:55:47 PM PDT 24 345201169 ps
T81 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1373475137 Aug 02 05:56:10 PM PDT 24 Aug 02 05:56:15 PM PDT 24 130999415 ps
T111 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1676322782 Aug 02 05:55:51 PM PDT 24 Aug 02 05:57:01 PM PDT 24 488645553 ps
T408 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.890201379 Aug 02 05:55:42 PM PDT 24 Aug 02 05:55:48 PM PDT 24 1493591462 ps
T409 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3124711344 Aug 02 05:55:53 PM PDT 24 Aug 02 05:55:59 PM PDT 24 281881455 ps
T410 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.391512680 Aug 02 05:55:51 PM PDT 24 Aug 02 05:55:57 PM PDT 24 1386919818 ps
T82 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1358436177 Aug 02 05:55:57 PM PDT 24 Aug 02 05:56:01 PM PDT 24 175084779 ps
T411 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2871008230 Aug 02 05:56:10 PM PDT 24 Aug 02 05:56:15 PM PDT 24 311807359 ps
T412 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3925553453 Aug 02 05:55:54 PM PDT 24 Aug 02 05:56:31 PM PDT 24 222634610 ps
T413 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3143481061 Aug 02 05:55:58 PM PDT 24 Aug 02 05:56:02 PM PDT 24 354519903 ps
T83 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1007840861 Aug 02 05:55:59 PM PDT 24 Aug 02 05:56:05 PM PDT 24 131558682 ps
T84 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3334617727 Aug 02 05:55:38 PM PDT 24 Aug 02 05:55:44 PM PDT 24 501078940 ps
T414 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.654358373 Aug 02 05:55:34 PM PDT 24 Aug 02 05:55:39 PM PDT 24 249859859 ps
T415 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3546633536 Aug 02 05:55:46 PM PDT 24 Aug 02 05:55:55 PM PDT 24 2184668726 ps

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3197697849
Short name T4
Test name
Test status
Simulation time 27303577341 ps
CPU time 1083.21 seconds
Started Aug 02 05:54:37 PM PDT 24
Finished Aug 02 06:12:40 PM PDT 24
Peak memory 236724 kb
Host smart-f975efa5-7dfc-4575-a008-9612a0ff3d90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197697849 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.3197697849
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1497023207
Short name T1
Test name
Test status
Simulation time 10176748402 ps
CPU time 159.25 seconds
Started Aug 02 05:55:33 PM PDT 24
Finished Aug 02 05:58:12 PM PDT 24
Peak memory 235584 kb
Host smart-61c42be7-7c1d-478e-88f7-d9d6d77eb0ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497023207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1497023207
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.645589029
Short name T15
Test name
Test status
Simulation time 34000190404 ps
CPU time 1296.44 seconds
Started Aug 02 05:55:18 PM PDT 24
Finished Aug 02 06:16:55 PM PDT 24
Peak memory 235692 kb
Host smart-7fba9935-d837-4b43-93bc-23d25a1b15fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645589029 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.645589029
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2385120672
Short name T51
Test name
Test status
Simulation time 512174963 ps
CPU time 68.7 seconds
Started Aug 02 05:56:09 PM PDT 24
Finished Aug 02 05:57:18 PM PDT 24
Peak memory 213200 kb
Host smart-292ac42f-d1c6-4151-acc0-32f26bb7c7d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385120672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2385120672
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1436794642
Short name T35
Test name
Test status
Simulation time 3187058696 ps
CPU time 140.35 seconds
Started Aug 02 05:54:53 PM PDT 24
Finished Aug 02 05:57:14 PM PDT 24
Peak memory 213212 kb
Host smart-0c8f2183-c3dd-48ad-ab51-08f07583d914
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436794642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1436794642
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2477371937
Short name T20
Test name
Test status
Simulation time 496317308 ps
CPU time 52.12 seconds
Started Aug 02 05:54:43 PM PDT 24
Finished Aug 02 05:55:35 PM PDT 24
Peak memory 238508 kb
Host smart-29a651a0-0204-42f0-8bb6-4eaa72b6fba2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477371937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2477371937
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.992630480
Short name T62
Test name
Test status
Simulation time 250326337 ps
CPU time 5.02 seconds
Started Aug 02 05:55:44 PM PDT 24
Finished Aug 02 05:55:49 PM PDT 24
Peak memory 218228 kb
Host smart-720dfda7-2089-417d-87ce-dc53226451ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992630480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.992630480
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.957467155
Short name T34
Test name
Test status
Simulation time 831907322 ps
CPU time 4.4 seconds
Started Aug 02 05:55:01 PM PDT 24
Finished Aug 02 05:55:06 PM PDT 24
Peak memory 212052 kb
Host smart-93e8cf83-9eb0-482f-affc-a464626d5cb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957467155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.957467155
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2912152875
Short name T106
Test name
Test status
Simulation time 383274191 ps
CPU time 71.31 seconds
Started Aug 02 05:55:33 PM PDT 24
Finished Aug 02 05:56:44 PM PDT 24
Peak memory 213180 kb
Host smart-6f780a7f-a162-4500-9546-4d47aead2b89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912152875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2912152875
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3597566616
Short name T110
Test name
Test status
Simulation time 144853684 ps
CPU time 35.6 seconds
Started Aug 02 05:55:57 PM PDT 24
Finished Aug 02 05:56:33 PM PDT 24
Peak memory 219556 kb
Host smart-a4c5e57b-e176-45f2-8077-0f1eed20c9b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597566616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3597566616
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.485472874
Short name T16
Test name
Test status
Simulation time 138083055 ps
CPU time 6.6 seconds
Started Aug 02 05:55:05 PM PDT 24
Finished Aug 02 05:55:12 PM PDT 24
Peak memory 212216 kb
Host smart-eb4c3e19-88fd-4ae9-8519-3903ed143e31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=485472874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.485472874
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3551711353
Short name T31
Test name
Test status
Simulation time 2490546978 ps
CPU time 11.32 seconds
Started Aug 02 05:54:52 PM PDT 24
Finished Aug 02 05:55:04 PM PDT 24
Peak memory 213084 kb
Host smart-af31ea77-d6cc-4a80-8808-f277d3b61208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551711353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3551711353
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2856849422
Short name T249
Test name
Test status
Simulation time 335121067 ps
CPU time 9.54 seconds
Started Aug 02 05:54:52 PM PDT 24
Finished Aug 02 05:55:02 PM PDT 24
Peak memory 213340 kb
Host smart-a48b5de6-a02b-40c5-aed1-76d974a6fdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856849422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2856849422
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1329091208
Short name T405
Test name
Test status
Simulation time 924536032 ps
CPU time 69.02 seconds
Started Aug 02 05:56:00 PM PDT 24
Finished Aug 02 05:57:09 PM PDT 24
Peak memory 219648 kb
Host smart-24774ab3-8f47-44ff-905d-cdd94376b8a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329091208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1329091208
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.507261025
Short name T46
Test name
Test status
Simulation time 53016942292 ps
CPU time 3552.1 seconds
Started Aug 02 05:55:06 PM PDT 24
Finished Aug 02 06:54:19 PM PDT 24
Peak memory 236684 kb
Host smart-baf58f73-da15-4acc-9cd8-0d8b4cf07f8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507261025 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.507261025
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2801773758
Short name T86
Test name
Test status
Simulation time 1247562162 ps
CPU time 5.17 seconds
Started Aug 02 05:55:53 PM PDT 24
Finished Aug 02 05:55:58 PM PDT 24
Peak memory 211448 kb
Host smart-8f1ddfc8-43d7-4201-93d9-2dd2c9c6324c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801773758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2801773758
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3840823096
Short name T71
Test name
Test status
Simulation time 1645317660 ps
CPU time 21.02 seconds
Started Aug 02 05:54:53 PM PDT 24
Finished Aug 02 05:55:14 PM PDT 24
Peak memory 217484 kb
Host smart-df83ab70-57a1-4d87-8132-8bbfc3f83e9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840823096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3840823096
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1935769567
Short name T61
Test name
Test status
Simulation time 543155981 ps
CPU time 4.99 seconds
Started Aug 02 05:55:39 PM PDT 24
Finished Aug 02 05:55:45 PM PDT 24
Peak memory 211376 kb
Host smart-59060910-fe80-4a03-be44-a77f780dd252
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935769567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1935769567
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3835680058
Short name T54
Test name
Test status
Simulation time 654156995 ps
CPU time 5.72 seconds
Started Aug 02 05:55:40 PM PDT 24
Finished Aug 02 05:55:46 PM PDT 24
Peak memory 211380 kb
Host smart-a19f11f9-7724-409c-aa46-a549630aa5ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835680058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3835680058
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3955747072
Short name T340
Test name
Test status
Simulation time 93612823 ps
CPU time 7.17 seconds
Started Aug 02 05:55:30 PM PDT 24
Finished Aug 02 05:55:37 PM PDT 24
Peak memory 219388 kb
Host smart-4bf42f94-b46d-4c91-9fb5-49930fd445f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955747072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3955747072
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.890201379
Short name T408
Test name
Test status
Simulation time 1493591462 ps
CPU time 6.03 seconds
Started Aug 02 05:55:42 PM PDT 24
Finished Aug 02 05:55:48 PM PDT 24
Peak memory 216236 kb
Host smart-222880b8-cbae-4d58-a51d-34a002387573
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890201379 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.890201379
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1621018993
Short name T80
Test name
Test status
Simulation time 512745802 ps
CPU time 4.95 seconds
Started Aug 02 05:55:39 PM PDT 24
Finished Aug 02 05:55:44 PM PDT 24
Peak memory 218484 kb
Host smart-db200290-e0b6-4479-ad67-0f3ae94fb2f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621018993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1621018993
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.654358373
Short name T414
Test name
Test status
Simulation time 249859859 ps
CPU time 4.97 seconds
Started Aug 02 05:55:34 PM PDT 24
Finished Aug 02 05:55:39 PM PDT 24
Peak memory 211220 kb
Host smart-5b300a4c-ff53-48b1-a635-0ff5b92bbcda
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654358373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.654358373
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3094048026
Short name T335
Test name
Test status
Simulation time 291159502 ps
CPU time 5.02 seconds
Started Aug 02 05:55:31 PM PDT 24
Finished Aug 02 05:55:36 PM PDT 24
Peak memory 211232 kb
Host smart-5929ad88-7677-4d23-aa40-6c2b3f7f6cee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094048026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3094048026
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2021791741
Short name T90
Test name
Test status
Simulation time 463850529 ps
CPU time 4.36 seconds
Started Aug 02 05:55:40 PM PDT 24
Finished Aug 02 05:55:44 PM PDT 24
Peak memory 211408 kb
Host smart-4fc33568-e4e7-485e-8d1e-20c73eecc9f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021791741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2021791741
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1303783348
Short name T384
Test name
Test status
Simulation time 505876347 ps
CPU time 11.39 seconds
Started Aug 02 05:55:35 PM PDT 24
Finished Aug 02 05:55:46 PM PDT 24
Peak memory 216620 kb
Host smart-e67b0e5d-1cf4-46f6-8952-2c60f20cdc7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303783348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1303783348
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1582219617
Short name T375
Test name
Test status
Simulation time 249862461 ps
CPU time 5.02 seconds
Started Aug 02 05:55:40 PM PDT 24
Finished Aug 02 05:55:45 PM PDT 24
Peak memory 211356 kb
Host smart-41c4e82a-2dcd-421a-8cdd-9ac436d354e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582219617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1582219617
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3334617727
Short name T84
Test name
Test status
Simulation time 501078940 ps
CPU time 5.54 seconds
Started Aug 02 05:55:38 PM PDT 24
Finished Aug 02 05:55:44 PM PDT 24
Peak memory 211376 kb
Host smart-4701aa8e-d682-4e8d-bed7-089480508ba5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334617727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3334617727
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1148198818
Short name T402
Test name
Test status
Simulation time 145145995 ps
CPU time 6.74 seconds
Started Aug 02 05:55:40 PM PDT 24
Finished Aug 02 05:55:48 PM PDT 24
Peak memory 211336 kb
Host smart-907f1608-b30e-4711-9d34-a22956abf33d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148198818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1148198818
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2953418519
Short name T333
Test name
Test status
Simulation time 671880407 ps
CPU time 5.46 seconds
Started Aug 02 05:55:41 PM PDT 24
Finished Aug 02 05:55:47 PM PDT 24
Peak memory 214692 kb
Host smart-31e7019f-1d44-496b-bc2b-e5d39559d76b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953418519 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2953418519
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.957158092
Short name T355
Test name
Test status
Simulation time 249858315 ps
CPU time 5.11 seconds
Started Aug 02 05:55:40 PM PDT 24
Finished Aug 02 05:55:45 PM PDT 24
Peak memory 211296 kb
Host smart-c1f2c600-9ec5-4267-9d0f-9a3d00ca4c73
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957158092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.957158092
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2738840966
Short name T346
Test name
Test status
Simulation time 2486917177 ps
CPU time 5.03 seconds
Started Aug 02 05:55:38 PM PDT 24
Finished Aug 02 05:55:43 PM PDT 24
Peak memory 211320 kb
Host smart-cf57af07-c642-4538-8e0b-4f611b1a8b1e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738840966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2738840966
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4134269749
Short name T373
Test name
Test status
Simulation time 179408194 ps
CPU time 5.95 seconds
Started Aug 02 05:55:40 PM PDT 24
Finished Aug 02 05:55:46 PM PDT 24
Peak memory 211812 kb
Host smart-118c1e2a-34b0-43eb-8164-12d158a9b52f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134269749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.4134269749
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.322983276
Short name T360
Test name
Test status
Simulation time 515836555 ps
CPU time 7.23 seconds
Started Aug 02 05:55:37 PM PDT 24
Finished Aug 02 05:55:44 PM PDT 24
Peak memory 216440 kb
Host smart-c35eb134-248a-4dc7-91dc-8d765da3f6f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322983276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.322983276
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2402952469
Short name T105
Test name
Test status
Simulation time 359586338 ps
CPU time 71.47 seconds
Started Aug 02 05:55:38 PM PDT 24
Finished Aug 02 05:56:50 PM PDT 24
Peak memory 219580 kb
Host smart-60de6658-a7e7-49bd-ac16-6a1ee66ca5b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402952469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2402952469
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3512785068
Short name T385
Test name
Test status
Simulation time 284811015 ps
CPU time 5.96 seconds
Started Aug 02 05:55:57 PM PDT 24
Finished Aug 02 05:56:03 PM PDT 24
Peak memory 219632 kb
Host smart-6000680c-2af9-4bf7-bd10-46eafbc9a483
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512785068 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3512785068
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1570353394
Short name T392
Test name
Test status
Simulation time 518778397 ps
CPU time 5.04 seconds
Started Aug 02 05:55:52 PM PDT 24
Finished Aug 02 05:55:57 PM PDT 24
Peak memory 218052 kb
Host smart-bd165cff-3e64-4815-b10c-dd11659e24b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570353394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1570353394
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.78969829
Short name T334
Test name
Test status
Simulation time 2064497060 ps
CPU time 10.29 seconds
Started Aug 02 05:55:57 PM PDT 24
Finished Aug 02 05:56:07 PM PDT 24
Peak memory 216396 kb
Host smart-c6fe84ab-0802-43fa-9458-98a58d12d202
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78969829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.78969829
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3143481061
Short name T413
Test name
Test status
Simulation time 354519903 ps
CPU time 4.36 seconds
Started Aug 02 05:55:58 PM PDT 24
Finished Aug 02 05:56:02 PM PDT 24
Peak memory 219620 kb
Host smart-5909a3c6-0033-4333-b8e3-812a124c67de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143481061 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3143481061
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2786194089
Short name T336
Test name
Test status
Simulation time 8172689930 ps
CPU time 7.64 seconds
Started Aug 02 05:55:53 PM PDT 24
Finished Aug 02 05:56:01 PM PDT 24
Peak memory 211432 kb
Host smart-9d023e03-5b29-41a6-87e8-237550b7484a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786194089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2786194089
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2747542795
Short name T63
Test name
Test status
Simulation time 520371261 ps
CPU time 5.34 seconds
Started Aug 02 05:55:55 PM PDT 24
Finished Aug 02 05:56:00 PM PDT 24
Peak memory 218896 kb
Host smart-3e8282f7-1973-4e4d-9efb-fc814c00f097
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747542795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2747542795
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2313134396
Short name T378
Test name
Test status
Simulation time 250355935 ps
CPU time 6.9 seconds
Started Aug 02 05:55:53 PM PDT 24
Finished Aug 02 05:56:01 PM PDT 24
Peak memory 219728 kb
Host smart-977291d6-6ed4-4b89-b1de-f6ba1037401b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313134396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2313134396
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3925553453
Short name T412
Test name
Test status
Simulation time 222634610 ps
CPU time 37.62 seconds
Started Aug 02 05:55:54 PM PDT 24
Finished Aug 02 05:56:31 PM PDT 24
Peak memory 212000 kb
Host smart-376338b5-608f-4448-92e0-a5433852b3d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925553453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3925553453
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3711545165
Short name T366
Test name
Test status
Simulation time 562924088 ps
CPU time 6.48 seconds
Started Aug 02 05:56:06 PM PDT 24
Finished Aug 02 05:56:12 PM PDT 24
Peak memory 219668 kb
Host smart-1aaf740b-1acb-4412-9c6d-6f623e02c1a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711545165 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3711545165
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3822701242
Short name T377
Test name
Test status
Simulation time 462632135 ps
CPU time 5.11 seconds
Started Aug 02 05:55:57 PM PDT 24
Finished Aug 02 05:56:02 PM PDT 24
Peak memory 211352 kb
Host smart-518043b9-903c-4cde-84fe-44bbf2992c3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822701242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3822701242
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.244682704
Short name T67
Test name
Test status
Simulation time 88112588 ps
CPU time 4.32 seconds
Started Aug 02 05:55:55 PM PDT 24
Finished Aug 02 05:56:00 PM PDT 24
Peak memory 218832 kb
Host smart-b70b9042-cfb6-47ad-9be1-98f16137af64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244682704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.244682704
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3358178696
Short name T341
Test name
Test status
Simulation time 159111459 ps
CPU time 10.7 seconds
Started Aug 02 05:55:55 PM PDT 24
Finished Aug 02 05:56:06 PM PDT 24
Peak memory 217828 kb
Host smart-0d5a0138-9233-42c3-a84f-9492928752b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358178696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3358178696
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2457787730
Short name T102
Test name
Test status
Simulation time 157840197 ps
CPU time 36.69 seconds
Started Aug 02 05:55:56 PM PDT 24
Finished Aug 02 05:56:33 PM PDT 24
Peak memory 219540 kb
Host smart-b7305d6e-2f8d-4bb2-954c-41bab137acf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457787730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2457787730
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2601573539
Short name T380
Test name
Test status
Simulation time 146752630 ps
CPU time 6.72 seconds
Started Aug 02 05:56:04 PM PDT 24
Finished Aug 02 05:56:11 PM PDT 24
Peak memory 219652 kb
Host smart-595ec634-774c-48b1-ac84-16d7226d8dd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601573539 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2601573539
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.452365667
Short name T387
Test name
Test status
Simulation time 252588174 ps
CPU time 5.22 seconds
Started Aug 02 05:56:01 PM PDT 24
Finished Aug 02 05:56:06 PM PDT 24
Peak memory 218476 kb
Host smart-ac95a8ed-cf58-4c9e-a465-f393d0142479
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452365667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.452365667
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.486786787
Short name T358
Test name
Test status
Simulation time 695962689 ps
CPU time 4.41 seconds
Started Aug 02 05:56:02 PM PDT 24
Finished Aug 02 05:56:06 PM PDT 24
Peak memory 211464 kb
Host smart-846bbf97-8a43-47f1-be00-4a50d7aaa0cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486786787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.486786787
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2698027464
Short name T332
Test name
Test status
Simulation time 262924485 ps
CPU time 7.57 seconds
Started Aug 02 05:56:06 PM PDT 24
Finished Aug 02 05:56:13 PM PDT 24
Peak memory 216492 kb
Host smart-d33c4c8a-33d5-4974-9d16-6e56734f29db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698027464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2698027464
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.525520370
Short name T107
Test name
Test status
Simulation time 454449333 ps
CPU time 70.04 seconds
Started Aug 02 05:56:01 PM PDT 24
Finished Aug 02 05:57:12 PM PDT 24
Peak memory 219604 kb
Host smart-c57cb107-1216-4042-83bc-61a93b55d356
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525520370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.525520370
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1939467721
Short name T367
Test name
Test status
Simulation time 142345409 ps
CPU time 6.52 seconds
Started Aug 02 05:56:03 PM PDT 24
Finished Aug 02 05:56:10 PM PDT 24
Peak memory 219640 kb
Host smart-7c1cf864-9591-42d8-a55d-293af4c8c1c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939467721 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1939467721
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3042966549
Short name T64
Test name
Test status
Simulation time 350131614 ps
CPU time 4.32 seconds
Started Aug 02 05:56:03 PM PDT 24
Finished Aug 02 05:56:07 PM PDT 24
Peak memory 211332 kb
Host smart-9496ba5f-5f3b-4397-84cd-58cfa29b87b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042966549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3042966549
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.512820495
Short name T389
Test name
Test status
Simulation time 379083359 ps
CPU time 4.35 seconds
Started Aug 02 05:56:02 PM PDT 24
Finished Aug 02 05:56:06 PM PDT 24
Peak memory 211392 kb
Host smart-514cb3d8-dfb9-4599-9a8d-978a1ca3427e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512820495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.512820495
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.815095168
Short name T399
Test name
Test status
Simulation time 88499916 ps
CPU time 7.66 seconds
Started Aug 02 05:56:03 PM PDT 24
Finished Aug 02 05:56:11 PM PDT 24
Peak memory 216432 kb
Host smart-5945c6d9-9d51-4388-a6e3-096b6cd4b3e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815095168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.815095168
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2367447769
Short name T52
Test name
Test status
Simulation time 595416141 ps
CPU time 37.27 seconds
Started Aug 02 05:56:02 PM PDT 24
Finished Aug 02 05:56:40 PM PDT 24
Peak memory 219524 kb
Host smart-d11f9b2d-30ed-4f63-be5a-8f3621cf0f32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367447769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2367447769
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1937022820
Short name T362
Test name
Test status
Simulation time 996118817 ps
CPU time 5.7 seconds
Started Aug 02 05:56:01 PM PDT 24
Finished Aug 02 05:56:07 PM PDT 24
Peak memory 219672 kb
Host smart-c3c179f1-14f1-4cfc-a359-cb8fa48f4c1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937022820 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1937022820
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2728494620
Short name T395
Test name
Test status
Simulation time 518063873 ps
CPU time 4.94 seconds
Started Aug 02 05:56:01 PM PDT 24
Finished Aug 02 05:56:06 PM PDT 24
Peak memory 218180 kb
Host smart-6e82e7a1-50a0-4f49-8ae9-e5e8088253f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728494620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2728494620
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4214410364
Short name T88
Test name
Test status
Simulation time 557381301 ps
CPU time 4.36 seconds
Started Aug 02 05:55:59 PM PDT 24
Finished Aug 02 05:56:03 PM PDT 24
Peak memory 219472 kb
Host smart-e6b5fffd-2ce0-446a-a8ca-1debb6cdf692
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214410364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.4214410364
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1530686487
Short name T369
Test name
Test status
Simulation time 131781407 ps
CPU time 7.33 seconds
Started Aug 02 05:56:02 PM PDT 24
Finished Aug 02 05:56:10 PM PDT 24
Peak memory 219672 kb
Host smart-d450b87f-65e4-4779-9004-f201f8d4216f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530686487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1530686487
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.927308265
Short name T50
Test name
Test status
Simulation time 276692645 ps
CPU time 39.28 seconds
Started Aug 02 05:56:02 PM PDT 24
Finished Aug 02 05:56:42 PM PDT 24
Peak memory 219584 kb
Host smart-754a3b16-9165-43cb-a9b8-ae31c538cca5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927308265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.927308265
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1067773628
Short name T372
Test name
Test status
Simulation time 366510550 ps
CPU time 5.49 seconds
Started Aug 02 05:56:10 PM PDT 24
Finished Aug 02 05:56:15 PM PDT 24
Peak memory 219680 kb
Host smart-e7ddf3a1-e7a7-4fbb-a74f-59885fc1f388
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067773628 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1067773628
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1007840861
Short name T83
Test name
Test status
Simulation time 131558682 ps
CPU time 5.25 seconds
Started Aug 02 05:55:59 PM PDT 24
Finished Aug 02 05:56:05 PM PDT 24
Peak memory 211364 kb
Host smart-a4553d2c-0ac0-4a87-9997-771d976f3f27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007840861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1007840861
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2406239885
Short name T379
Test name
Test status
Simulation time 493889277 ps
CPU time 6.74 seconds
Started Aug 02 05:56:13 PM PDT 24
Finished Aug 02 05:56:20 PM PDT 24
Peak memory 211372 kb
Host smart-e294b81f-1ee9-4aeb-81c2-4ed9c7e5b29e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406239885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2406239885
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3941224996
Short name T363
Test name
Test status
Simulation time 85621643 ps
CPU time 7.06 seconds
Started Aug 02 05:56:02 PM PDT 24
Finished Aug 02 05:56:10 PM PDT 24
Peak memory 216628 kb
Host smart-eb8a5761-0db4-4faf-a3fe-3cf80ad55041
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941224996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3941224996
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2871008230
Short name T411
Test name
Test status
Simulation time 311807359 ps
CPU time 5.82 seconds
Started Aug 02 05:56:10 PM PDT 24
Finished Aug 02 05:56:15 PM PDT 24
Peak memory 216576 kb
Host smart-dd6c33f0-6fed-46f5-b0ba-3614f01430a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871008230 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2871008230
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1373475137
Short name T81
Test name
Test status
Simulation time 130999415 ps
CPU time 5.13 seconds
Started Aug 02 05:56:10 PM PDT 24
Finished Aug 02 05:56:15 PM PDT 24
Peak memory 211356 kb
Host smart-aa7be00a-7eb3-419d-8d92-de25762507a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373475137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1373475137
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1113034984
Short name T382
Test name
Test status
Simulation time 89247926 ps
CPU time 4.49 seconds
Started Aug 02 05:56:10 PM PDT 24
Finished Aug 02 05:56:15 PM PDT 24
Peak memory 219564 kb
Host smart-727decdc-7808-4fcc-a5fd-c55b8a6aa22c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113034984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1113034984
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3814691562
Short name T345
Test name
Test status
Simulation time 106437538 ps
CPU time 7.86 seconds
Started Aug 02 05:56:20 PM PDT 24
Finished Aug 02 05:56:28 PM PDT 24
Peak memory 219680 kb
Host smart-61723a9e-81c6-46aa-9afb-31cbcbe41022
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814691562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3814691562
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3528353877
Short name T394
Test name
Test status
Simulation time 311288221 ps
CPU time 6.87 seconds
Started Aug 02 05:56:08 PM PDT 24
Finished Aug 02 05:56:15 PM PDT 24
Peak memory 217004 kb
Host smart-9d1dc1aa-c248-435b-bac8-90021c1372dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528353877 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3528353877
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.347788304
Short name T338
Test name
Test status
Simulation time 86485442 ps
CPU time 4.19 seconds
Started Aug 02 05:56:16 PM PDT 24
Finished Aug 02 05:56:20 PM PDT 24
Peak memory 218336 kb
Host smart-0f16e8e7-a4e9-4e92-a23c-7e60def667c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347788304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.347788304
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4070852539
Short name T406
Test name
Test status
Simulation time 543280316 ps
CPU time 28.14 seconds
Started Aug 02 05:56:14 PM PDT 24
Finished Aug 02 05:56:42 PM PDT 24
Peak memory 211456 kb
Host smart-04ee258d-97d2-4bac-bb7e-07ef393480c2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070852539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.4070852539
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1498452048
Short name T55
Test name
Test status
Simulation time 594535768 ps
CPU time 4.97 seconds
Started Aug 02 05:56:18 PM PDT 24
Finished Aug 02 05:56:23 PM PDT 24
Peak memory 218564 kb
Host smart-3543d7a2-6390-4716-961b-71688a0cfc67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498452048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1498452048
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1195021005
Short name T388
Test name
Test status
Simulation time 540396055 ps
CPU time 8.07 seconds
Started Aug 02 05:56:09 PM PDT 24
Finished Aug 02 05:56:17 PM PDT 24
Peak memory 219712 kb
Host smart-d181783a-4393-4b44-8006-c8350baadc09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195021005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1195021005
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1447888284
Short name T376
Test name
Test status
Simulation time 799130822 ps
CPU time 36.58 seconds
Started Aug 02 05:56:13 PM PDT 24
Finished Aug 02 05:56:49 PM PDT 24
Peak memory 212804 kb
Host smart-1cd8475a-f877-4293-89ec-523c04ab278d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447888284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1447888284
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.267780939
Short name T343
Test name
Test status
Simulation time 374363385 ps
CPU time 5.33 seconds
Started Aug 02 05:56:10 PM PDT 24
Finished Aug 02 05:56:15 PM PDT 24
Peak memory 219648 kb
Host smart-2aa3415f-f1c7-41f7-83a6-30dbe2866360
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267780939 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.267780939
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3129372879
Short name T68
Test name
Test status
Simulation time 348148037 ps
CPU time 4.21 seconds
Started Aug 02 05:56:08 PM PDT 24
Finished Aug 02 05:56:13 PM PDT 24
Peak memory 219460 kb
Host smart-27cfeccd-b44e-491b-9adb-e1621acb93d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129372879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3129372879
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1946524098
Short name T381
Test name
Test status
Simulation time 134548695 ps
CPU time 5.23 seconds
Started Aug 02 05:56:07 PM PDT 24
Finished Aug 02 05:56:13 PM PDT 24
Peak memory 211408 kb
Host smart-764db9ce-72d8-4d43-b0e3-f192c902b4e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946524098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1946524098
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.799940902
Short name T398
Test name
Test status
Simulation time 503005594 ps
CPU time 7.43 seconds
Started Aug 02 05:56:13 PM PDT 24
Finished Aug 02 05:56:21 PM PDT 24
Peak memory 216628 kb
Host smart-0391ed3b-2744-4622-b9c4-cbcb90ed6fce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799940902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.799940902
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.10124539
Short name T108
Test name
Test status
Simulation time 6842499251 ps
CPU time 38.48 seconds
Started Aug 02 05:56:09 PM PDT 24
Finished Aug 02 05:56:48 PM PDT 24
Peak memory 213228 kb
Host smart-2ef6a064-40b8-4ea6-a274-be3b68da5aeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10124539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_int
g_err.10124539
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3347571302
Short name T93
Test name
Test status
Simulation time 88202940 ps
CPU time 4.35 seconds
Started Aug 02 05:55:43 PM PDT 24
Finished Aug 02 05:55:48 PM PDT 24
Peak memory 211360 kb
Host smart-feb79dea-0d76-4d46-b2ed-50fbd5e7b5d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347571302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3347571302
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2692676870
Short name T356
Test name
Test status
Simulation time 336417652 ps
CPU time 4.36 seconds
Started Aug 02 05:55:36 PM PDT 24
Finished Aug 02 05:55:41 PM PDT 24
Peak memory 219468 kb
Host smart-01aa9d53-3dda-42e9-976a-4042520d11d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692676870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2692676870
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1283224720
Short name T407
Test name
Test status
Simulation time 345201169 ps
CPU time 7.37 seconds
Started Aug 02 05:55:39 PM PDT 24
Finished Aug 02 05:55:47 PM PDT 24
Peak memory 219440 kb
Host smart-d6e5eb46-7627-471f-92ee-db8e7983e056
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283224720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1283224720
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1226484683
Short name T354
Test name
Test status
Simulation time 1491179686 ps
CPU time 5.83 seconds
Started Aug 02 05:55:37 PM PDT 24
Finished Aug 02 05:55:43 PM PDT 24
Peak memory 215648 kb
Host smart-a1e0ad50-e288-46f0-b9a7-343f083e1c80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226484683 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1226484683
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.469309773
Short name T348
Test name
Test status
Simulation time 91009255 ps
CPU time 4.34 seconds
Started Aug 02 05:55:41 PM PDT 24
Finished Aug 02 05:55:46 PM PDT 24
Peak memory 211364 kb
Host smart-ea27b8d3-d0e2-46fd-b89f-21014a45e041
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469309773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.469309773
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1670426020
Short name T391
Test name
Test status
Simulation time 521232298 ps
CPU time 4.87 seconds
Started Aug 02 05:55:38 PM PDT 24
Finished Aug 02 05:55:43 PM PDT 24
Peak memory 211292 kb
Host smart-abeca04d-fafc-403e-914a-51d4d9ca4650
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670426020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1670426020
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3363249915
Short name T347
Test name
Test status
Simulation time 85653832 ps
CPU time 4.19 seconds
Started Aug 02 05:55:40 PM PDT 24
Finished Aug 02 05:55:44 PM PDT 24
Peak memory 211284 kb
Host smart-63558282-ab5a-4f1c-bc04-b0080c8e9502
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363249915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3363249915
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2574338934
Short name T65
Test name
Test status
Simulation time 1033247726 ps
CPU time 9.08 seconds
Started Aug 02 05:55:38 PM PDT 24
Finished Aug 02 05:55:47 PM PDT 24
Peak memory 211740 kb
Host smart-bd4df569-192b-4b8d-a32a-bee224cbe1f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574338934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2574338934
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4048519985
Short name T331
Test name
Test status
Simulation time 88079740 ps
CPU time 6.6 seconds
Started Aug 02 05:55:40 PM PDT 24
Finished Aug 02 05:55:47 PM PDT 24
Peak memory 216520 kb
Host smart-9816d5f9-8488-4314-8f3b-3537841cd6b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048519985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.4048519985
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2341930739
Short name T104
Test name
Test status
Simulation time 703858634 ps
CPU time 40.23 seconds
Started Aug 02 05:55:40 PM PDT 24
Finished Aug 02 05:56:20 PM PDT 24
Peak memory 211864 kb
Host smart-745c1ee9-100b-458f-b24d-39743c828940
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341930739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2341930739
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1462374395
Short name T365
Test name
Test status
Simulation time 132197511 ps
CPU time 5.07 seconds
Started Aug 02 05:55:50 PM PDT 24
Finished Aug 02 05:55:55 PM PDT 24
Peak memory 211376 kb
Host smart-463f7831-8cec-4435-aa16-b0e4b06c2f4c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462374395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1462374395
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2860372647
Short name T396
Test name
Test status
Simulation time 87633247 ps
CPU time 4.53 seconds
Started Aug 02 05:55:47 PM PDT 24
Finished Aug 02 05:55:52 PM PDT 24
Peak memory 219376 kb
Host smart-26c916d3-0c94-486e-87eb-f00ee8dff46e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860372647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2860372647
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2479510237
Short name T79
Test name
Test status
Simulation time 130116743 ps
CPU time 8.17 seconds
Started Aug 02 05:55:44 PM PDT 24
Finished Aug 02 05:55:52 PM PDT 24
Peak memory 218360 kb
Host smart-861146c0-a4fb-40f5-a89c-075389339fc0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479510237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2479510237
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3198354440
Short name T344
Test name
Test status
Simulation time 383263579 ps
CPU time 4.74 seconds
Started Aug 02 05:55:45 PM PDT 24
Finished Aug 02 05:55:50 PM PDT 24
Peak memory 219660 kb
Host smart-ad9e0bf9-7206-40c7-bb56-aa4b21fe22f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198354440 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3198354440
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3833408347
Short name T349
Test name
Test status
Simulation time 444160499 ps
CPU time 4.16 seconds
Started Aug 02 05:55:47 PM PDT 24
Finished Aug 02 05:55:51 PM PDT 24
Peak memory 219424 kb
Host smart-d6acad8e-d8cd-42ae-9649-5fd6ea983a18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833408347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3833408347
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.466450823
Short name T357
Test name
Test status
Simulation time 502521436 ps
CPU time 5.18 seconds
Started Aug 02 05:55:50 PM PDT 24
Finished Aug 02 05:55:55 PM PDT 24
Peak memory 211260 kb
Host smart-5c38b92a-8d29-41bd-a464-66e157ace232
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466450823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.466450823
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.570078380
Short name T386
Test name
Test status
Simulation time 346235694 ps
CPU time 4.15 seconds
Started Aug 02 05:55:50 PM PDT 24
Finished Aug 02 05:55:54 PM PDT 24
Peak memory 211248 kb
Host smart-a4651d9e-c7aa-45e8-b01a-7562620b42b2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570078380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
570078380
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3746908522
Short name T66
Test name
Test status
Simulation time 10509565423 ps
CPU time 22.48 seconds
Started Aug 02 05:55:45 PM PDT 24
Finished Aug 02 05:56:08 PM PDT 24
Peak memory 211412 kb
Host smart-2ab83662-3f00-461f-bc44-2be6538fc683
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746908522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3746908522
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2062066663
Short name T87
Test name
Test status
Simulation time 98140208 ps
CPU time 6.21 seconds
Started Aug 02 05:55:48 PM PDT 24
Finished Aug 02 05:55:54 PM PDT 24
Peak memory 211500 kb
Host smart-cbc46429-16e1-4a32-a65e-51695054a2f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062066663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2062066663
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.526859495
Short name T97
Test name
Test status
Simulation time 146011128 ps
CPU time 10.71 seconds
Started Aug 02 05:55:46 PM PDT 24
Finished Aug 02 05:55:57 PM PDT 24
Peak memory 215752 kb
Host smart-5bad7b04-bbcc-4a78-9862-31a5f22898bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526859495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.526859495
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1930408596
Short name T101
Test name
Test status
Simulation time 492485168 ps
CPU time 68.69 seconds
Started Aug 02 05:55:47 PM PDT 24
Finished Aug 02 05:56:56 PM PDT 24
Peak memory 213296 kb
Host smart-5088b670-7d90-44a4-b738-0f5bbc84c53f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930408596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1930408596
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1545678391
Short name T78
Test name
Test status
Simulation time 88740239 ps
CPU time 4.25 seconds
Started Aug 02 05:55:47 PM PDT 24
Finished Aug 02 05:55:52 PM PDT 24
Peak memory 219456 kb
Host smart-3548cd48-a643-4196-8d5a-278b97d95fbe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545678391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1545678391
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2176638968
Short name T350
Test name
Test status
Simulation time 1193481170 ps
CPU time 4.34 seconds
Started Aug 02 05:55:47 PM PDT 24
Finished Aug 02 05:55:51 PM PDT 24
Peak memory 211352 kb
Host smart-b66e9435-d610-4c7d-ab31-c2151f0f683b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176638968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2176638968
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3561273966
Short name T403
Test name
Test status
Simulation time 171726432 ps
CPU time 5.81 seconds
Started Aug 02 05:55:48 PM PDT 24
Finished Aug 02 05:55:54 PM PDT 24
Peak memory 219224 kb
Host smart-fa3ccf66-abe9-4d91-b8bd-deae3ef814dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561273966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3561273966
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3546633536
Short name T415
Test name
Test status
Simulation time 2184668726 ps
CPU time 8.24 seconds
Started Aug 02 05:55:46 PM PDT 24
Finished Aug 02 05:55:55 PM PDT 24
Peak memory 219728 kb
Host smart-55008800-8f45-4e13-bc14-6c9a9ffa6023
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546633536 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3546633536
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1870288504
Short name T92
Test name
Test status
Simulation time 175317723 ps
CPU time 4.32 seconds
Started Aug 02 05:55:54 PM PDT 24
Finished Aug 02 05:55:58 PM PDT 24
Peak memory 211412 kb
Host smart-bcfff15c-700b-494e-9c3b-2920dc22ffa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870288504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1870288504
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3771070602
Short name T339
Test name
Test status
Simulation time 334963544 ps
CPU time 4.23 seconds
Started Aug 02 05:55:50 PM PDT 24
Finished Aug 02 05:55:54 PM PDT 24
Peak memory 211220 kb
Host smart-5065931c-2fc6-47e1-bd0f-8c322f3ce521
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771070602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3771070602
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.592402337
Short name T374
Test name
Test status
Simulation time 502986840 ps
CPU time 4.97 seconds
Started Aug 02 05:55:48 PM PDT 24
Finished Aug 02 05:55:53 PM PDT 24
Peak memory 211248 kb
Host smart-7104cb4c-7550-4a02-8eb3-554e9b50e86d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592402337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
592402337
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1496915814
Short name T85
Test name
Test status
Simulation time 91632204 ps
CPU time 4.3 seconds
Started Aug 02 05:55:45 PM PDT 24
Finished Aug 02 05:55:50 PM PDT 24
Peak memory 211432 kb
Host smart-73bd0983-b98a-46a1-847c-e1946a93ae97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496915814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1496915814
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1554048628
Short name T368
Test name
Test status
Simulation time 93338791 ps
CPU time 7.39 seconds
Started Aug 02 05:55:50 PM PDT 24
Finished Aug 02 05:55:57 PM PDT 24
Peak memory 215516 kb
Host smart-84b6700b-2639-4166-991b-5ef8039553f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554048628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1554048628
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1306987538
Short name T103
Test name
Test status
Simulation time 631943705 ps
CPU time 36.05 seconds
Started Aug 02 05:55:46 PM PDT 24
Finished Aug 02 05:56:22 PM PDT 24
Peak memory 219528 kb
Host smart-c537bf48-8403-417a-a3e8-c7e463e34f69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306987538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1306987538
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3321737580
Short name T352
Test name
Test status
Simulation time 533005292 ps
CPU time 8.36 seconds
Started Aug 02 05:55:45 PM PDT 24
Finished Aug 02 05:55:54 PM PDT 24
Peak memory 215720 kb
Host smart-257384c9-9813-449d-8f62-cd44bdac4995
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321737580 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3321737580
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2782640925
Short name T89
Test name
Test status
Simulation time 88906605 ps
CPU time 4.16 seconds
Started Aug 02 05:55:49 PM PDT 24
Finished Aug 02 05:55:53 PM PDT 24
Peak memory 219496 kb
Host smart-6289acc9-8207-48f4-9b9a-d652db022be8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782640925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2782640925
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3806122477
Short name T371
Test name
Test status
Simulation time 1388683487 ps
CPU time 5.19 seconds
Started Aug 02 05:55:48 PM PDT 24
Finished Aug 02 05:55:54 PM PDT 24
Peak memory 219516 kb
Host smart-abebf263-b25b-4284-8aea-2c0f9b32ceb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806122477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3806122477
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.750707073
Short name T370
Test name
Test status
Simulation time 653119330 ps
CPU time 7.47 seconds
Started Aug 02 05:55:47 PM PDT 24
Finished Aug 02 05:55:54 PM PDT 24
Peak memory 216528 kb
Host smart-be39c94a-58d4-447d-9f4f-63b7df45dc19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750707073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.750707073
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1676322782
Short name T111
Test name
Test status
Simulation time 488645553 ps
CPU time 70.12 seconds
Started Aug 02 05:55:51 PM PDT 24
Finished Aug 02 05:57:01 PM PDT 24
Peak memory 213160 kb
Host smart-d561eb65-36f2-47ac-a3fc-7cf9d8a51ba2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676322782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1676322782
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3454973711
Short name T353
Test name
Test status
Simulation time 100434687 ps
CPU time 5.29 seconds
Started Aug 02 05:55:54 PM PDT 24
Finished Aug 02 05:55:59 PM PDT 24
Peak memory 216904 kb
Host smart-4605b18a-a349-416d-bcc7-8337d9311d0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454973711 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3454973711
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4046800361
Short name T400
Test name
Test status
Simulation time 93947407 ps
CPU time 4.22 seconds
Started Aug 02 05:55:50 PM PDT 24
Finished Aug 02 05:55:54 PM PDT 24
Peak memory 211336 kb
Host smart-1ed71db9-82fe-488e-b729-ca6d0a8f1e64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046800361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.4046800361
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3226808980
Short name T401
Test name
Test status
Simulation time 222422944 ps
CPU time 4.48 seconds
Started Aug 02 05:55:46 PM PDT 24
Finished Aug 02 05:55:50 PM PDT 24
Peak memory 211448 kb
Host smart-31af1d86-13ff-489b-90f7-2f47affd5872
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226808980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3226808980
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.634349957
Short name T359
Test name
Test status
Simulation time 126954584 ps
CPU time 7.46 seconds
Started Aug 02 05:55:49 PM PDT 24
Finished Aug 02 05:55:56 PM PDT 24
Peak memory 219652 kb
Host smart-51d4ff42-abc0-4ba1-8603-912ae3a17228
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634349957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.634349957
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3636498048
Short name T397
Test name
Test status
Simulation time 273958473 ps
CPU time 69.14 seconds
Started Aug 02 05:55:45 PM PDT 24
Finished Aug 02 05:56:54 PM PDT 24
Peak memory 219580 kb
Host smart-e07647d8-6a4d-4c8f-a861-260e38e358ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636498048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3636498048
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2685525906
Short name T361
Test name
Test status
Simulation time 178268143 ps
CPU time 5.01 seconds
Started Aug 02 05:55:56 PM PDT 24
Finished Aug 02 05:56:01 PM PDT 24
Peak memory 216124 kb
Host smart-881e6d13-3e1e-40ba-ad08-7c161c958719
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685525906 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2685525906
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1358436177
Short name T82
Test name
Test status
Simulation time 175084779 ps
CPU time 4.23 seconds
Started Aug 02 05:55:57 PM PDT 24
Finished Aug 02 05:56:01 PM PDT 24
Peak memory 211352 kb
Host smart-b59a990f-1334-4354-aa00-3ae61cb56590
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358436177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1358436177
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3849299648
Short name T342
Test name
Test status
Simulation time 1401316033 ps
CPU time 18.98 seconds
Started Aug 02 05:55:55 PM PDT 24
Finished Aug 02 05:56:14 PM PDT 24
Peak memory 211432 kb
Host smart-10523922-ead7-4c46-991d-7ff0e6c49adc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849299648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3849299648
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1232768438
Short name T404
Test name
Test status
Simulation time 520152018 ps
CPU time 7.22 seconds
Started Aug 02 05:55:58 PM PDT 24
Finished Aug 02 05:56:05 PM PDT 24
Peak memory 211428 kb
Host smart-2f83317e-433c-4cf3-8046-8ecd649d26dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232768438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1232768438
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1742657159
Short name T351
Test name
Test status
Simulation time 88212546 ps
CPU time 6.24 seconds
Started Aug 02 05:55:52 PM PDT 24
Finished Aug 02 05:55:59 PM PDT 24
Peak memory 219732 kb
Host smart-cdabb7d9-c53d-47be-bc02-2b38560587b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742657159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1742657159
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1918053224
Short name T100
Test name
Test status
Simulation time 442146627 ps
CPU time 67.79 seconds
Started Aug 02 05:55:53 PM PDT 24
Finished Aug 02 05:57:01 PM PDT 24
Peak memory 212896 kb
Host smart-64d2e3d4-9968-4151-b594-cf7e9746e3fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918053224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1918053224
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3124711344
Short name T409
Test name
Test status
Simulation time 281881455 ps
CPU time 5.9 seconds
Started Aug 02 05:55:53 PM PDT 24
Finished Aug 02 05:55:59 PM PDT 24
Peak memory 215400 kb
Host smart-a698ac3a-a3d8-416e-a91c-2363c4c52f1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124711344 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3124711344
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1209569584
Short name T91
Test name
Test status
Simulation time 498754820 ps
CPU time 5.15 seconds
Started Aug 02 05:55:57 PM PDT 24
Finished Aug 02 05:56:02 PM PDT 24
Peak memory 218652 kb
Host smart-1e34f581-5a5e-4d22-90d5-b0ae1396438b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209569584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1209569584
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1652579670
Short name T60
Test name
Test status
Simulation time 252149704 ps
CPU time 5.07 seconds
Started Aug 02 05:55:51 PM PDT 24
Finished Aug 02 05:55:57 PM PDT 24
Peak memory 211404 kb
Host smart-ddfcbfee-61fe-438e-b147-8eb0ba35c40a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652579670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1652579670
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.73213729
Short name T393
Test name
Test status
Simulation time 696024573 ps
CPU time 6.36 seconds
Started Aug 02 05:55:52 PM PDT 24
Finished Aug 02 05:55:58 PM PDT 24
Peak memory 216048 kb
Host smart-eab0a92e-a26e-4bd3-ba58-00063917b43b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73213729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.73213729
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.103544138
Short name T383
Test name
Test status
Simulation time 749109119 ps
CPU time 37.34 seconds
Started Aug 02 05:55:56 PM PDT 24
Finished Aug 02 05:56:33 PM PDT 24
Peak memory 211712 kb
Host smart-fe88e70f-8686-4d31-ad44-a79a7fc31d52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103544138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.103544138
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2660927357
Short name T364
Test name
Test status
Simulation time 266137997 ps
CPU time 4.38 seconds
Started Aug 02 05:55:55 PM PDT 24
Finished Aug 02 05:55:59 PM PDT 24
Peak memory 213312 kb
Host smart-16b17df6-e30d-4cc8-b52d-673a5d26b801
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660927357 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2660927357
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2261182533
Short name T390
Test name
Test status
Simulation time 169612331 ps
CPU time 4.27 seconds
Started Aug 02 05:55:52 PM PDT 24
Finished Aug 02 05:55:57 PM PDT 24
Peak memory 211368 kb
Host smart-c229ec12-ff88-4a1d-89a6-98ea8885c5dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261182533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2261182533
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.391512680
Short name T410
Test name
Test status
Simulation time 1386919818 ps
CPU time 5.07 seconds
Started Aug 02 05:55:51 PM PDT 24
Finished Aug 02 05:55:57 PM PDT 24
Peak memory 211444 kb
Host smart-e9155717-914a-4261-92cd-c80259398733
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391512680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.391512680
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1607064421
Short name T337
Test name
Test status
Simulation time 127914157 ps
CPU time 8.58 seconds
Started Aug 02 05:55:58 PM PDT 24
Finished Aug 02 05:56:06 PM PDT 24
Peak memory 215580 kb
Host smart-e3ed27be-36db-491b-a8b9-db14bf5b03d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607064421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1607064421
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4083272768
Short name T109
Test name
Test status
Simulation time 153264953 ps
CPU time 36.89 seconds
Started Aug 02 05:55:54 PM PDT 24
Finished Aug 02 05:56:31 PM PDT 24
Peak memory 219560 kb
Host smart-968ac432-81d7-4906-a845-5ebe76fdb436
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083272768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.4083272768
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.4005250429
Short name T207
Test name
Test status
Simulation time 261187670 ps
CPU time 5.35 seconds
Started Aug 02 05:54:33 PM PDT 24
Finished Aug 02 05:54:38 PM PDT 24
Peak memory 212068 kb
Host smart-1a13083f-1eba-4a76-a0a3-44f78ccdff9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005250429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.4005250429
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3244133091
Short name T244
Test name
Test status
Simulation time 7140819209 ps
CPU time 117.29 seconds
Started Aug 02 05:54:39 PM PDT 24
Finished Aug 02 05:56:36 PM PDT 24
Peak memory 240524 kb
Host smart-bf35393e-297e-429e-8b40-ace04b0d7ec8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244133091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3244133091
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2870581287
Short name T202
Test name
Test status
Simulation time 1650840391 ps
CPU time 11.59 seconds
Started Aug 02 05:54:36 PM PDT 24
Finished Aug 02 05:54:48 PM PDT 24
Peak memory 212988 kb
Host smart-60910bbe-27ac-43c1-80fd-f23f6394bf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870581287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2870581287
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2271926854
Short name T313
Test name
Test status
Simulation time 537992166 ps
CPU time 6.84 seconds
Started Aug 02 05:54:37 PM PDT 24
Finished Aug 02 05:54:44 PM PDT 24
Peak memory 212272 kb
Host smart-ac17be04-02ad-4704-9a04-5a732109f4f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2271926854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2271926854
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.852081056
Short name T22
Test name
Test status
Simulation time 280150756 ps
CPU time 101.26 seconds
Started Aug 02 05:54:34 PM PDT 24
Finished Aug 02 05:56:15 PM PDT 24
Peak memory 237448 kb
Host smart-a991d834-dd06-4fdc-ac81-1b14bcf95865
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852081056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.852081056
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.257701503
Short name T273
Test name
Test status
Simulation time 192595127 ps
CPU time 5.66 seconds
Started Aug 02 05:54:36 PM PDT 24
Finished Aug 02 05:54:41 PM PDT 24
Peak memory 212216 kb
Host smart-180327a0-db9c-487a-8425-51e7734f01a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257701503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.257701503
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2428373947
Short name T220
Test name
Test status
Simulation time 2180415270 ps
CPU time 12.07 seconds
Started Aug 02 05:54:33 PM PDT 24
Finished Aug 02 05:54:46 PM PDT 24
Peak memory 213512 kb
Host smart-e1985f32-13f0-4973-a32e-03ac330957ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428373947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2428373947
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2765611510
Short name T123
Test name
Test status
Simulation time 171374141 ps
CPU time 4.3 seconds
Started Aug 02 05:54:38 PM PDT 24
Finished Aug 02 05:54:43 PM PDT 24
Peak memory 211976 kb
Host smart-a67b5843-ab83-47c8-9be9-9e39348a26ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765611510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2765611510
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3304408740
Short name T317
Test name
Test status
Simulation time 5490107047 ps
CPU time 191.53 seconds
Started Aug 02 05:54:34 PM PDT 24
Finished Aug 02 05:57:46 PM PDT 24
Peak memory 238540 kb
Host smart-96a8648e-c433-4b9e-9d0a-339b71b8ebc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304408740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3304408740
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2408791936
Short name T158
Test name
Test status
Simulation time 262034482 ps
CPU time 11.56 seconds
Started Aug 02 05:54:37 PM PDT 24
Finished Aug 02 05:54:49 PM PDT 24
Peak memory 213000 kb
Host smart-97d82760-cd8f-4db9-8131-62683f166819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408791936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2408791936
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.291330949
Short name T145
Test name
Test status
Simulation time 277323458 ps
CPU time 6.48 seconds
Started Aug 02 05:54:38 PM PDT 24
Finished Aug 02 05:54:45 PM PDT 24
Peak memory 212172 kb
Host smart-b3edc49b-f0c8-495a-95f8-576b4d840874
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=291330949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.291330949
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.785719237
Short name T21
Test name
Test status
Simulation time 1776643697 ps
CPU time 99.53 seconds
Started Aug 02 05:54:41 PM PDT 24
Finished Aug 02 05:56:21 PM PDT 24
Peak memory 237356 kb
Host smart-9a913d87-45fc-4171-86f4-7a6a1005aeb8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785719237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.785719237
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3445780441
Short name T270
Test name
Test status
Simulation time 1848098994 ps
CPU time 6.09 seconds
Started Aug 02 05:54:41 PM PDT 24
Finished Aug 02 05:54:48 PM PDT 24
Peak memory 212468 kb
Host smart-7b03a3ff-ddd1-41c4-a0a4-3bb5be446c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445780441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3445780441
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.143887801
Short name T166
Test name
Test status
Simulation time 146258074 ps
CPU time 9.59 seconds
Started Aug 02 05:54:35 PM PDT 24
Finished Aug 02 05:54:45 PM PDT 24
Peak memory 212120 kb
Host smart-1101bc7c-4968-4559-9110-486ee2392a32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143887801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.143887801
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2974822235
Short name T117
Test name
Test status
Simulation time 159472328 ps
CPU time 5.49 seconds
Started Aug 02 05:54:53 PM PDT 24
Finished Aug 02 05:54:58 PM PDT 24
Peak memory 212112 kb
Host smart-87212ba1-1e7d-4a80-87e8-f041d1f142bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974822235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2974822235
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.409649235
Short name T150
Test name
Test status
Simulation time 6263104956 ps
CPU time 148.85 seconds
Started Aug 02 05:54:53 PM PDT 24
Finished Aug 02 05:57:22 PM PDT 24
Peak memory 238448 kb
Host smart-6c1ff3a4-1e88-4724-92fb-d9842dfb5745
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409649235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.409649235
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.390422944
Short name T247
Test name
Test status
Simulation time 95847715 ps
CPU time 5.61 seconds
Started Aug 02 05:54:52 PM PDT 24
Finished Aug 02 05:54:58 PM PDT 24
Peak memory 212180 kb
Host smart-1418a18e-2d76-41ff-ad1f-ca2f0c9bc7be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=390422944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.390422944
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1920347177
Short name T164
Test name
Test status
Simulation time 588632751 ps
CPU time 19.88 seconds
Started Aug 02 05:54:50 PM PDT 24
Finished Aug 02 05:55:10 PM PDT 24
Peak memory 216344 kb
Host smart-0fac5b71-bcd7-4993-8f2a-22ce9c42c0ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920347177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1920347177
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2205486569
Short name T56
Test name
Test status
Simulation time 499675121 ps
CPU time 5.15 seconds
Started Aug 02 05:54:53 PM PDT 24
Finished Aug 02 05:54:58 PM PDT 24
Peak memory 212080 kb
Host smart-55cf88fb-3e53-4349-88c4-3708c8930e03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205486569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2205486569
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1907143597
Short name T149
Test name
Test status
Simulation time 3977873887 ps
CPU time 136.95 seconds
Started Aug 02 05:54:48 PM PDT 24
Finished Aug 02 05:57:05 PM PDT 24
Peak memory 235528 kb
Host smart-abe13d4d-f257-484d-9f26-47f6de023e32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907143597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1907143597
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2969101377
Short name T195
Test name
Test status
Simulation time 994625997 ps
CPU time 11.53 seconds
Started Aug 02 05:54:51 PM PDT 24
Finished Aug 02 05:55:03 PM PDT 24
Peak memory 212972 kb
Host smart-abbafb5c-fd65-4896-8cb1-a48931bed782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969101377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2969101377
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.369736080
Short name T155
Test name
Test status
Simulation time 419528720 ps
CPU time 5.62 seconds
Started Aug 02 05:54:51 PM PDT 24
Finished Aug 02 05:54:56 PM PDT 24
Peak memory 212108 kb
Host smart-15397bec-01ac-4ba7-af9d-e30a1d49591f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=369736080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.369736080
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2312519711
Short name T314
Test name
Test status
Simulation time 132849133538 ps
CPU time 5625.2 seconds
Started Aug 02 05:54:53 PM PDT 24
Finished Aug 02 07:28:39 PM PDT 24
Peak memory 266536 kb
Host smart-5e96dc52-436e-4981-b51f-cff9a92f4b68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312519711 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2312519711
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.4234822081
Short name T133
Test name
Test status
Simulation time 1130364111 ps
CPU time 5.03 seconds
Started Aug 02 05:54:53 PM PDT 24
Finished Aug 02 05:54:58 PM PDT 24
Peak memory 212064 kb
Host smart-cc17d8f4-da58-4af9-864f-10ec4489c1e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234822081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4234822081
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1558671317
Short name T236
Test name
Test status
Simulation time 256426574 ps
CPU time 11.18 seconds
Started Aug 02 05:54:51 PM PDT 24
Finished Aug 02 05:55:02 PM PDT 24
Peak memory 213060 kb
Host smart-75ce66ac-6e2d-4381-a52b-84fd7c4ed557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558671317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1558671317
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.946420541
Short name T292
Test name
Test status
Simulation time 94162678 ps
CPU time 5.41 seconds
Started Aug 02 05:54:52 PM PDT 24
Finished Aug 02 05:54:57 PM PDT 24
Peak memory 212172 kb
Host smart-9b032290-9bb5-4f99-8b86-841e328041bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=946420541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.946420541
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2024350209
Short name T243
Test name
Test status
Simulation time 290459478 ps
CPU time 15.56 seconds
Started Aug 02 05:54:50 PM PDT 24
Finished Aug 02 05:55:06 PM PDT 24
Peak memory 216300 kb
Host smart-2f894719-651e-4e05-8d59-d6d9b3f8816a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024350209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2024350209
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1209024065
Short name T242
Test name
Test status
Simulation time 30881561618 ps
CPU time 1366.48 seconds
Started Aug 02 05:54:52 PM PDT 24
Finished Aug 02 06:17:39 PM PDT 24
Peak memory 236672 kb
Host smart-d5d8b58c-1aa8-4190-b624-90826eefc453
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209024065 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.1209024065
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.829747763
Short name T224
Test name
Test status
Simulation time 2048467208 ps
CPU time 7.93 seconds
Started Aug 02 05:54:53 PM PDT 24
Finished Aug 02 05:55:01 PM PDT 24
Peak memory 212092 kb
Host smart-2e8a3193-17c7-45ce-9d62-2595adb8c842
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829747763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.829747763
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.631458023
Short name T323
Test name
Test status
Simulation time 2161405996 ps
CPU time 114.61 seconds
Started Aug 02 05:54:53 PM PDT 24
Finished Aug 02 05:56:48 PM PDT 24
Peak memory 228956 kb
Host smart-14e652f7-ec77-474e-bae4-b325092ef906
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631458023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.631458023
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1051770534
Short name T326
Test name
Test status
Simulation time 280157747 ps
CPU time 6.57 seconds
Started Aug 02 05:54:52 PM PDT 24
Finished Aug 02 05:54:59 PM PDT 24
Peak memory 212176 kb
Host smart-793c5a19-6572-46dc-8df2-9764865d6ccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051770534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1051770534
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.554101871
Short name T252
Test name
Test status
Simulation time 550905397 ps
CPU time 11.89 seconds
Started Aug 02 05:54:50 PM PDT 24
Finished Aug 02 05:55:02 PM PDT 24
Peak memory 212136 kb
Host smart-f6ff8fef-6d21-42b6-86a5-c25f44b683b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554101871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.554101871
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3985891561
Short name T18
Test name
Test status
Simulation time 380967330166 ps
CPU time 2024.7 seconds
Started Aug 02 05:54:50 PM PDT 24
Finished Aug 02 06:28:35 PM PDT 24
Peak memory 248868 kb
Host smart-d48b6097-7e31-4eb3-af35-b02be14d62bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985891561 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3985891561
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.269167403
Short name T294
Test name
Test status
Simulation time 262283195 ps
CPU time 5.13 seconds
Started Aug 02 05:54:59 PM PDT 24
Finished Aug 02 05:55:04 PM PDT 24
Peak memory 212132 kb
Host smart-4f772a93-7043-4ac7-9623-7b922b1b6ea8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269167403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.269167403
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3573201231
Short name T39
Test name
Test status
Simulation time 4161651770 ps
CPU time 217.75 seconds
Started Aug 02 05:54:54 PM PDT 24
Finished Aug 02 05:58:32 PM PDT 24
Peak memory 238476 kb
Host smart-a101fd5d-cb2b-4129-90ef-02c8a5de421b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573201231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3573201231
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1517658826
Short name T302
Test name
Test status
Simulation time 506486758 ps
CPU time 11.2 seconds
Started Aug 02 05:54:48 PM PDT 24
Finished Aug 02 05:54:59 PM PDT 24
Peak memory 212884 kb
Host smart-c6a44049-c66f-443e-91f8-0c4e9f14f3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517658826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1517658826
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1229299088
Short name T170
Test name
Test status
Simulation time 147483628 ps
CPU time 6.06 seconds
Started Aug 02 05:54:51 PM PDT 24
Finished Aug 02 05:54:57 PM PDT 24
Peak memory 212188 kb
Host smart-438de51d-f369-4321-9efa-afe3bb5b8291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1229299088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1229299088
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1688405999
Short name T328
Test name
Test status
Simulation time 305469828 ps
CPU time 8.63 seconds
Started Aug 02 05:54:51 PM PDT 24
Finished Aug 02 05:55:00 PM PDT 24
Peak memory 212124 kb
Host smart-9b352ace-4f2e-4ffd-9483-725f33ff3a7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688405999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1688405999
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3506211221
Short name T172
Test name
Test status
Simulation time 19799771309 ps
CPU time 889.14 seconds
Started Aug 02 05:54:50 PM PDT 24
Finished Aug 02 06:09:39 PM PDT 24
Peak memory 236688 kb
Host smart-2f716fc7-3bd5-4c3c-9abd-665f8a712b01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506211221 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3506211221
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3235056535
Short name T130
Test name
Test status
Simulation time 90903388 ps
CPU time 4.47 seconds
Started Aug 02 05:54:56 PM PDT 24
Finished Aug 02 05:55:01 PM PDT 24
Peak memory 212096 kb
Host smart-a82518df-3d43-463a-b5ed-acda8517e7be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235056535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3235056535
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3359847987
Short name T38
Test name
Test status
Simulation time 9395806147 ps
CPU time 118.03 seconds
Started Aug 02 05:55:03 PM PDT 24
Finished Aug 02 05:57:01 PM PDT 24
Peak memory 238132 kb
Host smart-dff8d781-37f5-4aa1-99f5-1175239cc55f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359847987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3359847987
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4009210196
Short name T25
Test name
Test status
Simulation time 341826415 ps
CPU time 9.7 seconds
Started Aug 02 05:55:02 PM PDT 24
Finished Aug 02 05:55:11 PM PDT 24
Peak memory 212820 kb
Host smart-fd9dd8f9-a3f3-4a12-a96a-0eacd8bdfc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009210196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4009210196
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1314773822
Short name T203
Test name
Test status
Simulation time 271927325 ps
CPU time 6.62 seconds
Started Aug 02 05:55:04 PM PDT 24
Finished Aug 02 05:55:10 PM PDT 24
Peak memory 212148 kb
Host smart-7dfb6260-a2cb-4097-a842-286a0d591982
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1314773822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1314773822
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2148890150
Short name T235
Test name
Test status
Simulation time 264866229 ps
CPU time 7.75 seconds
Started Aug 02 05:54:58 PM PDT 24
Finished Aug 02 05:55:06 PM PDT 24
Peak memory 212164 kb
Host smart-c1a8da51-98cc-4782-bec6-d1f49301c652
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148890150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2148890150
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.809911377
Short name T232
Test name
Test status
Simulation time 269790414863 ps
CPU time 2895.62 seconds
Started Aug 02 05:54:56 PM PDT 24
Finished Aug 02 06:43:12 PM PDT 24
Peak memory 253112 kb
Host smart-27341c73-28a6-445d-8068-651934907947
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809911377 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.809911377
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.60334395
Short name T225
Test name
Test status
Simulation time 2070721838 ps
CPU time 106.65 seconds
Started Aug 02 05:55:05 PM PDT 24
Finished Aug 02 05:56:52 PM PDT 24
Peak memory 214388 kb
Host smart-adef2780-8f35-45b2-ba81-ac371af3e443
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60334395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_co
rrupt_sig_fatal_chk.60334395
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3746751237
Short name T209
Test name
Test status
Simulation time 990468855 ps
CPU time 11.52 seconds
Started Aug 02 05:55:01 PM PDT 24
Finished Aug 02 05:55:13 PM PDT 24
Peak memory 212948 kb
Host smart-2360612b-d681-4b34-b77e-d5d65bd9a905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746751237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3746751237
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.600893139
Short name T112
Test name
Test status
Simulation time 524009315 ps
CPU time 8.48 seconds
Started Aug 02 05:54:59 PM PDT 24
Finished Aug 02 05:55:08 PM PDT 24
Peak memory 212148 kb
Host smart-6fdb5aaa-de43-4de1-b7fd-5b4d357d93ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=600893139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.600893139
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3945689107
Short name T241
Test name
Test status
Simulation time 571303050 ps
CPU time 6.53 seconds
Started Aug 02 05:54:59 PM PDT 24
Finished Aug 02 05:55:06 PM PDT 24
Peak memory 212132 kb
Host smart-35df0d33-c3ca-40dc-b904-e094a937798c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945689107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3945689107
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1951894399
Short name T300
Test name
Test status
Simulation time 347040945 ps
CPU time 4.35 seconds
Started Aug 02 05:54:56 PM PDT 24
Finished Aug 02 05:55:00 PM PDT 24
Peak memory 212100 kb
Host smart-9f7ba221-979b-4bf0-80b2-3d9377d4638e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951894399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1951894399
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2047982344
Short name T153
Test name
Test status
Simulation time 31090761721 ps
CPU time 154.44 seconds
Started Aug 02 05:55:00 PM PDT 24
Finished Aug 02 05:57:35 PM PDT 24
Peak memory 228972 kb
Host smart-2d84d9b9-3b89-4ebf-b516-5ca35e4a2215
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047982344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2047982344
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2865069891
Short name T259
Test name
Test status
Simulation time 175984950 ps
CPU time 9.66 seconds
Started Aug 02 05:55:00 PM PDT 24
Finished Aug 02 05:55:10 PM PDT 24
Peak memory 213028 kb
Host smart-0bf56c81-7d21-4e18-851f-484a1c07101e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865069891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2865069891
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3326439740
Short name T128
Test name
Test status
Simulation time 562223579 ps
CPU time 6.78 seconds
Started Aug 02 05:55:00 PM PDT 24
Finished Aug 02 05:55:07 PM PDT 24
Peak memory 212180 kb
Host smart-f50a02c7-0c86-4446-b31c-a24e595d2320
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3326439740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3326439740
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1880369433
Short name T261
Test name
Test status
Simulation time 1263032271 ps
CPU time 14.69 seconds
Started Aug 02 05:54:55 PM PDT 24
Finished Aug 02 05:55:10 PM PDT 24
Peak memory 217468 kb
Host smart-a305eb2c-895e-44a5-948e-2daa853548da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880369433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1880369433
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2212253134
Short name T98
Test name
Test status
Simulation time 461130088656 ps
CPU time 4990.91 seconds
Started Aug 02 05:55:05 PM PDT 24
Finished Aug 02 07:18:16 PM PDT 24
Peak memory 261284 kb
Host smart-c68a3b4c-db8c-4a68-8465-b5baa31eec0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212253134 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2212253134
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3207222903
Short name T318
Test name
Test status
Simulation time 173076124 ps
CPU time 4.25 seconds
Started Aug 02 05:54:57 PM PDT 24
Finished Aug 02 05:55:01 PM PDT 24
Peak memory 212060 kb
Host smart-160435b4-d1b8-4fe1-a370-2a607dfa1da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207222903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3207222903
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3301591965
Short name T204
Test name
Test status
Simulation time 3428540900 ps
CPU time 87.02 seconds
Started Aug 02 05:55:04 PM PDT 24
Finished Aug 02 05:56:31 PM PDT 24
Peak memory 225732 kb
Host smart-d26dd1f0-c5bd-4884-a73b-0e1f30f4d786
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301591965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3301591965
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1448755560
Short name T264
Test name
Test status
Simulation time 334770915 ps
CPU time 9.93 seconds
Started Aug 02 05:54:56 PM PDT 24
Finished Aug 02 05:55:06 PM PDT 24
Peak memory 213432 kb
Host smart-e4bfd7dd-aa2a-4521-9f74-4897b84dd7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448755560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1448755560
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2967599731
Short name T189
Test name
Test status
Simulation time 905567531 ps
CPU time 5.4 seconds
Started Aug 02 05:55:01 PM PDT 24
Finished Aug 02 05:55:07 PM PDT 24
Peak memory 212176 kb
Host smart-68039ac0-ee13-45c7-be09-0a54469d5864
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2967599731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2967599731
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3753885320
Short name T174
Test name
Test status
Simulation time 2102190552 ps
CPU time 19.39 seconds
Started Aug 02 05:55:04 PM PDT 24
Finished Aug 02 05:55:23 PM PDT 24
Peak memory 214492 kb
Host smart-d5d115d3-7d63-4212-b918-d8b77e2dcbfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753885320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3753885320
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3659128210
Short name T140
Test name
Test status
Simulation time 19820656281 ps
CPU time 843.46 seconds
Started Aug 02 05:55:03 PM PDT 24
Finished Aug 02 06:09:07 PM PDT 24
Peak memory 234064 kb
Host smart-03c63cbf-aeb5-4f1c-b5d6-1b40569dcd55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659128210 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3659128210
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2799801941
Short name T266
Test name
Test status
Simulation time 347506412 ps
CPU time 4.35 seconds
Started Aug 02 05:55:03 PM PDT 24
Finished Aug 02 05:55:08 PM PDT 24
Peak memory 212052 kb
Host smart-2cb47ada-2218-4f06-bb4a-47c08a88db15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799801941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2799801941
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3374036048
Short name T41
Test name
Test status
Simulation time 2995215727 ps
CPU time 135.87 seconds
Started Aug 02 05:55:04 PM PDT 24
Finished Aug 02 05:57:20 PM PDT 24
Peak memory 213436 kb
Host smart-45bfdb3a-6173-437b-9558-7b2b71a0f378
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374036048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3374036048
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2639480823
Short name T33
Test name
Test status
Simulation time 511561895 ps
CPU time 11.27 seconds
Started Aug 02 05:54:58 PM PDT 24
Finished Aug 02 05:55:09 PM PDT 24
Peak memory 212852 kb
Host smart-545bd2cb-ce31-4d98-b05b-7c592c0dd8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639480823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2639480823
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.576999964
Short name T219
Test name
Test status
Simulation time 553733367 ps
CPU time 6.33 seconds
Started Aug 02 05:55:02 PM PDT 24
Finished Aug 02 05:55:08 PM PDT 24
Peak memory 212184 kb
Host smart-4531b76b-818d-4e59-a949-794aaf37db20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=576999964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.576999964
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3720223349
Short name T184
Test name
Test status
Simulation time 827342834 ps
CPU time 19.12 seconds
Started Aug 02 05:55:00 PM PDT 24
Finished Aug 02 05:55:19 PM PDT 24
Peak memory 213892 kb
Host smart-abcb0f21-a757-4356-b225-2146ffe9791e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720223349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3720223349
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3143134255
Short name T193
Test name
Test status
Simulation time 497203931 ps
CPU time 5.2 seconds
Started Aug 02 05:54:43 PM PDT 24
Finished Aug 02 05:54:49 PM PDT 24
Peak memory 212040 kb
Host smart-6c7a1bd5-f1a2-4b09-91db-25f357a231ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143134255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3143134255
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2248524809
Short name T222
Test name
Test status
Simulation time 14287826532 ps
CPU time 157.47 seconds
Started Aug 02 05:54:35 PM PDT 24
Finished Aug 02 05:57:13 PM PDT 24
Peak memory 234612 kb
Host smart-ec79343a-1b88-4a31-9baf-3c83196e9fb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248524809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2248524809
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2651280303
Short name T299
Test name
Test status
Simulation time 168579587 ps
CPU time 9.58 seconds
Started Aug 02 05:54:33 PM PDT 24
Finished Aug 02 05:54:43 PM PDT 24
Peak memory 212924 kb
Host smart-8c4dab91-e499-4c1d-9d30-7d6dfa2c5212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651280303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2651280303
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1274236337
Short name T188
Test name
Test status
Simulation time 655376279 ps
CPU time 6.26 seconds
Started Aug 02 05:54:37 PM PDT 24
Finished Aug 02 05:54:43 PM PDT 24
Peak memory 212152 kb
Host smart-809b86fb-1f33-4be0-a48a-8b7c192daa2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1274236337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1274236337
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1469194839
Short name T279
Test name
Test status
Simulation time 635078799 ps
CPU time 6.16 seconds
Started Aug 02 05:54:41 PM PDT 24
Finished Aug 02 05:54:47 PM PDT 24
Peak memory 212176 kb
Host smart-5fc6ff04-2674-4a15-823c-72afdb881178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469194839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1469194839
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1777460951
Short name T212
Test name
Test status
Simulation time 122664430 ps
CPU time 7.58 seconds
Started Aug 02 05:54:31 PM PDT 24
Finished Aug 02 05:54:39 PM PDT 24
Peak memory 212092 kb
Host smart-484289f4-b10c-4822-8d86-225f911f12ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777460951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1777460951
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2897111994
Short name T12
Test name
Test status
Simulation time 130290568684 ps
CPU time 991.15 seconds
Started Aug 02 05:54:41 PM PDT 24
Finished Aug 02 06:11:12 PM PDT 24
Peak memory 232996 kb
Host smart-bc1c3e08-f7c7-410e-89af-ea30eacb40ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897111994 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.2897111994
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1009675017
Short name T230
Test name
Test status
Simulation time 155616678 ps
CPU time 4.2 seconds
Started Aug 02 05:55:02 PM PDT 24
Finished Aug 02 05:55:06 PM PDT 24
Peak memory 212080 kb
Host smart-a1c68bd5-c18e-4038-8799-2cd1221215da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009675017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1009675017
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1670266500
Short name T305
Test name
Test status
Simulation time 6070953315 ps
CPU time 92.35 seconds
Started Aug 02 05:55:03 PM PDT 24
Finished Aug 02 05:56:36 PM PDT 24
Peak memory 240524 kb
Host smart-5fdc718c-9d9f-419d-ade0-6baa3073b260
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670266500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1670266500
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3194433857
Short name T255
Test name
Test status
Simulation time 340844675 ps
CPU time 9.37 seconds
Started Aug 02 05:55:02 PM PDT 24
Finished Aug 02 05:55:11 PM PDT 24
Peak memory 212940 kb
Host smart-9e9bdaa1-9e67-4496-bdc5-9c0de9980e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194433857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3194433857
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.4100245472
Short name T257
Test name
Test status
Simulation time 139935347 ps
CPU time 6.72 seconds
Started Aug 02 05:55:04 PM PDT 24
Finished Aug 02 05:55:11 PM PDT 24
Peak memory 212148 kb
Host smart-e67c36e2-1ca6-4511-8a45-9f7bdbd8b9be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4100245472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.4100245472
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.579422492
Short name T187
Test name
Test status
Simulation time 198576115 ps
CPU time 12.07 seconds
Started Aug 02 05:54:57 PM PDT 24
Finished Aug 02 05:55:09 PM PDT 24
Peak memory 213452 kb
Host smart-29e22c85-114d-4598-823b-d01fed33e4ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579422492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.579422492
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2391798028
Short name T48
Test name
Test status
Simulation time 139080261330 ps
CPU time 931.83 seconds
Started Aug 02 05:55:02 PM PDT 24
Finished Aug 02 06:10:34 PM PDT 24
Peak memory 236664 kb
Host smart-596402ff-3253-47df-b72c-cc330089fd61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391798028 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2391798028
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2441478314
Short name T127
Test name
Test status
Simulation time 156730782 ps
CPU time 4.36 seconds
Started Aug 02 05:55:01 PM PDT 24
Finished Aug 02 05:55:06 PM PDT 24
Peak memory 212052 kb
Host smart-dd4120fe-865a-495c-a79e-7d96d215a326
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441478314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2441478314
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2301578904
Short name T221
Test name
Test status
Simulation time 1513778173 ps
CPU time 84.36 seconds
Started Aug 02 05:54:57 PM PDT 24
Finished Aug 02 05:56:21 PM PDT 24
Peak memory 225560 kb
Host smart-dfb93e58-1805-4182-bae5-3184cd1e28e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301578904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2301578904
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2888870747
Short name T141
Test name
Test status
Simulation time 1914258132 ps
CPU time 11.5 seconds
Started Aug 02 05:55:00 PM PDT 24
Finished Aug 02 05:55:12 PM PDT 24
Peak memory 212964 kb
Host smart-cdc0da4e-7b34-41af-9d98-b5b653aeee4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888870747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2888870747
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.813377758
Short name T263
Test name
Test status
Simulation time 139225922 ps
CPU time 6.21 seconds
Started Aug 02 05:54:59 PM PDT 24
Finished Aug 02 05:55:06 PM PDT 24
Peak memory 212168 kb
Host smart-ed5b4789-368f-4017-bb9c-bee8c5ec3c1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=813377758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.813377758
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.694695456
Short name T319
Test name
Test status
Simulation time 177471087 ps
CPU time 7.7 seconds
Started Aug 02 05:55:04 PM PDT 24
Finished Aug 02 05:55:12 PM PDT 24
Peak memory 212140 kb
Host smart-f456d916-9580-4779-b3cb-ee366cbc71e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694695456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.694695456
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1268499711
Short name T44
Test name
Test status
Simulation time 499379791 ps
CPU time 5.09 seconds
Started Aug 02 05:55:04 PM PDT 24
Finished Aug 02 05:55:09 PM PDT 24
Peak memory 212052 kb
Host smart-5d5ad3bf-8fb6-4b4d-96cd-975a56975fe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268499711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1268499711
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1136269262
Short name T271
Test name
Test status
Simulation time 6924625573 ps
CPU time 99.61 seconds
Started Aug 02 05:55:06 PM PDT 24
Finished Aug 02 05:56:46 PM PDT 24
Peak memory 239368 kb
Host smart-8a49edd2-f06d-428e-918e-79886f20e20e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136269262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1136269262
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.74982140
Short name T186
Test name
Test status
Simulation time 1860430611 ps
CPU time 9.72 seconds
Started Aug 02 05:55:09 PM PDT 24
Finished Aug 02 05:55:19 PM PDT 24
Peak memory 212956 kb
Host smart-e411cbf9-55a2-4628-861b-ac0dbd56ce43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74982140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.74982140
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.4145518289
Short name T228
Test name
Test status
Simulation time 191724621 ps
CPU time 5.54 seconds
Started Aug 02 05:55:08 PM PDT 24
Finished Aug 02 05:55:14 PM PDT 24
Peak memory 212108 kb
Host smart-ff1173e8-ba85-4202-a4a5-317c72f9880d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4145518289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.4145518289
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.713053392
Short name T69
Test name
Test status
Simulation time 131693445 ps
CPU time 8.59 seconds
Started Aug 02 05:55:07 PM PDT 24
Finished Aug 02 05:55:15 PM PDT 24
Peak memory 212104 kb
Host smart-4300eea3-acb1-49a9-8956-f9cfb53cd49a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713053392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.713053392
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.447878253
Short name T146
Test name
Test status
Simulation time 89322130 ps
CPU time 4.35 seconds
Started Aug 02 05:55:04 PM PDT 24
Finished Aug 02 05:55:08 PM PDT 24
Peak memory 212104 kb
Host smart-825ad9b4-4087-4bc5-a8d2-28feaefc6f5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447878253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.447878253
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1992378941
Short name T196
Test name
Test status
Simulation time 2479522580 ps
CPU time 120.51 seconds
Started Aug 02 05:55:05 PM PDT 24
Finished Aug 02 05:57:05 PM PDT 24
Peak memory 235600 kb
Host smart-54a97dfb-79f6-436d-a0a2-bab6b82f0bb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992378941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1992378941
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3824091803
Short name T138
Test name
Test status
Simulation time 190533428 ps
CPU time 9.71 seconds
Started Aug 02 05:55:07 PM PDT 24
Finished Aug 02 05:55:17 PM PDT 24
Peak memory 212860 kb
Host smart-8114f26a-8765-4c10-9f9f-cd53f8024643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824091803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3824091803
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2000512207
Short name T144
Test name
Test status
Simulation time 608148159 ps
CPU time 6.32 seconds
Started Aug 02 05:55:06 PM PDT 24
Finished Aug 02 05:55:13 PM PDT 24
Peak memory 212176 kb
Host smart-0736c389-b8ca-4c0e-a490-a155b3ff905e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2000512207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2000512207
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.308800174
Short name T200
Test name
Test status
Simulation time 283716179 ps
CPU time 13.47 seconds
Started Aug 02 05:55:10 PM PDT 24
Finished Aug 02 05:55:24 PM PDT 24
Peak memory 213820 kb
Host smart-64bd24ec-a9a2-4954-8b5e-84b04e1513a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308800174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.308800174
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1865113456
Short name T238
Test name
Test status
Simulation time 75210446563 ps
CPU time 2927.03 seconds
Started Aug 02 05:55:08 PM PDT 24
Finished Aug 02 06:43:56 PM PDT 24
Peak memory 250920 kb
Host smart-f3b2dff9-a2b4-4b3a-8983-874ac4d81f0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865113456 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1865113456
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3624888958
Short name T28
Test name
Test status
Simulation time 437422123 ps
CPU time 4.36 seconds
Started Aug 02 05:55:06 PM PDT 24
Finished Aug 02 05:55:10 PM PDT 24
Peak memory 212108 kb
Host smart-d0725820-93ba-4eab-a01b-2a9350adf149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624888958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3624888958
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1141810735
Short name T276
Test name
Test status
Simulation time 23384170178 ps
CPU time 146.83 seconds
Started Aug 02 05:55:06 PM PDT 24
Finished Aug 02 05:57:33 PM PDT 24
Peak memory 235584 kb
Host smart-53f87fa3-605f-4d8e-bbea-6a699468fbca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141810735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1141810735
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3376753567
Short name T159
Test name
Test status
Simulation time 342991315 ps
CPU time 9.43 seconds
Started Aug 02 05:55:06 PM PDT 24
Finished Aug 02 05:55:15 PM PDT 24
Peak memory 213132 kb
Host smart-230dcac3-bf9d-4ca8-ab59-364daafcc2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376753567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3376753567
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3937440694
Short name T126
Test name
Test status
Simulation time 96356125 ps
CPU time 5.76 seconds
Started Aug 02 05:55:10 PM PDT 24
Finished Aug 02 05:55:15 PM PDT 24
Peak memory 212200 kb
Host smart-7d9584a8-7bc4-41e5-8d61-e1c54cba5f97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3937440694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3937440694
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1415924942
Short name T124
Test name
Test status
Simulation time 482994060 ps
CPU time 7.77 seconds
Started Aug 02 05:55:10 PM PDT 24
Finished Aug 02 05:55:18 PM PDT 24
Peak memory 212244 kb
Host smart-fc8aef3e-4293-4ebb-bf5d-47ed9552383a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415924942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1415924942
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3674334322
Short name T278
Test name
Test status
Simulation time 245678176 ps
CPU time 5.23 seconds
Started Aug 02 05:55:07 PM PDT 24
Finished Aug 02 05:55:12 PM PDT 24
Peak memory 212080 kb
Host smart-852bbc7c-715e-41c9-9b06-87f92796f0bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674334322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3674334322
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1328866177
Short name T239
Test name
Test status
Simulation time 6703710201 ps
CPU time 116.03 seconds
Started Aug 02 05:55:05 PM PDT 24
Finished Aug 02 05:57:01 PM PDT 24
Peak memory 239312 kb
Host smart-c6a94df5-e677-450f-abd8-95896d0cd95a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328866177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1328866177
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.429305143
Short name T256
Test name
Test status
Simulation time 263016356 ps
CPU time 11.34 seconds
Started Aug 02 05:55:07 PM PDT 24
Finished Aug 02 05:55:18 PM PDT 24
Peak memory 212832 kb
Host smart-25e44354-8335-49e9-83ef-3b2dfa0e0403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429305143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.429305143
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1509898137
Short name T231
Test name
Test status
Simulation time 140668893 ps
CPU time 9.29 seconds
Started Aug 02 05:55:07 PM PDT 24
Finished Aug 02 05:55:16 PM PDT 24
Peak memory 212132 kb
Host smart-d78ac535-8141-4004-8ccf-dc7abf929f81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509898137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1509898137
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.264085715
Short name T281
Test name
Test status
Simulation time 23625182888 ps
CPU time 1020.45 seconds
Started Aug 02 05:55:10 PM PDT 24
Finished Aug 02 06:12:10 PM PDT 24
Peak memory 226136 kb
Host smart-96d5e751-6bdc-420c-a7bc-79db4ab901b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264085715 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.264085715
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1226704580
Short name T32
Test name
Test status
Simulation time 491603155 ps
CPU time 4.34 seconds
Started Aug 02 05:55:05 PM PDT 24
Finished Aug 02 05:55:10 PM PDT 24
Peak memory 212088 kb
Host smart-bf38de58-0cbf-4d1a-af27-74c1ceba05b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226704580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1226704580
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2101274194
Short name T37
Test name
Test status
Simulation time 1355688513 ps
CPU time 78.29 seconds
Started Aug 02 05:55:05 PM PDT 24
Finished Aug 02 05:56:23 PM PDT 24
Peak memory 234296 kb
Host smart-20a0b31c-19f8-401f-8a0c-b96aea69a506
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101274194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2101274194
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.821201708
Short name T182
Test name
Test status
Simulation time 499660783 ps
CPU time 11 seconds
Started Aug 02 05:55:06 PM PDT 24
Finished Aug 02 05:55:17 PM PDT 24
Peak memory 213004 kb
Host smart-c1f3442a-9f5c-447f-9d70-66897e2fd480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821201708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.821201708
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3798495426
Short name T59
Test name
Test status
Simulation time 97259802 ps
CPU time 5.48 seconds
Started Aug 02 05:55:08 PM PDT 24
Finished Aug 02 05:55:13 PM PDT 24
Peak memory 212228 kb
Host smart-36a7847f-bde7-4775-8d47-817a61bdd57a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3798495426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3798495426
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1650759282
Short name T14
Test name
Test status
Simulation time 586428393 ps
CPU time 15.83 seconds
Started Aug 02 05:55:07 PM PDT 24
Finished Aug 02 05:55:23 PM PDT 24
Peak memory 215256 kb
Host smart-add2eae0-661e-4c80-9a79-92a503e6bc06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650759282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1650759282
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3679187158
Short name T129
Test name
Test status
Simulation time 127590146 ps
CPU time 5.27 seconds
Started Aug 02 05:55:08 PM PDT 24
Finished Aug 02 05:55:13 PM PDT 24
Peak memory 212028 kb
Host smart-e7db9e7d-bffa-4668-8331-be05d32b2b3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679187158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3679187158
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.356249912
Short name T173
Test name
Test status
Simulation time 1946768577 ps
CPU time 99.15 seconds
Started Aug 02 05:55:07 PM PDT 24
Finished Aug 02 05:56:46 PM PDT 24
Peak memory 238368 kb
Host smart-bb36ebb1-8c17-4034-8418-e821c6da075c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356249912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.356249912
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1428130848
Short name T265
Test name
Test status
Simulation time 177535086 ps
CPU time 9.78 seconds
Started Aug 02 05:55:06 PM PDT 24
Finished Aug 02 05:55:16 PM PDT 24
Peak memory 212900 kb
Host smart-1e641f97-c629-4aab-b91b-c6fbdc990b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428130848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1428130848
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.119009565
Short name T297
Test name
Test status
Simulation time 197313065 ps
CPU time 5.71 seconds
Started Aug 02 05:55:08 PM PDT 24
Finished Aug 02 05:55:14 PM PDT 24
Peak memory 212228 kb
Host smart-a7131920-5f33-4270-b35d-4350f776108e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=119009565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.119009565
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2930498622
Short name T213
Test name
Test status
Simulation time 210573674 ps
CPU time 13.45 seconds
Started Aug 02 05:55:07 PM PDT 24
Finished Aug 02 05:55:21 PM PDT 24
Peak memory 215044 kb
Host smart-b91daa44-3c89-4aa6-9630-b8961d0d4cf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930498622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2930498622
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.294396001
Short name T293
Test name
Test status
Simulation time 361777159 ps
CPU time 4.32 seconds
Started Aug 02 05:55:07 PM PDT 24
Finished Aug 02 05:55:12 PM PDT 24
Peak memory 212108 kb
Host smart-3c578475-43dd-4c0c-bea9-0cdfd6075402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294396001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.294396001
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.431359261
Short name T19
Test name
Test status
Simulation time 1851625854 ps
CPU time 70.78 seconds
Started Aug 02 05:55:07 PM PDT 24
Finished Aug 02 05:56:18 PM PDT 24
Peak memory 233264 kb
Host smart-503a35a2-a95c-4b76-b6c1-42dafb1c1bd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431359261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.431359261
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.4144797579
Short name T316
Test name
Test status
Simulation time 2262871867 ps
CPU time 11.2 seconds
Started Aug 02 05:55:07 PM PDT 24
Finished Aug 02 05:55:18 PM PDT 24
Peak memory 213752 kb
Host smart-e6ad7eee-a95b-4e6e-b4c8-3b2eb445744d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144797579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.4144797579
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3449131
Short name T132
Test name
Test status
Simulation time 287186099 ps
CPU time 6.81 seconds
Started Aug 02 05:55:08 PM PDT 24
Finished Aug 02 05:55:15 PM PDT 24
Peak memory 212232 kb
Host smart-68f95473-0a7e-4a03-8af5-0cb7017f7052
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3449131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3449131
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.568334193
Short name T77
Test name
Test status
Simulation time 1081694370 ps
CPU time 14.97 seconds
Started Aug 02 05:55:05 PM PDT 24
Finished Aug 02 05:55:20 PM PDT 24
Peak memory 213472 kb
Host smart-64d03ef3-f6e9-4c3a-921a-c8e93655a489
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568334193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.568334193
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3295343225
Short name T275
Test name
Test status
Simulation time 126029194 ps
CPU time 5.26 seconds
Started Aug 02 05:55:09 PM PDT 24
Finished Aug 02 05:55:15 PM PDT 24
Peak memory 212080 kb
Host smart-d7a5daa3-3e11-47c8-8ea3-4e34e36d2017
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295343225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3295343225
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1687212075
Short name T245
Test name
Test status
Simulation time 900166633 ps
CPU time 64.47 seconds
Started Aug 02 05:55:06 PM PDT 24
Finished Aug 02 05:56:10 PM PDT 24
Peak memory 238424 kb
Host smart-3987b284-30e7-469a-8c10-98f7bd45249d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687212075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1687212075
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2821885237
Short name T125
Test name
Test status
Simulation time 520468890 ps
CPU time 11.36 seconds
Started Aug 02 05:55:04 PM PDT 24
Finished Aug 02 05:55:16 PM PDT 24
Peak memory 212972 kb
Host smart-4a8be321-c0cf-431f-9309-4e5144d8b33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821885237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2821885237
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3961864945
Short name T282
Test name
Test status
Simulation time 390192589 ps
CPU time 5.81 seconds
Started Aug 02 05:55:04 PM PDT 24
Finished Aug 02 05:55:10 PM PDT 24
Peak memory 212136 kb
Host smart-c5b46810-8fff-426f-81e0-025bd1973a58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3961864945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3961864945
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2141062713
Short name T73
Test name
Test status
Simulation time 205123685 ps
CPU time 10.91 seconds
Started Aug 02 05:55:09 PM PDT 24
Finished Aug 02 05:55:20 PM PDT 24
Peak memory 214648 kb
Host smart-a0a31994-fdb0-4be3-b6da-872cbdd1154a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141062713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2141062713
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3076582872
Short name T251
Test name
Test status
Simulation time 42677290216 ps
CPU time 8356.47 seconds
Started Aug 02 05:55:05 PM PDT 24
Finished Aug 02 08:14:23 PM PDT 24
Peak memory 229132 kb
Host smart-863049e0-8adc-46cf-86a8-c43736358c73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076582872 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3076582872
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.4130515047
Short name T183
Test name
Test status
Simulation time 271796971 ps
CPU time 4.52 seconds
Started Aug 02 05:54:45 PM PDT 24
Finished Aug 02 05:54:49 PM PDT 24
Peak memory 212040 kb
Host smart-79937e6f-138d-46f7-bbc8-5e7d65ce57c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130515047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.4130515047
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.33837246
Short name T285
Test name
Test status
Simulation time 2882447903 ps
CPU time 89.38 seconds
Started Aug 02 05:54:41 PM PDT 24
Finished Aug 02 05:56:10 PM PDT 24
Peak memory 213460 kb
Host smart-d27a555d-48a0-4d18-b938-57ed2574f1bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33837246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_cor
rupt_sig_fatal_chk.33837246
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3314868971
Short name T324
Test name
Test status
Simulation time 330465923 ps
CPU time 9.39 seconds
Started Aug 02 05:54:44 PM PDT 24
Finished Aug 02 05:54:54 PM PDT 24
Peak memory 212904 kb
Host smart-65972f85-dae1-4c74-a3db-62111769a848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314868971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3314868971
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2741057258
Short name T169
Test name
Test status
Simulation time 385847407 ps
CPU time 5.46 seconds
Started Aug 02 05:54:42 PM PDT 24
Finished Aug 02 05:54:48 PM PDT 24
Peak memory 212192 kb
Host smart-74a0287a-48e3-4b48-b108-191bc6c8487f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2741057258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2741057258
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3871282868
Short name T27
Test name
Test status
Simulation time 278962580 ps
CPU time 55.13 seconds
Started Aug 02 05:54:45 PM PDT 24
Finished Aug 02 05:55:40 PM PDT 24
Peak memory 236416 kb
Host smart-f5ce2525-d190-43fc-8274-575d77508c1b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871282868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3871282868
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2140357706
Short name T74
Test name
Test status
Simulation time 697564707 ps
CPU time 6.58 seconds
Started Aug 02 05:54:42 PM PDT 24
Finished Aug 02 05:54:49 PM PDT 24
Peak memory 212232 kb
Host smart-e07c8e2e-36a3-4e1b-bfeb-ec96d6ed0354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140357706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2140357706
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3205391770
Short name T6
Test name
Test status
Simulation time 107544369 ps
CPU time 8.86 seconds
Started Aug 02 05:54:42 PM PDT 24
Finished Aug 02 05:54:51 PM PDT 24
Peak memory 212104 kb
Host smart-0774640a-10c4-41a5-b7bc-282f0dc45714
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205391770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3205391770
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3819572164
Short name T47
Test name
Test status
Simulation time 14970472195 ps
CPU time 1617.59 seconds
Started Aug 02 05:54:45 PM PDT 24
Finished Aug 02 06:21:43 PM PDT 24
Peak memory 228488 kb
Host smart-dc27dd1b-0ddd-4b26-a41e-37397c8daf51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819572164 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.3819572164
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2197592941
Short name T24
Test name
Test status
Simulation time 91261237 ps
CPU time 4.4 seconds
Started Aug 02 05:55:09 PM PDT 24
Finished Aug 02 05:55:14 PM PDT 24
Peak memory 212080 kb
Host smart-8790f657-1bc4-42db-a0c9-6e2e15aa7464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197592941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2197592941
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1244185120
Short name T310
Test name
Test status
Simulation time 3401448265 ps
CPU time 101.51 seconds
Started Aug 02 05:55:08 PM PDT 24
Finished Aug 02 05:56:49 PM PDT 24
Peak memory 238796 kb
Host smart-7127d6ac-7d18-4075-82e1-b44e204d9285
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244185120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1244185120
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2823277041
Short name T135
Test name
Test status
Simulation time 257024186 ps
CPU time 11.19 seconds
Started Aug 02 05:55:07 PM PDT 24
Finished Aug 02 05:55:18 PM PDT 24
Peak memory 212884 kb
Host smart-266e04f5-f1d7-49bf-8e81-f4c893227faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823277041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2823277041
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2765984744
Short name T7
Test name
Test status
Simulation time 191643789 ps
CPU time 5.54 seconds
Started Aug 02 05:55:08 PM PDT 24
Finished Aug 02 05:55:13 PM PDT 24
Peak memory 212184 kb
Host smart-332b0024-010b-4c29-b15e-b867141751bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2765984744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2765984744
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1766223886
Short name T269
Test name
Test status
Simulation time 140278069 ps
CPU time 9.4 seconds
Started Aug 02 05:55:08 PM PDT 24
Finished Aug 02 05:55:18 PM PDT 24
Peak memory 212156 kb
Host smart-5fae8ca8-6e09-47cb-a314-872e985a8287
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766223886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1766223886
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2449105648
Short name T177
Test name
Test status
Simulation time 519491376 ps
CPU time 5.06 seconds
Started Aug 02 05:55:10 PM PDT 24
Finished Aug 02 05:55:16 PM PDT 24
Peak memory 212080 kb
Host smart-57d8cd52-6df1-4ff4-b963-a12742b14543
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449105648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2449105648
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1662527633
Short name T167
Test name
Test status
Simulation time 2789764682 ps
CPU time 138.32 seconds
Started Aug 02 05:55:09 PM PDT 24
Finished Aug 02 05:57:27 PM PDT 24
Peak memory 238384 kb
Host smart-fff29abb-4f1a-4b54-a726-8c0a30d66fe7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662527633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1662527633
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.4103386234
Short name T122
Test name
Test status
Simulation time 176725903 ps
CPU time 9.42 seconds
Started Aug 02 05:55:10 PM PDT 24
Finished Aug 02 05:55:19 PM PDT 24
Peak memory 212872 kb
Host smart-fa8f8674-4472-4277-af41-06da280a2075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103386234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.4103386234
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4208297172
Short name T116
Test name
Test status
Simulation time 100345175 ps
CPU time 5.48 seconds
Started Aug 02 05:55:07 PM PDT 24
Finished Aug 02 05:55:12 PM PDT 24
Peak memory 212192 kb
Host smart-11deb2c4-28ab-4724-84d0-202ab285d89e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4208297172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4208297172
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2149385010
Short name T240
Test name
Test status
Simulation time 145958624 ps
CPU time 7.62 seconds
Started Aug 02 05:55:08 PM PDT 24
Finished Aug 02 05:55:16 PM PDT 24
Peak memory 212148 kb
Host smart-f867b73e-1f4c-432c-9f88-716a529308db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149385010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2149385010
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.410216571
Short name T9
Test name
Test status
Simulation time 500525161 ps
CPU time 5.25 seconds
Started Aug 02 05:55:16 PM PDT 24
Finished Aug 02 05:55:22 PM PDT 24
Peak memory 211980 kb
Host smart-4a5673a5-6087-4e20-979b-0117b62c19ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410216571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.410216571
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3927865586
Short name T268
Test name
Test status
Simulation time 7939684050 ps
CPU time 114.43 seconds
Started Aug 02 05:55:10 PM PDT 24
Finished Aug 02 05:57:05 PM PDT 24
Peak memory 229164 kb
Host smart-477976be-cfe2-49f4-9fff-3e7e2e8dd7d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927865586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3927865586
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3449692790
Short name T120
Test name
Test status
Simulation time 620428950 ps
CPU time 9.4 seconds
Started Aug 02 05:55:10 PM PDT 24
Finished Aug 02 05:55:19 PM PDT 24
Peak memory 213052 kb
Host smart-5bb6acb0-4c92-43bb-8154-317f1efc4152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449692790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3449692790
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3742411755
Short name T206
Test name
Test status
Simulation time 532777014 ps
CPU time 6.53 seconds
Started Aug 02 05:55:09 PM PDT 24
Finished Aug 02 05:55:16 PM PDT 24
Peak memory 211892 kb
Host smart-09c08929-db70-474d-96dd-a7d5929628c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3742411755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3742411755
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.524962708
Short name T142
Test name
Test status
Simulation time 450189713 ps
CPU time 7.54 seconds
Started Aug 02 05:55:05 PM PDT 24
Finished Aug 02 05:55:13 PM PDT 24
Peak memory 212164 kb
Host smart-52ea92f7-bf92-4c42-b192-fbcb2fc1e5ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524962708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.524962708
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3632720568
Short name T8
Test name
Test status
Simulation time 87474360 ps
CPU time 4.3 seconds
Started Aug 02 05:55:16 PM PDT 24
Finished Aug 02 05:55:20 PM PDT 24
Peak memory 212124 kb
Host smart-88e5ad7d-52de-4d12-bc84-5ff0574553eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632720568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3632720568
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.466791610
Short name T272
Test name
Test status
Simulation time 9142202397 ps
CPU time 158.32 seconds
Started Aug 02 05:55:17 PM PDT 24
Finished Aug 02 05:57:55 PM PDT 24
Peak memory 226180 kb
Host smart-171aa172-f934-4ab8-9583-073e2a20cff0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466791610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.466791610
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.851534004
Short name T295
Test name
Test status
Simulation time 1277549820 ps
CPU time 9.19 seconds
Started Aug 02 05:55:20 PM PDT 24
Finished Aug 02 05:55:29 PM PDT 24
Peak memory 212844 kb
Host smart-0bb6db93-05cf-4870-9683-c32e676ff903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851534004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.851534004
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2847285827
Short name T94
Test name
Test status
Simulation time 276004334 ps
CPU time 6.23 seconds
Started Aug 02 05:55:17 PM PDT 24
Finished Aug 02 05:55:24 PM PDT 24
Peak memory 212180 kb
Host smart-d2ff9e44-2a0b-467c-8285-1a6247fa6c9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2847285827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2847285827
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.339676179
Short name T327
Test name
Test status
Simulation time 458613286 ps
CPU time 18.92 seconds
Started Aug 02 05:55:16 PM PDT 24
Finished Aug 02 05:55:35 PM PDT 24
Peak memory 213548 kb
Host smart-783af89a-d9b4-40d9-a9be-ab9a64e14e69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339676179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.339676179
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1765658213
Short name T49
Test name
Test status
Simulation time 84657280625 ps
CPU time 8759.29 seconds
Started Aug 02 05:55:20 PM PDT 24
Finished Aug 02 08:21:21 PM PDT 24
Peak memory 232232 kb
Host smart-7884b59c-f1c2-4b3d-b7c2-779345f885c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765658213 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.1765658213
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.994341740
Short name T151
Test name
Test status
Simulation time 2885523668 ps
CPU time 7.63 seconds
Started Aug 02 05:55:16 PM PDT 24
Finished Aug 02 05:55:24 PM PDT 24
Peak memory 212196 kb
Host smart-00923ec2-2603-4fbc-b434-395f7175df77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994341740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.994341740
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1055592649
Short name T284
Test name
Test status
Simulation time 79782731218 ps
CPU time 168.65 seconds
Started Aug 02 05:55:18 PM PDT 24
Finished Aug 02 05:58:06 PM PDT 24
Peak memory 234720 kb
Host smart-a51a8573-bf38-412b-8fba-9908d96abdc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055592649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1055592649
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1944645452
Short name T233
Test name
Test status
Simulation time 420063844 ps
CPU time 9.49 seconds
Started Aug 02 05:55:17 PM PDT 24
Finished Aug 02 05:55:27 PM PDT 24
Peak memory 213196 kb
Host smart-3373cc4b-ab29-48b8-9dbb-b2156c6eefa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944645452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1944645452
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2260672946
Short name T57
Test name
Test status
Simulation time 391270324 ps
CPU time 5.69 seconds
Started Aug 02 05:55:21 PM PDT 24
Finished Aug 02 05:55:27 PM PDT 24
Peak memory 212192 kb
Host smart-931ac7a7-951b-475d-80d7-0f0fd6a3ca58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2260672946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2260672946
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2496974874
Short name T308
Test name
Test status
Simulation time 220497633 ps
CPU time 12.8 seconds
Started Aug 02 05:55:20 PM PDT 24
Finished Aug 02 05:55:33 PM PDT 24
Peak memory 217044 kb
Host smart-244816f3-fffb-4edd-af43-079fa6fc2b9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496974874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2496974874
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3726016434
Short name T134
Test name
Test status
Simulation time 129140027 ps
CPU time 5.23 seconds
Started Aug 02 05:55:17 PM PDT 24
Finished Aug 02 05:55:23 PM PDT 24
Peak memory 212080 kb
Host smart-a37e2a74-03e8-42ee-94c1-3b3bb06f7d24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726016434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3726016434
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3652222433
Short name T194
Test name
Test status
Simulation time 2468519073 ps
CPU time 143.88 seconds
Started Aug 02 05:55:16 PM PDT 24
Finished Aug 02 05:57:40 PM PDT 24
Peak memory 238524 kb
Host smart-aef0e8e7-1c91-4024-94c9-6f0fa7950a62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652222433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3652222433
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1937926315
Short name T185
Test name
Test status
Simulation time 500265679 ps
CPU time 11.17 seconds
Started Aug 02 05:55:16 PM PDT 24
Finished Aug 02 05:55:28 PM PDT 24
Peak memory 212952 kb
Host smart-553e809b-e33a-44c4-97f1-492e23515ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937926315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1937926315
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4150936191
Short name T303
Test name
Test status
Simulation time 540687171 ps
CPU time 6.42 seconds
Started Aug 02 05:55:19 PM PDT 24
Finished Aug 02 05:55:25 PM PDT 24
Peak memory 212260 kb
Host smart-54168b2f-da67-4cc8-9541-2f4765c07a5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4150936191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4150936191
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2069711118
Short name T223
Test name
Test status
Simulation time 367654462 ps
CPU time 23.25 seconds
Started Aug 02 05:55:15 PM PDT 24
Finished Aug 02 05:55:39 PM PDT 24
Peak memory 216240 kb
Host smart-856f797a-df34-4e74-86ab-b3df02ef5634
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069711118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2069711118
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4035222251
Short name T3
Test name
Test status
Simulation time 691114252 ps
CPU time 4.22 seconds
Started Aug 02 05:55:20 PM PDT 24
Finished Aug 02 05:55:24 PM PDT 24
Peak memory 212056 kb
Host smart-abd25fd7-5ad5-4e45-9b08-791b5cc86224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035222251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4035222251
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3805971310
Short name T198
Test name
Test status
Simulation time 4443823005 ps
CPU time 54.15 seconds
Started Aug 02 05:55:17 PM PDT 24
Finished Aug 02 05:56:11 PM PDT 24
Peak memory 213504 kb
Host smart-b36fccba-2d21-45f7-9dc6-5d195c65f027
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805971310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3805971310
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4071271634
Short name T29
Test name
Test status
Simulation time 250982103 ps
CPU time 11.14 seconds
Started Aug 02 05:55:19 PM PDT 24
Finished Aug 02 05:55:30 PM PDT 24
Peak memory 212904 kb
Host smart-7d766b35-6827-482d-8ac4-f30a56195cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071271634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4071271634
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.169758775
Short name T58
Test name
Test status
Simulation time 545400451 ps
CPU time 6.11 seconds
Started Aug 02 05:55:15 PM PDT 24
Finished Aug 02 05:55:22 PM PDT 24
Peak memory 212208 kb
Host smart-3d08e08f-1419-4b53-b793-dd2df439bf42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=169758775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.169758775
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.4113601980
Short name T258
Test name
Test status
Simulation time 186997828 ps
CPU time 7.5 seconds
Started Aug 02 05:55:21 PM PDT 24
Finished Aug 02 05:55:28 PM PDT 24
Peak memory 212104 kb
Host smart-08914ae7-3ae8-4335-ad9b-bf253c4454dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113601980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.4113601980
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.4068686065
Short name T162
Test name
Test status
Simulation time 216586356 ps
CPU time 4.98 seconds
Started Aug 02 05:55:18 PM PDT 24
Finished Aug 02 05:55:23 PM PDT 24
Peak memory 212088 kb
Host smart-b13f60a3-c556-45db-a3d1-7d2fd8d3f0bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068686065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.4068686065
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3198593797
Short name T218
Test name
Test status
Simulation time 2618975636 ps
CPU time 137.29 seconds
Started Aug 02 05:55:20 PM PDT 24
Finished Aug 02 05:57:38 PM PDT 24
Peak memory 238544 kb
Host smart-53660f43-2914-4c70-b5ea-a6be9fd5c5f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198593797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3198593797
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.450383498
Short name T298
Test name
Test status
Simulation time 169896511 ps
CPU time 9.57 seconds
Started Aug 02 05:55:22 PM PDT 24
Finished Aug 02 05:55:32 PM PDT 24
Peak memory 213132 kb
Host smart-ecdf294c-557b-46cc-a3d3-f9a8b0acaf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450383498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.450383498
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1002000145
Short name T139
Test name
Test status
Simulation time 101483181 ps
CPU time 5.54 seconds
Started Aug 02 05:55:19 PM PDT 24
Finished Aug 02 05:55:25 PM PDT 24
Peak memory 212160 kb
Host smart-00442c19-d5a6-4fef-9279-37002388aa8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1002000145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1002000145
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3136774595
Short name T75
Test name
Test status
Simulation time 202724769 ps
CPU time 12.24 seconds
Started Aug 02 05:55:21 PM PDT 24
Finished Aug 02 05:55:33 PM PDT 24
Peak memory 215832 kb
Host smart-ee2c37d8-fb02-4ac6-ba5e-2e3ef4c189a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136774595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3136774595
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.402177885
Short name T99
Test name
Test status
Simulation time 263730547673 ps
CPU time 2946.95 seconds
Started Aug 02 05:55:16 PM PDT 24
Finished Aug 02 06:44:23 PM PDT 24
Peak memory 244912 kb
Host smart-d88d301d-f138-4c5b-9401-49e54469bb89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402177885 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.402177885
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3735428763
Short name T210
Test name
Test status
Simulation time 87471527 ps
CPU time 4.28 seconds
Started Aug 02 05:55:16 PM PDT 24
Finished Aug 02 05:55:21 PM PDT 24
Peak memory 212092 kb
Host smart-be9b385f-867f-4baa-9f78-78a7ec5a0377
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735428763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3735428763
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.694394092
Short name T175
Test name
Test status
Simulation time 1672986994 ps
CPU time 119.21 seconds
Started Aug 02 05:55:21 PM PDT 24
Finished Aug 02 05:57:20 PM PDT 24
Peak memory 237440 kb
Host smart-60b6c11a-8077-4d5f-8185-b86f81f635ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694394092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.694394092
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.787118560
Short name T226
Test name
Test status
Simulation time 4155929878 ps
CPU time 11.06 seconds
Started Aug 02 05:55:18 PM PDT 24
Finished Aug 02 05:55:30 PM PDT 24
Peak memory 213052 kb
Host smart-87e9cb85-98a5-4782-8499-af442a62f0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787118560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.787118560
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3971624739
Short name T215
Test name
Test status
Simulation time 278035485 ps
CPU time 6.24 seconds
Started Aug 02 05:55:21 PM PDT 24
Finished Aug 02 05:55:28 PM PDT 24
Peak memory 212200 kb
Host smart-6f12b07e-8f61-4628-964e-aaf51537411b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3971624739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3971624739
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2327084493
Short name T307
Test name
Test status
Simulation time 325505896 ps
CPU time 18.33 seconds
Started Aug 02 05:55:19 PM PDT 24
Finished Aug 02 05:55:37 PM PDT 24
Peak memory 217284 kb
Host smart-3bbabca2-7f97-47a0-83f9-5c14930987ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327084493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2327084493
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2117485410
Short name T171
Test name
Test status
Simulation time 333045993 ps
CPU time 4.3 seconds
Started Aug 02 05:55:18 PM PDT 24
Finished Aug 02 05:55:23 PM PDT 24
Peak memory 212108 kb
Host smart-a461b087-69c7-41f9-b67b-5bc34df0bd8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117485410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2117485410
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1449716554
Short name T306
Test name
Test status
Simulation time 4465910412 ps
CPU time 150.44 seconds
Started Aug 02 05:55:16 PM PDT 24
Finished Aug 02 05:57:47 PM PDT 24
Peak memory 234524 kb
Host smart-4a1affca-b70c-4ebd-b2d7-39c079a4d683
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449716554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1449716554
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2366612321
Short name T267
Test name
Test status
Simulation time 836881030 ps
CPU time 9.53 seconds
Started Aug 02 05:55:15 PM PDT 24
Finished Aug 02 05:55:25 PM PDT 24
Peak memory 213076 kb
Host smart-558038e6-bc9e-4da2-9bc9-9769b1e4bf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366612321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2366612321
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.497699955
Short name T283
Test name
Test status
Simulation time 1622460985 ps
CPU time 6.38 seconds
Started Aug 02 05:55:19 PM PDT 24
Finished Aug 02 05:55:25 PM PDT 24
Peak memory 212160 kb
Host smart-0cf0a638-b945-4302-856b-5e7b3d309aa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=497699955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.497699955
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3725374837
Short name T321
Test name
Test status
Simulation time 305266309 ps
CPU time 18.93 seconds
Started Aug 02 05:55:16 PM PDT 24
Finished Aug 02 05:55:35 PM PDT 24
Peak memory 215076 kb
Host smart-4fd71715-9fd7-495e-83d5-473b1ca1e25b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725374837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3725374837
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1758645288
Short name T161
Test name
Test status
Simulation time 100659304551 ps
CPU time 3588.93 seconds
Started Aug 02 05:55:17 PM PDT 24
Finished Aug 02 06:55:06 PM PDT 24
Peak memory 246236 kb
Host smart-f7546a2a-036d-4548-8847-71e36b4a04a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758645288 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1758645288
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3699961350
Short name T53
Test name
Test status
Simulation time 127325939 ps
CPU time 5.18 seconds
Started Aug 02 05:54:41 PM PDT 24
Finished Aug 02 05:54:46 PM PDT 24
Peak memory 212088 kb
Host smart-0e47dd90-c227-42cd-ae40-934c15c34a36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699961350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3699961350
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3024507629
Short name T40
Test name
Test status
Simulation time 12689911970 ps
CPU time 166.4 seconds
Started Aug 02 05:54:46 PM PDT 24
Finished Aug 02 05:57:33 PM PDT 24
Peak memory 228888 kb
Host smart-f3f3ecd5-7835-46c3-9bb8-c742e26eb2fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024507629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3024507629
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3152228160
Short name T176
Test name
Test status
Simulation time 479299791 ps
CPU time 11.39 seconds
Started Aug 02 05:54:39 PM PDT 24
Finished Aug 02 05:54:51 PM PDT 24
Peak memory 213676 kb
Host smart-0ac1f41e-70b3-4f76-9c5b-24c0e8af6da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152228160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3152228160
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.787234516
Short name T229
Test name
Test status
Simulation time 96802862 ps
CPU time 5.85 seconds
Started Aug 02 05:54:41 PM PDT 24
Finished Aug 02 05:54:47 PM PDT 24
Peak memory 212184 kb
Host smart-44c310d6-e4d2-4263-8405-0da484e8707b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=787234516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.787234516
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.940386916
Short name T26
Test name
Test status
Simulation time 688981147 ps
CPU time 53.08 seconds
Started Aug 02 05:54:41 PM PDT 24
Finished Aug 02 05:55:34 PM PDT 24
Peak memory 237432 kb
Host smart-86fee4d7-24e1-4cda-8acc-cf8fe823746e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940386916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.940386916
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2994696027
Short name T330
Test name
Test status
Simulation time 519908389 ps
CPU time 8.74 seconds
Started Aug 02 05:54:45 PM PDT 24
Finished Aug 02 05:54:54 PM PDT 24
Peak memory 212172 kb
Host smart-69c59eac-98b5-4bdd-a4e2-63027ed7f8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994696027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2994696027
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.903118690
Short name T76
Test name
Test status
Simulation time 392573122 ps
CPU time 12.18 seconds
Started Aug 02 05:54:41 PM PDT 24
Finished Aug 02 05:54:54 PM PDT 24
Peak memory 214464 kb
Host smart-2cfeb07b-88a1-4148-a261-e95845ebdef3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903118690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.903118690
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1500860492
Short name T157
Test name
Test status
Simulation time 333205234 ps
CPU time 4.28 seconds
Started Aug 02 05:55:30 PM PDT 24
Finished Aug 02 05:55:34 PM PDT 24
Peak memory 212100 kb
Host smart-405f9e92-4022-403f-8568-fefb2ff10668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500860492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1500860492
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.468394066
Short name T156
Test name
Test status
Simulation time 8389878350 ps
CPU time 155.87 seconds
Started Aug 02 05:55:24 PM PDT 24
Finished Aug 02 05:58:00 PM PDT 24
Peak memory 234860 kb
Host smart-bfceba6b-e93e-4fc8-b1b3-7b50364f2a5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468394066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.468394066
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3199796903
Short name T115
Test name
Test status
Simulation time 1242480315 ps
CPU time 11.12 seconds
Started Aug 02 05:55:29 PM PDT 24
Finished Aug 02 05:55:40 PM PDT 24
Peak memory 212976 kb
Host smart-a6ef18d7-906e-4a2d-8f0a-6b85e5c16bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199796903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3199796903
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.591493929
Short name T304
Test name
Test status
Simulation time 1943001619 ps
CPU time 8.94 seconds
Started Aug 02 05:55:29 PM PDT 24
Finished Aug 02 05:55:38 PM PDT 24
Peak memory 212232 kb
Host smart-d34a4828-97cf-4e5b-aead-b1783c7bd211
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=591493929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.591493929
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.923708862
Short name T165
Test name
Test status
Simulation time 273862368 ps
CPU time 15.16 seconds
Started Aug 02 05:55:25 PM PDT 24
Finished Aug 02 05:55:41 PM PDT 24
Peak memory 215372 kb
Host smart-7e036396-7fd2-4fd4-a576-8b7ec85c9b07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923708862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.923708862
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3355438396
Short name T311
Test name
Test status
Simulation time 89024945 ps
CPU time 4.18 seconds
Started Aug 02 05:55:31 PM PDT 24
Finished Aug 02 05:55:36 PM PDT 24
Peak memory 212056 kb
Host smart-7893f484-18d2-4685-be0b-a950fda727cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355438396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3355438396
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3739658518
Short name T286
Test name
Test status
Simulation time 3928595004 ps
CPU time 193.97 seconds
Started Aug 02 05:55:25 PM PDT 24
Finished Aug 02 05:58:39 PM PDT 24
Peak memory 214496 kb
Host smart-3e2e7030-95b2-4f29-a76e-55d3e8213fe7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739658518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3739658518
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3948717302
Short name T325
Test name
Test status
Simulation time 784549842 ps
CPU time 11.28 seconds
Started Aug 02 05:55:24 PM PDT 24
Finished Aug 02 05:55:36 PM PDT 24
Peak memory 212224 kb
Host smart-7919489b-e276-4ef1-a2df-35e423e9b8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948717302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3948717302
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3637815565
Short name T260
Test name
Test status
Simulation time 522987338 ps
CPU time 6.23 seconds
Started Aug 02 05:55:21 PM PDT 24
Finished Aug 02 05:55:28 PM PDT 24
Peak memory 212236 kb
Host smart-6a161cf3-7d06-476e-8152-3e1edac50cbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3637815565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3637815565
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.820632483
Short name T234
Test name
Test status
Simulation time 820292847 ps
CPU time 8.1 seconds
Started Aug 02 05:55:23 PM PDT 24
Finished Aug 02 05:55:31 PM PDT 24
Peak memory 212148 kb
Host smart-0c4a5e60-f077-45b4-afe8-a656248d536e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820632483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.820632483
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1275300663
Short name T201
Test name
Test status
Simulation time 86239037 ps
CPU time 4.41 seconds
Started Aug 02 05:55:24 PM PDT 24
Finished Aug 02 05:55:28 PM PDT 24
Peak memory 212124 kb
Host smart-c408811a-64e2-446c-ab7a-807c3937518d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275300663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1275300663
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2247681936
Short name T17
Test name
Test status
Simulation time 4060254616 ps
CPU time 106.21 seconds
Started Aug 02 05:55:26 PM PDT 24
Finished Aug 02 05:57:12 PM PDT 24
Peak memory 238496 kb
Host smart-a954aabe-8188-4636-9a6d-c29f8ddd2b27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247681936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2247681936
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.4145915295
Short name T2
Test name
Test status
Simulation time 257541971 ps
CPU time 11.48 seconds
Started Aug 02 05:55:24 PM PDT 24
Finished Aug 02 05:55:35 PM PDT 24
Peak memory 212164 kb
Host smart-63120947-0f22-4d22-9054-9a507df376c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145915295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.4145915295
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3285586100
Short name T154
Test name
Test status
Simulation time 201977425 ps
CPU time 5.82 seconds
Started Aug 02 05:55:30 PM PDT 24
Finished Aug 02 05:55:36 PM PDT 24
Peak memory 212172 kb
Host smart-f9cefdc4-de6d-4315-aab0-cd843300d2b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3285586100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3285586100
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3277771285
Short name T301
Test name
Test status
Simulation time 572439359 ps
CPU time 11.73 seconds
Started Aug 02 05:55:26 PM PDT 24
Finished Aug 02 05:55:38 PM PDT 24
Peak memory 212364 kb
Host smart-515976eb-7848-4d51-b87c-f814914964f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277771285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3277771285
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.996393426
Short name T178
Test name
Test status
Simulation time 171688971 ps
CPU time 4.21 seconds
Started Aug 02 05:55:27 PM PDT 24
Finished Aug 02 05:55:31 PM PDT 24
Peak memory 212044 kb
Host smart-af7f1703-8579-425d-bdcf-322b9a758555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996393426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.996393426
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2374204890
Short name T147
Test name
Test status
Simulation time 5075573287 ps
CPU time 139.25 seconds
Started Aug 02 05:55:24 PM PDT 24
Finished Aug 02 05:57:43 PM PDT 24
Peak memory 214516 kb
Host smart-536a7364-f896-495a-847f-75524b5160cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374204890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2374204890
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4023108378
Short name T254
Test name
Test status
Simulation time 1036772776 ps
CPU time 11.07 seconds
Started Aug 02 05:55:29 PM PDT 24
Finished Aug 02 05:55:40 PM PDT 24
Peak memory 212944 kb
Host smart-ec6605bd-bcba-4218-acc6-eafb0728cd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023108378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4023108378
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3185768
Short name T136
Test name
Test status
Simulation time 136963795 ps
CPU time 6.33 seconds
Started Aug 02 05:55:30 PM PDT 24
Finished Aug 02 05:55:36 PM PDT 24
Peak memory 212208 kb
Host smart-845bcc9b-05f1-433e-a4f2-06081c2e9646
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3185768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3185768
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1903907862
Short name T181
Test name
Test status
Simulation time 2632894022 ps
CPU time 9.83 seconds
Started Aug 02 05:55:25 PM PDT 24
Finished Aug 02 05:55:35 PM PDT 24
Peak memory 214904 kb
Host smart-0b33ff3b-2eb1-4fed-97a7-94b4f1e62e9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903907862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1903907862
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2029147093
Short name T322
Test name
Test status
Simulation time 589534932 ps
CPU time 4.99 seconds
Started Aug 02 05:55:23 PM PDT 24
Finished Aug 02 05:55:28 PM PDT 24
Peak memory 212056 kb
Host smart-1f414ffb-c659-4b8c-878c-1c1ea9357c7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029147093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2029147093
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1535118324
Short name T148
Test name
Test status
Simulation time 47952953712 ps
CPU time 216.74 seconds
Started Aug 02 05:55:30 PM PDT 24
Finished Aug 02 05:59:07 PM PDT 24
Peak memory 239516 kb
Host smart-43be9723-4e17-4a2d-be64-a92de2126782
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535118324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1535118324
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.716614195
Short name T23
Test name
Test status
Simulation time 177330805 ps
CPU time 9.16 seconds
Started Aug 02 05:55:30 PM PDT 24
Finished Aug 02 05:55:40 PM PDT 24
Peak memory 212988 kb
Host smart-aa155bcb-6b1e-4e55-b6ca-1273dda10966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716614195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.716614195
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.403188389
Short name T312
Test name
Test status
Simulation time 527225175 ps
CPU time 6.1 seconds
Started Aug 02 05:55:24 PM PDT 24
Finished Aug 02 05:55:30 PM PDT 24
Peak memory 212204 kb
Host smart-b37d8ec3-6223-4c0c-8411-9e6b3d1ffdc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403188389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.403188389
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.669024292
Short name T13
Test name
Test status
Simulation time 307848341 ps
CPU time 17.76 seconds
Started Aug 02 05:55:27 PM PDT 24
Finished Aug 02 05:55:45 PM PDT 24
Peak memory 216352 kb
Host smart-73b35021-bb43-4b97-a912-2e8ac796619d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669024292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.669024292
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1377101068
Short name T208
Test name
Test status
Simulation time 333839410 ps
CPU time 4.3 seconds
Started Aug 02 05:55:24 PM PDT 24
Finished Aug 02 05:55:28 PM PDT 24
Peak memory 212108 kb
Host smart-cd58fda9-0bab-4658-9144-aeb3ddb9c106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377101068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1377101068
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.447349794
Short name T290
Test name
Test status
Simulation time 6636419684 ps
CPU time 88.18 seconds
Started Aug 02 05:55:31 PM PDT 24
Finished Aug 02 05:56:59 PM PDT 24
Peak memory 213436 kb
Host smart-d9abc1d9-9973-4635-b74b-230db02d769a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447349794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.447349794
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3765752578
Short name T211
Test name
Test status
Simulation time 1782409571 ps
CPU time 10.96 seconds
Started Aug 02 05:55:31 PM PDT 24
Finished Aug 02 05:55:42 PM PDT 24
Peak memory 213172 kb
Host smart-d735b6fa-ec61-4922-8900-2cd05702afa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765752578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3765752578
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2651862012
Short name T217
Test name
Test status
Simulation time 396376271 ps
CPU time 5.82 seconds
Started Aug 02 05:55:25 PM PDT 24
Finished Aug 02 05:55:31 PM PDT 24
Peak memory 212208 kb
Host smart-5cec266d-a2a5-420c-84a9-badcf981f7ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2651862012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2651862012
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1259697180
Short name T70
Test name
Test status
Simulation time 864509410 ps
CPU time 11.04 seconds
Started Aug 02 05:55:29 PM PDT 24
Finished Aug 02 05:55:40 PM PDT 24
Peak memory 215280 kb
Host smart-dcb652f2-7ff5-4b75-9dee-1ad645751223
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259697180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1259697180
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.633279368
Short name T180
Test name
Test status
Simulation time 85438232 ps
CPU time 4.32 seconds
Started Aug 02 05:55:30 PM PDT 24
Finished Aug 02 05:55:35 PM PDT 24
Peak memory 212044 kb
Host smart-e44f8628-1af8-4c1f-bea2-b7ce7130e1b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633279368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.633279368
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.145168363
Short name T216
Test name
Test status
Simulation time 14556236717 ps
CPU time 128.55 seconds
Started Aug 02 05:55:24 PM PDT 24
Finished Aug 02 05:57:33 PM PDT 24
Peak memory 213484 kb
Host smart-18376c8c-9d8e-4167-9de9-b63ee3ed34e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145168363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.145168363
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.338170716
Short name T250
Test name
Test status
Simulation time 263034352 ps
CPU time 11.33 seconds
Started Aug 02 05:55:23 PM PDT 24
Finished Aug 02 05:55:34 PM PDT 24
Peak memory 213004 kb
Host smart-8b1edd67-c51b-4727-90e8-a767a23882e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338170716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.338170716
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.4104229560
Short name T191
Test name
Test status
Simulation time 197968082 ps
CPU time 5.9 seconds
Started Aug 02 05:55:30 PM PDT 24
Finished Aug 02 05:55:36 PM PDT 24
Peak memory 212196 kb
Host smart-97227575-ec80-4ac7-87cb-82e7a2a6bb6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4104229560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.4104229560
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1679085745
Short name T291
Test name
Test status
Simulation time 2101592280 ps
CPU time 19.55 seconds
Started Aug 02 05:55:27 PM PDT 24
Finished Aug 02 05:55:46 PM PDT 24
Peak memory 214804 kb
Host smart-1f0bd772-2de4-45e8-bb4c-6ccce6f8aa16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679085745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1679085745
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.147041641
Short name T253
Test name
Test status
Simulation time 128900441 ps
CPU time 5.06 seconds
Started Aug 02 05:55:29 PM PDT 24
Finished Aug 02 05:55:34 PM PDT 24
Peak memory 212060 kb
Host smart-63d66016-7b89-4025-ab2a-c1a69bde7bed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147041641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.147041641
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3118408931
Short name T280
Test name
Test status
Simulation time 11190574689 ps
CPU time 127.3 seconds
Started Aug 02 05:55:23 PM PDT 24
Finished Aug 02 05:57:31 PM PDT 24
Peak memory 238252 kb
Host smart-c88cd68a-6bbd-4147-96f6-7af3bf21ea17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118408931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3118408931
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2241777660
Short name T121
Test name
Test status
Simulation time 619211750 ps
CPU time 9.51 seconds
Started Aug 02 05:55:32 PM PDT 24
Finished Aug 02 05:55:42 PM PDT 24
Peak memory 213000 kb
Host smart-5d889839-da70-45b6-91b5-f3c42935d505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241777660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2241777660
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.352747633
Short name T246
Test name
Test status
Simulation time 144002560 ps
CPU time 6.63 seconds
Started Aug 02 05:55:29 PM PDT 24
Finished Aug 02 05:55:36 PM PDT 24
Peak memory 212232 kb
Host smart-7960c62f-3b38-4ef6-90a4-e884439ef7cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=352747633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.352747633
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3921066644
Short name T205
Test name
Test status
Simulation time 815262001 ps
CPU time 10.41 seconds
Started Aug 02 05:55:31 PM PDT 24
Finished Aug 02 05:55:41 PM PDT 24
Peak memory 214916 kb
Host smart-b84299a5-aaea-43a1-9eea-e5746488b93d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921066644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3921066644
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.97451010
Short name T11
Test name
Test status
Simulation time 65913772225 ps
CPU time 7966.2 seconds
Started Aug 02 05:55:33 PM PDT 24
Finished Aug 02 08:08:20 PM PDT 24
Peak memory 236696 kb
Host smart-bfefe30b-ae0c-4aae-aa56-7baa00527215
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97451010 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.97451010
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1022621387
Short name T320
Test name
Test status
Simulation time 89299481 ps
CPU time 4.17 seconds
Started Aug 02 05:55:33 PM PDT 24
Finished Aug 02 05:55:37 PM PDT 24
Peak memory 212084 kb
Host smart-57623ea3-3602-44e0-be57-00b39475f5e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022621387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1022621387
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.154864829
Short name T36
Test name
Test status
Simulation time 26901708324 ps
CPU time 154.32 seconds
Started Aug 02 05:55:31 PM PDT 24
Finished Aug 02 05:58:05 PM PDT 24
Peak memory 226336 kb
Host smart-fcae0a97-5c6b-4447-8405-93d1e04d5f65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154864829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.154864829
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1536792137
Short name T42
Test name
Test status
Simulation time 2774666299 ps
CPU time 11.39 seconds
Started Aug 02 05:55:31 PM PDT 24
Finished Aug 02 05:55:42 PM PDT 24
Peak memory 213828 kb
Host smart-956a6af3-f4a4-4f02-9522-63cdcd45d5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536792137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1536792137
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2125986238
Short name T119
Test name
Test status
Simulation time 95684957 ps
CPU time 5.55 seconds
Started Aug 02 05:55:32 PM PDT 24
Finished Aug 02 05:55:38 PM PDT 24
Peak memory 212176 kb
Host smart-7a7ad4c4-4b9f-48f6-999c-a7eb1694784f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2125986238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2125986238
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.4158209077
Short name T10
Test name
Test status
Simulation time 418565145 ps
CPU time 18.53 seconds
Started Aug 02 05:55:31 PM PDT 24
Finished Aug 02 05:55:50 PM PDT 24
Peak memory 214952 kb
Host smart-cffddbac-4e29-4cc6-bcd0-54fa5b4df371
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158209077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.4158209077
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2993702582
Short name T277
Test name
Test status
Simulation time 143754991609 ps
CPU time 8082.39 seconds
Started Aug 02 05:55:33 PM PDT 24
Finished Aug 02 08:10:16 PM PDT 24
Peak memory 237476 kb
Host smart-dc5b689f-2012-4a3f-bb9d-89f4617b5ba9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993702582 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2993702582
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3310988145
Short name T114
Test name
Test status
Simulation time 498833757 ps
CPU time 5.2 seconds
Started Aug 02 05:55:31 PM PDT 24
Finished Aug 02 05:55:36 PM PDT 24
Peak memory 212080 kb
Host smart-3e5ef674-6978-4a6f-a36c-8623bf4f15e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310988145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3310988145
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3662599893
Short name T43
Test name
Test status
Simulation time 168424259 ps
CPU time 9.75 seconds
Started Aug 02 05:55:37 PM PDT 24
Finished Aug 02 05:55:47 PM PDT 24
Peak memory 212860 kb
Host smart-c7604429-1115-4277-a4e2-e9783e976878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662599893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3662599893
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3653847190
Short name T160
Test name
Test status
Simulation time 2231939265 ps
CPU time 6.54 seconds
Started Aug 02 05:55:30 PM PDT 24
Finished Aug 02 05:55:37 PM PDT 24
Peak memory 212308 kb
Host smart-2a28be91-f644-40c9-b774-576f7e16cfb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3653847190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3653847190
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3737051275
Short name T72
Test name
Test status
Simulation time 846244406 ps
CPU time 14.35 seconds
Started Aug 02 05:55:30 PM PDT 24
Finished Aug 02 05:55:45 PM PDT 24
Peak memory 214496 kb
Host smart-5771417c-2cdb-4e0d-96aa-fa7d5ab965ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737051275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3737051275
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.656942790
Short name T190
Test name
Test status
Simulation time 85747453 ps
CPU time 4.37 seconds
Started Aug 02 05:54:47 PM PDT 24
Finished Aug 02 05:54:52 PM PDT 24
Peak memory 212076 kb
Host smart-3f6c816b-1e9b-48ba-bc42-3790cf3359b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656942790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.656942790
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3042133836
Short name T192
Test name
Test status
Simulation time 23507520190 ps
CPU time 76.13 seconds
Started Aug 02 05:54:41 PM PDT 24
Finished Aug 02 05:55:57 PM PDT 24
Peak memory 229244 kb
Host smart-0ede8aff-0ced-4cf9-b56f-8d7b1b4ebed9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042133836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3042133836
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3816950052
Short name T30
Test name
Test status
Simulation time 169649323 ps
CPU time 9.56 seconds
Started Aug 02 05:54:45 PM PDT 24
Finished Aug 02 05:54:54 PM PDT 24
Peak memory 212932 kb
Host smart-83baf031-f78a-4e10-b18c-8c59bc8da19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816950052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3816950052
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.825123489
Short name T5
Test name
Test status
Simulation time 135227057 ps
CPU time 6.56 seconds
Started Aug 02 05:54:39 PM PDT 24
Finished Aug 02 05:54:46 PM PDT 24
Peak memory 212228 kb
Host smart-dc358854-8e42-4278-99d6-c14e780c7326
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=825123489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.825123489
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1514071748
Short name T131
Test name
Test status
Simulation time 189785185 ps
CPU time 5.52 seconds
Started Aug 02 05:54:41 PM PDT 24
Finished Aug 02 05:54:47 PM PDT 24
Peak memory 212176 kb
Host smart-3cbca4f5-accd-4402-8f37-8b26a1bb7ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514071748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1514071748
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3153811534
Short name T118
Test name
Test status
Simulation time 1304737339 ps
CPU time 14.62 seconds
Started Aug 02 05:54:41 PM PDT 24
Finished Aug 02 05:54:56 PM PDT 24
Peak memory 215076 kb
Host smart-77c09406-d2af-4738-8708-a3e5f934ca0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153811534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3153811534
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3144025040
Short name T288
Test name
Test status
Simulation time 827824132 ps
CPU time 5.08 seconds
Started Aug 02 05:54:47 PM PDT 24
Finished Aug 02 05:54:52 PM PDT 24
Peak memory 212068 kb
Host smart-aa45888a-2790-422f-b01a-f10206b33643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144025040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3144025040
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1269574320
Short name T163
Test name
Test status
Simulation time 295673513 ps
CPU time 11.31 seconds
Started Aug 02 05:54:40 PM PDT 24
Finished Aug 02 05:54:51 PM PDT 24
Peak memory 213064 kb
Host smart-2ab95ee1-a656-4e6b-b370-df392fab8ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269574320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1269574320
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.724813909
Short name T113
Test name
Test status
Simulation time 1781724729 ps
CPU time 8.62 seconds
Started Aug 02 05:54:39 PM PDT 24
Finished Aug 02 05:54:48 PM PDT 24
Peak memory 212216 kb
Host smart-6dc1c0b0-7d57-454b-bd11-37bed1521605
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=724813909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.724813909
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3480405084
Short name T179
Test name
Test status
Simulation time 189507162 ps
CPU time 5.75 seconds
Started Aug 02 05:54:43 PM PDT 24
Finished Aug 02 05:54:49 PM PDT 24
Peak memory 212224 kb
Host smart-8d92f8ac-5891-40cf-ac15-bb4eba8d456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480405084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3480405084
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2845006259
Short name T137
Test name
Test status
Simulation time 4083547346 ps
CPU time 37.38 seconds
Started Aug 02 05:54:42 PM PDT 24
Finished Aug 02 05:55:20 PM PDT 24
Peak memory 218456 kb
Host smart-43875b31-8bf2-49fc-a9ae-256cbe6ddb7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845006259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2845006259
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1470166012
Short name T96
Test name
Test status
Simulation time 78645461545 ps
CPU time 9398.82 seconds
Started Aug 02 05:54:41 PM PDT 24
Finished Aug 02 08:31:21 PM PDT 24
Peak memory 231644 kb
Host smart-68a31f9f-d1f0-4c51-bfc8-a807b493fa92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470166012 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.1470166012
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.353134262
Short name T262
Test name
Test status
Simulation time 171752363 ps
CPU time 4.43 seconds
Started Aug 02 05:54:41 PM PDT 24
Finished Aug 02 05:54:45 PM PDT 24
Peak memory 212108 kb
Host smart-24c3f535-dadb-482a-b615-eb6dc27b0703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353134262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.353134262
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2726494692
Short name T237
Test name
Test status
Simulation time 3259888280 ps
CPU time 94.92 seconds
Started Aug 02 05:54:44 PM PDT 24
Finished Aug 02 05:56:19 PM PDT 24
Peak memory 213352 kb
Host smart-42da059d-0243-43d6-bff6-7dbdea7e3e05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726494692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2726494692
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1291236890
Short name T329
Test name
Test status
Simulation time 1253097131 ps
CPU time 11.14 seconds
Started Aug 02 05:54:44 PM PDT 24
Finished Aug 02 05:54:56 PM PDT 24
Peak memory 212908 kb
Host smart-e657d5c2-bd83-4746-bf28-c44df90537b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291236890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1291236890
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2670300261
Short name T227
Test name
Test status
Simulation time 848036958 ps
CPU time 5.82 seconds
Started Aug 02 05:54:41 PM PDT 24
Finished Aug 02 05:54:47 PM PDT 24
Peak memory 212152 kb
Host smart-1a273efb-4369-4057-b00f-891b4f61d569
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2670300261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2670300261
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2114574661
Short name T214
Test name
Test status
Simulation time 140615695 ps
CPU time 6.52 seconds
Started Aug 02 05:54:41 PM PDT 24
Finished Aug 02 05:54:48 PM PDT 24
Peak memory 212216 kb
Host smart-7aeebba7-702c-4e8d-a844-01c889c4d057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114574661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2114574661
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2791973423
Short name T143
Test name
Test status
Simulation time 568096730 ps
CPU time 13.46 seconds
Started Aug 02 05:54:42 PM PDT 24
Finished Aug 02 05:54:55 PM PDT 24
Peak memory 215160 kb
Host smart-a0e0e724-0bc3-47e8-b53f-f29f75d9fa45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791973423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2791973423
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1922736352
Short name T168
Test name
Test status
Simulation time 889850090 ps
CPU time 5.3 seconds
Started Aug 02 05:54:52 PM PDT 24
Finished Aug 02 05:54:57 PM PDT 24
Peak memory 212100 kb
Host smart-ba6c952d-6dd9-4f15-bc5c-dd7039bc8456
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922736352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1922736352
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1130326118
Short name T287
Test name
Test status
Simulation time 5421634535 ps
CPU time 124.24 seconds
Started Aug 02 05:54:47 PM PDT 24
Finished Aug 02 05:56:52 PM PDT 24
Peak memory 225908 kb
Host smart-6e477e21-a7c1-4f0e-9c2d-a7ce34703e57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130326118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1130326118
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.348430395
Short name T274
Test name
Test status
Simulation time 176874620 ps
CPU time 9.87 seconds
Started Aug 02 05:54:54 PM PDT 24
Finished Aug 02 05:55:04 PM PDT 24
Peak memory 212988 kb
Host smart-011634d1-9819-40dc-9de5-7acfec243910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348430395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.348430395
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.442195235
Short name T199
Test name
Test status
Simulation time 2265487484 ps
CPU time 7.06 seconds
Started Aug 02 05:54:53 PM PDT 24
Finished Aug 02 05:55:00 PM PDT 24
Peak memory 212320 kb
Host smart-2af56594-05d3-47b3-8ff2-bd050fdaa9cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=442195235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.442195235
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2648177709
Short name T315
Test name
Test status
Simulation time 294828393 ps
CPU time 6.32 seconds
Started Aug 02 05:54:44 PM PDT 24
Finished Aug 02 05:54:51 PM PDT 24
Peak memory 212172 kb
Host smart-51ee7e6d-9d67-48ae-8112-083f31c41acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648177709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2648177709
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1756782529
Short name T152
Test name
Test status
Simulation time 503452900 ps
CPU time 22.9 seconds
Started Aug 02 05:54:51 PM PDT 24
Finished Aug 02 05:55:14 PM PDT 24
Peak memory 216632 kb
Host smart-3ed217d2-1043-4374-a90c-82798802a849
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756782529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1756782529
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1557680281
Short name T45
Test name
Test status
Simulation time 199016242238 ps
CPU time 1535.51 seconds
Started Aug 02 05:54:52 PM PDT 24
Finished Aug 02 06:20:27 PM PDT 24
Peak memory 236708 kb
Host smart-d734b0ea-4064-4fb2-ac01-0b621a9cc634
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557680281 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.1557680281
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3416228574
Short name T248
Test name
Test status
Simulation time 132735127 ps
CPU time 4.36 seconds
Started Aug 02 05:54:50 PM PDT 24
Finished Aug 02 05:54:54 PM PDT 24
Peak memory 212084 kb
Host smart-fe0e1542-c3ee-4ac3-9e0e-f3b9abf4f3d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416228574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3416228574
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.151223472
Short name T289
Test name
Test status
Simulation time 2052256805 ps
CPU time 126 seconds
Started Aug 02 05:54:48 PM PDT 24
Finished Aug 02 05:56:54 PM PDT 24
Peak memory 234336 kb
Host smart-73d424ee-fbd5-4e4b-91be-10e749a25bd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151223472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.151223472
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2124247366
Short name T296
Test name
Test status
Simulation time 670629808 ps
CPU time 9.49 seconds
Started Aug 02 05:54:50 PM PDT 24
Finished Aug 02 05:55:00 PM PDT 24
Peak memory 213132 kb
Host smart-faab1ce7-36ff-42ae-b319-078d7bfa0487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124247366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2124247366
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3412846227
Short name T95
Test name
Test status
Simulation time 173522859 ps
CPU time 6.36 seconds
Started Aug 02 05:54:51 PM PDT 24
Finished Aug 02 05:54:57 PM PDT 24
Peak memory 212236 kb
Host smart-934f9e98-7f42-42f6-822f-3b0cf1cf144a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3412846227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3412846227
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1626058755
Short name T197
Test name
Test status
Simulation time 134909336 ps
CPU time 6.67 seconds
Started Aug 02 05:54:51 PM PDT 24
Finished Aug 02 05:54:58 PM PDT 24
Peak memory 212196 kb
Host smart-0c352345-e4fd-4fff-b9b3-c26d377f54bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626058755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1626058755
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1711516151
Short name T309
Test name
Test status
Simulation time 862210740 ps
CPU time 8.39 seconds
Started Aug 02 05:54:49 PM PDT 24
Finished Aug 02 05:54:58 PM PDT 24
Peak memory 212156 kb
Host smart-a86d3c95-ecbd-47ba-8683-e1d99aecdfe4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711516151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1711516151
Directory /workspace/9.rom_ctrl_stress_all/latest
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