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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.22 96.89 91.85 97.67 100.00 98.28 97.45 98.37


Total test records in report: 418
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T297 /workspace/coverage/default/17.rom_ctrl_alert_test.3856337032 Aug 03 04:50:18 PM PDT 24 Aug 03 04:50:24 PM PDT 24 128947216 ps
T298 /workspace/coverage/default/21.rom_ctrl_stress_all.4058192876 Aug 03 04:50:25 PM PDT 24 Aug 03 04:50:32 PM PDT 24 175139456 ps
T299 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1642633969 Aug 03 04:50:39 PM PDT 24 Aug 03 04:50:49 PM PDT 24 172285684 ps
T300 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1639723579 Aug 03 04:50:38 PM PDT 24 Aug 03 05:12:56 PM PDT 24 142263623151 ps
T301 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2355886674 Aug 03 04:50:07 PM PDT 24 Aug 03 04:50:14 PM PDT 24 139392581 ps
T302 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2464102337 Aug 03 04:50:55 PM PDT 24 Aug 03 04:51:01 PM PDT 24 376525602 ps
T303 /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.802369370 Aug 03 04:50:54 PM PDT 24 Aug 03 07:10:13 PM PDT 24 41877001782 ps
T304 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2634624645 Aug 03 04:50:47 PM PDT 24 Aug 03 04:52:37 PM PDT 24 6898358749 ps
T305 /workspace/coverage/default/29.rom_ctrl_alert_test.3113909449 Aug 03 04:50:37 PM PDT 24 Aug 03 04:50:43 PM PDT 24 143945117 ps
T306 /workspace/coverage/default/33.rom_ctrl_stress_all.2898621690 Aug 03 04:50:40 PM PDT 24 Aug 03 04:50:47 PM PDT 24 130795836 ps
T307 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3981055047 Aug 03 04:50:36 PM PDT 24 Aug 03 04:50:43 PM PDT 24 148020470 ps
T308 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.829561590 Aug 03 04:50:19 PM PDT 24 Aug 03 04:52:33 PM PDT 24 10194428097 ps
T309 /workspace/coverage/default/36.rom_ctrl_alert_test.1952952411 Aug 03 04:50:49 PM PDT 24 Aug 03 04:50:54 PM PDT 24 127092888 ps
T310 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3974738410 Aug 03 04:50:18 PM PDT 24 Aug 03 04:50:29 PM PDT 24 996671752 ps
T311 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1106241751 Aug 03 04:50:08 PM PDT 24 Aug 03 04:50:20 PM PDT 24 264587597 ps
T312 /workspace/coverage/default/44.rom_ctrl_stress_all.2482592602 Aug 03 04:50:55 PM PDT 24 Aug 03 04:51:11 PM PDT 24 375237237 ps
T313 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2121511660 Aug 03 04:50:41 PM PDT 24 Aug 03 04:52:12 PM PDT 24 6477327208 ps
T314 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2455417706 Aug 03 04:50:59 PM PDT 24 Aug 03 07:11:07 PM PDT 24 110972344816 ps
T315 /workspace/coverage/default/10.rom_ctrl_stress_all.3296436610 Aug 03 04:50:20 PM PDT 24 Aug 03 04:50:41 PM PDT 24 1050989646 ps
T316 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.474455723 Aug 03 04:50:51 PM PDT 24 Aug 03 04:51:44 PM PDT 24 3263351490 ps
T317 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.593165892 Aug 03 04:50:22 PM PDT 24 Aug 03 07:10:45 PM PDT 24 53746693215 ps
T318 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2162550815 Aug 03 04:50:32 PM PDT 24 Aug 03 04:50:39 PM PDT 24 564614985 ps
T319 /workspace/coverage/default/19.rom_ctrl_alert_test.3261580855 Aug 03 04:50:27 PM PDT 24 Aug 03 04:50:32 PM PDT 24 132850593 ps
T320 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.352514585 Aug 03 04:50:52 PM PDT 24 Aug 03 04:50:58 PM PDT 24 271096862 ps
T321 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3706707532 Aug 03 04:50:34 PM PDT 24 Aug 03 04:50:45 PM PDT 24 257348426 ps
T322 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1700300012 Aug 03 04:50:59 PM PDT 24 Aug 03 04:52:34 PM PDT 24 9598904230 ps
T323 /workspace/coverage/default/27.rom_ctrl_stress_all.1247277084 Aug 03 04:50:35 PM PDT 24 Aug 03 04:50:56 PM PDT 24 2801672636 ps
T324 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4232411377 Aug 03 04:50:06 PM PDT 24 Aug 03 04:50:18 PM PDT 24 925524921 ps
T325 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2552463916 Aug 03 04:50:19 PM PDT 24 Aug 03 04:52:23 PM PDT 24 4229038176 ps
T326 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3810848104 Aug 03 04:50:18 PM PDT 24 Aug 03 04:52:11 PM PDT 24 25353087640 ps
T327 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3364419518 Aug 03 04:51:01 PM PDT 24 Aug 03 04:51:08 PM PDT 24 556317216 ps
T328 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2483580168 Aug 03 04:50:19 PM PDT 24 Aug 03 04:50:25 PM PDT 24 181682774 ps
T329 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.639206382 Aug 03 04:51:00 PM PDT 24 Aug 03 04:51:07 PM PDT 24 564028251 ps
T330 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1220482338 Aug 03 04:50:16 PM PDT 24 Aug 03 04:50:28 PM PDT 24 803152208 ps
T331 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3945194628 Aug 03 04:50:40 PM PDT 24 Aug 03 04:50:51 PM PDT 24 1465432046 ps
T332 /workspace/coverage/default/17.rom_ctrl_stress_all.727676715 Aug 03 04:50:21 PM PDT 24 Aug 03 04:50:28 PM PDT 24 112819394 ps
T61 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2866498663 Aug 03 04:35:58 PM PDT 24 Aug 03 04:36:03 PM PDT 24 127196752 ps
T62 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1912442960 Aug 03 04:35:57 PM PDT 24 Aug 03 04:36:02 PM PDT 24 108321859 ps
T63 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.384295187 Aug 03 04:36:05 PM PDT 24 Aug 03 04:36:32 PM PDT 24 1099878725 ps
T333 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3364030782 Aug 03 04:36:00 PM PDT 24 Aug 03 04:36:07 PM PDT 24 309591887 ps
T102 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1080702730 Aug 03 04:35:56 PM PDT 24 Aug 03 04:36:01 PM PDT 24 162267233 ps
T103 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.255025772 Aug 03 04:35:57 PM PDT 24 Aug 03 04:36:02 PM PDT 24 252073454 ps
T58 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.511167056 Aug 03 04:35:42 PM PDT 24 Aug 03 04:36:52 PM PDT 24 270138028 ps
T68 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2919977663 Aug 03 04:36:01 PM PDT 24 Aug 03 04:36:20 PM PDT 24 729657183 ps
T104 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.313316203 Aug 03 04:35:55 PM PDT 24 Aug 03 04:36:00 PM PDT 24 256498880 ps
T59 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2854134906 Aug 03 04:35:50 PM PDT 24 Aug 03 04:36:26 PM PDT 24 592645788 ps
T69 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3547452274 Aug 03 04:36:03 PM PDT 24 Aug 03 04:36:08 PM PDT 24 201778157 ps
T60 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2233201679 Aug 03 04:35:46 PM PDT 24 Aug 03 04:36:23 PM PDT 24 179445749 ps
T334 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2758350737 Aug 03 04:36:04 PM PDT 24 Aug 03 04:36:12 PM PDT 24 333693776 ps
T110 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4183492079 Aug 03 04:35:49 PM PDT 24 Aug 03 04:35:55 PM PDT 24 327997333 ps
T335 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3861362991 Aug 03 04:35:47 PM PDT 24 Aug 03 04:35:54 PM PDT 24 297010242 ps
T111 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1508877289 Aug 03 04:35:51 PM PDT 24 Aug 03 04:35:56 PM PDT 24 126806102 ps
T70 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1519492673 Aug 03 04:35:49 PM PDT 24 Aug 03 04:35:55 PM PDT 24 127121510 ps
T71 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1924544948 Aug 03 04:36:08 PM PDT 24 Aug 03 04:36:13 PM PDT 24 127854441 ps
T336 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2086166630 Aug 03 04:36:02 PM PDT 24 Aug 03 04:36:09 PM PDT 24 85485515 ps
T337 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2844494914 Aug 03 04:35:55 PM PDT 24 Aug 03 04:36:02 PM PDT 24 511951569 ps
T338 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2741358087 Aug 03 04:35:50 PM PDT 24 Aug 03 04:35:56 PM PDT 24 138250804 ps
T339 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3314132904 Aug 03 04:35:54 PM PDT 24 Aug 03 04:35:59 PM PDT 24 811894574 ps
T340 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1131873379 Aug 03 04:35:53 PM PDT 24 Aug 03 04:35:58 PM PDT 24 348423625 ps
T72 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.164257027 Aug 03 04:35:49 PM PDT 24 Aug 03 04:35:55 PM PDT 24 97252564 ps
T341 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1503549532 Aug 03 04:36:02 PM PDT 24 Aug 03 04:36:08 PM PDT 24 1777111493 ps
T117 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2806436229 Aug 03 04:35:56 PM PDT 24 Aug 03 04:36:34 PM PDT 24 2444358265 ps
T342 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.557920399 Aug 03 04:35:58 PM PDT 24 Aug 03 04:36:04 PM PDT 24 144270908 ps
T343 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.927009785 Aug 03 04:36:01 PM PDT 24 Aug 03 04:36:08 PM PDT 24 117869777 ps
T123 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4201409467 Aug 03 04:35:57 PM PDT 24 Aug 03 04:36:34 PM PDT 24 447326184 ps
T73 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2890357659 Aug 03 04:35:55 PM PDT 24 Aug 03 04:36:00 PM PDT 24 348095113 ps
T344 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2787834266 Aug 03 04:35:45 PM PDT 24 Aug 03 04:35:50 PM PDT 24 346405807 ps
T345 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1485072717 Aug 03 04:35:44 PM PDT 24 Aug 03 04:36:03 PM PDT 24 736910653 ps
T105 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2459372841 Aug 03 04:35:55 PM PDT 24 Aug 03 04:36:01 PM PDT 24 128675208 ps
T74 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2956195156 Aug 03 04:35:48 PM PDT 24 Aug 03 04:35:53 PM PDT 24 132235985 ps
T118 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.626568699 Aug 03 04:35:49 PM PDT 24 Aug 03 04:36:55 PM PDT 24 837091356 ps
T346 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.283321527 Aug 03 04:35:49 PM PDT 24 Aug 03 04:35:55 PM PDT 24 127079594 ps
T347 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3430427966 Aug 03 04:35:49 PM PDT 24 Aug 03 04:35:56 PM PDT 24 147074531 ps
T348 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.51486559 Aug 03 04:36:03 PM PDT 24 Aug 03 04:36:10 PM PDT 24 256304165 ps
T349 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.758456714 Aug 03 04:35:41 PM PDT 24 Aug 03 04:35:46 PM PDT 24 363902162 ps
T350 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3879459125 Aug 03 04:35:50 PM PDT 24 Aug 03 04:35:55 PM PDT 24 132465739 ps
T75 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1110783353 Aug 03 04:36:01 PM PDT 24 Aug 03 04:36:20 PM PDT 24 3209393808 ps
T351 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1266286377 Aug 03 04:36:01 PM PDT 24 Aug 03 04:36:10 PM PDT 24 503970885 ps
T76 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1720740336 Aug 03 04:36:01 PM PDT 24 Aug 03 04:36:05 PM PDT 24 347012362 ps
T352 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1315562745 Aug 03 04:35:51 PM PDT 24 Aug 03 04:35:56 PM PDT 24 118927215 ps
T106 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3243771620 Aug 03 04:35:52 PM PDT 24 Aug 03 04:35:56 PM PDT 24 556075887 ps
T126 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3140400241 Aug 03 04:36:08 PM PDT 24 Aug 03 04:37:18 PM PDT 24 504196769 ps
T120 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1139509436 Aug 03 04:35:51 PM PDT 24 Aug 03 04:36:59 PM PDT 24 971461776 ps
T353 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.969956859 Aug 03 04:35:48 PM PDT 24 Aug 03 04:35:52 PM PDT 24 89459843 ps
T354 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.758094758 Aug 03 04:35:38 PM PDT 24 Aug 03 04:35:43 PM PDT 24 498950276 ps
T83 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.768531373 Aug 03 04:36:00 PM PDT 24 Aug 03 04:36:05 PM PDT 24 363251495 ps
T122 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1737840289 Aug 03 04:36:03 PM PDT 24 Aug 03 04:36:41 PM PDT 24 399361590 ps
T124 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4055638949 Aug 03 04:35:58 PM PDT 24 Aug 03 04:37:09 PM PDT 24 1060664207 ps
T355 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2859083416 Aug 03 04:36:03 PM PDT 24 Aug 03 04:36:40 PM PDT 24 189557028 ps
T84 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3511584563 Aug 03 04:35:54 PM PDT 24 Aug 03 04:35:59 PM PDT 24 622025224 ps
T356 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2081183592 Aug 03 04:36:01 PM PDT 24 Aug 03 04:36:06 PM PDT 24 90204901 ps
T357 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1327002921 Aug 03 04:36:06 PM PDT 24 Aug 03 04:36:11 PM PDT 24 261257692 ps
T107 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2586903318 Aug 03 04:35:43 PM PDT 24 Aug 03 04:35:48 PM PDT 24 336216629 ps
T108 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1552123615 Aug 03 04:35:53 PM PDT 24 Aug 03 04:35:58 PM PDT 24 87997770 ps
T358 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1569204855 Aug 03 04:35:50 PM PDT 24 Aug 03 04:35:55 PM PDT 24 499083500 ps
T359 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2406275253 Aug 03 04:35:47 PM PDT 24 Aug 03 04:35:52 PM PDT 24 255091924 ps
T360 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.478530695 Aug 03 04:35:49 PM PDT 24 Aug 03 04:36:07 PM PDT 24 1820490932 ps
T361 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.397792834 Aug 03 04:35:49 PM PDT 24 Aug 03 04:35:57 PM PDT 24 1130485973 ps
T121 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3515795176 Aug 03 04:35:50 PM PDT 24 Aug 03 04:36:58 PM PDT 24 997972417 ps
T362 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1368978777 Aug 03 04:36:05 PM PDT 24 Aug 03 04:36:12 PM PDT 24 347186805 ps
T363 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.132461280 Aug 03 04:35:54 PM PDT 24 Aug 03 04:36:00 PM PDT 24 1132989431 ps
T364 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4282840051 Aug 03 04:35:58 PM PDT 24 Aug 03 04:36:03 PM PDT 24 126135277 ps
T365 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3310963552 Aug 03 04:35:58 PM PDT 24 Aug 03 04:36:03 PM PDT 24 132838428 ps
T85 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2271103231 Aug 03 04:35:56 PM PDT 24 Aug 03 04:36:14 PM PDT 24 375426750 ps
T366 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.396653042 Aug 03 04:35:46 PM PDT 24 Aug 03 04:35:51 PM PDT 24 333891299 ps
T367 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1097680496 Aug 03 04:35:50 PM PDT 24 Aug 03 04:35:55 PM PDT 24 498687000 ps
T368 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2379578931 Aug 03 04:35:48 PM PDT 24 Aug 03 04:35:58 PM PDT 24 533064023 ps
T125 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1648392242 Aug 03 04:35:48 PM PDT 24 Aug 03 04:36:24 PM PDT 24 730610396 ps
T369 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1366880331 Aug 03 04:35:57 PM PDT 24 Aug 03 04:36:03 PM PDT 24 141842238 ps
T370 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1474548326 Aug 03 04:35:54 PM PDT 24 Aug 03 04:35:59 PM PDT 24 257475788 ps
T371 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2266301039 Aug 03 04:35:59 PM PDT 24 Aug 03 04:36:06 PM PDT 24 302047576 ps
T372 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.22705172 Aug 03 04:35:55 PM PDT 24 Aug 03 04:36:02 PM PDT 24 85873524 ps
T373 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3344857720 Aug 03 04:35:55 PM PDT 24 Aug 03 04:36:00 PM PDT 24 370789594 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.160663668 Aug 03 04:35:55 PM PDT 24 Aug 03 04:37:04 PM PDT 24 990201674 ps
T119 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.609129506 Aug 03 04:35:52 PM PDT 24 Aug 03 04:37:02 PM PDT 24 597909930 ps
T86 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3811592702 Aug 03 04:35:55 PM PDT 24 Aug 03 04:36:00 PM PDT 24 329466699 ps
T375 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1320837877 Aug 03 04:35:54 PM PDT 24 Aug 03 04:35:59 PM PDT 24 300334620 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3148280073 Aug 03 04:35:55 PM PDT 24 Aug 03 04:36:00 PM PDT 24 85474137 ps
T377 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3282694978 Aug 03 04:35:42 PM PDT 24 Aug 03 04:36:51 PM PDT 24 1022729010 ps
T87 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2513461249 Aug 03 04:36:01 PM PDT 24 Aug 03 04:36:19 PM PDT 24 854655166 ps
T378 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2096796324 Aug 03 04:36:04 PM PDT 24 Aug 03 04:37:14 PM PDT 24 289675294 ps
T379 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3457855012 Aug 03 04:35:59 PM PDT 24 Aug 03 04:36:03 PM PDT 24 90057450 ps
T380 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1586615030 Aug 03 04:35:52 PM PDT 24 Aug 03 04:36:01 PM PDT 24 126737932 ps
T381 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.312065911 Aug 03 04:35:47 PM PDT 24 Aug 03 04:35:52 PM PDT 24 249881301 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3396858673 Aug 03 04:35:51 PM PDT 24 Aug 03 04:36:00 PM PDT 24 560341818 ps
T383 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3444270914 Aug 03 04:35:59 PM PDT 24 Aug 03 04:36:05 PM PDT 24 87110612 ps
T384 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2241125591 Aug 03 04:36:02 PM PDT 24 Aug 03 04:36:08 PM PDT 24 556576375 ps
T385 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1350334247 Aug 03 04:35:45 PM PDT 24 Aug 03 04:35:49 PM PDT 24 168659153 ps
T386 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1883835346 Aug 03 04:36:00 PM PDT 24 Aug 03 04:36:09 PM PDT 24 569201207 ps
T387 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.903538558 Aug 03 04:35:51 PM PDT 24 Aug 03 04:35:58 PM PDT 24 87548308 ps
T388 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2877286010 Aug 03 04:35:51 PM PDT 24 Aug 03 04:36:59 PM PDT 24 1037802962 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1538236255 Aug 03 04:35:45 PM PDT 24 Aug 03 04:35:55 PM PDT 24 154040069 ps
T390 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1910114430 Aug 03 04:35:43 PM PDT 24 Aug 03 04:35:52 PM PDT 24 1013974216 ps
T391 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4261447992 Aug 03 04:35:54 PM PDT 24 Aug 03 04:35:59 PM PDT 24 416943957 ps
T88 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2793746773 Aug 03 04:35:53 PM PDT 24 Aug 03 04:35:57 PM PDT 24 175199399 ps
T392 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3730095492 Aug 03 04:35:52 PM PDT 24 Aug 03 04:35:58 PM PDT 24 86036915 ps
T92 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3592887799 Aug 03 04:35:53 PM PDT 24 Aug 03 04:35:57 PM PDT 24 462573711 ps
T393 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.449803806 Aug 03 04:35:55 PM PDT 24 Aug 03 04:36:01 PM PDT 24 261559065 ps
T394 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2148453570 Aug 03 04:35:50 PM PDT 24 Aug 03 04:35:55 PM PDT 24 172270049 ps
T395 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.525005554 Aug 03 04:35:57 PM PDT 24 Aug 03 04:36:01 PM PDT 24 219819778 ps
T396 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1350941847 Aug 03 04:35:49 PM PDT 24 Aug 03 04:35:53 PM PDT 24 86394581 ps
T397 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.813791286 Aug 03 04:35:48 PM PDT 24 Aug 03 04:35:55 PM PDT 24 283409516 ps
T398 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1719125224 Aug 03 04:35:49 PM PDT 24 Aug 03 04:35:54 PM PDT 24 129017797 ps
T399 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4003240931 Aug 03 04:36:05 PM PDT 24 Aug 03 04:36:10 PM PDT 24 137739186 ps
T89 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2694767668 Aug 03 04:35:55 PM PDT 24 Aug 03 04:36:00 PM PDT 24 146576510 ps
T400 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.587227545 Aug 03 04:35:48 PM PDT 24 Aug 03 04:35:55 PM PDT 24 298309230 ps
T401 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1418534993 Aug 03 04:35:53 PM PDT 24 Aug 03 04:36:00 PM PDT 24 560563785 ps
T402 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2757123346 Aug 03 04:35:41 PM PDT 24 Aug 03 04:35:46 PM PDT 24 1551935670 ps
T403 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4099411938 Aug 03 04:35:47 PM PDT 24 Aug 03 04:35:51 PM PDT 24 162118435 ps
T404 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.122537532 Aug 03 04:36:01 PM PDT 24 Aug 03 04:36:08 PM PDT 24 141599369 ps
T405 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.32436575 Aug 03 04:35:47 PM PDT 24 Aug 03 04:35:52 PM PDT 24 523451814 ps
T406 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.754023915 Aug 03 04:35:58 PM PDT 24 Aug 03 04:36:03 PM PDT 24 209666872 ps
T407 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3934301539 Aug 03 04:35:53 PM PDT 24 Aug 03 04:35:57 PM PDT 24 174997836 ps
T408 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.114168381 Aug 03 04:35:48 PM PDT 24 Aug 03 04:35:54 PM PDT 24 91228947 ps
T409 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1330268180 Aug 03 04:36:00 PM PDT 24 Aug 03 04:36:04 PM PDT 24 346541363 ps
T410 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1072732546 Aug 03 04:35:58 PM PDT 24 Aug 03 04:36:06 PM PDT 24 250189922 ps
T411 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.690811638 Aug 03 04:35:51 PM PDT 24 Aug 03 04:35:59 PM PDT 24 2055342656 ps
T90 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.510898738 Aug 03 04:36:01 PM PDT 24 Aug 03 04:36:06 PM PDT 24 450222591 ps
T127 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2404895721 Aug 03 04:35:53 PM PDT 24 Aug 03 04:37:01 PM PDT 24 1004646499 ps
T412 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2492533735 Aug 03 04:35:44 PM PDT 24 Aug 03 04:35:50 PM PDT 24 446943787 ps
T413 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3161743446 Aug 03 04:35:55 PM PDT 24 Aug 03 04:36:00 PM PDT 24 288093390 ps
T414 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.922789666 Aug 03 04:35:38 PM PDT 24 Aug 03 04:35:44 PM PDT 24 262005515 ps
T128 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4175195927 Aug 03 04:36:00 PM PDT 24 Aug 03 04:36:38 PM PDT 24 1062867420 ps
T415 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1116925654 Aug 03 04:35:38 PM PDT 24 Aug 03 04:35:42 PM PDT 24 171407611 ps
T91 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.699300217 Aug 03 04:35:49 PM PDT 24 Aug 03 04:35:57 PM PDT 24 1957742236 ps
T416 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2141175077 Aug 03 04:36:01 PM PDT 24 Aug 03 04:36:06 PM PDT 24 190114281 ps
T417 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.245633090 Aug 03 04:35:58 PM PDT 24 Aug 03 04:36:05 PM PDT 24 311651583 ps
T418 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4113282548 Aug 03 04:35:45 PM PDT 24 Aug 03 04:35:50 PM PDT 24 132203625 ps

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.150069956
Short name T4
Test name
Test status
Simulation time 14705450947 ps
CPU time 139.29 seconds
Started Aug 03 04:50:52 PM PDT 24
Finished Aug 03 04:53:11 PM PDT 24
Peak memory 214544 kb
Host smart-ce964b0f-80aa-4cea-a6c1-363b8869c20b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150069956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.150069956
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3222123983
Short name T13
Test name
Test status
Simulation time 381492635283 ps
CPU time 892.68 seconds
Started Aug 03 04:50:04 PM PDT 24
Finished Aug 03 05:04:57 PM PDT 24
Peak memory 236528 kb
Host smart-a818acc5-8243-4af0-bebd-870190e95854
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222123983 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.3222123983
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2087893567
Short name T6
Test name
Test status
Simulation time 2424724771 ps
CPU time 151.23 seconds
Started Aug 03 04:50:02 PM PDT 24
Finished Aug 03 04:52:33 PM PDT 24
Peak memory 229244 kb
Host smart-a389a274-77a2-4dc3-8565-42b8799c15a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087893567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2087893567
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1253075454
Short name T46
Test name
Test status
Simulation time 15102986878 ps
CPU time 137.88 seconds
Started Aug 03 04:50:23 PM PDT 24
Finished Aug 03 04:52:41 PM PDT 24
Peak memory 229164 kb
Host smart-46d5df62-e8d5-415b-823b-69863476429a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253075454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1253075454
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2233201679
Short name T60
Test name
Test status
Simulation time 179445749 ps
CPU time 36.87 seconds
Started Aug 03 04:35:46 PM PDT 24
Finished Aug 03 04:36:23 PM PDT 24
Peak memory 212004 kb
Host smart-a91026e6-302d-4119-be23-c536a4723f5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233201679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2233201679
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.283088525
Short name T11
Test name
Test status
Simulation time 1110624050 ps
CPU time 23.91 seconds
Started Aug 03 04:50:01 PM PDT 24
Finished Aug 03 04:50:25 PM PDT 24
Peak memory 216220 kb
Host smart-b0b8ef50-6024-427a-85e6-f015a052f670
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283088525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.283088525
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.10564135
Short name T20
Test name
Test status
Simulation time 365097534 ps
CPU time 102.67 seconds
Started Aug 03 04:50:01 PM PDT 24
Finished Aug 03 04:51:44 PM PDT 24
Peak memory 237100 kb
Host smart-0d3ae605-4e6d-4bb1-bfef-b955a90007cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10564135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.10564135
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.384295187
Short name T63
Test name
Test status
Simulation time 1099878725 ps
CPU time 27.13 seconds
Started Aug 03 04:36:05 PM PDT 24
Finished Aug 03 04:36:32 PM PDT 24
Peak memory 211380 kb
Host smart-54fa2b10-6d03-45b3-8f63-1d24fccae0fe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384295187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.384295187
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1139509436
Short name T120
Test name
Test status
Simulation time 971461776 ps
CPU time 68.61 seconds
Started Aug 03 04:35:51 PM PDT 24
Finished Aug 03 04:36:59 PM PDT 24
Peak memory 213176 kb
Host smart-36df0409-3b59-432f-a290-26d2134e6514
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139509436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1139509436
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3073999233
Short name T24
Test name
Test status
Simulation time 1006679532 ps
CPU time 16.22 seconds
Started Aug 03 04:50:16 PM PDT 24
Finished Aug 03 04:50:33 PM PDT 24
Peak memory 212892 kb
Host smart-53a74baa-afca-4a97-a3da-807ef5dc8fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073999233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3073999233
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3561033495
Short name T23
Test name
Test status
Simulation time 90164843 ps
CPU time 4.38 seconds
Started Aug 03 04:50:04 PM PDT 24
Finished Aug 03 04:50:09 PM PDT 24
Peak memory 211976 kb
Host smart-05afb6a3-57bc-4034-8d12-a595f4802f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561033495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3561033495
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.761236835
Short name T200
Test name
Test status
Simulation time 6602658219 ps
CPU time 16.36 seconds
Started Aug 03 04:50:28 PM PDT 24
Finished Aug 03 04:50:45 PM PDT 24
Peak memory 213568 kb
Host smart-fd181eab-ac6b-4371-b359-32c8d8ca699f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761236835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.761236835
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1648392242
Short name T125
Test name
Test status
Simulation time 730610396 ps
CPU time 36.62 seconds
Started Aug 03 04:35:48 PM PDT 24
Finished Aug 03 04:36:24 PM PDT 24
Peak memory 211852 kb
Host smart-8b042f1e-6d6c-4d29-b40c-5d3285b9ddbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648392242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1648392242
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3640707743
Short name T14
Test name
Test status
Simulation time 164702682353 ps
CPU time 3073.28 seconds
Started Aug 03 04:50:38 PM PDT 24
Finished Aug 03 05:41:52 PM PDT 24
Peak memory 253016 kb
Host smart-abc5d815-d654-462d-a457-58d130240405
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640707743 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.3640707743
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.397860755
Short name T16
Test name
Test status
Simulation time 6242436919 ps
CPU time 133.64 seconds
Started Aug 03 04:50:06 PM PDT 24
Finished Aug 03 04:52:20 PM PDT 24
Peak memory 213768 kb
Host smart-6c4cb175-e7c0-4912-986c-906885f568b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397860755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.397860755
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.699300217
Short name T91
Test name
Test status
Simulation time 1957742236 ps
CPU time 7.82 seconds
Started Aug 03 04:35:49 PM PDT 24
Finished Aug 03 04:35:57 PM PDT 24
Peak memory 218372 kb
Host smart-b4280d84-2963-4981-aca0-a6a800a5b515
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699300217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.699300217
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.626568699
Short name T118
Test name
Test status
Simulation time 837091356 ps
CPU time 66.71 seconds
Started Aug 03 04:35:49 PM PDT 24
Finished Aug 03 04:36:55 PM PDT 24
Peak memory 213056 kb
Host smart-34e3a016-b07d-4a75-9a07-87d09d76a9a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626568699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.626568699
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2586903318
Short name T107
Test name
Test status
Simulation time 336216629 ps
CPU time 4.43 seconds
Started Aug 03 04:35:43 PM PDT 24
Finished Aug 03 04:35:48 PM PDT 24
Peak memory 219496 kb
Host smart-f0569e37-c382-4900-98b1-8a67889d7216
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586903318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2586903318
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2287695413
Short name T93
Test name
Test status
Simulation time 797248038 ps
CPU time 6.87 seconds
Started Aug 03 04:50:55 PM PDT 24
Finished Aug 03 04:51:02 PM PDT 24
Peak memory 212024 kb
Host smart-6227b14b-5a01-447f-acab-afac1445ff2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2287695413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2287695413
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1116925654
Short name T415
Test name
Test status
Simulation time 171407611 ps
CPU time 4.07 seconds
Started Aug 03 04:35:38 PM PDT 24
Finished Aug 03 04:35:42 PM PDT 24
Peak memory 217812 kb
Host smart-57e6aafb-f3c9-40dd-a9c4-45caf414ec39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116925654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1116925654
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.922789666
Short name T414
Test name
Test status
Simulation time 262005515 ps
CPU time 6.38 seconds
Started Aug 03 04:35:38 PM PDT 24
Finished Aug 03 04:35:44 PM PDT 24
Peak memory 219168 kb
Host smart-bd9263ac-1985-4c80-b362-946c003f5ff9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922789666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.922789666
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3861362991
Short name T335
Test name
Test status
Simulation time 297010242 ps
CPU time 7.25 seconds
Started Aug 03 04:35:47 PM PDT 24
Finished Aug 03 04:35:54 PM PDT 24
Peak memory 219492 kb
Host smart-88fbb775-e94a-433b-b082-d17570666102
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861362991 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3861362991
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1350941847
Short name T396
Test name
Test status
Simulation time 86394581 ps
CPU time 4.2 seconds
Started Aug 03 04:35:49 PM PDT 24
Finished Aug 03 04:35:53 PM PDT 24
Peak memory 219408 kb
Host smart-b6214aa1-44fe-400e-af92-cd74770167bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350941847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1350941847
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.758094758
Short name T354
Test name
Test status
Simulation time 498950276 ps
CPU time 4.95 seconds
Started Aug 03 04:35:38 PM PDT 24
Finished Aug 03 04:35:43 PM PDT 24
Peak memory 211200 kb
Host smart-c944fc69-21ee-4d44-81f3-a2fcff760d54
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758094758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.758094758
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2757123346
Short name T402
Test name
Test status
Simulation time 1551935670 ps
CPU time 5.03 seconds
Started Aug 03 04:35:41 PM PDT 24
Finished Aug 03 04:35:46 PM PDT 24
Peak memory 211124 kb
Host smart-2098ca6f-eb5a-4cae-866b-43cee214398b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757123346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2757123346
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1538236255
Short name T389
Test name
Test status
Simulation time 154040069 ps
CPU time 9.91 seconds
Started Aug 03 04:35:45 PM PDT 24
Finished Aug 03 04:35:55 PM PDT 24
Peak memory 219532 kb
Host smart-cdddaf93-6609-4603-9b10-dfbcf10bc583
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538236255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1538236255
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3282694978
Short name T377
Test name
Test status
Simulation time 1022729010 ps
CPU time 68.64 seconds
Started Aug 03 04:35:42 PM PDT 24
Finished Aug 03 04:36:51 PM PDT 24
Peak memory 219508 kb
Host smart-05c865ad-080f-4440-9217-e8e6451b8b99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282694978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3282694978
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1097680496
Short name T367
Test name
Test status
Simulation time 498687000 ps
CPU time 4.87 seconds
Started Aug 03 04:35:50 PM PDT 24
Finished Aug 03 04:35:55 PM PDT 24
Peak memory 211216 kb
Host smart-7e1e8ca5-a6ba-4130-8720-ffc350d508f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097680496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1097680496
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.283321527
Short name T346
Test name
Test status
Simulation time 127079594 ps
CPU time 5.96 seconds
Started Aug 03 04:35:49 PM PDT 24
Finished Aug 03 04:35:55 PM PDT 24
Peak memory 211208 kb
Host smart-b99684e6-b78f-4ccd-a12f-98b9e8c4721d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283321527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.283321527
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2844494914
Short name T337
Test name
Test status
Simulation time 511951569 ps
CPU time 6.86 seconds
Started Aug 03 04:35:55 PM PDT 24
Finished Aug 03 04:36:02 PM PDT 24
Peak memory 211180 kb
Host smart-11d7d080-6e63-43eb-82e4-74ac968b3dc6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844494914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2844494914
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2492533735
Short name T412
Test name
Test status
Simulation time 446943787 ps
CPU time 5.45 seconds
Started Aug 03 04:35:44 PM PDT 24
Finished Aug 03 04:35:50 PM PDT 24
Peak memory 219604 kb
Host smart-f33de98d-8900-43be-9bde-3341e2608e48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492533735 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2492533735
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4113282548
Short name T418
Test name
Test status
Simulation time 132203625 ps
CPU time 5.08 seconds
Started Aug 03 04:35:45 PM PDT 24
Finished Aug 03 04:35:50 PM PDT 24
Peak memory 211148 kb
Host smart-9d317478-97d5-47d0-8c41-63ffbd9e6103
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113282548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4113282548
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.969956859
Short name T353
Test name
Test status
Simulation time 89459843 ps
CPU time 4.17 seconds
Started Aug 03 04:35:48 PM PDT 24
Finished Aug 03 04:35:52 PM PDT 24
Peak memory 211148 kb
Host smart-5d1225ea-6d9f-4e5f-8aaf-903c15e072c4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969956859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.969956859
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.525005554
Short name T395
Test name
Test status
Simulation time 219819778 ps
CPU time 4.06 seconds
Started Aug 03 04:35:57 PM PDT 24
Finished Aug 03 04:36:01 PM PDT 24
Peak memory 211180 kb
Host smart-778b4154-4b04-4142-b7bd-a558284e76ff
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525005554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
525005554
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.32436575
Short name T405
Test name
Test status
Simulation time 523451814 ps
CPU time 4.17 seconds
Started Aug 03 04:35:47 PM PDT 24
Finished Aug 03 04:35:52 PM PDT 24
Peak memory 211236 kb
Host smart-8a5b096c-9119-44c7-a8df-31c797d75f10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32436575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_same_csr_outstanding.32436575
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1910114430
Short name T390
Test name
Test status
Simulation time 1013974216 ps
CPU time 8.93 seconds
Started Aug 03 04:35:43 PM PDT 24
Finished Aug 03 04:35:52 PM PDT 24
Peak memory 219564 kb
Host smart-0e213af5-c767-4216-b1b6-d70f88265a38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910114430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1910114430
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.557920399
Short name T342
Test name
Test status
Simulation time 144270908 ps
CPU time 5.68 seconds
Started Aug 03 04:35:58 PM PDT 24
Finished Aug 03 04:36:04 PM PDT 24
Peak memory 215076 kb
Host smart-bf9670a6-5960-4f9f-95fe-ad495ee57f12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557920399 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.557920399
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3811592702
Short name T86
Test name
Test status
Simulation time 329466699 ps
CPU time 5.18 seconds
Started Aug 03 04:35:55 PM PDT 24
Finished Aug 03 04:36:00 PM PDT 24
Peak memory 211320 kb
Host smart-498b9ee4-e886-4e14-988e-d739bbc0917c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811592702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3811592702
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2379578931
Short name T368
Test name
Test status
Simulation time 533064023 ps
CPU time 9.12 seconds
Started Aug 03 04:35:48 PM PDT 24
Finished Aug 03 04:35:58 PM PDT 24
Peak memory 211364 kb
Host smart-c35b526d-3739-4214-924f-5f42872eea57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379578931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2379578931
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.397792834
Short name T361
Test name
Test status
Simulation time 1130485973 ps
CPU time 6.9 seconds
Started Aug 03 04:35:49 PM PDT 24
Finished Aug 03 04:35:57 PM PDT 24
Peak memory 219640 kb
Host smart-e66f3933-0461-485c-a506-c7f134b731bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397792834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.397792834
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1737840289
Short name T122
Test name
Test status
Simulation time 399361590 ps
CPU time 37.52 seconds
Started Aug 03 04:36:03 PM PDT 24
Finished Aug 03 04:36:41 PM PDT 24
Peak memory 212864 kb
Host smart-c940f962-ed6c-4aba-90ee-f00d44bb9670
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737840289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1737840289
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4003240931
Short name T399
Test name
Test status
Simulation time 137739186 ps
CPU time 5.25 seconds
Started Aug 03 04:36:05 PM PDT 24
Finished Aug 03 04:36:10 PM PDT 24
Peak memory 214752 kb
Host smart-95a2efd7-7370-4e58-9e17-70eeafb2f447
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003240931 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4003240931
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3161743446
Short name T413
Test name
Test status
Simulation time 288093390 ps
CPU time 4.39 seconds
Started Aug 03 04:35:55 PM PDT 24
Finished Aug 03 04:36:00 PM PDT 24
Peak memory 217900 kb
Host smart-05eaea2d-1586-40db-a09d-4ba107c4f1d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161743446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3161743446
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2271103231
Short name T85
Test name
Test status
Simulation time 375426750 ps
CPU time 18.04 seconds
Started Aug 03 04:35:56 PM PDT 24
Finished Aug 03 04:36:14 PM PDT 24
Peak memory 211308 kb
Host smart-c4cb9d00-9ee4-4b2d-9111-a004a9813a35
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271103231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2271103231
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.255025772
Short name T103
Test name
Test status
Simulation time 252073454 ps
CPU time 5.08 seconds
Started Aug 03 04:35:57 PM PDT 24
Finished Aug 03 04:36:02 PM PDT 24
Peak memory 218232 kb
Host smart-1cf554d8-ec87-4cdd-8cf9-cd4c0c3d4321
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255025772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.255025772
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3730095492
Short name T392
Test name
Test status
Simulation time 86036915 ps
CPU time 6.82 seconds
Started Aug 03 04:35:52 PM PDT 24
Finished Aug 03 04:35:58 PM PDT 24
Peak memory 216244 kb
Host smart-820dbc10-4797-476a-b570-264338641349
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730095492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3730095492
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.587227545
Short name T400
Test name
Test status
Simulation time 298309230 ps
CPU time 6.31 seconds
Started Aug 03 04:35:48 PM PDT 24
Finished Aug 03 04:35:55 PM PDT 24
Peak memory 219592 kb
Host smart-9fa45123-bb83-4213-9814-f249453fc4cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587227545 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.587227545
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1519492673
Short name T70
Test name
Test status
Simulation time 127121510 ps
CPU time 5.07 seconds
Started Aug 03 04:35:49 PM PDT 24
Finished Aug 03 04:35:55 PM PDT 24
Peak memory 211304 kb
Host smart-9c0ad88c-82eb-4334-95c0-fa4d447f639e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519492673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1519492673
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.478530695
Short name T360
Test name
Test status
Simulation time 1820490932 ps
CPU time 18.5 seconds
Started Aug 03 04:35:49 PM PDT 24
Finished Aug 03 04:36:07 PM PDT 24
Peak memory 211268 kb
Host smart-a6d084cd-13eb-456d-89b5-051ead5ccaed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478530695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.478530695
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3243771620
Short name T106
Test name
Test status
Simulation time 556075887 ps
CPU time 4.26 seconds
Started Aug 03 04:35:52 PM PDT 24
Finished Aug 03 04:35:56 PM PDT 24
Peak memory 218764 kb
Host smart-392c92ef-7b77-4eef-8a23-8131991bf5a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243771620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3243771620
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1883835346
Short name T386
Test name
Test status
Simulation time 569201207 ps
CPU time 9.26 seconds
Started Aug 03 04:36:00 PM PDT 24
Finished Aug 03 04:36:09 PM PDT 24
Peak memory 216420 kb
Host smart-e45160fa-b265-4d0b-948d-8181fe9cb829
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883835346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1883835346
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3515795176
Short name T121
Test name
Test status
Simulation time 997972417 ps
CPU time 68.47 seconds
Started Aug 03 04:35:50 PM PDT 24
Finished Aug 03 04:36:58 PM PDT 24
Peak memory 219368 kb
Host smart-b1070cef-f523-4c88-a528-efcfefcd895b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515795176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3515795176
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1912442960
Short name T62
Test name
Test status
Simulation time 108321859 ps
CPU time 5.08 seconds
Started Aug 03 04:35:57 PM PDT 24
Finished Aug 03 04:36:02 PM PDT 24
Peak memory 219572 kb
Host smart-b8c2782e-82e8-4acd-b8cb-fa21fceb0a90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912442960 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1912442960
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3511584563
Short name T84
Test name
Test status
Simulation time 622025224 ps
CPU time 5.15 seconds
Started Aug 03 04:35:54 PM PDT 24
Finished Aug 03 04:35:59 PM PDT 24
Peak memory 218332 kb
Host smart-4f9cccfb-e2e3-41c2-b4a4-475fa517f232
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511584563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3511584563
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2513461249
Short name T87
Test name
Test status
Simulation time 854655166 ps
CPU time 18.39 seconds
Started Aug 03 04:36:01 PM PDT 24
Finished Aug 03 04:36:19 PM PDT 24
Peak memory 211268 kb
Host smart-aca13b1b-cf22-4a4b-b4f1-0d24028782cb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513461249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2513461249
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.122537532
Short name T404
Test name
Test status
Simulation time 141599369 ps
CPU time 6.91 seconds
Started Aug 03 04:36:01 PM PDT 24
Finished Aug 03 04:36:08 PM PDT 24
Peak memory 210952 kb
Host smart-433e997c-fd75-4b93-af4b-8bbe933f7740
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122537532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.122537532
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.927009785
Short name T343
Test name
Test status
Simulation time 117869777 ps
CPU time 6.87 seconds
Started Aug 03 04:36:01 PM PDT 24
Finished Aug 03 04:36:08 PM PDT 24
Peak memory 219608 kb
Host smart-88a3609f-7820-4312-9bce-2466fce2e8c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927009785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.927009785
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2096796324
Short name T378
Test name
Test status
Simulation time 289675294 ps
CPU time 69.95 seconds
Started Aug 03 04:36:04 PM PDT 24
Finished Aug 03 04:37:14 PM PDT 24
Peak memory 212996 kb
Host smart-255231a9-f018-41d6-bd57-2cb66570d44b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096796324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2096796324
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.754023915
Short name T406
Test name
Test status
Simulation time 209666872 ps
CPU time 4.93 seconds
Started Aug 03 04:35:58 PM PDT 24
Finished Aug 03 04:36:03 PM PDT 24
Peak memory 219492 kb
Host smart-85c944ec-b4cc-4479-9d2b-f9ed6234404b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754023915 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.754023915
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2694767668
Short name T89
Test name
Test status
Simulation time 146576510 ps
CPU time 4.32 seconds
Started Aug 03 04:35:55 PM PDT 24
Finished Aug 03 04:36:00 PM PDT 24
Peak memory 211152 kb
Host smart-bd1f027b-efcb-4a1b-9f89-3904a6849c74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694767668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2694767668
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.132461280
Short name T363
Test name
Test status
Simulation time 1132989431 ps
CPU time 5.42 seconds
Started Aug 03 04:35:54 PM PDT 24
Finished Aug 03 04:36:00 PM PDT 24
Peak memory 211344 kb
Host smart-6f61449b-be76-4ebf-9813-9d4609e3eb54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132461280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.132461280
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2758350737
Short name T334
Test name
Test status
Simulation time 333693776 ps
CPU time 8.14 seconds
Started Aug 03 04:36:04 PM PDT 24
Finished Aug 03 04:36:12 PM PDT 24
Peak memory 219608 kb
Host smart-97d96c56-c4b3-47d1-a06d-dc05cb0b6ef7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758350737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2758350737
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4055638949
Short name T124
Test name
Test status
Simulation time 1060664207 ps
CPU time 70.55 seconds
Started Aug 03 04:35:58 PM PDT 24
Finished Aug 03 04:37:09 PM PDT 24
Peak memory 213156 kb
Host smart-d7e8322e-0c46-4b2b-bb8a-acde9b2a6cae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055638949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.4055638949
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1327002921
Short name T357
Test name
Test status
Simulation time 261257692 ps
CPU time 4.57 seconds
Started Aug 03 04:36:06 PM PDT 24
Finished Aug 03 04:36:11 PM PDT 24
Peak memory 215668 kb
Host smart-67a1910f-e48e-4d2b-a3f6-18b265364a13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327002921 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1327002921
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1720740336
Short name T76
Test name
Test status
Simulation time 347012362 ps
CPU time 4.31 seconds
Started Aug 03 04:36:01 PM PDT 24
Finished Aug 03 04:36:05 PM PDT 24
Peak memory 211220 kb
Host smart-e7ca0bdb-a300-4050-ad03-d03ef8dee209
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720740336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1720740336
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1080702730
Short name T102
Test name
Test status
Simulation time 162267233 ps
CPU time 4.35 seconds
Started Aug 03 04:35:56 PM PDT 24
Finished Aug 03 04:36:01 PM PDT 24
Peak memory 211268 kb
Host smart-91f636f9-f4d3-4338-abf0-6bf884222f5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080702730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1080702730
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3444270914
Short name T383
Test name
Test status
Simulation time 87110612 ps
CPU time 6.49 seconds
Started Aug 03 04:35:59 PM PDT 24
Finished Aug 03 04:36:05 PM PDT 24
Peak memory 216444 kb
Host smart-d04b5cf4-ec86-4272-8f09-fd1666a03926
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444270914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3444270914
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4201409467
Short name T123
Test name
Test status
Simulation time 447326184 ps
CPU time 37.58 seconds
Started Aug 03 04:35:57 PM PDT 24
Finished Aug 03 04:36:34 PM PDT 24
Peak memory 219508 kb
Host smart-2205d004-9151-4dc6-a25e-14fb79b7d830
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201409467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.4201409467
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1366880331
Short name T369
Test name
Test status
Simulation time 141842238 ps
CPU time 5.58 seconds
Started Aug 03 04:35:57 PM PDT 24
Finished Aug 03 04:36:03 PM PDT 24
Peak memory 214664 kb
Host smart-9abf384f-5749-4c82-b7e5-d5bb3dd46fff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366880331 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1366880331
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2890357659
Short name T73
Test name
Test status
Simulation time 348095113 ps
CPU time 4.22 seconds
Started Aug 03 04:35:55 PM PDT 24
Finished Aug 03 04:36:00 PM PDT 24
Peak memory 210560 kb
Host smart-e5de35e7-80c4-4508-9f70-50dae8ae3f5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890357659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2890357659
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1552123615
Short name T108
Test name
Test status
Simulation time 87997770 ps
CPU time 4.49 seconds
Started Aug 03 04:35:53 PM PDT 24
Finished Aug 03 04:35:58 PM PDT 24
Peak memory 211264 kb
Host smart-6e7b4e3b-c17d-4761-84a3-7e86ea0ca7f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552123615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1552123615
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.245633090
Short name T417
Test name
Test status
Simulation time 311651583 ps
CPU time 6.58 seconds
Started Aug 03 04:35:58 PM PDT 24
Finished Aug 03 04:36:05 PM PDT 24
Peak memory 219504 kb
Host smart-7e039563-c184-47a0-b29d-572c15f67bd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245633090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.245633090
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2859083416
Short name T355
Test name
Test status
Simulation time 189557028 ps
CPU time 37.02 seconds
Started Aug 03 04:36:03 PM PDT 24
Finished Aug 03 04:36:40 PM PDT 24
Peak memory 219324 kb
Host smart-245b8b3f-2553-47b3-9a01-3db2ec72e71d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859083416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2859083416
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2241125591
Short name T384
Test name
Test status
Simulation time 556576375 ps
CPU time 6 seconds
Started Aug 03 04:36:02 PM PDT 24
Finished Aug 03 04:36:08 PM PDT 24
Peak memory 219580 kb
Host smart-b09b407d-6110-470d-9c97-c9645aad7149
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241125591 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2241125591
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.510898738
Short name T90
Test name
Test status
Simulation time 450222591 ps
CPU time 5.05 seconds
Started Aug 03 04:36:01 PM PDT 24
Finished Aug 03 04:36:06 PM PDT 24
Peak memory 217936 kb
Host smart-8f2613b6-a73b-4ca7-8b50-fa2152a1f51b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510898738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.510898738
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3457855012
Short name T379
Test name
Test status
Simulation time 90057450 ps
CPU time 4.43 seconds
Started Aug 03 04:35:59 PM PDT 24
Finished Aug 03 04:36:03 PM PDT 24
Peak memory 211256 kb
Host smart-d0a4c465-4453-4296-ba33-176ec519a746
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457855012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3457855012
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1368978777
Short name T362
Test name
Test status
Simulation time 347186805 ps
CPU time 6.56 seconds
Started Aug 03 04:36:05 PM PDT 24
Finished Aug 03 04:36:12 PM PDT 24
Peak memory 216232 kb
Host smart-95ed5429-b53b-4274-a378-9e23927f5533
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368978777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1368978777
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2404895721
Short name T127
Test name
Test status
Simulation time 1004646499 ps
CPU time 68.4 seconds
Started Aug 03 04:35:53 PM PDT 24
Finished Aug 03 04:37:01 PM PDT 24
Peak memory 219508 kb
Host smart-0b9c1d3f-00fa-4e22-860d-b5797cf38bca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404895721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2404895721
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2141175077
Short name T416
Test name
Test status
Simulation time 190114281 ps
CPU time 5.29 seconds
Started Aug 03 04:36:01 PM PDT 24
Finished Aug 03 04:36:06 PM PDT 24
Peak memory 216064 kb
Host smart-eb7134c6-7a58-436a-83e2-a6eb6b6c8477
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141175077 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2141175077
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1924544948
Short name T71
Test name
Test status
Simulation time 127854441 ps
CPU time 5.07 seconds
Started Aug 03 04:36:08 PM PDT 24
Finished Aug 03 04:36:13 PM PDT 24
Peak memory 211196 kb
Host smart-904edcd4-ac9d-4368-b6ea-c5f3066d88d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924544948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1924544948
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3547452274
Short name T69
Test name
Test status
Simulation time 201778157 ps
CPU time 4.22 seconds
Started Aug 03 04:36:03 PM PDT 24
Finished Aug 03 04:36:08 PM PDT 24
Peak memory 219388 kb
Host smart-2e873760-f2cd-4034-89e5-6c9f2bf634d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547452274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3547452274
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2086166630
Short name T336
Test name
Test status
Simulation time 85485515 ps
CPU time 6.69 seconds
Started Aug 03 04:36:02 PM PDT 24
Finished Aug 03 04:36:09 PM PDT 24
Peak memory 219472 kb
Host smart-a31c27c8-7b8a-4447-80a9-7b644a33245d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086166630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2086166630
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3140400241
Short name T126
Test name
Test status
Simulation time 504196769 ps
CPU time 70.15 seconds
Started Aug 03 04:36:08 PM PDT 24
Finished Aug 03 04:37:18 PM PDT 24
Peak memory 213024 kb
Host smart-18cc9d48-7d4a-4b56-8fb1-ca2db5e1d25d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140400241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3140400241
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3310963552
Short name T365
Test name
Test status
Simulation time 132838428 ps
CPU time 5.49 seconds
Started Aug 03 04:35:58 PM PDT 24
Finished Aug 03 04:36:03 PM PDT 24
Peak memory 219600 kb
Host smart-652b79bd-93b6-48fd-ad08-18c44d48849f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310963552 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3310963552
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2081183592
Short name T356
Test name
Test status
Simulation time 90204901 ps
CPU time 4.26 seconds
Started Aug 03 04:36:01 PM PDT 24
Finished Aug 03 04:36:06 PM PDT 24
Peak memory 211304 kb
Host smart-61931e3c-4b21-465b-94f0-008373b2782c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081183592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2081183592
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2919977663
Short name T68
Test name
Test status
Simulation time 729657183 ps
CPU time 18.21 seconds
Started Aug 03 04:36:01 PM PDT 24
Finished Aug 03 04:36:20 PM PDT 24
Peak memory 211268 kb
Host smart-ef4f27d8-d01b-4436-a571-7fa599a78b64
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919977663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2919977663
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.313316203
Short name T104
Test name
Test status
Simulation time 256498880 ps
CPU time 5.12 seconds
Started Aug 03 04:35:55 PM PDT 24
Finished Aug 03 04:36:00 PM PDT 24
Peak memory 218472 kb
Host smart-4eab57f9-db70-4376-a7df-1dd6ddd63c06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313316203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.313316203
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.51486559
Short name T348
Test name
Test status
Simulation time 256304165 ps
CPU time 6.62 seconds
Started Aug 03 04:36:03 PM PDT 24
Finished Aug 03 04:36:10 PM PDT 24
Peak memory 219556 kb
Host smart-73cb407b-e8aa-4d96-b7d3-d37d680e2b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51486559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.51486559
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4175195927
Short name T128
Test name
Test status
Simulation time 1062867420 ps
CPU time 37.3 seconds
Started Aug 03 04:36:00 PM PDT 24
Finished Aug 03 04:36:38 PM PDT 24
Peak memory 219496 kb
Host smart-d0288f09-dc44-48e3-8ed3-9ce812134889
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175195927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.4175195927
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2793746773
Short name T88
Test name
Test status
Simulation time 175199399 ps
CPU time 4.3 seconds
Started Aug 03 04:35:53 PM PDT 24
Finished Aug 03 04:35:57 PM PDT 24
Peak memory 211204 kb
Host smart-ac629d7c-af52-4768-a894-96fde9f50128
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793746773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2793746773
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3344857720
Short name T373
Test name
Test status
Simulation time 370789594 ps
CPU time 5.17 seconds
Started Aug 03 04:35:55 PM PDT 24
Finished Aug 03 04:36:00 PM PDT 24
Peak memory 211140 kb
Host smart-c6a7e951-4aec-4ca1-a62f-cfadf3ccbe9a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344857720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3344857720
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4183492079
Short name T110
Test name
Test status
Simulation time 327997333 ps
CPU time 5.64 seconds
Started Aug 03 04:35:49 PM PDT 24
Finished Aug 03 04:35:55 PM PDT 24
Peak memory 211296 kb
Host smart-0678105c-82ce-453a-8de1-b92d095c21d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183492079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.4183492079
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.758456714
Short name T349
Test name
Test status
Simulation time 363902162 ps
CPU time 4.46 seconds
Started Aug 03 04:35:41 PM PDT 24
Finished Aug 03 04:35:46 PM PDT 24
Peak memory 219604 kb
Host smart-e54f16fd-58fe-435b-a6cc-2c51d87b9757
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758456714 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.758456714
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1508877289
Short name T111
Test name
Test status
Simulation time 126806102 ps
CPU time 4.93 seconds
Started Aug 03 04:35:51 PM PDT 24
Finished Aug 03 04:35:56 PM PDT 24
Peak memory 211220 kb
Host smart-9ce4dd07-1d75-49e3-b61b-00c432693bcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508877289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1508877289
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.396653042
Short name T366
Test name
Test status
Simulation time 333891299 ps
CPU time 4.46 seconds
Started Aug 03 04:35:46 PM PDT 24
Finished Aug 03 04:35:51 PM PDT 24
Peak memory 211200 kb
Host smart-a37622e8-c6a1-48dd-86ac-0bc450d7bdd1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396653042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.396653042
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1131873379
Short name T340
Test name
Test status
Simulation time 348423625 ps
CPU time 4.04 seconds
Started Aug 03 04:35:53 PM PDT 24
Finished Aug 03 04:35:58 PM PDT 24
Peak memory 211072 kb
Host smart-4954a1a7-6b81-4507-a4a6-54e780590b77
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131873379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1131873379
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3148280073
Short name T376
Test name
Test status
Simulation time 85474137 ps
CPU time 4.59 seconds
Started Aug 03 04:35:55 PM PDT 24
Finished Aug 03 04:36:00 PM PDT 24
Peak memory 211256 kb
Host smart-ca8d77b3-78dc-4100-a61c-af9b5aa47aed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148280073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3148280073
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3396858673
Short name T382
Test name
Test status
Simulation time 560341818 ps
CPU time 8.87 seconds
Started Aug 03 04:35:51 PM PDT 24
Finished Aug 03 04:36:00 PM PDT 24
Peak memory 219644 kb
Host smart-195e2203-9bd8-48a7-8100-6498a835fcaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396858673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3396858673
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.511167056
Short name T58
Test name
Test status
Simulation time 270138028 ps
CPU time 69.68 seconds
Started Aug 03 04:35:42 PM PDT 24
Finished Aug 03 04:36:52 PM PDT 24
Peak memory 212840 kb
Host smart-603ca35b-95e8-4493-9d3d-c00662dcb6b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511167056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.511167056
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1719125224
Short name T398
Test name
Test status
Simulation time 129017797 ps
CPU time 5.15 seconds
Started Aug 03 04:35:49 PM PDT 24
Finished Aug 03 04:35:54 PM PDT 24
Peak memory 211180 kb
Host smart-d40cae1b-2736-4c29-8bc6-facbef8c273a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719125224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1719125224
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2787834266
Short name T344
Test name
Test status
Simulation time 346405807 ps
CPU time 4.45 seconds
Started Aug 03 04:35:45 PM PDT 24
Finished Aug 03 04:35:50 PM PDT 24
Peak memory 219284 kb
Host smart-dd88d68f-40ac-4bb4-8e00-6efc42c43758
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787834266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2787834266
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.114168381
Short name T408
Test name
Test status
Simulation time 91228947 ps
CPU time 5.81 seconds
Started Aug 03 04:35:48 PM PDT 24
Finished Aug 03 04:35:54 PM PDT 24
Peak memory 211228 kb
Host smart-6c1c76a7-7d96-4d7f-af1b-5a6f6332ff21
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114168381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.114168381
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1315562745
Short name T352
Test name
Test status
Simulation time 118927215 ps
CPU time 5.6 seconds
Started Aug 03 04:35:51 PM PDT 24
Finished Aug 03 04:35:56 PM PDT 24
Peak memory 216872 kb
Host smart-83832d91-afb1-4047-bb17-ff0d454f2f14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315562745 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1315562745
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4099411938
Short name T403
Test name
Test status
Simulation time 162118435 ps
CPU time 4.12 seconds
Started Aug 03 04:35:47 PM PDT 24
Finished Aug 03 04:35:51 PM PDT 24
Peak memory 211220 kb
Host smart-392a7d1e-d112-41e5-a5ba-bc23506ceba0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099411938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.4099411938
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2406275253
Short name T359
Test name
Test status
Simulation time 255091924 ps
CPU time 4.99 seconds
Started Aug 03 04:35:47 PM PDT 24
Finished Aug 03 04:35:52 PM PDT 24
Peak memory 211116 kb
Host smart-24728351-7584-469f-b59b-54625cbee710
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406275253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2406275253
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1350334247
Short name T385
Test name
Test status
Simulation time 168659153 ps
CPU time 4.18 seconds
Started Aug 03 04:35:45 PM PDT 24
Finished Aug 03 04:35:49 PM PDT 24
Peak memory 211116 kb
Host smart-5dc64df9-c3f6-44a5-8172-03a7733c605c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350334247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1350334247
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.312065911
Short name T381
Test name
Test status
Simulation time 249881301 ps
CPU time 5.12 seconds
Started Aug 03 04:35:47 PM PDT 24
Finished Aug 03 04:35:52 PM PDT 24
Peak memory 211296 kb
Host smart-b8fb9271-c90e-4a19-901d-5899e2beaf47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312065911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.312065911
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.903538558
Short name T387
Test name
Test status
Simulation time 87548308 ps
CPU time 6.87 seconds
Started Aug 03 04:35:51 PM PDT 24
Finished Aug 03 04:35:58 PM PDT 24
Peak memory 215080 kb
Host smart-4c764a10-907a-4967-9944-6551915e24d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903538558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.903538558
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4282840051
Short name T364
Test name
Test status
Simulation time 126135277 ps
CPU time 5.12 seconds
Started Aug 03 04:35:58 PM PDT 24
Finished Aug 03 04:36:03 PM PDT 24
Peak memory 211256 kb
Host smart-829b0d02-4a8b-443b-a941-31ac71e407b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282840051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.4282840051
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1503549532
Short name T341
Test name
Test status
Simulation time 1777111493 ps
CPU time 5.46 seconds
Started Aug 03 04:36:02 PM PDT 24
Finished Aug 03 04:36:08 PM PDT 24
Peak memory 211240 kb
Host smart-c1e23c5e-4cc1-441f-a5d4-82d3fa49f1f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503549532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1503549532
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.813791286
Short name T397
Test name
Test status
Simulation time 283409516 ps
CPU time 6.49 seconds
Started Aug 03 04:35:48 PM PDT 24
Finished Aug 03 04:35:55 PM PDT 24
Peak memory 211140 kb
Host smart-4de8d9e9-8e37-400d-a4a9-da872b3a2f64
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813791286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.813791286
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3934301539
Short name T407
Test name
Test status
Simulation time 174997836 ps
CPU time 4.35 seconds
Started Aug 03 04:35:53 PM PDT 24
Finished Aug 03 04:35:57 PM PDT 24
Peak memory 213024 kb
Host smart-41c8e4f1-5a69-4167-a38e-8e689eea17d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934301539 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3934301539
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.768531373
Short name T83
Test name
Test status
Simulation time 363251495 ps
CPU time 4.37 seconds
Started Aug 03 04:36:00 PM PDT 24
Finished Aug 03 04:36:05 PM PDT 24
Peak memory 211224 kb
Host smart-138e1636-b7d4-46f8-b470-682c740a2aad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768531373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.768531373
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1474548326
Short name T370
Test name
Test status
Simulation time 257475788 ps
CPU time 4.97 seconds
Started Aug 03 04:35:54 PM PDT 24
Finished Aug 03 04:35:59 PM PDT 24
Peak memory 211220 kb
Host smart-7b794432-20c0-4682-8d7d-4f571bbeba1a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474548326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1474548326
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3879459125
Short name T350
Test name
Test status
Simulation time 132465739 ps
CPU time 4.93 seconds
Started Aug 03 04:35:50 PM PDT 24
Finished Aug 03 04:35:55 PM PDT 24
Peak memory 211248 kb
Host smart-011586d6-8db2-4350-8067-26236256ee96
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879459125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3879459125
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1485072717
Short name T345
Test name
Test status
Simulation time 736910653 ps
CPU time 18.81 seconds
Started Aug 03 04:35:44 PM PDT 24
Finished Aug 03 04:36:03 PM PDT 24
Peak memory 211380 kb
Host smart-2e1e37a3-2659-40fe-ab37-25514f3225d9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485072717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1485072717
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1418534993
Short name T401
Test name
Test status
Simulation time 560563785 ps
CPU time 6.98 seconds
Started Aug 03 04:35:53 PM PDT 24
Finished Aug 03 04:36:00 PM PDT 24
Peak memory 211384 kb
Host smart-81c1499d-0b09-4396-9c1f-abb00c00a445
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418534993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1418534993
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.22705172
Short name T372
Test name
Test status
Simulation time 85873524 ps
CPU time 6.1 seconds
Started Aug 03 04:35:55 PM PDT 24
Finished Aug 03 04:36:02 PM PDT 24
Peak memory 215948 kb
Host smart-352a911e-d7c2-467c-95b1-af06b0d4d13a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22705172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.22705172
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.160663668
Short name T374
Test name
Test status
Simulation time 990201674 ps
CPU time 69.57 seconds
Started Aug 03 04:35:55 PM PDT 24
Finished Aug 03 04:37:04 PM PDT 24
Peak memory 213092 kb
Host smart-7502a9a4-4398-4656-98e3-30c22b2d6d5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160663668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.160663668
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2266301039
Short name T371
Test name
Test status
Simulation time 302047576 ps
CPU time 7.49 seconds
Started Aug 03 04:35:59 PM PDT 24
Finished Aug 03 04:36:06 PM PDT 24
Peak memory 216828 kb
Host smart-31b74d73-df31-48ed-b8af-6852f60bf26a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266301039 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2266301039
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2148453570
Short name T394
Test name
Test status
Simulation time 172270049 ps
CPU time 4.34 seconds
Started Aug 03 04:35:50 PM PDT 24
Finished Aug 03 04:35:55 PM PDT 24
Peak memory 211188 kb
Host smart-a0f497e1-900c-44eb-b120-ba4ed16e2aec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148453570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2148453570
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.164257027
Short name T72
Test name
Test status
Simulation time 97252564 ps
CPU time 5.85 seconds
Started Aug 03 04:35:49 PM PDT 24
Finished Aug 03 04:35:55 PM PDT 24
Peak memory 219360 kb
Host smart-4905a228-b7de-449c-af32-61e0d555f083
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164257027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.164257027
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1266286377
Short name T351
Test name
Test status
Simulation time 503970885 ps
CPU time 9.45 seconds
Started Aug 03 04:36:01 PM PDT 24
Finished Aug 03 04:36:10 PM PDT 24
Peak memory 216608 kb
Host smart-33b9213b-4f1a-4c79-94c5-c654625d0a0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266286377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1266286377
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.609129506
Short name T119
Test name
Test status
Simulation time 597909930 ps
CPU time 70.34 seconds
Started Aug 03 04:35:52 PM PDT 24
Finished Aug 03 04:37:02 PM PDT 24
Peak memory 219540 kb
Host smart-541cca19-79f3-420f-84ed-acefa911a651
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609129506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.609129506
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3314132904
Short name T339
Test name
Test status
Simulation time 811894574 ps
CPU time 5.1 seconds
Started Aug 03 04:35:54 PM PDT 24
Finished Aug 03 04:35:59 PM PDT 24
Peak memory 219536 kb
Host smart-67f74b3e-262b-4f7d-944c-2d1587485a0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314132904 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3314132904
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2956195156
Short name T74
Test name
Test status
Simulation time 132235985 ps
CPU time 5.08 seconds
Started Aug 03 04:35:48 PM PDT 24
Finished Aug 03 04:35:53 PM PDT 24
Peak memory 211268 kb
Host smart-afbba139-85c9-40d6-a77c-f3b6670a1e49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956195156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2956195156
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1569204855
Short name T358
Test name
Test status
Simulation time 499083500 ps
CPU time 5.17 seconds
Started Aug 03 04:35:50 PM PDT 24
Finished Aug 03 04:35:55 PM PDT 24
Peak memory 211360 kb
Host smart-4ca4e675-1d56-4d82-8140-bc70a1166d80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569204855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1569204855
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3364030782
Short name T333
Test name
Test status
Simulation time 309591887 ps
CPU time 6.37 seconds
Started Aug 03 04:36:00 PM PDT 24
Finished Aug 03 04:36:07 PM PDT 24
Peak memory 215132 kb
Host smart-d645a230-f452-4c67-aff2-f73a804ee0b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364030782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3364030782
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2877286010
Short name T388
Test name
Test status
Simulation time 1037802962 ps
CPU time 67.79 seconds
Started Aug 03 04:35:51 PM PDT 24
Finished Aug 03 04:36:59 PM PDT 24
Peak memory 219400 kb
Host smart-268f6ec3-e46f-4ef0-a167-439c004a8a8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877286010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2877286010
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.449803806
Short name T393
Test name
Test status
Simulation time 261559065 ps
CPU time 5.58 seconds
Started Aug 03 04:35:55 PM PDT 24
Finished Aug 03 04:36:01 PM PDT 24
Peak memory 219620 kb
Host smart-b41401fe-38f6-4f7c-b949-f2cb093f9b25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449803806 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.449803806
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4261447992
Short name T391
Test name
Test status
Simulation time 416943957 ps
CPU time 4.1 seconds
Started Aug 03 04:35:54 PM PDT 24
Finished Aug 03 04:35:59 PM PDT 24
Peak memory 211152 kb
Host smart-3bb89c2b-1be7-4d80-86d8-71b280e71b42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261447992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.4261447992
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1320837877
Short name T375
Test name
Test status
Simulation time 300334620 ps
CPU time 4.41 seconds
Started Aug 03 04:35:54 PM PDT 24
Finished Aug 03 04:35:59 PM PDT 24
Peak memory 219488 kb
Host smart-d34ba366-a04b-420f-9268-11eedc18a624
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320837877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1320837877
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1586615030
Short name T380
Test name
Test status
Simulation time 126737932 ps
CPU time 8.57 seconds
Started Aug 03 04:35:52 PM PDT 24
Finished Aug 03 04:36:01 PM PDT 24
Peak memory 217396 kb
Host smart-279e82c5-28fc-40d0-9c60-add43990db16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586615030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1586615030
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2854134906
Short name T59
Test name
Test status
Simulation time 592645788 ps
CPU time 35.66 seconds
Started Aug 03 04:35:50 PM PDT 24
Finished Aug 03 04:36:26 PM PDT 24
Peak memory 219500 kb
Host smart-bfc3ed06-a0fe-4426-827f-1d5b1d340e72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854134906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2854134906
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2741358087
Short name T338
Test name
Test status
Simulation time 138250804 ps
CPU time 5.88 seconds
Started Aug 03 04:35:50 PM PDT 24
Finished Aug 03 04:35:56 PM PDT 24
Peak memory 216500 kb
Host smart-9d3b27f3-3855-4527-b3a0-5281a3965c05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741358087 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2741358087
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2866498663
Short name T61
Test name
Test status
Simulation time 127196752 ps
CPU time 5.01 seconds
Started Aug 03 04:35:58 PM PDT 24
Finished Aug 03 04:36:03 PM PDT 24
Peak memory 211304 kb
Host smart-f726eedc-b40a-4815-8e19-d9b66b34cd1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866498663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2866498663
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1330268180
Short name T409
Test name
Test status
Simulation time 346541363 ps
CPU time 4.35 seconds
Started Aug 03 04:36:00 PM PDT 24
Finished Aug 03 04:36:04 PM PDT 24
Peak memory 211360 kb
Host smart-cc6a0eeb-5c00-4274-b1a7-6f15fa571208
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330268180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1330268180
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.690811638
Short name T411
Test name
Test status
Simulation time 2055342656 ps
CPU time 7.66 seconds
Started Aug 03 04:35:51 PM PDT 24
Finished Aug 03 04:35:59 PM PDT 24
Peak memory 216188 kb
Host smart-8c1000a2-8c3a-4014-8009-f4c7cededeb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690811638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.690811638
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2806436229
Short name T117
Test name
Test status
Simulation time 2444358265 ps
CPU time 37.11 seconds
Started Aug 03 04:35:56 PM PDT 24
Finished Aug 03 04:36:34 PM PDT 24
Peak memory 219568 kb
Host smart-b0b809bc-3dbd-4ce4-90ab-60a42839466b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806436229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2806436229
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3430427966
Short name T347
Test name
Test status
Simulation time 147074531 ps
CPU time 6.57 seconds
Started Aug 03 04:35:49 PM PDT 24
Finished Aug 03 04:35:56 PM PDT 24
Peak memory 219580 kb
Host smart-f35dd51d-ee05-46f6-8ae1-db73bc8b70e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430427966 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3430427966
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3592887799
Short name T92
Test name
Test status
Simulation time 462573711 ps
CPU time 4.84 seconds
Started Aug 03 04:35:53 PM PDT 24
Finished Aug 03 04:35:57 PM PDT 24
Peak memory 211272 kb
Host smart-ef10e8ae-4e26-432f-be28-66df49321ba9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592887799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3592887799
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1110783353
Short name T75
Test name
Test status
Simulation time 3209393808 ps
CPU time 18.64 seconds
Started Aug 03 04:36:01 PM PDT 24
Finished Aug 03 04:36:20 PM PDT 24
Peak memory 211488 kb
Host smart-3385dd93-2ec3-42f2-b004-38f6a15d265f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110783353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1110783353
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2459372841
Short name T105
Test name
Test status
Simulation time 128675208 ps
CPU time 5.08 seconds
Started Aug 03 04:35:55 PM PDT 24
Finished Aug 03 04:36:01 PM PDT 24
Peak memory 211320 kb
Host smart-f8dc738b-15a4-430f-8eb8-3e90c6545eff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459372841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2459372841
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1072732546
Short name T410
Test name
Test status
Simulation time 250189922 ps
CPU time 7.36 seconds
Started Aug 03 04:35:58 PM PDT 24
Finished Aug 03 04:36:06 PM PDT 24
Peak memory 216488 kb
Host smart-922f9501-af11-4877-b12a-47daa0bef328
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072732546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1072732546
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.205883274
Short name T263
Test name
Test status
Simulation time 1038003658 ps
CPU time 11.21 seconds
Started Aug 03 04:50:04 PM PDT 24
Finished Aug 03 04:50:16 PM PDT 24
Peak memory 212816 kb
Host smart-8d8c55fe-4230-4b3e-872a-eee49442b8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205883274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.205883274
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.514801063
Short name T178
Test name
Test status
Simulation time 97948272 ps
CPU time 5.72 seconds
Started Aug 03 04:50:04 PM PDT 24
Finished Aug 03 04:50:10 PM PDT 24
Peak memory 212136 kb
Host smart-c5bbcbd8-bde0-446e-87fc-b1bfb4aaf204
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=514801063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.514801063
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3404491969
Short name T17
Test name
Test status
Simulation time 136908320 ps
CPU time 6.42 seconds
Started Aug 03 04:50:04 PM PDT 24
Finished Aug 03 04:50:11 PM PDT 24
Peak memory 212380 kb
Host smart-e563d2b2-5c49-44e4-af98-31ead59cfaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404491969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3404491969
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1545275839
Short name T32
Test name
Test status
Simulation time 85712247 ps
CPU time 4.28 seconds
Started Aug 03 04:50:06 PM PDT 24
Finished Aug 03 04:50:11 PM PDT 24
Peak memory 212000 kb
Host smart-7506252a-56e1-45bc-b59f-648bf51525db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545275839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1545275839
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3810848104
Short name T326
Test name
Test status
Simulation time 25353087640 ps
CPU time 113.53 seconds
Started Aug 03 04:50:18 PM PDT 24
Finished Aug 03 04:52:11 PM PDT 24
Peak memory 238508 kb
Host smart-541b7321-936c-4751-862a-a34525698fcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810848104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3810848104
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.381662966
Short name T193
Test name
Test status
Simulation time 173474056 ps
CPU time 9.49 seconds
Started Aug 03 04:50:17 PM PDT 24
Finished Aug 03 04:50:27 PM PDT 24
Peak memory 212984 kb
Host smart-053862c9-c2bc-4e32-8728-bf1bededde5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381662966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.381662966
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2355886674
Short name T301
Test name
Test status
Simulation time 139392581 ps
CPU time 6.72 seconds
Started Aug 03 04:50:07 PM PDT 24
Finished Aug 03 04:50:14 PM PDT 24
Peak memory 212120 kb
Host smart-e1d14106-f726-4aa1-83dd-7f75a4d493bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2355886674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2355886674
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3745862983
Short name T19
Test name
Test status
Simulation time 1819331339 ps
CPU time 99.7 seconds
Started Aug 03 04:50:07 PM PDT 24
Finished Aug 03 04:51:46 PM PDT 24
Peak memory 237192 kb
Host smart-9ca19153-b462-4c50-8df8-0fe287c2a506
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745862983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3745862983
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.689888035
Short name T208
Test name
Test status
Simulation time 187919615 ps
CPU time 5.4 seconds
Started Aug 03 04:50:01 PM PDT 24
Finished Aug 03 04:50:07 PM PDT 24
Peak memory 212228 kb
Host smart-bb5d507c-6dd9-444d-85ee-8be634c31852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689888035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.689888035
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2269490632
Short name T33
Test name
Test status
Simulation time 1685528044 ps
CPU time 14.25 seconds
Started Aug 03 04:50:17 PM PDT 24
Finished Aug 03 04:50:32 PM PDT 24
Peak memory 214784 kb
Host smart-89a4ffa1-c84b-4c47-855c-f4c8c20b51b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269490632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2269490632
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.333238030
Short name T31
Test name
Test status
Simulation time 733674778 ps
CPU time 5.33 seconds
Started Aug 03 04:50:15 PM PDT 24
Finished Aug 03 04:50:20 PM PDT 24
Peak memory 212040 kb
Host smart-37c2d6f4-dcc2-4d2a-a198-89eb1a0c74f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333238030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.333238030
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3163928366
Short name T175
Test name
Test status
Simulation time 2147288306 ps
CPU time 75.76 seconds
Started Aug 03 04:50:19 PM PDT 24
Finished Aug 03 04:51:35 PM PDT 24
Peak memory 234280 kb
Host smart-590b244c-047f-4fb8-9663-728433370482
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163928366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3163928366
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1220482338
Short name T330
Test name
Test status
Simulation time 803152208 ps
CPU time 11.5 seconds
Started Aug 03 04:50:16 PM PDT 24
Finished Aug 03 04:50:28 PM PDT 24
Peak memory 212968 kb
Host smart-162f12b0-0a66-4664-b145-40e47ddc82a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220482338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1220482338
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3685327767
Short name T56
Test name
Test status
Simulation time 95746743 ps
CPU time 5.59 seconds
Started Aug 03 04:50:19 PM PDT 24
Finished Aug 03 04:50:25 PM PDT 24
Peak memory 212024 kb
Host smart-90886a73-d380-4ce5-8340-ca27f3db1dde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3685327767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3685327767
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3296436610
Short name T315
Test name
Test status
Simulation time 1050989646 ps
CPU time 21.17 seconds
Started Aug 03 04:50:20 PM PDT 24
Finished Aug 03 04:50:41 PM PDT 24
Peak memory 216080 kb
Host smart-f8bec799-fb80-452a-82e4-0a03d02f440c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296436610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3296436610
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3441604493
Short name T52
Test name
Test status
Simulation time 25868046900 ps
CPU time 784.7 seconds
Started Aug 03 04:50:15 PM PDT 24
Finished Aug 03 05:03:20 PM PDT 24
Peak memory 236656 kb
Host smart-41ee4081-5037-4837-ad84-4ada043ef8f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441604493 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3441604493
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2219494181
Short name T197
Test name
Test status
Simulation time 334298285 ps
CPU time 4.24 seconds
Started Aug 03 04:50:21 PM PDT 24
Finished Aug 03 04:50:26 PM PDT 24
Peak memory 212012 kb
Host smart-6808c928-5ada-4223-9383-972d61454c8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219494181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2219494181
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.829561590
Short name T308
Test name
Test status
Simulation time 10194428097 ps
CPU time 132.86 seconds
Started Aug 03 04:50:19 PM PDT 24
Finished Aug 03 04:52:33 PM PDT 24
Peak memory 235416 kb
Host smart-4fa191c9-f8ff-44bb-9bd8-212616c9ee22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829561590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.829561590
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2861601201
Short name T113
Test name
Test status
Simulation time 787608708 ps
CPU time 6.82 seconds
Started Aug 03 04:50:15 PM PDT 24
Finished Aug 03 04:50:22 PM PDT 24
Peak memory 212136 kb
Host smart-f5d78d4a-8e32-4f1d-975f-5667cd90dc65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2861601201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2861601201
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1293990716
Short name T201
Test name
Test status
Simulation time 453885397 ps
CPU time 21.53 seconds
Started Aug 03 04:50:21 PM PDT 24
Finished Aug 03 04:50:42 PM PDT 24
Peak memory 215492 kb
Host smart-3ad8743e-1c55-490a-a121-cc8cce1feb0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293990716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1293990716
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2723929789
Short name T293
Test name
Test status
Simulation time 34426161440 ps
CPU time 708.32 seconds
Started Aug 03 04:50:19 PM PDT 24
Finished Aug 03 05:02:08 PM PDT 24
Peak memory 228448 kb
Host smart-596afd0c-4ec4-439f-ae9e-224e0c4810a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723929789 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2723929789
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1892774229
Short name T210
Test name
Test status
Simulation time 440016968 ps
CPU time 4.29 seconds
Started Aug 03 04:50:19 PM PDT 24
Finished Aug 03 04:50:24 PM PDT 24
Peak memory 212052 kb
Host smart-d3b51091-9510-439b-b880-ba661aa5ba13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892774229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1892774229
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3296118248
Short name T7
Test name
Test status
Simulation time 4432399138 ps
CPU time 92.97 seconds
Started Aug 03 04:50:21 PM PDT 24
Finished Aug 03 04:51:54 PM PDT 24
Peak memory 238500 kb
Host smart-2421fa31-4e6f-4b14-9159-17f462833b0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296118248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3296118248
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3757485148
Short name T270
Test name
Test status
Simulation time 665909784 ps
CPU time 9.51 seconds
Started Aug 03 04:50:20 PM PDT 24
Finished Aug 03 04:50:30 PM PDT 24
Peak memory 213340 kb
Host smart-a5003016-925b-4fa4-88c5-b926fed9cb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757485148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3757485148
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2396554748
Short name T161
Test name
Test status
Simulation time 138763097 ps
CPU time 6.35 seconds
Started Aug 03 04:50:15 PM PDT 24
Finished Aug 03 04:50:22 PM PDT 24
Peak memory 212060 kb
Host smart-1e0adb54-9f7a-4a0c-8f78-643486d13cbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2396554748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2396554748
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2603611493
Short name T29
Test name
Test status
Simulation time 175853921 ps
CPU time 5.05 seconds
Started Aug 03 04:50:16 PM PDT 24
Finished Aug 03 04:50:22 PM PDT 24
Peak memory 211796 kb
Host smart-01c5dded-2f61-4e6e-87d9-29b0b4b3c734
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603611493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2603611493
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3648476572
Short name T65
Test name
Test status
Simulation time 348987373 ps
CPU time 4.34 seconds
Started Aug 03 04:50:20 PM PDT 24
Finished Aug 03 04:50:25 PM PDT 24
Peak memory 211972 kb
Host smart-8d3b0384-6b89-4104-9bc3-3f8c0fa5f277
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648476572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3648476572
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2552463916
Short name T325
Test name
Test status
Simulation time 4229038176 ps
CPU time 123.68 seconds
Started Aug 03 04:50:19 PM PDT 24
Finished Aug 03 04:52:23 PM PDT 24
Peak memory 238472 kb
Host smart-6f108aed-2a52-41e2-910f-d605a5b967c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552463916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2552463916
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.4101229691
Short name T294
Test name
Test status
Simulation time 168707854 ps
CPU time 9.34 seconds
Started Aug 03 04:50:19 PM PDT 24
Finished Aug 03 04:50:29 PM PDT 24
Peak memory 212812 kb
Host smart-3eacfcd4-46e2-4077-ab65-a110df42f6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101229691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.4101229691
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1516185673
Short name T217
Test name
Test status
Simulation time 99222687 ps
CPU time 5.74 seconds
Started Aug 03 04:50:19 PM PDT 24
Finished Aug 03 04:50:25 PM PDT 24
Peak memory 212136 kb
Host smart-ee789ebb-f459-4133-856c-d9d8c7c72545
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1516185673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1516185673
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1870484272
Short name T287
Test name
Test status
Simulation time 4971821627 ps
CPU time 18.23 seconds
Started Aug 03 04:50:18 PM PDT 24
Finished Aug 03 04:50:36 PM PDT 24
Peak memory 216852 kb
Host smart-9d2c560d-810f-4521-86f1-c490e2f5f991
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870484272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1870484272
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.4091431507
Short name T50
Test name
Test status
Simulation time 35286264531 ps
CPU time 2179.6 seconds
Started Aug 03 04:50:21 PM PDT 24
Finished Aug 03 05:26:41 PM PDT 24
Peak memory 227636 kb
Host smart-ece032ca-1d09-4970-8e4e-11797421c538
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091431507 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.4091431507
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3873813326
Short name T295
Test name
Test status
Simulation time 308624547 ps
CPU time 4.19 seconds
Started Aug 03 04:50:20 PM PDT 24
Finished Aug 03 04:50:25 PM PDT 24
Peak memory 212028 kb
Host smart-5fe92bff-e35f-4ea1-ac17-06dc12510855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873813326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3873813326
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1035960246
Short name T129
Test name
Test status
Simulation time 13808075271 ps
CPU time 164.38 seconds
Started Aug 03 04:50:22 PM PDT 24
Finished Aug 03 04:53:06 PM PDT 24
Peak memory 241560 kb
Host smart-2331b6e9-3bcc-4e60-a719-1b2d401b0c51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035960246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1035960246
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.4162687068
Short name T267
Test name
Test status
Simulation time 2052292356 ps
CPU time 16.05 seconds
Started Aug 03 04:50:21 PM PDT 24
Finished Aug 03 04:50:37 PM PDT 24
Peak memory 213020 kb
Host smart-36e9485a-a993-4ea6-b3d8-b2cefab2f7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162687068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.4162687068
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2029503098
Short name T189
Test name
Test status
Simulation time 189118519 ps
CPU time 5.46 seconds
Started Aug 03 04:50:21 PM PDT 24
Finished Aug 03 04:50:27 PM PDT 24
Peak memory 212168 kb
Host smart-76ee23aa-1fe2-4006-a0db-c0a119d10c33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2029503098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2029503098
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3410643668
Short name T253
Test name
Test status
Simulation time 2067958675 ps
CPU time 22.33 seconds
Started Aug 03 04:50:20 PM PDT 24
Finished Aug 03 04:50:42 PM PDT 24
Peak memory 215440 kb
Host smart-7d0d67da-e210-44e0-8e1b-0cb89718cace
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410643668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3410643668
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1082236674
Short name T66
Test name
Test status
Simulation time 175661233 ps
CPU time 4.25 seconds
Started Aug 03 04:50:23 PM PDT 24
Finished Aug 03 04:50:27 PM PDT 24
Peak memory 211980 kb
Host smart-7f2ee3e0-f9c2-4ea6-8350-a4c516dad534
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082236674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1082236674
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.418712453
Short name T271
Test name
Test status
Simulation time 1974312348 ps
CPU time 122.86 seconds
Started Aug 03 04:50:23 PM PDT 24
Finished Aug 03 04:52:26 PM PDT 24
Peak memory 237300 kb
Host smart-fcdb93c2-c572-4fcd-8c3e-3a110cd7c034
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418712453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.418712453
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3974738410
Short name T310
Test name
Test status
Simulation time 996671752 ps
CPU time 11.06 seconds
Started Aug 03 04:50:18 PM PDT 24
Finished Aug 03 04:50:29 PM PDT 24
Peak memory 213012 kb
Host smart-33cdcb19-9dcd-4925-bfb7-e2593dcba0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974738410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3974738410
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2430527233
Short name T97
Test name
Test status
Simulation time 140341510 ps
CPU time 6.36 seconds
Started Aug 03 04:50:18 PM PDT 24
Finished Aug 03 04:50:25 PM PDT 24
Peak memory 212112 kb
Host smart-1aabb54f-7399-4ec5-80b8-c117e466a017
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2430527233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2430527233
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2167115881
Short name T96
Test name
Test status
Simulation time 845166412 ps
CPU time 13.85 seconds
Started Aug 03 04:50:20 PM PDT 24
Finished Aug 03 04:50:34 PM PDT 24
Peak memory 215372 kb
Host smart-abe90b2e-6c40-42e0-a2ed-d1ac8b01584c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167115881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2167115881
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.593165892
Short name T317
Test name
Test status
Simulation time 53746693215 ps
CPU time 8422.05 seconds
Started Aug 03 04:50:22 PM PDT 24
Finished Aug 03 07:10:45 PM PDT 24
Peak memory 236628 kb
Host smart-ad6fec2c-339c-4c90-b010-6b11988e0678
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593165892 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.593165892
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3986766886
Short name T296
Test name
Test status
Simulation time 88139849 ps
CPU time 4.33 seconds
Started Aug 03 04:50:20 PM PDT 24
Finished Aug 03 04:50:24 PM PDT 24
Peak memory 212024 kb
Host smart-bfc8e609-8911-41f7-876f-fb2f35e32f43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986766886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3986766886
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3403375109
Short name T259
Test name
Test status
Simulation time 347912850 ps
CPU time 9.54 seconds
Started Aug 03 04:50:19 PM PDT 24
Finished Aug 03 04:50:29 PM PDT 24
Peak memory 212876 kb
Host smart-8368a8e4-f9e4-4b3b-8abd-6c749a6b679c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403375109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3403375109
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.830248676
Short name T95
Test name
Test status
Simulation time 152962304 ps
CPU time 6.59 seconds
Started Aug 03 04:50:18 PM PDT 24
Finished Aug 03 04:50:25 PM PDT 24
Peak memory 212152 kb
Host smart-d3f9b50d-65f4-4644-ae66-c4278a4a5771
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=830248676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.830248676
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1764917859
Short name T227
Test name
Test status
Simulation time 2718530976 ps
CPU time 13.15 seconds
Started Aug 03 04:50:19 PM PDT 24
Finished Aug 03 04:50:32 PM PDT 24
Peak memory 213840 kb
Host smart-67c247d7-69ed-40be-8856-e259d500ac1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764917859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1764917859
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.30855089
Short name T265
Test name
Test status
Simulation time 23896029252 ps
CPU time 8769.65 seconds
Started Aug 03 04:50:20 PM PDT 24
Finished Aug 03 07:16:30 PM PDT 24
Peak memory 236548 kb
Host smart-853744b3-7026-4231-8b48-82cf42824ade
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30855089 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.30855089
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3856337032
Short name T297
Test name
Test status
Simulation time 128947216 ps
CPU time 5.23 seconds
Started Aug 03 04:50:18 PM PDT 24
Finished Aug 03 04:50:24 PM PDT 24
Peak memory 212048 kb
Host smart-378d2f97-ccbc-45bf-9fb7-02549aeeee44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856337032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3856337032
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4003404601
Short name T196
Test name
Test status
Simulation time 31388018970 ps
CPU time 154.83 seconds
Started Aug 03 04:50:23 PM PDT 24
Finished Aug 03 04:52:58 PM PDT 24
Peak memory 213512 kb
Host smart-6c725073-bb43-4ed3-b754-e7da47376ebd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003404601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.4003404601
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2372394723
Short name T269
Test name
Test status
Simulation time 335250463 ps
CPU time 9.83 seconds
Started Aug 03 04:50:22 PM PDT 24
Finished Aug 03 04:50:31 PM PDT 24
Peak memory 212876 kb
Host smart-613f8ac2-d099-46e4-ad6f-f0806ee5c485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372394723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2372394723
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.173665037
Short name T228
Test name
Test status
Simulation time 188370934 ps
CPU time 5.63 seconds
Started Aug 03 04:50:19 PM PDT 24
Finished Aug 03 04:50:25 PM PDT 24
Peak memory 212156 kb
Host smart-9bb3f749-904d-4b16-aeb3-9532a20042b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=173665037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.173665037
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.727676715
Short name T332
Test name
Test status
Simulation time 112819394 ps
CPU time 5.94 seconds
Started Aug 03 04:50:21 PM PDT 24
Finished Aug 03 04:50:28 PM PDT 24
Peak memory 212096 kb
Host smart-e2b5caf0-2bd7-4928-a80a-3c02dcef9918
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727676715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.727676715
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.4166985879
Short name T67
Test name
Test status
Simulation time 1184214333 ps
CPU time 4.28 seconds
Started Aug 03 04:50:21 PM PDT 24
Finished Aug 03 04:50:25 PM PDT 24
Peak memory 212048 kb
Host smart-bafd992d-2833-4b1f-8e4c-e2eb8d74d5c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166985879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.4166985879
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1648292196
Short name T94
Test name
Test status
Simulation time 19399492775 ps
CPU time 189.61 seconds
Started Aug 03 04:50:23 PM PDT 24
Finished Aug 03 04:53:32 PM PDT 24
Peak memory 235808 kb
Host smart-988bc37a-2031-4d83-b23a-752e198f1902
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648292196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1648292196
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1412779203
Short name T204
Test name
Test status
Simulation time 262666448 ps
CPU time 11.26 seconds
Started Aug 03 04:50:20 PM PDT 24
Finished Aug 03 04:50:32 PM PDT 24
Peak memory 212864 kb
Host smart-d5c0c804-046b-4bc6-be63-c1ab1df81e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412779203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1412779203
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.965611234
Short name T163
Test name
Test status
Simulation time 279423282 ps
CPU time 6.58 seconds
Started Aug 03 04:50:19 PM PDT 24
Finished Aug 03 04:50:25 PM PDT 24
Peak memory 212144 kb
Host smart-174e2dac-1ec9-4a63-82e1-051ff17670d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=965611234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.965611234
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2939882895
Short name T183
Test name
Test status
Simulation time 3226390538 ps
CPU time 13.48 seconds
Started Aug 03 04:50:21 PM PDT 24
Finished Aug 03 04:50:34 PM PDT 24
Peak memory 214556 kb
Host smart-5bdff6fd-3d21-46c9-8828-05509774a66d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939882895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2939882895
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3261580855
Short name T319
Test name
Test status
Simulation time 132850593 ps
CPU time 5.2 seconds
Started Aug 03 04:50:27 PM PDT 24
Finished Aug 03 04:50:32 PM PDT 24
Peak memory 212004 kb
Host smart-90557763-5f8d-4bdd-aac4-e4a4f0b81d97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261580855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3261580855
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1653317110
Short name T40
Test name
Test status
Simulation time 10988288658 ps
CPU time 130.55 seconds
Started Aug 03 04:50:19 PM PDT 24
Finished Aug 03 04:52:30 PM PDT 24
Peak memory 213544 kb
Host smart-036109a0-2495-4ed3-9c83-ffdf7394f309
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653317110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1653317110
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2042924514
Short name T195
Test name
Test status
Simulation time 253854565 ps
CPU time 9.88 seconds
Started Aug 03 04:50:20 PM PDT 24
Finished Aug 03 04:50:30 PM PDT 24
Peak memory 215620 kb
Host smart-d6186159-93c1-46f9-a22a-bc58ff2a229d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042924514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2042924514
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2764703005
Short name T225
Test name
Test status
Simulation time 553654623 ps
CPU time 6.28 seconds
Started Aug 03 04:50:21 PM PDT 24
Finished Aug 03 04:50:27 PM PDT 24
Peak memory 212004 kb
Host smart-6c2253a2-8a06-4b5a-a659-a5bf09a77958
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2764703005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2764703005
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3602362220
Short name T256
Test name
Test status
Simulation time 652256186 ps
CPU time 12.02 seconds
Started Aug 03 04:50:21 PM PDT 24
Finished Aug 03 04:50:34 PM PDT 24
Peak memory 215272 kb
Host smart-501273f4-825a-46cd-948a-bb6466585846
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602362220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3602362220
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2540342671
Short name T64
Test name
Test status
Simulation time 168211484 ps
CPU time 4.31 seconds
Started Aug 03 04:50:08 PM PDT 24
Finished Aug 03 04:50:13 PM PDT 24
Peak memory 212004 kb
Host smart-01ec4b94-a25f-421e-b3a7-17c742b1f937
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540342671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2540342671
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1106241751
Short name T311
Test name
Test status
Simulation time 264587597 ps
CPU time 11.39 seconds
Started Aug 03 04:50:08 PM PDT 24
Finished Aug 03 04:50:20 PM PDT 24
Peak memory 212876 kb
Host smart-e4c99b15-e9ce-4e93-bef7-b8677e6cea38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106241751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1106241751
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3449229349
Short name T9
Test name
Test status
Simulation time 536046053 ps
CPU time 6.47 seconds
Started Aug 03 04:50:08 PM PDT 24
Finished Aug 03 04:50:15 PM PDT 24
Peak memory 212128 kb
Host smart-4fdf3d47-4e9f-4795-bde3-eb6e614cda5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3449229349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3449229349
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.363094153
Short name T21
Test name
Test status
Simulation time 322633125 ps
CPU time 103.4 seconds
Started Aug 03 04:50:06 PM PDT 24
Finished Aug 03 04:51:49 PM PDT 24
Peak memory 238760 kb
Host smart-0614dcda-39a0-4b8b-bcea-9dce7e0d99ce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363094153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.363094153
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3833187297
Short name T192
Test name
Test status
Simulation time 99945288 ps
CPU time 5.84 seconds
Started Aug 03 04:50:07 PM PDT 24
Finished Aug 03 04:50:13 PM PDT 24
Peak memory 211960 kb
Host smart-e142cb40-d578-4598-baf7-4960e4fa89fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833187297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3833187297
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.434425882
Short name T98
Test name
Test status
Simulation time 250041633 ps
CPU time 12.25 seconds
Started Aug 03 04:50:17 PM PDT 24
Finished Aug 03 04:50:30 PM PDT 24
Peak memory 214116 kb
Host smart-b3b825b4-e2ea-4f8b-8da0-d29d0ecb4afd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434425882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.434425882
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3136710008
Short name T57
Test name
Test status
Simulation time 416056007 ps
CPU time 5.04 seconds
Started Aug 03 04:50:27 PM PDT 24
Finished Aug 03 04:50:32 PM PDT 24
Peak memory 212060 kb
Host smart-6aeae558-dafb-4c25-b332-32c162815b8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136710008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3136710008
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4027772988
Short name T261
Test name
Test status
Simulation time 2950409472 ps
CPU time 83.17 seconds
Started Aug 03 04:50:28 PM PDT 24
Finished Aug 03 04:51:51 PM PDT 24
Peak memory 238464 kb
Host smart-fd9dac96-9577-4bc6-8014-d540c54609b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027772988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.4027772988
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3596357626
Short name T239
Test name
Test status
Simulation time 256817301 ps
CPU time 11.33 seconds
Started Aug 03 04:50:35 PM PDT 24
Finished Aug 03 04:50:46 PM PDT 24
Peak memory 212888 kb
Host smart-1761bbb4-ce84-4cb4-8fd1-afd38307a451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596357626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3596357626
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3477802099
Short name T112
Test name
Test status
Simulation time 96080734 ps
CPU time 5.63 seconds
Started Aug 03 04:50:28 PM PDT 24
Finished Aug 03 04:50:33 PM PDT 24
Peak memory 212168 kb
Host smart-bb037e1c-a901-448f-8460-e4c3b5d1e520
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3477802099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3477802099
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3873027559
Short name T236
Test name
Test status
Simulation time 222734747 ps
CPU time 11.37 seconds
Started Aug 03 04:50:28 PM PDT 24
Finished Aug 03 04:50:40 PM PDT 24
Peak memory 214768 kb
Host smart-d2efaae0-38b9-4ca8-b3bf-a5b4664f156e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873027559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3873027559
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.4268500471
Short name T288
Test name
Test status
Simulation time 429467833 ps
CPU time 5.14 seconds
Started Aug 03 04:50:27 PM PDT 24
Finished Aug 03 04:50:32 PM PDT 24
Peak memory 212028 kb
Host smart-be0be1f3-1ea3-45d0-b79e-cbc4f7176b0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268500471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.4268500471
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3371489431
Short name T146
Test name
Test status
Simulation time 2022016724 ps
CPU time 112.79 seconds
Started Aug 03 04:50:29 PM PDT 24
Finished Aug 03 04:52:22 PM PDT 24
Peak memory 214348 kb
Host smart-73bcf841-b863-45e0-9bd9-db75966efda8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371489431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3371489431
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2887511470
Short name T25
Test name
Test status
Simulation time 2521176637 ps
CPU time 16.04 seconds
Started Aug 03 04:50:27 PM PDT 24
Finished Aug 03 04:50:44 PM PDT 24
Peak memory 213096 kb
Host smart-06d325d3-76cc-4c37-9403-cc17a68b9ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887511470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2887511470
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2436314161
Short name T222
Test name
Test status
Simulation time 137588095 ps
CPU time 6.54 seconds
Started Aug 03 04:50:27 PM PDT 24
Finished Aug 03 04:50:33 PM PDT 24
Peak memory 212128 kb
Host smart-665d9493-d832-4dee-a1b2-5dc707a1ba37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2436314161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2436314161
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.4058192876
Short name T298
Test name
Test status
Simulation time 175139456 ps
CPU time 6.49 seconds
Started Aug 03 04:50:25 PM PDT 24
Finished Aug 03 04:50:32 PM PDT 24
Peak memory 212092 kb
Host smart-5b7757d3-7ac2-4505-ac21-50e2b64a0148
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058192876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.4058192876
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3427208822
Short name T54
Test name
Test status
Simulation time 127039732256 ps
CPU time 1153.36 seconds
Started Aug 03 04:50:28 PM PDT 24
Finished Aug 03 05:09:42 PM PDT 24
Peak memory 236672 kb
Host smart-36f728b1-64f1-4a1c-9b02-1a7e89269434
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427208822 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.3427208822
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1142155985
Short name T182
Test name
Test status
Simulation time 380274514 ps
CPU time 4.23 seconds
Started Aug 03 04:50:25 PM PDT 24
Finished Aug 03 04:50:29 PM PDT 24
Peak memory 212040 kb
Host smart-d9114071-0c04-4f88-b99c-dfc4ac042e8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142155985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1142155985
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2303629591
Short name T235
Test name
Test status
Simulation time 3752239782 ps
CPU time 95.37 seconds
Started Aug 03 04:50:26 PM PDT 24
Finished Aug 03 04:52:02 PM PDT 24
Peak memory 229232 kb
Host smart-e32ab4c0-9517-4743-9dfb-e1846cc24a70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303629591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2303629591
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.151173879
Short name T162
Test name
Test status
Simulation time 379967238 ps
CPU time 11.06 seconds
Started Aug 03 04:50:26 PM PDT 24
Finished Aug 03 04:50:37 PM PDT 24
Peak memory 213364 kb
Host smart-fa6eaaf4-0720-4a5e-ab17-a6198e03f0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151173879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.151173879
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3586317472
Short name T221
Test name
Test status
Simulation time 2078276169 ps
CPU time 8.8 seconds
Started Aug 03 04:50:27 PM PDT 24
Finished Aug 03 04:50:35 PM PDT 24
Peak memory 212112 kb
Host smart-1c0450ea-e613-46de-8742-7d5109e4efd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3586317472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3586317472
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3096689168
Short name T99
Test name
Test status
Simulation time 331522092 ps
CPU time 22.11 seconds
Started Aug 03 04:50:25 PM PDT 24
Finished Aug 03 04:50:48 PM PDT 24
Peak memory 215996 kb
Host smart-979e4723-ae5a-4549-b6d7-2ff3aa265a0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096689168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3096689168
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.731499054
Short name T48
Test name
Test status
Simulation time 508343873729 ps
CPU time 1254.09 seconds
Started Aug 03 04:50:27 PM PDT 24
Finished Aug 03 05:11:21 PM PDT 24
Peak memory 230448 kb
Host smart-f8a9cfae-1352-4b0a-b1c9-889710ac8bc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731499054 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.731499054
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1271079900
Short name T274
Test name
Test status
Simulation time 131490421 ps
CPU time 5.15 seconds
Started Aug 03 04:50:26 PM PDT 24
Finished Aug 03 04:50:32 PM PDT 24
Peak memory 212036 kb
Host smart-57f174a5-953a-439f-964d-86a2257c612e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271079900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1271079900
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2722263787
Short name T130
Test name
Test status
Simulation time 10324090145 ps
CPU time 165.62 seconds
Started Aug 03 04:50:34 PM PDT 24
Finished Aug 03 04:53:20 PM PDT 24
Peak memory 238440 kb
Host smart-3d7a1b85-1dd6-487e-a6d4-89efea33f588
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722263787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2722263787
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3706707532
Short name T321
Test name
Test status
Simulation time 257348426 ps
CPU time 11.38 seconds
Started Aug 03 04:50:34 PM PDT 24
Finished Aug 03 04:50:45 PM PDT 24
Peak memory 212704 kb
Host smart-7d025fc4-13d1-4971-af50-afe4178678e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706707532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3706707532
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2446542217
Short name T151
Test name
Test status
Simulation time 828124042 ps
CPU time 5.66 seconds
Started Aug 03 04:50:26 PM PDT 24
Finished Aug 03 04:50:32 PM PDT 24
Peak memory 212188 kb
Host smart-ef783338-9eba-4aeb-8969-ccdb5de65bc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2446542217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2446542217
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.989652098
Short name T8
Test name
Test status
Simulation time 427875657 ps
CPU time 21.46 seconds
Started Aug 03 04:50:27 PM PDT 24
Finished Aug 03 04:50:48 PM PDT 24
Peak memory 214156 kb
Host smart-e2a309ee-2dd3-4123-9390-7979f091f49c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989652098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.989652098
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3894725320
Short name T191
Test name
Test status
Simulation time 127544027 ps
CPU time 4.99 seconds
Started Aug 03 04:50:27 PM PDT 24
Finished Aug 03 04:50:32 PM PDT 24
Peak memory 212020 kb
Host smart-9290fa96-9c15-41cf-9ad3-6ef190fe1872
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894725320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3894725320
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2476650355
Short name T38
Test name
Test status
Simulation time 2317763634 ps
CPU time 111.16 seconds
Started Aug 03 04:50:28 PM PDT 24
Finished Aug 03 04:52:19 PM PDT 24
Peak memory 237620 kb
Host smart-bd16111f-8339-46ca-ba27-670e94079f14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476650355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2476650355
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.870709416
Short name T28
Test name
Test status
Simulation time 303177052 ps
CPU time 5.55 seconds
Started Aug 03 04:50:27 PM PDT 24
Finished Aug 03 04:50:32 PM PDT 24
Peak memory 212092 kb
Host smart-ec9d1b10-d80d-491b-aa6d-06fb209f4410
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=870709416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.870709416
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3023465803
Short name T79
Test name
Test status
Simulation time 157812198 ps
CPU time 8.6 seconds
Started Aug 03 04:50:27 PM PDT 24
Finished Aug 03 04:50:35 PM PDT 24
Peak memory 212016 kb
Host smart-b1e7318d-73e7-4229-9647-39ea469854b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023465803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3023465803
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.205847547
Short name T286
Test name
Test status
Simulation time 39315027255 ps
CPU time 1593.78 seconds
Started Aug 03 04:50:28 PM PDT 24
Finished Aug 03 05:17:02 PM PDT 24
Peak memory 236648 kb
Host smart-40872f73-5e4c-4183-bb0d-1639143de70d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205847547 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.205847547
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3536509275
Short name T144
Test name
Test status
Simulation time 129358192 ps
CPU time 5.09 seconds
Started Aug 03 04:50:32 PM PDT 24
Finished Aug 03 04:50:37 PM PDT 24
Peak memory 212044 kb
Host smart-154d8cd0-bf9c-4410-b58e-5795619995c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536509275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3536509275
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1061278913
Short name T249
Test name
Test status
Simulation time 2777877011 ps
CPU time 149.93 seconds
Started Aug 03 04:50:32 PM PDT 24
Finished Aug 03 04:53:02 PM PDT 24
Peak memory 238060 kb
Host smart-5275a22d-4fbf-4c1b-82b4-8eb657f2c1a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061278913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1061278913
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3911300771
Short name T231
Test name
Test status
Simulation time 250828305 ps
CPU time 10.89 seconds
Started Aug 03 04:50:32 PM PDT 24
Finished Aug 03 04:50:43 PM PDT 24
Peak memory 212804 kb
Host smart-bfd12b24-85d4-4a4f-bfea-f4a3b56cbdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911300771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3911300771
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2918706185
Short name T209
Test name
Test status
Simulation time 99327828 ps
CPU time 5.26 seconds
Started Aug 03 04:50:32 PM PDT 24
Finished Aug 03 04:50:38 PM PDT 24
Peak memory 212172 kb
Host smart-9b46191d-64e7-419f-9a3a-9c26822d376f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2918706185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2918706185
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1805637287
Short name T135
Test name
Test status
Simulation time 2225562531 ps
CPU time 12.3 seconds
Started Aug 03 04:50:35 PM PDT 24
Finished Aug 03 04:50:47 PM PDT 24
Peak memory 213076 kb
Host smart-750c8c3e-8c2f-45ff-98ec-dec3b55992f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805637287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1805637287
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3026316706
Short name T181
Test name
Test status
Simulation time 89037783 ps
CPU time 4.33 seconds
Started Aug 03 04:50:36 PM PDT 24
Finished Aug 03 04:50:41 PM PDT 24
Peak memory 212048 kb
Host smart-3207c735-2ef3-4548-ab0a-be00d8ef4e11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026316706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3026316706
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1811284526
Short name T172
Test name
Test status
Simulation time 8950151402 ps
CPU time 146.14 seconds
Started Aug 03 04:50:31 PM PDT 24
Finished Aug 03 04:52:58 PM PDT 24
Peak memory 238396 kb
Host smart-4f7a3598-a1d9-4ef6-be33-b9e8ab710457
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811284526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1811284526
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.656248433
Short name T232
Test name
Test status
Simulation time 694224368 ps
CPU time 9.64 seconds
Started Aug 03 04:50:34 PM PDT 24
Finished Aug 03 04:50:44 PM PDT 24
Peak memory 212832 kb
Host smart-f02beaa0-9d85-43a9-9448-518b21e741d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656248433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.656248433
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3981055047
Short name T307
Test name
Test status
Simulation time 148020470 ps
CPU time 6.88 seconds
Started Aug 03 04:50:36 PM PDT 24
Finished Aug 03 04:50:43 PM PDT 24
Peak memory 212112 kb
Host smart-196a4d25-46f3-449f-815e-98e0d70e1c9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3981055047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3981055047
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3912451459
Short name T114
Test name
Test status
Simulation time 316632144 ps
CPU time 15.35 seconds
Started Aug 03 04:50:37 PM PDT 24
Finished Aug 03 04:50:53 PM PDT 24
Peak memory 215596 kb
Host smart-09b981f9-831b-423c-bdab-ae9cf36923b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912451459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3912451459
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.4151242555
Short name T101
Test name
Test status
Simulation time 462416059 ps
CPU time 4.23 seconds
Started Aug 03 04:50:33 PM PDT 24
Finished Aug 03 04:50:37 PM PDT 24
Peak memory 212028 kb
Host smart-b196de1f-f235-449d-bc27-c3d59d15280b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151242555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.4151242555
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2401779469
Short name T251
Test name
Test status
Simulation time 4065460851 ps
CPU time 134.05 seconds
Started Aug 03 04:50:33 PM PDT 24
Finished Aug 03 04:52:48 PM PDT 24
Peak memory 235856 kb
Host smart-418d5a8e-8d29-4675-af58-b786bde21546
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401779469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2401779469
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3522229950
Short name T160
Test name
Test status
Simulation time 4472188530 ps
CPU time 16.03 seconds
Started Aug 03 04:50:36 PM PDT 24
Finished Aug 03 04:50:52 PM PDT 24
Peak memory 213560 kb
Host smart-15723ec1-afe2-414c-9e98-a3c3d77e648b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522229950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3522229950
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2162550815
Short name T318
Test name
Test status
Simulation time 564614985 ps
CPU time 6.43 seconds
Started Aug 03 04:50:32 PM PDT 24
Finished Aug 03 04:50:39 PM PDT 24
Peak memory 212092 kb
Host smart-0ea721b4-1d68-4bf9-81d6-fbd5c951d34a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2162550815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2162550815
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1247277084
Short name T323
Test name
Test status
Simulation time 2801672636 ps
CPU time 21.68 seconds
Started Aug 03 04:50:35 PM PDT 24
Finished Aug 03 04:50:56 PM PDT 24
Peak memory 216608 kb
Host smart-ae759b93-93a6-4456-93e4-40f4ff19d84f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247277084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1247277084
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3052917666
Short name T224
Test name
Test status
Simulation time 88403098 ps
CPU time 4.27 seconds
Started Aug 03 04:50:32 PM PDT 24
Finished Aug 03 04:50:37 PM PDT 24
Peak memory 212216 kb
Host smart-94a12400-d45a-454e-a236-0490380209f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052917666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3052917666
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1174074427
Short name T284
Test name
Test status
Simulation time 4187444375 ps
CPU time 66.72 seconds
Started Aug 03 04:50:36 PM PDT 24
Finished Aug 03 04:51:43 PM PDT 24
Peak memory 238432 kb
Host smart-0f4dea02-5055-4880-b9a6-50f48ea5999f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174074427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1174074427
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3424310025
Short name T243
Test name
Test status
Simulation time 665868076 ps
CPU time 9.65 seconds
Started Aug 03 04:50:32 PM PDT 24
Finished Aug 03 04:50:42 PM PDT 24
Peak memory 212904 kb
Host smart-e1bfde1a-f512-4073-a174-91f34f205e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424310025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3424310025
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1638083924
Short name T152
Test name
Test status
Simulation time 369116032 ps
CPU time 5.31 seconds
Started Aug 03 04:50:32 PM PDT 24
Finished Aug 03 04:50:38 PM PDT 24
Peak memory 212168 kb
Host smart-00ae3978-734d-4f49-8d9c-3df883f08cac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1638083924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1638083924
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3328908118
Short name T115
Test name
Test status
Simulation time 1312906716 ps
CPU time 16.86 seconds
Started Aug 03 04:50:31 PM PDT 24
Finished Aug 03 04:50:48 PM PDT 24
Peak memory 215608 kb
Host smart-fd4ed2f5-c8d4-4b11-b2de-9f75fef2882f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328908118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3328908118
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3113909449
Short name T305
Test name
Test status
Simulation time 143945117 ps
CPU time 5.17 seconds
Started Aug 03 04:50:37 PM PDT 24
Finished Aug 03 04:50:43 PM PDT 24
Peak memory 211920 kb
Host smart-a7b86032-31d0-4f6a-bc2e-416a3cc56f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113909449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3113909449
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.237812474
Short name T30
Test name
Test status
Simulation time 2918181435 ps
CPU time 142.3 seconds
Started Aug 03 04:50:36 PM PDT 24
Finished Aug 03 04:52:58 PM PDT 24
Peak memory 226256 kb
Host smart-c356ce8e-3e81-427b-b342-d7c1a28dffc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237812474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.237812474
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1342937982
Short name T145
Test name
Test status
Simulation time 543094242 ps
CPU time 11.29 seconds
Started Aug 03 04:50:37 PM PDT 24
Finished Aug 03 04:50:48 PM PDT 24
Peak memory 212976 kb
Host smart-48a2726e-6c13-4efc-94fd-25ceb842ef62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342937982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1342937982
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1645246597
Short name T250
Test name
Test status
Simulation time 102593108 ps
CPU time 5.47 seconds
Started Aug 03 04:50:34 PM PDT 24
Finished Aug 03 04:50:40 PM PDT 24
Peak memory 212120 kb
Host smart-6d73409b-0037-437c-94c3-4891799b6135
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1645246597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1645246597
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3487153701
Short name T207
Test name
Test status
Simulation time 104471444 ps
CPU time 5.72 seconds
Started Aug 03 04:50:34 PM PDT 24
Finished Aug 03 04:50:40 PM PDT 24
Peak memory 212080 kb
Host smart-ff1da0ea-2434-4a53-a8b9-5cc76bfc1d4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487153701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3487153701
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1639723579
Short name T300
Test name
Test status
Simulation time 142263623151 ps
CPU time 1337.2 seconds
Started Aug 03 04:50:38 PM PDT 24
Finished Aug 03 05:12:56 PM PDT 24
Peak memory 236624 kb
Host smart-bf50b1be-af66-4705-b8b5-2d7b957354a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639723579 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1639723579
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3088228841
Short name T292
Test name
Test status
Simulation time 127258911 ps
CPU time 5.18 seconds
Started Aug 03 04:50:07 PM PDT 24
Finished Aug 03 04:50:12 PM PDT 24
Peak memory 211972 kb
Host smart-c172e0f1-debf-4995-a20b-745314f03705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088228841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3088228841
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1792400371
Short name T220
Test name
Test status
Simulation time 1856625945 ps
CPU time 90.89 seconds
Started Aug 03 04:50:06 PM PDT 24
Finished Aug 03 04:51:37 PM PDT 24
Peak memory 238396 kb
Host smart-a1e7c799-ffad-481e-9e59-52d6a8f50d9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792400371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1792400371
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.802535752
Short name T176
Test name
Test status
Simulation time 350367386 ps
CPU time 9.53 seconds
Started Aug 03 04:50:06 PM PDT 24
Finished Aug 03 04:50:16 PM PDT 24
Peak memory 212844 kb
Host smart-cb05d27e-be82-4445-8e29-aa9b87052a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802535752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.802535752
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.524342090
Short name T187
Test name
Test status
Simulation time 102289649 ps
CPU time 5.7 seconds
Started Aug 03 04:50:05 PM PDT 24
Finished Aug 03 04:50:11 PM PDT 24
Peak memory 212168 kb
Host smart-11e32d3a-8358-45f3-809c-edd8825dcfb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=524342090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.524342090
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.926176883
Short name T27
Test name
Test status
Simulation time 164497307 ps
CPU time 52.49 seconds
Started Aug 03 04:50:05 PM PDT 24
Finished Aug 03 04:50:58 PM PDT 24
Peak memory 238040 kb
Host smart-2485bde5-de51-4f52-9b79-8439178c2907
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926176883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.926176883
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3194767457
Short name T247
Test name
Test status
Simulation time 138522698 ps
CPU time 6.56 seconds
Started Aug 03 04:50:07 PM PDT 24
Finished Aug 03 04:50:14 PM PDT 24
Peak memory 212092 kb
Host smart-5f6bf67b-64eb-4cf2-8379-f51b2e32b415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194767457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3194767457
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2569081458
Short name T150
Test name
Test status
Simulation time 162821143 ps
CPU time 12.81 seconds
Started Aug 03 04:50:17 PM PDT 24
Finished Aug 03 04:50:30 PM PDT 24
Peak memory 212088 kb
Host smart-5b711ebf-7879-48cd-886a-25218a893da7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569081458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2569081458
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2603645142
Short name T53
Test name
Test status
Simulation time 133759770739 ps
CPU time 774.96 seconds
Started Aug 03 04:50:08 PM PDT 24
Finished Aug 03 05:03:03 PM PDT 24
Peak memory 236608 kb
Host smart-be9ac72b-278c-470d-a6f2-16b566710d9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603645142 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.2603645142
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3283004988
Short name T275
Test name
Test status
Simulation time 521451041 ps
CPU time 5.17 seconds
Started Aug 03 04:50:33 PM PDT 24
Finished Aug 03 04:50:39 PM PDT 24
Peak memory 212024 kb
Host smart-29ec3e26-af39-4a3f-be1f-1962741bf843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283004988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3283004988
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1733555058
Short name T215
Test name
Test status
Simulation time 1588707490 ps
CPU time 99.42 seconds
Started Aug 03 04:50:37 PM PDT 24
Finished Aug 03 04:52:16 PM PDT 24
Peak memory 213284 kb
Host smart-eafdb97e-777c-4e56-b644-485d1e153ab4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733555058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1733555058
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3585812143
Short name T260
Test name
Test status
Simulation time 696670579 ps
CPU time 9.33 seconds
Started Aug 03 04:50:32 PM PDT 24
Finished Aug 03 04:50:42 PM PDT 24
Peak memory 213012 kb
Host smart-cf6f1737-67c0-4b2d-8c4f-b0277c99ab8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585812143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3585812143
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3979196443
Short name T12
Test name
Test status
Simulation time 498388170 ps
CPU time 6.53 seconds
Started Aug 03 04:50:37 PM PDT 24
Finished Aug 03 04:50:44 PM PDT 24
Peak memory 212180 kb
Host smart-23efe1c8-3c83-4004-9213-782bb62ec84d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3979196443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3979196443
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.551521827
Short name T81
Test name
Test status
Simulation time 433230638 ps
CPU time 21.89 seconds
Started Aug 03 04:50:40 PM PDT 24
Finished Aug 03 04:51:02 PM PDT 24
Peak memory 214804 kb
Host smart-36f386b9-11cc-41f2-8c2c-0f692e22431e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551521827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.551521827
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2259756636
Short name T171
Test name
Test status
Simulation time 132844240 ps
CPU time 5.14 seconds
Started Aug 03 04:50:38 PM PDT 24
Finished Aug 03 04:50:44 PM PDT 24
Peak memory 212016 kb
Host smart-6b52fa8e-d7bc-4b87-88f4-80b2b199a871
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259756636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2259756636
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1075176137
Short name T211
Test name
Test status
Simulation time 1621892505 ps
CPU time 87.78 seconds
Started Aug 03 04:50:44 PM PDT 24
Finished Aug 03 04:52:12 PM PDT 24
Peak memory 228744 kb
Host smart-e0fcdfed-285a-4ef5-85eb-52408d4b8c6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075176137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1075176137
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3945194628
Short name T331
Test name
Test status
Simulation time 1465432046 ps
CPU time 11.49 seconds
Started Aug 03 04:50:40 PM PDT 24
Finished Aug 03 04:50:51 PM PDT 24
Peak memory 212820 kb
Host smart-803f7164-c652-4b2b-891e-2158b736be23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945194628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3945194628
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2882662145
Short name T10
Test name
Test status
Simulation time 1023910252 ps
CPU time 9.12 seconds
Started Aug 03 04:50:42 PM PDT 24
Finished Aug 03 04:50:51 PM PDT 24
Peak memory 212136 kb
Host smart-6be52019-2f50-42cd-90f4-0e6a1b19b783
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2882662145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2882662145
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2439046537
Short name T219
Test name
Test status
Simulation time 104693247 ps
CPU time 7.01 seconds
Started Aug 03 04:50:37 PM PDT 24
Finished Aug 03 04:50:44 PM PDT 24
Peak memory 212104 kb
Host smart-3df61a8b-72f6-48f4-8b6d-ca1badd59767
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439046537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2439046537
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1972890860
Short name T273
Test name
Test status
Simulation time 269045500 ps
CPU time 5.23 seconds
Started Aug 03 04:50:40 PM PDT 24
Finished Aug 03 04:50:45 PM PDT 24
Peak memory 212044 kb
Host smart-c5659674-a76a-449d-98e7-f6f95adf00f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972890860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1972890860
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.623729092
Short name T244
Test name
Test status
Simulation time 5084764464 ps
CPU time 65.53 seconds
Started Aug 03 04:50:38 PM PDT 24
Finished Aug 03 04:51:43 PM PDT 24
Peak memory 213448 kb
Host smart-9724db37-b248-4a0c-866c-b0090866737a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623729092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.623729092
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1642633969
Short name T299
Test name
Test status
Simulation time 172285684 ps
CPU time 9.58 seconds
Started Aug 03 04:50:39 PM PDT 24
Finished Aug 03 04:50:49 PM PDT 24
Peak memory 213192 kb
Host smart-8a857a19-b836-4c88-97cb-56ab51a96c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642633969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1642633969
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3113534313
Short name T131
Test name
Test status
Simulation time 101848362 ps
CPU time 5.5 seconds
Started Aug 03 04:50:38 PM PDT 24
Finished Aug 03 04:50:44 PM PDT 24
Peak memory 212164 kb
Host smart-a8408787-887d-4122-9ae1-eccb2705227e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3113534313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3113534313
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.401480437
Short name T139
Test name
Test status
Simulation time 341677289 ps
CPU time 10.14 seconds
Started Aug 03 04:50:40 PM PDT 24
Finished Aug 03 04:50:51 PM PDT 24
Peak memory 212732 kb
Host smart-a23737ee-ffa4-4d95-9485-3b21dfd157af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401480437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.401480437
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2386181113
Short name T185
Test name
Test status
Simulation time 87260379 ps
CPU time 4.29 seconds
Started Aug 03 04:50:38 PM PDT 24
Finished Aug 03 04:50:42 PM PDT 24
Peak memory 212020 kb
Host smart-63c13eba-e23f-4e30-83e0-06d9a6ec327b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386181113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2386181113
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1362066352
Short name T42
Test name
Test status
Simulation time 8746140880 ps
CPU time 94.43 seconds
Started Aug 03 04:50:38 PM PDT 24
Finished Aug 03 04:52:13 PM PDT 24
Peak memory 226252 kb
Host smart-22e605f3-49a7-4886-8533-aa4c63c65e0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362066352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1362066352
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2944463321
Short name T280
Test name
Test status
Simulation time 171349729 ps
CPU time 9.55 seconds
Started Aug 03 04:50:40 PM PDT 24
Finished Aug 03 04:50:50 PM PDT 24
Peak memory 212864 kb
Host smart-849929d5-ce1b-40d2-ae30-f4f4b76d2ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944463321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2944463321
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.158143640
Short name T238
Test name
Test status
Simulation time 206834415 ps
CPU time 6.3 seconds
Started Aug 03 04:50:41 PM PDT 24
Finished Aug 03 04:50:47 PM PDT 24
Peak memory 212156 kb
Host smart-f7ee7772-2e7b-488f-b1c6-9ce5a5a70dab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=158143640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.158143640
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2898621690
Short name T306
Test name
Test status
Simulation time 130795836 ps
CPU time 6.39 seconds
Started Aug 03 04:50:40 PM PDT 24
Finished Aug 03 04:50:47 PM PDT 24
Peak memory 212052 kb
Host smart-d31b3a96-3523-43ef-945e-fda2286aa6e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898621690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2898621690
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.998923501
Short name T51
Test name
Test status
Simulation time 13742869226 ps
CPU time 589.92 seconds
Started Aug 03 04:50:43 PM PDT 24
Finished Aug 03 05:00:33 PM PDT 24
Peak memory 232148 kb
Host smart-b47a79da-e62c-421b-82ae-e8926cdb4153
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998923501 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.998923501
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.432718141
Short name T170
Test name
Test status
Simulation time 200840242 ps
CPU time 4.32 seconds
Started Aug 03 04:50:39 PM PDT 24
Finished Aug 03 04:50:43 PM PDT 24
Peak memory 212060 kb
Host smart-dbb795fc-77ff-4c33-85bd-7d688d852042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432718141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.432718141
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.783384167
Short name T164
Test name
Test status
Simulation time 9398576996 ps
CPU time 174.77 seconds
Started Aug 03 04:50:39 PM PDT 24
Finished Aug 03 04:53:34 PM PDT 24
Peak memory 228892 kb
Host smart-28065779-cf9e-4752-913c-38ffddfef828
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783384167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.783384167
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2066514542
Short name T149
Test name
Test status
Simulation time 169532456 ps
CPU time 9.56 seconds
Started Aug 03 04:50:44 PM PDT 24
Finished Aug 03 04:50:53 PM PDT 24
Peak memory 212912 kb
Host smart-5c9146b5-46d7-45a6-9a3e-5fe3691420b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066514542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2066514542
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2992901941
Short name T205
Test name
Test status
Simulation time 140975400 ps
CPU time 6.39 seconds
Started Aug 03 04:50:38 PM PDT 24
Finished Aug 03 04:50:45 PM PDT 24
Peak memory 212140 kb
Host smart-f40d919c-b28f-4cc7-9116-eaf2cdbaa3aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2992901941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2992901941
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2556096756
Short name T18
Test name
Test status
Simulation time 512626752 ps
CPU time 13.78 seconds
Started Aug 03 04:50:38 PM PDT 24
Finished Aug 03 04:50:52 PM PDT 24
Peak memory 215908 kb
Host smart-d31134d9-2aed-4beb-8f5f-bc65db80b660
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556096756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2556096756
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2698115188
Short name T173
Test name
Test status
Simulation time 88904809 ps
CPU time 4.34 seconds
Started Aug 03 04:50:40 PM PDT 24
Finished Aug 03 04:50:44 PM PDT 24
Peak memory 212044 kb
Host smart-f545703f-b546-4064-b05a-2e68f2280091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698115188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2698115188
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2121511660
Short name T313
Test name
Test status
Simulation time 6477327208 ps
CPU time 91.14 seconds
Started Aug 03 04:50:41 PM PDT 24
Finished Aug 03 04:52:12 PM PDT 24
Peak memory 229256 kb
Host smart-0a0f908c-7393-4346-8525-fc596acc0222
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121511660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2121511660
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.817334342
Short name T141
Test name
Test status
Simulation time 269343540 ps
CPU time 11.32 seconds
Started Aug 03 04:50:43 PM PDT 24
Finished Aug 03 04:50:54 PM PDT 24
Peak memory 212884 kb
Host smart-36ef6275-70e4-48fc-967a-a3fd1654c443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817334342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.817334342
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.989849125
Short name T237
Test name
Test status
Simulation time 191196687 ps
CPU time 5.48 seconds
Started Aug 03 04:50:38 PM PDT 24
Finished Aug 03 04:50:44 PM PDT 24
Peak memory 212136 kb
Host smart-bf3866e0-c52e-4e95-981e-7a3ff7718c83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=989849125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.989849125
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3766060099
Short name T186
Test name
Test status
Simulation time 5093001926 ps
CPU time 17.48 seconds
Started Aug 03 04:50:39 PM PDT 24
Finished Aug 03 04:50:56 PM PDT 24
Peak memory 215996 kb
Host smart-dc68aacf-ecd9-462e-92fb-dc95b95ef811
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766060099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3766060099
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3980329344
Short name T278
Test name
Test status
Simulation time 694002420952 ps
CPU time 2076.27 seconds
Started Aug 03 04:50:42 PM PDT 24
Finished Aug 03 05:25:18 PM PDT 24
Peak memory 242952 kb
Host smart-8b565087-d0ec-47d6-ab76-3d5470472952
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980329344 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3980329344
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1952952411
Short name T309
Test name
Test status
Simulation time 127092888 ps
CPU time 5.22 seconds
Started Aug 03 04:50:49 PM PDT 24
Finished Aug 03 04:50:54 PM PDT 24
Peak memory 212048 kb
Host smart-20f6cab8-e2d9-4b9a-8eef-5f7fee20f10e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952952411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1952952411
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2908148841
Short name T199
Test name
Test status
Simulation time 4624382303 ps
CPU time 114.23 seconds
Started Aug 03 04:50:48 PM PDT 24
Finished Aug 03 04:52:42 PM PDT 24
Peak memory 234404 kb
Host smart-d7a510a1-1e8f-4ca8-a056-e620363780f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908148841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2908148841
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2605234850
Short name T179
Test name
Test status
Simulation time 171553458 ps
CPU time 9.25 seconds
Started Aug 03 04:50:49 PM PDT 24
Finished Aug 03 04:50:58 PM PDT 24
Peak memory 212888 kb
Host smart-c9b2e146-116f-4eb1-9aa7-1636c71062fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605234850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2605234850
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.4002643896
Short name T153
Test name
Test status
Simulation time 199688892 ps
CPU time 5.71 seconds
Started Aug 03 04:50:47 PM PDT 24
Finished Aug 03 04:50:53 PM PDT 24
Peak memory 212092 kb
Host smart-d3e4443a-4231-40cc-ac53-aac7c8eaf53e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4002643896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.4002643896
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.4287772663
Short name T36
Test name
Test status
Simulation time 1141824555 ps
CPU time 13.43 seconds
Started Aug 03 04:50:46 PM PDT 24
Finished Aug 03 04:51:00 PM PDT 24
Peak memory 213960 kb
Host smart-53044df0-4d9c-4d80-9a05-61b5285c6f26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287772663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.4287772663
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3307694433
Short name T223
Test name
Test status
Simulation time 131999505 ps
CPU time 5.14 seconds
Started Aug 03 04:50:47 PM PDT 24
Finished Aug 03 04:50:52 PM PDT 24
Peak memory 212028 kb
Host smart-c1f4a57b-362f-4f3b-82c0-3373608cec55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307694433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3307694433
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3420588607
Short name T43
Test name
Test status
Simulation time 38647083126 ps
CPU time 190.85 seconds
Started Aug 03 04:50:50 PM PDT 24
Finished Aug 03 04:54:01 PM PDT 24
Peak memory 214464 kb
Host smart-7f6b134d-e193-496f-9fa7-a6410e2be9ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420588607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3420588607
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2812732917
Short name T258
Test name
Test status
Simulation time 1308261741 ps
CPU time 11.48 seconds
Started Aug 03 04:50:45 PM PDT 24
Finished Aug 03 04:50:57 PM PDT 24
Peak memory 212820 kb
Host smart-aa180e85-bb38-438d-ba38-bbcb94cacd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812732917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2812732917
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.658572174
Short name T283
Test name
Test status
Simulation time 298083101 ps
CPU time 6.55 seconds
Started Aug 03 04:50:46 PM PDT 24
Finished Aug 03 04:50:53 PM PDT 24
Peak memory 212112 kb
Host smart-0861bf73-c186-428b-8566-404b53134fba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=658572174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.658572174
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2224424105
Short name T155
Test name
Test status
Simulation time 282014556 ps
CPU time 14.86 seconds
Started Aug 03 04:50:48 PM PDT 24
Finished Aug 03 04:51:03 PM PDT 24
Peak memory 215388 kb
Host smart-34683471-e3cb-4ce1-b1ba-d88cd6ac4250
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224424105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2224424105
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1892406749
Short name T3
Test name
Test status
Simulation time 261671848 ps
CPU time 5.1 seconds
Started Aug 03 04:50:48 PM PDT 24
Finished Aug 03 04:50:53 PM PDT 24
Peak memory 212044 kb
Host smart-d0a9d195-331a-4c9e-85f5-801c4e77f834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892406749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1892406749
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.279696351
Short name T212
Test name
Test status
Simulation time 7236725589 ps
CPU time 89.76 seconds
Started Aug 03 04:50:45 PM PDT 24
Finished Aug 03 04:52:15 PM PDT 24
Peak memory 214652 kb
Host smart-83d32eba-c773-4d2e-b1d9-b5cf7986710d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279696351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.279696351
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1091250260
Short name T180
Test name
Test status
Simulation time 692889138 ps
CPU time 9.5 seconds
Started Aug 03 04:50:46 PM PDT 24
Finished Aug 03 04:50:56 PM PDT 24
Peak memory 213064 kb
Host smart-dbb578b8-2097-4a85-94fc-3db6c1ff50ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091250260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1091250260
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1223611640
Short name T245
Test name
Test status
Simulation time 97393998 ps
CPU time 5.46 seconds
Started Aug 03 04:50:46 PM PDT 24
Finished Aug 03 04:50:51 PM PDT 24
Peak memory 212152 kb
Host smart-0de0c0e4-dcfd-4b5d-ace9-6243f564f7a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223611640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1223611640
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3577570195
Short name T1
Test name
Test status
Simulation time 271649762 ps
CPU time 14.7 seconds
Started Aug 03 04:50:49 PM PDT 24
Finished Aug 03 04:51:04 PM PDT 24
Peak memory 214632 kb
Host smart-8dec0346-c04c-40c6-8c9e-f2a553300a1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577570195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3577570195
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.23924802
Short name T136
Test name
Test status
Simulation time 363124514 ps
CPU time 4.41 seconds
Started Aug 03 04:50:52 PM PDT 24
Finished Aug 03 04:50:56 PM PDT 24
Peak memory 212008 kb
Host smart-6aa31b12-1581-4cc3-9bce-ef831409edca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23924802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.23924802
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2634624645
Short name T304
Test name
Test status
Simulation time 6898358749 ps
CPU time 109.4 seconds
Started Aug 03 04:50:47 PM PDT 24
Finished Aug 03 04:52:37 PM PDT 24
Peak memory 238408 kb
Host smart-43aa4ef4-258b-4fe2-abc8-d4e7a03107b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634624645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2634624645
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3230030354
Short name T248
Test name
Test status
Simulation time 169644984 ps
CPU time 9.52 seconds
Started Aug 03 04:50:46 PM PDT 24
Finished Aug 03 04:50:56 PM PDT 24
Peak memory 212912 kb
Host smart-ed66e1b5-8429-4ae3-bfbb-277a57f02ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230030354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3230030354
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1075359468
Short name T168
Test name
Test status
Simulation time 289160449 ps
CPU time 6.61 seconds
Started Aug 03 04:50:46 PM PDT 24
Finished Aug 03 04:50:52 PM PDT 24
Peak memory 212156 kb
Host smart-861a809f-c966-4f80-8de1-3f9303fbc174
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1075359468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1075359468
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1200490450
Short name T34
Test name
Test status
Simulation time 551675638 ps
CPU time 16.43 seconds
Started Aug 03 04:50:51 PM PDT 24
Finished Aug 03 04:51:08 PM PDT 24
Peak memory 215436 kb
Host smart-70111a2a-e0a2-483b-a765-4b5f12baf0f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200490450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1200490450
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2511100538
Short name T218
Test name
Test status
Simulation time 245910854 ps
CPU time 5.05 seconds
Started Aug 03 04:50:17 PM PDT 24
Finished Aug 03 04:50:22 PM PDT 24
Peak memory 212036 kb
Host smart-98d422c0-12c5-4556-accd-f0d2a39fa61c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511100538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2511100538
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.879100636
Short name T132
Test name
Test status
Simulation time 1356805163 ps
CPU time 80.51 seconds
Started Aug 03 04:50:07 PM PDT 24
Finished Aug 03 04:51:28 PM PDT 24
Peak memory 238352 kb
Host smart-b66e8f44-48cf-4cfc-bc38-1863dfdce2fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879100636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.879100636
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2260391033
Short name T290
Test name
Test status
Simulation time 1034371964 ps
CPU time 11.29 seconds
Started Aug 03 04:50:08 PM PDT 24
Finished Aug 03 04:50:19 PM PDT 24
Peak memory 212660 kb
Host smart-9945a7bc-f39d-4023-84c5-f7ad79fbf6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260391033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2260391033
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.58245915
Short name T282
Test name
Test status
Simulation time 547646548 ps
CPU time 6.71 seconds
Started Aug 03 04:50:07 PM PDT 24
Finished Aug 03 04:50:14 PM PDT 24
Peak memory 212092 kb
Host smart-34266bc6-975a-40b5-97d8-1b5c3b2ae1e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58245915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.58245915
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.74951245
Short name T26
Test name
Test status
Simulation time 543720992 ps
CPU time 51.54 seconds
Started Aug 03 04:50:05 PM PDT 24
Finished Aug 03 04:50:57 PM PDT 24
Peak memory 238448 kb
Host smart-35905044-ce5a-4bf6-b02d-7802106913c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74951245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.74951245
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1749975872
Short name T198
Test name
Test status
Simulation time 138539892 ps
CPU time 6.59 seconds
Started Aug 03 04:50:06 PM PDT 24
Finished Aug 03 04:50:13 PM PDT 24
Peak memory 212140 kb
Host smart-898fd056-d5d5-4d41-a83f-bc5bde7d981f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749975872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1749975872
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3428756177
Short name T229
Test name
Test status
Simulation time 243991648 ps
CPU time 6.29 seconds
Started Aug 03 04:50:08 PM PDT 24
Finished Aug 03 04:50:14 PM PDT 24
Peak memory 212008 kb
Host smart-232ef489-4ed1-44f1-bcdd-ac84c47fa399
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428756177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3428756177
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3957082448
Short name T133
Test name
Test status
Simulation time 521758286 ps
CPU time 5.2 seconds
Started Aug 03 04:50:53 PM PDT 24
Finished Aug 03 04:50:58 PM PDT 24
Peak memory 211972 kb
Host smart-559f9326-d94c-403f-abc6-966c0d7d71bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957082448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3957082448
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2138708958
Short name T37
Test name
Test status
Simulation time 2854541178 ps
CPU time 143.64 seconds
Started Aug 03 04:50:57 PM PDT 24
Finished Aug 03 04:53:20 PM PDT 24
Peak memory 225704 kb
Host smart-284c985c-1df2-4ba6-945b-5da715ea2934
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138708958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2138708958
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2143135453
Short name T188
Test name
Test status
Simulation time 1037449963 ps
CPU time 11.23 seconds
Started Aug 03 04:50:54 PM PDT 24
Finished Aug 03 04:51:06 PM PDT 24
Peak memory 212916 kb
Host smart-b58be5fd-7f3d-431c-8552-d2ad3aaa6c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143135453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2143135453
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1272207690
Short name T55
Test name
Test status
Simulation time 274535657 ps
CPU time 14.89 seconds
Started Aug 03 04:50:53 PM PDT 24
Finished Aug 03 04:51:08 PM PDT 24
Peak memory 216040 kb
Host smart-c576ac52-fc41-4f84-93a4-54612bdc399f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272207690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1272207690
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.594161572
Short name T143
Test name
Test status
Simulation time 498421251 ps
CPU time 5.05 seconds
Started Aug 03 04:50:52 PM PDT 24
Finished Aug 03 04:50:58 PM PDT 24
Peak memory 212040 kb
Host smart-3b73e8f0-c909-483a-8942-28d852b5fe02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594161572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.594161572
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.24846430
Short name T47
Test name
Test status
Simulation time 177541071 ps
CPU time 9.56 seconds
Started Aug 03 04:50:54 PM PDT 24
Finished Aug 03 04:51:04 PM PDT 24
Peak memory 212880 kb
Host smart-6a379fe0-f9d2-46b9-a222-fa5be9265064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24846430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.24846430
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2016732616
Short name T147
Test name
Test status
Simulation time 97029990 ps
CPU time 5.4 seconds
Started Aug 03 04:50:55 PM PDT 24
Finished Aug 03 04:51:00 PM PDT 24
Peak memory 212116 kb
Host smart-6437ee0e-942c-45f7-a659-6932388706fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2016732616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2016732616
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1997701980
Short name T166
Test name
Test status
Simulation time 841714655 ps
CPU time 11 seconds
Started Aug 03 04:50:53 PM PDT 24
Finished Aug 03 04:51:04 PM PDT 24
Peak memory 215336 kb
Host smart-8a8652b3-3bee-4bc7-a9dd-7ba35cce256c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997701980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1997701980
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.449633777
Short name T137
Test name
Test status
Simulation time 497880382 ps
CPU time 5.02 seconds
Started Aug 03 04:50:55 PM PDT 24
Finished Aug 03 04:51:00 PM PDT 24
Peak memory 211956 kb
Host smart-7469b7fa-199c-4556-bcc3-5b8827884010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449633777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.449633777
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.76842792
Short name T266
Test name
Test status
Simulation time 3801600619 ps
CPU time 73.52 seconds
Started Aug 03 04:50:52 PM PDT 24
Finished Aug 03 04:52:06 PM PDT 24
Peak memory 234384 kb
Host smart-ab8352ea-c9ce-480f-8f91-9ed489c98067
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76842792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_co
rrupt_sig_fatal_chk.76842792
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.4181231463
Short name T264
Test name
Test status
Simulation time 173996635 ps
CPU time 9.45 seconds
Started Aug 03 04:50:55 PM PDT 24
Finished Aug 03 04:51:05 PM PDT 24
Peak memory 212872 kb
Host smart-67f9908e-5a2a-4f45-ae6b-dc187d9995f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181231463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.4181231463
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.352514585
Short name T320
Test name
Test status
Simulation time 271096862 ps
CPU time 6.27 seconds
Started Aug 03 04:50:52 PM PDT 24
Finished Aug 03 04:50:58 PM PDT 24
Peak memory 212108 kb
Host smart-aa9ff3b9-8bf6-457e-b3e1-7fa150ba953c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=352514585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.352514585
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.988940792
Short name T230
Test name
Test status
Simulation time 420850801 ps
CPU time 19.85 seconds
Started Aug 03 04:50:53 PM PDT 24
Finished Aug 03 04:51:13 PM PDT 24
Peak memory 215272 kb
Host smart-75cbb18f-d36a-4c2c-ae2a-85dbd7646141
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988940792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.988940792
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.802369370
Short name T303
Test name
Test status
Simulation time 41877001782 ps
CPU time 8357.93 seconds
Started Aug 03 04:50:54 PM PDT 24
Finished Aug 03 07:10:13 PM PDT 24
Peak memory 228468 kb
Host smart-f13bfef7-6a2d-4a26-a9a6-9c00717f7630
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802369370 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.802369370
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1297256273
Short name T252
Test name
Test status
Simulation time 518516432 ps
CPU time 5.21 seconds
Started Aug 03 04:50:53 PM PDT 24
Finished Aug 03 04:50:58 PM PDT 24
Peak memory 212048 kb
Host smart-fb851298-3b2b-4ea6-83d3-91205d855b62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297256273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1297256273
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2796356895
Short name T214
Test name
Test status
Simulation time 887598005 ps
CPU time 76.58 seconds
Started Aug 03 04:50:53 PM PDT 24
Finished Aug 03 04:52:10 PM PDT 24
Peak memory 238308 kb
Host smart-5f85be1b-85df-49ed-8723-60d1bcb361b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796356895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2796356895
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.83088390
Short name T277
Test name
Test status
Simulation time 350335997 ps
CPU time 9.59 seconds
Started Aug 03 04:50:55 PM PDT 24
Finished Aug 03 04:51:05 PM PDT 24
Peak memory 212896 kb
Host smart-d2b6977d-1681-44ef-b5e5-e77f913f718d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83088390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.83088390
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.399894838
Short name T140
Test name
Test status
Simulation time 137216747 ps
CPU time 6.7 seconds
Started Aug 03 04:50:53 PM PDT 24
Finished Aug 03 04:50:59 PM PDT 24
Peak memory 212120 kb
Host smart-82418f52-b592-4800-9cd4-216f4313d0ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=399894838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.399894838
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.894461446
Short name T134
Test name
Test status
Simulation time 127363883 ps
CPU time 8.03 seconds
Started Aug 03 04:50:52 PM PDT 24
Finished Aug 03 04:51:01 PM PDT 24
Peak memory 212244 kb
Host smart-d158c190-ce64-429e-93ff-b5027808841b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894461446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.894461446
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1393593812
Short name T174
Test name
Test status
Simulation time 90304016 ps
CPU time 4.36 seconds
Started Aug 03 04:50:53 PM PDT 24
Finished Aug 03 04:50:57 PM PDT 24
Peak memory 212028 kb
Host smart-c8ec08ce-d8ca-4976-9a0c-46f68ee94daf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393593812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1393593812
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.474455723
Short name T316
Test name
Test status
Simulation time 3263351490 ps
CPU time 52.22 seconds
Started Aug 03 04:50:51 PM PDT 24
Finished Aug 03 04:51:44 PM PDT 24
Peak memory 238356 kb
Host smart-9428f1f0-d2f7-4c97-abfd-878422815144
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474455723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.474455723
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2854561625
Short name T234
Test name
Test status
Simulation time 170886623 ps
CPU time 9.59 seconds
Started Aug 03 04:50:53 PM PDT 24
Finished Aug 03 04:51:03 PM PDT 24
Peak memory 213228 kb
Host smart-fe2eba75-7b4c-4319-a624-d27faceef076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854561625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2854561625
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2464102337
Short name T302
Test name
Test status
Simulation time 376525602 ps
CPU time 5.39 seconds
Started Aug 03 04:50:55 PM PDT 24
Finished Aug 03 04:51:01 PM PDT 24
Peak memory 212136 kb
Host smart-947e8c69-8cbf-4566-b3bf-2d1d9c007ece
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2464102337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2464102337
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2482592602
Short name T312
Test name
Test status
Simulation time 375237237 ps
CPU time 15.64 seconds
Started Aug 03 04:50:55 PM PDT 24
Finished Aug 03 04:51:11 PM PDT 24
Peak memory 213340 kb
Host smart-76e57e52-3d52-4070-b737-257a58c87c8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482592602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2482592602
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.4027623105
Short name T233
Test name
Test status
Simulation time 520641202 ps
CPU time 5.07 seconds
Started Aug 03 04:51:02 PM PDT 24
Finished Aug 03 04:51:07 PM PDT 24
Peak memory 212044 kb
Host smart-009916d9-368f-4546-a790-9c59d133f402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027623105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.4027623105
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1800032565
Short name T41
Test name
Test status
Simulation time 3226474609 ps
CPU time 169.11 seconds
Started Aug 03 04:51:06 PM PDT 24
Finished Aug 03 04:53:55 PM PDT 24
Peak memory 238488 kb
Host smart-9ba4b316-f16b-47a5-b00a-8c6ef8a8a59c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800032565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1800032565
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1025894213
Short name T44
Test name
Test status
Simulation time 327673625 ps
CPU time 9.72 seconds
Started Aug 03 04:50:58 PM PDT 24
Finished Aug 03 04:51:08 PM PDT 24
Peak memory 212904 kb
Host smart-9844fa99-dce7-4238-b90d-c26329fa4d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025894213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1025894213
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.252841691
Short name T167
Test name
Test status
Simulation time 140866860 ps
CPU time 6.74 seconds
Started Aug 03 04:50:53 PM PDT 24
Finished Aug 03 04:50:59 PM PDT 24
Peak memory 212160 kb
Host smart-b6ff2e61-146c-4ab7-b33c-f1db7cea9302
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=252841691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.252841691
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2593853229
Short name T165
Test name
Test status
Simulation time 162033304 ps
CPU time 11.43 seconds
Started Aug 03 04:50:53 PM PDT 24
Finished Aug 03 04:51:05 PM PDT 24
Peak memory 213072 kb
Host smart-df0aa84b-814e-42b3-a7bb-f500ad6161e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593853229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2593853229
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3667429080
Short name T22
Test name
Test status
Simulation time 349383721 ps
CPU time 4.27 seconds
Started Aug 03 04:51:02 PM PDT 24
Finished Aug 03 04:51:07 PM PDT 24
Peak memory 212044 kb
Host smart-44c8dee6-325f-427a-9e9a-3228414aa5ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667429080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3667429080
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.315390959
Short name T262
Test name
Test status
Simulation time 1517255970 ps
CPU time 101.77 seconds
Started Aug 03 04:50:59 PM PDT 24
Finished Aug 03 04:52:41 PM PDT 24
Peak memory 238356 kb
Host smart-1cc8ce7d-6f8f-448a-b31e-2384e1476aaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315390959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.315390959
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.341454787
Short name T45
Test name
Test status
Simulation time 723452729 ps
CPU time 9.65 seconds
Started Aug 03 04:51:00 PM PDT 24
Finished Aug 03 04:51:10 PM PDT 24
Peak memory 212888 kb
Host smart-a6cf038d-329d-4121-91bd-35431d2ccfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341454787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.341454787
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.639206382
Short name T329
Test name
Test status
Simulation time 564028251 ps
CPU time 6.73 seconds
Started Aug 03 04:51:00 PM PDT 24
Finished Aug 03 04:51:07 PM PDT 24
Peak memory 212144 kb
Host smart-98f15c4b-1736-4e4b-b853-6b4403bb3c76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=639206382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.639206382
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3739141321
Short name T35
Test name
Test status
Simulation time 8464893149 ps
CPU time 25.5 seconds
Started Aug 03 04:51:00 PM PDT 24
Finished Aug 03 04:51:25 PM PDT 24
Peak memory 216968 kb
Host smart-c9e14dcf-3be7-46f1-a15a-1c6433c69b2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739141321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3739141321
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2455417706
Short name T314
Test name
Test status
Simulation time 110972344816 ps
CPU time 8407.2 seconds
Started Aug 03 04:50:59 PM PDT 24
Finished Aug 03 07:11:07 PM PDT 24
Peak memory 236656 kb
Host smart-8e9cc92d-2833-47c5-8cde-e421bdb41cdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455417706 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.2455417706
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2694121417
Short name T177
Test name
Test status
Simulation time 522337610 ps
CPU time 5.02 seconds
Started Aug 03 04:51:00 PM PDT 24
Finished Aug 03 04:51:05 PM PDT 24
Peak memory 211952 kb
Host smart-0f4945bc-b3f9-4e54-a991-eb8fc45a45c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694121417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2694121417
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1700300012
Short name T322
Test name
Test status
Simulation time 9598904230 ps
CPU time 95.14 seconds
Started Aug 03 04:50:59 PM PDT 24
Finished Aug 03 04:52:34 PM PDT 24
Peak memory 238232 kb
Host smart-dcf86c6d-467f-4865-a558-e598caf47057
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700300012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1700300012
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3397093806
Short name T184
Test name
Test status
Simulation time 581028504 ps
CPU time 11.33 seconds
Started Aug 03 04:50:58 PM PDT 24
Finished Aug 03 04:51:09 PM PDT 24
Peak memory 212892 kb
Host smart-6114e4c6-f478-49a6-94ec-b1a6892341fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397093806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3397093806
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1525207377
Short name T154
Test name
Test status
Simulation time 143183849 ps
CPU time 6.63 seconds
Started Aug 03 04:50:59 PM PDT 24
Finished Aug 03 04:51:05 PM PDT 24
Peak memory 212132 kb
Host smart-6a3d507a-7b8a-46c5-9622-a819c5eded5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1525207377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1525207377
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.851164353
Short name T78
Test name
Test status
Simulation time 122044462 ps
CPU time 6.21 seconds
Started Aug 03 04:51:06 PM PDT 24
Finished Aug 03 04:51:13 PM PDT 24
Peak memory 212112 kb
Host smart-64e0db8f-cb7c-426f-bb2e-70421e621053
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851164353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.851164353
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.4288304687
Short name T116
Test name
Test status
Simulation time 44840132702 ps
CPU time 5146.78 seconds
Started Aug 03 04:51:00 PM PDT 24
Finished Aug 03 06:16:48 PM PDT 24
Peak memory 230880 kb
Host smart-0c924d83-67e2-49d5-b1b6-167d91c3923f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288304687 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.4288304687
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.864023203
Short name T213
Test name
Test status
Simulation time 171750205 ps
CPU time 4.34 seconds
Started Aug 03 04:50:59 PM PDT 24
Finished Aug 03 04:51:04 PM PDT 24
Peak memory 211976 kb
Host smart-922128b3-9896-4b45-aeac-e9be01b578a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864023203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.864023203
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3379609318
Short name T289
Test name
Test status
Simulation time 5798951435 ps
CPU time 81.99 seconds
Started Aug 03 04:51:03 PM PDT 24
Finished Aug 03 04:52:25 PM PDT 24
Peak memory 238500 kb
Host smart-16b7a018-805b-421a-8eb9-d215e315965a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379609318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3379609318
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1230513747
Short name T203
Test name
Test status
Simulation time 1664332484 ps
CPU time 9.43 seconds
Started Aug 03 04:51:00 PM PDT 24
Finished Aug 03 04:51:10 PM PDT 24
Peak memory 213232 kb
Host smart-9d49e010-6aa7-48fc-9441-3f695d26ee24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230513747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1230513747
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3364419518
Short name T327
Test name
Test status
Simulation time 556317216 ps
CPU time 6.41 seconds
Started Aug 03 04:51:01 PM PDT 24
Finished Aug 03 04:51:08 PM PDT 24
Peak memory 212084 kb
Host smart-47015299-90cf-48c5-b3f0-ad62a921d189
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3364419518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3364419518
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2697862222
Short name T109
Test name
Test status
Simulation time 250381749 ps
CPU time 7.71 seconds
Started Aug 03 04:51:01 PM PDT 24
Finished Aug 03 04:51:09 PM PDT 24
Peak memory 212092 kb
Host smart-172ce3e0-0bf1-4c89-a091-d21b5f0ab98e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697862222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2697862222
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1513601958
Short name T148
Test name
Test status
Simulation time 127205706 ps
CPU time 5.15 seconds
Started Aug 03 04:51:03 PM PDT 24
Finished Aug 03 04:51:08 PM PDT 24
Peak memory 212044 kb
Host smart-8566ffbb-ac34-40c5-8406-8387f9a1508f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513601958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1513601958
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.4267218966
Short name T206
Test name
Test status
Simulation time 19504840514 ps
CPU time 153.1 seconds
Started Aug 03 04:51:00 PM PDT 24
Finished Aug 03 04:53:33 PM PDT 24
Peak memory 238492 kb
Host smart-046c4a3f-4573-4e79-92c0-dce831d59db1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267218966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.4267218966
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.601957735
Short name T242
Test name
Test status
Simulation time 671204445 ps
CPU time 9.6 seconds
Started Aug 03 04:51:01 PM PDT 24
Finished Aug 03 04:51:11 PM PDT 24
Peak memory 212908 kb
Host smart-111874f0-894e-48c5-b29a-c15370fec956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601957735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.601957735
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.504234057
Short name T159
Test name
Test status
Simulation time 100377137 ps
CPU time 5.51 seconds
Started Aug 03 04:50:59 PM PDT 24
Finished Aug 03 04:51:05 PM PDT 24
Peak memory 212180 kb
Host smart-c35180f4-8ab3-4f0e-88bc-068b85603232
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=504234057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.504234057
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3244716881
Short name T272
Test name
Test status
Simulation time 905147530 ps
CPU time 18.72 seconds
Started Aug 03 04:51:01 PM PDT 24
Finished Aug 03 04:51:20 PM PDT 24
Peak memory 217124 kb
Host smart-51e73af0-e4e4-40ab-a85e-7f39fc60c0ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244716881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3244716881
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2563328453
Short name T158
Test name
Test status
Simulation time 88095999 ps
CPU time 4.22 seconds
Started Aug 03 04:50:15 PM PDT 24
Finished Aug 03 04:50:19 PM PDT 24
Peak memory 211916 kb
Host smart-1919112b-73c0-47f0-9979-4dd917be5018
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563328453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2563328453
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2104045067
Short name T281
Test name
Test status
Simulation time 2589348519 ps
CPU time 81.26 seconds
Started Aug 03 04:50:07 PM PDT 24
Finished Aug 03 04:51:29 PM PDT 24
Peak memory 235412 kb
Host smart-e44817a7-cae0-4e3d-a4f3-6b5a3dfa7220
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104045067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2104045067
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4232411377
Short name T324
Test name
Test status
Simulation time 925524921 ps
CPU time 10.99 seconds
Started Aug 03 04:50:06 PM PDT 24
Finished Aug 03 04:50:18 PM PDT 24
Peak memory 212944 kb
Host smart-38df27f8-67cf-45fc-bd2d-61d4b40ff07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232411377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.4232411377
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.64955803
Short name T291
Test name
Test status
Simulation time 191226746 ps
CPU time 5.39 seconds
Started Aug 03 04:50:05 PM PDT 24
Finished Aug 03 04:50:11 PM PDT 24
Peak memory 212124 kb
Host smart-dde569fd-3065-476d-a527-b5c6fb80bd1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64955803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.64955803
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.4283352075
Short name T257
Test name
Test status
Simulation time 1296242719 ps
CPU time 6.39 seconds
Started Aug 03 04:50:07 PM PDT 24
Finished Aug 03 04:50:13 PM PDT 24
Peak memory 212180 kb
Host smart-7282ade8-d759-4f64-a39f-057dfd9ad3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283352075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.4283352075
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3790152384
Short name T82
Test name
Test status
Simulation time 1626566731 ps
CPU time 19.07 seconds
Started Aug 03 04:50:06 PM PDT 24
Finished Aug 03 04:50:25 PM PDT 24
Peak memory 215492 kb
Host smart-b6feac6b-1fa7-47ba-8053-620fc4c3ec3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790152384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3790152384
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1385607030
Short name T49
Test name
Test status
Simulation time 131655556810 ps
CPU time 1398.32 seconds
Started Aug 03 04:50:20 PM PDT 24
Finished Aug 03 05:13:38 PM PDT 24
Peak memory 236604 kb
Host smart-d5249e24-6adf-4c5d-a2d5-67a972b8680e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385607030 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.1385607030
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1978398718
Short name T216
Test name
Test status
Simulation time 254791489 ps
CPU time 5.21 seconds
Started Aug 03 04:50:17 PM PDT 24
Finished Aug 03 04:50:22 PM PDT 24
Peak memory 211968 kb
Host smart-f0cadbaa-1ee5-431d-bbfa-275c40589e70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978398718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1978398718
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2643307306
Short name T142
Test name
Test status
Simulation time 10977829821 ps
CPU time 138.83 seconds
Started Aug 03 04:50:16 PM PDT 24
Finished Aug 03 04:52:35 PM PDT 24
Peak memory 226032 kb
Host smart-2636a8b5-e9a8-4530-9817-469fa32ef8e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643307306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2643307306
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2381133378
Short name T169
Test name
Test status
Simulation time 342824948 ps
CPU time 9.55 seconds
Started Aug 03 04:50:19 PM PDT 24
Finished Aug 03 04:50:29 PM PDT 24
Peak memory 212876 kb
Host smart-a03be195-a661-4e07-b58e-66595edd1c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381133378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2381133378
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3728987438
Short name T276
Test name
Test status
Simulation time 193967419 ps
CPU time 5.8 seconds
Started Aug 03 04:50:13 PM PDT 24
Finished Aug 03 04:50:19 PM PDT 24
Peak memory 212132 kb
Host smart-321bef9f-7cc2-4a15-bda1-52b4aed0ff7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3728987438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3728987438
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3571468290
Short name T285
Test name
Test status
Simulation time 2079005343 ps
CPU time 8.54 seconds
Started Aug 03 04:50:16 PM PDT 24
Finished Aug 03 04:50:24 PM PDT 24
Peak memory 212324 kb
Host smart-3c876796-dd68-4918-8144-a257a8e6a4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571468290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3571468290
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2756034770
Short name T246
Test name
Test status
Simulation time 1508723226 ps
CPU time 19.68 seconds
Started Aug 03 04:50:18 PM PDT 24
Finished Aug 03 04:50:38 PM PDT 24
Peak memory 215164 kb
Host smart-382f81ad-fee9-4c8c-a386-27322929948f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756034770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2756034770
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.537201594
Short name T268
Test name
Test status
Simulation time 122362351201 ps
CPU time 8422.71 seconds
Started Aug 03 04:50:14 PM PDT 24
Finished Aug 03 07:10:37 PM PDT 24
Peak memory 236660 kb
Host smart-74992e57-4755-4b29-a5fb-2a2add2e9d55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537201594 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.537201594
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2398225988
Short name T100
Test name
Test status
Simulation time 335880525 ps
CPU time 4.28 seconds
Started Aug 03 04:50:16 PM PDT 24
Finished Aug 03 04:50:20 PM PDT 24
Peak memory 211952 kb
Host smart-927bf3ee-2c20-40bc-b41a-ab3e32134de0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398225988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2398225988
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1106023194
Short name T157
Test name
Test status
Simulation time 2759383150 ps
CPU time 175.99 seconds
Started Aug 03 04:50:17 PM PDT 24
Finished Aug 03 04:53:13 PM PDT 24
Peak memory 238472 kb
Host smart-8e1c15c9-f1ae-472e-b835-df58c87e5c04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106023194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1106023194
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3290343316
Short name T194
Test name
Test status
Simulation time 2053777110 ps
CPU time 15.56 seconds
Started Aug 03 04:50:17 PM PDT 24
Finished Aug 03 04:50:33 PM PDT 24
Peak memory 213220 kb
Host smart-a03c92a9-2006-426b-9149-e64917b349e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290343316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3290343316
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2506326267
Short name T156
Test name
Test status
Simulation time 1469296351 ps
CPU time 6.55 seconds
Started Aug 03 04:50:15 PM PDT 24
Finished Aug 03 04:50:22 PM PDT 24
Peak memory 212116 kb
Host smart-1f416eec-8449-4f49-9454-66b59acd811a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2506326267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2506326267
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3339516955
Short name T226
Test name
Test status
Simulation time 326342134 ps
CPU time 6.72 seconds
Started Aug 03 04:50:15 PM PDT 24
Finished Aug 03 04:50:22 PM PDT 24
Peak memory 212160 kb
Host smart-9980a456-8a9b-4a9c-89b2-b71e9862cd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339516955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3339516955
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1325055156
Short name T254
Test name
Test status
Simulation time 568569885 ps
CPU time 12.74 seconds
Started Aug 03 04:50:15 PM PDT 24
Finished Aug 03 04:50:28 PM PDT 24
Peak memory 213332 kb
Host smart-9253cda9-9db8-4398-a8a2-57aad7d32bac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325055156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1325055156
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3693936572
Short name T15
Test name
Test status
Simulation time 56417710741 ps
CPU time 1946.3 seconds
Started Aug 03 04:50:14 PM PDT 24
Finished Aug 03 05:22:41 PM PDT 24
Peak memory 236636 kb
Host smart-216432af-3e11-454d-b5d4-570d34457fad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693936572 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3693936572
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3449286740
Short name T240
Test name
Test status
Simulation time 126570453 ps
CPU time 5.22 seconds
Started Aug 03 04:50:15 PM PDT 24
Finished Aug 03 04:50:21 PM PDT 24
Peak memory 212036 kb
Host smart-1fe212ad-0c14-4273-8e61-86ae9cc48951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449286740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3449286740
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.272353055
Short name T39
Test name
Test status
Simulation time 39012612321 ps
CPU time 138.24 seconds
Started Aug 03 04:50:19 PM PDT 24
Finished Aug 03 04:52:37 PM PDT 24
Peak memory 213368 kb
Host smart-9fa733bc-910d-4783-a092-fca7aceb9be3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272353055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.272353055
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.897219461
Short name T2
Test name
Test status
Simulation time 2363904505 ps
CPU time 9.48 seconds
Started Aug 03 04:50:19 PM PDT 24
Finished Aug 03 04:50:28 PM PDT 24
Peak memory 212880 kb
Host smart-1019b2d8-d696-4f64-ae53-0b10e64495e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897219461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.897219461
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2483580168
Short name T328
Test name
Test status
Simulation time 181682774 ps
CPU time 5.53 seconds
Started Aug 03 04:50:19 PM PDT 24
Finished Aug 03 04:50:25 PM PDT 24
Peak memory 212120 kb
Host smart-b1b45638-d469-416f-b8ec-81f407158df6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2483580168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2483580168
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2129701902
Short name T279
Test name
Test status
Simulation time 724982964 ps
CPU time 5.56 seconds
Started Aug 03 04:50:16 PM PDT 24
Finished Aug 03 04:50:21 PM PDT 24
Peak memory 212128 kb
Host smart-60f4a3d3-90c1-41a7-824e-817963525ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129701902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2129701902
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1736776342
Short name T80
Test name
Test status
Simulation time 1619476570 ps
CPU time 14.33 seconds
Started Aug 03 04:50:16 PM PDT 24
Finished Aug 03 04:50:31 PM PDT 24
Peak memory 215920 kb
Host smart-f1215b82-0235-40b0-9fa6-509e6a754657
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736776342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1736776342
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3195067504
Short name T255
Test name
Test status
Simulation time 18778867543 ps
CPU time 722.13 seconds
Started Aug 03 04:50:21 PM PDT 24
Finished Aug 03 05:02:23 PM PDT 24
Peak memory 226420 kb
Host smart-3333be39-8caf-4acd-bb6d-86841639f722
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195067504 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3195067504
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2900696235
Short name T138
Test name
Test status
Simulation time 131167328 ps
CPU time 5.41 seconds
Started Aug 03 04:50:17 PM PDT 24
Finished Aug 03 04:50:23 PM PDT 24
Peak memory 212004 kb
Host smart-694f944f-d19a-4a29-af53-05fee32b007f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900696235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2900696235
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1835712436
Short name T202
Test name
Test status
Simulation time 3305767046 ps
CPU time 154.28 seconds
Started Aug 03 04:50:17 PM PDT 24
Finished Aug 03 04:52:52 PM PDT 24
Peak memory 213404 kb
Host smart-379032fd-d61e-4bdd-8614-013183f52308
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835712436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1835712436
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4199747975
Short name T190
Test name
Test status
Simulation time 1843915631 ps
CPU time 9.52 seconds
Started Aug 03 04:50:19 PM PDT 24
Finished Aug 03 04:50:28 PM PDT 24
Peak memory 212816 kb
Host smart-ab13a4ad-3224-4b88-9be0-af82d7da4422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199747975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4199747975
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3663935732
Short name T241
Test name
Test status
Simulation time 138838753 ps
CPU time 6.61 seconds
Started Aug 03 04:50:21 PM PDT 24
Finished Aug 03 04:50:28 PM PDT 24
Peak memory 212108 kb
Host smart-0796a704-705a-46ec-bf09-1437c8bf5c88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3663935732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3663935732
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.268327288
Short name T77
Test name
Test status
Simulation time 504345861 ps
CPU time 6.44 seconds
Started Aug 03 04:50:14 PM PDT 24
Finished Aug 03 04:50:21 PM PDT 24
Peak memory 212060 kb
Host smart-81aaabab-9971-4316-b783-476c0c580e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268327288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.268327288
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.968396271
Short name T5
Test name
Test status
Simulation time 155919775 ps
CPU time 8.14 seconds
Started Aug 03 04:50:15 PM PDT 24
Finished Aug 03 04:50:24 PM PDT 24
Peak memory 212100 kb
Host smart-2fb70308-65f6-4a42-8dfa-48ceae75478c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968396271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.968396271
Directory /workspace/9.rom_ctrl_stress_all/latest
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