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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.29 96.89 91.99 97.67 100.00 98.62 97.45 98.37


Total test records in report: 411
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T296 /workspace/coverage/default/46.rom_ctrl_alert_test.1927918687 Aug 04 05:29:38 PM PDT 24 Aug 04 05:29:43 PM PDT 24 129622621 ps
T297 /workspace/coverage/default/5.rom_ctrl_smoke.624368342 Aug 04 05:29:09 PM PDT 24 Aug 04 05:29:19 PM PDT 24 524486827 ps
T298 /workspace/coverage/default/16.rom_ctrl_stress_all.1337969619 Aug 04 05:29:28 PM PDT 24 Aug 04 05:29:40 PM PDT 24 893421993 ps
T299 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2642489183 Aug 04 05:29:17 PM PDT 24 Aug 04 05:29:24 PM PDT 24 294063260 ps
T300 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.951668978 Aug 04 05:29:27 PM PDT 24 Aug 04 05:29:33 PM PDT 24 463056840 ps
T301 /workspace/coverage/default/1.rom_ctrl_alert_test.3316297453 Aug 04 05:29:20 PM PDT 24 Aug 04 05:29:24 PM PDT 24 346348178 ps
T302 /workspace/coverage/default/42.rom_ctrl_stress_all.3391104246 Aug 04 05:29:29 PM PDT 24 Aug 04 05:29:39 PM PDT 24 1496859427 ps
T303 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2377741495 Aug 04 05:29:27 PM PDT 24 Aug 04 05:29:34 PM PDT 24 136547762 ps
T304 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1348160959 Aug 04 05:29:40 PM PDT 24 Aug 04 05:31:31 PM PDT 24 17500458302 ps
T305 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.798769755 Aug 04 05:29:26 PM PDT 24 Aug 04 05:29:32 PM PDT 24 527047393 ps
T306 /workspace/coverage/default/43.rom_ctrl_alert_test.693739285 Aug 04 05:29:36 PM PDT 24 Aug 04 05:29:41 PM PDT 24 86696530 ps
T307 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.4049160112 Aug 04 05:29:38 PM PDT 24 Aug 04 05:31:37 PM PDT 24 9941745446 ps
T308 /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.222532885 Aug 04 05:29:27 PM PDT 24 Aug 04 05:48:16 PM PDT 24 168884346673 ps
T309 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1409437165 Aug 04 05:29:27 PM PDT 24 Aug 04 05:29:38 PM PDT 24 1777625984 ps
T310 /workspace/coverage/default/7.rom_ctrl_alert_test.1126000740 Aug 04 05:29:22 PM PDT 24 Aug 04 05:29:26 PM PDT 24 336472673 ps
T311 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.261053996 Aug 04 05:29:39 PM PDT 24 Aug 04 05:29:49 PM PDT 24 363465417 ps
T312 /workspace/coverage/default/10.rom_ctrl_stress_all.1888468446 Aug 04 05:29:25 PM PDT 24 Aug 04 05:29:39 PM PDT 24 281414872 ps
T313 /workspace/coverage/default/29.rom_ctrl_stress_all.1714788830 Aug 04 05:29:30 PM PDT 24 Aug 04 05:29:42 PM PDT 24 771908503 ps
T314 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1835464105 Aug 04 05:29:36 PM PDT 24 Aug 04 05:29:45 PM PDT 24 1390890825 ps
T315 /workspace/coverage/default/6.rom_ctrl_alert_test.2239102575 Aug 04 05:29:15 PM PDT 24 Aug 04 05:29:20 PM PDT 24 127011673 ps
T316 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.180706594 Aug 04 05:29:29 PM PDT 24 Aug 04 05:30:36 PM PDT 24 18103031903 ps
T317 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2990178830 Aug 04 05:29:28 PM PDT 24 Aug 04 05:29:35 PM PDT 24 260106139 ps
T318 /workspace/coverage/default/44.rom_ctrl_alert_test.513633338 Aug 04 05:29:38 PM PDT 24 Aug 04 05:29:42 PM PDT 24 1038408100 ps
T319 /workspace/coverage/default/18.rom_ctrl_stress_all.4291271743 Aug 04 05:29:27 PM PDT 24 Aug 04 05:29:39 PM PDT 24 226285982 ps
T320 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.809324925 Aug 04 05:29:04 PM PDT 24 Aug 04 08:05:08 PM PDT 24 44087390559 ps
T321 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.212084879 Aug 04 05:29:31 PM PDT 24 Aug 04 05:29:40 PM PDT 24 173203468 ps
T322 /workspace/coverage/default/5.rom_ctrl_stress_all.2456140116 Aug 04 05:29:25 PM PDT 24 Aug 04 05:29:45 PM PDT 24 636272060 ps
T323 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3281683221 Aug 04 05:29:28 PM PDT 24 Aug 04 05:29:34 PM PDT 24 563462221 ps
T324 /workspace/coverage/default/13.rom_ctrl_alert_test.415566120 Aug 04 05:29:27 PM PDT 24 Aug 04 05:29:32 PM PDT 24 95975709 ps
T325 /workspace/coverage/default/1.rom_ctrl_smoke.2135421687 Aug 04 05:29:11 PM PDT 24 Aug 04 05:29:17 PM PDT 24 181548016 ps
T326 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.563073869 Aug 04 05:27:37 PM PDT 24 Aug 04 05:27:42 PM PDT 24 86647790 ps
T327 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2318021511 Aug 04 05:27:31 PM PDT 24 Aug 04 05:27:39 PM PDT 24 85823989 ps
T51 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3773504863 Aug 04 05:27:46 PM PDT 24 Aug 04 05:27:50 PM PDT 24 351430643 ps
T48 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2501151140 Aug 04 05:27:39 PM PDT 24 Aug 04 05:28:48 PM PDT 24 258210522 ps
T52 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2518729101 Aug 04 05:27:46 PM PDT 24 Aug 04 05:27:51 PM PDT 24 523194933 ps
T54 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2487378751 Aug 04 05:27:44 PM PDT 24 Aug 04 05:28:03 PM PDT 24 383610939 ps
T328 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1083486100 Aug 04 05:27:45 PM PDT 24 Aug 04 05:27:50 PM PDT 24 624764489 ps
T89 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.797422499 Aug 04 05:27:49 PM PDT 24 Aug 04 05:27:54 PM PDT 24 499901439 ps
T329 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1863433800 Aug 04 05:27:30 PM PDT 24 Aug 04 05:27:35 PM PDT 24 521524225 ps
T55 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1739820235 Aug 04 05:27:46 PM PDT 24 Aug 04 05:27:53 PM PDT 24 880970325 ps
T330 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3965848418 Aug 04 05:27:48 PM PDT 24 Aug 04 05:27:54 PM PDT 24 264464060 ps
T95 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2085146335 Aug 04 05:27:48 PM PDT 24 Aug 04 05:27:53 PM PDT 24 500461371 ps
T331 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3763191696 Aug 04 05:27:37 PM PDT 24 Aug 04 05:27:42 PM PDT 24 256436771 ps
T332 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2827075372 Aug 04 05:27:47 PM PDT 24 Aug 04 05:27:52 PM PDT 24 350743896 ps
T96 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2724897372 Aug 04 05:27:46 PM PDT 24 Aug 04 05:27:50 PM PDT 24 85442173 ps
T56 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.280054702 Aug 04 05:27:34 PM PDT 24 Aug 04 05:27:39 PM PDT 24 141081905 ps
T333 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3033687808 Aug 04 05:27:47 PM PDT 24 Aug 04 05:27:52 PM PDT 24 129927249 ps
T49 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4139888928 Aug 04 05:27:48 PM PDT 24 Aug 04 05:28:24 PM PDT 24 288153839 ps
T57 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3577586670 Aug 04 05:27:47 PM PDT 24 Aug 04 05:27:52 PM PDT 24 954998365 ps
T97 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2213544967 Aug 04 05:27:42 PM PDT 24 Aug 04 05:27:47 PM PDT 24 88868183 ps
T90 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4176882284 Aug 04 05:27:49 PM PDT 24 Aug 04 05:27:54 PM PDT 24 133389135 ps
T58 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2402646148 Aug 04 05:27:46 PM PDT 24 Aug 04 05:27:50 PM PDT 24 168744522 ps
T91 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3252443754 Aug 04 05:27:29 PM PDT 24 Aug 04 05:27:34 PM PDT 24 562867439 ps
T92 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3575551583 Aug 04 05:28:00 PM PDT 24 Aug 04 05:28:04 PM PDT 24 176102115 ps
T334 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1172193406 Aug 04 05:27:49 PM PDT 24 Aug 04 05:27:55 PM PDT 24 131157980 ps
T59 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1683153460 Aug 04 05:27:57 PM PDT 24 Aug 04 05:28:03 PM PDT 24 454421378 ps
T335 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3179949777 Aug 04 05:27:45 PM PDT 24 Aug 04 05:27:54 PM PDT 24 960315825 ps
T336 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2719665351 Aug 04 05:27:45 PM PDT 24 Aug 04 05:27:50 PM PDT 24 523448045 ps
T50 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3655564283 Aug 04 05:27:46 PM PDT 24 Aug 04 05:28:24 PM PDT 24 244673495 ps
T60 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2001388667 Aug 04 05:27:35 PM PDT 24 Aug 04 05:27:41 PM PDT 24 498539537 ps
T61 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2428566873 Aug 04 05:27:30 PM PDT 24 Aug 04 05:27:38 PM PDT 24 133165223 ps
T93 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.249914437 Aug 04 05:27:49 PM PDT 24 Aug 04 05:27:55 PM PDT 24 997363588 ps
T337 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1603564088 Aug 04 05:27:33 PM PDT 24 Aug 04 05:27:45 PM PDT 24 494101378 ps
T62 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.29483502 Aug 04 05:27:34 PM PDT 24 Aug 04 05:27:39 PM PDT 24 253406976 ps
T338 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2138699579 Aug 04 05:27:45 PM PDT 24 Aug 04 05:27:51 PM PDT 24 1060472614 ps
T339 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3903274960 Aug 04 05:27:45 PM PDT 24 Aug 04 05:27:51 PM PDT 24 87532923 ps
T340 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2978340179 Aug 04 05:27:55 PM PDT 24 Aug 04 05:28:00 PM PDT 24 391762481 ps
T106 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3847367643 Aug 04 05:27:50 PM PDT 24 Aug 04 05:28:27 PM PDT 24 325896362 ps
T114 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2166159073 Aug 04 05:27:47 PM PDT 24 Aug 04 05:28:58 PM PDT 24 227051837 ps
T341 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2505471492 Aug 04 05:27:55 PM PDT 24 Aug 04 05:28:03 PM PDT 24 135929509 ps
T342 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2326907715 Aug 04 05:27:30 PM PDT 24 Aug 04 05:27:36 PM PDT 24 250089945 ps
T343 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.184298959 Aug 04 05:27:48 PM PDT 24 Aug 04 05:27:58 PM PDT 24 369262971 ps
T344 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1655170923 Aug 04 05:27:34 PM PDT 24 Aug 04 05:27:38 PM PDT 24 347891882 ps
T109 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2739522055 Aug 04 05:27:50 PM PDT 24 Aug 04 05:28:59 PM PDT 24 898429891 ps
T94 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2025893840 Aug 04 05:27:33 PM PDT 24 Aug 04 05:27:38 PM PDT 24 89200650 ps
T116 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.509441273 Aug 04 05:27:42 PM PDT 24 Aug 04 05:28:20 PM PDT 24 202976312 ps
T345 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3846241762 Aug 04 05:27:33 PM PDT 24 Aug 04 05:27:39 PM PDT 24 127888668 ps
T72 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.766167610 Aug 04 05:27:44 PM PDT 24 Aug 04 05:27:49 PM PDT 24 500238658 ps
T73 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2302640101 Aug 04 05:27:47 PM PDT 24 Aug 04 05:28:06 PM PDT 24 374620677 ps
T346 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.220542545 Aug 04 05:27:43 PM PDT 24 Aug 04 05:27:52 PM PDT 24 256157537 ps
T347 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.551599999 Aug 04 05:27:34 PM PDT 24 Aug 04 05:27:39 PM PDT 24 514099969 ps
T348 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1154823949 Aug 04 05:27:48 PM PDT 24 Aug 04 05:27:56 PM PDT 24 90404580 ps
T349 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.707612179 Aug 04 05:27:44 PM PDT 24 Aug 04 05:27:50 PM PDT 24 176755349 ps
T74 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3347757951 Aug 04 05:27:38 PM PDT 24 Aug 04 05:27:45 PM PDT 24 1730784172 ps
T350 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2575809669 Aug 04 05:27:34 PM PDT 24 Aug 04 05:27:38 PM PDT 24 322262686 ps
T351 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2941333598 Aug 04 05:27:47 PM PDT 24 Aug 04 05:27:52 PM PDT 24 89136751 ps
T352 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2549727193 Aug 04 05:27:46 PM PDT 24 Aug 04 05:27:51 PM PDT 24 501271153 ps
T353 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.845659627 Aug 04 05:27:48 PM PDT 24 Aug 04 05:27:54 PM PDT 24 282055479 ps
T354 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.832865361 Aug 04 05:27:43 PM PDT 24 Aug 04 05:27:48 PM PDT 24 400322309 ps
T355 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3114331721 Aug 04 05:27:46 PM PDT 24 Aug 04 05:28:14 PM PDT 24 550100609 ps
T356 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3492326851 Aug 04 05:27:45 PM PDT 24 Aug 04 05:27:51 PM PDT 24 1093930181 ps
T357 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1128369108 Aug 04 05:28:00 PM PDT 24 Aug 04 05:28:04 PM PDT 24 171151906 ps
T358 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2960133309 Aug 04 05:27:44 PM PDT 24 Aug 04 05:27:49 PM PDT 24 545342425 ps
T359 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.326605826 Aug 04 05:27:44 PM PDT 24 Aug 04 05:27:49 PM PDT 24 593803087 ps
T360 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2068869268 Aug 04 05:27:33 PM PDT 24 Aug 04 05:27:38 PM PDT 24 171188342 ps
T361 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1204444133 Aug 04 05:27:32 PM PDT 24 Aug 04 05:27:40 PM PDT 24 2037409842 ps
T110 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1094984600 Aug 04 05:27:42 PM PDT 24 Aug 04 05:29:01 PM PDT 24 791983453 ps
T104 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4188484256 Aug 04 05:27:50 PM PDT 24 Aug 04 05:28:00 PM PDT 24 438845629 ps
T362 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1358413127 Aug 04 05:27:55 PM PDT 24 Aug 04 05:28:00 PM PDT 24 136778046 ps
T363 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.684233863 Aug 04 05:27:38 PM PDT 24 Aug 04 05:27:46 PM PDT 24 348232839 ps
T364 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2825292846 Aug 04 05:27:51 PM PDT 24 Aug 04 05:27:58 PM PDT 24 126439044 ps
T365 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3189579190 Aug 04 05:27:46 PM PDT 24 Aug 04 05:27:53 PM PDT 24 95538752 ps
T366 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.315405002 Aug 04 05:27:48 PM PDT 24 Aug 04 05:27:52 PM PDT 24 85783902 ps
T115 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2731077262 Aug 04 05:27:30 PM PDT 24 Aug 04 05:28:39 PM PDT 24 1116824798 ps
T367 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3276406622 Aug 04 05:27:31 PM PDT 24 Aug 04 05:27:35 PM PDT 24 88999331 ps
T368 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.947527236 Aug 04 05:27:44 PM PDT 24 Aug 04 05:27:49 PM PDT 24 355946121 ps
T117 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1861951332 Aug 04 05:27:50 PM PDT 24 Aug 04 05:28:27 PM PDT 24 1185681686 ps
T369 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2356750653 Aug 04 05:27:34 PM PDT 24 Aug 04 05:27:39 PM PDT 24 86463054 ps
T370 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3189355718 Aug 04 05:27:33 PM PDT 24 Aug 04 05:27:38 PM PDT 24 292169166 ps
T371 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4171139441 Aug 04 05:27:49 PM PDT 24 Aug 04 05:27:54 PM PDT 24 498556598 ps
T372 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1041958860 Aug 04 05:27:45 PM PDT 24 Aug 04 05:27:51 PM PDT 24 556772469 ps
T373 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1637137700 Aug 04 05:27:53 PM PDT 24 Aug 04 05:28:04 PM PDT 24 827539805 ps
T374 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1612185687 Aug 04 05:27:48 PM PDT 24 Aug 04 05:27:53 PM PDT 24 101159303 ps
T375 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1085647492 Aug 04 05:27:41 PM PDT 24 Aug 04 05:27:45 PM PDT 24 157808115 ps
T75 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1176796614 Aug 04 05:27:48 PM PDT 24 Aug 04 05:27:53 PM PDT 24 522058980 ps
T376 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3943672225 Aug 04 05:27:46 PM PDT 24 Aug 04 05:27:50 PM PDT 24 88863439 ps
T377 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2860305186 Aug 04 05:27:50 PM PDT 24 Aug 04 05:27:57 PM PDT 24 1270321908 ps
T378 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.810455584 Aug 04 05:27:48 PM PDT 24 Aug 04 05:27:54 PM PDT 24 415578688 ps
T379 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1967891389 Aug 04 05:27:34 PM PDT 24 Aug 04 05:27:39 PM PDT 24 298267384 ps
T380 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2449470510 Aug 04 05:27:51 PM PDT 24 Aug 04 05:28:00 PM PDT 24 263585554 ps
T381 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1478987566 Aug 04 05:27:30 PM PDT 24 Aug 04 05:27:35 PM PDT 24 382171968 ps
T76 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.727240899 Aug 04 05:27:35 PM PDT 24 Aug 04 05:27:40 PM PDT 24 130268270 ps
T382 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1176089673 Aug 04 05:27:47 PM PDT 24 Aug 04 05:27:52 PM PDT 24 1544469859 ps
T383 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1965169563 Aug 04 05:27:39 PM PDT 24 Aug 04 05:27:46 PM PDT 24 95998426 ps
T111 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.207018867 Aug 04 05:27:39 PM PDT 24 Aug 04 05:28:19 PM PDT 24 580739565 ps
T107 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1239440269 Aug 04 05:27:48 PM PDT 24 Aug 04 05:29:08 PM PDT 24 2237274235 ps
T108 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3443532650 Aug 04 05:27:33 PM PDT 24 Aug 04 05:28:45 PM PDT 24 350596632 ps
T384 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2377001876 Aug 04 05:27:45 PM PDT 24 Aug 04 05:27:53 PM PDT 24 131341254 ps
T385 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1104775572 Aug 04 05:27:34 PM PDT 24 Aug 04 05:28:44 PM PDT 24 974146192 ps
T386 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3017601845 Aug 04 05:27:30 PM PDT 24 Aug 04 05:27:35 PM PDT 24 362898161 ps
T118 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2599581876 Aug 04 05:27:48 PM PDT 24 Aug 04 05:28:26 PM PDT 24 3133727362 ps
T387 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1247212102 Aug 04 05:27:49 PM PDT 24 Aug 04 05:27:55 PM PDT 24 138873252 ps
T388 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1015649760 Aug 04 05:27:49 PM PDT 24 Aug 04 05:27:58 PM PDT 24 271713091 ps
T389 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.484083673 Aug 04 05:27:43 PM PDT 24 Aug 04 05:27:51 PM PDT 24 516417116 ps
T390 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3067030684 Aug 04 05:27:48 PM PDT 24 Aug 04 05:27:53 PM PDT 24 521182997 ps
T391 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2641022312 Aug 04 05:27:35 PM PDT 24 Aug 04 05:27:54 PM PDT 24 1426363235 ps
T392 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3560957719 Aug 04 05:27:51 PM PDT 24 Aug 04 05:27:55 PM PDT 24 85887628 ps
T78 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.292670400 Aug 04 05:27:50 PM PDT 24 Aug 04 05:28:17 PM PDT 24 2160143466 ps
T393 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3883037168 Aug 04 05:27:33 PM PDT 24 Aug 04 05:27:52 PM PDT 24 375002281 ps
T112 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1196622155 Aug 04 05:27:48 PM PDT 24 Aug 04 05:28:25 PM PDT 24 329662309 ps
T394 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1776261521 Aug 04 05:27:51 PM PDT 24 Aug 04 05:28:29 PM PDT 24 383891597 ps
T113 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.6977742 Aug 04 05:27:50 PM PDT 24 Aug 04 05:28:29 PM PDT 24 2259778585 ps
T395 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1961926415 Aug 04 05:27:30 PM PDT 24 Aug 04 05:27:34 PM PDT 24 334106255 ps
T396 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3917579126 Aug 04 05:27:49 PM PDT 24 Aug 04 05:27:56 PM PDT 24 127871054 ps
T79 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2213477077 Aug 04 05:27:45 PM PDT 24 Aug 04 05:27:50 PM PDT 24 349684109 ps
T397 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.133859800 Aug 04 05:27:48 PM PDT 24 Aug 04 05:27:53 PM PDT 24 97772750 ps
T398 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3429430168 Aug 04 05:27:46 PM PDT 24 Aug 04 05:27:53 PM PDT 24 524422185 ps
T399 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2602245833 Aug 04 05:27:45 PM PDT 24 Aug 04 05:27:50 PM PDT 24 90072735 ps
T400 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.135678846 Aug 04 05:27:50 PM PDT 24 Aug 04 05:27:57 PM PDT 24 273394800 ps
T401 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.110457910 Aug 04 05:27:36 PM PDT 24 Aug 04 05:27:46 PM PDT 24 305896412 ps
T402 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.42590198 Aug 04 05:27:32 PM PDT 24 Aug 04 05:27:37 PM PDT 24 542314032 ps
T403 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2400705309 Aug 04 05:27:45 PM PDT 24 Aug 04 05:28:21 PM PDT 24 537455217 ps
T404 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3912804999 Aug 04 05:27:55 PM PDT 24 Aug 04 05:28:38 PM PDT 24 331974145 ps
T405 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2412750256 Aug 04 05:27:50 PM PDT 24 Aug 04 05:27:54 PM PDT 24 90152773 ps
T406 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2296968944 Aug 04 05:27:49 PM PDT 24 Aug 04 05:28:00 PM PDT 24 159711873 ps
T407 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1590425861 Aug 04 05:27:56 PM PDT 24 Aug 04 05:28:02 PM PDT 24 853094133 ps
T408 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1272724670 Aug 04 05:27:46 PM PDT 24 Aug 04 05:27:53 PM PDT 24 673889262 ps
T409 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2143451954 Aug 04 05:27:46 PM PDT 24 Aug 04 05:27:53 PM PDT 24 282714599 ps
T77 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4275467970 Aug 04 05:27:29 PM PDT 24 Aug 04 05:27:36 PM PDT 24 1254461311 ps
T410 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1844785415 Aug 04 05:27:29 PM PDT 24 Aug 04 05:27:35 PM PDT 24 108229603 ps
T411 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1510447390 Aug 04 05:27:45 PM PDT 24 Aug 04 05:27:53 PM PDT 24 7002227565 ps

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2336776044
Short name T6
Test name
Test status
Simulation time 65572528747 ps
CPU time 616.27 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:39:45 PM PDT 24
Peak memory 236564 kb
Host smart-3dbd7fc7-ba3f-4666-9c1a-ca55108539fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336776044 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2336776044
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2605971792
Short name T2
Test name
Test status
Simulation time 6549106736 ps
CPU time 126.03 seconds
Started Aug 04 05:29:25 PM PDT 24
Finished Aug 04 05:31:31 PM PDT 24
Peak memory 238444 kb
Host smart-89c72dde-342a-47a6-ab3b-2701d17da1dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605971792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2605971792
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3691642400
Short name T33
Test name
Test status
Simulation time 13762003223 ps
CPU time 152.23 seconds
Started Aug 04 05:29:14 PM PDT 24
Finished Aug 04 05:31:46 PM PDT 24
Peak memory 225988 kb
Host smart-4c4080f9-5ec8-4338-b297-f188147d9bfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691642400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3691642400
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2501151140
Short name T48
Test name
Test status
Simulation time 258210522 ps
CPU time 68.73 seconds
Started Aug 04 05:27:39 PM PDT 24
Finished Aug 04 05:28:48 PM PDT 24
Peak memory 219452 kb
Host smart-db901ca6-6172-4cb7-9705-0449c6f6fbbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501151140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2501151140
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.185055345
Short name T5
Test name
Test status
Simulation time 270626182 ps
CPU time 13.39 seconds
Started Aug 04 05:29:24 PM PDT 24
Finished Aug 04 05:29:38 PM PDT 24
Peak memory 213096 kb
Host smart-7a6ea5a6-7420-4383-9a2a-940a14a9a8a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185055345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.185055345
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2901807325
Short name T19
Test name
Test status
Simulation time 966825942 ps
CPU time 99.18 seconds
Started Aug 04 05:29:12 PM PDT 24
Finished Aug 04 05:30:56 PM PDT 24
Peak memory 236848 kb
Host smart-be7bbcc4-9baa-403c-9b2d-3e8f15f5b2a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901807325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2901807325
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2487378751
Short name T54
Test name
Test status
Simulation time 383610939 ps
CPU time 19.17 seconds
Started Aug 04 05:27:44 PM PDT 24
Finished Aug 04 05:28:03 PM PDT 24
Peak memory 211452 kb
Host smart-cdebdd1c-826a-4a1d-982d-55b29ab137c6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487378751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2487378751
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2731077262
Short name T115
Test name
Test status
Simulation time 1116824798 ps
CPU time 69.36 seconds
Started Aug 04 05:27:30 PM PDT 24
Finished Aug 04 05:28:39 PM PDT 24
Peak memory 219476 kb
Host smart-a1b63448-f848-4064-802d-b74a100cb44e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731077262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2731077262
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1255820620
Short name T11
Test name
Test status
Simulation time 133875004492 ps
CPU time 1297.32 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:51:05 PM PDT 24
Peak memory 236864 kb
Host smart-0abf8209-9b73-4873-b714-c7925973643d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255820620 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.1255820620
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2543778845
Short name T103
Test name
Test status
Simulation time 132548824 ps
CPU time 5.18 seconds
Started Aug 04 05:29:20 PM PDT 24
Finished Aug 04 05:29:26 PM PDT 24
Peak memory 211976 kb
Host smart-f25e41c8-b07b-4fdb-a390-96f5c451e9a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543778845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2543778845
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3707397095
Short name T1
Test name
Test status
Simulation time 205227836 ps
CPU time 9.35 seconds
Started Aug 04 05:29:07 PM PDT 24
Finished Aug 04 05:29:17 PM PDT 24
Peak memory 212944 kb
Host smart-49b8ddd2-fb7b-460f-8c16-25bdce6592e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707397095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3707397095
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3643753865
Short name T123
Test name
Test status
Simulation time 263856934 ps
CPU time 11.52 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:38 PM PDT 24
Peak memory 212872 kb
Host smart-0e764cfe-6f37-403a-86cd-49d4a5a0a999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643753865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3643753865
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3391174959
Short name T39
Test name
Test status
Simulation time 263821109 ps
CPU time 10.94 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:29:39 PM PDT 24
Peak memory 213004 kb
Host smart-e86aaf62-b738-469b-bce4-f76ed2b5f743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391174959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3391174959
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1239440269
Short name T107
Test name
Test status
Simulation time 2237274235 ps
CPU time 79.68 seconds
Started Aug 04 05:27:48 PM PDT 24
Finished Aug 04 05:29:08 PM PDT 24
Peak memory 219636 kb
Host smart-c1efc070-79fb-4cd4-b755-60fa281fc74b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239440269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1239440269
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1196622155
Short name T112
Test name
Test status
Simulation time 329662309 ps
CPU time 37.53 seconds
Started Aug 04 05:27:48 PM PDT 24
Finished Aug 04 05:28:25 PM PDT 24
Peak memory 211916 kb
Host smart-a82e7cbc-95f6-4fd3-a4df-0128410ac512
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196622155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1196622155
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.292670400
Short name T78
Test name
Test status
Simulation time 2160143466 ps
CPU time 27.65 seconds
Started Aug 04 05:27:50 PM PDT 24
Finished Aug 04 05:28:17 PM PDT 24
Peak memory 211492 kb
Host smart-f12a0af0-0390-433c-9a80-04c84d8cb1eb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292670400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.292670400
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1711004180
Short name T98
Test name
Test status
Simulation time 275000828 ps
CPU time 6.55 seconds
Started Aug 04 05:29:29 PM PDT 24
Finished Aug 04 05:29:35 PM PDT 24
Peak memory 212156 kb
Host smart-1b67aaa8-af88-4a2f-8649-515d64c813e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1711004180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1711004180
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3252443754
Short name T91
Test name
Test status
Simulation time 562867439 ps
CPU time 5.03 seconds
Started Aug 04 05:27:29 PM PDT 24
Finished Aug 04 05:27:34 PM PDT 24
Peak memory 218620 kb
Host smart-f074a055-2a36-44df-8fc2-daeaae98f287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252443754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3252443754
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.914207407
Short name T80
Test name
Test status
Simulation time 278623364 ps
CPU time 6.49 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:29:35 PM PDT 24
Peak memory 212068 kb
Host smart-a1221471-a980-41a0-9d11-7c44fa6ffa97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=914207407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.914207407
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3017601845
Short name T386
Test name
Test status
Simulation time 362898161 ps
CPU time 4.2 seconds
Started Aug 04 05:27:30 PM PDT 24
Finished Aug 04 05:27:35 PM PDT 24
Peak memory 218368 kb
Host smart-f13eb4c8-25dd-4af1-bc1b-909c2d82ab49
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017601845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3017601845
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1204444133
Short name T361
Test name
Test status
Simulation time 2037409842 ps
CPU time 7.96 seconds
Started Aug 04 05:27:32 PM PDT 24
Finished Aug 04 05:27:40 PM PDT 24
Peak memory 218208 kb
Host smart-2f7942d1-3b3b-43c1-b793-bbed177d44e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204444133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1204444133
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2428566873
Short name T61
Test name
Test status
Simulation time 133165223 ps
CPU time 8.51 seconds
Started Aug 04 05:27:30 PM PDT 24
Finished Aug 04 05:27:38 PM PDT 24
Peak memory 211328 kb
Host smart-6569d1de-8771-49a9-a503-1eca4bf3bd2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428566873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2428566873
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1844785415
Short name T410
Test name
Test status
Simulation time 108229603 ps
CPU time 6.07 seconds
Started Aug 04 05:27:29 PM PDT 24
Finished Aug 04 05:27:35 PM PDT 24
Peak memory 216940 kb
Host smart-be2dca04-a168-4993-8574-2f759d37bbdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844785415 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1844785415
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1655170923
Short name T344
Test name
Test status
Simulation time 347891882 ps
CPU time 4.33 seconds
Started Aug 04 05:27:34 PM PDT 24
Finished Aug 04 05:27:38 PM PDT 24
Peak memory 219344 kb
Host smart-f7179246-77c1-4c2d-994d-ffd793ef133b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655170923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1655170923
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1863433800
Short name T329
Test name
Test status
Simulation time 521524225 ps
CPU time 5.13 seconds
Started Aug 04 05:27:30 PM PDT 24
Finished Aug 04 05:27:35 PM PDT 24
Peak memory 211268 kb
Host smart-80b8376c-f426-4c60-bc4e-550a2bb5d74c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863433800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1863433800
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3276406622
Short name T367
Test name
Test status
Simulation time 88999331 ps
CPU time 4.09 seconds
Started Aug 04 05:27:31 PM PDT 24
Finished Aug 04 05:27:35 PM PDT 24
Peak memory 211260 kb
Host smart-85be22d8-d11e-4a4e-8769-f2ca7a73c8db
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276406622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3276406622
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2641022312
Short name T391
Test name
Test status
Simulation time 1426363235 ps
CPU time 18.85 seconds
Started Aug 04 05:27:35 PM PDT 24
Finished Aug 04 05:27:54 PM PDT 24
Peak memory 211368 kb
Host smart-475cc954-e2ea-420d-893b-4743a7cb0ba8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641022312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2641022312
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1965169563
Short name T383
Test name
Test status
Simulation time 95998426 ps
CPU time 7.1 seconds
Started Aug 04 05:27:39 PM PDT 24
Finished Aug 04 05:27:46 PM PDT 24
Peak memory 219656 kb
Host smart-cfeeba64-ee53-4d81-8ed0-a5b5775e1624
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965169563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1965169563
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3443532650
Short name T108
Test name
Test status
Simulation time 350596632 ps
CPU time 72.1 seconds
Started Aug 04 05:27:33 PM PDT 24
Finished Aug 04 05:28:45 PM PDT 24
Peak memory 212056 kb
Host smart-4bbaba97-e4a7-4727-bd4b-3cbeb40af691
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443532650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3443532650
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1961926415
Short name T395
Test name
Test status
Simulation time 334106255 ps
CPU time 4.33 seconds
Started Aug 04 05:27:30 PM PDT 24
Finished Aug 04 05:27:34 PM PDT 24
Peak memory 219372 kb
Host smart-0eee4796-9934-4b1b-b6a6-1ef685a2ea84
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961926415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1961926415
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1478987566
Short name T381
Test name
Test status
Simulation time 382171968 ps
CPU time 4.53 seconds
Started Aug 04 05:27:30 PM PDT 24
Finished Aug 04 05:27:35 PM PDT 24
Peak memory 219488 kb
Host smart-2d59e93c-a876-40e7-af56-519bc819c368
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478987566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1478987566
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4275467970
Short name T77
Test name
Test status
Simulation time 1254461311 ps
CPU time 6.66 seconds
Started Aug 04 05:27:29 PM PDT 24
Finished Aug 04 05:27:36 PM PDT 24
Peak memory 211332 kb
Host smart-869caa67-06f6-4606-b077-9f7aac0fc38c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275467970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.4275467970
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.551599999
Short name T347
Test name
Test status
Simulation time 514099969 ps
CPU time 5.22 seconds
Started Aug 04 05:27:34 PM PDT 24
Finished Aug 04 05:27:39 PM PDT 24
Peak memory 219476 kb
Host smart-003fc140-7307-4401-939b-6da42a745b80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551599999 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.551599999
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.727240899
Short name T76
Test name
Test status
Simulation time 130268270 ps
CPU time 5.07 seconds
Started Aug 04 05:27:35 PM PDT 24
Finished Aug 04 05:27:40 PM PDT 24
Peak memory 217904 kb
Host smart-0132ccc8-55f3-46b8-8a04-3bc68b3122e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727240899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.727240899
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3763191696
Short name T331
Test name
Test status
Simulation time 256436771 ps
CPU time 5.01 seconds
Started Aug 04 05:27:37 PM PDT 24
Finished Aug 04 05:27:42 PM PDT 24
Peak memory 211272 kb
Host smart-a3e98340-5171-4a8f-b206-582c7ec3f010
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763191696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3763191696
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2326907715
Short name T342
Test name
Test status
Simulation time 250089945 ps
CPU time 5.13 seconds
Started Aug 04 05:27:30 PM PDT 24
Finished Aug 04 05:27:36 PM PDT 24
Peak memory 211068 kb
Host smart-706b8f14-4b70-4d86-948a-2204e7d9f18a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326907715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2326907715
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3883037168
Short name T393
Test name
Test status
Simulation time 375002281 ps
CPU time 19.01 seconds
Started Aug 04 05:27:33 PM PDT 24
Finished Aug 04 05:27:52 PM PDT 24
Peak memory 211472 kb
Host smart-00a4a5cf-f5bc-4b14-ae31-f9ffef7379ac
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883037168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3883037168
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3189355718
Short name T370
Test name
Test status
Simulation time 292169166 ps
CPU time 5.22 seconds
Started Aug 04 05:27:33 PM PDT 24
Finished Aug 04 05:27:38 PM PDT 24
Peak memory 211364 kb
Host smart-c79071b1-6ab1-4084-8798-0ed1ed46f709
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189355718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3189355718
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2318021511
Short name T327
Test name
Test status
Simulation time 85823989 ps
CPU time 7.85 seconds
Started Aug 04 05:27:31 PM PDT 24
Finished Aug 04 05:27:39 PM PDT 24
Peak memory 217712 kb
Host smart-599cd0d3-cf67-4770-b9b2-b2883d077f52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318021511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2318021511
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1041958860
Short name T372
Test name
Test status
Simulation time 556772469 ps
CPU time 5.43 seconds
Started Aug 04 05:27:45 PM PDT 24
Finished Aug 04 05:27:51 PM PDT 24
Peak memory 219592 kb
Host smart-3dbf0010-78f5-4014-89d5-2630598ea117
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041958860 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1041958860
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2213544967
Short name T97
Test name
Test status
Simulation time 88868183 ps
CPU time 4.29 seconds
Started Aug 04 05:27:42 PM PDT 24
Finished Aug 04 05:27:47 PM PDT 24
Peak memory 211260 kb
Host smart-6e84a7bd-ba79-4f06-a0e2-7b4ab0399782
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213544967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2213544967
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.326605826
Short name T359
Test name
Test status
Simulation time 593803087 ps
CPU time 4.33 seconds
Started Aug 04 05:27:44 PM PDT 24
Finished Aug 04 05:27:49 PM PDT 24
Peak memory 218640 kb
Host smart-83d7955c-bb5a-4621-917f-2a6b6e69542a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326605826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.326605826
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1637137700
Short name T373
Test name
Test status
Simulation time 827539805 ps
CPU time 9.97 seconds
Started Aug 04 05:27:53 PM PDT 24
Finished Aug 04 05:28:04 PM PDT 24
Peak memory 219608 kb
Host smart-774b0b09-5e96-4610-99c3-93b7e7f7a0b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637137700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1637137700
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2400705309
Short name T403
Test name
Test status
Simulation time 537455217 ps
CPU time 35.69 seconds
Started Aug 04 05:27:45 PM PDT 24
Finished Aug 04 05:28:21 PM PDT 24
Peak memory 211848 kb
Host smart-70513195-6173-4065-ae03-21fc216a0233
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400705309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2400705309
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2827075372
Short name T332
Test name
Test status
Simulation time 350743896 ps
CPU time 4.87 seconds
Started Aug 04 05:27:47 PM PDT 24
Finished Aug 04 05:27:52 PM PDT 24
Peak memory 215780 kb
Host smart-9403567d-9cef-4d70-b938-79204e9fe7f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827075372 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2827075372
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2549727193
Short name T352
Test name
Test status
Simulation time 501271153 ps
CPU time 4.97 seconds
Started Aug 04 05:27:46 PM PDT 24
Finished Aug 04 05:27:51 PM PDT 24
Peak memory 218200 kb
Host smart-63ff3c7a-d50b-4ce2-9dbb-ff0c46510dab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549727193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2549727193
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4176882284
Short name T90
Test name
Test status
Simulation time 133389135 ps
CPU time 5.31 seconds
Started Aug 04 05:27:49 PM PDT 24
Finished Aug 04 05:27:54 PM PDT 24
Peak memory 211384 kb
Host smart-e4a0d2b2-94ba-499f-a4d8-0e9ff623f7f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176882284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.4176882284
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.484083673
Short name T389
Test name
Test status
Simulation time 516417116 ps
CPU time 7.29 seconds
Started Aug 04 05:27:43 PM PDT 24
Finished Aug 04 05:27:51 PM PDT 24
Peak memory 219628 kb
Host smart-afc9db67-ede4-457d-8e62-c728319e12a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484083673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.484083673
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2143451954
Short name T409
Test name
Test status
Simulation time 282714599 ps
CPU time 6.94 seconds
Started Aug 04 05:27:46 PM PDT 24
Finished Aug 04 05:27:53 PM PDT 24
Peak memory 216788 kb
Host smart-a8572d2c-2875-4a83-85ed-f9548ea477c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143451954 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2143451954
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2941333598
Short name T351
Test name
Test status
Simulation time 89136751 ps
CPU time 4.26 seconds
Started Aug 04 05:27:47 PM PDT 24
Finished Aug 04 05:27:52 PM PDT 24
Peak memory 211312 kb
Host smart-d64d70f6-e8d2-41f0-8b04-8a32379171c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941333598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2941333598
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.249914437
Short name T93
Test name
Test status
Simulation time 997363588 ps
CPU time 6.1 seconds
Started Aug 04 05:27:49 PM PDT 24
Finished Aug 04 05:27:55 PM PDT 24
Peak memory 219724 kb
Host smart-510dc275-d080-4d72-99ad-0f799a751379
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249914437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.249914437
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2449470510
Short name T380
Test name
Test status
Simulation time 263585554 ps
CPU time 8.77 seconds
Started Aug 04 05:27:51 PM PDT 24
Finished Aug 04 05:28:00 PM PDT 24
Peak memory 219612 kb
Host smart-ca03f894-7fa7-4ef1-9338-69fc2de996a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449470510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2449470510
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4139888928
Short name T49
Test name
Test status
Simulation time 288153839 ps
CPU time 36.64 seconds
Started Aug 04 05:27:48 PM PDT 24
Finished Aug 04 05:28:24 PM PDT 24
Peak memory 211972 kb
Host smart-ca8edfe1-a3ad-4211-9a7d-c649dd0a4bf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139888928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.4139888928
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.133859800
Short name T397
Test name
Test status
Simulation time 97772750 ps
CPU time 4.83 seconds
Started Aug 04 05:27:48 PM PDT 24
Finished Aug 04 05:27:53 PM PDT 24
Peak memory 215848 kb
Host smart-64d8b25f-9382-4451-be35-306d58c6d5c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133859800 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.133859800
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2213477077
Short name T79
Test name
Test status
Simulation time 349684109 ps
CPU time 4.16 seconds
Started Aug 04 05:27:45 PM PDT 24
Finished Aug 04 05:27:50 PM PDT 24
Peak memory 211264 kb
Host smart-ccdfa30f-4a69-434f-82bc-3b65e88d9ea0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213477077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2213477077
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.797422499
Short name T89
Test name
Test status
Simulation time 499901439 ps
CPU time 5.26 seconds
Started Aug 04 05:27:49 PM PDT 24
Finished Aug 04 05:27:54 PM PDT 24
Peak memory 211584 kb
Host smart-52ada9ee-cfd0-4e0a-82e3-b55ce3e98c0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797422499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.797422499
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.707612179
Short name T349
Test name
Test status
Simulation time 176755349 ps
CPU time 6.09 seconds
Started Aug 04 05:27:44 PM PDT 24
Finished Aug 04 05:27:50 PM PDT 24
Peak memory 219584 kb
Host smart-1ca6b4c9-11ea-42dc-b421-9ab44ed22470
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707612179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.707612179
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1094984600
Short name T110
Test name
Test status
Simulation time 791983453 ps
CPU time 79.51 seconds
Started Aug 04 05:27:42 PM PDT 24
Finished Aug 04 05:29:01 PM PDT 24
Peak memory 219572 kb
Host smart-f2bf1b08-426a-4f01-80fe-7e656b333045
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094984600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1094984600
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1247212102
Short name T387
Test name
Test status
Simulation time 138873252 ps
CPU time 5.51 seconds
Started Aug 04 05:27:49 PM PDT 24
Finished Aug 04 05:27:55 PM PDT 24
Peak memory 214964 kb
Host smart-e3ac13fa-b65d-4730-82c7-37f3abbb0f20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247212102 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1247212102
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3943672225
Short name T376
Test name
Test status
Simulation time 88863439 ps
CPU time 4.23 seconds
Started Aug 04 05:27:46 PM PDT 24
Finished Aug 04 05:27:50 PM PDT 24
Peak memory 211152 kb
Host smart-964edc5d-8131-4b9a-97a2-94b515de0972
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943672225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3943672225
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3773504863
Short name T51
Test name
Test status
Simulation time 351430643 ps
CPU time 4.27 seconds
Started Aug 04 05:27:46 PM PDT 24
Finished Aug 04 05:27:50 PM PDT 24
Peak memory 219400 kb
Host smart-c6d1e7b6-59e3-4501-b4fa-d2c2f680f5bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773504863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3773504863
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.184298959
Short name T343
Test name
Test status
Simulation time 369262971 ps
CPU time 9.33 seconds
Started Aug 04 05:27:48 PM PDT 24
Finished Aug 04 05:27:58 PM PDT 24
Peak memory 219640 kb
Host smart-a7167d26-835d-4b88-a98c-d3e99ccdcab6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184298959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.184298959
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2599581876
Short name T118
Test name
Test status
Simulation time 3133727362 ps
CPU time 37.57 seconds
Started Aug 04 05:27:48 PM PDT 24
Finished Aug 04 05:28:26 PM PDT 24
Peak memory 212084 kb
Host smart-cbc4a23c-73b2-46d3-8396-cb59a83b886f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599581876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2599581876
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3492326851
Short name T356
Test name
Test status
Simulation time 1093930181 ps
CPU time 5.07 seconds
Started Aug 04 05:27:45 PM PDT 24
Finished Aug 04 05:27:51 PM PDT 24
Peak memory 219804 kb
Host smart-6b8f1c6f-5435-43dd-8030-5db502094a0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492326851 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3492326851
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2724897372
Short name T96
Test name
Test status
Simulation time 85442173 ps
CPU time 4.1 seconds
Started Aug 04 05:27:46 PM PDT 24
Finished Aug 04 05:27:50 PM PDT 24
Peak memory 211180 kb
Host smart-fab149a7-0699-4dbe-957f-2da67f54ec5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724897372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2724897372
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3429430168
Short name T398
Test name
Test status
Simulation time 524422185 ps
CPU time 6.8 seconds
Started Aug 04 05:27:46 PM PDT 24
Finished Aug 04 05:27:53 PM PDT 24
Peak memory 211472 kb
Host smart-6195d2e9-f874-4eb1-a4c0-b8fa5daa84fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429430168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3429430168
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2377001876
Short name T384
Test name
Test status
Simulation time 131341254 ps
CPU time 7.49 seconds
Started Aug 04 05:27:45 PM PDT 24
Finished Aug 04 05:27:53 PM PDT 24
Peak memory 219660 kb
Host smart-25f39343-a9c4-4799-839f-d27e57398f2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377001876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2377001876
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3655564283
Short name T50
Test name
Test status
Simulation time 244673495 ps
CPU time 38.14 seconds
Started Aug 04 05:27:46 PM PDT 24
Finished Aug 04 05:28:24 PM PDT 24
Peak memory 212860 kb
Host smart-5239333e-ea13-4922-9ee5-228549c16978
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655564283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3655564283
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3965848418
Short name T330
Test name
Test status
Simulation time 264464060 ps
CPU time 5.46 seconds
Started Aug 04 05:27:48 PM PDT 24
Finished Aug 04 05:27:54 PM PDT 24
Peak memory 215848 kb
Host smart-392f4129-909e-42a2-abb7-d7e2a4682a7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965848418 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3965848418
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2402646148
Short name T58
Test name
Test status
Simulation time 168744522 ps
CPU time 4.21 seconds
Started Aug 04 05:27:46 PM PDT 24
Finished Aug 04 05:27:50 PM PDT 24
Peak memory 211172 kb
Host smart-6b50aaad-fe49-4a1b-9af1-df21d7fd3ab8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402646148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2402646148
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3189579190
Short name T365
Test name
Test status
Simulation time 95538752 ps
CPU time 6.1 seconds
Started Aug 04 05:27:46 PM PDT 24
Finished Aug 04 05:27:53 PM PDT 24
Peak memory 219132 kb
Host smart-7c4ae17b-3719-42eb-a021-cbc4089a9db1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189579190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3189579190
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3917579126
Short name T396
Test name
Test status
Simulation time 127871054 ps
CPU time 7.29 seconds
Started Aug 04 05:27:49 PM PDT 24
Finished Aug 04 05:27:56 PM PDT 24
Peak memory 216516 kb
Host smart-fbc0214f-2ea0-43c4-b928-0e900653c0d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917579126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3917579126
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3847367643
Short name T106
Test name
Test status
Simulation time 325896362 ps
CPU time 36.78 seconds
Started Aug 04 05:27:50 PM PDT 24
Finished Aug 04 05:28:27 PM PDT 24
Peak memory 212756 kb
Host smart-7d245a28-5a40-4265-89c6-222e4d0d06b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847367643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3847367643
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1590425861
Short name T407
Test name
Test status
Simulation time 853094133 ps
CPU time 5.69 seconds
Started Aug 04 05:27:56 PM PDT 24
Finished Aug 04 05:28:02 PM PDT 24
Peak memory 215660 kb
Host smart-76e349af-028b-4d1c-ac36-e18a6e570059
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590425861 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1590425861
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3560957719
Short name T392
Test name
Test status
Simulation time 85887628 ps
CPU time 4.14 seconds
Started Aug 04 05:27:51 PM PDT 24
Finished Aug 04 05:27:55 PM PDT 24
Peak memory 211304 kb
Host smart-65020886-f0e2-46b9-9fba-019c1f654a70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560957719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3560957719
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2302640101
Short name T73
Test name
Test status
Simulation time 374620677 ps
CPU time 18.89 seconds
Started Aug 04 05:27:47 PM PDT 24
Finished Aug 04 05:28:06 PM PDT 24
Peak memory 211436 kb
Host smart-5cdebb82-edf3-4bfc-b4a1-92ef1f763d87
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302640101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2302640101
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2860305186
Short name T377
Test name
Test status
Simulation time 1270321908 ps
CPU time 6.75 seconds
Started Aug 04 05:27:50 PM PDT 24
Finished Aug 04 05:27:57 PM PDT 24
Peak memory 218740 kb
Host smart-b7e8734a-997b-41f2-8732-6ef1fd205de1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860305186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2860305186
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2825292846
Short name T364
Test name
Test status
Simulation time 126439044 ps
CPU time 7.36 seconds
Started Aug 04 05:27:51 PM PDT 24
Finished Aug 04 05:27:58 PM PDT 24
Peak memory 219696 kb
Host smart-1bde344c-7925-40c6-9f2f-eec483fe7569
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825292846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2825292846
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.6977742
Short name T113
Test name
Test status
Simulation time 2259778585 ps
CPU time 39.21 seconds
Started Aug 04 05:27:50 PM PDT 24
Finished Aug 04 05:28:29 PM PDT 24
Peak memory 211680 kb
Host smart-6877317f-0bfe-4cd0-ba46-e25b5eaa7c64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6977742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg
_err.6977742
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.135678846
Short name T400
Test name
Test status
Simulation time 273394800 ps
CPU time 5.91 seconds
Started Aug 04 05:27:50 PM PDT 24
Finished Aug 04 05:27:57 PM PDT 24
Peak memory 219552 kb
Host smart-fb48b1c6-d191-4a6e-856e-341b177757f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135678846 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.135678846
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3575551583
Short name T92
Test name
Test status
Simulation time 176102115 ps
CPU time 4.15 seconds
Started Aug 04 05:28:00 PM PDT 24
Finished Aug 04 05:28:04 PM PDT 24
Peak memory 210952 kb
Host smart-1f75e565-da6c-4c20-bb48-cddb26afdbc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575551583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3575551583
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1683153460
Short name T59
Test name
Test status
Simulation time 454421378 ps
CPU time 6.35 seconds
Started Aug 04 05:27:57 PM PDT 24
Finished Aug 04 05:28:03 PM PDT 24
Peak memory 211540 kb
Host smart-bfa55473-2ffa-48b4-a0a6-228ee04d6f97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683153460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1683153460
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4188484256
Short name T104
Test name
Test status
Simulation time 438845629 ps
CPU time 10.26 seconds
Started Aug 04 05:27:50 PM PDT 24
Finished Aug 04 05:28:00 PM PDT 24
Peak memory 219672 kb
Host smart-b2f7f924-f735-499f-b354-38ed83053de7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188484256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4188484256
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1776261521
Short name T394
Test name
Test status
Simulation time 383891597 ps
CPU time 37.37 seconds
Started Aug 04 05:27:51 PM PDT 24
Finished Aug 04 05:28:29 PM PDT 24
Peak memory 219528 kb
Host smart-f913b5a2-e92b-4659-838a-de4da2bc94de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776261521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1776261521
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2978340179
Short name T340
Test name
Test status
Simulation time 391762481 ps
CPU time 4.91 seconds
Started Aug 04 05:27:55 PM PDT 24
Finished Aug 04 05:28:00 PM PDT 24
Peak memory 215136 kb
Host smart-37d1d017-f948-4a44-a1bc-968a2166db04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978340179 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2978340179
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1358413127
Short name T362
Test name
Test status
Simulation time 136778046 ps
CPU time 5.04 seconds
Started Aug 04 05:27:55 PM PDT 24
Finished Aug 04 05:28:00 PM PDT 24
Peak memory 211216 kb
Host smart-a91f8c33-905c-43a2-a25b-cea537baad42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358413127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1358413127
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1128369108
Short name T357
Test name
Test status
Simulation time 171151906 ps
CPU time 4.34 seconds
Started Aug 04 05:28:00 PM PDT 24
Finished Aug 04 05:28:04 PM PDT 24
Peak memory 211268 kb
Host smart-9140dfd4-da70-4b61-b1e2-d00392017ac9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128369108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1128369108
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2505471492
Short name T341
Test name
Test status
Simulation time 135929509 ps
CPU time 7.48 seconds
Started Aug 04 05:27:55 PM PDT 24
Finished Aug 04 05:28:03 PM PDT 24
Peak memory 219704 kb
Host smart-b61c5316-967a-4087-b0c0-b71155dbafee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505471492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2505471492
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2739522055
Short name T109
Test name
Test status
Simulation time 898429891 ps
CPU time 68.26 seconds
Started Aug 04 05:27:50 PM PDT 24
Finished Aug 04 05:28:59 PM PDT 24
Peak memory 213044 kb
Host smart-be6e5bb1-e47d-4872-9c60-8b49b8853627
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739522055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2739522055
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.766167610
Short name T72
Test name
Test status
Simulation time 500238658 ps
CPU time 5.03 seconds
Started Aug 04 05:27:44 PM PDT 24
Finished Aug 04 05:27:49 PM PDT 24
Peak memory 211328 kb
Host smart-59cf53c0-b18b-46dd-996e-324f0950381f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766167610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.766167610
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1172193406
Short name T334
Test name
Test status
Simulation time 131157980 ps
CPU time 5.32 seconds
Started Aug 04 05:27:49 PM PDT 24
Finished Aug 04 05:27:55 PM PDT 24
Peak memory 211276 kb
Host smart-d49f4e11-16e3-4cb1-9943-8cfb795ec8b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172193406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1172193406
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2138699579
Short name T338
Test name
Test status
Simulation time 1060472614 ps
CPU time 5.92 seconds
Started Aug 04 05:27:45 PM PDT 24
Finished Aug 04 05:27:51 PM PDT 24
Peak memory 211296 kb
Host smart-66e79970-382e-48e7-853c-75d23dda489e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138699579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2138699579
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1085647492
Short name T375
Test name
Test status
Simulation time 157808115 ps
CPU time 4.67 seconds
Started Aug 04 05:27:41 PM PDT 24
Finished Aug 04 05:27:45 PM PDT 24
Peak memory 219448 kb
Host smart-b7dadfcf-d925-4788-9f7e-0bb0a015b51a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085647492 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1085647492
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.29483502
Short name T62
Test name
Test status
Simulation time 253406976 ps
CPU time 5.06 seconds
Started Aug 04 05:27:34 PM PDT 24
Finished Aug 04 05:27:39 PM PDT 24
Peak memory 218208 kb
Host smart-67c137b1-5740-4c4f-80ba-130f5ef47007
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29483502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.29483502
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2575809669
Short name T350
Test name
Test status
Simulation time 322262686 ps
CPU time 4.13 seconds
Started Aug 04 05:27:34 PM PDT 24
Finished Aug 04 05:27:38 PM PDT 24
Peak memory 211240 kb
Host smart-09d9364b-b8ec-44ca-95f6-3938dcc5f0ca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575809669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2575809669
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1967891389
Short name T379
Test name
Test status
Simulation time 298267384 ps
CPU time 4.28 seconds
Started Aug 04 05:27:34 PM PDT 24
Finished Aug 04 05:27:39 PM PDT 24
Peak memory 211152 kb
Host smart-ca69f665-8382-4970-bb9c-59dd9a852572
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967891389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1967891389
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2025893840
Short name T94
Test name
Test status
Simulation time 89200650 ps
CPU time 4.47 seconds
Started Aug 04 05:27:33 PM PDT 24
Finished Aug 04 05:27:38 PM PDT 24
Peak memory 211296 kb
Host smart-c5549d04-22f0-4cab-a751-91b1ec711980
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025893840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2025893840
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1603564088
Short name T337
Test name
Test status
Simulation time 494101378 ps
CPU time 12.16 seconds
Started Aug 04 05:27:33 PM PDT 24
Finished Aug 04 05:27:45 PM PDT 24
Peak memory 219692 kb
Host smart-f19e5f2a-425b-41a5-9527-2128919a6d2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603564088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1603564088
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1104775572
Short name T385
Test name
Test status
Simulation time 974146192 ps
CPU time 70.17 seconds
Started Aug 04 05:27:34 PM PDT 24
Finished Aug 04 05:28:44 PM PDT 24
Peak memory 219524 kb
Host smart-871d904a-320e-4e18-bc55-4a86674b9c43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104775572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1104775572
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2068869268
Short name T360
Test name
Test status
Simulation time 171188342 ps
CPU time 4.23 seconds
Started Aug 04 05:27:33 PM PDT 24
Finished Aug 04 05:27:38 PM PDT 24
Peak memory 211308 kb
Host smart-8792e78c-d10b-43c1-b631-88918a40eb18
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068869268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2068869268
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.315405002
Short name T366
Test name
Test status
Simulation time 85783902 ps
CPU time 4.66 seconds
Started Aug 04 05:27:48 PM PDT 24
Finished Aug 04 05:27:52 PM PDT 24
Peak memory 211264 kb
Host smart-33ccd707-77a9-463b-83f3-8c4405bc2a4d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315405002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.315405002
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3347757951
Short name T74
Test name
Test status
Simulation time 1730784172 ps
CPU time 7.16 seconds
Started Aug 04 05:27:38 PM PDT 24
Finished Aug 04 05:27:45 PM PDT 24
Peak memory 211248 kb
Host smart-051c20fd-4b45-45db-a143-d5b800308f7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347757951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3347757951
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3033687808
Short name T333
Test name
Test status
Simulation time 129927249 ps
CPU time 5.31 seconds
Started Aug 04 05:27:47 PM PDT 24
Finished Aug 04 05:27:52 PM PDT 24
Peak memory 213268 kb
Host smart-8208b705-b847-43ae-98de-2ea5e419ee7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033687808 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3033687808
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3067030684
Short name T390
Test name
Test status
Simulation time 521182997 ps
CPU time 5.06 seconds
Started Aug 04 05:27:48 PM PDT 24
Finished Aug 04 05:27:53 PM PDT 24
Peak memory 218452 kb
Host smart-aa045319-9f8e-4f4a-aed2-fd9d25c23d13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067030684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3067030684
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.563073869
Short name T326
Test name
Test status
Simulation time 86647790 ps
CPU time 4.29 seconds
Started Aug 04 05:27:37 PM PDT 24
Finished Aug 04 05:27:42 PM PDT 24
Peak memory 211260 kb
Host smart-5362c650-0fe3-4b1c-9cd2-79c021e56501
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563073869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.563073869
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2356750653
Short name T369
Test name
Test status
Simulation time 86463054 ps
CPU time 4.26 seconds
Started Aug 04 05:27:34 PM PDT 24
Finished Aug 04 05:27:39 PM PDT 24
Peak memory 211268 kb
Host smart-3c896607-95a0-4c75-a680-d77c5cc57b7b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356750653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2356750653
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1176089673
Short name T382
Test name
Test status
Simulation time 1544469859 ps
CPU time 4.83 seconds
Started Aug 04 05:27:47 PM PDT 24
Finished Aug 04 05:27:52 PM PDT 24
Peak memory 218288 kb
Host smart-21a09cb4-31e2-49d3-95b0-713d246e20be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176089673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1176089673
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.110457910
Short name T401
Test name
Test status
Simulation time 305896412 ps
CPU time 9.7 seconds
Started Aug 04 05:27:36 PM PDT 24
Finished Aug 04 05:27:46 PM PDT 24
Peak memory 219676 kb
Host smart-0ce7b5d1-4dda-499b-ac5c-562467fd63ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110457910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.110457910
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3912804999
Short name T404
Test name
Test status
Simulation time 331974145 ps
CPU time 37.31 seconds
Started Aug 04 05:27:55 PM PDT 24
Finished Aug 04 05:28:38 PM PDT 24
Peak memory 213092 kb
Host smart-ca7ec781-a766-4ffa-9509-481f40f419a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912804999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3912804999
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2518729101
Short name T52
Test name
Test status
Simulation time 523194933 ps
CPU time 4.94 seconds
Started Aug 04 05:27:46 PM PDT 24
Finished Aug 04 05:27:51 PM PDT 24
Peak memory 218180 kb
Host smart-b5ed53f8-561f-4dec-9c24-e8d34ab6a218
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518729101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2518729101
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3846241762
Short name T345
Test name
Test status
Simulation time 127888668 ps
CPU time 5.36 seconds
Started Aug 04 05:27:33 PM PDT 24
Finished Aug 04 05:27:39 PM PDT 24
Peak memory 211224 kb
Host smart-f738b183-b85f-46a8-80c6-0cd85a30f04c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846241762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3846241762
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3903274960
Short name T339
Test name
Test status
Simulation time 87532923 ps
CPU time 5.67 seconds
Started Aug 04 05:27:45 PM PDT 24
Finished Aug 04 05:27:51 PM PDT 24
Peak memory 211264 kb
Host smart-7bd78399-1286-4958-bde2-b48500bfd50b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903274960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3903274960
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.845659627
Short name T353
Test name
Test status
Simulation time 282055479 ps
CPU time 5.74 seconds
Started Aug 04 05:27:48 PM PDT 24
Finished Aug 04 05:27:54 PM PDT 24
Peak memory 219612 kb
Host smart-34e8933c-8edc-4004-9d0a-ee5a51af1bf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845659627 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.845659627
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2001388667
Short name T60
Test name
Test status
Simulation time 498539537 ps
CPU time 5.12 seconds
Started Aug 04 05:27:35 PM PDT 24
Finished Aug 04 05:27:41 PM PDT 24
Peak memory 218372 kb
Host smart-4f2294b5-aa58-461e-92d3-6bd3b97407c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001388667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2001388667
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.42590198
Short name T402
Test name
Test status
Simulation time 542314032 ps
CPU time 5.14 seconds
Started Aug 04 05:27:32 PM PDT 24
Finished Aug 04 05:27:37 PM PDT 24
Peak memory 211156 kb
Host smart-df0ce6ea-3640-4455-80b5-0d37a3e6bb0d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42590198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_
mem_partial_access.42590198
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2719665351
Short name T336
Test name
Test status
Simulation time 523448045 ps
CPU time 4.95 seconds
Started Aug 04 05:27:45 PM PDT 24
Finished Aug 04 05:27:50 PM PDT 24
Peak memory 211252 kb
Host smart-5e1814b6-98e0-421f-a673-74deb530a875
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719665351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2719665351
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.280054702
Short name T56
Test name
Test status
Simulation time 141081905 ps
CPU time 5.28 seconds
Started Aug 04 05:27:34 PM PDT 24
Finished Aug 04 05:27:39 PM PDT 24
Peak memory 211320 kb
Host smart-ee8c81a4-2664-40db-8809-530f73b9fb20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280054702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.280054702
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3179949777
Short name T335
Test name
Test status
Simulation time 960315825 ps
CPU time 8.73 seconds
Started Aug 04 05:27:45 PM PDT 24
Finished Aug 04 05:27:54 PM PDT 24
Peak memory 216656 kb
Host smart-71fc55c7-f652-4531-859b-e0d28694a0c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179949777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3179949777
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2166159073
Short name T114
Test name
Test status
Simulation time 227051837 ps
CPU time 70.31 seconds
Started Aug 04 05:27:47 PM PDT 24
Finished Aug 04 05:28:58 PM PDT 24
Peak memory 219568 kb
Host smart-0fbe028d-5bcb-4d96-9904-c6e64041cd8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166159073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2166159073
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1612185687
Short name T374
Test name
Test status
Simulation time 101159303 ps
CPU time 5.22 seconds
Started Aug 04 05:27:48 PM PDT 24
Finished Aug 04 05:27:53 PM PDT 24
Peak memory 216600 kb
Host smart-d322ab1b-b146-40ae-9584-89bcc63addaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612185687 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1612185687
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2085146335
Short name T95
Test name
Test status
Simulation time 500461371 ps
CPU time 5.16 seconds
Started Aug 04 05:27:48 PM PDT 24
Finished Aug 04 05:27:53 PM PDT 24
Peak memory 211252 kb
Host smart-d7af5992-55a6-4419-a226-c492c6350f91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085146335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2085146335
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4171139441
Short name T371
Test name
Test status
Simulation time 498556598 ps
CPU time 5.12 seconds
Started Aug 04 05:27:49 PM PDT 24
Finished Aug 04 05:27:54 PM PDT 24
Peak memory 211208 kb
Host smart-2c6fefa8-25b0-4894-b07e-b0f0e3eb8ef4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171139441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.4171139441
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1154823949
Short name T348
Test name
Test status
Simulation time 90404580 ps
CPU time 7.8 seconds
Started Aug 04 05:27:48 PM PDT 24
Finished Aug 04 05:27:56 PM PDT 24
Peak memory 219628 kb
Host smart-6322e8bd-c998-45a9-b7cc-cc5cabe7543e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154823949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1154823949
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.509441273
Short name T116
Test name
Test status
Simulation time 202976312 ps
CPU time 37.32 seconds
Started Aug 04 05:27:42 PM PDT 24
Finished Aug 04 05:28:20 PM PDT 24
Peak memory 212012 kb
Host smart-8bdf31b7-5b76-4832-8092-26c14a83922b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509441273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.509441273
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1083486100
Short name T328
Test name
Test status
Simulation time 624764489 ps
CPU time 5.56 seconds
Started Aug 04 05:27:45 PM PDT 24
Finished Aug 04 05:27:50 PM PDT 24
Peak memory 215504 kb
Host smart-bde17604-646e-4a3b-a32b-b8163dd0e944
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083486100 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1083486100
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2412750256
Short name T405
Test name
Test status
Simulation time 90152773 ps
CPU time 4.28 seconds
Started Aug 04 05:27:50 PM PDT 24
Finished Aug 04 05:27:54 PM PDT 24
Peak memory 211296 kb
Host smart-2109776d-d9bb-4f95-aaf8-b2218a3feebb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412750256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2412750256
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3114331721
Short name T355
Test name
Test status
Simulation time 550100609 ps
CPU time 28.35 seconds
Started Aug 04 05:27:46 PM PDT 24
Finished Aug 04 05:28:14 PM PDT 24
Peak memory 211456 kb
Host smart-037da3b9-926c-475d-8464-393fa87d3c94
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114331721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3114331721
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1510447390
Short name T411
Test name
Test status
Simulation time 7002227565 ps
CPU time 7.86 seconds
Started Aug 04 05:27:45 PM PDT 24
Finished Aug 04 05:27:53 PM PDT 24
Peak memory 218972 kb
Host smart-10b19d0f-3632-47e9-b040-9ab57888abf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510447390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1510447390
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1015649760
Short name T388
Test name
Test status
Simulation time 271713091 ps
CPU time 9.17 seconds
Started Aug 04 05:27:49 PM PDT 24
Finished Aug 04 05:27:58 PM PDT 24
Peak memory 219628 kb
Host smart-0bf94313-9789-4fb6-809c-0f4f6415df8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015649760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1015649760
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.947527236
Short name T368
Test name
Test status
Simulation time 355946121 ps
CPU time 4.18 seconds
Started Aug 04 05:27:44 PM PDT 24
Finished Aug 04 05:27:49 PM PDT 24
Peak memory 219512 kb
Host smart-749798e0-9331-475e-8336-8e7117c97285
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947527236 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.947527236
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1739820235
Short name T55
Test name
Test status
Simulation time 880970325 ps
CPU time 7.28 seconds
Started Aug 04 05:27:46 PM PDT 24
Finished Aug 04 05:27:53 PM PDT 24
Peak memory 211312 kb
Host smart-a5378870-b420-4ecd-9c73-6a1cad109f9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739820235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1739820235
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1272724670
Short name T408
Test name
Test status
Simulation time 673889262 ps
CPU time 6.78 seconds
Started Aug 04 05:27:46 PM PDT 24
Finished Aug 04 05:27:53 PM PDT 24
Peak memory 211328 kb
Host smart-494094fa-81f3-4a60-ae95-75b5f1256ee0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272724670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1272724670
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.220542545
Short name T346
Test name
Test status
Simulation time 256157537 ps
CPU time 9.02 seconds
Started Aug 04 05:27:43 PM PDT 24
Finished Aug 04 05:27:52 PM PDT 24
Peak memory 216764 kb
Host smart-6575c7c1-e3e2-4d25-bdd3-97ab959cc96d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220542545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.220542545
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1861951332
Short name T117
Test name
Test status
Simulation time 1185681686 ps
CPU time 37.51 seconds
Started Aug 04 05:27:50 PM PDT 24
Finished Aug 04 05:28:27 PM PDT 24
Peak memory 211880 kb
Host smart-6e8baacd-5c98-481c-b416-44273041c6fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861951332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1861951332
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.810455584
Short name T378
Test name
Test status
Simulation time 415578688 ps
CPU time 5.2 seconds
Started Aug 04 05:27:48 PM PDT 24
Finished Aug 04 05:27:54 PM PDT 24
Peak memory 219424 kb
Host smart-1090b9f1-0386-4d99-9f9e-a95f94d7f948
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810455584 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.810455584
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1176796614
Short name T75
Test name
Test status
Simulation time 522058980 ps
CPU time 5.08 seconds
Started Aug 04 05:27:48 PM PDT 24
Finished Aug 04 05:27:53 PM PDT 24
Peak memory 218388 kb
Host smart-71659e04-78e1-4927-ba32-597402bc6b9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176796614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1176796614
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2960133309
Short name T358
Test name
Test status
Simulation time 545342425 ps
CPU time 5.07 seconds
Started Aug 04 05:27:44 PM PDT 24
Finished Aug 04 05:27:49 PM PDT 24
Peak memory 218308 kb
Host smart-9f032840-4bc0-4678-90dc-43583c2ee7ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960133309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2960133309
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2296968944
Short name T406
Test name
Test status
Simulation time 159711873 ps
CPU time 10.83 seconds
Started Aug 04 05:27:49 PM PDT 24
Finished Aug 04 05:28:00 PM PDT 24
Peak memory 216552 kb
Host smart-8d944668-9b8a-4282-89a7-60ac59805c66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296968944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2296968944
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.832865361
Short name T354
Test name
Test status
Simulation time 400322309 ps
CPU time 5.06 seconds
Started Aug 04 05:27:43 PM PDT 24
Finished Aug 04 05:27:48 PM PDT 24
Peak memory 219604 kb
Host smart-175bfa16-5b65-4e55-9c3b-f5e1f633dd4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832865361 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.832865361
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3577586670
Short name T57
Test name
Test status
Simulation time 954998365 ps
CPU time 4.91 seconds
Started Aug 04 05:27:47 PM PDT 24
Finished Aug 04 05:27:52 PM PDT 24
Peak memory 218096 kb
Host smart-b609af2a-366a-4464-8ef9-c7e3210a930b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577586670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3577586670
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2602245833
Short name T399
Test name
Test status
Simulation time 90072735 ps
CPU time 4.35 seconds
Started Aug 04 05:27:45 PM PDT 24
Finished Aug 04 05:27:50 PM PDT 24
Peak memory 219524 kb
Host smart-3d76f467-7693-4023-ab71-9717eae79053
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602245833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2602245833
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.684233863
Short name T363
Test name
Test status
Simulation time 348232839 ps
CPU time 7.91 seconds
Started Aug 04 05:27:38 PM PDT 24
Finished Aug 04 05:27:46 PM PDT 24
Peak memory 216748 kb
Host smart-0acf3ec7-5224-4444-9d4c-f90abbcbe40d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684233863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.684233863
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.207018867
Short name T111
Test name
Test status
Simulation time 580739565 ps
CPU time 39.8 seconds
Started Aug 04 05:27:39 PM PDT 24
Finished Aug 04 05:28:19 PM PDT 24
Peak memory 213744 kb
Host smart-4cc400fc-ec94-4e77-8992-caef8151a6ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207018867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.207018867
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3522713174
Short name T159
Test name
Test status
Simulation time 1371653529 ps
CPU time 5.13 seconds
Started Aug 04 05:28:55 PM PDT 24
Finished Aug 04 05:29:00 PM PDT 24
Peak memory 212036 kb
Host smart-f8392870-30f7-4d06-a80b-4a68cea00883
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522713174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3522713174
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3926668613
Short name T235
Test name
Test status
Simulation time 1609070199 ps
CPU time 110.36 seconds
Started Aug 04 05:28:56 PM PDT 24
Finished Aug 04 05:30:46 PM PDT 24
Peak memory 237528 kb
Host smart-2bc25eca-38fa-4f08-9450-8be4c18fa269
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926668613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3926668613
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1935492696
Short name T222
Test name
Test status
Simulation time 143229705 ps
CPU time 6.48 seconds
Started Aug 04 05:29:15 PM PDT 24
Finished Aug 04 05:29:22 PM PDT 24
Peak memory 212104 kb
Host smart-de12ca45-cdeb-4d83-ba0b-292b9692f6f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1935492696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1935492696
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2810156951
Short name T23
Test name
Test status
Simulation time 2220366273 ps
CPU time 102.7 seconds
Started Aug 04 05:29:04 PM PDT 24
Finished Aug 04 05:30:47 PM PDT 24
Peak memory 237516 kb
Host smart-7d182b53-0b6a-472e-86e7-d9fe92f4e24b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810156951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2810156951
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1362916607
Short name T220
Test name
Test status
Simulation time 637078290 ps
CPU time 5.51 seconds
Started Aug 04 05:29:05 PM PDT 24
Finished Aug 04 05:29:15 PM PDT 24
Peak memory 212272 kb
Host smart-db7326d4-fecb-41ff-81b0-4ca76e850bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362916607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1362916607
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2415756195
Short name T229
Test name
Test status
Simulation time 389041711 ps
CPU time 15.36 seconds
Started Aug 04 05:28:55 PM PDT 24
Finished Aug 04 05:29:10 PM PDT 24
Peak memory 215516 kb
Host smart-c6f3f86b-a70e-4fee-8e4b-d198bf55ff7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415756195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2415756195
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3316297453
Short name T301
Test name
Test status
Simulation time 346348178 ps
CPU time 4.16 seconds
Started Aug 04 05:29:20 PM PDT 24
Finished Aug 04 05:29:24 PM PDT 24
Peak memory 212056 kb
Host smart-5ce006ec-db86-4602-97df-da730b34ea22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316297453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3316297453
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.45640856
Short name T268
Test name
Test status
Simulation time 11959553066 ps
CPU time 147.88 seconds
Started Aug 04 05:29:10 PM PDT 24
Finished Aug 04 05:31:38 PM PDT 24
Peak memory 238492 kb
Host smart-5f965334-b413-41a7-9ce3-84be3f550096
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45640856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_cor
rupt_sig_fatal_chk.45640856
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.761539297
Short name T191
Test name
Test status
Simulation time 1178245763 ps
CPU time 16.55 seconds
Started Aug 04 05:29:06 PM PDT 24
Finished Aug 04 05:29:23 PM PDT 24
Peak memory 212896 kb
Host smart-dc95e1d5-509a-468b-a51f-1d51dfabd20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761539297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.761539297
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3502367981
Short name T270
Test name
Test status
Simulation time 537555527 ps
CPU time 6.25 seconds
Started Aug 04 05:29:13 PM PDT 24
Finished Aug 04 05:29:19 PM PDT 24
Peak memory 212132 kb
Host smart-a7ae17bd-cc33-48ad-a8f4-35ac653308f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3502367981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3502367981
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.981073327
Short name T24
Test name
Test status
Simulation time 954204891 ps
CPU time 99.44 seconds
Started Aug 04 05:29:01 PM PDT 24
Finished Aug 04 05:30:40 PM PDT 24
Peak memory 237776 kb
Host smart-3b634711-cf03-4981-9a97-b84c8c221d44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981073327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.981073327
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2135421687
Short name T325
Test name
Test status
Simulation time 181548016 ps
CPU time 5.61 seconds
Started Aug 04 05:29:11 PM PDT 24
Finished Aug 04 05:29:17 PM PDT 24
Peak memory 212096 kb
Host smart-6d857bee-4b33-4a7d-93a1-91fadedd8f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135421687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2135421687
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1184602693
Short name T272
Test name
Test status
Simulation time 895543057 ps
CPU time 18.06 seconds
Started Aug 04 05:29:03 PM PDT 24
Finished Aug 04 05:29:22 PM PDT 24
Peak memory 215712 kb
Host smart-7f631bb6-dfdf-4a1a-94b2-c2ce806c5983
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184602693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1184602693
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1122463992
Short name T188
Test name
Test status
Simulation time 10804850357 ps
CPU time 123.29 seconds
Started Aug 04 05:29:13 PM PDT 24
Finished Aug 04 05:31:17 PM PDT 24
Peak memory 226236 kb
Host smart-b3657504-bf65-472e-bbfe-a186ee9ed1fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122463992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1122463992
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.782578003
Short name T197
Test name
Test status
Simulation time 998304897 ps
CPU time 11.28 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:38 PM PDT 24
Peak memory 213008 kb
Host smart-0b83386a-3b0e-429f-ae9b-1e931e6eb3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782578003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.782578003
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2377741495
Short name T303
Test name
Test status
Simulation time 136547762 ps
CPU time 6.25 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:29:34 PM PDT 24
Peak memory 212176 kb
Host smart-11a6ba3c-6b78-438c-b5dd-e91dd7643d5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2377741495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2377741495
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1888468446
Short name T312
Test name
Test status
Simulation time 281414872 ps
CPU time 14.36 seconds
Started Aug 04 05:29:25 PM PDT 24
Finished Aug 04 05:29:39 PM PDT 24
Peak memory 214244 kb
Host smart-d08de402-cf57-47b8-87fa-e6abb24f5a04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888468446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1888468446
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3226085459
Short name T183
Test name
Test status
Simulation time 85710681 ps
CPU time 4.28 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:29:33 PM PDT 24
Peak memory 212000 kb
Host smart-3ad8c430-cc2d-4689-a988-c0efbe4127d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226085459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3226085459
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2496655999
Short name T86
Test name
Test status
Simulation time 693455196 ps
CPU time 9.48 seconds
Started Aug 04 05:29:18 PM PDT 24
Finished Aug 04 05:29:28 PM PDT 24
Peak memory 212876 kb
Host smart-d60b43a8-2116-487b-adcd-a13316a0abc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496655999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2496655999
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3803207392
Short name T164
Test name
Test status
Simulation time 97737443 ps
CPU time 5.67 seconds
Started Aug 04 05:29:22 PM PDT 24
Finished Aug 04 05:29:28 PM PDT 24
Peak memory 212112 kb
Host smart-a9d911fb-0e1f-4e11-a159-a29af057d0f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3803207392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3803207392
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.713298200
Short name T238
Test name
Test status
Simulation time 1131242162 ps
CPU time 12.56 seconds
Started Aug 04 05:29:14 PM PDT 24
Finished Aug 04 05:29:27 PM PDT 24
Peak memory 215552 kb
Host smart-5b257776-d087-4195-8472-c013d4d45b1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713298200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.713298200
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3077413728
Short name T278
Test name
Test status
Simulation time 520194036 ps
CPU time 5.11 seconds
Started Aug 04 05:29:16 PM PDT 24
Finished Aug 04 05:29:21 PM PDT 24
Peak memory 212084 kb
Host smart-29102844-e4e4-4a7a-8d46-71d568523037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077413728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3077413728
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3219683634
Short name T240
Test name
Test status
Simulation time 2174709936 ps
CPU time 117.06 seconds
Started Aug 04 05:29:21 PM PDT 24
Finished Aug 04 05:31:18 PM PDT 24
Peak memory 229096 kb
Host smart-5bfa7f1a-9213-41a5-a2fa-0b88d863203f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219683634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3219683634
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4131228654
Short name T213
Test name
Test status
Simulation time 2096187908 ps
CPU time 8.88 seconds
Started Aug 04 05:29:24 PM PDT 24
Finished Aug 04 05:29:33 PM PDT 24
Peak memory 212084 kb
Host smart-5796c31a-08f3-42e5-9eb4-6df9c43f65ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131228654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.4131228654
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3130875956
Short name T206
Test name
Test status
Simulation time 2236565904 ps
CPU time 6.26 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:29:34 PM PDT 24
Peak memory 212232 kb
Host smart-ab81abd6-3196-4e87-9e2b-df14e7dfc149
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3130875956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3130875956
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2026054288
Short name T82
Test name
Test status
Simulation time 294757510 ps
CPU time 12.68 seconds
Started Aug 04 05:29:19 PM PDT 24
Finished Aug 04 05:29:32 PM PDT 24
Peak memory 213252 kb
Host smart-9076125c-a59f-4e4d-967b-44abb5d9e419
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026054288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2026054288
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.415566120
Short name T324
Test name
Test status
Simulation time 95975709 ps
CPU time 4.18 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:29:32 PM PDT 24
Peak memory 212020 kb
Host smart-6371e7ea-d93d-49c3-9347-6eb85d3e1e9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415566120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.415566120
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3271090338
Short name T288
Test name
Test status
Simulation time 1964047109 ps
CPU time 95.36 seconds
Started Aug 04 05:29:25 PM PDT 24
Finished Aug 04 05:31:00 PM PDT 24
Peak memory 213308 kb
Host smart-1e6dd1e4-ef08-405e-8e30-c57d612d15e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271090338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3271090338
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1675358668
Short name T38
Test name
Test status
Simulation time 362842844 ps
CPU time 9.64 seconds
Started Aug 04 05:29:32 PM PDT 24
Finished Aug 04 05:29:42 PM PDT 24
Peak memory 213000 kb
Host smart-947b2318-dace-408d-b380-46562bc95a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675358668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1675358668
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1295701571
Short name T153
Test name
Test status
Simulation time 101893465 ps
CPU time 5.76 seconds
Started Aug 04 05:29:25 PM PDT 24
Finished Aug 04 05:29:31 PM PDT 24
Peak memory 212096 kb
Host smart-277a8673-50fa-4713-8039-4fb3fd232283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1295701571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1295701571
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.958385955
Short name T67
Test name
Test status
Simulation time 454364684 ps
CPU time 12.56 seconds
Started Aug 04 05:29:18 PM PDT 24
Finished Aug 04 05:29:30 PM PDT 24
Peak memory 214360 kb
Host smart-831cbbee-80b7-4e01-b52d-95551c49f5ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958385955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.958385955
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.261117046
Short name T175
Test name
Test status
Simulation time 86637615 ps
CPU time 4.27 seconds
Started Aug 04 05:29:23 PM PDT 24
Finished Aug 04 05:29:28 PM PDT 24
Peak memory 212084 kb
Host smart-e02ee12c-d8fb-4a13-a63c-73dfa72d4322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261117046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.261117046
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3617159895
Short name T169
Test name
Test status
Simulation time 7977056520 ps
CPU time 83.73 seconds
Started Aug 04 05:29:25 PM PDT 24
Finished Aug 04 05:30:49 PM PDT 24
Peak memory 228400 kb
Host smart-74bba4f4-9242-4035-a403-b80d9ee22e2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617159895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3617159895
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.633438511
Short name T202
Test name
Test status
Simulation time 266546824 ps
CPU time 11.54 seconds
Started Aug 04 05:29:20 PM PDT 24
Finished Aug 04 05:29:32 PM PDT 24
Peak memory 216472 kb
Host smart-1b743824-18ee-4dbf-b563-498cec3eb4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633438511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.633438511
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2878664493
Short name T184
Test name
Test status
Simulation time 130992076 ps
CPU time 9.28 seconds
Started Aug 04 05:29:25 PM PDT 24
Finished Aug 04 05:29:35 PM PDT 24
Peak memory 212100 kb
Host smart-314e4081-063e-474f-a22e-205c91c0036d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878664493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2878664493
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.4198309746
Short name T133
Test name
Test status
Simulation time 835698062 ps
CPU time 4.99 seconds
Started Aug 04 05:29:30 PM PDT 24
Finished Aug 04 05:29:35 PM PDT 24
Peak memory 212000 kb
Host smart-b6008dde-6797-422c-af75-18c102a0d894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198309746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.4198309746
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3716230510
Short name T177
Test name
Test status
Simulation time 1241108184 ps
CPU time 6.82 seconds
Started Aug 04 05:29:24 PM PDT 24
Finished Aug 04 05:29:31 PM PDT 24
Peak memory 212060 kb
Host smart-2cf94d33-6839-4cfc-9fc7-8c0b60ea4e4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3716230510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3716230510
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.847257978
Short name T9
Test name
Test status
Simulation time 415878334 ps
CPU time 18.97 seconds
Started Aug 04 05:29:33 PM PDT 24
Finished Aug 04 05:29:52 PM PDT 24
Peak memory 215908 kb
Host smart-fe2e5193-3a57-4f85-9456-e3296cf26a6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847257978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.847257978
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3443889865
Short name T248
Test name
Test status
Simulation time 12029024532 ps
CPU time 448.21 seconds
Started Aug 04 05:29:18 PM PDT 24
Finished Aug 04 05:36:46 PM PDT 24
Peak memory 226820 kb
Host smart-65e03ae0-b8e8-4289-9985-94f441d9670f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443889865 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.3443889865
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2679533721
Short name T209
Test name
Test status
Simulation time 1654254527 ps
CPU time 4.21 seconds
Started Aug 04 05:29:24 PM PDT 24
Finished Aug 04 05:29:29 PM PDT 24
Peak memory 211996 kb
Host smart-9b5d27b4-fafc-487e-8605-bc0482139c8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679533721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2679533721
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1409437165
Short name T309
Test name
Test status
Simulation time 1777625984 ps
CPU time 11.12 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:29:38 PM PDT 24
Peak memory 212956 kb
Host smart-69709c79-e708-40c6-9e30-7d6b4b3b51d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409437165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1409437165
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1337969619
Short name T298
Test name
Test status
Simulation time 893421993 ps
CPU time 12.12 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:29:40 PM PDT 24
Peak memory 214680 kb
Host smart-2bb874df-48c9-4916-ab42-e54d3640d0b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337969619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1337969619
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2119042700
Short name T8
Test name
Test status
Simulation time 127241161 ps
CPU time 4.94 seconds
Started Aug 04 05:29:25 PM PDT 24
Finished Aug 04 05:29:30 PM PDT 24
Peak memory 211968 kb
Host smart-c025562d-7d08-472e-b436-885be1eca382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119042700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2119042700
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2439703026
Short name T216
Test name
Test status
Simulation time 4540053191 ps
CPU time 137.2 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:31:45 PM PDT 24
Peak memory 234376 kb
Host smart-2df8be18-e083-4c01-bef4-1727fc21e05a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439703026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2439703026
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.754292948
Short name T134
Test name
Test status
Simulation time 507507307 ps
CPU time 8.6 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:29:37 PM PDT 24
Peak memory 212124 kb
Host smart-5405bab3-dd6b-4c15-bc75-7c51f061c271
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=754292948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.754292948
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2046299448
Short name T266
Test name
Test status
Simulation time 1022135006 ps
CPU time 18.28 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:29:47 PM PDT 24
Peak memory 216932 kb
Host smart-82bbbc9b-a782-4a1f-b711-b08f6a9eb3b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046299448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2046299448
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3964199010
Short name T250
Test name
Test status
Simulation time 598021958 ps
CPU time 4.16 seconds
Started Aug 04 05:29:24 PM PDT 24
Finished Aug 04 05:29:28 PM PDT 24
Peak memory 211996 kb
Host smart-f55b1c3e-d1f7-4ae2-965e-04bffbe99c52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964199010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3964199010
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1230478488
Short name T274
Test name
Test status
Simulation time 2941630855 ps
CPU time 78.67 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:30:46 PM PDT 24
Peak memory 234352 kb
Host smart-f02bf27d-13a6-4316-882a-e20b1b659065
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230478488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1230478488
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.221034291
Short name T85
Test name
Test status
Simulation time 595118172 ps
CPU time 9.5 seconds
Started Aug 04 05:29:29 PM PDT 24
Finished Aug 04 05:29:38 PM PDT 24
Peak memory 212904 kb
Host smart-f1e6cf80-8565-4a15-b930-ab37079009f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221034291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.221034291
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3994640911
Short name T283
Test name
Test status
Simulation time 279942412 ps
CPU time 6.28 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:29:34 PM PDT 24
Peak memory 212124 kb
Host smart-f82f0aae-ccbb-466c-a877-71858522114d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3994640911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3994640911
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.4291271743
Short name T319
Test name
Test status
Simulation time 226285982 ps
CPU time 11.22 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:29:39 PM PDT 24
Peak memory 214512 kb
Host smart-0105fb03-8958-4a6d-8fc6-1204762c09a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291271743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.4291271743
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3062315708
Short name T131
Test name
Test status
Simulation time 249579540 ps
CPU time 5.12 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:31 PM PDT 24
Peak memory 211996 kb
Host smart-a84fd667-1d55-4fa4-b56e-b21850f669de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062315708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3062315708
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3370982362
Short name T199
Test name
Test status
Simulation time 1939553600 ps
CPU time 118.19 seconds
Started Aug 04 05:29:30 PM PDT 24
Finished Aug 04 05:31:28 PM PDT 24
Peak memory 229104 kb
Host smart-6730e49c-3f2f-4d59-b950-9d7b46a16976
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370982362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3370982362
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3996746385
Short name T292
Test name
Test status
Simulation time 875262892 ps
CPU time 9.28 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:29:37 PM PDT 24
Peak memory 213148 kb
Host smart-d3327ba1-2df8-44d5-9483-7413e3f7888a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996746385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3996746385
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3126840937
Short name T102
Test name
Test status
Simulation time 143065460 ps
CPU time 6.37 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:32 PM PDT 24
Peak memory 212360 kb
Host smart-e17303d9-c4ab-4f4f-9960-9320139d6d1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3126840937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3126840937
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3301708313
Short name T31
Test name
Test status
Simulation time 754903803 ps
CPU time 14.35 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:29:43 PM PDT 24
Peak memory 215732 kb
Host smart-fdab2248-6f24-4a1b-ad8c-54f19b5ae1f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301708313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3301708313
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.909320155
Short name T144
Test name
Test status
Simulation time 126575612 ps
CPU time 5.14 seconds
Started Aug 04 05:29:13 PM PDT 24
Finished Aug 04 05:29:18 PM PDT 24
Peak memory 212056 kb
Host smart-77cf7bee-2066-4003-b433-305bf6c0f173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909320155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.909320155
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.200000937
Short name T289
Test name
Test status
Simulation time 76898154384 ps
CPU time 278.41 seconds
Started Aug 04 05:29:04 PM PDT 24
Finished Aug 04 05:33:42 PM PDT 24
Peak memory 234916 kb
Host smart-085a592a-5cd6-4382-904c-c9bd713f133f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200000937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.200000937
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.477561743
Short name T7
Test name
Test status
Simulation time 175517595 ps
CPU time 9.48 seconds
Started Aug 04 05:29:07 PM PDT 24
Finished Aug 04 05:29:17 PM PDT 24
Peak memory 212860 kb
Host smart-a05940e4-b47b-4f86-a3bf-de48e0edae74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477561743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.477561743
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3292445800
Short name T275
Test name
Test status
Simulation time 241840799 ps
CPU time 5.48 seconds
Started Aug 04 05:29:02 PM PDT 24
Finished Aug 04 05:29:07 PM PDT 24
Peak memory 212076 kb
Host smart-0899b363-a1df-4447-ab3f-c0dfde3a8613
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3292445800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3292445800
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1312031419
Short name T20
Test name
Test status
Simulation time 345853908 ps
CPU time 103.61 seconds
Started Aug 04 05:29:15 PM PDT 24
Finished Aug 04 05:30:59 PM PDT 24
Peak memory 237404 kb
Host smart-a3c80832-9345-4a28-90ad-afce23a86f34
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312031419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1312031419
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1196558333
Short name T70
Test name
Test status
Simulation time 645448153 ps
CPU time 5.68 seconds
Started Aug 04 05:29:16 PM PDT 24
Finished Aug 04 05:29:21 PM PDT 24
Peak memory 212488 kb
Host smart-03078c19-b4c9-47a7-b45e-eb5811145d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196558333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1196558333
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.488998989
Short name T226
Test name
Test status
Simulation time 201902053 ps
CPU time 11.4 seconds
Started Aug 04 05:29:06 PM PDT 24
Finished Aug 04 05:29:18 PM PDT 24
Peak memory 214708 kb
Host smart-cc0e43f9-b561-48aa-911c-a3215c1d4e15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488998989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.488998989
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.809324925
Short name T320
Test name
Test status
Simulation time 44087390559 ps
CPU time 9362.69 seconds
Started Aug 04 05:29:04 PM PDT 24
Finished Aug 04 08:05:08 PM PDT 24
Peak memory 232340 kb
Host smart-c64bd3b4-eff9-440b-9b76-452a274977fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809324925 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.809324925
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.616157676
Short name T130
Test name
Test status
Simulation time 1651822207 ps
CPU time 4.31 seconds
Started Aug 04 05:29:29 PM PDT 24
Finished Aug 04 05:29:34 PM PDT 24
Peak memory 212024 kb
Host smart-802591fb-5e71-4a61-933f-d8e3509794c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616157676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.616157676
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.899004056
Short name T195
Test name
Test status
Simulation time 2202368376 ps
CPU time 134.29 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:31:40 PM PDT 24
Peak memory 240044 kb
Host smart-f70bb2d1-2fdc-409b-8ed1-a91577db0596
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899004056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.899004056
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3962799595
Short name T166
Test name
Test status
Simulation time 667769281 ps
CPU time 9.5 seconds
Started Aug 04 05:29:44 PM PDT 24
Finished Aug 04 05:29:54 PM PDT 24
Peak memory 212892 kb
Host smart-4e6fb8cd-65cd-41fb-a825-eaad99e8d315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962799595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3962799595
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.4072670133
Short name T173
Test name
Test status
Simulation time 538179119 ps
CPU time 6.48 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:33 PM PDT 24
Peak memory 212144 kb
Host smart-5a0a61e9-3b00-4553-98a7-b2fd63e6654a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4072670133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.4072670133
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2223850616
Short name T221
Test name
Test status
Simulation time 191894067 ps
CPU time 14.07 seconds
Started Aug 04 05:29:19 PM PDT 24
Finished Aug 04 05:29:33 PM PDT 24
Peak memory 213520 kb
Host smart-de4b5af0-0cac-43ab-b6bb-ee2287974f22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223850616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2223850616
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1773286360
Short name T87
Test name
Test status
Simulation time 334406607 ps
CPU time 4.1 seconds
Started Aug 04 05:29:17 PM PDT 24
Finished Aug 04 05:29:21 PM PDT 24
Peak memory 211960 kb
Host smart-28ace68d-75f1-48bf-81fc-56232fc8770d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773286360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1773286360
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.553851905
Short name T205
Test name
Test status
Simulation time 8910672108 ps
CPU time 209.29 seconds
Started Aug 04 05:29:31 PM PDT 24
Finished Aug 04 05:33:01 PM PDT 24
Peak memory 226216 kb
Host smart-47067121-7f8e-421a-80fb-ba1c382eb8af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553851905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.553851905
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3135040576
Short name T4
Test name
Test status
Simulation time 174782521 ps
CPU time 9.36 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:29:37 PM PDT 24
Peak memory 213032 kb
Host smart-6080b55b-2eba-4f98-83b6-3007fd3d413d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135040576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3135040576
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3103315759
Short name T126
Test name
Test status
Simulation time 98592804 ps
CPU time 5.72 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:29:33 PM PDT 24
Peak memory 212156 kb
Host smart-d0580f26-10de-4aa0-b178-8003624d4231
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3103315759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3103315759
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3672518369
Short name T211
Test name
Test status
Simulation time 435249830 ps
CPU time 20.58 seconds
Started Aug 04 05:29:23 PM PDT 24
Finished Aug 04 05:29:43 PM PDT 24
Peak memory 216984 kb
Host smart-177b0cb4-663c-4c12-b29d-176ca5ec281f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672518369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3672518369
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2584677401
Short name T138
Test name
Test status
Simulation time 334249693 ps
CPU time 4.16 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:31 PM PDT 24
Peak memory 212072 kb
Host smart-aec6cc7b-d3aa-4830-ab78-941df3cb050b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584677401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2584677401
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.578639215
Short name T194
Test name
Test status
Simulation time 1211976361 ps
CPU time 88.95 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:30:56 PM PDT 24
Peak memory 238428 kb
Host smart-0a2a3bbf-f227-4cce-bf3b-e9e9ff68b27f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578639215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.578639215
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1683996741
Short name T196
Test name
Test status
Simulation time 4090016134 ps
CPU time 16.51 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:43 PM PDT 24
Peak memory 212772 kb
Host smart-85264611-cf07-4be3-b7fc-9ee139c61edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683996741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1683996741
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3227261714
Short name T241
Test name
Test status
Simulation time 418964611 ps
CPU time 5.43 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:29:34 PM PDT 24
Peak memory 212168 kb
Host smart-01448d5c-7a49-49d0-a0d4-85be6ab2f9d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3227261714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3227261714
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2145336152
Short name T66
Test name
Test status
Simulation time 2675130219 ps
CPU time 14.39 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:41 PM PDT 24
Peak memory 215516 kb
Host smart-9279298b-9a0f-47ca-a2d3-813bc3fe7e6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145336152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2145336152
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2541650821
Short name T83
Test name
Test status
Simulation time 126985551 ps
CPU time 5.06 seconds
Started Aug 04 05:29:25 PM PDT 24
Finished Aug 04 05:29:30 PM PDT 24
Peak memory 212032 kb
Host smart-ae32e31a-7076-491c-85b9-6b98e5f6dada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541650821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2541650821
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1184361208
Short name T160
Test name
Test status
Simulation time 4504360226 ps
CPU time 106.93 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:31:15 PM PDT 24
Peak memory 225536 kb
Host smart-49c1692f-287c-46eb-8b0f-4cf47c5c81ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184361208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1184361208
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3178551235
Short name T293
Test name
Test status
Simulation time 760404813 ps
CPU time 9.43 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:29:38 PM PDT 24
Peak memory 213008 kb
Host smart-f2573d6b-fd27-4790-85eb-97658d241d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178551235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3178551235
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2973096245
Short name T280
Test name
Test status
Simulation time 204616378 ps
CPU time 6.41 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:33 PM PDT 24
Peak memory 212112 kb
Host smart-455145b1-580b-413a-bbe1-12f24817a9d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2973096245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2973096245
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.706512219
Short name T135
Test name
Test status
Simulation time 485683042 ps
CPU time 7.22 seconds
Started Aug 04 05:29:31 PM PDT 24
Finished Aug 04 05:29:38 PM PDT 24
Peak memory 212100 kb
Host smart-38caa44f-fd18-4f20-b524-f63bddd6c90e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706512219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.706512219
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3974322501
Short name T178
Test name
Test status
Simulation time 90020432 ps
CPU time 4.21 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:29:32 PM PDT 24
Peak memory 212016 kb
Host smart-e2d11b09-17e1-495a-9a98-00603a0aae52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974322501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3974322501
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2065796519
Short name T186
Test name
Test status
Simulation time 1235111577 ps
CPU time 63.99 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:30:32 PM PDT 24
Peak memory 234324 kb
Host smart-2cf2a2d1-aa30-4331-8f04-56c63a4d873d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065796519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2065796519
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.101658780
Short name T273
Test name
Test status
Simulation time 988140836 ps
CPU time 15.7 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:43 PM PDT 24
Peak memory 212940 kb
Host smart-9a5399a9-1c37-4743-be1c-574d53159b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101658780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.101658780
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.422893842
Short name T214
Test name
Test status
Simulation time 139460540 ps
CPU time 6.69 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:29:35 PM PDT 24
Peak memory 212048 kb
Host smart-57fa4c60-bd68-46a8-b5d7-1095f230b5e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=422893842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.422893842
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3593601700
Short name T212
Test name
Test status
Simulation time 2818784813 ps
CPU time 21.37 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:29:50 PM PDT 24
Peak memory 216032 kb
Host smart-5fae245a-79a9-4070-b8cd-b82ad1475b34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593601700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3593601700
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2515179703
Short name T44
Test name
Test status
Simulation time 54246524727 ps
CPU time 2109.01 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 06:04:36 PM PDT 24
Peak memory 236652 kb
Host smart-f7e9ca66-526f-429b-ada8-376375c7371f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515179703 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2515179703
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.54396764
Short name T3
Test name
Test status
Simulation time 378578486 ps
CPU time 5.03 seconds
Started Aug 04 05:29:32 PM PDT 24
Finished Aug 04 05:29:37 PM PDT 24
Peak memory 212060 kb
Host smart-6931ac83-24c1-4ed7-a841-4115560136b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54396764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.54396764
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1807090215
Short name T127
Test name
Test status
Simulation time 1058939007 ps
CPU time 78.79 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:30:45 PM PDT 24
Peak memory 234288 kb
Host smart-c6ee2a67-27b2-4014-8089-f94d273bb5c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807090215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1807090215
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.425171271
Short name T41
Test name
Test status
Simulation time 880867083 ps
CPU time 9.38 seconds
Started Aug 04 05:29:25 PM PDT 24
Finished Aug 04 05:29:35 PM PDT 24
Peak memory 212964 kb
Host smart-1c0b365e-ee53-4f46-8a85-3d5c7dd90a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425171271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.425171271
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.798769755
Short name T305
Test name
Test status
Simulation time 527047393 ps
CPU time 6.39 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:32 PM PDT 24
Peak memory 212144 kb
Host smart-884830ad-3c57-4776-81b4-a6a4cbda683d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=798769755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.798769755
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3922952216
Short name T14
Test name
Test status
Simulation time 379588153 ps
CPU time 22.83 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:50 PM PDT 24
Peak memory 215916 kb
Host smart-c5c73c25-9356-4d94-814d-6201a8f8a85d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922952216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3922952216
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2617911968
Short name T261
Test name
Test status
Simulation time 509711086 ps
CPU time 7.87 seconds
Started Aug 04 05:29:36 PM PDT 24
Finished Aug 04 05:29:44 PM PDT 24
Peak memory 212036 kb
Host smart-e92c38b2-5f03-4990-88b0-863951fec6e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617911968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2617911968
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.582044495
Short name T287
Test name
Test status
Simulation time 8940083656 ps
CPU time 86.49 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:30:55 PM PDT 24
Peak memory 229040 kb
Host smart-11c06208-e1e2-4e47-b0f3-c58aefa96a81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582044495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.582044495
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.573705268
Short name T198
Test name
Test status
Simulation time 510292047 ps
CPU time 10.86 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:29:39 PM PDT 24
Peak memory 212820 kb
Host smart-bd532407-d26a-4b5f-978c-c01139114d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573705268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.573705268
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.4294852845
Short name T219
Test name
Test status
Simulation time 1158828686 ps
CPU time 5.76 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:33 PM PDT 24
Peak memory 212048 kb
Host smart-7c8ee58a-f4b2-48ab-9eb4-ccbca342a41e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294852845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.4294852845
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.50851910
Short name T290
Test name
Test status
Simulation time 161082618 ps
CPU time 8.22 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:29:36 PM PDT 24
Peak memory 212132 kb
Host smart-14d3f04a-4a12-407f-ad46-cc23588d66f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50851910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 26.rom_ctrl_stress_all.50851910
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.775882864
Short name T215
Test name
Test status
Simulation time 133432000 ps
CPU time 5.26 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:31 PM PDT 24
Peak memory 211952 kb
Host smart-a6c3afa4-6260-4305-8bc8-f52283a00387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775882864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.775882864
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.180706594
Short name T316
Test name
Test status
Simulation time 18103031903 ps
CPU time 67.2 seconds
Started Aug 04 05:29:29 PM PDT 24
Finished Aug 04 05:30:36 PM PDT 24
Peak memory 213460 kb
Host smart-b2aa78d7-91e6-490e-9416-7bd1c2c7bcdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180706594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.180706594
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.640140314
Short name T176
Test name
Test status
Simulation time 5209830091 ps
CPU time 16.01 seconds
Started Aug 04 05:29:22 PM PDT 24
Finished Aug 04 05:29:38 PM PDT 24
Peak memory 213264 kb
Host smart-1e5592b7-3db2-41b6-b705-ab1372158be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640140314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.640140314
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3281683221
Short name T323
Test name
Test status
Simulation time 563462221 ps
CPU time 5.63 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:29:34 PM PDT 24
Peak memory 212176 kb
Host smart-fd7c908c-caf7-4125-a6eb-56deb1355346
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3281683221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3281683221
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.47994378
Short name T142
Test name
Test status
Simulation time 1117744038 ps
CPU time 14.95 seconds
Started Aug 04 05:29:29 PM PDT 24
Finished Aug 04 05:29:44 PM PDT 24
Peak memory 214100 kb
Host smart-0c7ce164-ec55-4c33-9800-5b0bd90178a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47994378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 27.rom_ctrl_stress_all.47994378
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.222532885
Short name T308
Test name
Test status
Simulation time 168884346673 ps
CPU time 1128.71 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:48:16 PM PDT 24
Peak memory 233792 kb
Host smart-80f6ab92-b687-4a26-a218-c77ecc9d56d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222532885 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.222532885
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2385874382
Short name T284
Test name
Test status
Simulation time 653542565 ps
CPU time 5.13 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:29:33 PM PDT 24
Peak memory 212008 kb
Host smart-f76dcc2c-210a-4b51-a790-838fc4c27a20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385874382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2385874382
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1941828214
Short name T122
Test name
Test status
Simulation time 3558212689 ps
CPU time 11.5 seconds
Started Aug 04 05:29:21 PM PDT 24
Finished Aug 04 05:29:33 PM PDT 24
Peak memory 212996 kb
Host smart-2f2c8fcf-11af-4d89-afd7-23dd092c8dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941828214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1941828214
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.4161730695
Short name T245
Test name
Test status
Simulation time 144557592 ps
CPU time 6.53 seconds
Started Aug 04 05:29:29 PM PDT 24
Finished Aug 04 05:29:36 PM PDT 24
Peak memory 212188 kb
Host smart-86c0cd37-30ca-480f-ad60-caadbfafad8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4161730695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.4161730695
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2314998745
Short name T10
Test name
Test status
Simulation time 314071510 ps
CPU time 13.97 seconds
Started Aug 04 05:29:19 PM PDT 24
Finished Aug 04 05:29:33 PM PDT 24
Peak memory 215228 kb
Host smart-7d0344ac-53a0-4193-ae40-17b960fc885e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314998745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2314998745
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.911952666
Short name T43
Test name
Test status
Simulation time 3630197730 ps
CPU time 138.07 seconds
Started Aug 04 05:29:25 PM PDT 24
Finished Aug 04 05:31:44 PM PDT 24
Peak memory 221280 kb
Host smart-32441cf3-08ec-45c3-8e34-673fb0f075bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911952666 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.911952666
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1881233815
Short name T231
Test name
Test status
Simulation time 127096925 ps
CPU time 5.14 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:32 PM PDT 24
Peak memory 211904 kb
Host smart-e8cd3acb-e424-4572-81ec-0e5ed5c2caa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881233815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1881233815
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1133957698
Short name T154
Test name
Test status
Simulation time 2211640180 ps
CPU time 65.91 seconds
Started Aug 04 05:29:32 PM PDT 24
Finished Aug 04 05:30:38 PM PDT 24
Peak memory 213420 kb
Host smart-4ac1ff69-4a09-4bbf-b927-0aeda9fc43cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133957698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1133957698
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3487250491
Short name T217
Test name
Test status
Simulation time 175873335 ps
CPU time 9.37 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:36 PM PDT 24
Peak memory 213168 kb
Host smart-f3a19150-9c40-4e27-9be8-8583a3b9583c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487250491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3487250491
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3252969010
Short name T265
Test name
Test status
Simulation time 137550870 ps
CPU time 6.29 seconds
Started Aug 04 05:29:29 PM PDT 24
Finished Aug 04 05:29:35 PM PDT 24
Peak memory 212096 kb
Host smart-22ab66e2-80d7-45ba-8e46-25dd6dbd0a49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3252969010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3252969010
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1714788830
Short name T313
Test name
Test status
Simulation time 771908503 ps
CPU time 11.87 seconds
Started Aug 04 05:29:30 PM PDT 24
Finished Aug 04 05:29:42 PM PDT 24
Peak memory 214720 kb
Host smart-a76726a1-63fa-4895-83d0-1fac2c57f226
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714788830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1714788830
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2597438505
Short name T236
Test name
Test status
Simulation time 349787555 ps
CPU time 4.26 seconds
Started Aug 04 05:29:06 PM PDT 24
Finished Aug 04 05:29:11 PM PDT 24
Peak memory 211968 kb
Host smart-88553596-da65-4fce-a5e2-47cc4b7f7062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597438505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2597438505
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2278992741
Short name T16
Test name
Test status
Simulation time 7864326535 ps
CPU time 134.15 seconds
Started Aug 04 05:29:11 PM PDT 24
Finished Aug 04 05:31:25 PM PDT 24
Peak memory 213448 kb
Host smart-feb6934b-9b33-4dd7-b928-3a2979f1043d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278992741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2278992741
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.616384471
Short name T182
Test name
Test status
Simulation time 171927587 ps
CPU time 9.24 seconds
Started Aug 04 05:29:04 PM PDT 24
Finished Aug 04 05:29:14 PM PDT 24
Peak memory 212836 kb
Host smart-929a0924-2913-40e2-861c-8bdab315ea66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616384471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.616384471
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3684719991
Short name T88
Test name
Test status
Simulation time 140824511 ps
CPU time 6.39 seconds
Started Aug 04 05:29:15 PM PDT 24
Finished Aug 04 05:29:21 PM PDT 24
Peak memory 212056 kb
Host smart-34b1ef1c-a7db-41c5-a6c5-9021918ce3eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3684719991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3684719991
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2283821941
Short name T81
Test name
Test status
Simulation time 2252252477 ps
CPU time 6.39 seconds
Started Aug 04 05:29:09 PM PDT 24
Finished Aug 04 05:29:15 PM PDT 24
Peak memory 212200 kb
Host smart-180f31c1-34bd-4f56-9ad2-a0558878ad43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283821941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2283821941
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3547824905
Short name T69
Test name
Test status
Simulation time 1112753302 ps
CPU time 17.3 seconds
Started Aug 04 05:28:57 PM PDT 24
Finished Aug 04 05:29:15 PM PDT 24
Peak memory 215964 kb
Host smart-b254505b-5094-44c6-a21d-1def08af8724
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547824905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3547824905
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2963074133
Short name T30
Test name
Test status
Simulation time 351305192 ps
CPU time 4.17 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:31 PM PDT 24
Peak memory 212060 kb
Host smart-88b0f62f-7d1b-4f8f-81cf-6fbf58c19ca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963074133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2963074133
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3323039505
Short name T26
Test name
Test status
Simulation time 5729033318 ps
CPU time 97.28 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:31:05 PM PDT 24
Peak memory 234448 kb
Host smart-ccb3183a-8c62-4afe-9c41-b2429a03afc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323039505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3323039505
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1333636319
Short name T291
Test name
Test status
Simulation time 258189873 ps
CPU time 11.01 seconds
Started Aug 04 05:29:32 PM PDT 24
Finished Aug 04 05:29:43 PM PDT 24
Peak memory 212828 kb
Host smart-03d63786-4a2c-4472-9490-15538017ffac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333636319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1333636319
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2990178830
Short name T317
Test name
Test status
Simulation time 260106139 ps
CPU time 6.25 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:29:35 PM PDT 24
Peak memory 212168 kb
Host smart-72c25c53-c7a9-4d63-a304-d703d0d8df54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2990178830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2990178830
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2399258781
Short name T286
Test name
Test status
Simulation time 139147983 ps
CPU time 11.43 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:37 PM PDT 24
Peak memory 212028 kb
Host smart-6dafcafc-e384-48da-8c70-af8d3ef30e4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399258781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2399258781
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2741838449
Short name T105
Test name
Test status
Simulation time 103625883314 ps
CPU time 1031.66 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:46:39 PM PDT 24
Peak memory 236644 kb
Host smart-86f4a8b3-ffac-4363-a307-64d63822cc98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741838449 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2741838449
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2837859101
Short name T285
Test name
Test status
Simulation time 131223234 ps
CPU time 5.26 seconds
Started Aug 04 05:29:29 PM PDT 24
Finished Aug 04 05:29:35 PM PDT 24
Peak memory 212012 kb
Host smart-1b865f96-b1aa-4165-9ec1-a601446562ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837859101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2837859101
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2222620818
Short name T120
Test name
Test status
Simulation time 1988513492 ps
CPU time 95.34 seconds
Started Aug 04 05:29:32 PM PDT 24
Finished Aug 04 05:31:07 PM PDT 24
Peak memory 225228 kb
Host smart-8193e816-2ee0-4044-b6e4-9fd4fa4ef7ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222620818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2222620818
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2738940344
Short name T25
Test name
Test status
Simulation time 1033586574 ps
CPU time 15.54 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:41 PM PDT 24
Peak memory 212728 kb
Host smart-a689619a-b5b1-4ea5-b02b-abf569130a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738940344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2738940344
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.166767807
Short name T165
Test name
Test status
Simulation time 367983883 ps
CPU time 6.61 seconds
Started Aug 04 05:29:25 PM PDT 24
Finished Aug 04 05:29:32 PM PDT 24
Peak memory 212176 kb
Host smart-2519d623-4827-4eb3-8d28-fbc9cc521e77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=166767807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.166767807
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1283533180
Short name T136
Test name
Test status
Simulation time 1139997932 ps
CPU time 16.36 seconds
Started Aug 04 05:29:29 PM PDT 24
Finished Aug 04 05:29:46 PM PDT 24
Peak memory 214228 kb
Host smart-e03d3175-70d1-4244-b6e9-3f7e060d3f3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283533180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1283533180
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3239482827
Short name T243
Test name
Test status
Simulation time 131162555 ps
CPU time 4.99 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:32 PM PDT 24
Peak memory 212252 kb
Host smart-7d8aa21a-9f43-43f7-b239-e5dc4bf426ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239482827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3239482827
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2785191906
Short name T28
Test name
Test status
Simulation time 4131655518 ps
CPU time 100.91 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:31:09 PM PDT 24
Peak memory 238464 kb
Host smart-71616394-84d8-4f79-8c7f-ad967ea88d3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785191906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2785191906
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2021249718
Short name T237
Test name
Test status
Simulation time 699771787 ps
CPU time 9.73 seconds
Started Aug 04 05:29:29 PM PDT 24
Finished Aug 04 05:29:39 PM PDT 24
Peak memory 213148 kb
Host smart-82e5e46e-42ed-4c84-a069-355f14b5b559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021249718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2021249718
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1456286801
Short name T146
Test name
Test status
Simulation time 97162070 ps
CPU time 5.73 seconds
Started Aug 04 05:29:33 PM PDT 24
Finished Aug 04 05:29:39 PM PDT 24
Peak memory 212060 kb
Host smart-81e60cd1-c23c-4764-aba7-ffe205556d10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1456286801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1456286801
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.479720619
Short name T189
Test name
Test status
Simulation time 266967766 ps
CPU time 10.77 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:29:39 PM PDT 24
Peak memory 212368 kb
Host smart-f0e44521-81e9-4f28-a62e-a96fab160dd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479720619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.479720619
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.4121754545
Short name T46
Test name
Test status
Simulation time 76492029250 ps
CPU time 779.74 seconds
Started Aug 04 05:29:29 PM PDT 24
Finished Aug 04 05:42:29 PM PDT 24
Peak memory 231124 kb
Host smart-ae2077d2-da26-4f40-97a8-c8ae9d7f65b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121754545 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.4121754545
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1918138357
Short name T143
Test name
Test status
Simulation time 495237828 ps
CPU time 5.02 seconds
Started Aug 04 05:29:30 PM PDT 24
Finished Aug 04 05:29:35 PM PDT 24
Peak memory 212084 kb
Host smart-80d0ccb8-cec8-4bd1-8e60-fce248261958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918138357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1918138357
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2066575094
Short name T37
Test name
Test status
Simulation time 17885533024 ps
CPU time 80.09 seconds
Started Aug 04 05:29:22 PM PDT 24
Finished Aug 04 05:30:42 PM PDT 24
Peak memory 235544 kb
Host smart-d9c8c39a-fbcb-4a40-ab64-e3ac2f43e7de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066575094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2066575094
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1767872699
Short name T260
Test name
Test status
Simulation time 348597253 ps
CPU time 9.69 seconds
Started Aug 04 05:29:31 PM PDT 24
Finished Aug 04 05:29:41 PM PDT 24
Peak memory 212836 kb
Host smart-38ac23ff-622b-4e22-81ab-e4ac38c49e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767872699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1767872699
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1354084647
Short name T17
Test name
Test status
Simulation time 542922721 ps
CPU time 6.15 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:29:35 PM PDT 24
Peak memory 212096 kb
Host smart-2a048223-e499-44d7-a415-90660d8dca19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1354084647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1354084647
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3067515247
Short name T63
Test name
Test status
Simulation time 2161817194 ps
CPU time 26.31 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:29:54 PM PDT 24
Peak memory 216032 kb
Host smart-4c1dcc7f-7680-405b-aae1-a04ab482d3fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067515247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3067515247
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4047538997
Short name T168
Test name
Test status
Simulation time 350396550 ps
CPU time 4.16 seconds
Started Aug 04 05:29:32 PM PDT 24
Finished Aug 04 05:29:36 PM PDT 24
Peak memory 212024 kb
Host smart-bc228050-7aaa-4858-b473-68c30e80d739
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047538997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4047538997
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2473602319
Short name T239
Test name
Test status
Simulation time 1907208901 ps
CPU time 65.92 seconds
Started Aug 04 05:29:21 PM PDT 24
Finished Aug 04 05:30:27 PM PDT 24
Peak memory 228124 kb
Host smart-bb5f7b76-7a01-47e9-bd73-8a4c914cdce6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473602319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2473602319
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3595931199
Short name T125
Test name
Test status
Simulation time 256630201 ps
CPU time 11.17 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:38 PM PDT 24
Peak memory 212824 kb
Host smart-00b03374-7bee-4aee-9bbf-538957a581c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595931199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3595931199
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2117521362
Short name T128
Test name
Test status
Simulation time 138025594 ps
CPU time 6.45 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:33 PM PDT 24
Peak memory 212064 kb
Host smart-9f8c4b99-b6b4-4340-87c3-73199291c0ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2117521362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2117521362
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2861143299
Short name T269
Test name
Test status
Simulation time 294138656 ps
CPU time 13.77 seconds
Started Aug 04 05:29:25 PM PDT 24
Finished Aug 04 05:29:39 PM PDT 24
Peak memory 214280 kb
Host smart-942617ec-75bf-4771-b4cf-f5744b76d37e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861143299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2861143299
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.834063283
Short name T282
Test name
Test status
Simulation time 132095975 ps
CPU time 5.05 seconds
Started Aug 04 05:29:38 PM PDT 24
Finished Aug 04 05:29:43 PM PDT 24
Peak memory 212080 kb
Host smart-05b7b176-205f-46c0-96b3-fd8ff06b9176
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834063283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.834063283
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2808986262
Short name T151
Test name
Test status
Simulation time 5693309985 ps
CPU time 86.34 seconds
Started Aug 04 05:29:32 PM PDT 24
Finished Aug 04 05:30:58 PM PDT 24
Peak memory 213492 kb
Host smart-bebd71ef-43aa-4fd0-96cc-3e03a6311a5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808986262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2808986262
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2397041872
Short name T246
Test name
Test status
Simulation time 519284086 ps
CPU time 11.52 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:29:39 PM PDT 24
Peak memory 212824 kb
Host smart-4124741b-52c5-445c-959e-ed83b5e8491a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397041872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2397041872
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2798915030
Short name T147
Test name
Test status
Simulation time 198603442 ps
CPU time 5.7 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:32 PM PDT 24
Peak memory 212100 kb
Host smart-cd96c6c5-26c6-4f92-9a97-51cbafbfc095
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2798915030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2798915030
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.199707893
Short name T71
Test name
Test status
Simulation time 315868675 ps
CPU time 8.15 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:35 PM PDT 24
Peak memory 212756 kb
Host smart-c413e175-cba1-4529-a7da-2eff8bc8bee6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199707893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.199707893
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2793914741
Short name T139
Test name
Test status
Simulation time 90305528 ps
CPU time 4.37 seconds
Started Aug 04 05:29:29 PM PDT 24
Finished Aug 04 05:29:33 PM PDT 24
Peak memory 212024 kb
Host smart-36611e0f-38d9-493b-8f4e-70fb0bebf5e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793914741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2793914741
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.4049160112
Short name T307
Test name
Test status
Simulation time 9941745446 ps
CPU time 118.6 seconds
Started Aug 04 05:29:38 PM PDT 24
Finished Aug 04 05:31:37 PM PDT 24
Peak memory 237856 kb
Host smart-14260728-a64e-46b5-95f4-89b1e2d3f6ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049160112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.4049160112
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3462447435
Short name T170
Test name
Test status
Simulation time 175744159 ps
CPU time 9.74 seconds
Started Aug 04 05:29:29 PM PDT 24
Finished Aug 04 05:29:39 PM PDT 24
Peak memory 213068 kb
Host smart-7c89777f-d269-43db-96bd-e562b63e15a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462447435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3462447435
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.525286098
Short name T32
Test name
Test status
Simulation time 528881310 ps
CPU time 8.89 seconds
Started Aug 04 05:29:36 PM PDT 24
Finished Aug 04 05:29:45 PM PDT 24
Peak memory 212048 kb
Host smart-c709532f-f83f-449e-9335-98848b7e02d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=525286098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.525286098
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2681027617
Short name T150
Test name
Test status
Simulation time 1371218815 ps
CPU time 14.25 seconds
Started Aug 04 05:29:35 PM PDT 24
Finished Aug 04 05:29:49 PM PDT 24
Peak memory 215808 kb
Host smart-d7334e21-c24a-4065-83d9-5bce9a101bfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681027617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2681027617
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2895093788
Short name T234
Test name
Test status
Simulation time 334027512 ps
CPU time 4.2 seconds
Started Aug 04 05:29:36 PM PDT 24
Finished Aug 04 05:29:40 PM PDT 24
Peak memory 212032 kb
Host smart-a350c5f7-8db4-48e9-a50c-906f73d6977c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895093788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2895093788
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1219488697
Short name T18
Test name
Test status
Simulation time 7133986565 ps
CPU time 108.82 seconds
Started Aug 04 05:29:30 PM PDT 24
Finished Aug 04 05:31:19 PM PDT 24
Peak memory 226304 kb
Host smart-21315fca-5b19-490c-a941-047f70b5a057
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219488697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1219488697
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1339273910
Short name T251
Test name
Test status
Simulation time 1035720173 ps
CPU time 11.2 seconds
Started Aug 04 05:29:36 PM PDT 24
Finished Aug 04 05:29:48 PM PDT 24
Peak memory 212896 kb
Host smart-b61fba1b-6080-41a0-b5e4-d783dc2853d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339273910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1339273910
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3655822089
Short name T281
Test name
Test status
Simulation time 275366754 ps
CPU time 5.93 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:29:34 PM PDT 24
Peak memory 211968 kb
Host smart-c19a017a-e35d-427c-adfc-2708a3f3b799
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3655822089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3655822089
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.471396647
Short name T193
Test name
Test status
Simulation time 214005727 ps
CPU time 12.22 seconds
Started Aug 04 05:29:29 PM PDT 24
Finished Aug 04 05:29:41 PM PDT 24
Peak memory 213524 kb
Host smart-58b19ea0-97ed-49cc-8079-f7db1727d88f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471396647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.471396647
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2049518569
Short name T47
Test name
Test status
Simulation time 433887818027 ps
CPU time 2432.13 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 06:10:00 PM PDT 24
Peak memory 241104 kb
Host smart-5c42a848-87e0-4dab-8f85-72a26d3e39c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049518569 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2049518569
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.17526370
Short name T179
Test name
Test status
Simulation time 130608671 ps
CPU time 5.05 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:29:34 PM PDT 24
Peak memory 211952 kb
Host smart-2b055bd7-67f2-429d-ab2d-c16f03abdb01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17526370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.17526370
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1610786056
Short name T259
Test name
Test status
Simulation time 1650733408 ps
CPU time 47.44 seconds
Started Aug 04 05:29:34 PM PDT 24
Finished Aug 04 05:30:21 PM PDT 24
Peak memory 237004 kb
Host smart-2d09b270-93be-462d-aae0-f3103669d728
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610786056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1610786056
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3221714067
Short name T124
Test name
Test status
Simulation time 260672102 ps
CPU time 11.28 seconds
Started Aug 04 05:29:37 PM PDT 24
Finished Aug 04 05:29:48 PM PDT 24
Peak memory 212924 kb
Host smart-5641dd10-6909-4e7d-9051-189418eed3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221714067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3221714067
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.234218841
Short name T148
Test name
Test status
Simulation time 277306300 ps
CPU time 6.43 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:29:35 PM PDT 24
Peak memory 212200 kb
Host smart-1f649120-2dd9-400a-b405-8420be5684d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=234218841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.234218841
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1297132802
Short name T200
Test name
Test status
Simulation time 768939227 ps
CPU time 18.72 seconds
Started Aug 04 05:29:33 PM PDT 24
Finished Aug 04 05:29:51 PM PDT 24
Peak memory 215140 kb
Host smart-433e4971-c8d9-448a-822e-0580a0cf3df6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297132802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1297132802
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3352625754
Short name T22
Test name
Test status
Simulation time 85657175 ps
CPU time 4.32 seconds
Started Aug 04 05:29:34 PM PDT 24
Finished Aug 04 05:29:39 PM PDT 24
Peak memory 212048 kb
Host smart-dc03cb9c-0444-448a-a25a-8df20cddb4d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352625754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3352625754
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1348160959
Short name T304
Test name
Test status
Simulation time 17500458302 ps
CPU time 110.53 seconds
Started Aug 04 05:29:40 PM PDT 24
Finished Aug 04 05:31:31 PM PDT 24
Peak memory 239384 kb
Host smart-0ef8b7d7-a21b-4112-9b08-8e2bf69ec06f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348160959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1348160959
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.677946372
Short name T295
Test name
Test status
Simulation time 988617425 ps
CPU time 10.9 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:29:38 PM PDT 24
Peak memory 212760 kb
Host smart-5a3f71d4-69ec-4765-ac9a-0134425089aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677946372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.677946372
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1814425181
Short name T218
Test name
Test status
Simulation time 134031422 ps
CPU time 6.15 seconds
Started Aug 04 05:29:35 PM PDT 24
Finished Aug 04 05:29:41 PM PDT 24
Peak memory 212168 kb
Host smart-32afc840-efeb-4561-a895-14b152fa5cfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1814425181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1814425181
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.332787125
Short name T68
Test name
Test status
Simulation time 1236779632 ps
CPU time 12.69 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:29:41 PM PDT 24
Peak memory 215176 kb
Host smart-d4739d22-58ec-40c4-b2df-bef2bf60bf98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332787125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.332787125
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.959821846
Short name T257
Test name
Test status
Simulation time 142401652836 ps
CPU time 1310.46 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:51:19 PM PDT 24
Peak memory 236600 kb
Host smart-24d86064-9c61-4640-9a6d-a49ed0ba242e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959821846 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.959821846
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.456253211
Short name T161
Test name
Test status
Simulation time 519094957 ps
CPU time 5.06 seconds
Started Aug 04 05:29:09 PM PDT 24
Finished Aug 04 05:29:14 PM PDT 24
Peak memory 212248 kb
Host smart-81110d6e-62f6-4da7-8e28-9a3a4236c411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456253211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.456253211
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.786284428
Short name T185
Test name
Test status
Simulation time 6139747652 ps
CPU time 109.8 seconds
Started Aug 04 05:29:10 PM PDT 24
Finished Aug 04 05:31:00 PM PDT 24
Peak memory 228952 kb
Host smart-6027c202-574a-4e9b-abaf-08e5f5f5eb7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786284428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.786284428
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2074637168
Short name T149
Test name
Test status
Simulation time 340409273 ps
CPU time 9.48 seconds
Started Aug 04 05:29:22 PM PDT 24
Finished Aug 04 05:29:31 PM PDT 24
Peak memory 212936 kb
Host smart-224915de-4e98-4508-b31a-46188cd8c219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074637168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2074637168
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2726086054
Short name T276
Test name
Test status
Simulation time 1120888525 ps
CPU time 5.42 seconds
Started Aug 04 05:29:12 PM PDT 24
Finished Aug 04 05:29:18 PM PDT 24
Peak memory 212084 kb
Host smart-92d9d066-ea6b-45d5-a412-b54fbcaa212c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2726086054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2726086054
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1221419551
Short name T21
Test name
Test status
Simulation time 472026893 ps
CPU time 99.83 seconds
Started Aug 04 05:29:07 PM PDT 24
Finished Aug 04 05:30:47 PM PDT 24
Peak memory 237896 kb
Host smart-654bbfba-34de-45f2-abcf-3b433e8b7dc0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221419551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1221419551
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.533962582
Short name T192
Test name
Test status
Simulation time 377938399 ps
CPU time 5.4 seconds
Started Aug 04 05:29:13 PM PDT 24
Finished Aug 04 05:29:19 PM PDT 24
Peak memory 212084 kb
Host smart-6a0e580a-94c6-4ba8-b740-4cbe83e5fed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533962582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.533962582
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1446713532
Short name T262
Test name
Test status
Simulation time 259514297 ps
CPU time 6.44 seconds
Started Aug 04 05:29:07 PM PDT 24
Finished Aug 04 05:29:14 PM PDT 24
Peak memory 212136 kb
Host smart-fe5fb8b6-7c48-4940-b1f2-f780bb92b0c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446713532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1446713532
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.314568814
Short name T42
Test name
Test status
Simulation time 17463159387 ps
CPU time 7518.66 seconds
Started Aug 04 05:29:21 PM PDT 24
Finished Aug 04 07:34:40 PM PDT 24
Peak memory 232096 kb
Host smart-1a93f03b-256b-4e49-8bbb-5ef14cb05428
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314568814 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.314568814
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1596366735
Short name T249
Test name
Test status
Simulation time 129688732 ps
CPU time 5.11 seconds
Started Aug 04 05:29:29 PM PDT 24
Finished Aug 04 05:29:34 PM PDT 24
Peak memory 212020 kb
Host smart-5b16f4bc-5e79-4019-8ec9-1f67f95e8194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596366735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1596366735
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2040139021
Short name T187
Test name
Test status
Simulation time 12520727094 ps
CPU time 146.07 seconds
Started Aug 04 05:29:34 PM PDT 24
Finished Aug 04 05:32:00 PM PDT 24
Peak memory 214448 kb
Host smart-a8f97e91-4bb7-46b0-9cc0-09e8f836b1fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040139021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2040139021
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1527258787
Short name T242
Test name
Test status
Simulation time 1274497242 ps
CPU time 9.46 seconds
Started Aug 04 05:29:32 PM PDT 24
Finished Aug 04 05:29:42 PM PDT 24
Peak memory 212776 kb
Host smart-1aaaa807-4b2c-42f6-beb5-de1fa3718175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527258787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1527258787
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.428581131
Short name T100
Test name
Test status
Simulation time 271095707 ps
CPU time 6.72 seconds
Started Aug 04 05:29:34 PM PDT 24
Finished Aug 04 05:29:41 PM PDT 24
Peak memory 212116 kb
Host smart-8e396ee9-0f2a-4410-98d4-8867df3f60b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=428581131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.428581131
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.837425904
Short name T162
Test name
Test status
Simulation time 208071842 ps
CPU time 12.12 seconds
Started Aug 04 05:29:32 PM PDT 24
Finished Aug 04 05:29:44 PM PDT 24
Peak memory 214884 kb
Host smart-04a9b4c8-8be8-4338-a90b-9ed27798e026
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837425904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.837425904
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2812683330
Short name T294
Test name
Test status
Simulation time 173095333 ps
CPU time 4.25 seconds
Started Aug 04 05:29:33 PM PDT 24
Finished Aug 04 05:29:38 PM PDT 24
Peak memory 212008 kb
Host smart-020fe56f-aa1f-4d08-8780-ca154043196e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812683330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2812683330
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.294644675
Short name T279
Test name
Test status
Simulation time 2654970293 ps
CPU time 133.93 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:31:42 PM PDT 24
Peak memory 212944 kb
Host smart-d433ff47-96d0-4567-a0cd-8b49729a3be9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294644675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.294644675
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1835464105
Short name T314
Test name
Test status
Simulation time 1390890825 ps
CPU time 9.42 seconds
Started Aug 04 05:29:36 PM PDT 24
Finished Aug 04 05:29:45 PM PDT 24
Peak memory 213284 kb
Host smart-6ec1eb4c-d497-43b5-b3af-6f589d7b1855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835464105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1835464105
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3249544669
Short name T140
Test name
Test status
Simulation time 96416424 ps
CPU time 5.61 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:29:34 PM PDT 24
Peak memory 212064 kb
Host smart-d983aa77-feb9-4411-b9a9-8c80f82ce32e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3249544669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3249544669
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1193766046
Short name T156
Test name
Test status
Simulation time 378365611 ps
CPU time 10.22 seconds
Started Aug 04 05:29:31 PM PDT 24
Finished Aug 04 05:29:42 PM PDT 24
Peak memory 213512 kb
Host smart-7c2daec2-54ae-412e-ac19-03fcf857055f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193766046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1193766046
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.38506730
Short name T256
Test name
Test status
Simulation time 517861796 ps
CPU time 4.93 seconds
Started Aug 04 05:29:39 PM PDT 24
Finished Aug 04 05:29:44 PM PDT 24
Peak memory 212048 kb
Host smart-5d829159-64a9-4c17-aaa0-f9377a4be82b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38506730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.38506730
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3799761577
Short name T172
Test name
Test status
Simulation time 1420681363 ps
CPU time 69.16 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:30:36 PM PDT 24
Peak memory 213232 kb
Host smart-f4cfcec9-bbec-4a6d-a020-78cc4ee2113e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799761577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3799761577
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.212084879
Short name T321
Test name
Test status
Simulation time 173203468 ps
CPU time 9.36 seconds
Started Aug 04 05:29:31 PM PDT 24
Finished Aug 04 05:29:40 PM PDT 24
Peak memory 213108 kb
Host smart-6b8594ae-11a6-4d0c-bff8-cbbbcf7d1907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212084879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.212084879
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4122734060
Short name T201
Test name
Test status
Simulation time 190716714 ps
CPU time 5.29 seconds
Started Aug 04 05:29:37 PM PDT 24
Finished Aug 04 05:29:43 PM PDT 24
Peak memory 212076 kb
Host smart-3e79eac4-2649-499f-b26f-ed6b24a5eed3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122734060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4122734060
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3391104246
Short name T302
Test name
Test status
Simulation time 1496859427 ps
CPU time 9.76 seconds
Started Aug 04 05:29:29 PM PDT 24
Finished Aug 04 05:29:39 PM PDT 24
Peak memory 213292 kb
Host smart-75b995c4-447b-4ac4-86dd-dce108117698
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391104246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3391104246
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2965549842
Short name T45
Test name
Test status
Simulation time 50337311355 ps
CPU time 1906.75 seconds
Started Aug 04 05:29:36 PM PDT 24
Finished Aug 04 06:01:24 PM PDT 24
Peak memory 236636 kb
Host smart-8c92ba9e-5c21-48a9-9740-d29d5d5d32e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965549842 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2965549842
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.693739285
Short name T306
Test name
Test status
Simulation time 86696530 ps
CPU time 4.28 seconds
Started Aug 04 05:29:36 PM PDT 24
Finished Aug 04 05:29:41 PM PDT 24
Peak memory 212072 kb
Host smart-cf11c2a4-d6dc-4ec1-9085-ce95655e6355
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693739285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.693739285
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4175863969
Short name T145
Test name
Test status
Simulation time 4632766531 ps
CPU time 76.01 seconds
Started Aug 04 05:29:37 PM PDT 24
Finished Aug 04 05:30:53 PM PDT 24
Peak memory 238448 kb
Host smart-6d1bc1f8-3ba3-4f11-af76-aa3ce8d347be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175863969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.4175863969
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1249476987
Short name T223
Test name
Test status
Simulation time 986900136 ps
CPU time 16.34 seconds
Started Aug 04 05:29:41 PM PDT 24
Finished Aug 04 05:29:57 PM PDT 24
Peak memory 212888 kb
Host smart-582aa0b3-6389-499f-9627-e41724cebded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249476987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1249476987
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.757499153
Short name T15
Test name
Test status
Simulation time 140570032 ps
CPU time 6.49 seconds
Started Aug 04 05:29:35 PM PDT 24
Finished Aug 04 05:29:42 PM PDT 24
Peak memory 212192 kb
Host smart-db7c2802-2ab3-4929-8193-aaa14ef72d49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=757499153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.757499153
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1456968901
Short name T228
Test name
Test status
Simulation time 288476873 ps
CPU time 6.64 seconds
Started Aug 04 05:29:40 PM PDT 24
Finished Aug 04 05:29:47 PM PDT 24
Peak memory 212136 kb
Host smart-d641c837-a11f-4fb0-a6c3-e79434cf12d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456968901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1456968901
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.513633338
Short name T318
Test name
Test status
Simulation time 1038408100 ps
CPU time 4.14 seconds
Started Aug 04 05:29:38 PM PDT 24
Finished Aug 04 05:29:42 PM PDT 24
Peak memory 212080 kb
Host smart-053de331-21ff-4510-bcab-8d8460ec78d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513633338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.513633338
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3436369644
Short name T35
Test name
Test status
Simulation time 2417090832 ps
CPU time 133.25 seconds
Started Aug 04 05:29:37 PM PDT 24
Finished Aug 04 05:31:50 PM PDT 24
Peak memory 238456 kb
Host smart-1b0e7b95-189c-40e4-834e-f5de4cb67247
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436369644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3436369644
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1385673906
Short name T180
Test name
Test status
Simulation time 699506678 ps
CPU time 9.33 seconds
Started Aug 04 05:29:34 PM PDT 24
Finished Aug 04 05:29:43 PM PDT 24
Peak memory 213004 kb
Host smart-ad999e1e-84f0-49c2-b790-c54cd217499a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385673906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1385673906
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1728590589
Short name T252
Test name
Test status
Simulation time 559132368 ps
CPU time 6.5 seconds
Started Aug 04 05:29:41 PM PDT 24
Finished Aug 04 05:29:47 PM PDT 24
Peak memory 212084 kb
Host smart-ae9f214e-18e9-4417-a077-c34a56ea7d7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1728590589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1728590589
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.753810751
Short name T264
Test name
Test status
Simulation time 472648998 ps
CPU time 7.66 seconds
Started Aug 04 05:29:40 PM PDT 24
Finished Aug 04 05:29:48 PM PDT 24
Peak memory 212024 kb
Host smart-5e06abbb-8035-4e37-9c11-7a2a6f083267
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753810751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.753810751
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.4099453321
Short name T158
Test name
Test status
Simulation time 115320106 ps
CPU time 4.37 seconds
Started Aug 04 05:29:41 PM PDT 24
Finished Aug 04 05:29:46 PM PDT 24
Peak memory 212024 kb
Host smart-9d3b55ae-50e0-4af0-8e0a-e706894403fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099453321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.4099453321
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1019162981
Short name T36
Test name
Test status
Simulation time 36353172843 ps
CPU time 173.32 seconds
Started Aug 04 05:29:41 PM PDT 24
Finished Aug 04 05:32:34 PM PDT 24
Peak memory 226096 kb
Host smart-af5b8f57-1f50-48a5-9d7b-aa65a8a4450d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019162981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1019162981
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3303548974
Short name T233
Test name
Test status
Simulation time 699116458 ps
CPU time 9.26 seconds
Started Aug 04 05:29:38 PM PDT 24
Finished Aug 04 05:29:48 PM PDT 24
Peak memory 212944 kb
Host smart-cb755eb1-d210-4d14-9ba1-fafec8f83c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303548974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3303548974
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.568187459
Short name T253
Test name
Test status
Simulation time 375474515 ps
CPU time 5.63 seconds
Started Aug 04 05:29:40 PM PDT 24
Finished Aug 04 05:29:46 PM PDT 24
Peak memory 212124 kb
Host smart-159b3706-87d3-423f-869e-d6c0e709642a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=568187459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.568187459
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.216448889
Short name T207
Test name
Test status
Simulation time 537352105 ps
CPU time 7.01 seconds
Started Aug 04 05:29:36 PM PDT 24
Finished Aug 04 05:29:43 PM PDT 24
Peak memory 212092 kb
Host smart-5d73d31f-4bbe-4fc0-9db6-30fcc27eb60b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216448889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.216448889
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2114047782
Short name T12
Test name
Test status
Simulation time 137050495356 ps
CPU time 1447.29 seconds
Started Aug 04 05:29:40 PM PDT 24
Finished Aug 04 05:53:47 PM PDT 24
Peak memory 236620 kb
Host smart-7df5025a-9ccc-4eeb-84df-f28fb849e02b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114047782 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2114047782
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1927918687
Short name T296
Test name
Test status
Simulation time 129622621 ps
CPU time 5.08 seconds
Started Aug 04 05:29:38 PM PDT 24
Finished Aug 04 05:29:43 PM PDT 24
Peak memory 212080 kb
Host smart-fc71569e-a6bc-4745-9799-df52b81037ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927918687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1927918687
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.867253357
Short name T181
Test name
Test status
Simulation time 6179099573 ps
CPU time 164.72 seconds
Started Aug 04 05:29:36 PM PDT 24
Finished Aug 04 05:32:20 PM PDT 24
Peak memory 226268 kb
Host smart-8dab9560-f1f4-4ab7-90af-17a7afd4baec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867253357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.867253357
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.583742097
Short name T210
Test name
Test status
Simulation time 336194862 ps
CPU time 9.21 seconds
Started Aug 04 05:29:40 PM PDT 24
Finished Aug 04 05:29:50 PM PDT 24
Peak memory 212932 kb
Host smart-72b25656-c26a-4cfa-bc4d-e7edf7e7c024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583742097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.583742097
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3746956869
Short name T53
Test name
Test status
Simulation time 139799096 ps
CPU time 6.7 seconds
Started Aug 04 05:29:38 PM PDT 24
Finished Aug 04 05:29:44 PM PDT 24
Peak memory 212076 kb
Host smart-20d9863e-dc13-45dd-a9a0-c7d46c5c19ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3746956869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3746956869
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3818086487
Short name T65
Test name
Test status
Simulation time 285972198 ps
CPU time 14.14 seconds
Started Aug 04 05:29:35 PM PDT 24
Finished Aug 04 05:29:50 PM PDT 24
Peak memory 214640 kb
Host smart-8c61e52b-572c-498a-a6cd-632983f08e41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818086487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3818086487
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1261110541
Short name T157
Test name
Test status
Simulation time 197868369 ps
CPU time 5.29 seconds
Started Aug 04 05:29:38 PM PDT 24
Finished Aug 04 05:29:43 PM PDT 24
Peak memory 212076 kb
Host smart-127fd3ee-9bd0-4ba5-afdd-92b27042fcd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261110541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1261110541
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4033931370
Short name T247
Test name
Test status
Simulation time 2196897250 ps
CPU time 122.1 seconds
Started Aug 04 05:29:38 PM PDT 24
Finished Aug 04 05:31:41 PM PDT 24
Peak memory 229296 kb
Host smart-3fc356d7-1761-4262-ace7-3e3b7c594b95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033931370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.4033931370
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2461989762
Short name T40
Test name
Test status
Simulation time 1185832335 ps
CPU time 11.46 seconds
Started Aug 04 05:29:39 PM PDT 24
Finished Aug 04 05:29:51 PM PDT 24
Peak memory 212920 kb
Host smart-8e96531f-91a8-4876-8bbe-85331eea86eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461989762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2461989762
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.812587301
Short name T230
Test name
Test status
Simulation time 190481035 ps
CPU time 5.59 seconds
Started Aug 04 05:29:39 PM PDT 24
Finished Aug 04 05:29:45 PM PDT 24
Peak memory 212116 kb
Host smart-9f368dc1-5b52-4498-9479-b42fa05b40e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=812587301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.812587301
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3508085417
Short name T263
Test name
Test status
Simulation time 205854296 ps
CPU time 11.73 seconds
Started Aug 04 05:29:37 PM PDT 24
Finished Aug 04 05:29:49 PM PDT 24
Peak memory 215888 kb
Host smart-462d604e-c150-49ba-b84e-5243fde27b07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508085417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3508085417
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.410357845
Short name T244
Test name
Test status
Simulation time 272534924 ps
CPU time 5.03 seconds
Started Aug 04 05:29:45 PM PDT 24
Finished Aug 04 05:29:50 PM PDT 24
Peak memory 212040 kb
Host smart-8069bd02-068d-4e9f-b5dd-1118d77864db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410357845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.410357845
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2763066054
Short name T163
Test name
Test status
Simulation time 3703460292 ps
CPU time 109.32 seconds
Started Aug 04 05:29:38 PM PDT 24
Finished Aug 04 05:31:27 PM PDT 24
Peak memory 238476 kb
Host smart-4579aba0-08a7-4f32-b5b9-d5e829d8e809
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763066054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2763066054
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.261053996
Short name T311
Test name
Test status
Simulation time 363465417 ps
CPU time 9.8 seconds
Started Aug 04 05:29:39 PM PDT 24
Finished Aug 04 05:29:49 PM PDT 24
Peak memory 212852 kb
Host smart-7ed3a373-1065-46b2-8e17-cf5925c4663c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261053996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.261053996
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3728468711
Short name T129
Test name
Test status
Simulation time 682289315 ps
CPU time 5.88 seconds
Started Aug 04 05:29:39 PM PDT 24
Finished Aug 04 05:29:45 PM PDT 24
Peak memory 212072 kb
Host smart-bf4d11da-8439-4c02-a522-8b69dfcdc928
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3728468711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3728468711
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2075125725
Short name T141
Test name
Test status
Simulation time 581430351 ps
CPU time 11.35 seconds
Started Aug 04 05:29:40 PM PDT 24
Finished Aug 04 05:29:51 PM PDT 24
Peak memory 214460 kb
Host smart-34e443ae-a315-4fdf-a48d-be5e4ef456a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075125725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2075125725
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1632977658
Short name T258
Test name
Test status
Simulation time 44095367202 ps
CPU time 1398.69 seconds
Started Aug 04 05:29:43 PM PDT 24
Finished Aug 04 05:53:02 PM PDT 24
Peak memory 236644 kb
Host smart-4230603a-9823-4342-ae53-362ec5ac415d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632977658 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.1632977658
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2324123235
Short name T27
Test name
Test status
Simulation time 85801242 ps
CPU time 4.36 seconds
Started Aug 04 05:29:42 PM PDT 24
Finished Aug 04 05:29:46 PM PDT 24
Peak memory 212024 kb
Host smart-c0a675e7-9d65-4bd6-9610-797977500803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324123235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2324123235
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.875230767
Short name T267
Test name
Test status
Simulation time 85188468392 ps
CPU time 210.31 seconds
Started Aug 04 05:29:42 PM PDT 24
Finished Aug 04 05:33:13 PM PDT 24
Peak memory 234632 kb
Host smart-f408dcf3-36b7-4179-b874-9bdcadb6bfa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875230767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.875230767
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1412063609
Short name T155
Test name
Test status
Simulation time 168751858 ps
CPU time 9.73 seconds
Started Aug 04 05:29:42 PM PDT 24
Finished Aug 04 05:29:52 PM PDT 24
Peak memory 212900 kb
Host smart-5512773f-dbd5-4567-a6cb-19ff0e5f988a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412063609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1412063609
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2144405500
Short name T101
Test name
Test status
Simulation time 267693772 ps
CPU time 6.42 seconds
Started Aug 04 05:29:44 PM PDT 24
Finished Aug 04 05:29:51 PM PDT 24
Peak memory 212176 kb
Host smart-864799e1-f4e3-4231-b7e3-aa50f8e3e197
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2144405500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2144405500
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3215230943
Short name T99
Test name
Test status
Simulation time 287573754 ps
CPU time 8.09 seconds
Started Aug 04 05:29:41 PM PDT 24
Finished Aug 04 05:29:49 PM PDT 24
Peak memory 213352 kb
Host smart-a3f7f004-9be4-4fb5-9871-535653814d2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215230943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3215230943
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.592963057
Short name T232
Test name
Test status
Simulation time 824245070 ps
CPU time 4.98 seconds
Started Aug 04 05:29:05 PM PDT 24
Finished Aug 04 05:29:10 PM PDT 24
Peak memory 212024 kb
Host smart-f7fe6b15-2ffb-49ff-ac56-7ea56cf5b353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592963057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.592963057
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1721571632
Short name T208
Test name
Test status
Simulation time 1145436433 ps
CPU time 72.43 seconds
Started Aug 04 05:29:11 PM PDT 24
Finished Aug 04 05:30:28 PM PDT 24
Peak memory 237332 kb
Host smart-65c03741-8b78-4367-8e10-e6428922a8f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721571632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1721571632
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3174409144
Short name T204
Test name
Test status
Simulation time 640985598 ps
CPU time 11.12 seconds
Started Aug 04 05:29:14 PM PDT 24
Finished Aug 04 05:29:25 PM PDT 24
Peak memory 212912 kb
Host smart-cb8a7c02-e2bb-4982-8adc-2b01bee008e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174409144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3174409144
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2642489183
Short name T299
Test name
Test status
Simulation time 294063260 ps
CPU time 6.58 seconds
Started Aug 04 05:29:17 PM PDT 24
Finished Aug 04 05:29:24 PM PDT 24
Peak memory 212072 kb
Host smart-e675c603-dbe5-4308-b7d9-2da675bd08b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2642489183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2642489183
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.624368342
Short name T297
Test name
Test status
Simulation time 524486827 ps
CPU time 9.39 seconds
Started Aug 04 05:29:09 PM PDT 24
Finished Aug 04 05:29:19 PM PDT 24
Peak memory 212192 kb
Host smart-2a16dd8e-b719-44b6-914e-7f9efdce2d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624368342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.624368342
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2456140116
Short name T322
Test name
Test status
Simulation time 636272060 ps
CPU time 20.06 seconds
Started Aug 04 05:29:25 PM PDT 24
Finished Aug 04 05:29:45 PM PDT 24
Peak memory 216768 kb
Host smart-503593e7-3a3b-443c-b6b0-e420065e5d7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456140116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2456140116
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2239102575
Short name T315
Test name
Test status
Simulation time 127011673 ps
CPU time 5.15 seconds
Started Aug 04 05:29:15 PM PDT 24
Finished Aug 04 05:29:20 PM PDT 24
Peak memory 211952 kb
Host smart-85f22708-7e24-43b9-843f-ac3822003bda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239102575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2239102575
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2902641975
Short name T119
Test name
Test status
Simulation time 2536314335 ps
CPU time 123.94 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:31:32 PM PDT 24
Peak memory 213460 kb
Host smart-9b18d1fa-41d9-42f2-ad78-ec2f8535d564
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902641975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2902641975
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2626086606
Short name T121
Test name
Test status
Simulation time 169647453 ps
CPU time 9.68 seconds
Started Aug 04 05:29:13 PM PDT 24
Finished Aug 04 05:29:22 PM PDT 24
Peak memory 212868 kb
Host smart-3996fc3a-d3ca-4b83-85f7-4ffe4bed64d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626086606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2626086606
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2514519009
Short name T190
Test name
Test status
Simulation time 390404149 ps
CPU time 5.68 seconds
Started Aug 04 05:29:11 PM PDT 24
Finished Aug 04 05:29:17 PM PDT 24
Peak memory 212188 kb
Host smart-d35a10fe-b700-4e69-b7bc-46243a9077ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2514519009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2514519009
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.299713311
Short name T64
Test name
Test status
Simulation time 2165681652 ps
CPU time 6.39 seconds
Started Aug 04 05:29:09 PM PDT 24
Finished Aug 04 05:29:15 PM PDT 24
Peak memory 212244 kb
Host smart-c091b63b-b1c4-4319-939a-b2d0a9db8345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299713311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.299713311
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2027589154
Short name T277
Test name
Test status
Simulation time 892930566 ps
CPU time 14.36 seconds
Started Aug 04 05:29:11 PM PDT 24
Finished Aug 04 05:29:26 PM PDT 24
Peak memory 214648 kb
Host smart-c1a13306-9414-42b0-a1e7-32d4204e3e32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027589154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2027589154
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1126000740
Short name T310
Test name
Test status
Simulation time 336472673 ps
CPU time 4.26 seconds
Started Aug 04 05:29:22 PM PDT 24
Finished Aug 04 05:29:26 PM PDT 24
Peak memory 212044 kb
Host smart-6cce5285-b789-4226-875c-519ed1a5f595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126000740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1126000740
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3062538906
Short name T227
Test name
Test status
Simulation time 48115381124 ps
CPU time 122.77 seconds
Started Aug 04 05:29:14 PM PDT 24
Finished Aug 04 05:31:17 PM PDT 24
Peak memory 226272 kb
Host smart-5ecdac69-040b-4684-8817-6954193786ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062538906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3062538906
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1134625790
Short name T167
Test name
Test status
Simulation time 347295797 ps
CPU time 9.4 seconds
Started Aug 04 05:29:16 PM PDT 24
Finished Aug 04 05:29:25 PM PDT 24
Peak memory 212904 kb
Host smart-e1eb183f-3831-4a83-9970-a0be22a85d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134625790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1134625790
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1259344539
Short name T225
Test name
Test status
Simulation time 141091169 ps
CPU time 6.59 seconds
Started Aug 04 05:29:25 PM PDT 24
Finished Aug 04 05:29:32 PM PDT 24
Peak memory 212140 kb
Host smart-628185e6-6eed-4865-b690-5d0d7ac44c2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1259344539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1259344539
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2565662631
Short name T84
Test name
Test status
Simulation time 559222840 ps
CPU time 6.49 seconds
Started Aug 04 05:29:19 PM PDT 24
Finished Aug 04 05:29:26 PM PDT 24
Peak memory 212160 kb
Host smart-0a557198-bbca-42fc-9064-2e535f4b1481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565662631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2565662631
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1174068225
Short name T174
Test name
Test status
Simulation time 364660108904 ps
CPU time 1382.41 seconds
Started Aug 04 05:29:26 PM PDT 24
Finished Aug 04 05:52:30 PM PDT 24
Peak memory 234528 kb
Host smart-b68c7364-8993-4d5f-91bd-f2916e8528b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174068225 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.1174068225
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3410707756
Short name T29
Test name
Test status
Simulation time 1784764864 ps
CPU time 5.13 seconds
Started Aug 04 05:29:22 PM PDT 24
Finished Aug 04 05:29:28 PM PDT 24
Peak memory 212036 kb
Host smart-3edf9baa-528a-437f-a267-58f3b37d551c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410707756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3410707756
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.33233707
Short name T34
Test name
Test status
Simulation time 1722238948 ps
CPU time 111.8 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:31:20 PM PDT 24
Peak memory 234324 kb
Host smart-32383fd4-96a8-40a0-841d-daf4121da3f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33233707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_cor
rupt_sig_fatal_chk.33233707
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2445149474
Short name T254
Test name
Test status
Simulation time 390424365 ps
CPU time 10.94 seconds
Started Aug 04 05:29:23 PM PDT 24
Finished Aug 04 05:29:34 PM PDT 24
Peak memory 212876 kb
Host smart-4446bbef-04bd-4b08-9c49-f8148275e15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445149474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2445149474
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.951668978
Short name T300
Test name
Test status
Simulation time 463056840 ps
CPU time 5.61 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:29:33 PM PDT 24
Peak memory 212124 kb
Host smart-1a022016-f474-470d-a4a4-2b0614330ad0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=951668978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.951668978
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2327850656
Short name T171
Test name
Test status
Simulation time 190764102 ps
CPU time 5.44 seconds
Started Aug 04 05:29:14 PM PDT 24
Finished Aug 04 05:29:19 PM PDT 24
Peak memory 212040 kb
Host smart-16d0e871-0017-4e1c-8611-21657fe848b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327850656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2327850656
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.523143659
Short name T255
Test name
Test status
Simulation time 4625695861 ps
CPU time 12.77 seconds
Started Aug 04 05:29:14 PM PDT 24
Finished Aug 04 05:29:27 PM PDT 24
Peak memory 214940 kb
Host smart-be1f6df8-fa1b-4c6d-9924-8f9f34a1d6d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523143659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.523143659
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3927337125
Short name T152
Test name
Test status
Simulation time 519562380 ps
CPU time 5.07 seconds
Started Aug 04 05:29:19 PM PDT 24
Finished Aug 04 05:29:25 PM PDT 24
Peak memory 212072 kb
Host smart-f71954d9-f601-4189-80cf-8fc55acafc18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927337125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3927337125
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2145326038
Short name T137
Test name
Test status
Simulation time 6193625165 ps
CPU time 113.44 seconds
Started Aug 04 05:29:28 PM PDT 24
Finished Aug 04 05:31:22 PM PDT 24
Peak memory 234792 kb
Host smart-cbe8c47d-e56c-42af-aa0a-60aa0d76415c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145326038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2145326038
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.149262091
Short name T224
Test name
Test status
Simulation time 519122310 ps
CPU time 11.1 seconds
Started Aug 04 05:29:25 PM PDT 24
Finished Aug 04 05:29:36 PM PDT 24
Peak memory 212884 kb
Host smart-61849d6a-4c27-4377-a613-b810080d76d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149262091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.149262091
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2387400773
Short name T203
Test name
Test status
Simulation time 375105783 ps
CPU time 5.63 seconds
Started Aug 04 05:29:16 PM PDT 24
Finished Aug 04 05:29:22 PM PDT 24
Peak memory 212096 kb
Host smart-d56c03eb-157c-4eab-bbab-9570908a9410
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2387400773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2387400773
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2249848584
Short name T271
Test name
Test status
Simulation time 182837249 ps
CPU time 5.4 seconds
Started Aug 04 05:29:14 PM PDT 24
Finished Aug 04 05:29:20 PM PDT 24
Peak memory 212076 kb
Host smart-d08d7f0b-fd35-4392-9ad5-e63715210d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249848584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2249848584
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3887190856
Short name T132
Test name
Test status
Simulation time 781960720 ps
CPU time 6.16 seconds
Started Aug 04 05:29:17 PM PDT 24
Finished Aug 04 05:29:24 PM PDT 24
Peak memory 212040 kb
Host smart-04bd813e-7051-428d-b0c2-07f194cbc943
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887190856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3887190856
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.732345024
Short name T13
Test name
Test status
Simulation time 67232763831 ps
CPU time 1247.96 seconds
Started Aug 04 05:29:27 PM PDT 24
Finished Aug 04 05:50:16 PM PDT 24
Peak memory 236648 kb
Host smart-4e79e175-1fc3-4956-aeb7-c4f6716f3a6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732345024 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.732345024
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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