Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.26 96.89 91.99 97.67 100.00 98.62 97.30 98.37


Total test records in report: 415
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T294 /workspace/coverage/default/26.rom_ctrl_stress_all.773792180 Aug 05 05:41:18 PM PDT 24 Aug 05 05:41:41 PM PDT 24 545059793 ps
T295 /workspace/coverage/default/21.rom_ctrl_stress_all.776517968 Aug 05 05:41:06 PM PDT 24 Aug 05 05:41:15 PM PDT 24 391447727 ps
T296 /workspace/coverage/default/31.rom_ctrl_alert_test.653964935 Aug 05 05:41:17 PM PDT 24 Aug 05 05:41:23 PM PDT 24 599240553 ps
T297 /workspace/coverage/default/12.rom_ctrl_stress_all.757697334 Aug 05 05:41:01 PM PDT 24 Aug 05 05:41:18 PM PDT 24 225197627 ps
T298 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1485392815 Aug 05 05:41:27 PM PDT 24 Aug 05 05:41:39 PM PDT 24 251831737 ps
T299 /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.917162473 Aug 05 05:40:57 PM PDT 24 Aug 05 06:27:59 PM PDT 24 65570578352 ps
T300 /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1708714587 Aug 05 05:40:52 PM PDT 24 Aug 05 05:56:13 PM PDT 24 48951586447 ps
T301 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2982216199 Aug 05 05:41:23 PM PDT 24 Aug 05 05:41:34 PM PDT 24 507005493 ps
T302 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2358338722 Aug 05 05:41:22 PM PDT 24 Aug 05 05:41:33 PM PDT 24 260523019 ps
T303 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1094759007 Aug 05 05:41:22 PM PDT 24 Aug 05 05:55:04 PM PDT 24 79313442596 ps
T304 /workspace/coverage/default/1.rom_ctrl_stress_all.3959411765 Aug 05 05:41:00 PM PDT 24 Aug 05 05:41:14 PM PDT 24 280441913 ps
T305 /workspace/coverage/default/34.rom_ctrl_stress_all.207270889 Aug 05 05:41:23 PM PDT 24 Aug 05 05:41:39 PM PDT 24 1012291967 ps
T306 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.995354629 Aug 05 05:41:22 PM PDT 24 Aug 05 05:41:33 PM PDT 24 993973108 ps
T307 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3074722378 Aug 05 05:41:06 PM PDT 24 Aug 05 05:41:16 PM PDT 24 175031115 ps
T308 /workspace/coverage/default/2.rom_ctrl_alert_test.2681346416 Aug 05 05:41:00 PM PDT 24 Aug 05 05:41:05 PM PDT 24 86372858 ps
T309 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3488879109 Aug 05 05:41:20 PM PDT 24 Aug 05 05:41:26 PM PDT 24 310839971 ps
T310 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.104347128 Aug 05 05:41:08 PM PDT 24 Aug 05 05:41:17 PM PDT 24 669029217 ps
T311 /workspace/coverage/default/0.rom_ctrl_smoke.1407106832 Aug 05 05:40:41 PM PDT 24 Aug 05 05:40:48 PM PDT 24 139981987 ps
T99 /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3078652342 Aug 05 05:40:49 PM PDT 24 Aug 05 05:56:52 PM PDT 24 5076019261 ps
T312 /workspace/coverage/default/27.rom_ctrl_stress_all.1794549551 Aug 05 05:41:11 PM PDT 24 Aug 05 05:41:24 PM PDT 24 228811554 ps
T313 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.768616365 Aug 05 05:41:15 PM PDT 24 Aug 05 05:41:26 PM PDT 24 256198389 ps
T314 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2993647209 Aug 05 05:41:19 PM PDT 24 Aug 05 05:41:24 PM PDT 24 103163507 ps
T315 /workspace/coverage/default/45.rom_ctrl_alert_test.3080397223 Aug 05 05:41:36 PM PDT 24 Aug 05 05:41:41 PM PDT 24 1772803091 ps
T316 /workspace/coverage/default/20.rom_ctrl_stress_all.200292807 Aug 05 05:41:14 PM PDT 24 Aug 05 05:41:23 PM PDT 24 155945995 ps
T317 /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2141056867 Aug 05 05:41:12 PM PDT 24 Aug 05 07:16:16 PM PDT 24 29339985801 ps
T318 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1088195526 Aug 05 05:41:12 PM PDT 24 Aug 05 07:12:26 PM PDT 24 16706797647 ps
T319 /workspace/coverage/default/2.rom_ctrl_stress_all.477049582 Aug 05 05:40:57 PM PDT 24 Aug 05 05:41:06 PM PDT 24 471167541 ps
T320 /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.4293872047 Aug 05 05:40:56 PM PDT 24 Aug 05 06:07:57 PM PDT 24 41854733173 ps
T321 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3825733149 Aug 05 05:41:13 PM PDT 24 Aug 05 05:42:45 PM PDT 24 9485945618 ps
T322 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2246301714 Aug 05 05:41:26 PM PDT 24 Aug 05 05:41:37 PM PDT 24 508895248 ps
T323 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1105360496 Aug 05 05:41:11 PM PDT 24 Aug 05 05:43:25 PM PDT 24 2643657993 ps
T324 /workspace/coverage/default/7.rom_ctrl_alert_test.1889971730 Aug 05 05:40:54 PM PDT 24 Aug 05 05:40:59 PM PDT 24 465101173 ps
T325 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.488674352 Aug 05 05:41:11 PM PDT 24 Aug 05 05:41:20 PM PDT 24 169968166 ps
T326 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2496501007 Aug 05 05:41:01 PM PDT 24 Aug 05 05:41:13 PM PDT 24 142910839 ps
T327 /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3798667439 Aug 05 05:41:07 PM PDT 24 Aug 05 05:48:06 PM PDT 24 20880841590 ps
T328 /workspace/coverage/default/9.rom_ctrl_alert_test.3027100183 Aug 05 05:41:01 PM PDT 24 Aug 05 05:41:05 PM PDT 24 350213456 ps
T57 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2009686080 Aug 05 05:03:34 PM PDT 24 Aug 05 05:03:39 PM PDT 24 90109296 ps
T58 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.604413310 Aug 05 05:03:38 PM PDT 24 Aug 05 05:03:44 PM PDT 24 131496454 ps
T59 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.692825438 Aug 05 05:03:41 PM PDT 24 Aug 05 05:03:47 PM PDT 24 97612547 ps
T93 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2062755219 Aug 05 05:03:20 PM PDT 24 Aug 05 05:03:25 PM PDT 24 172258474 ps
T329 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3973587038 Aug 05 05:03:19 PM PDT 24 Aug 05 05:03:26 PM PDT 24 528535420 ps
T65 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4046753945 Aug 05 05:03:18 PM PDT 24 Aug 05 05:03:40 PM PDT 24 532001344 ps
T330 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2135213469 Aug 05 05:03:19 PM PDT 24 Aug 05 05:03:24 PM PDT 24 89795467 ps
T331 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2948634264 Aug 05 05:03:37 PM PDT 24 Aug 05 05:03:42 PM PDT 24 138389771 ps
T94 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3769855779 Aug 05 05:03:22 PM PDT 24 Aug 05 05:03:29 PM PDT 24 183142007 ps
T66 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.861158196 Aug 05 05:03:23 PM PDT 24 Aug 05 05:03:28 PM PDT 24 520603977 ps
T97 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1765974657 Aug 05 05:03:17 PM PDT 24 Aug 05 05:03:23 PM PDT 24 129651516 ps
T67 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.229052645 Aug 05 05:03:45 PM PDT 24 Aug 05 05:03:51 PM PDT 24 310171366 ps
T332 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2815270042 Aug 05 05:03:06 PM PDT 24 Aug 05 05:03:11 PM PDT 24 568054815 ps
T333 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.149068907 Aug 05 05:03:25 PM PDT 24 Aug 05 05:03:30 PM PDT 24 482693127 ps
T334 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.86592479 Aug 05 05:03:06 PM PDT 24 Aug 05 05:03:11 PM PDT 24 115769874 ps
T98 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2227084814 Aug 05 05:03:15 PM PDT 24 Aug 05 05:03:21 PM PDT 24 173112547 ps
T68 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2672501668 Aug 05 05:03:27 PM PDT 24 Aug 05 05:03:32 PM PDT 24 127795806 ps
T54 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.563714268 Aug 05 05:03:15 PM PDT 24 Aug 05 05:03:55 PM PDT 24 9132169581 ps
T95 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3343086436 Aug 05 05:03:19 PM PDT 24 Aug 05 05:03:23 PM PDT 24 173520913 ps
T335 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1407436881 Aug 05 05:03:09 PM PDT 24 Aug 05 05:03:15 PM PDT 24 133945634 ps
T69 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3828268431 Aug 05 05:03:25 PM PDT 24 Aug 05 05:03:31 PM PDT 24 103225914 ps
T336 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2612147657 Aug 05 05:03:17 PM PDT 24 Aug 05 05:03:26 PM PDT 24 133438240 ps
T70 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3441234183 Aug 05 05:03:41 PM PDT 24 Aug 05 05:03:45 PM PDT 24 88749330 ps
T337 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2118717724 Aug 05 05:03:25 PM PDT 24 Aug 05 05:03:32 PM PDT 24 557443565 ps
T338 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.771692830 Aug 05 05:03:49 PM PDT 24 Aug 05 05:03:59 PM PDT 24 2040547581 ps
T55 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1511982941 Aug 05 05:03:16 PM PDT 24 Aug 05 05:03:53 PM PDT 24 387097691 ps
T71 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3640476302 Aug 05 05:03:29 PM PDT 24 Aug 05 05:03:34 PM PDT 24 126867917 ps
T339 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2622501431 Aug 05 05:03:31 PM PDT 24 Aug 05 05:03:36 PM PDT 24 99733079 ps
T72 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.815915532 Aug 05 05:03:17 PM PDT 24 Aug 05 05:03:24 PM PDT 24 469370268 ps
T340 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2141836927 Aug 05 05:03:43 PM PDT 24 Aug 05 05:03:51 PM PDT 24 140468937 ps
T73 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2635330069 Aug 05 05:03:18 PM PDT 24 Aug 05 05:03:23 PM PDT 24 88433984 ps
T341 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.777019880 Aug 05 05:03:23 PM PDT 24 Aug 05 05:03:29 PM PDT 24 636456778 ps
T96 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3942174377 Aug 05 05:03:46 PM PDT 24 Aug 05 05:03:51 PM PDT 24 336300832 ps
T342 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4169368077 Aug 05 05:03:15 PM PDT 24 Aug 05 05:03:20 PM PDT 24 334465446 ps
T343 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2636275158 Aug 05 05:03:33 PM PDT 24 Aug 05 05:03:44 PM PDT 24 536367361 ps
T344 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3977976826 Aug 05 05:03:10 PM PDT 24 Aug 05 05:03:15 PM PDT 24 520910708 ps
T83 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.689403561 Aug 05 05:03:12 PM PDT 24 Aug 05 05:03:18 PM PDT 24 1131285689 ps
T84 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.4292840245 Aug 05 05:03:16 PM PDT 24 Aug 05 05:03:34 PM PDT 24 373459498 ps
T345 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3923691842 Aug 05 05:03:26 PM PDT 24 Aug 05 05:03:31 PM PDT 24 1556610432 ps
T346 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3613495229 Aug 05 05:03:45 PM PDT 24 Aug 05 05:03:50 PM PDT 24 99581850 ps
T85 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4153515439 Aug 05 05:03:17 PM PDT 24 Aug 05 05:03:22 PM PDT 24 543767287 ps
T56 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2557486000 Aug 05 05:03:40 PM PDT 24 Aug 05 05:04:49 PM PDT 24 706772367 ps
T347 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2020654330 Aug 05 05:03:32 PM PDT 24 Aug 05 05:03:39 PM PDT 24 581473990 ps
T348 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2077470635 Aug 05 05:03:41 PM PDT 24 Aug 05 05:03:45 PM PDT 24 336372973 ps
T349 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3373666030 Aug 05 05:03:14 PM PDT 24 Aug 05 05:03:20 PM PDT 24 503324127 ps
T104 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.991019457 Aug 05 05:03:14 PM PDT 24 Aug 05 05:03:52 PM PDT 24 225498111 ps
T350 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3293727993 Aug 05 05:03:21 PM PDT 24 Aug 05 05:03:27 PM PDT 24 326691731 ps
T102 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.160352076 Aug 05 05:03:37 PM PDT 24 Aug 05 05:04:13 PM PDT 24 365754786 ps
T351 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3574680112 Aug 05 05:03:05 PM PDT 24 Aug 05 05:03:09 PM PDT 24 333519430 ps
T86 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2416096468 Aug 05 05:03:21 PM PDT 24 Aug 05 05:03:29 PM PDT 24 1914310622 ps
T352 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1026928508 Aug 05 05:03:38 PM PDT 24 Aug 05 05:03:46 PM PDT 24 88540412 ps
T353 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1092639222 Aug 05 05:03:17 PM PDT 24 Aug 05 05:03:22 PM PDT 24 347826630 ps
T354 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3698847553 Aug 05 05:03:23 PM PDT 24 Aug 05 05:03:32 PM PDT 24 501049009 ps
T355 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2134387968 Aug 05 05:03:28 PM PDT 24 Aug 05 05:03:34 PM PDT 24 145041102 ps
T356 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1442886080 Aug 05 05:03:43 PM PDT 24 Aug 05 05:03:49 PM PDT 24 142208074 ps
T87 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.98907950 Aug 05 05:03:18 PM PDT 24 Aug 05 05:03:46 PM PDT 24 540907840 ps
T100 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.925744013 Aug 05 05:03:16 PM PDT 24 Aug 05 05:04:27 PM PDT 24 1007982996 ps
T357 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2471038494 Aug 05 05:03:09 PM PDT 24 Aug 05 05:03:18 PM PDT 24 500081229 ps
T101 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1269790499 Aug 05 05:03:21 PM PDT 24 Aug 05 05:03:59 PM PDT 24 398118934 ps
T103 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.586925806 Aug 05 05:03:52 PM PDT 24 Aug 05 05:05:03 PM PDT 24 394538649 ps
T105 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2343121376 Aug 05 05:03:38 PM PDT 24 Aug 05 05:04:15 PM PDT 24 692469953 ps
T358 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1000482613 Aug 05 05:03:18 PM PDT 24 Aug 05 05:03:23 PM PDT 24 89107576 ps
T359 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3032832181 Aug 05 05:03:15 PM PDT 24 Aug 05 05:03:21 PM PDT 24 139555902 ps
T360 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2970750954 Aug 05 05:03:13 PM PDT 24 Aug 05 05:03:23 PM PDT 24 1295336001 ps
T361 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.646625841 Aug 05 05:03:18 PM PDT 24 Aug 05 05:03:56 PM PDT 24 420495101 ps
T362 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1887060472 Aug 05 05:03:28 PM PDT 24 Aug 05 05:03:33 PM PDT 24 153044648 ps
T363 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3448081032 Aug 05 05:03:27 PM PDT 24 Aug 05 05:03:36 PM PDT 24 526864858 ps
T88 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1263763965 Aug 05 05:03:27 PM PDT 24 Aug 05 05:03:32 PM PDT 24 415847829 ps
T364 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.409008638 Aug 05 05:03:29 PM PDT 24 Aug 05 05:03:34 PM PDT 24 85812305 ps
T365 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1061410657 Aug 05 05:03:27 PM PDT 24 Aug 05 05:03:38 PM PDT 24 500377756 ps
T366 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.57614315 Aug 05 05:03:45 PM PDT 24 Aug 05 05:03:51 PM PDT 24 592075884 ps
T367 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1835427462 Aug 05 05:03:21 PM PDT 24 Aug 05 05:03:27 PM PDT 24 536098521 ps
T368 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.445591162 Aug 05 05:03:30 PM PDT 24 Aug 05 05:03:35 PM PDT 24 126588626 ps
T369 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.550270203 Aug 05 05:03:35 PM PDT 24 Aug 05 05:03:42 PM PDT 24 85694866 ps
T370 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4085004838 Aug 05 05:03:38 PM PDT 24 Aug 05 05:03:44 PM PDT 24 521482643 ps
T371 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1035154142 Aug 05 05:03:05 PM PDT 24 Aug 05 05:03:11 PM PDT 24 97781923 ps
T89 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1790642781 Aug 05 05:03:19 PM PDT 24 Aug 05 05:03:24 PM PDT 24 521120379 ps
T372 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.137081468 Aug 05 05:03:31 PM PDT 24 Aug 05 05:03:37 PM PDT 24 554242092 ps
T373 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3167138592 Aug 05 05:03:14 PM PDT 24 Aug 05 05:03:21 PM PDT 24 362839189 ps
T374 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.685204675 Aug 05 05:03:45 PM PDT 24 Aug 05 05:03:49 PM PDT 24 175293117 ps
T106 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1359545482 Aug 05 05:03:25 PM PDT 24 Aug 05 05:04:01 PM PDT 24 712489011 ps
T90 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.432143541 Aug 05 05:03:06 PM PDT 24 Aug 05 05:03:11 PM PDT 24 569939039 ps
T375 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1225082356 Aug 05 05:03:17 PM PDT 24 Aug 05 05:03:23 PM PDT 24 587167583 ps
T376 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3015257743 Aug 05 05:03:17 PM PDT 24 Aug 05 05:03:25 PM PDT 24 519019253 ps
T377 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3063125545 Aug 05 05:03:22 PM PDT 24 Aug 05 05:03:41 PM PDT 24 746748576 ps
T378 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1042519385 Aug 05 05:03:14 PM PDT 24 Aug 05 05:03:18 PM PDT 24 169089963 ps
T379 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3543678471 Aug 05 05:03:14 PM PDT 24 Aug 05 05:03:21 PM PDT 24 130204518 ps
T380 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1812150851 Aug 05 05:03:30 PM PDT 24 Aug 05 05:03:35 PM PDT 24 95434773 ps
T381 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1944332790 Aug 05 05:03:11 PM PDT 24 Aug 05 05:03:15 PM PDT 24 346224640 ps
T382 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.997529306 Aug 05 05:03:12 PM PDT 24 Aug 05 05:03:18 PM PDT 24 348009956 ps
T107 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1318571756 Aug 05 05:03:25 PM PDT 24 Aug 05 05:04:35 PM PDT 24 257308782 ps
T383 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2553778473 Aug 05 05:03:32 PM PDT 24 Aug 05 05:03:39 PM PDT 24 143431134 ps
T110 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.458190379 Aug 05 05:03:24 PM PDT 24 Aug 05 05:04:35 PM PDT 24 281664883 ps
T108 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3080372425 Aug 05 05:03:41 PM PDT 24 Aug 05 05:04:18 PM PDT 24 167272934 ps
T384 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3361383452 Aug 05 05:03:07 PM PDT 24 Aug 05 05:03:14 PM PDT 24 90438958 ps
T385 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3871265476 Aug 05 05:03:46 PM PDT 24 Aug 05 05:03:50 PM PDT 24 348656175 ps
T386 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3495711247 Aug 05 05:03:18 PM PDT 24 Aug 05 05:03:25 PM PDT 24 554931420 ps
T91 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1435057296 Aug 05 05:03:19 PM PDT 24 Aug 05 05:03:24 PM PDT 24 175520774 ps
T387 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.158176876 Aug 05 05:03:17 PM PDT 24 Aug 05 05:03:24 PM PDT 24 143764239 ps
T388 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.186669570 Aug 05 05:03:08 PM PDT 24 Aug 05 05:03:13 PM PDT 24 132611868 ps
T389 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3378686316 Aug 05 05:03:34 PM PDT 24 Aug 05 05:04:10 PM PDT 24 564269468 ps
T390 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1644219771 Aug 05 05:03:19 PM PDT 24 Aug 05 05:03:25 PM PDT 24 133131627 ps
T391 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2629196645 Aug 05 05:03:40 PM PDT 24 Aug 05 05:03:45 PM PDT 24 171819506 ps
T392 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.685119762 Aug 05 05:03:30 PM PDT 24 Aug 05 05:03:35 PM PDT 24 827861101 ps
T393 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2632459545 Aug 05 05:03:16 PM PDT 24 Aug 05 05:03:26 PM PDT 24 297110927 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3856891150 Aug 05 05:03:15 PM PDT 24 Aug 05 05:03:22 PM PDT 24 136689817 ps
T395 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.121683095 Aug 05 05:03:27 PM PDT 24 Aug 05 05:03:35 PM PDT 24 332992204 ps
T396 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2389651809 Aug 05 05:03:45 PM PDT 24 Aug 05 05:03:51 PM PDT 24 130815163 ps
T397 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2373965347 Aug 05 05:03:09 PM PDT 24 Aug 05 05:03:14 PM PDT 24 129773652 ps
T398 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.540225197 Aug 05 05:03:19 PM PDT 24 Aug 05 05:03:24 PM PDT 24 1070474319 ps
T399 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.872004541 Aug 05 05:03:32 PM PDT 24 Aug 05 05:03:40 PM PDT 24 172067899 ps
T400 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3403612466 Aug 05 05:03:07 PM PDT 24 Aug 05 05:03:13 PM PDT 24 128515507 ps
T401 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2816014820 Aug 05 05:03:18 PM PDT 24 Aug 05 05:03:24 PM PDT 24 884537775 ps
T402 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2666065351 Aug 05 05:03:38 PM PDT 24 Aug 05 05:04:50 PM PDT 24 532668889 ps
T403 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1580259097 Aug 05 05:03:22 PM PDT 24 Aug 05 05:03:27 PM PDT 24 518414800 ps
T404 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4292676125 Aug 05 05:03:16 PM PDT 24 Aug 05 05:03:24 PM PDT 24 126806414 ps
T92 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.132078310 Aug 05 05:03:21 PM PDT 24 Aug 05 05:03:25 PM PDT 24 133762930 ps
T405 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2399385630 Aug 05 05:03:30 PM PDT 24 Aug 05 05:03:36 PM PDT 24 153460133 ps
T406 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.282096547 Aug 05 05:03:40 PM PDT 24 Aug 05 05:03:48 PM PDT 24 134036240 ps
T407 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2940184545 Aug 05 05:03:31 PM PDT 24 Aug 05 05:03:39 PM PDT 24 128061866 ps
T408 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4156731838 Aug 05 05:03:18 PM PDT 24 Aug 05 05:04:27 PM PDT 24 897298070 ps
T109 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2380016270 Aug 05 05:03:13 PM PDT 24 Aug 05 05:03:49 PM PDT 24 161701949 ps
T409 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1715622304 Aug 05 05:03:17 PM PDT 24 Aug 05 05:03:24 PM PDT 24 529180148 ps
T410 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.419239808 Aug 05 05:03:25 PM PDT 24 Aug 05 05:04:02 PM PDT 24 173975705 ps
T411 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1025469876 Aug 05 05:03:31 PM PDT 24 Aug 05 05:03:36 PM PDT 24 102214726 ps
T412 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1208733451 Aug 05 05:03:20 PM PDT 24 Aug 05 05:04:33 PM PDT 24 1319936058 ps
T413 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1327068166 Aug 05 05:03:48 PM PDT 24 Aug 05 05:03:52 PM PDT 24 375905126 ps
T414 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1671561976 Aug 05 05:03:32 PM PDT 24 Aug 05 05:03:42 PM PDT 24 784652694 ps
T415 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.758134777 Aug 05 05:03:40 PM PDT 24 Aug 05 05:03:44 PM PDT 24 692411269 ps

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2074727540
Short name T5
Test name
Test status
Simulation time 223454902 ps
CPU time 16.57 seconds
Started Aug 05 05:41:03 PM PDT 24
Finished Aug 05 05:41:19 PM PDT 24
Peak memory 214844 kb
Host smart-59c0a5c5-6e7a-4f19-a9e5-750f5e6c0aee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074727540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2074727540
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1187401296
Short name T13
Test name
Test status
Simulation time 277652034461 ps
CPU time 2328.67 seconds
Started Aug 05 05:41:08 PM PDT 24
Finished Aug 05 06:19:57 PM PDT 24
Peak memory 252864 kb
Host smart-a45cfed0-b77f-42ba-bbc0-e5c48167d864
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187401296 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1187401296
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2652356432
Short name T20
Test name
Test status
Simulation time 12945828794 ps
CPU time 134.43 seconds
Started Aug 05 05:41:25 PM PDT 24
Finished Aug 05 05:43:40 PM PDT 24
Peak memory 213400 kb
Host smart-ab7995ea-b262-4a69-a765-3dcfa23c81ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652356432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2652356432
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2557486000
Short name T56
Test name
Test status
Simulation time 706772367 ps
CPU time 68.56 seconds
Started Aug 05 05:03:40 PM PDT 24
Finished Aug 05 05:04:49 PM PDT 24
Peak memory 214256 kb
Host smart-7a6df677-ff6e-4e4a-a31d-8c221809f0cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557486000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2557486000
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3673776896
Short name T24
Test name
Test status
Simulation time 495134846 ps
CPU time 106.83 seconds
Started Aug 05 05:40:47 PM PDT 24
Finished Aug 05 05:42:34 PM PDT 24
Peak memory 238836 kb
Host smart-d801e094-44e3-4428-a5e8-c96ddb7e3b97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673776896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3673776896
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.506624493
Short name T16
Test name
Test status
Simulation time 1692778362 ps
CPU time 17.88 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:41:29 PM PDT 24
Peak memory 215924 kb
Host smart-9a2fa934-d0b2-4925-a52e-5c3589616266
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506624493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.506624493
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.4074789199
Short name T10
Test name
Test status
Simulation time 249609896 ps
CPU time 5.23 seconds
Started Aug 05 05:41:07 PM PDT 24
Finished Aug 05 05:41:12 PM PDT 24
Peak memory 211948 kb
Host smart-f1c7cb7b-7f38-41f9-8dae-54bbffb16ed3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074789199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.4074789199
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4046753945
Short name T65
Test name
Test status
Simulation time 532001344 ps
CPU time 22.46 seconds
Started Aug 05 05:03:18 PM PDT 24
Finished Aug 05 05:03:40 PM PDT 24
Peak memory 211468 kb
Host smart-2bae1a0e-2130-48b3-a15c-e572534b0009
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046753945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.4046753945
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.925744013
Short name T100
Test name
Test status
Simulation time 1007982996 ps
CPU time 70.68 seconds
Started Aug 05 05:03:16 PM PDT 24
Finished Aug 05 05:04:27 PM PDT 24
Peak memory 213912 kb
Host smart-8e1e40df-3c2c-4d61-a81c-0b41abd0c9e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925744013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.925744013
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2581768486
Short name T126
Test name
Test status
Simulation time 7052418861 ps
CPU time 75 seconds
Started Aug 05 05:41:16 PM PDT 24
Finished Aug 05 05:42:31 PM PDT 24
Peak memory 238240 kb
Host smart-563ae44c-8c1d-4efa-aa62-f68b3c936c42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581768486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2581768486
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3080372425
Short name T108
Test name
Test status
Simulation time 167272934 ps
CPU time 36.43 seconds
Started Aug 05 05:03:41 PM PDT 24
Finished Aug 05 05:04:18 PM PDT 24
Peak memory 212980 kb
Host smart-a8b1ef3d-48b7-4429-a7ec-11b0bf58185e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080372425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3080372425
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3917009025
Short name T139
Test name
Test status
Simulation time 250153141 ps
CPU time 10.85 seconds
Started Aug 05 05:41:13 PM PDT 24
Finished Aug 05 05:41:24 PM PDT 24
Peak memory 213012 kb
Host smart-f372c403-5a49-44bc-be79-3c90e8626b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917009025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3917009025
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.145101165
Short name T121
Test name
Test status
Simulation time 280599821 ps
CPU time 9.61 seconds
Started Aug 05 05:41:00 PM PDT 24
Finished Aug 05 05:41:10 PM PDT 24
Peak memory 212972 kb
Host smart-17696376-f0ff-42be-b17b-0c0f8a921d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145101165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.145101165
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3347505190
Short name T42
Test name
Test status
Simulation time 991938634 ps
CPU time 10.86 seconds
Started Aug 05 05:41:17 PM PDT 24
Finished Aug 05 05:41:28 PM PDT 24
Peak memory 212828 kb
Host smart-d0139b51-d63c-4c4e-bb02-e948d27097e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347505190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3347505190
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2122038746
Short name T82
Test name
Test status
Simulation time 163893805 ps
CPU time 8.75 seconds
Started Aug 05 05:41:20 PM PDT 24
Finished Aug 05 05:41:29 PM PDT 24
Peak memory 212924 kb
Host smart-92083908-d95e-4840-b7bf-08f147cb6281
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122038746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2122038746
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.950892422
Short name T112
Test name
Test status
Simulation time 518210640 ps
CPU time 8.77 seconds
Started Aug 05 05:41:04 PM PDT 24
Finished Aug 05 05:41:13 PM PDT 24
Peak memory 212096 kb
Host smart-6d26f2f6-9ad0-444c-ba64-62a4abb011e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=950892422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.950892422
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3078652342
Short name T99
Test name
Test status
Simulation time 5076019261 ps
CPU time 962.62 seconds
Started Aug 05 05:40:49 PM PDT 24
Finished Aug 05 05:56:52 PM PDT 24
Peak memory 223016 kb
Host smart-7567ef87-44ad-4057-853e-a05f27c6bf39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078652342 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3078652342
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3640476302
Short name T71
Test name
Test status
Simulation time 126867917 ps
CPU time 4.92 seconds
Started Aug 05 05:03:29 PM PDT 24
Finished Aug 05 05:03:34 PM PDT 24
Peak memory 211308 kb
Host smart-021588b1-b2e0-4a69-96d5-12dbb3adeaf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640476302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3640476302
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2416096468
Short name T86
Test name
Test status
Simulation time 1914310622 ps
CPU time 7.46 seconds
Started Aug 05 05:03:21 PM PDT 24
Finished Aug 05 05:03:29 PM PDT 24
Peak memory 211320 kb
Host smart-885e8b0e-8df8-4efa-8e95-3cddba463abc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416096468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2416096468
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1765974657
Short name T97
Test name
Test status
Simulation time 129651516 ps
CPU time 5.23 seconds
Started Aug 05 05:03:17 PM PDT 24
Finished Aug 05 05:03:23 PM PDT 24
Peak memory 211220 kb
Host smart-ea732f96-3cb7-413b-a563-75749208a78f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765974657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1765974657
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3361383452
Short name T384
Test name
Test status
Simulation time 90438958 ps
CPU time 7.29 seconds
Started Aug 05 05:03:07 PM PDT 24
Finished Aug 05 05:03:14 PM PDT 24
Peak memory 219488 kb
Host smart-1edf8c15-bd14-4e35-b693-d69256e7e333
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361383452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3361383452
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.86592479
Short name T334
Test name
Test status
Simulation time 115769874 ps
CPU time 5.2 seconds
Started Aug 05 05:03:06 PM PDT 24
Finished Aug 05 05:03:11 PM PDT 24
Peak memory 219568 kb
Host smart-bd00b7c8-2ce9-47ec-8e40-6f5c2d2132b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86592479 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.86592479
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.604413310
Short name T58
Test name
Test status
Simulation time 131496454 ps
CPU time 5.1 seconds
Started Aug 05 05:03:38 PM PDT 24
Finished Aug 05 05:03:44 PM PDT 24
Peak memory 211264 kb
Host smart-6b79459e-e97d-4fa2-b75e-f730d5b77cf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604413310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.604413310
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4169368077
Short name T342
Test name
Test status
Simulation time 334465446 ps
CPU time 4.38 seconds
Started Aug 05 05:03:15 PM PDT 24
Finished Aug 05 05:03:20 PM PDT 24
Peak memory 211240 kb
Host smart-5e96413e-33a5-40b1-bac5-e1ecb3a534b4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169368077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4169368077
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2815270042
Short name T332
Test name
Test status
Simulation time 568054815 ps
CPU time 4.98 seconds
Started Aug 05 05:03:06 PM PDT 24
Finished Aug 05 05:03:11 PM PDT 24
Peak memory 211276 kb
Host smart-ddaf7908-b182-4bae-93ea-91c2eb0331f6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815270042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2815270042
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1035154142
Short name T371
Test name
Test status
Simulation time 97781923 ps
CPU time 6.2 seconds
Started Aug 05 05:03:05 PM PDT 24
Finished Aug 05 05:03:11 PM PDT 24
Peak memory 211308 kb
Host smart-639e1803-5699-4d44-bab8-04a841e67764
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035154142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1035154142
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2970750954
Short name T360
Test name
Test status
Simulation time 1295336001 ps
CPU time 9.65 seconds
Started Aug 05 05:03:13 PM PDT 24
Finished Aug 05 05:03:23 PM PDT 24
Peak memory 216544 kb
Host smart-b57fc5f4-cf9c-4625-8584-10d046679374
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970750954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2970750954
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2380016270
Short name T109
Test name
Test status
Simulation time 161701949 ps
CPU time 36.47 seconds
Started Aug 05 05:03:13 PM PDT 24
Finished Aug 05 05:03:49 PM PDT 24
Peak memory 219540 kb
Host smart-776866a8-144f-4aff-b65a-edde1a9aff60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380016270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2380016270
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.432143541
Short name T90
Test name
Test status
Simulation time 569939039 ps
CPU time 4.92 seconds
Started Aug 05 05:03:06 PM PDT 24
Finished Aug 05 05:03:11 PM PDT 24
Peak memory 218180 kb
Host smart-7ae11372-6637-4d98-9ea8-e1c2de497e85
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432143541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.432143541
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3574680112
Short name T351
Test name
Test status
Simulation time 333519430 ps
CPU time 4.57 seconds
Started Aug 05 05:03:05 PM PDT 24
Finished Aug 05 05:03:09 PM PDT 24
Peak memory 211352 kb
Host smart-413baf10-f525-49d0-9788-754e5c8fec2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574680112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3574680112
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3543678471
Short name T379
Test name
Test status
Simulation time 130204518 ps
CPU time 6.78 seconds
Started Aug 05 05:03:14 PM PDT 24
Finished Aug 05 05:03:21 PM PDT 24
Peak memory 211260 kb
Host smart-f16dcb60-ec50-441d-97e7-4f7e08c020c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543678471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3543678471
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2636275158
Short name T343
Test name
Test status
Simulation time 536367361 ps
CPU time 5.94 seconds
Started Aug 05 05:03:33 PM PDT 24
Finished Aug 05 05:03:44 PM PDT 24
Peak memory 216096 kb
Host smart-1267c216-a050-4a90-9acd-6997d63d3c10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636275158 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2636275158
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.186669570
Short name T388
Test name
Test status
Simulation time 132611868 ps
CPU time 4.9 seconds
Started Aug 05 05:03:08 PM PDT 24
Finished Aug 05 05:03:13 PM PDT 24
Peak memory 211120 kb
Host smart-cb566e2d-c049-4acf-a839-18224be4302b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186669570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.186669570
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2373965347
Short name T397
Test name
Test status
Simulation time 129773652 ps
CPU time 5.02 seconds
Started Aug 05 05:03:09 PM PDT 24
Finished Aug 05 05:03:14 PM PDT 24
Peak memory 211156 kb
Host smart-ac1d3e47-1be8-4120-a582-96c009c36599
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373965347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2373965347
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3856891150
Short name T394
Test name
Test status
Simulation time 136689817 ps
CPU time 7.04 seconds
Started Aug 05 05:03:15 PM PDT 24
Finished Aug 05 05:03:22 PM PDT 24
Peak memory 218748 kb
Host smart-9e019176-29cf-45b2-9113-20866d9195c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856891150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3856891150
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.997529306
Short name T382
Test name
Test status
Simulation time 348009956 ps
CPU time 6.24 seconds
Started Aug 05 05:03:12 PM PDT 24
Finished Aug 05 05:03:18 PM PDT 24
Peak memory 214904 kb
Host smart-1d1dd39e-d12c-459f-a7ed-56af6ed63f30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997529306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.997529306
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1318571756
Short name T107
Test name
Test status
Simulation time 257308782 ps
CPU time 69.77 seconds
Started Aug 05 05:03:25 PM PDT 24
Finished Aug 05 05:04:35 PM PDT 24
Peak memory 219532 kb
Host smart-4bbf506d-20e6-4b1d-9fc0-44c2841537dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318571756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1318571756
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2134387968
Short name T355
Test name
Test status
Simulation time 145041102 ps
CPU time 6.03 seconds
Started Aug 05 05:03:28 PM PDT 24
Finished Aug 05 05:03:34 PM PDT 24
Peak memory 216196 kb
Host smart-d93b9eb2-60b8-4c8c-95cd-f6a89ee9f269
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134387968 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2134387968
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4085004838
Short name T370
Test name
Test status
Simulation time 521482643 ps
CPU time 5.13 seconds
Started Aug 05 05:03:38 PM PDT 24
Finished Aug 05 05:03:44 PM PDT 24
Peak memory 211336 kb
Host smart-796f9035-4469-498d-b022-68e7793cac10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085004838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4085004838
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.57614315
Short name T366
Test name
Test status
Simulation time 592075884 ps
CPU time 5.08 seconds
Started Aug 05 05:03:45 PM PDT 24
Finished Aug 05 05:03:51 PM PDT 24
Peak memory 211400 kb
Host smart-a67c4484-ca7f-4e6f-a2b3-cfac4cbe5831
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57614315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ct
rl_same_csr_outstanding.57614315
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.550270203
Short name T369
Test name
Test status
Simulation time 85694866 ps
CPU time 6.9 seconds
Started Aug 05 05:03:35 PM PDT 24
Finished Aug 05 05:03:42 PM PDT 24
Peak memory 217832 kb
Host smart-cb1d63b7-e653-4ee3-a74f-e786ddcdc13b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550270203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.550270203
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1511982941
Short name T55
Test name
Test status
Simulation time 387097691 ps
CPU time 36.85 seconds
Started Aug 05 05:03:16 PM PDT 24
Finished Aug 05 05:03:53 PM PDT 24
Peak memory 219444 kb
Host smart-0e637ffe-b0e6-4b1c-a83d-e2240d848cd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511982941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1511982941
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1225082356
Short name T375
Test name
Test status
Simulation time 587167583 ps
CPU time 5.79 seconds
Started Aug 05 05:03:17 PM PDT 24
Finished Aug 05 05:03:23 PM PDT 24
Peak memory 219644 kb
Host smart-496471ef-73c9-4a9e-b9c2-c22cf7f56d49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225082356 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1225082356
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3871265476
Short name T385
Test name
Test status
Simulation time 348656175 ps
CPU time 4.25 seconds
Started Aug 05 05:03:46 PM PDT 24
Finished Aug 05 05:03:50 PM PDT 24
Peak memory 211340 kb
Host smart-7c881ba4-9f22-4f8c-ac34-19e6bfd5f1be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871265476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3871265476
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2629196645
Short name T391
Test name
Test status
Simulation time 171819506 ps
CPU time 4.31 seconds
Started Aug 05 05:03:40 PM PDT 24
Finished Aug 05 05:03:45 PM PDT 24
Peak memory 211392 kb
Host smart-05aba43b-e76a-4239-91d9-811925ef7d37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629196645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2629196645
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1026928508
Short name T352
Test name
Test status
Simulation time 88540412 ps
CPU time 7.84 seconds
Started Aug 05 05:03:38 PM PDT 24
Finished Aug 05 05:03:46 PM PDT 24
Peak memory 219560 kb
Host smart-d9b4b11f-f760-4de3-8580-8b71a6a78710
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026928508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1026928508
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4156731838
Short name T408
Test name
Test status
Simulation time 897298070 ps
CPU time 68.68 seconds
Started Aug 05 05:03:18 PM PDT 24
Finished Aug 05 05:04:27 PM PDT 24
Peak memory 219468 kb
Host smart-023ffdb0-a22b-470b-b5fe-d59bf82cbac7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156731838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.4156731838
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1327068166
Short name T413
Test name
Test status
Simulation time 375905126 ps
CPU time 4.52 seconds
Started Aug 05 05:03:48 PM PDT 24
Finished Aug 05 05:03:52 PM PDT 24
Peak memory 219472 kb
Host smart-89f184f1-4d53-4ae2-bc0d-19802b655bf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327068166 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1327068166
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3343086436
Short name T95
Test name
Test status
Simulation time 173520913 ps
CPU time 4.1 seconds
Started Aug 05 05:03:19 PM PDT 24
Finished Aug 05 05:03:23 PM PDT 24
Peak memory 211352 kb
Host smart-e78985b7-57fa-435c-8029-14aa817f338d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343086436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3343086436
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1715622304
Short name T409
Test name
Test status
Simulation time 529180148 ps
CPU time 6.62 seconds
Started Aug 05 05:03:17 PM PDT 24
Finished Aug 05 05:03:24 PM PDT 24
Peak memory 219440 kb
Host smart-cb8a1dea-73d3-4172-b926-4af6747a2a45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715622304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1715622304
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.771692830
Short name T338
Test name
Test status
Simulation time 2040547581 ps
CPU time 9.94 seconds
Started Aug 05 05:03:49 PM PDT 24
Finished Aug 05 05:03:59 PM PDT 24
Peak memory 219868 kb
Host smart-17591f7c-b9fe-4b46-a439-4948e45e577c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771692830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.771692830
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3378686316
Short name T389
Test name
Test status
Simulation time 564269468 ps
CPU time 36.13 seconds
Started Aug 05 05:03:34 PM PDT 24
Finished Aug 05 05:04:10 PM PDT 24
Peak memory 212796 kb
Host smart-99951330-dfe7-4f3e-b2a4-cf5366f34d21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378686316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3378686316
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3613495229
Short name T346
Test name
Test status
Simulation time 99581850 ps
CPU time 5.45 seconds
Started Aug 05 05:03:45 PM PDT 24
Finished Aug 05 05:03:50 PM PDT 24
Peak memory 219536 kb
Host smart-af37ab9e-c1ad-470a-a862-1c2f5d568006
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613495229 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3613495229
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1092639222
Short name T353
Test name
Test status
Simulation time 347826630 ps
CPU time 4.3 seconds
Started Aug 05 05:03:17 PM PDT 24
Finished Aug 05 05:03:22 PM PDT 24
Peak memory 219488 kb
Host smart-58aede62-df1b-497f-bf5d-d46f6d01dcb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092639222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1092639222
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.692825438
Short name T59
Test name
Test status
Simulation time 97612547 ps
CPU time 6.13 seconds
Started Aug 05 05:03:41 PM PDT 24
Finished Aug 05 05:03:47 PM PDT 24
Peak memory 211300 kb
Host smart-7f5453ea-e05c-42ef-871b-60827425f2d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692825438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.692825438
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.282096547
Short name T406
Test name
Test status
Simulation time 134036240 ps
CPU time 8.04 seconds
Started Aug 05 05:03:40 PM PDT 24
Finished Aug 05 05:03:48 PM PDT 24
Peak memory 216784 kb
Host smart-969f8534-8b7c-44ef-b219-f91cb145555c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282096547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.282096547
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.160352076
Short name T102
Test name
Test status
Simulation time 365754786 ps
CPU time 36.36 seconds
Started Aug 05 05:03:37 PM PDT 24
Finished Aug 05 05:04:13 PM PDT 24
Peak memory 212668 kb
Host smart-d377cda5-7f32-4b8f-a371-2616a1ec3603
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160352076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.160352076
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1025469876
Short name T411
Test name
Test status
Simulation time 102214726 ps
CPU time 4.76 seconds
Started Aug 05 05:03:31 PM PDT 24
Finished Aug 05 05:03:36 PM PDT 24
Peak memory 215152 kb
Host smart-3ccabf5b-6705-4dac-af64-df47b09dd598
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025469876 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1025469876
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.861158196
Short name T66
Test name
Test status
Simulation time 520603977 ps
CPU time 4.95 seconds
Started Aug 05 05:03:23 PM PDT 24
Finished Aug 05 05:03:28 PM PDT 24
Peak memory 211312 kb
Host smart-0f8b90a1-7cc0-43fe-bd47-2913914f14e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861158196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.861158196
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1644219771
Short name T390
Test name
Test status
Simulation time 133131627 ps
CPU time 5.47 seconds
Started Aug 05 05:03:19 PM PDT 24
Finished Aug 05 05:03:25 PM PDT 24
Peak memory 211296 kb
Host smart-d49207dc-5809-4119-ac32-48f1a09600b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644219771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1644219771
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3698847553
Short name T354
Test name
Test status
Simulation time 501049009 ps
CPU time 9.08 seconds
Started Aug 05 05:03:23 PM PDT 24
Finished Aug 05 05:03:32 PM PDT 24
Peak memory 219564 kb
Host smart-11d207e1-7f7a-4e90-b84a-3e475c928c3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698847553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3698847553
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.646625841
Short name T361
Test name
Test status
Simulation time 420495101 ps
CPU time 37.7 seconds
Started Aug 05 05:03:18 PM PDT 24
Finished Aug 05 05:03:56 PM PDT 24
Peak memory 219556 kb
Host smart-1e59eaed-ea90-4edd-b75c-b63d1428deb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646625841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.646625841
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1835427462
Short name T367
Test name
Test status
Simulation time 536098521 ps
CPU time 5.67 seconds
Started Aug 05 05:03:21 PM PDT 24
Finished Aug 05 05:03:27 PM PDT 24
Peak memory 214960 kb
Host smart-c853e88d-cb0c-49e3-bbf7-d6d832768301
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835427462 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1835427462
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2635330069
Short name T73
Test name
Test status
Simulation time 88433984 ps
CPU time 4.26 seconds
Started Aug 05 05:03:18 PM PDT 24
Finished Aug 05 05:03:23 PM PDT 24
Peak memory 217988 kb
Host smart-e7c23b56-f440-4310-a24d-69cbb48ad774
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635330069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2635330069
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3441234183
Short name T70
Test name
Test status
Simulation time 88749330 ps
CPU time 4.27 seconds
Started Aug 05 05:03:41 PM PDT 24
Finished Aug 05 05:03:45 PM PDT 24
Peak memory 219528 kb
Host smart-cdd4a25d-9638-462d-bfb2-c5ebb1142914
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441234183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3441234183
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2553778473
Short name T383
Test name
Test status
Simulation time 143431134 ps
CPU time 7.44 seconds
Started Aug 05 05:03:32 PM PDT 24
Finished Aug 05 05:03:39 PM PDT 24
Peak memory 219680 kb
Host smart-b8611640-f30c-4318-b86b-be2a6e637f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553778473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2553778473
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2020654330
Short name T347
Test name
Test status
Simulation time 581473990 ps
CPU time 6.81 seconds
Started Aug 05 05:03:32 PM PDT 24
Finished Aug 05 05:03:39 PM PDT 24
Peak memory 216756 kb
Host smart-5bdb3674-d298-444e-85e1-5482c00b389c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020654330 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2020654330
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2009686080
Short name T57
Test name
Test status
Simulation time 90109296 ps
CPU time 4.28 seconds
Started Aug 05 05:03:34 PM PDT 24
Finished Aug 05 05:03:39 PM PDT 24
Peak memory 211220 kb
Host smart-949a7dbe-f498-4f67-b4b7-1cae70c88ddf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009686080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2009686080
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.685119762
Short name T392
Test name
Test status
Simulation time 827861101 ps
CPU time 5.03 seconds
Started Aug 05 05:03:30 PM PDT 24
Finished Aug 05 05:03:35 PM PDT 24
Peak memory 211412 kb
Host smart-0f2a56cb-989b-4052-8a3b-9d74538d1845
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685119762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.685119762
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1671561976
Short name T414
Test name
Test status
Simulation time 784652694 ps
CPU time 10.25 seconds
Started Aug 05 05:03:32 PM PDT 24
Finished Aug 05 05:03:42 PM PDT 24
Peak memory 215480 kb
Host smart-481a7871-d3a9-4675-a337-261112613e36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671561976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1671561976
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.458190379
Short name T110
Test name
Test status
Simulation time 281664883 ps
CPU time 70.88 seconds
Started Aug 05 05:03:24 PM PDT 24
Finished Aug 05 05:04:35 PM PDT 24
Peak memory 213228 kb
Host smart-08b2c027-ffeb-4959-9759-f9d7b990aa7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458190379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.458190379
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1442886080
Short name T356
Test name
Test status
Simulation time 142208074 ps
CPU time 5.73 seconds
Started Aug 05 05:03:43 PM PDT 24
Finished Aug 05 05:03:49 PM PDT 24
Peak memory 215048 kb
Host smart-98675e5e-5b2a-4aab-9aa3-1b32090a8eea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442886080 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1442886080
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2399385630
Short name T405
Test name
Test status
Simulation time 153460133 ps
CPU time 4.96 seconds
Started Aug 05 05:03:30 PM PDT 24
Finished Aug 05 05:03:36 PM PDT 24
Peak memory 218264 kb
Host smart-33b94aa9-38c7-4119-bd03-978f8e21ca87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399385630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2399385630
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2672501668
Short name T68
Test name
Test status
Simulation time 127795806 ps
CPU time 5.13 seconds
Started Aug 05 05:03:27 PM PDT 24
Finished Aug 05 05:03:32 PM PDT 24
Peak memory 211400 kb
Host smart-0902c9a6-9e5f-4d55-92ea-ae4201212a33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672501668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2672501668
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3448081032
Short name T363
Test name
Test status
Simulation time 526864858 ps
CPU time 9.22 seconds
Started Aug 05 05:03:27 PM PDT 24
Finished Aug 05 05:03:36 PM PDT 24
Peak memory 219564 kb
Host smart-65a8dbff-8f00-4d60-80ee-b3f1d6e399de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448081032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3448081032
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2343121376
Short name T105
Test name
Test status
Simulation time 692469953 ps
CPU time 36.92 seconds
Started Aug 05 05:03:38 PM PDT 24
Finished Aug 05 05:04:15 PM PDT 24
Peak memory 211644 kb
Host smart-f6a11b52-b68a-4070-ae61-b3e9a9e640b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343121376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2343121376
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2622501431
Short name T339
Test name
Test status
Simulation time 99733079 ps
CPU time 5.33 seconds
Started Aug 05 05:03:31 PM PDT 24
Finished Aug 05 05:03:36 PM PDT 24
Peak memory 219656 kb
Host smart-b8a24813-fce8-43d0-a7eb-33ff813ae6d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622501431 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2622501431
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.229052645
Short name T67
Test name
Test status
Simulation time 310171366 ps
CPU time 5.09 seconds
Started Aug 05 05:03:45 PM PDT 24
Finished Aug 05 05:03:51 PM PDT 24
Peak memory 217840 kb
Host smart-61edd299-3b65-46c1-9bd2-fdd4b7f75626
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229052645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.229052645
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.445591162
Short name T368
Test name
Test status
Simulation time 126588626 ps
CPU time 5.17 seconds
Started Aug 05 05:03:30 PM PDT 24
Finished Aug 05 05:03:35 PM PDT 24
Peak memory 218832 kb
Host smart-899b3aa2-926c-4443-aca7-21beb092b3e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445591162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.445591162
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2141836927
Short name T340
Test name
Test status
Simulation time 140468937 ps
CPU time 7.16 seconds
Started Aug 05 05:03:43 PM PDT 24
Finished Aug 05 05:03:51 PM PDT 24
Peak memory 215200 kb
Host smart-44b4bce8-1139-4923-98c4-8a76a03758d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141836927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2141836927
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2666065351
Short name T402
Test name
Test status
Simulation time 532668889 ps
CPU time 71.36 seconds
Started Aug 05 05:03:38 PM PDT 24
Finished Aug 05 05:04:50 PM PDT 24
Peak memory 219548 kb
Host smart-0a3fb5e7-884d-4210-a0b5-bf33a90bba74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666065351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2666065351
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.137081468
Short name T372
Test name
Test status
Simulation time 554242092 ps
CPU time 5.94 seconds
Started Aug 05 05:03:31 PM PDT 24
Finished Aug 05 05:03:37 PM PDT 24
Peak memory 219576 kb
Host smart-37c4a934-87a4-4c18-b199-4be883f8e1d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137081468 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.137081468
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1887060472
Short name T362
Test name
Test status
Simulation time 153044648 ps
CPU time 5.14 seconds
Started Aug 05 05:03:28 PM PDT 24
Finished Aug 05 05:03:33 PM PDT 24
Peak memory 211304 kb
Host smart-37cc0b83-3411-4528-85ee-a24e8912cac5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887060472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1887060472
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3942174377
Short name T96
Test name
Test status
Simulation time 336300832 ps
CPU time 4.24 seconds
Started Aug 05 05:03:46 PM PDT 24
Finished Aug 05 05:03:51 PM PDT 24
Peak memory 219432 kb
Host smart-35b4e586-b240-4941-9ff7-cb8d3f7958eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942174377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3942174377
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2940184545
Short name T407
Test name
Test status
Simulation time 128061866 ps
CPU time 7.52 seconds
Started Aug 05 05:03:31 PM PDT 24
Finished Aug 05 05:03:39 PM PDT 24
Peak memory 219604 kb
Host smart-99a3b9f8-82bb-4d2d-a48e-26f7a984113d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940184545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2940184545
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.586925806
Short name T103
Test name
Test status
Simulation time 394538649 ps
CPU time 71.33 seconds
Started Aug 05 05:03:52 PM PDT 24
Finished Aug 05 05:05:03 PM PDT 24
Peak memory 213984 kb
Host smart-b40b9484-fee3-420d-b32d-4b62f5d9bf16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586925806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.586925806
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.689403561
Short name T83
Test name
Test status
Simulation time 1131285689 ps
CPU time 5.1 seconds
Started Aug 05 05:03:12 PM PDT 24
Finished Aug 05 05:03:18 PM PDT 24
Peak memory 218096 kb
Host smart-14ae31c7-053e-4e83-93f7-38e1a993f9ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689403561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.689403561
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2816014820
Short name T401
Test name
Test status
Simulation time 884537775 ps
CPU time 5.27 seconds
Started Aug 05 05:03:18 PM PDT 24
Finished Aug 05 05:03:24 PM PDT 24
Peak memory 211348 kb
Host smart-8b04daa7-4693-4434-942f-a7ae5a76c410
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816014820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2816014820
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2227084814
Short name T98
Test name
Test status
Simulation time 173112547 ps
CPU time 5.65 seconds
Started Aug 05 05:03:15 PM PDT 24
Finished Aug 05 05:03:21 PM PDT 24
Peak memory 211248 kb
Host smart-9945a5e2-9e27-4499-b2d4-c6923eb9b5cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227084814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2227084814
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3373666030
Short name T349
Test name
Test status
Simulation time 503324127 ps
CPU time 5.84 seconds
Started Aug 05 05:03:14 PM PDT 24
Finished Aug 05 05:03:20 PM PDT 24
Peak memory 219652 kb
Host smart-17f3732d-c14a-40f7-bcff-d09dbf9f83bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373666030 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3373666030
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2062755219
Short name T93
Test name
Test status
Simulation time 172258474 ps
CPU time 4.06 seconds
Started Aug 05 05:03:20 PM PDT 24
Finished Aug 05 05:03:25 PM PDT 24
Peak memory 219464 kb
Host smart-61cc4c99-6111-4b9b-98dc-eec9e1bcea8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062755219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2062755219
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3977976826
Short name T344
Test name
Test status
Simulation time 520910708 ps
CPU time 5.11 seconds
Started Aug 05 05:03:10 PM PDT 24
Finished Aug 05 05:03:15 PM PDT 24
Peak memory 211168 kb
Host smart-c122f77f-fbea-4f09-a07f-32616e0e924e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977976826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3977976826
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1000482613
Short name T358
Test name
Test status
Simulation time 89107576 ps
CPU time 4.25 seconds
Started Aug 05 05:03:18 PM PDT 24
Finished Aug 05 05:03:23 PM PDT 24
Peak memory 211280 kb
Host smart-9f13ce41-718a-4cf2-a052-e6ef2a75c5e5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000482613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1000482613
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.98907950
Short name T87
Test name
Test status
Simulation time 540907840 ps
CPU time 27.25 seconds
Started Aug 05 05:03:18 PM PDT 24
Finished Aug 05 05:03:46 PM PDT 24
Peak memory 211464 kb
Host smart-2b66fa8f-81d6-4a15-84c2-a192051b396e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98907950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pass
thru_mem_tl_intg_err.98907950
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3403612466
Short name T400
Test name
Test status
Simulation time 128515507 ps
CPU time 5.21 seconds
Started Aug 05 05:03:07 PM PDT 24
Finished Aug 05 05:03:13 PM PDT 24
Peak memory 211328 kb
Host smart-12519332-9a0e-416b-af82-d27d31f2440b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403612466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3403612466
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3167138592
Short name T373
Test name
Test status
Simulation time 362839189 ps
CPU time 6.95 seconds
Started Aug 05 05:03:14 PM PDT 24
Finished Aug 05 05:03:21 PM PDT 24
Peak memory 219692 kb
Host smart-1ded8181-2a73-40f1-af45-62a6fd1cde32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167138592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3167138592
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.991019457
Short name T104
Test name
Test status
Simulation time 225498111 ps
CPU time 37.8 seconds
Started Aug 05 05:03:14 PM PDT 24
Finished Aug 05 05:03:52 PM PDT 24
Peak memory 211768 kb
Host smart-bc4da3b7-fba6-4c89-bff8-03e0513105a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991019457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.991019457
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1580259097
Short name T403
Test name
Test status
Simulation time 518414800 ps
CPU time 4.91 seconds
Started Aug 05 05:03:22 PM PDT 24
Finished Aug 05 05:03:27 PM PDT 24
Peak memory 217864 kb
Host smart-8d64f201-6b1a-48cd-b0db-166dfd5cbf29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580259097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1580259097
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1407436881
Short name T335
Test name
Test status
Simulation time 133945634 ps
CPU time 5.31 seconds
Started Aug 05 05:03:09 PM PDT 24
Finished Aug 05 05:03:15 PM PDT 24
Peak memory 211344 kb
Host smart-a501f8c5-07f7-4492-9e56-fbcd658030d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407436881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1407436881
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3973587038
Short name T329
Test name
Test status
Simulation time 528535420 ps
CPU time 6.72 seconds
Started Aug 05 05:03:19 PM PDT 24
Finished Aug 05 05:03:26 PM PDT 24
Peak memory 211352 kb
Host smart-140bbef8-0e0b-4cbf-80b6-127f7a606908
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973587038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3973587038
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3032832181
Short name T359
Test name
Test status
Simulation time 139555902 ps
CPU time 5.58 seconds
Started Aug 05 05:03:15 PM PDT 24
Finished Aug 05 05:03:21 PM PDT 24
Peak memory 215392 kb
Host smart-886b66fd-75df-4e4e-a57b-931140263c2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032832181 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3032832181
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2948634264
Short name T331
Test name
Test status
Simulation time 138389771 ps
CPU time 4.2 seconds
Started Aug 05 05:03:37 PM PDT 24
Finished Aug 05 05:03:42 PM PDT 24
Peak memory 211312 kb
Host smart-cbc4a1c3-da45-428e-9b3d-62db6126afb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948634264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2948634264
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.685204675
Short name T374
Test name
Test status
Simulation time 175293117 ps
CPU time 4.13 seconds
Started Aug 05 05:03:45 PM PDT 24
Finished Aug 05 05:03:49 PM PDT 24
Peak memory 211136 kb
Host smart-ea8e7ecb-6607-4667-b5a4-d12e0d01fc28
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685204675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.685204675
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.409008638
Short name T364
Test name
Test status
Simulation time 85812305 ps
CPU time 4.22 seconds
Started Aug 05 05:03:29 PM PDT 24
Finished Aug 05 05:03:34 PM PDT 24
Peak memory 211136 kb
Host smart-88f1a291-b75b-428d-9bb8-53f9faa9992c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409008638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
409008638
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.158176876
Short name T387
Test name
Test status
Simulation time 143764239 ps
CPU time 7.07 seconds
Started Aug 05 05:03:17 PM PDT 24
Finished Aug 05 05:03:24 PM PDT 24
Peak memory 211368 kb
Host smart-092cd563-aace-4b01-83c6-c433d9c4b0e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158176876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.158176876
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.872004541
Short name T399
Test name
Test status
Simulation time 172067899 ps
CPU time 8.38 seconds
Started Aug 05 05:03:32 PM PDT 24
Finished Aug 05 05:03:40 PM PDT 24
Peak memory 216772 kb
Host smart-203b7e26-e40c-458d-a5a7-0e7b49e9010e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872004541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.872004541
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1269790499
Short name T101
Test name
Test status
Simulation time 398118934 ps
CPU time 37.85 seconds
Started Aug 05 05:03:21 PM PDT 24
Finished Aug 05 05:03:59 PM PDT 24
Peak memory 212664 kb
Host smart-a6d6cd94-569d-4809-ba56-42d8da73b554
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269790499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1269790499
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1435057296
Short name T91
Test name
Test status
Simulation time 175520774 ps
CPU time 4.3 seconds
Started Aug 05 05:03:19 PM PDT 24
Finished Aug 05 05:03:24 PM PDT 24
Peak memory 211348 kb
Host smart-8a35598f-ce23-4547-bcfe-9de723329b21
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435057296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1435057296
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1944332790
Short name T381
Test name
Test status
Simulation time 346224640 ps
CPU time 4.69 seconds
Started Aug 05 05:03:11 PM PDT 24
Finished Aug 05 05:03:15 PM PDT 24
Peak memory 211192 kb
Host smart-340d045e-11a8-492c-b542-6e557af512c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944332790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1944332790
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1061410657
Short name T365
Test name
Test status
Simulation time 500377756 ps
CPU time 10.78 seconds
Started Aug 05 05:03:27 PM PDT 24
Finished Aug 05 05:03:38 PM PDT 24
Peak memory 211348 kb
Host smart-4808bc24-48a6-4daf-bc0f-f039af13c508
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061410657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1061410657
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2118717724
Short name T337
Test name
Test status
Simulation time 557443565 ps
CPU time 6.62 seconds
Started Aug 05 05:03:25 PM PDT 24
Finished Aug 05 05:03:32 PM PDT 24
Peak memory 219536 kb
Host smart-b4bb0886-6d7b-45f5-a621-b7d2e0ce79b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118717724 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2118717724
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.758134777
Short name T415
Test name
Test status
Simulation time 692411269 ps
CPU time 4.19 seconds
Started Aug 05 05:03:40 PM PDT 24
Finished Aug 05 05:03:44 PM PDT 24
Peak memory 219656 kb
Host smart-e85c45e7-9dd9-4c12-b28d-59126c6e7c51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758134777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.758134777
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3923691842
Short name T345
Test name
Test status
Simulation time 1556610432 ps
CPU time 5 seconds
Started Aug 05 05:03:26 PM PDT 24
Finished Aug 05 05:03:31 PM PDT 24
Peak memory 211272 kb
Host smart-8ef25c4f-9746-48d0-9623-c9e82e6a590a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923691842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3923691842
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.149068907
Short name T333
Test name
Test status
Simulation time 482693127 ps
CPU time 4.94 seconds
Started Aug 05 05:03:25 PM PDT 24
Finished Aug 05 05:03:30 PM PDT 24
Peak memory 211336 kb
Host smart-da668636-5bf7-469a-87a9-b06271f98991
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149068907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
149068907
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3769855779
Short name T94
Test name
Test status
Simulation time 183142007 ps
CPU time 6.15 seconds
Started Aug 05 05:03:22 PM PDT 24
Finished Aug 05 05:03:29 PM PDT 24
Peak memory 211396 kb
Host smart-0390663f-c47a-4cf0-adcd-27f802a3bda0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769855779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3769855779
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2471038494
Short name T357
Test name
Test status
Simulation time 500081229 ps
CPU time 8.82 seconds
Started Aug 05 05:03:09 PM PDT 24
Finished Aug 05 05:03:18 PM PDT 24
Peak memory 219592 kb
Host smart-fd076adb-355c-44d6-a38a-4e6f97afa7a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471038494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2471038494
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.777019880
Short name T341
Test name
Test status
Simulation time 636456778 ps
CPU time 5.62 seconds
Started Aug 05 05:03:23 PM PDT 24
Finished Aug 05 05:03:29 PM PDT 24
Peak memory 219508 kb
Host smart-82ea845d-33f7-45ff-9611-7357f017a175
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777019880 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.777019880
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4153515439
Short name T85
Test name
Test status
Simulation time 543767287 ps
CPU time 4.93 seconds
Started Aug 05 05:03:17 PM PDT 24
Finished Aug 05 05:03:22 PM PDT 24
Peak memory 218184 kb
Host smart-ff4a0cb4-3542-4568-98be-7a0ef3950c99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153515439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.4153515439
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1042519385
Short name T378
Test name
Test status
Simulation time 169089963 ps
CPU time 4.12 seconds
Started Aug 05 05:03:14 PM PDT 24
Finished Aug 05 05:03:18 PM PDT 24
Peak memory 219520 kb
Host smart-f2e8dcaf-c18a-4664-b6fd-0930a0d5554a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042519385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1042519385
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.121683095
Short name T395
Test name
Test status
Simulation time 332992204 ps
CPU time 7.92 seconds
Started Aug 05 05:03:27 PM PDT 24
Finished Aug 05 05:03:35 PM PDT 24
Peak memory 219668 kb
Host smart-879a3e4f-366b-4b23-a0b7-b861c9bd1209
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121683095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.121683095
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.563714268
Short name T54
Test name
Test status
Simulation time 9132169581 ps
CPU time 39.35 seconds
Started Aug 05 05:03:15 PM PDT 24
Finished Aug 05 05:03:55 PM PDT 24
Peak memory 213904 kb
Host smart-bf716978-17f9-4db1-9aa7-c56e059d113e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563714268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.563714268
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1812150851
Short name T380
Test name
Test status
Simulation time 95434773 ps
CPU time 4.97 seconds
Started Aug 05 05:03:30 PM PDT 24
Finished Aug 05 05:03:35 PM PDT 24
Peak memory 219504 kb
Host smart-62d4cd6f-929c-4bf3-96e1-c27c10a3678d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812150851 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1812150851
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2077470635
Short name T348
Test name
Test status
Simulation time 336372973 ps
CPU time 4.28 seconds
Started Aug 05 05:03:41 PM PDT 24
Finished Aug 05 05:03:45 PM PDT 24
Peak memory 211340 kb
Host smart-27b17fd4-2f94-429a-8c8e-afc4aaefff10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077470635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2077470635
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.4292840245
Short name T84
Test name
Test status
Simulation time 373459498 ps
CPU time 18.12 seconds
Started Aug 05 05:03:16 PM PDT 24
Finished Aug 05 05:03:34 PM PDT 24
Peak memory 211396 kb
Host smart-52372009-572a-4eb9-9d33-2ea6324ce548
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292840245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.4292840245
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.815915532
Short name T72
Test name
Test status
Simulation time 469370268 ps
CPU time 6.67 seconds
Started Aug 05 05:03:17 PM PDT 24
Finished Aug 05 05:03:24 PM PDT 24
Peak memory 211316 kb
Host smart-bb409bb7-50b1-4902-bb2b-e3701829ad26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815915532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.815915532
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2632459545
Short name T393
Test name
Test status
Simulation time 297110927 ps
CPU time 10.09 seconds
Started Aug 05 05:03:16 PM PDT 24
Finished Aug 05 05:03:26 PM PDT 24
Peak memory 219564 kb
Host smart-c9cec738-8b08-40d4-9e12-650b79f2aed9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632459545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2632459545
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.419239808
Short name T410
Test name
Test status
Simulation time 173975705 ps
CPU time 36.81 seconds
Started Aug 05 05:03:25 PM PDT 24
Finished Aug 05 05:04:02 PM PDT 24
Peak memory 211988 kb
Host smart-916b5cff-7cd7-4dea-b290-66815e8c09f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419239808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.419239808
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3293727993
Short name T350
Test name
Test status
Simulation time 326691731 ps
CPU time 5.43 seconds
Started Aug 05 05:03:21 PM PDT 24
Finished Aug 05 05:03:27 PM PDT 24
Peak memory 219632 kb
Host smart-3977083f-66d6-4d93-8421-942a7a69d08e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293727993 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3293727993
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.132078310
Short name T92
Test name
Test status
Simulation time 133762930 ps
CPU time 4.39 seconds
Started Aug 05 05:03:21 PM PDT 24
Finished Aug 05 05:03:25 PM PDT 24
Peak memory 211356 kb
Host smart-e5500bae-2e8c-4bea-8eb7-b912ed6205ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132078310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.132078310
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3828268431
Short name T69
Test name
Test status
Simulation time 103225914 ps
CPU time 6.44 seconds
Started Aug 05 05:03:25 PM PDT 24
Finished Aug 05 05:03:31 PM PDT 24
Peak memory 219436 kb
Host smart-c232d903-d138-440f-933c-d23d9919c30d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828268431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3828268431
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3015257743
Short name T376
Test name
Test status
Simulation time 519019253 ps
CPU time 7.86 seconds
Started Aug 05 05:03:17 PM PDT 24
Finished Aug 05 05:03:25 PM PDT 24
Peak memory 216480 kb
Host smart-24088188-4b8c-438f-8fd6-2f7377f93786
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015257743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3015257743
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2135213469
Short name T330
Test name
Test status
Simulation time 89795467 ps
CPU time 4.56 seconds
Started Aug 05 05:03:19 PM PDT 24
Finished Aug 05 05:03:24 PM PDT 24
Peak memory 213440 kb
Host smart-17c04590-9691-42d4-a657-32e6ab22175e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135213469 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2135213469
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1790642781
Short name T89
Test name
Test status
Simulation time 521120379 ps
CPU time 5.05 seconds
Started Aug 05 05:03:19 PM PDT 24
Finished Aug 05 05:03:24 PM PDT 24
Peak memory 218336 kb
Host smart-7d1c19db-cb96-42a5-bd94-c0455c5966ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790642781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1790642781
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2389651809
Short name T396
Test name
Test status
Simulation time 130815163 ps
CPU time 6.85 seconds
Started Aug 05 05:03:45 PM PDT 24
Finished Aug 05 05:03:51 PM PDT 24
Peak memory 219436 kb
Host smart-cc69bd64-cb50-4cdf-84d0-9a5c9deb1dfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389651809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2389651809
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4292676125
Short name T404
Test name
Test status
Simulation time 126806414 ps
CPU time 7.98 seconds
Started Aug 05 05:03:16 PM PDT 24
Finished Aug 05 05:03:24 PM PDT 24
Peak memory 216544 kb
Host smart-4a7a6edc-56a9-46e3-9384-a077ca1f9d2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292676125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.4292676125
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1208733451
Short name T412
Test name
Test status
Simulation time 1319936058 ps
CPU time 72.47 seconds
Started Aug 05 05:03:20 PM PDT 24
Finished Aug 05 05:04:33 PM PDT 24
Peak memory 212024 kb
Host smart-533bd373-1ff2-417f-9b2c-6f501f667a56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208733451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1208733451
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.540225197
Short name T398
Test name
Test status
Simulation time 1070474319 ps
CPU time 5.1 seconds
Started Aug 05 05:03:19 PM PDT 24
Finished Aug 05 05:03:24 PM PDT 24
Peak memory 215760 kb
Host smart-8ea5d1fe-1158-42ee-8686-3c5d2f3f8ef4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540225197 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.540225197
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1263763965
Short name T88
Test name
Test status
Simulation time 415847829 ps
CPU time 4.11 seconds
Started Aug 05 05:03:27 PM PDT 24
Finished Aug 05 05:03:32 PM PDT 24
Peak memory 218676 kb
Host smart-cf700ae8-e5a5-4f95-bf3e-78ec0d333844
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263763965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1263763965
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3063125545
Short name T377
Test name
Test status
Simulation time 746748576 ps
CPU time 18.39 seconds
Started Aug 05 05:03:22 PM PDT 24
Finished Aug 05 05:03:41 PM PDT 24
Peak memory 211436 kb
Host smart-bf94ddcd-7ba6-46a9-8e26-3893f913819d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063125545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3063125545
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3495711247
Short name T386
Test name
Test status
Simulation time 554931420 ps
CPU time 7.01 seconds
Started Aug 05 05:03:18 PM PDT 24
Finished Aug 05 05:03:25 PM PDT 24
Peak memory 211460 kb
Host smart-7102e567-a264-406a-8a64-bb531638cb44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495711247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3495711247
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2612147657
Short name T336
Test name
Test status
Simulation time 133438240 ps
CPU time 8.88 seconds
Started Aug 05 05:03:17 PM PDT 24
Finished Aug 05 05:03:26 PM PDT 24
Peak memory 216488 kb
Host smart-2b1823a9-0eb6-41c1-b31f-5ab405ea9427
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612147657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2612147657
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1359545482
Short name T106
Test name
Test status
Simulation time 712489011 ps
CPU time 35.94 seconds
Started Aug 05 05:03:25 PM PDT 24
Finished Aug 05 05:04:01 PM PDT 24
Peak memory 211996 kb
Host smart-7e3d77e5-3e3d-41d4-8e41-d64181af2846
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359545482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1359545482
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2071920790
Short name T222
Test name
Test status
Simulation time 168160463 ps
CPU time 4.28 seconds
Started Aug 05 05:40:45 PM PDT 24
Finished Aug 05 05:40:50 PM PDT 24
Peak memory 211964 kb
Host smart-8321b796-1f45-46d5-9143-a6a0c18b2758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071920790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2071920790
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2717517261
Short name T154
Test name
Test status
Simulation time 3610149407 ps
CPU time 107.39 seconds
Started Aug 05 05:40:48 PM PDT 24
Finished Aug 05 05:42:35 PM PDT 24
Peak memory 238488 kb
Host smart-6ed55a4b-5147-48cd-bc75-15b6cb7ea17a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717517261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2717517261
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3299362958
Short name T136
Test name
Test status
Simulation time 1031758206 ps
CPU time 11.09 seconds
Started Aug 05 05:40:49 PM PDT 24
Finished Aug 05 05:41:00 PM PDT 24
Peak memory 212884 kb
Host smart-af18dfdf-787a-4a56-ad2a-0b0374249e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299362958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3299362958
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.438855363
Short name T187
Test name
Test status
Simulation time 1677532092 ps
CPU time 6.6 seconds
Started Aug 05 05:40:54 PM PDT 24
Finished Aug 05 05:41:00 PM PDT 24
Peak memory 212064 kb
Host smart-a998b992-4c96-4a3f-bb6e-cc41452ebfc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438855363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.438855363
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1671472946
Short name T27
Test name
Test status
Simulation time 971667943 ps
CPU time 102.84 seconds
Started Aug 05 05:40:49 PM PDT 24
Finished Aug 05 05:42:32 PM PDT 24
Peak memory 239060 kb
Host smart-9ac0ecf8-ca44-4174-b76d-9fa13c0c01e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671472946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1671472946
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1407106832
Short name T311
Test name
Test status
Simulation time 139981987 ps
CPU time 6.77 seconds
Started Aug 05 05:40:41 PM PDT 24
Finished Aug 05 05:40:48 PM PDT 24
Peak memory 212304 kb
Host smart-bf69dd7c-cd78-4702-acce-c2c00009cd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407106832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1407106832
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3711109380
Short name T75
Test name
Test status
Simulation time 186886410 ps
CPU time 11.59 seconds
Started Aug 05 05:40:51 PM PDT 24
Finished Aug 05 05:41:03 PM PDT 24
Peak memory 214896 kb
Host smart-778db22d-4a19-4fd8-b29d-c9acc1278a3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711109380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3711109380
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4225195226
Short name T216
Test name
Test status
Simulation time 127568156 ps
CPU time 5.13 seconds
Started Aug 05 05:40:56 PM PDT 24
Finished Aug 05 05:41:01 PM PDT 24
Peak memory 212048 kb
Host smart-55364c01-71f9-4547-ba57-a6b9452d4446
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225195226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4225195226
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4145706499
Short name T32
Test name
Test status
Simulation time 6653406718 ps
CPU time 76.99 seconds
Started Aug 05 05:41:02 PM PDT 24
Finished Aug 05 05:42:19 PM PDT 24
Peak memory 213844 kb
Host smart-ea167175-bf66-452e-921c-ee27df694541
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145706499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.4145706499
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3220732970
Short name T148
Test name
Test status
Simulation time 168625997 ps
CPU time 9.73 seconds
Started Aug 05 05:41:06 PM PDT 24
Finished Aug 05 05:41:16 PM PDT 24
Peak memory 212908 kb
Host smart-9d940b88-8807-4fb7-8e4b-797c20403adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220732970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3220732970
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1884158613
Short name T285
Test name
Test status
Simulation time 220558769 ps
CPU time 6.38 seconds
Started Aug 05 05:40:43 PM PDT 24
Finished Aug 05 05:40:49 PM PDT 24
Peak memory 212096 kb
Host smart-934a0806-8030-4f04-9c26-89e0848255d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1884158613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1884158613
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2140686120
Short name T25
Test name
Test status
Simulation time 195122380 ps
CPU time 99.58 seconds
Started Aug 05 05:40:50 PM PDT 24
Finished Aug 05 05:42:30 PM PDT 24
Peak memory 238820 kb
Host smart-417ee96c-0996-4697-b926-8df0a471108e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140686120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2140686120
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3689641624
Short name T279
Test name
Test status
Simulation time 740212886 ps
CPU time 6.68 seconds
Started Aug 05 05:40:59 PM PDT 24
Finished Aug 05 05:41:06 PM PDT 24
Peak memory 212244 kb
Host smart-4865daf5-0c95-4877-ad5e-7c348f8777a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689641624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3689641624
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3959411765
Short name T304
Test name
Test status
Simulation time 280441913 ps
CPU time 13.64 seconds
Started Aug 05 05:41:00 PM PDT 24
Finished Aug 05 05:41:14 PM PDT 24
Peak memory 215116 kb
Host smart-7a0af9d0-adda-40fe-a5e2-e7478b031fb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959411765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3959411765
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1184236671
Short name T48
Test name
Test status
Simulation time 91542683340 ps
CPU time 3600.19 seconds
Started Aug 05 05:40:39 PM PDT 24
Finished Aug 05 06:40:40 PM PDT 24
Peak memory 244984 kb
Host smart-80e32e98-cf40-4ab7-8d54-e85d92d79983
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184236671 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.1184236671
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2976500212
Short name T251
Test name
Test status
Simulation time 334320055 ps
CPU time 4.38 seconds
Started Aug 05 05:40:59 PM PDT 24
Finished Aug 05 05:41:03 PM PDT 24
Peak memory 212004 kb
Host smart-7fc337ea-c1c4-4754-9154-de8981d78b10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976500212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2976500212
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.512402755
Short name T184
Test name
Test status
Simulation time 23365182028 ps
CPU time 107.98 seconds
Started Aug 05 05:41:02 PM PDT 24
Finished Aug 05 05:42:50 PM PDT 24
Peak memory 238504 kb
Host smart-58d733a1-98c7-4525-a321-b9c64a7ee08e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512402755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.512402755
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.4274931981
Short name T160
Test name
Test status
Simulation time 253111115 ps
CPU time 11.33 seconds
Started Aug 05 05:41:08 PM PDT 24
Finished Aug 05 05:41:19 PM PDT 24
Peak memory 213128 kb
Host smart-bc4653ce-d634-4e78-856d-2cb8ed74ca98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274931981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.4274931981
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4101901486
Short name T258
Test name
Test status
Simulation time 97307754 ps
CPU time 5.85 seconds
Started Aug 05 05:41:15 PM PDT 24
Finished Aug 05 05:41:21 PM PDT 24
Peak memory 212168 kb
Host smart-effc8dce-b318-4cd2-909b-ca542f3513a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4101901486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.4101901486
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3794615483
Short name T17
Test name
Test status
Simulation time 298087288 ps
CPU time 14.36 seconds
Started Aug 05 05:40:56 PM PDT 24
Finished Aug 05 05:41:11 PM PDT 24
Peak memory 214852 kb
Host smart-9d62661c-db36-4717-a2a6-204b9016a516
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794615483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3794615483
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1203865732
Short name T155
Test name
Test status
Simulation time 127633655 ps
CPU time 5.06 seconds
Started Aug 05 05:41:16 PM PDT 24
Finished Aug 05 05:41:21 PM PDT 24
Peak memory 212032 kb
Host smart-1884a2ac-3bc0-4838-92a0-2aa01f69ee1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203865732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1203865732
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1072212287
Short name T41
Test name
Test status
Simulation time 24617478823 ps
CPU time 142.37 seconds
Started Aug 05 05:41:09 PM PDT 24
Finished Aug 05 05:43:31 PM PDT 24
Peak memory 235448 kb
Host smart-13cb5595-bb56-4744-998b-931ec4c043fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072212287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1072212287
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.104347128
Short name T310
Test name
Test status
Simulation time 669029217 ps
CPU time 9.59 seconds
Started Aug 05 05:41:08 PM PDT 24
Finished Aug 05 05:41:17 PM PDT 24
Peak memory 212892 kb
Host smart-3fd7937d-7433-4fb2-9f78-348201b10e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104347128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.104347128
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.422640311
Short name T64
Test name
Test status
Simulation time 363265499 ps
CPU time 5.87 seconds
Started Aug 05 05:40:52 PM PDT 24
Finished Aug 05 05:40:58 PM PDT 24
Peak memory 212184 kb
Host smart-b8aa5cce-8c2e-414e-8d11-799fd166a6ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=422640311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.422640311
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1675802922
Short name T151
Test name
Test status
Simulation time 1121849005 ps
CPU time 13.7 seconds
Started Aug 05 05:40:57 PM PDT 24
Finished Aug 05 05:41:10 PM PDT 24
Peak memory 215800 kb
Host smart-aa267651-3114-4cfa-b41e-c73b528a38d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675802922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1675802922
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1076804779
Short name T289
Test name
Test status
Simulation time 89630940 ps
CPU time 4.12 seconds
Started Aug 05 05:41:08 PM PDT 24
Finished Aug 05 05:41:13 PM PDT 24
Peak memory 212060 kb
Host smart-a39174f6-016b-443e-8221-5bb8121eedeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076804779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1076804779
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3825733149
Short name T321
Test name
Test status
Simulation time 9485945618 ps
CPU time 91.67 seconds
Started Aug 05 05:41:13 PM PDT 24
Finished Aug 05 05:42:45 PM PDT 24
Peak memory 238460 kb
Host smart-2881bf5e-8cce-4641-a47d-9bb17bfc207e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825733149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3825733149
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.447841583
Short name T213
Test name
Test status
Simulation time 173567362 ps
CPU time 9.45 seconds
Started Aug 05 05:41:03 PM PDT 24
Finished Aug 05 05:41:12 PM PDT 24
Peak memory 212916 kb
Host smart-88928d05-2bee-410a-96f1-1075ef899e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447841583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.447841583
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.945959413
Short name T183
Test name
Test status
Simulation time 141218945 ps
CPU time 6.37 seconds
Started Aug 05 05:41:07 PM PDT 24
Finished Aug 05 05:41:13 PM PDT 24
Peak memory 212184 kb
Host smart-c6c52ff4-acf2-4c73-97d6-25578f99a75d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=945959413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.945959413
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.757697334
Short name T297
Test name
Test status
Simulation time 225197627 ps
CPU time 16.09 seconds
Started Aug 05 05:41:01 PM PDT 24
Finished Aug 05 05:41:18 PM PDT 24
Peak memory 215424 kb
Host smart-da1df920-cffd-46b4-89e8-fdc382def2a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757697334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.757697334
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3103695188
Short name T201
Test name
Test status
Simulation time 663033953 ps
CPU time 5.11 seconds
Started Aug 05 05:41:07 PM PDT 24
Finished Aug 05 05:41:12 PM PDT 24
Peak memory 212060 kb
Host smart-c12c3758-7374-4dd4-8e62-5d8fabd02e38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103695188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3103695188
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3854595226
Short name T128
Test name
Test status
Simulation time 9110262013 ps
CPU time 138.05 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:43:30 PM PDT 24
Peak memory 213456 kb
Host smart-82c67bfb-db03-4cfb-b283-71c6edf482e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854595226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3854595226
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.735677279
Short name T238
Test name
Test status
Simulation time 759897375 ps
CPU time 9.56 seconds
Started Aug 05 05:40:54 PM PDT 24
Finished Aug 05 05:41:04 PM PDT 24
Peak memory 212996 kb
Host smart-2fc17033-7526-4908-ad5f-0ce04f98fe79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735677279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.735677279
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2496501007
Short name T326
Test name
Test status
Simulation time 142910839 ps
CPU time 6.38 seconds
Started Aug 05 05:41:01 PM PDT 24
Finished Aug 05 05:41:13 PM PDT 24
Peak memory 212116 kb
Host smart-67aca735-6bb4-496f-a00b-d55cd6540577
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2496501007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2496501007
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3300235742
Short name T138
Test name
Test status
Simulation time 350666039 ps
CPU time 4.47 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:41:15 PM PDT 24
Peak memory 212000 kb
Host smart-cc760b8a-3fdb-4733-81b1-ed546961fc54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300235742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3300235742
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3373213628
Short name T174
Test name
Test status
Simulation time 183058472 ps
CPU time 6.71 seconds
Started Aug 05 05:41:02 PM PDT 24
Finished Aug 05 05:41:09 PM PDT 24
Peak memory 212172 kb
Host smart-f0f4cc0d-d348-4335-8acb-5e9699ba0d60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3373213628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3373213628
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1680813233
Short name T204
Test name
Test status
Simulation time 5016806567 ps
CPU time 19.55 seconds
Started Aug 05 05:41:04 PM PDT 24
Finished Aug 05 05:41:24 PM PDT 24
Peak memory 214524 kb
Host smart-cbc3ea9c-59da-46f3-a384-af9c85ecb044
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680813233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1680813233
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.484678076
Short name T197
Test name
Test status
Simulation time 2576958891 ps
CPU time 7.76 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:41:19 PM PDT 24
Peak memory 212200 kb
Host smart-065b092f-cb6a-482e-9cf7-1fcbf192e210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484678076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.484678076
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.671384243
Short name T287
Test name
Test status
Simulation time 22113064128 ps
CPU time 140.05 seconds
Started Aug 05 05:41:12 PM PDT 24
Finished Aug 05 05:43:33 PM PDT 24
Peak memory 234392 kb
Host smart-ee708a29-03f1-4eef-9353-b09262124327
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671384243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.671384243
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2525371394
Short name T212
Test name
Test status
Simulation time 350903344 ps
CPU time 9.63 seconds
Started Aug 05 05:41:01 PM PDT 24
Finished Aug 05 05:41:11 PM PDT 24
Peak memory 212856 kb
Host smart-dfeb6131-8ee2-4832-8a6f-06096a317bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525371394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2525371394
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2047634355
Short name T141
Test name
Test status
Simulation time 1521524499 ps
CPU time 5.49 seconds
Started Aug 05 05:41:06 PM PDT 24
Finished Aug 05 05:41:12 PM PDT 24
Peak memory 212128 kb
Host smart-50876f29-f11a-4048-9f0d-bfddd457541c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2047634355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2047634355
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3233014275
Short name T190
Test name
Test status
Simulation time 2092553790 ps
CPU time 19.94 seconds
Started Aug 05 05:41:02 PM PDT 24
Finished Aug 05 05:41:22 PM PDT 24
Peak memory 213516 kb
Host smart-c28bf6f6-32e9-49bf-9710-6c92e4dd4faa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233014275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3233014275
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3512391036
Short name T145
Test name
Test status
Simulation time 502656410 ps
CPU time 5.33 seconds
Started Aug 05 05:41:13 PM PDT 24
Finished Aug 05 05:41:19 PM PDT 24
Peak memory 212056 kb
Host smart-022d93b6-a310-4f02-b676-e319ef794998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512391036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3512391036
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.4091416425
Short name T276
Test name
Test status
Simulation time 2723913047 ps
CPU time 140.67 seconds
Started Aug 05 05:41:09 PM PDT 24
Finished Aug 05 05:43:30 PM PDT 24
Peak memory 214432 kb
Host smart-5c3f7eca-78c1-4119-ad90-368d1bee8489
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091416425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.4091416425
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.237021275
Short name T243
Test name
Test status
Simulation time 357871740 ps
CPU time 9.6 seconds
Started Aug 05 05:41:02 PM PDT 24
Finished Aug 05 05:41:12 PM PDT 24
Peak memory 212916 kb
Host smart-7271b3fa-cc9e-4f62-a198-d708b5d6a86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237021275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.237021275
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3305605581
Short name T267
Test name
Test status
Simulation time 141354568 ps
CPU time 6.63 seconds
Started Aug 05 05:41:09 PM PDT 24
Finished Aug 05 05:41:16 PM PDT 24
Peak memory 212156 kb
Host smart-5a1f872a-8a38-4e08-a92e-dfbb8fc78ef0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3305605581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3305605581
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.4087486317
Short name T249
Test name
Test status
Simulation time 952466952 ps
CPU time 20.55 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:41:32 PM PDT 24
Peak memory 215864 kb
Host smart-4deee350-3dbf-4e00-a7f2-75f9e59eab2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087486317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.4087486317
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1094759007
Short name T303
Test name
Test status
Simulation time 79313442596 ps
CPU time 822.04 seconds
Started Aug 05 05:41:22 PM PDT 24
Finished Aug 05 05:55:04 PM PDT 24
Peak memory 236640 kb
Host smart-29aee40a-1904-4563-939e-2aebee3b6bff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094759007 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1094759007
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2541975555
Short name T29
Test name
Test status
Simulation time 362963690 ps
CPU time 4.36 seconds
Started Aug 05 05:41:14 PM PDT 24
Finished Aug 05 05:41:19 PM PDT 24
Peak memory 212040 kb
Host smart-0bd31955-5de2-45dc-aa9d-7f92ca32f25e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541975555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2541975555
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3254105340
Short name T33
Test name
Test status
Simulation time 3777826396 ps
CPU time 120.63 seconds
Started Aug 05 05:41:06 PM PDT 24
Finished Aug 05 05:43:07 PM PDT 24
Peak memory 225584 kb
Host smart-86494b79-e542-487e-94d1-b7eb982b9356
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254105340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3254105340
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4025491162
Short name T192
Test name
Test status
Simulation time 991950419 ps
CPU time 15.99 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:41:27 PM PDT 24
Peak memory 212856 kb
Host smart-2ba92db4-f253-4cae-8a33-db9877f1dca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025491162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.4025491162
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3514491807
Short name T237
Test name
Test status
Simulation time 171167901 ps
CPU time 6.43 seconds
Started Aug 05 05:41:08 PM PDT 24
Finished Aug 05 05:41:15 PM PDT 24
Peak memory 212164 kb
Host smart-49f0f231-4eaf-4966-8cf2-fb7d96efdce9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3514491807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3514491807
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3628934543
Short name T117
Test name
Test status
Simulation time 259389978 ps
CPU time 12.86 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:41:25 PM PDT 24
Peak memory 214348 kb
Host smart-0bedce1e-d1fb-448e-b4a2-b53eee215b14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628934543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3628934543
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1780621742
Short name T152
Test name
Test status
Simulation time 263824093 ps
CPU time 5.22 seconds
Started Aug 05 05:41:22 PM PDT 24
Finished Aug 05 05:41:28 PM PDT 24
Peak memory 212004 kb
Host smart-4a2e546c-2c89-4357-aed8-afdf3e97f44b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780621742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1780621742
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2742071089
Short name T35
Test name
Test status
Simulation time 10287920733 ps
CPU time 150.85 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:43:42 PM PDT 24
Peak memory 236764 kb
Host smart-4f22d9e5-d26b-44c1-8aa9-625e7a06302d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742071089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2742071089
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3154551889
Short name T195
Test name
Test status
Simulation time 986875517 ps
CPU time 16.42 seconds
Started Aug 05 05:41:19 PM PDT 24
Finished Aug 05 05:41:35 PM PDT 24
Peak memory 212824 kb
Host smart-ad7ece62-b854-495b-b2ee-5996f58abcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154551889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3154551889
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1944945113
Short name T4
Test name
Test status
Simulation time 186386206 ps
CPU time 6.92 seconds
Started Aug 05 05:41:10 PM PDT 24
Finished Aug 05 05:41:17 PM PDT 24
Peak memory 212156 kb
Host smart-e37c2675-8165-49d0-811d-a2a6dafedb1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1944945113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1944945113
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3304464574
Short name T264
Test name
Test status
Simulation time 820277118 ps
CPU time 13.5 seconds
Started Aug 05 05:41:23 PM PDT 24
Finished Aug 05 05:41:37 PM PDT 24
Peak memory 214336 kb
Host smart-47e46ba8-bba8-4e07-b207-27d361ee9208
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304464574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3304464574
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1919660879
Short name T119
Test name
Test status
Simulation time 1383673616 ps
CPU time 5.17 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:41:17 PM PDT 24
Peak memory 212036 kb
Host smart-63e8ddb7-a307-4fa4-9034-56bcf0b3fb3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919660879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1919660879
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.384337972
Short name T40
Test name
Test status
Simulation time 3501061198 ps
CPU time 88.8 seconds
Started Aug 05 05:41:08 PM PDT 24
Finished Aug 05 05:42:37 PM PDT 24
Peak memory 234624 kb
Host smart-4e0fdf46-020f-411b-a0c3-a65faedaaca3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384337972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.384337972
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3485693734
Short name T214
Test name
Test status
Simulation time 697282965 ps
CPU time 9.69 seconds
Started Aug 05 05:41:09 PM PDT 24
Finished Aug 05 05:41:19 PM PDT 24
Peak memory 212756 kb
Host smart-eb22af1f-786f-4399-b2f5-30e2fba55a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485693734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3485693734
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1939783446
Short name T265
Test name
Test status
Simulation time 528880551 ps
CPU time 6.5 seconds
Started Aug 05 05:41:02 PM PDT 24
Finished Aug 05 05:41:09 PM PDT 24
Peak memory 212080 kb
Host smart-4efca9fd-7f2a-4390-a0bc-a7e86db35b9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1939783446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1939783446
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2681346416
Short name T308
Test name
Test status
Simulation time 86372858 ps
CPU time 4.31 seconds
Started Aug 05 05:41:00 PM PDT 24
Finished Aug 05 05:41:05 PM PDT 24
Peak memory 212024 kb
Host smart-c447250d-d527-4dfd-8de0-0000303b0fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681346416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2681346416
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.843807925
Short name T210
Test name
Test status
Simulation time 32485888038 ps
CPU time 168.14 seconds
Started Aug 05 05:40:46 PM PDT 24
Finished Aug 05 05:43:35 PM PDT 24
Peak memory 238296 kb
Host smart-c1bc298d-f8c9-4862-b40b-96eb5b65fcad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843807925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.843807925
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3514721318
Short name T241
Test name
Test status
Simulation time 256402199 ps
CPU time 11.24 seconds
Started Aug 05 05:40:49 PM PDT 24
Finished Aug 05 05:41:05 PM PDT 24
Peak memory 212848 kb
Host smart-05ae5f90-9d80-48fd-baad-f0ddf55c6f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514721318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3514721318
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3569557379
Short name T161
Test name
Test status
Simulation time 95758546 ps
CPU time 5.82 seconds
Started Aug 05 05:40:47 PM PDT 24
Finished Aug 05 05:40:53 PM PDT 24
Peak memory 212068 kb
Host smart-bf39d084-acaf-44e7-a442-86480171807a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3569557379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3569557379
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.4144975958
Short name T12
Test name
Test status
Simulation time 638592349 ps
CPU time 52.63 seconds
Started Aug 05 05:40:55 PM PDT 24
Finished Aug 05 05:41:48 PM PDT 24
Peak memory 237640 kb
Host smart-775aa1bb-8852-4a00-988b-acc2b376d93d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144975958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.4144975958
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3965728358
Short name T165
Test name
Test status
Simulation time 533141578 ps
CPU time 6.21 seconds
Started Aug 05 05:40:55 PM PDT 24
Finished Aug 05 05:41:01 PM PDT 24
Peak memory 212288 kb
Host smart-fdbe464c-85ba-4b03-9da7-ba717acbab18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965728358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3965728358
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.477049582
Short name T319
Test name
Test status
Simulation time 471167541 ps
CPU time 9.35 seconds
Started Aug 05 05:40:57 PM PDT 24
Finished Aug 05 05:41:06 PM PDT 24
Peak memory 212116 kb
Host smart-11634f4d-3e37-4a5f-81d3-44faf79af025
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477049582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.477049582
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.62502494
Short name T44
Test name
Test status
Simulation time 248974239082 ps
CPU time 1212.26 seconds
Started Aug 05 05:40:51 PM PDT 24
Finished Aug 05 06:01:04 PM PDT 24
Peak memory 233120 kb
Host smart-ebcbc24c-249f-4ca8-9137-cab3a60114cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62502494 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.62502494
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3760343909
Short name T52
Test name
Test status
Simulation time 498449557 ps
CPU time 5.12 seconds
Started Aug 05 05:41:15 PM PDT 24
Finished Aug 05 05:41:21 PM PDT 24
Peak memory 212048 kb
Host smart-d0a0c24e-938b-4d1b-87b9-7cf29639bdb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760343909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3760343909
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3440992747
Short name T194
Test name
Test status
Simulation time 1573101160 ps
CPU time 112.15 seconds
Started Aug 05 05:41:10 PM PDT 24
Finished Aug 05 05:43:03 PM PDT 24
Peak memory 228980 kb
Host smart-132bf85b-cf90-4d72-a3d1-96030979cef8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440992747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3440992747
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1344208153
Short name T226
Test name
Test status
Simulation time 722964191 ps
CPU time 9.63 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:41:21 PM PDT 24
Peak memory 212896 kb
Host smart-ba68fea3-7b9e-4672-aa96-592ebce38cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344208153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1344208153
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3595144816
Short name T143
Test name
Test status
Simulation time 356980095 ps
CPU time 5.22 seconds
Started Aug 05 05:41:06 PM PDT 24
Finished Aug 05 05:41:11 PM PDT 24
Peak memory 212096 kb
Host smart-7cac92ec-4ece-49da-9269-12ba99450418
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3595144816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3595144816
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.200292807
Short name T316
Test name
Test status
Simulation time 155945995 ps
CPU time 8.2 seconds
Started Aug 05 05:41:14 PM PDT 24
Finished Aug 05 05:41:23 PM PDT 24
Peak memory 212028 kb
Host smart-28943073-ded9-46f3-a22e-f428b9d32be4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200292807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.200292807
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.282064124
Short name T158
Test name
Test status
Simulation time 128570792 ps
CPU time 5.27 seconds
Started Aug 05 05:41:06 PM PDT 24
Finished Aug 05 05:41:12 PM PDT 24
Peak memory 212056 kb
Host smart-35fbf2cb-d4c0-457c-8877-c1f5351a14c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282064124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.282064124
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1105360496
Short name T323
Test name
Test status
Simulation time 2643657993 ps
CPU time 133.58 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:43:25 PM PDT 24
Peak memory 238280 kb
Host smart-b46ef745-cacb-4915-9000-042a9018b738
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105360496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1105360496
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3567927256
Short name T11
Test name
Test status
Simulation time 268375742 ps
CPU time 6.22 seconds
Started Aug 05 05:41:13 PM PDT 24
Finished Aug 05 05:41:19 PM PDT 24
Peak memory 212156 kb
Host smart-8bb06d54-703f-4735-a40f-876ceda9d0a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3567927256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3567927256
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.776517968
Short name T295
Test name
Test status
Simulation time 391447727 ps
CPU time 8.59 seconds
Started Aug 05 05:41:06 PM PDT 24
Finished Aug 05 05:41:15 PM PDT 24
Peak memory 213260 kb
Host smart-8574c8b0-acd3-409b-b26c-cdf9345b7521
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776517968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.776517968
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3798667439
Short name T327
Test name
Test status
Simulation time 20880841590 ps
CPU time 418.87 seconds
Started Aug 05 05:41:07 PM PDT 24
Finished Aug 05 05:48:06 PM PDT 24
Peak memory 228488 kb
Host smart-ff4d24a9-8a2f-4ad3-9bbb-e4fcab159341
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798667439 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.3798667439
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2734865117
Short name T180
Test name
Test status
Simulation time 886527572 ps
CPU time 5.29 seconds
Started Aug 05 05:41:04 PM PDT 24
Finished Aug 05 05:41:09 PM PDT 24
Peak memory 211964 kb
Host smart-d9cdf3df-7687-412a-809e-ffd6eef12007
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734865117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2734865117
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.256744376
Short name T203
Test name
Test status
Simulation time 10189189365 ps
CPU time 118.14 seconds
Started Aug 05 05:41:22 PM PDT 24
Finished Aug 05 05:43:21 PM PDT 24
Peak memory 213484 kb
Host smart-5e3b3747-ef46-4fe8-9e21-2c0cac00d9d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256744376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.256744376
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3074722378
Short name T307
Test name
Test status
Simulation time 175031115 ps
CPU time 9.54 seconds
Started Aug 05 05:41:06 PM PDT 24
Finished Aug 05 05:41:16 PM PDT 24
Peak memory 213048 kb
Host smart-93247086-04a6-4045-ac23-796821fa64bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074722378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3074722378
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2581356660
Short name T177
Test name
Test status
Simulation time 245997447 ps
CPU time 15.79 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:41:26 PM PDT 24
Peak memory 214396 kb
Host smart-a0ec4333-2f2c-4668-b982-48185659a99a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581356660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2581356660
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2998038211
Short name T115
Test name
Test status
Simulation time 126996827 ps
CPU time 5.36 seconds
Started Aug 05 05:41:08 PM PDT 24
Finished Aug 05 05:41:13 PM PDT 24
Peak memory 212048 kb
Host smart-6cf6a150-99e8-43c1-81c7-8059f4d30153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998038211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2998038211
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.339642195
Short name T282
Test name
Test status
Simulation time 3560921061 ps
CPU time 126.1 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:43:17 PM PDT 24
Peak memory 238384 kb
Host smart-4e879b6e-be45-4535-bfd4-07cc9f4036d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339642195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.339642195
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.995354629
Short name T306
Test name
Test status
Simulation time 993973108 ps
CPU time 11.2 seconds
Started Aug 05 05:41:22 PM PDT 24
Finished Aug 05 05:41:33 PM PDT 24
Peak memory 212972 kb
Host smart-50655395-df7f-450e-a63e-95b404d1ed5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995354629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.995354629
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2799901384
Short name T50
Test name
Test status
Simulation time 383579059 ps
CPU time 5.91 seconds
Started Aug 05 05:41:26 PM PDT 24
Finished Aug 05 05:41:33 PM PDT 24
Peak memory 212096 kb
Host smart-d7085dad-0183-4ab0-b299-1cc4a47dc6a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2799901384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2799901384
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.261756145
Short name T74
Test name
Test status
Simulation time 1125656231 ps
CPU time 14.81 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:41:26 PM PDT 24
Peak memory 215280 kb
Host smart-c779f455-f0af-4f32-80b4-a0c25e7e4e9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261756145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.261756145
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3802966140
Short name T228
Test name
Test status
Simulation time 1397193872 ps
CPU time 4.3 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:41:15 PM PDT 24
Peak memory 211980 kb
Host smart-7f2266cc-c579-4126-b8c5-232d998a7572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802966140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3802966140
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.4188864626
Short name T146
Test name
Test status
Simulation time 1916763153 ps
CPU time 110.15 seconds
Started Aug 05 05:41:27 PM PDT 24
Finished Aug 05 05:43:17 PM PDT 24
Peak memory 237384 kb
Host smart-bbace022-babb-461e-8d44-10b8b31608b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188864626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.4188864626
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.966207007
Short name T257
Test name
Test status
Simulation time 335819584 ps
CPU time 9.52 seconds
Started Aug 05 05:41:08 PM PDT 24
Finished Aug 05 05:41:18 PM PDT 24
Peak memory 212912 kb
Host smart-f99302e0-b63d-4b0a-9191-2fb009ee3e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966207007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.966207007
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2993647209
Short name T314
Test name
Test status
Simulation time 103163507 ps
CPU time 5.61 seconds
Started Aug 05 05:41:19 PM PDT 24
Finished Aug 05 05:41:24 PM PDT 24
Peak memory 212072 kb
Host smart-12d0c437-d0ad-4165-bff1-54bbee21d23a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2993647209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2993647209
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1313085557
Short name T186
Test name
Test status
Simulation time 652230222 ps
CPU time 14.36 seconds
Started Aug 05 05:41:09 PM PDT 24
Finished Aug 05 05:41:23 PM PDT 24
Peak memory 212108 kb
Host smart-b31295d5-4b44-4737-937d-c20f4ac00330
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313085557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1313085557
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3005152426
Short name T123
Test name
Test status
Simulation time 557825913 ps
CPU time 4.26 seconds
Started Aug 05 05:41:09 PM PDT 24
Finished Aug 05 05:41:13 PM PDT 24
Peak memory 212036 kb
Host smart-9d6e3c53-049f-4dd9-9d4a-f2baead03b6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005152426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3005152426
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.4237463372
Short name T229
Test name
Test status
Simulation time 14115014083 ps
CPU time 168.49 seconds
Started Aug 05 05:41:07 PM PDT 24
Finished Aug 05 05:43:56 PM PDT 24
Peak memory 213460 kb
Host smart-b8444909-2268-4bfa-bd48-11f70656bddb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237463372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.4237463372
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.4290201054
Short name T2
Test name
Test status
Simulation time 261950835 ps
CPU time 10.82 seconds
Started Aug 05 05:41:08 PM PDT 24
Finished Aug 05 05:41:19 PM PDT 24
Peak memory 212984 kb
Host smart-83a94c23-61a9-4545-a4e1-de034d79f183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290201054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.4290201054
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3501315973
Short name T173
Test name
Test status
Simulation time 579094415 ps
CPU time 6.26 seconds
Started Aug 05 05:41:07 PM PDT 24
Finished Aug 05 05:41:13 PM PDT 24
Peak memory 212184 kb
Host smart-f2542c0b-1d50-47a8-968b-97e9d057c0cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3501315973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3501315973
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.175796934
Short name T255
Test name
Test status
Simulation time 529268429 ps
CPU time 9.6 seconds
Started Aug 05 05:41:15 PM PDT 24
Finished Aug 05 05:41:24 PM PDT 24
Peak memory 212188 kb
Host smart-2a54c18b-0f73-4ca5-a8a5-62b3fcd5b8c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175796934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.175796934
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.4288210703
Short name T28
Test name
Test status
Simulation time 347451430 ps
CPU time 4.22 seconds
Started Aug 05 05:41:03 PM PDT 24
Finished Aug 05 05:41:07 PM PDT 24
Peak memory 212024 kb
Host smart-fb716a1a-38fe-4ab7-b662-72da2f6260dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288210703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.4288210703
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2562732092
Short name T130
Test name
Test status
Simulation time 15541893504 ps
CPU time 71.77 seconds
Started Aug 05 05:41:05 PM PDT 24
Finished Aug 05 05:42:16 PM PDT 24
Peak memory 213484 kb
Host smart-bd4b54d1-e964-4c8f-9c45-f149645a11e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562732092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2562732092
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2358338722
Short name T302
Test name
Test status
Simulation time 260523019 ps
CPU time 11.01 seconds
Started Aug 05 05:41:22 PM PDT 24
Finished Aug 05 05:41:33 PM PDT 24
Peak memory 213024 kb
Host smart-e7f1b385-ffc1-4cb9-8da4-cc387249466f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358338722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2358338722
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.496172626
Short name T246
Test name
Test status
Simulation time 186332981 ps
CPU time 5.4 seconds
Started Aug 05 05:41:05 PM PDT 24
Finished Aug 05 05:41:10 PM PDT 24
Peak memory 212052 kb
Host smart-097d82ac-c913-46f5-81c9-f618446ea970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=496172626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.496172626
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.773792180
Short name T294
Test name
Test status
Simulation time 545059793 ps
CPU time 22.95 seconds
Started Aug 05 05:41:18 PM PDT 24
Finished Aug 05 05:41:41 PM PDT 24
Peak memory 216132 kb
Host smart-11b80af7-0576-4aaa-a93c-d98530d36348
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773792180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.773792180
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1088195526
Short name T318
Test name
Test status
Simulation time 16706797647 ps
CPU time 5473.97 seconds
Started Aug 05 05:41:12 PM PDT 24
Finished Aug 05 07:12:26 PM PDT 24
Peak memory 236612 kb
Host smart-108f907b-05a3-47c7-a0da-4ac2644bbc6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088195526 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1088195526
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.107678012
Short name T132
Test name
Test status
Simulation time 131803101 ps
CPU time 5.2 seconds
Started Aug 05 05:41:06 PM PDT 24
Finished Aug 05 05:41:11 PM PDT 24
Peak memory 212052 kb
Host smart-a6c39e18-9348-4913-a7af-f157595e40c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107678012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.107678012
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.540321096
Short name T22
Test name
Test status
Simulation time 18542532355 ps
CPU time 70.19 seconds
Started Aug 05 05:41:06 PM PDT 24
Finished Aug 05 05:42:17 PM PDT 24
Peak memory 213416 kb
Host smart-2ad49b02-699f-41d3-9035-c7695085308d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540321096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.540321096
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3356119881
Short name T61
Test name
Test status
Simulation time 261769826 ps
CPU time 11.15 seconds
Started Aug 05 05:41:12 PM PDT 24
Finished Aug 05 05:41:23 PM PDT 24
Peak memory 212848 kb
Host smart-5c145e07-c760-492c-8733-2178ac9c56d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356119881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3356119881
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2544628889
Short name T281
Test name
Test status
Simulation time 584492493 ps
CPU time 6.31 seconds
Started Aug 05 05:41:09 PM PDT 24
Finished Aug 05 05:41:16 PM PDT 24
Peak memory 212132 kb
Host smart-9e2dd1f4-b869-4389-b930-cef2430272b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2544628889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2544628889
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1794549551
Short name T312
Test name
Test status
Simulation time 228811554 ps
CPU time 12.78 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:41:24 PM PDT 24
Peak memory 214120 kb
Host smart-a41be70d-6093-4fe4-9f56-77de2d8b8376
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794549551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1794549551
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.4012312800
Short name T118
Test name
Test status
Simulation time 129782829 ps
CPU time 5.09 seconds
Started Aug 05 05:41:20 PM PDT 24
Finished Aug 05 05:41:25 PM PDT 24
Peak memory 212036 kb
Host smart-3561a0a3-c816-4360-a690-f29977c402ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012312800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.4012312800
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3697959187
Short name T220
Test name
Test status
Simulation time 3965949261 ps
CPU time 149.13 seconds
Started Aug 05 05:41:03 PM PDT 24
Finished Aug 05 05:43:33 PM PDT 24
Peak memory 238940 kb
Host smart-6270e5e6-9598-4961-9268-c9012806e462
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697959187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3697959187
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.784327821
Short name T114
Test name
Test status
Simulation time 343137067 ps
CPU time 9.7 seconds
Started Aug 05 05:41:09 PM PDT 24
Finished Aug 05 05:41:19 PM PDT 24
Peak memory 212936 kb
Host smart-2dc41202-17ae-4398-a0f2-1807f126e7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784327821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.784327821
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3842662944
Short name T278
Test name
Test status
Simulation time 528808626 ps
CPU time 6.1 seconds
Started Aug 05 05:41:13 PM PDT 24
Finished Aug 05 05:41:19 PM PDT 24
Peak memory 212140 kb
Host smart-e8a78c9d-5e05-4642-b603-b73159de4d4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3842662944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3842662944
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.677225911
Short name T270
Test name
Test status
Simulation time 336074991 ps
CPU time 8.74 seconds
Started Aug 05 05:41:05 PM PDT 24
Finished Aug 05 05:41:14 PM PDT 24
Peak memory 212084 kb
Host smart-ba27f467-e4e7-4500-9857-28f3d13502a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677225911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.677225911
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1562662172
Short name T47
Test name
Test status
Simulation time 10127562926 ps
CPU time 205.64 seconds
Started Aug 05 05:41:13 PM PDT 24
Finished Aug 05 05:44:39 PM PDT 24
Peak memory 224772 kb
Host smart-1f7f861b-10d7-4036-90d5-3a65b5606894
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562662172 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1562662172
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2167346535
Short name T6
Test name
Test status
Simulation time 2734008124 ps
CPU time 7.42 seconds
Started Aug 05 05:41:18 PM PDT 24
Finished Aug 05 05:41:26 PM PDT 24
Peak memory 212160 kb
Host smart-823cec54-b088-4c4c-8d99-57acb5173b31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167346535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2167346535
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.542640219
Short name T34
Test name
Test status
Simulation time 4356762340 ps
CPU time 132.28 seconds
Started Aug 05 05:41:13 PM PDT 24
Finished Aug 05 05:43:26 PM PDT 24
Peak memory 238520 kb
Host smart-64af52f0-aae4-4054-9d68-ac0c290336be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542640219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.542640219
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2055017084
Short name T275
Test name
Test status
Simulation time 499765398 ps
CPU time 11.13 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:41:22 PM PDT 24
Peak memory 212952 kb
Host smart-9b077a51-63b6-4e7d-9b21-cd90d0c1a69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055017084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2055017084
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3488879109
Short name T309
Test name
Test status
Simulation time 310839971 ps
CPU time 5.82 seconds
Started Aug 05 05:41:20 PM PDT 24
Finished Aug 05 05:41:26 PM PDT 24
Peak memory 212072 kb
Host smart-9566e97c-35c9-4895-a0c5-4c1c55a8554b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3488879109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3488879109
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3273476568
Short name T227
Test name
Test status
Simulation time 417009376 ps
CPU time 12.66 seconds
Started Aug 05 05:41:18 PM PDT 24
Finished Aug 05 05:41:30 PM PDT 24
Peak memory 215456 kb
Host smart-0a41de88-b673-4a53-910f-0a94a499d094
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273476568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3273476568
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3529359695
Short name T215
Test name
Test status
Simulation time 420646560080 ps
CPU time 1375.73 seconds
Started Aug 05 05:41:13 PM PDT 24
Finished Aug 05 06:04:09 PM PDT 24
Peak memory 234104 kb
Host smart-c93ae11b-16bd-4f32-a052-26bf9144be7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529359695 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3529359695
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1997903069
Short name T280
Test name
Test status
Simulation time 500667005 ps
CPU time 5.08 seconds
Started Aug 05 05:41:08 PM PDT 24
Finished Aug 05 05:41:13 PM PDT 24
Peak memory 211992 kb
Host smart-8aebd8d1-3962-4974-8a00-9de6735e4e0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997903069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1997903069
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1370437835
Short name T149
Test name
Test status
Simulation time 15554618916 ps
CPU time 97.01 seconds
Started Aug 05 05:40:54 PM PDT 24
Finished Aug 05 05:42:31 PM PDT 24
Peak memory 237448 kb
Host smart-00c481bb-88b8-43a7-94b1-5c27af29ec19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370437835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1370437835
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3568241609
Short name T225
Test name
Test status
Simulation time 170183895 ps
CPU time 9.53 seconds
Started Aug 05 05:41:05 PM PDT 24
Finished Aug 05 05:41:14 PM PDT 24
Peak memory 213124 kb
Host smart-e417a3af-3a7c-4435-ae93-0aa70dbf45f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568241609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3568241609
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2668029479
Short name T252
Test name
Test status
Simulation time 269254743 ps
CPU time 6.53 seconds
Started Aug 05 05:40:56 PM PDT 24
Finished Aug 05 05:41:02 PM PDT 24
Peak memory 212180 kb
Host smart-0fdee4bc-e443-4f5c-8716-ac6470ba4b76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2668029479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2668029479
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1653154198
Short name T137
Test name
Test status
Simulation time 94830464 ps
CPU time 5.5 seconds
Started Aug 05 05:40:50 PM PDT 24
Finished Aug 05 05:40:56 PM PDT 24
Peak memory 212156 kb
Host smart-9760338f-69dd-46d2-a613-2d0b10fd3c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653154198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1653154198
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1490434541
Short name T247
Test name
Test status
Simulation time 959979726 ps
CPU time 8.83 seconds
Started Aug 05 05:40:57 PM PDT 24
Finished Aug 05 05:41:06 PM PDT 24
Peak memory 212080 kb
Host smart-863d6e05-5e4a-4825-9353-19a0eaa88737
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490434541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1490434541
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3953682993
Short name T290
Test name
Test status
Simulation time 127139517 ps
CPU time 5.13 seconds
Started Aug 05 05:41:08 PM PDT 24
Finished Aug 05 05:41:14 PM PDT 24
Peak memory 211976 kb
Host smart-9e7ba2a7-467a-42e9-8ab6-bcf21a0e1ecd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953682993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3953682993
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1937522666
Short name T233
Test name
Test status
Simulation time 3637493722 ps
CPU time 171.09 seconds
Started Aug 05 05:41:24 PM PDT 24
Finished Aug 05 05:44:15 PM PDT 24
Peak memory 237640 kb
Host smart-13b5e28b-58c1-4abf-8063-646f51ca5b5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937522666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1937522666
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2992944185
Short name T63
Test name
Test status
Simulation time 262220213 ps
CPU time 11.2 seconds
Started Aug 05 05:41:20 PM PDT 24
Finished Aug 05 05:41:31 PM PDT 24
Peak memory 212904 kb
Host smart-82da7acd-b8ed-4d01-b232-bc5d5fd84c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992944185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2992944185
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1513885294
Short name T196
Test name
Test status
Simulation time 1657726452 ps
CPU time 6.24 seconds
Started Aug 05 05:41:24 PM PDT 24
Finished Aug 05 05:41:30 PM PDT 24
Peak memory 212156 kb
Host smart-70e657fd-a5f7-4802-a067-40358ec29047
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1513885294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1513885294
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2570365875
Short name T79
Test name
Test status
Simulation time 429727178 ps
CPU time 18.67 seconds
Started Aug 05 05:41:17 PM PDT 24
Finished Aug 05 05:41:36 PM PDT 24
Peak memory 215888 kb
Host smart-838591cc-7c96-403c-8c78-e1db4a26c9d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570365875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2570365875
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.653964935
Short name T296
Test name
Test status
Simulation time 599240553 ps
CPU time 5.05 seconds
Started Aug 05 05:41:17 PM PDT 24
Finished Aug 05 05:41:23 PM PDT 24
Peak memory 211960 kb
Host smart-1613ffd8-5d33-4de1-ae67-9884ac851476
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653964935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.653964935
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2544097400
Short name T181
Test name
Test status
Simulation time 7567246227 ps
CPU time 110.96 seconds
Started Aug 05 05:41:22 PM PDT 24
Finished Aug 05 05:43:14 PM PDT 24
Peak memory 229040 kb
Host smart-21672ea2-926d-4b7c-9b0f-d93fb0b8f8d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544097400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2544097400
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1122911297
Short name T134
Test name
Test status
Simulation time 997906607 ps
CPU time 11.28 seconds
Started Aug 05 05:41:09 PM PDT 24
Finished Aug 05 05:41:21 PM PDT 24
Peak memory 212912 kb
Host smart-d337f12a-5e9f-446d-9f1d-7d28f984b329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122911297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1122911297
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1780514988
Short name T198
Test name
Test status
Simulation time 143211861 ps
CPU time 6.67 seconds
Started Aug 05 05:41:09 PM PDT 24
Finished Aug 05 05:41:16 PM PDT 24
Peak memory 212072 kb
Host smart-7ab3fc82-2d4e-4637-bea8-bc999db07101
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1780514988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1780514988
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1410990894
Short name T80
Test name
Test status
Simulation time 8861272428 ps
CPU time 26.24 seconds
Started Aug 05 05:41:27 PM PDT 24
Finished Aug 05 05:41:53 PM PDT 24
Peak memory 218352 kb
Host smart-cd0b485a-3618-4a0c-b0f5-b55bc8887974
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410990894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1410990894
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2501482589
Short name T14
Test name
Test status
Simulation time 169512802345 ps
CPU time 1560.13 seconds
Started Aug 05 05:41:24 PM PDT 24
Finished Aug 05 06:07:24 PM PDT 24
Peak memory 237752 kb
Host smart-1563ce4d-77fe-4cde-80b1-40ec5729ab3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501482589 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2501482589
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.107172006
Short name T60
Test name
Test status
Simulation time 89415149 ps
CPU time 4.39 seconds
Started Aug 05 05:41:29 PM PDT 24
Finished Aug 05 05:41:33 PM PDT 24
Peak memory 212060 kb
Host smart-317887f8-785e-4453-9512-b1b2953235eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107172006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.107172006
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2637498504
Short name T147
Test name
Test status
Simulation time 4406796495 ps
CPU time 145.82 seconds
Started Aug 05 05:41:24 PM PDT 24
Finished Aug 05 05:43:50 PM PDT 24
Peak memory 218824 kb
Host smart-57d9b8df-8a16-4419-a560-17eae10d7b7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637498504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2637498504
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1840654398
Short name T168
Test name
Test status
Simulation time 1668622957 ps
CPU time 11.38 seconds
Started Aug 05 05:41:22 PM PDT 24
Finished Aug 05 05:41:33 PM PDT 24
Peak memory 212924 kb
Host smart-494dc346-b61e-43a0-b1b7-48c5fc055538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840654398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1840654398
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3081274783
Short name T179
Test name
Test status
Simulation time 513409915 ps
CPU time 8.79 seconds
Started Aug 05 05:41:25 PM PDT 24
Finished Aug 05 05:41:34 PM PDT 24
Peak memory 212064 kb
Host smart-0f2dedab-65c8-4686-9956-581bdb6efc75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3081274783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3081274783
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1572387348
Short name T18
Test name
Test status
Simulation time 2029117758 ps
CPU time 10.98 seconds
Started Aug 05 05:41:25 PM PDT 24
Finished Aug 05 05:41:36 PM PDT 24
Peak memory 213404 kb
Host smart-25cfebb8-5a79-4e78-ad00-3d0364d472cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572387348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1572387348
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1807295199
Short name T219
Test name
Test status
Simulation time 520233959 ps
CPU time 4.33 seconds
Started Aug 05 05:41:09 PM PDT 24
Finished Aug 05 05:41:13 PM PDT 24
Peak memory 211960 kb
Host smart-8f637500-3aaf-4aec-a24e-1cd6ad9b5b70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807295199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1807295199
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1873909119
Short name T256
Test name
Test status
Simulation time 8349287087 ps
CPU time 162.64 seconds
Started Aug 05 05:41:17 PM PDT 24
Finished Aug 05 05:44:00 PM PDT 24
Peak memory 213432 kb
Host smart-4b4778c6-50f1-4853-b3bc-edf653388507
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873909119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1873909119
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3280316801
Short name T211
Test name
Test status
Simulation time 695476751 ps
CPU time 9.44 seconds
Started Aug 05 05:41:14 PM PDT 24
Finished Aug 05 05:41:24 PM PDT 24
Peak memory 212892 kb
Host smart-8bb24cf5-1e53-43b7-a0bc-6d8dc8ccc08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280316801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3280316801
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3272205107
Short name T191
Test name
Test status
Simulation time 267760957 ps
CPU time 6.34 seconds
Started Aug 05 05:41:20 PM PDT 24
Finished Aug 05 05:41:27 PM PDT 24
Peak memory 212208 kb
Host smart-ec514b63-6467-4b5e-9983-82807fd7f30b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3272205107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3272205107
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3753342356
Short name T77
Test name
Test status
Simulation time 912662615 ps
CPU time 13.8 seconds
Started Aug 05 05:41:16 PM PDT 24
Finished Aug 05 05:41:30 PM PDT 24
Peak memory 214288 kb
Host smart-b43aaa03-cddb-42e3-9efe-1311daaea6ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753342356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3753342356
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3660036340
Short name T262
Test name
Test status
Simulation time 726296432 ps
CPU time 5.06 seconds
Started Aug 05 05:41:25 PM PDT 24
Finished Aug 05 05:41:30 PM PDT 24
Peak memory 212040 kb
Host smart-20849b6c-2823-41a6-a2fd-176420819a4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660036340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3660036340
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.338650048
Short name T111
Test name
Test status
Simulation time 25428001594 ps
CPU time 137.38 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:43:29 PM PDT 24
Peak memory 238348 kb
Host smart-194242d0-5fe0-47a9-b283-5c0308f92962
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338650048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.338650048
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.768616365
Short name T313
Test name
Test status
Simulation time 256198389 ps
CPU time 11.57 seconds
Started Aug 05 05:41:15 PM PDT 24
Finished Aug 05 05:41:26 PM PDT 24
Peak memory 213236 kb
Host smart-c0a63ae6-e3d2-469a-99de-440c98e0653f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768616365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.768616365
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.986026052
Short name T3
Test name
Test status
Simulation time 190596252 ps
CPU time 5.66 seconds
Started Aug 05 05:41:08 PM PDT 24
Finished Aug 05 05:41:14 PM PDT 24
Peak memory 212160 kb
Host smart-65dde75f-0af3-4199-8f30-b6efd330db7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=986026052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.986026052
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.207270889
Short name T305
Test name
Test status
Simulation time 1012291967 ps
CPU time 15.89 seconds
Started Aug 05 05:41:23 PM PDT 24
Finished Aug 05 05:41:39 PM PDT 24
Peak memory 214872 kb
Host smart-681b76e4-08a7-4ddb-8dbd-006b6427e947
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207270889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.207270889
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2900571
Short name T131
Test name
Test status
Simulation time 156429213 ps
CPU time 4.59 seconds
Started Aug 05 05:41:35 PM PDT 24
Finished Aug 05 05:41:39 PM PDT 24
Peak memory 212060 kb
Host smart-b5b6718e-c63d-4e62-afe4-d4eb01859cd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2900571
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1787936636
Short name T245
Test name
Test status
Simulation time 5214145190 ps
CPU time 123.49 seconds
Started Aug 05 05:41:23 PM PDT 24
Finished Aug 05 05:43:27 PM PDT 24
Peak memory 225548 kb
Host smart-a992093d-ab1c-447e-9c0b-635f00cf261c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787936636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1787936636
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.14751460
Short name T291
Test name
Test status
Simulation time 1513464748 ps
CPU time 9.76 seconds
Started Aug 05 05:41:25 PM PDT 24
Finished Aug 05 05:41:35 PM PDT 24
Peak memory 212856 kb
Host smart-2bda5e4d-cd8e-4642-9159-b031f50a73d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14751460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.14751460
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1142106847
Short name T62
Test name
Test status
Simulation time 144811284 ps
CPU time 6.69 seconds
Started Aug 05 05:41:32 PM PDT 24
Finished Aug 05 05:41:39 PM PDT 24
Peak memory 212156 kb
Host smart-169c88d7-6157-4f15-93e3-c1df3cc072d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1142106847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1142106847
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1333973600
Short name T125
Test name
Test status
Simulation time 3363913722 ps
CPU time 21.26 seconds
Started Aug 05 05:41:26 PM PDT 24
Finished Aug 05 05:41:47 PM PDT 24
Peak memory 216184 kb
Host smart-48c33791-0bec-41a2-8ba6-a7fbb0f03e93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333973600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1333973600
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3341719625
Short name T199
Test name
Test status
Simulation time 134571724 ps
CPU time 4.92 seconds
Started Aug 05 05:41:26 PM PDT 24
Finished Aug 05 05:41:31 PM PDT 24
Peak memory 212084 kb
Host smart-39ce1954-6bf2-4ec0-9154-b34d4736b97f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341719625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3341719625
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.333068926
Short name T135
Test name
Test status
Simulation time 9578119498 ps
CPU time 142.63 seconds
Started Aug 05 05:41:21 PM PDT 24
Finished Aug 05 05:43:44 PM PDT 24
Peak memory 238348 kb
Host smart-8ce6ec83-4b6d-45cc-88e8-316bc6dd2e98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333068926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.333068926
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.10659046
Short name T7
Test name
Test status
Simulation time 698183884 ps
CPU time 9.36 seconds
Started Aug 05 05:41:24 PM PDT 24
Finished Aug 05 05:41:34 PM PDT 24
Peak memory 212360 kb
Host smart-90168a54-c48f-43ea-957b-e92562f7e6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10659046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.10659046
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1736104849
Short name T21
Test name
Test status
Simulation time 130386372 ps
CPU time 5.75 seconds
Started Aug 05 05:41:26 PM PDT 24
Finished Aug 05 05:41:32 PM PDT 24
Peak memory 212216 kb
Host smart-4eecc689-6682-4fdb-8e08-0c14c22099a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1736104849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1736104849
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2251096016
Short name T208
Test name
Test status
Simulation time 439466265 ps
CPU time 12.62 seconds
Started Aug 05 05:41:23 PM PDT 24
Finished Aug 05 05:41:36 PM PDT 24
Peak memory 214308 kb
Host smart-2ceaf7bf-799b-43b9-9bf4-e8e85f069545
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251096016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2251096016
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.966940260
Short name T49
Test name
Test status
Simulation time 245532390355 ps
CPU time 2313.28 seconds
Started Aug 05 05:41:24 PM PDT 24
Finished Aug 05 06:19:58 PM PDT 24
Peak memory 249668 kb
Host smart-033b8529-2da3-4f5f-affa-3533546c7daf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966940260 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.966940260
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2449424756
Short name T120
Test name
Test status
Simulation time 130433410 ps
CPU time 5.06 seconds
Started Aug 05 05:41:26 PM PDT 24
Finished Aug 05 05:41:31 PM PDT 24
Peak memory 212048 kb
Host smart-3a0e7f4a-e7ed-45ad-9ffc-5b39d07cdb30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449424756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2449424756
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1498462184
Short name T167
Test name
Test status
Simulation time 10100439827 ps
CPU time 137.19 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:43:28 PM PDT 24
Peak memory 235456 kb
Host smart-794e4823-43fa-4ae7-9385-ec877a4bcd79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498462184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1498462184
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2246301714
Short name T322
Test name
Test status
Simulation time 508895248 ps
CPU time 11.08 seconds
Started Aug 05 05:41:26 PM PDT 24
Finished Aug 05 05:41:37 PM PDT 24
Peak memory 212976 kb
Host smart-cfe8e242-35c6-440f-80b1-88e1ef1559ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246301714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2246301714
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.646736017
Short name T253
Test name
Test status
Simulation time 144120454 ps
CPU time 6.5 seconds
Started Aug 05 05:41:23 PM PDT 24
Finished Aug 05 05:41:29 PM PDT 24
Peak memory 212156 kb
Host smart-7245f37f-b829-479d-af14-0086416fda58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=646736017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.646736017
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3489256765
Short name T224
Test name
Test status
Simulation time 304388125 ps
CPU time 17.12 seconds
Started Aug 05 05:41:24 PM PDT 24
Finished Aug 05 05:41:41 PM PDT 24
Peak memory 214980 kb
Host smart-f4122a8a-a2cf-454a-a5e4-4480c7e1b34b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489256765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3489256765
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.26818122
Short name T277
Test name
Test status
Simulation time 9405441057 ps
CPU time 2270.03 seconds
Started Aug 05 05:41:26 PM PDT 24
Finished Aug 05 06:19:16 PM PDT 24
Peak memory 220340 kb
Host smart-6c9ec133-13a7-481a-a8fc-a47d18ba6907
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26818122 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.26818122
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2994926031
Short name T172
Test name
Test status
Simulation time 518318668 ps
CPU time 5.18 seconds
Started Aug 05 05:41:18 PM PDT 24
Finished Aug 05 05:41:23 PM PDT 24
Peak memory 212048 kb
Host smart-786482d6-bc38-44be-a1d3-98efc10d4865
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994926031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2994926031
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2440288439
Short name T166
Test name
Test status
Simulation time 2892843705 ps
CPU time 95.89 seconds
Started Aug 05 05:41:16 PM PDT 24
Finished Aug 05 05:42:52 PM PDT 24
Peak memory 240504 kb
Host smart-3323f183-5565-4e86-819c-bbb1367df6c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440288439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2440288439
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.973309490
Short name T38
Test name
Test status
Simulation time 508164751 ps
CPU time 11.22 seconds
Started Aug 05 05:41:12 PM PDT 24
Finished Aug 05 05:41:23 PM PDT 24
Peak memory 212556 kb
Host smart-5bdcf233-a908-48e6-afcd-b01587a331b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973309490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.973309490
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3829121910
Short name T1
Test name
Test status
Simulation time 142864525 ps
CPU time 6.53 seconds
Started Aug 05 05:41:28 PM PDT 24
Finished Aug 05 05:41:35 PM PDT 24
Peak memory 212164 kb
Host smart-4999480f-9e11-410c-8d7f-64443783df57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3829121910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3829121910
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.4171086134
Short name T272
Test name
Test status
Simulation time 803424746 ps
CPU time 18.17 seconds
Started Aug 05 05:41:25 PM PDT 24
Finished Aug 05 05:41:43 PM PDT 24
Peak memory 217296 kb
Host smart-9a26625d-0229-43de-89f2-8d78e605081f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171086134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.4171086134
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.4100666223
Short name T45
Test name
Test status
Simulation time 90645667785 ps
CPU time 3970.8 seconds
Started Aug 05 05:41:24 PM PDT 24
Finished Aug 05 06:47:35 PM PDT 24
Peak memory 254856 kb
Host smart-edc4cc1f-b1e2-4118-938a-569f0594378d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100666223 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.4100666223
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.337264037
Short name T240
Test name
Test status
Simulation time 178618005 ps
CPU time 5.04 seconds
Started Aug 05 05:41:26 PM PDT 24
Finished Aug 05 05:41:31 PM PDT 24
Peak memory 212088 kb
Host smart-1a772d2e-6e97-41d4-98cc-62cfd4732767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337264037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.337264037
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2076075166
Short name T156
Test name
Test status
Simulation time 4121057718 ps
CPU time 135.82 seconds
Started Aug 05 05:41:26 PM PDT 24
Finished Aug 05 05:43:42 PM PDT 24
Peak memory 229204 kb
Host smart-6836d766-686e-44e6-9f17-3ef588d318b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076075166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2076075166
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3584219410
Short name T113
Test name
Test status
Simulation time 2210381065 ps
CPU time 6.31 seconds
Started Aug 05 05:41:25 PM PDT 24
Finished Aug 05 05:41:32 PM PDT 24
Peak memory 212292 kb
Host smart-0e40eaf9-0020-479f-88ba-de5beeedfe06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3584219410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3584219410
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.45708122
Short name T53
Test name
Test status
Simulation time 458218901 ps
CPU time 10.58 seconds
Started Aug 05 05:41:26 PM PDT 24
Finished Aug 05 05:41:37 PM PDT 24
Peak memory 212248 kb
Host smart-a75c44ec-64b2-4aa6-8e9a-2d0a8d4b35e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45708122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 39.rom_ctrl_stress_all.45708122
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3020356856
Short name T200
Test name
Test status
Simulation time 1130506779 ps
CPU time 69.88 seconds
Started Aug 05 05:40:54 PM PDT 24
Finished Aug 05 05:42:04 PM PDT 24
Peak memory 237684 kb
Host smart-76850579-6fb1-404b-8949-752ba8670af0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020356856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3020356856
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3867628887
Short name T8
Test name
Test status
Simulation time 253621773 ps
CPU time 11.08 seconds
Started Aug 05 05:40:54 PM PDT 24
Finished Aug 05 05:41:05 PM PDT 24
Peak memory 214828 kb
Host smart-bb66d351-6543-47cf-8297-c10a532198b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867628887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3867628887
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3819111376
Short name T144
Test name
Test status
Simulation time 142054202 ps
CPU time 6.69 seconds
Started Aug 05 05:40:54 PM PDT 24
Finished Aug 05 05:41:01 PM PDT 24
Peak memory 212068 kb
Host smart-5c0fb1c5-7eeb-44a5-9ac5-2e2b1ec74356
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3819111376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3819111376
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.4276653660
Short name T26
Test name
Test status
Simulation time 254483532 ps
CPU time 102.85 seconds
Started Aug 05 05:40:49 PM PDT 24
Finished Aug 05 05:42:32 PM PDT 24
Peak memory 238872 kb
Host smart-f865c91d-ebf9-4a2e-a06d-af310a14f777
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276653660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.4276653660
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3577720598
Short name T78
Test name
Test status
Simulation time 3138567432 ps
CPU time 9.19 seconds
Started Aug 05 05:41:04 PM PDT 24
Finished Aug 05 05:41:13 PM PDT 24
Peak memory 212200 kb
Host smart-6ffb3e4b-63b5-4360-a037-8244be1399e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577720598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3577720598
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3312340617
Short name T284
Test name
Test status
Simulation time 3079919149 ps
CPU time 12.61 seconds
Started Aug 05 05:40:55 PM PDT 24
Finished Aug 05 05:41:08 PM PDT 24
Peak memory 212344 kb
Host smart-16980b90-abd2-4d33-b29c-795bcd7eae47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312340617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3312340617
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3190161957
Short name T43
Test name
Test status
Simulation time 66295261231 ps
CPU time 787.51 seconds
Started Aug 05 05:40:49 PM PDT 24
Finished Aug 05 05:53:57 PM PDT 24
Peak memory 234348 kb
Host smart-7cb61a6e-06f2-4f9d-8b78-ecc9da492037
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190161957 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.3190161957
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.494443970
Short name T239
Test name
Test status
Simulation time 173175896 ps
CPU time 4.22 seconds
Started Aug 05 05:41:25 PM PDT 24
Finished Aug 05 05:41:29 PM PDT 24
Peak memory 212052 kb
Host smart-34775f52-7c37-46f8-9dde-963f25c822b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494443970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.494443970
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4152640716
Short name T185
Test name
Test status
Simulation time 5532503943 ps
CPU time 190.62 seconds
Started Aug 05 05:41:45 PM PDT 24
Finished Aug 05 05:44:56 PM PDT 24
Peak memory 238496 kb
Host smart-a5c4b253-9344-4d07-a8ef-2cab389b5626
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152640716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4152640716
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1548463663
Short name T169
Test name
Test status
Simulation time 283716420 ps
CPU time 11.34 seconds
Started Aug 05 05:41:20 PM PDT 24
Finished Aug 05 05:41:31 PM PDT 24
Peak memory 212820 kb
Host smart-ea9899d9-9ce7-4dca-9d5b-cdfaa59cc982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548463663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1548463663
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1894053097
Short name T218
Test name
Test status
Simulation time 846391257 ps
CPU time 6.48 seconds
Started Aug 05 05:41:14 PM PDT 24
Finished Aug 05 05:41:20 PM PDT 24
Peak memory 212156 kb
Host smart-7116655c-261d-4948-b5dd-efe99d34a4b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1894053097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1894053097
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2844900378
Short name T236
Test name
Test status
Simulation time 2057400576 ps
CPU time 26.04 seconds
Started Aug 05 05:41:26 PM PDT 24
Finished Aug 05 05:41:52 PM PDT 24
Peak memory 219968 kb
Host smart-29290345-3e66-4207-ba7a-fbc305b8f332
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844900378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2844900378
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2745294881
Short name T46
Test name
Test status
Simulation time 23741105521 ps
CPU time 952.32 seconds
Started Aug 05 05:41:24 PM PDT 24
Finished Aug 05 05:57:16 PM PDT 24
Peak memory 236620 kb
Host smart-295e6374-18ba-4815-9ef2-cc018c4db309
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745294881 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.2745294881
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1479914987
Short name T230
Test name
Test status
Simulation time 755656060 ps
CPU time 4.22 seconds
Started Aug 05 05:41:21 PM PDT 24
Finished Aug 05 05:41:25 PM PDT 24
Peak memory 212032 kb
Host smart-1f3c6ed8-2e83-4f18-b626-5948526d6a17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479914987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1479914987
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.960044373
Short name T207
Test name
Test status
Simulation time 3227920308 ps
CPU time 164.32 seconds
Started Aug 05 05:41:27 PM PDT 24
Finished Aug 05 05:44:12 PM PDT 24
Peak memory 238792 kb
Host smart-3e2ed1dc-b9f8-4849-b3fb-a4171460dec8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960044373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.960044373
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.418532396
Short name T248
Test name
Test status
Simulation time 1082018602 ps
CPU time 11.17 seconds
Started Aug 05 05:41:25 PM PDT 24
Finished Aug 05 05:41:36 PM PDT 24
Peak memory 212876 kb
Host smart-edb0ebba-0540-4f0a-b692-c341ebb36b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418532396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.418532396
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1547653181
Short name T142
Test name
Test status
Simulation time 524282744 ps
CPU time 8.86 seconds
Started Aug 05 05:41:25 PM PDT 24
Finished Aug 05 05:41:34 PM PDT 24
Peak memory 212176 kb
Host smart-dc9806f2-dabc-4d00-8a88-46c53fc8efcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1547653181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1547653181
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3954873785
Short name T127
Test name
Test status
Simulation time 1106062100 ps
CPU time 15.55 seconds
Started Aug 05 05:41:23 PM PDT 24
Finished Aug 05 05:41:39 PM PDT 24
Peak memory 214640 kb
Host smart-edb2d239-5bd6-4057-bb57-af3abad33498
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954873785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3954873785
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3244082425
Short name T122
Test name
Test status
Simulation time 255885446 ps
CPU time 5.07 seconds
Started Aug 05 05:41:24 PM PDT 24
Finished Aug 05 05:41:29 PM PDT 24
Peak memory 211932 kb
Host smart-60a23ec4-262a-4b30-8dc7-e4d8e01b8589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244082425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3244082425
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4263522934
Short name T30
Test name
Test status
Simulation time 2448100010 ps
CPU time 130.67 seconds
Started Aug 05 05:41:23 PM PDT 24
Finished Aug 05 05:43:34 PM PDT 24
Peak memory 234140 kb
Host smart-44cb483d-2077-41cf-9752-0df5dfdfefef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263522934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.4263522934
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2982216199
Short name T301
Test name
Test status
Simulation time 507005493 ps
CPU time 11.35 seconds
Started Aug 05 05:41:23 PM PDT 24
Finished Aug 05 05:41:34 PM PDT 24
Peak memory 212940 kb
Host smart-a9f6c6a5-da3c-4eee-9f57-3ad4229fbb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982216199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2982216199
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2182725434
Short name T170
Test name
Test status
Simulation time 282546381 ps
CPU time 6.22 seconds
Started Aug 05 05:41:25 PM PDT 24
Finished Aug 05 05:41:31 PM PDT 24
Peak memory 212216 kb
Host smart-e3ac8d98-0c46-4968-8f1f-22eaa95a50e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2182725434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2182725434
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2364859681
Short name T223
Test name
Test status
Simulation time 1518753546 ps
CPU time 13.19 seconds
Started Aug 05 05:41:29 PM PDT 24
Finished Aug 05 05:41:42 PM PDT 24
Peak memory 214852 kb
Host smart-1d2e60ae-ffe8-4fbc-80ab-468c6f0480ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364859681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2364859681
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2141056867
Short name T317
Test name
Test status
Simulation time 29339985801 ps
CPU time 5702.69 seconds
Started Aug 05 05:41:12 PM PDT 24
Finished Aug 05 07:16:16 PM PDT 24
Peak memory 229180 kb
Host smart-189f10c9-3798-4740-ab09-add2d7024bb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141056867 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2141056867
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3759567736
Short name T133
Test name
Test status
Simulation time 1180313472 ps
CPU time 4.18 seconds
Started Aug 05 05:41:43 PM PDT 24
Finished Aug 05 05:41:47 PM PDT 24
Peak memory 212060 kb
Host smart-bf8e2c72-8d7d-4c4b-b2e5-28b34774fded
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759567736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3759567736
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.992965043
Short name T254
Test name
Test status
Simulation time 841054709 ps
CPU time 9.63 seconds
Started Aug 05 05:41:25 PM PDT 24
Finished Aug 05 05:41:35 PM PDT 24
Peak memory 212888 kb
Host smart-f2d984e5-8750-43a9-8c44-a9ff2ed32f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992965043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.992965043
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1625469084
Short name T286
Test name
Test status
Simulation time 525916117 ps
CPU time 6.18 seconds
Started Aug 05 05:41:26 PM PDT 24
Finished Aug 05 05:41:33 PM PDT 24
Peak memory 212116 kb
Host smart-86d34ad4-dcf8-4985-a86e-22a3b26537e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1625469084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1625469084
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3097027844
Short name T15
Test name
Test status
Simulation time 58408170762 ps
CPU time 681.47 seconds
Started Aug 05 05:41:24 PM PDT 24
Finished Aug 05 05:52:46 PM PDT 24
Peak memory 236588 kb
Host smart-a531edb2-fc4e-459a-9d23-d65ba8606d8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097027844 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3097027844
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1201250736
Short name T274
Test name
Test status
Simulation time 624488816 ps
CPU time 5.06 seconds
Started Aug 05 05:41:29 PM PDT 24
Finished Aug 05 05:41:34 PM PDT 24
Peak memory 212088 kb
Host smart-e634a17b-f6b7-4577-955e-72a582cf8669
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201250736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1201250736
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.673670213
Short name T23
Test name
Test status
Simulation time 4015617479 ps
CPU time 56.02 seconds
Started Aug 05 05:41:31 PM PDT 24
Finished Aug 05 05:42:27 PM PDT 24
Peak memory 237200 kb
Host smart-7f00fa9e-5b93-4b97-ba49-0081b737c907
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673670213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.673670213
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1485392815
Short name T298
Test name
Test status
Simulation time 251831737 ps
CPU time 11.37 seconds
Started Aug 05 05:41:27 PM PDT 24
Finished Aug 05 05:41:39 PM PDT 24
Peak memory 212996 kb
Host smart-ac0fa233-0402-4f1c-b037-9c55d7433fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485392815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1485392815
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2134545406
Short name T259
Test name
Test status
Simulation time 102104644 ps
CPU time 5.79 seconds
Started Aug 05 05:41:23 PM PDT 24
Finished Aug 05 05:41:29 PM PDT 24
Peak memory 212100 kb
Host smart-519ca88e-8a88-463b-9f3c-58bb0f2c52ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2134545406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2134545406
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2844004878
Short name T76
Test name
Test status
Simulation time 488767796 ps
CPU time 6.37 seconds
Started Aug 05 05:41:20 PM PDT 24
Finished Aug 05 05:41:26 PM PDT 24
Peak memory 212112 kb
Host smart-64a9c699-d7ce-4512-8256-dbc0cabde05b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844004878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2844004878
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.4009815283
Short name T202
Test name
Test status
Simulation time 60285240201 ps
CPU time 1036.86 seconds
Started Aug 05 05:41:20 PM PDT 24
Finished Aug 05 05:58:37 PM PDT 24
Peak memory 231312 kb
Host smart-8841958b-6e93-4ff6-b86c-20205460c256
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009815283 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.4009815283
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3080397223
Short name T315
Test name
Test status
Simulation time 1772803091 ps
CPU time 5.28 seconds
Started Aug 05 05:41:36 PM PDT 24
Finished Aug 05 05:41:41 PM PDT 24
Peak memory 212064 kb
Host smart-aeb24f52-3eb7-4948-8af8-a8cfcc950e61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080397223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3080397223
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1888646669
Short name T178
Test name
Test status
Simulation time 3587219863 ps
CPU time 91.5 seconds
Started Aug 05 05:41:27 PM PDT 24
Finished Aug 05 05:42:58 PM PDT 24
Peak memory 238428 kb
Host smart-2243e067-b483-4eea-9852-d61cb5a1a9c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888646669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1888646669
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3671432821
Short name T234
Test name
Test status
Simulation time 639679752 ps
CPU time 11.2 seconds
Started Aug 05 05:41:48 PM PDT 24
Finished Aug 05 05:41:59 PM PDT 24
Peak memory 213112 kb
Host smart-903c2671-0d33-4541-81ef-a5458090034e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671432821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3671432821
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3920240320
Short name T209
Test name
Test status
Simulation time 162268751 ps
CPU time 6.56 seconds
Started Aug 05 05:41:36 PM PDT 24
Finished Aug 05 05:41:43 PM PDT 24
Peak memory 212056 kb
Host smart-4bd39a11-db0f-4a2b-80b3-e66c7f99e6e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3920240320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3920240320
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2308258278
Short name T263
Test name
Test status
Simulation time 3066188480 ps
CPU time 25.63 seconds
Started Aug 05 05:41:29 PM PDT 24
Finished Aug 05 05:41:55 PM PDT 24
Peak memory 216756 kb
Host smart-f3d74fdc-3f2f-495a-9255-e9e8bf5e8e59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308258278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2308258278
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3956846002
Short name T140
Test name
Test status
Simulation time 2134650138 ps
CPU time 7.65 seconds
Started Aug 05 05:41:52 PM PDT 24
Finished Aug 05 05:42:00 PM PDT 24
Peak memory 212068 kb
Host smart-6843ac12-7ab3-43cf-82db-0118316ffbcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956846002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3956846002
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.698925787
Short name T221
Test name
Test status
Simulation time 7223605480 ps
CPU time 105.42 seconds
Started Aug 05 05:41:27 PM PDT 24
Finished Aug 05 05:43:13 PM PDT 24
Peak memory 213576 kb
Host smart-da886513-c8cf-4269-84ea-7f85bc834668
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698925787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.698925787
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1640803583
Short name T37
Test name
Test status
Simulation time 354831350 ps
CPU time 9.36 seconds
Started Aug 05 05:41:30 PM PDT 24
Finished Aug 05 05:41:39 PM PDT 24
Peak memory 212840 kb
Host smart-f8a8bcda-97cc-4a71-9228-4f55af46a176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640803583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1640803583
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3426550779
Short name T266
Test name
Test status
Simulation time 560617358 ps
CPU time 6.52 seconds
Started Aug 05 05:41:26 PM PDT 24
Finished Aug 05 05:41:33 PM PDT 24
Peak memory 212180 kb
Host smart-1e1f06ca-d7ad-4edb-b557-5124c17abad8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3426550779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3426550779
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3436905883
Short name T153
Test name
Test status
Simulation time 1413176697 ps
CPU time 7.46 seconds
Started Aug 05 05:41:23 PM PDT 24
Finished Aug 05 05:41:30 PM PDT 24
Peak memory 212028 kb
Host smart-dc9b9ca6-e94a-4e7b-af8c-74781876dd94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436905883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3436905883
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3164037881
Short name T9
Test name
Test status
Simulation time 87878354 ps
CPU time 4.36 seconds
Started Aug 05 05:41:35 PM PDT 24
Finished Aug 05 05:41:40 PM PDT 24
Peak memory 212040 kb
Host smart-d62d037c-b0bd-40dd-99a9-29f10c16b8d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164037881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3164037881
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2565628602
Short name T288
Test name
Test status
Simulation time 2663568483 ps
CPU time 126.99 seconds
Started Aug 05 05:41:26 PM PDT 24
Finished Aug 05 05:43:33 PM PDT 24
Peak memory 234960 kb
Host smart-a9225db7-ef93-410f-923a-5e041be7e91f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565628602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2565628602
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1124861816
Short name T39
Test name
Test status
Simulation time 173788560 ps
CPU time 9.53 seconds
Started Aug 05 05:41:22 PM PDT 24
Finished Aug 05 05:41:37 PM PDT 24
Peak memory 212848 kb
Host smart-c03c51fa-6aed-4172-97ad-3d2196828795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124861816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1124861816
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1680994027
Short name T293
Test name
Test status
Simulation time 189028888 ps
CPU time 5.74 seconds
Started Aug 05 05:41:25 PM PDT 24
Finished Aug 05 05:41:31 PM PDT 24
Peak memory 212184 kb
Host smart-63fe68c7-c2ea-4be6-b405-7a06271e8c8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1680994027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1680994027
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3859785991
Short name T283
Test name
Test status
Simulation time 1184842001 ps
CPU time 14.49 seconds
Started Aug 05 05:41:42 PM PDT 24
Finished Aug 05 05:41:57 PM PDT 24
Peak memory 214440 kb
Host smart-2c1362ce-6075-405d-a222-45f47b39433b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859785991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3859785991
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.962163030
Short name T235
Test name
Test status
Simulation time 73930633151 ps
CPU time 701.37 seconds
Started Aug 05 05:41:35 PM PDT 24
Finished Aug 05 05:53:17 PM PDT 24
Peak memory 228552 kb
Host smart-8ef618d1-0a62-40e3-8cbd-19da5bdd8e02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962163030 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.962163030
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1633606674
Short name T116
Test name
Test status
Simulation time 136015141 ps
CPU time 4.99 seconds
Started Aug 05 05:41:45 PM PDT 24
Finished Aug 05 05:41:50 PM PDT 24
Peak memory 212044 kb
Host smart-9cedf7a5-1239-4611-8f23-0b9ef958e29f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633606674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1633606674
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3789034283
Short name T163
Test name
Test status
Simulation time 2554993324 ps
CPU time 125.24 seconds
Started Aug 05 05:41:30 PM PDT 24
Finished Aug 05 05:43:36 PM PDT 24
Peak memory 238440 kb
Host smart-41580a09-cc94-487a-b5d6-0d6754bc07fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789034283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3789034283
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.4162546361
Short name T175
Test name
Test status
Simulation time 142243768 ps
CPU time 6.41 seconds
Started Aug 05 05:41:25 PM PDT 24
Finished Aug 05 05:41:32 PM PDT 24
Peak memory 212080 kb
Host smart-e7d2b45a-f12f-40c1-8a31-a6748a6546df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4162546361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.4162546361
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3058495689
Short name T19
Test name
Test status
Simulation time 189418236 ps
CPU time 11.6 seconds
Started Aug 05 05:41:28 PM PDT 24
Finished Aug 05 05:41:40 PM PDT 24
Peak memory 213836 kb
Host smart-1d4f2778-a812-49ae-bae2-0616900f0da9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058495689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3058495689
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1684917749
Short name T206
Test name
Test status
Simulation time 134895395 ps
CPU time 5.28 seconds
Started Aug 05 05:41:36 PM PDT 24
Finished Aug 05 05:41:41 PM PDT 24
Peak memory 212060 kb
Host smart-e3941f92-2548-4594-82a6-b2dc5a9cc3ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684917749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1684917749
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.663559867
Short name T217
Test name
Test status
Simulation time 7296522364 ps
CPU time 94.97 seconds
Started Aug 05 05:41:37 PM PDT 24
Finished Aug 05 05:43:12 PM PDT 24
Peak memory 213392 kb
Host smart-d9be2c2d-aaeb-4afb-8f6b-a9ca8b6b52fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663559867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.663559867
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.528041671
Short name T124
Test name
Test status
Simulation time 994647069 ps
CPU time 11.37 seconds
Started Aug 05 05:41:34 PM PDT 24
Finished Aug 05 05:41:45 PM PDT 24
Peak memory 212908 kb
Host smart-40d96316-ea36-4ffb-ad02-cae0ade64a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528041671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.528041671
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1106065657
Short name T193
Test name
Test status
Simulation time 201919107 ps
CPU time 5.78 seconds
Started Aug 05 05:41:28 PM PDT 24
Finished Aug 05 05:41:34 PM PDT 24
Peak memory 212092 kb
Host smart-c96c3f5b-04f4-41e4-a7b1-1e5c6d1a962d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1106065657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1106065657
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2870535163
Short name T271
Test name
Test status
Simulation time 311837430 ps
CPU time 16.23 seconds
Started Aug 05 05:41:19 PM PDT 24
Finished Aug 05 05:41:36 PM PDT 24
Peak memory 215920 kb
Host smart-37e798b0-48bf-4ce0-aeb2-8cd25b6014db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870535163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2870535163
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3358801050
Short name T150
Test name
Test status
Simulation time 346705546 ps
CPU time 4.26 seconds
Started Aug 05 05:41:03 PM PDT 24
Finished Aug 05 05:41:08 PM PDT 24
Peak memory 212052 kb
Host smart-e5ef5e04-9417-418a-a936-c2c78bd81b1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358801050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3358801050
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1146700450
Short name T189
Test name
Test status
Simulation time 11668830585 ps
CPU time 150.84 seconds
Started Aug 05 05:41:00 PM PDT 24
Finished Aug 05 05:43:30 PM PDT 24
Peak memory 228336 kb
Host smart-fdf747e4-2f32-4b3d-b879-0dadfdf78433
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146700450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1146700450
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2065066102
Short name T250
Test name
Test status
Simulation time 258174159 ps
CPU time 11.26 seconds
Started Aug 05 05:41:12 PM PDT 24
Finished Aug 05 05:41:24 PM PDT 24
Peak memory 212912 kb
Host smart-7eab30a3-2712-499d-a779-9d3218333d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065066102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2065066102
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.4207278566
Short name T164
Test name
Test status
Simulation time 94047203 ps
CPU time 5.53 seconds
Started Aug 05 05:41:02 PM PDT 24
Finished Aug 05 05:41:08 PM PDT 24
Peak memory 212184 kb
Host smart-342eaa26-3d7e-4d1c-981d-d440e8e28cce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4207278566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.4207278566
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1425517629
Short name T244
Test name
Test status
Simulation time 852159961 ps
CPU time 5.52 seconds
Started Aug 05 05:41:00 PM PDT 24
Finished Aug 05 05:41:06 PM PDT 24
Peak memory 212276 kb
Host smart-02edd300-3b28-486a-9030-f18149c31143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425517629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1425517629
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.658087173
Short name T176
Test name
Test status
Simulation time 645156908 ps
CPU time 6.78 seconds
Started Aug 05 05:41:01 PM PDT 24
Finished Aug 05 05:41:08 PM PDT 24
Peak memory 212340 kb
Host smart-186c9192-0bb6-41bd-b3d9-e8a12c3e52a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658087173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.658087173
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.4293872047
Short name T320
Test name
Test status
Simulation time 41854733173 ps
CPU time 1620.64 seconds
Started Aug 05 05:40:56 PM PDT 24
Finished Aug 05 06:07:57 PM PDT 24
Peak memory 236672 kb
Host smart-47043960-7c83-4cb4-add9-2c28b575aef9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293872047 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.4293872047
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1725462276
Short name T292
Test name
Test status
Simulation time 571119771 ps
CPU time 5.16 seconds
Started Aug 05 05:40:52 PM PDT 24
Finished Aug 05 05:40:57 PM PDT 24
Peak memory 211964 kb
Host smart-031f5758-4841-41af-b4f4-70e038e52b30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725462276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1725462276
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1661811398
Short name T157
Test name
Test status
Simulation time 1022969768 ps
CPU time 70.39 seconds
Started Aug 05 05:41:06 PM PDT 24
Finished Aug 05 05:42:16 PM PDT 24
Peak memory 238304 kb
Host smart-ef200cd1-fa16-40f1-a634-ece07b9b4f3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661811398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1661811398
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1467427470
Short name T129
Test name
Test status
Simulation time 319028797 ps
CPU time 11.17 seconds
Started Aug 05 05:40:49 PM PDT 24
Finished Aug 05 05:41:01 PM PDT 24
Peak memory 212172 kb
Host smart-85a73c13-d2f2-47fd-87ee-2a3b44e28b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467427470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1467427470
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1324070434
Short name T188
Test name
Test status
Simulation time 139740169 ps
CPU time 6.79 seconds
Started Aug 05 05:40:51 PM PDT 24
Finished Aug 05 05:40:58 PM PDT 24
Peak memory 212188 kb
Host smart-549d80ad-0e11-4632-8299-df55a618b42c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1324070434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1324070434
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3759662003
Short name T260
Test name
Test status
Simulation time 533443009 ps
CPU time 6.27 seconds
Started Aug 05 05:41:00 PM PDT 24
Finished Aug 05 05:41:07 PM PDT 24
Peak memory 212076 kb
Host smart-e7acd3e3-0d60-4400-a22f-230a91fac83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759662003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3759662003
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3081883741
Short name T159
Test name
Test status
Simulation time 203602005 ps
CPU time 10.7 seconds
Started Aug 05 05:40:59 PM PDT 24
Finished Aug 05 05:41:09 PM PDT 24
Peak memory 214340 kb
Host smart-903d9dbd-0a89-463a-a3ee-5143270b39a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081883741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3081883741
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1708714587
Short name T300
Test name
Test status
Simulation time 48951586447 ps
CPU time 921.5 seconds
Started Aug 05 05:40:52 PM PDT 24
Finished Aug 05 05:56:13 PM PDT 24
Peak memory 236676 kb
Host smart-5573c043-9da9-4052-aad2-08715c1738b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708714587 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.1708714587
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1889971730
Short name T324
Test name
Test status
Simulation time 465101173 ps
CPU time 5.18 seconds
Started Aug 05 05:40:54 PM PDT 24
Finished Aug 05 05:40:59 PM PDT 24
Peak memory 212020 kb
Host smart-7ffcbf9c-0b11-4257-b784-c146fff4b220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889971730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1889971730
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.4159740889
Short name T31
Test name
Test status
Simulation time 5836080554 ps
CPU time 130.61 seconds
Started Aug 05 05:40:54 PM PDT 24
Finished Aug 05 05:43:05 PM PDT 24
Peak memory 238316 kb
Host smart-1fd9e722-b410-4f99-b9d7-9c58e348675f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159740889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.4159740889
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.488674352
Short name T325
Test name
Test status
Simulation time 169968166 ps
CPU time 9.66 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:41:20 PM PDT 24
Peak memory 212920 kb
Host smart-b9d505d2-284c-4e59-b909-5676f4e474e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488674352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.488674352
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1666304309
Short name T232
Test name
Test status
Simulation time 101812437 ps
CPU time 5.81 seconds
Started Aug 05 05:41:00 PM PDT 24
Finished Aug 05 05:41:06 PM PDT 24
Peak memory 212180 kb
Host smart-0074c5f9-f660-4c88-9d3e-6c9f89a8311b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1666304309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1666304309
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2863021207
Short name T51
Test name
Test status
Simulation time 530995835 ps
CPU time 6.26 seconds
Started Aug 05 05:41:06 PM PDT 24
Finished Aug 05 05:41:12 PM PDT 24
Peak memory 212208 kb
Host smart-622efc9a-cc43-4de4-90bc-097dad32d279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863021207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2863021207
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2054216352
Short name T273
Test name
Test status
Simulation time 2637839132 ps
CPU time 18.47 seconds
Started Aug 05 05:40:52 PM PDT 24
Finished Aug 05 05:41:11 PM PDT 24
Peak memory 214676 kb
Host smart-23361bbf-23e0-4ac7-917f-3176ca5274ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054216352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2054216352
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2781541622
Short name T261
Test name
Test status
Simulation time 127555895 ps
CPU time 5.13 seconds
Started Aug 05 05:41:00 PM PDT 24
Finished Aug 05 05:41:05 PM PDT 24
Peak memory 212036 kb
Host smart-9b7c508f-2644-45c1-9858-1ff91684d561
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781541622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2781541622
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2864321912
Short name T205
Test name
Test status
Simulation time 1705584893 ps
CPU time 105.37 seconds
Started Aug 05 05:41:08 PM PDT 24
Finished Aug 05 05:42:54 PM PDT 24
Peak memory 237688 kb
Host smart-6b1d589c-52d9-4777-8237-d049eb21da2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864321912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2864321912
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3809540369
Short name T162
Test name
Test status
Simulation time 2261679720 ps
CPU time 10.97 seconds
Started Aug 05 05:41:09 PM PDT 24
Finished Aug 05 05:41:20 PM PDT 24
Peak memory 213088 kb
Host smart-92dacb82-1d16-4266-9b0b-fd5612a73cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809540369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3809540369
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3370756666
Short name T182
Test name
Test status
Simulation time 1512600182 ps
CPU time 5.52 seconds
Started Aug 05 05:41:08 PM PDT 24
Finished Aug 05 05:41:14 PM PDT 24
Peak memory 212096 kb
Host smart-772ff108-fc82-46c4-a60a-1da42f0bbb45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3370756666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3370756666
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1087504536
Short name T171
Test name
Test status
Simulation time 390152564 ps
CPU time 5.46 seconds
Started Aug 05 05:41:01 PM PDT 24
Finished Aug 05 05:41:06 PM PDT 24
Peak memory 212176 kb
Host smart-f113a08f-0285-4304-98bd-ce924dbdbbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087504536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1087504536
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.4122951006
Short name T242
Test name
Test status
Simulation time 803549690 ps
CPU time 17.31 seconds
Started Aug 05 05:41:00 PM PDT 24
Finished Aug 05 05:41:18 PM PDT 24
Peak memory 215360 kb
Host smart-05f32751-9c3d-4c20-9654-a0ef53b5c86f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122951006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.4122951006
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3027100183
Short name T328
Test name
Test status
Simulation time 350213456 ps
CPU time 4.36 seconds
Started Aug 05 05:41:01 PM PDT 24
Finished Aug 05 05:41:05 PM PDT 24
Peak memory 211932 kb
Host smart-68119623-139c-4a15-bf80-09ce9ff735c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027100183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3027100183
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3829700724
Short name T36
Test name
Test status
Simulation time 3525700219 ps
CPU time 175.23 seconds
Started Aug 05 05:41:11 PM PDT 24
Finished Aug 05 05:44:07 PM PDT 24
Peak memory 238796 kb
Host smart-4b6a718a-0a3b-49bb-86d6-a823335e2b42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829700724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3829700724
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2497915168
Short name T269
Test name
Test status
Simulation time 669582622 ps
CPU time 9.56 seconds
Started Aug 05 05:41:06 PM PDT 24
Finished Aug 05 05:41:16 PM PDT 24
Peak memory 212988 kb
Host smart-c2dd6d1f-5b1e-4404-af16-7698037c3af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497915168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2497915168
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1248745128
Short name T268
Test name
Test status
Simulation time 738036255 ps
CPU time 6.26 seconds
Started Aug 05 05:41:08 PM PDT 24
Finished Aug 05 05:41:14 PM PDT 24
Peak memory 212164 kb
Host smart-fd2ce251-cf14-40b0-aa10-70fbd0aac104
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1248745128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1248745128
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3418710924
Short name T81
Test name
Test status
Simulation time 134856203 ps
CPU time 6.89 seconds
Started Aug 05 05:41:07 PM PDT 24
Finished Aug 05 05:41:14 PM PDT 24
Peak memory 212052 kb
Host smart-5922ab49-e09b-4b27-9cdd-f8920e517586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418710924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3418710924
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.988332877
Short name T231
Test name
Test status
Simulation time 215501874 ps
CPU time 10.76 seconds
Started Aug 05 05:41:00 PM PDT 24
Finished Aug 05 05:41:11 PM PDT 24
Peak memory 214124 kb
Host smart-f9b28d9c-cf2c-43de-ad34-48ca62534f09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988332877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.988332877
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.917162473
Short name T299
Test name
Test status
Simulation time 65570578352 ps
CPU time 2821.19 seconds
Started Aug 05 05:40:57 PM PDT 24
Finished Aug 05 06:27:59 PM PDT 24
Peak memory 244880 kb
Host smart-78c9d791-c71b-4ef9-8e40-956f59b18520
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917162473 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.917162473
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%