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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.24 96.89 91.99 97.67 100.00 98.28 97.45 98.37


Total test records in report: 414
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T299 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1464201576 Aug 06 06:24:56 PM PDT 24 Aug 06 06:26:27 PM PDT 24 4353530306 ps
T300 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2638574117 Aug 06 06:23:42 PM PDT 24 Aug 06 06:23:47 PM PDT 24 1827318766 ps
T301 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2315761776 Aug 06 06:22:59 PM PDT 24 Aug 06 06:23:11 PM PDT 24 370066443 ps
T302 /workspace/coverage/default/48.rom_ctrl_stress_all.1066295648 Aug 06 06:24:43 PM PDT 24 Aug 06 06:24:52 PM PDT 24 150087652 ps
T303 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1168880651 Aug 06 06:24:09 PM PDT 24 Aug 06 06:24:20 PM PDT 24 251867572 ps
T97 /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2414580917 Aug 06 06:22:18 PM PDT 24 Aug 06 07:02:18 PM PDT 24 234849544403 ps
T304 /workspace/coverage/default/25.rom_ctrl_alert_test.683967748 Aug 06 06:22:32 PM PDT 24 Aug 06 06:22:37 PM PDT 24 247426730 ps
T305 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.121058617 Aug 06 06:22:03 PM PDT 24 Aug 06 06:22:14 PM PDT 24 510239254 ps
T306 /workspace/coverage/default/31.rom_ctrl_stress_all.3811983036 Aug 06 06:23:00 PM PDT 24 Aug 06 06:23:15 PM PDT 24 956039402 ps
T307 /workspace/coverage/default/44.rom_ctrl_alert_test.919427221 Aug 06 06:24:21 PM PDT 24 Aug 06 06:24:26 PM PDT 24 175994308 ps
T308 /workspace/coverage/default/37.rom_ctrl_alert_test.1512016400 Aug 06 06:24:11 PM PDT 24 Aug 06 06:24:16 PM PDT 24 126623490 ps
T309 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.899428994 Aug 06 06:24:10 PM PDT 24 Aug 06 06:24:19 PM PDT 24 1980749146 ps
T310 /workspace/coverage/default/4.rom_ctrl_stress_all.2765018940 Aug 06 06:19:55 PM PDT 24 Aug 06 06:20:03 PM PDT 24 834738101 ps
T311 /workspace/coverage/default/28.rom_ctrl_stress_all.1610676316 Aug 06 06:22:45 PM PDT 24 Aug 06 06:22:51 PM PDT 24 517524448 ps
T14 /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1069024897 Aug 06 06:20:08 PM PDT 24 Aug 06 06:41:57 PM PDT 24 68726982255 ps
T312 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.248839299 Aug 06 06:23:17 PM PDT 24 Aug 06 06:24:36 PM PDT 24 1223203755 ps
T313 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.76167942 Aug 06 06:24:09 PM PDT 24 Aug 06 06:25:58 PM PDT 24 8035759279 ps
T314 /workspace/coverage/default/47.rom_ctrl_stress_all.2778394757 Aug 06 06:24:44 PM PDT 24 Aug 06 06:25:05 PM PDT 24 3129191749 ps
T315 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.807910742 Aug 06 06:24:08 PM PDT 24 Aug 06 06:26:33 PM PDT 24 8459253156 ps
T316 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.4087227433 Aug 06 06:24:11 PM PDT 24 Aug 06 06:24:16 PM PDT 24 95202343 ps
T317 /workspace/coverage/default/21.rom_ctrl_stress_all.2882469029 Aug 06 06:22:03 PM PDT 24 Aug 06 06:22:15 PM PDT 24 762114546 ps
T318 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.4145952821 Aug 06 06:24:06 PM PDT 24 Aug 06 06:24:16 PM PDT 24 1850894745 ps
T319 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2592438552 Aug 06 06:21:43 PM PDT 24 Aug 06 06:21:53 PM PDT 24 170245243 ps
T320 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3074445771 Aug 06 06:21:41 PM PDT 24 Aug 06 06:21:47 PM PDT 24 139083470 ps
T321 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3083196136 Aug 06 06:23:18 PM PDT 24 Aug 06 06:23:25 PM PDT 24 797376840 ps
T322 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.53017312 Aug 06 06:24:08 PM PDT 24 Aug 06 06:26:33 PM PDT 24 2495210098 ps
T323 /workspace/coverage/default/14.rom_ctrl_stress_all.2892514368 Aug 06 06:21:23 PM PDT 24 Aug 06 06:21:36 PM PDT 24 179457357 ps
T324 /workspace/coverage/default/6.rom_ctrl_smoke.933038186 Aug 06 06:20:27 PM PDT 24 Aug 06 06:20:33 PM PDT 24 139407387 ps
T325 /workspace/coverage/default/39.rom_ctrl_alert_test.1443962733 Aug 06 06:24:07 PM PDT 24 Aug 06 06:24:11 PM PDT 24 85620779 ps
T326 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3656298994 Aug 06 06:21:51 PM PDT 24 Aug 06 06:21:58 PM PDT 24 559076924 ps
T327 /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3747272689 Aug 06 06:24:43 PM PDT 24 Aug 06 06:54:58 PM PDT 24 242416889628 ps
T328 /workspace/coverage/default/15.rom_ctrl_alert_test.3446787856 Aug 06 06:21:42 PM PDT 24 Aug 06 06:21:47 PM PDT 24 253782622 ps
T329 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3634746757 Aug 06 06:24:22 PM PDT 24 Aug 06 06:24:29 PM PDT 24 884344521 ps
T50 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.747446850 Aug 06 07:07:42 PM PDT 24 Aug 06 07:07:47 PM PDT 24 166617373 ps
T51 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.878068148 Aug 06 07:07:43 PM PDT 24 Aug 06 07:07:49 PM PDT 24 96022890 ps
T47 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4025328719 Aug 06 07:07:43 PM PDT 24 Aug 06 07:08:52 PM PDT 24 1169575426 ps
T330 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1011913550 Aug 06 07:07:41 PM PDT 24 Aug 06 07:07:48 PM PDT 24 171505540 ps
T48 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1319888552 Aug 06 07:07:41 PM PDT 24 Aug 06 07:08:50 PM PDT 24 1030654396 ps
T88 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4032630824 Aug 06 07:07:43 PM PDT 24 Aug 06 07:07:48 PM PDT 24 128541871 ps
T331 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2090516746 Aug 06 07:06:46 PM PDT 24 Aug 06 07:06:50 PM PDT 24 171819062 ps
T332 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2249866158 Aug 06 07:07:43 PM PDT 24 Aug 06 07:07:50 PM PDT 24 514963478 ps
T81 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.731892376 Aug 06 07:06:45 PM PDT 24 Aug 06 07:06:49 PM PDT 24 365770662 ps
T56 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3114138939 Aug 06 07:07:42 PM PDT 24 Aug 06 07:07:47 PM PDT 24 520640667 ps
T89 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3495963768 Aug 06 07:06:47 PM PDT 24 Aug 06 07:06:52 PM PDT 24 541610377 ps
T333 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.938235879 Aug 06 07:07:43 PM PDT 24 Aug 06 07:07:49 PM PDT 24 135088690 ps
T334 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.888037600 Aug 06 07:06:45 PM PDT 24 Aug 06 07:06:53 PM PDT 24 91157452 ps
T335 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2851958751 Aug 06 07:06:54 PM PDT 24 Aug 06 07:06:59 PM PDT 24 104806313 ps
T336 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.355432165 Aug 06 07:06:45 PM PDT 24 Aug 06 07:06:49 PM PDT 24 86270282 ps
T90 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3490793238 Aug 06 07:06:54 PM PDT 24 Aug 06 07:06:59 PM PDT 24 127545814 ps
T82 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.903851331 Aug 06 07:07:22 PM PDT 24 Aug 06 07:07:27 PM PDT 24 523885901 ps
T57 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.646492375 Aug 06 07:07:44 PM PDT 24 Aug 06 07:07:48 PM PDT 24 87390418 ps
T337 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4123026210 Aug 06 07:06:30 PM PDT 24 Aug 06 07:06:39 PM PDT 24 249672755 ps
T338 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3506258970 Aug 06 07:07:10 PM PDT 24 Aug 06 07:07:15 PM PDT 24 103886671 ps
T49 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2621698551 Aug 06 07:07:21 PM PDT 24 Aug 06 07:07:57 PM PDT 24 1744984168 ps
T339 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1505885681 Aug 06 07:06:33 PM PDT 24 Aug 06 07:06:38 PM PDT 24 879029403 ps
T340 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.862464560 Aug 06 07:06:44 PM PDT 24 Aug 06 07:06:52 PM PDT 24 127372576 ps
T91 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3974572049 Aug 06 07:06:47 PM PDT 24 Aug 06 07:06:58 PM PDT 24 512987855 ps
T101 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1931353963 Aug 06 07:07:05 PM PDT 24 Aug 06 07:08:12 PM PDT 24 741589310 ps
T341 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1698044156 Aug 06 07:07:41 PM PDT 24 Aug 06 07:07:49 PM PDT 24 1056462877 ps
T58 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1040632613 Aug 06 07:07:22 PM PDT 24 Aug 06 07:07:41 PM PDT 24 367101616 ps
T59 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3316006910 Aug 06 07:07:10 PM PDT 24 Aug 06 07:07:15 PM PDT 24 400373825 ps
T98 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3932018857 Aug 06 07:06:37 PM PDT 24 Aug 06 07:07:48 PM PDT 24 748346671 ps
T83 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1823505608 Aug 06 07:07:11 PM PDT 24 Aug 06 07:07:16 PM PDT 24 132288765 ps
T60 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.724470478 Aug 06 07:07:09 PM PDT 24 Aug 06 07:07:28 PM PDT 24 383754777 ps
T342 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3057607096 Aug 06 07:07:21 PM PDT 24 Aug 06 07:07:27 PM PDT 24 298472756 ps
T61 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1923051016 Aug 06 07:07:03 PM PDT 24 Aug 06 07:07:08 PM PDT 24 127570079 ps
T105 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3368199101 Aug 06 07:06:45 PM PDT 24 Aug 06 07:07:20 PM PDT 24 1125953133 ps
T343 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.710877216 Aug 06 07:07:06 PM PDT 24 Aug 06 07:07:11 PM PDT 24 172128163 ps
T84 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.518177902 Aug 06 07:06:54 PM PDT 24 Aug 06 07:07:00 PM PDT 24 2062984490 ps
T344 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1642695552 Aug 06 07:06:40 PM PDT 24 Aug 06 07:06:48 PM PDT 24 133455638 ps
T62 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2470475533 Aug 06 07:06:39 PM PDT 24 Aug 06 07:06:44 PM PDT 24 130942836 ps
T85 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3971628852 Aug 06 07:07:04 PM PDT 24 Aug 06 07:07:08 PM PDT 24 292195255 ps
T107 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.644456639 Aug 06 07:07:20 PM PDT 24 Aug 06 07:08:28 PM PDT 24 343585405 ps
T106 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3267578248 Aug 06 07:07:44 PM PDT 24 Aug 06 07:08:21 PM PDT 24 798683504 ps
T345 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3324095307 Aug 06 07:07:20 PM PDT 24 Aug 06 07:07:24 PM PDT 24 90291346 ps
T346 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4060793701 Aug 06 07:07:06 PM PDT 24 Aug 06 07:07:15 PM PDT 24 502479015 ps
T347 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3939906620 Aug 06 07:06:39 PM PDT 24 Aug 06 07:06:48 PM PDT 24 131937053 ps
T348 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2173315364 Aug 06 07:07:03 PM PDT 24 Aug 06 07:07:10 PM PDT 24 117868364 ps
T86 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4231145555 Aug 06 07:07:22 PM PDT 24 Aug 06 07:07:28 PM PDT 24 606283026 ps
T87 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2582842346 Aug 06 07:07:45 PM PDT 24 Aug 06 07:07:53 PM PDT 24 4133853352 ps
T63 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1657658125 Aug 06 07:06:44 PM PDT 24 Aug 06 07:06:50 PM PDT 24 93643502 ps
T349 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4110883362 Aug 06 07:06:46 PM PDT 24 Aug 06 07:06:54 PM PDT 24 140941800 ps
T350 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2888178803 Aug 06 07:07:39 PM PDT 24 Aug 06 07:07:46 PM PDT 24 1542708005 ps
T351 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2050797225 Aug 06 07:07:40 PM PDT 24 Aug 06 07:07:44 PM PDT 24 85489847 ps
T352 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1398239641 Aug 06 07:07:09 PM PDT 24 Aug 06 07:07:16 PM PDT 24 89277525 ps
T64 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3883400252 Aug 06 07:06:44 PM PDT 24 Aug 06 07:07:06 PM PDT 24 530439356 ps
T353 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2965451017 Aug 06 07:07:19 PM PDT 24 Aug 06 07:07:27 PM PDT 24 87555845 ps
T354 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3047772846 Aug 06 07:07:45 PM PDT 24 Aug 06 07:07:51 PM PDT 24 566828228 ps
T65 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.360673756 Aug 06 07:06:46 PM PDT 24 Aug 06 07:06:50 PM PDT 24 1383822797 ps
T102 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2028175806 Aug 06 07:07:41 PM PDT 24 Aug 06 07:08:20 PM PDT 24 245049632 ps
T355 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.302224924 Aug 06 07:07:22 PM PDT 24 Aug 06 07:07:27 PM PDT 24 109931332 ps
T356 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2887783895 Aug 06 07:07:43 PM PDT 24 Aug 06 07:07:49 PM PDT 24 1417346681 ps
T357 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.477343913 Aug 06 07:07:43 PM PDT 24 Aug 06 07:07:48 PM PDT 24 127143830 ps
T358 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3786402156 Aug 06 07:07:05 PM PDT 24 Aug 06 07:07:47 PM PDT 24 435835833 ps
T359 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2012646335 Aug 06 07:07:40 PM PDT 24 Aug 06 07:07:44 PM PDT 24 87869237 ps
T360 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2538091757 Aug 06 07:07:42 PM PDT 24 Aug 06 07:07:51 PM PDT 24 319717863 ps
T361 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1638873380 Aug 06 07:07:41 PM PDT 24 Aug 06 07:08:00 PM PDT 24 384634612 ps
T362 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.551208597 Aug 06 07:07:19 PM PDT 24 Aug 06 07:07:28 PM PDT 24 491932000 ps
T363 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2264269062 Aug 06 07:06:48 PM PDT 24 Aug 06 07:06:52 PM PDT 24 86527777 ps
T364 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1683526984 Aug 06 07:07:40 PM PDT 24 Aug 06 07:07:44 PM PDT 24 85787126 ps
T365 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.263515413 Aug 06 07:06:37 PM PDT 24 Aug 06 07:06:42 PM PDT 24 396726340 ps
T366 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.958467071 Aug 06 07:07:10 PM PDT 24 Aug 06 07:07:14 PM PDT 24 175294451 ps
T367 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3950683955 Aug 06 07:07:40 PM PDT 24 Aug 06 07:07:45 PM PDT 24 190213973 ps
T74 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2461370849 Aug 06 07:07:10 PM PDT 24 Aug 06 07:07:16 PM PDT 24 891394299 ps
T103 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.499792196 Aug 06 07:06:46 PM PDT 24 Aug 06 07:07:54 PM PDT 24 1138316173 ps
T368 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1795873199 Aug 06 07:07:08 PM PDT 24 Aug 06 07:07:13 PM PDT 24 518935508 ps
T75 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2482314623 Aug 06 07:07:04 PM PDT 24 Aug 06 07:07:22 PM PDT 24 1499425276 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.908146156 Aug 06 07:06:30 PM PDT 24 Aug 06 07:06:35 PM PDT 24 127289582 ps
T370 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2164718786 Aug 06 07:07:18 PM PDT 24 Aug 06 07:07:55 PM PDT 24 649228047 ps
T96 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3940033635 Aug 06 07:07:21 PM PDT 24 Aug 06 07:07:48 PM PDT 24 2361743470 ps
T371 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1306153359 Aug 06 07:07:23 PM PDT 24 Aug 06 07:07:27 PM PDT 24 520254352 ps
T76 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3038799488 Aug 06 07:07:05 PM PDT 24 Aug 06 07:07:10 PM PDT 24 265233653 ps
T372 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3302755151 Aug 06 07:07:21 PM PDT 24 Aug 06 07:07:27 PM PDT 24 86584267 ps
T77 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2820335644 Aug 06 07:07:41 PM PDT 24 Aug 06 07:07:49 PM PDT 24 1987664231 ps
T78 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3402817742 Aug 06 07:07:27 PM PDT 24 Aug 06 07:07:31 PM PDT 24 90648076 ps
T373 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.618889559 Aug 06 07:07:41 PM PDT 24 Aug 06 07:07:45 PM PDT 24 638149794 ps
T374 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2223904849 Aug 06 07:07:40 PM PDT 24 Aug 06 07:07:48 PM PDT 24 181962529 ps
T375 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3960910093 Aug 06 07:07:05 PM PDT 24 Aug 06 07:07:11 PM PDT 24 893179651 ps
T376 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.432193055 Aug 06 07:06:48 PM PDT 24 Aug 06 07:06:53 PM PDT 24 518306557 ps
T377 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3764757393 Aug 06 07:07:45 PM PDT 24 Aug 06 07:07:51 PM PDT 24 263286446 ps
T378 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1198912199 Aug 06 07:07:41 PM PDT 24 Aug 06 07:07:46 PM PDT 24 148004224 ps
T379 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3324949171 Aug 06 07:07:43 PM PDT 24 Aug 06 07:07:49 PM PDT 24 128634124 ps
T380 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4089907862 Aug 06 07:07:45 PM PDT 24 Aug 06 07:07:50 PM PDT 24 1770400392 ps
T381 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1578486010 Aug 06 07:07:44 PM PDT 24 Aug 06 07:07:53 PM PDT 24 660694322 ps
T382 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4033324036 Aug 06 07:07:20 PM PDT 24 Aug 06 07:07:24 PM PDT 24 518839333 ps
T383 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3863752472 Aug 06 07:07:43 PM PDT 24 Aug 06 07:07:47 PM PDT 24 176066180 ps
T384 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3687461954 Aug 06 07:07:42 PM PDT 24 Aug 06 07:07:49 PM PDT 24 520006662 ps
T385 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.484540106 Aug 06 07:07:04 PM PDT 24 Aug 06 07:07:15 PM PDT 24 495584161 ps
T386 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.697652097 Aug 06 07:07:05 PM PDT 24 Aug 06 07:07:09 PM PDT 24 89388239 ps
T104 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1476164974 Aug 06 07:07:42 PM PDT 24 Aug 06 07:08:53 PM PDT 24 345952768 ps
T387 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2409602300 Aug 06 07:07:03 PM PDT 24 Aug 06 07:07:08 PM PDT 24 439390499 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.173214315 Aug 06 07:06:44 PM PDT 24 Aug 06 07:06:49 PM PDT 24 362686750 ps
T389 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2473736449 Aug 06 07:07:42 PM PDT 24 Aug 06 07:07:47 PM PDT 24 103023426 ps
T390 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.770167466 Aug 06 07:07:41 PM PDT 24 Aug 06 07:07:47 PM PDT 24 144930904 ps
T391 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4153087978 Aug 06 07:07:42 PM PDT 24 Aug 06 07:07:47 PM PDT 24 341735923 ps
T99 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1771217345 Aug 06 07:06:30 PM PDT 24 Aug 06 07:07:38 PM PDT 24 946336354 ps
T392 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.572851079 Aug 06 07:06:47 PM PDT 24 Aug 06 07:06:52 PM PDT 24 175467320 ps
T393 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3872976579 Aug 06 07:07:19 PM PDT 24 Aug 06 07:07:26 PM PDT 24 130335459 ps
T394 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2829227378 Aug 06 07:06:39 PM PDT 24 Aug 06 07:06:44 PM PDT 24 337070351 ps
T108 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.716733497 Aug 06 07:07:42 PM PDT 24 Aug 06 07:08:51 PM PDT 24 515467831 ps
T395 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1546740970 Aug 06 07:07:19 PM PDT 24 Aug 06 07:07:24 PM PDT 24 575000185 ps
T396 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2701013233 Aug 06 07:07:04 PM PDT 24 Aug 06 07:07:41 PM PDT 24 392973400 ps
T397 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.41857732 Aug 06 07:06:47 PM PDT 24 Aug 06 07:06:55 PM PDT 24 171887929 ps
T100 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2831099151 Aug 06 07:07:42 PM PDT 24 Aug 06 07:08:19 PM PDT 24 288939364 ps
T398 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.220208526 Aug 06 07:07:11 PM PDT 24 Aug 06 07:07:17 PM PDT 24 581754192 ps
T399 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3699194655 Aug 06 07:07:22 PM PDT 24 Aug 06 07:07:28 PM PDT 24 127188557 ps
T80 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2595096519 Aug 06 07:06:47 PM PDT 24 Aug 06 07:06:52 PM PDT 24 130564397 ps
T400 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4233844561 Aug 06 07:06:46 PM PDT 24 Aug 06 07:06:51 PM PDT 24 127624781 ps
T401 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2450473656 Aug 06 07:06:30 PM PDT 24 Aug 06 07:06:35 PM PDT 24 423699982 ps
T402 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1236243689 Aug 06 07:06:46 PM PDT 24 Aug 06 07:06:50 PM PDT 24 87515644 ps
T403 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.328152405 Aug 06 07:06:40 PM PDT 24 Aug 06 07:06:45 PM PDT 24 592766208 ps
T404 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.142633489 Aug 06 07:06:54 PM PDT 24 Aug 06 07:08:03 PM PDT 24 304466426 ps
T405 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1906839220 Aug 06 07:07:19 PM PDT 24 Aug 06 07:08:27 PM PDT 24 848245627 ps
T406 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1048588793 Aug 06 07:07:20 PM PDT 24 Aug 06 07:07:25 PM PDT 24 131068430 ps
T79 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2137494122 Aug 06 07:06:35 PM PDT 24 Aug 06 07:06:40 PM PDT 24 250677898 ps
T407 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1659451897 Aug 06 07:06:54 PM PDT 24 Aug 06 07:06:59 PM PDT 24 369131885 ps
T408 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3281709438 Aug 06 07:07:11 PM PDT 24 Aug 06 07:07:15 PM PDT 24 173823598 ps
T409 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1277602953 Aug 06 07:06:39 PM PDT 24 Aug 06 07:06:43 PM PDT 24 86650695 ps
T410 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.869565843 Aug 06 07:07:42 PM PDT 24 Aug 06 07:07:54 PM PDT 24 182098940 ps
T411 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1348173191 Aug 06 07:06:46 PM PDT 24 Aug 06 07:06:52 PM PDT 24 129722980 ps
T412 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3896992918 Aug 06 07:06:46 PM PDT 24 Aug 06 07:06:50 PM PDT 24 332532284 ps
T109 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.233985340 Aug 06 07:07:40 PM PDT 24 Aug 06 07:08:48 PM PDT 24 1993206898 ps
T413 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1377474877 Aug 06 07:06:48 PM PDT 24 Aug 06 07:06:57 PM PDT 24 536648100 ps
T414 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.274694580 Aug 06 07:07:20 PM PDT 24 Aug 06 07:07:25 PM PDT 24 187229316 ps

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3744848827
Short name T7
Test name
Test status
Simulation time 32086584449 ps
CPU time 306.29 seconds
Started Aug 06 06:23:17 PM PDT 24
Finished Aug 06 06:28:23 PM PDT 24
Peak memory 233572 kb
Host smart-005b1631-06a5-4736-87fa-5f059b9c8c09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744848827 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.3744848827
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1657494701
Short name T3
Test name
Test status
Simulation time 32538598136 ps
CPU time 160.28 seconds
Started Aug 06 06:21:02 PM PDT 24
Finished Aug 06 06:23:42 PM PDT 24
Peak memory 238516 kb
Host smart-f6d5e2cc-65e3-4242-bac3-a3c576826797
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657494701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1657494701
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3239459419
Short name T36
Test name
Test status
Simulation time 12364248700 ps
CPU time 100.79 seconds
Started Aug 06 06:22:31 PM PDT 24
Finished Aug 06 06:24:12 PM PDT 24
Peak memory 234948 kb
Host smart-a596637d-da31-4518-a68e-ad4ec7a2fd69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239459419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3239459419
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4025328719
Short name T47
Test name
Test status
Simulation time 1169575426 ps
CPU time 69.3 seconds
Started Aug 06 07:07:43 PM PDT 24
Finished Aug 06 07:08:52 PM PDT 24
Peak memory 213048 kb
Host smart-67671c05-4579-4f19-95df-c5d661297ece
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025328719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.4025328719
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2454790899
Short name T15
Test name
Test status
Simulation time 410364328 ps
CPU time 13.82 seconds
Started Aug 06 06:24:09 PM PDT 24
Finished Aug 06 06:24:23 PM PDT 24
Peak memory 215324 kb
Host smart-6ec86401-2f45-42b8-890c-cc53e8409702
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454790899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2454790899
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2299664478
Short name T22
Test name
Test status
Simulation time 327543041 ps
CPU time 101.43 seconds
Started Aug 06 06:19:54 PM PDT 24
Finished Aug 06 06:21:36 PM PDT 24
Peak memory 237380 kb
Host smart-823a7324-76c8-4ede-8153-8e1d83535637
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299664478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2299664478
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3114138939
Short name T56
Test name
Test status
Simulation time 520640667 ps
CPU time 4.95 seconds
Started Aug 06 07:07:42 PM PDT 24
Finished Aug 06 07:07:47 PM PDT 24
Peak memory 211316 kb
Host smart-6aca0c5d-55e7-449b-9353-3b55c0a76bd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114138939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3114138939
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1771217345
Short name T99
Test name
Test status
Simulation time 946336354 ps
CPU time 67.25 seconds
Started Aug 06 07:06:30 PM PDT 24
Finished Aug 06 07:07:38 PM PDT 24
Peak memory 212968 kb
Host smart-3c664ea0-d99e-406e-90ad-697c8116eb9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771217345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1771217345
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.499792196
Short name T103
Test name
Test status
Simulation time 1138316173 ps
CPU time 67.64 seconds
Started Aug 06 07:06:46 PM PDT 24
Finished Aug 06 07:07:54 PM PDT 24
Peak memory 219460 kb
Host smart-eef6cc11-3adb-4f89-9c29-c9b32a4ea830
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499792196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.499792196
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3609386287
Short name T114
Test name
Test status
Simulation time 498004119 ps
CPU time 4.98 seconds
Started Aug 06 06:19:26 PM PDT 24
Finished Aug 06 06:19:31 PM PDT 24
Peak memory 211972 kb
Host smart-3c4885cc-f61f-491a-9d75-e867ed3678c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609386287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3609386287
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2956144372
Short name T110
Test name
Test status
Simulation time 3327449026 ps
CPU time 137.91 seconds
Started Aug 06 06:19:55 PM PDT 24
Finished Aug 06 06:22:13 PM PDT 24
Peak memory 241516 kb
Host smart-c0b5d658-cd14-4690-b87c-7a48abf94424
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956144372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2956144372
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2960017446
Short name T55
Test name
Test status
Simulation time 698611159 ps
CPU time 9.49 seconds
Started Aug 06 06:19:27 PM PDT 24
Finished Aug 06 06:19:37 PM PDT 24
Peak memory 212880 kb
Host smart-018eb9dd-9ce7-4f96-b1d8-c49867252f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960017446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2960017446
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.724490472
Short name T199
Test name
Test status
Simulation time 555550669 ps
CPU time 9.32 seconds
Started Aug 06 06:20:51 PM PDT 24
Finished Aug 06 06:21:01 PM PDT 24
Peak memory 213048 kb
Host smart-a56d5592-3ebe-4238-be3f-20ce4799a7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724490472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.724490472
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.502304385
Short name T94
Test name
Test status
Simulation time 106948238611 ps
CPU time 6552.88 seconds
Started Aug 06 06:22:30 PM PDT 24
Finished Aug 06 08:11:43 PM PDT 24
Peak memory 236684 kb
Host smart-5c24768e-5bf5-47cd-bea4-cd5d76ae4e8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502304385 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.502304385
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.202449858
Short name T6
Test name
Test status
Simulation time 1056152582 ps
CPU time 8.57 seconds
Started Aug 06 06:22:31 PM PDT 24
Finished Aug 06 06:22:39 PM PDT 24
Peak memory 212160 kb
Host smart-753a885f-0f94-4b13-a5e0-5a9fe7451f8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=202449858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.202449858
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2414580917
Short name T97
Test name
Test status
Simulation time 234849544403 ps
CPU time 2399.83 seconds
Started Aug 06 06:22:18 PM PDT 24
Finished Aug 06 07:02:18 PM PDT 24
Peak memory 245992 kb
Host smart-1421e12f-7563-406b-b0d2-1495ef388bb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414580917 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2414580917
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1069024897
Short name T14
Test name
Test status
Simulation time 68726982255 ps
CPU time 1308.12 seconds
Started Aug 06 06:20:08 PM PDT 24
Finished Aug 06 06:41:57 PM PDT 24
Peak memory 236632 kb
Host smart-905edd00-d0db-4e31-9799-188a3e88dbda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069024897 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1069024897
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.816277977
Short name T4
Test name
Test status
Simulation time 1443825460 ps
CPU time 10.99 seconds
Started Aug 06 06:20:52 PM PDT 24
Finished Aug 06 06:21:03 PM PDT 24
Peak memory 214708 kb
Host smart-e01ba07e-f56d-4022-a6e4-d6b9ffd53187
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816277977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.816277977
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2137494122
Short name T79
Test name
Test status
Simulation time 250677898 ps
CPU time 4.95 seconds
Started Aug 06 07:06:35 PM PDT 24
Finished Aug 06 07:06:40 PM PDT 24
Peak memory 217836 kb
Host smart-b3656959-3a50-4fc1-990a-57144231b2dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137494122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2137494122
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1277602953
Short name T409
Test name
Test status
Simulation time 86650695 ps
CPU time 4.59 seconds
Started Aug 06 07:06:39 PM PDT 24
Finished Aug 06 07:06:43 PM PDT 24
Peak memory 211284 kb
Host smart-b3eb1801-36ec-4011-b15d-8d65cc49181f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277602953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1277602953
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3939906620
Short name T347
Test name
Test status
Simulation time 131937053 ps
CPU time 8.12 seconds
Started Aug 06 07:06:39 PM PDT 24
Finished Aug 06 07:06:48 PM PDT 24
Peak memory 211252 kb
Host smart-a3a27c32-14e3-46dd-87df-5bb7fdad2dd0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939906620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3939906620
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2450473656
Short name T401
Test name
Test status
Simulation time 423699982 ps
CPU time 4.98 seconds
Started Aug 06 07:06:30 PM PDT 24
Finished Aug 06 07:06:35 PM PDT 24
Peak memory 216216 kb
Host smart-e143d56f-2fa3-4a4e-9034-29387e8deb8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450473656 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2450473656
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.328152405
Short name T403
Test name
Test status
Simulation time 592766208 ps
CPU time 5.01 seconds
Started Aug 06 07:06:40 PM PDT 24
Finished Aug 06 07:06:45 PM PDT 24
Peak memory 211288 kb
Host smart-b4a09242-d6e0-425f-b545-023e2816bbb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328152405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.328152405
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.908146156
Short name T369
Test name
Test status
Simulation time 127289582 ps
CPU time 4.83 seconds
Started Aug 06 07:06:30 PM PDT 24
Finished Aug 06 07:06:35 PM PDT 24
Peak memory 211208 kb
Host smart-30c49379-03a7-44fd-8593-33e0ed00148d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908146156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.908146156
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2829227378
Short name T394
Test name
Test status
Simulation time 337070351 ps
CPU time 4.12 seconds
Started Aug 06 07:06:39 PM PDT 24
Finished Aug 06 07:06:44 PM PDT 24
Peak memory 211216 kb
Host smart-fa919835-0026-40ed-8114-3fa9e05198f0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829227378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2829227378
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2470475533
Short name T62
Test name
Test status
Simulation time 130942836 ps
CPU time 5.11 seconds
Started Aug 06 07:06:39 PM PDT 24
Finished Aug 06 07:06:44 PM PDT 24
Peak memory 211352 kb
Host smart-55989051-0e19-4643-9293-49a49aaa0ff5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470475533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2470475533
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4123026210
Short name T337
Test name
Test status
Simulation time 249672755 ps
CPU time 8.56 seconds
Started Aug 06 07:06:30 PM PDT 24
Finished Aug 06 07:06:39 PM PDT 24
Peak memory 216572 kb
Host smart-a29e1061-2d43-413d-8ec2-b951eabac7ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123026210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.4123026210
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.360673756
Short name T65
Test name
Test status
Simulation time 1383822797 ps
CPU time 4.18 seconds
Started Aug 06 07:06:46 PM PDT 24
Finished Aug 06 07:06:50 PM PDT 24
Peak memory 218348 kb
Host smart-003af8f9-4a1f-450b-8dde-c86b1e4ec7f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360673756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.360673756
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3495963768
Short name T89
Test name
Test status
Simulation time 541610377 ps
CPU time 5.28 seconds
Started Aug 06 07:06:47 PM PDT 24
Finished Aug 06 07:06:52 PM PDT 24
Peak memory 218112 kb
Host smart-752296da-4442-47e3-bc3d-f9e316715bbd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495963768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3495963768
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3974572049
Short name T91
Test name
Test status
Simulation time 512987855 ps
CPU time 10.57 seconds
Started Aug 06 07:06:47 PM PDT 24
Finished Aug 06 07:06:58 PM PDT 24
Peak memory 218808 kb
Host smart-a34c92dc-66b7-4439-a177-08b3715a87b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974572049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3974572049
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1659451897
Short name T407
Test name
Test status
Simulation time 369131885 ps
CPU time 5.18 seconds
Started Aug 06 07:06:54 PM PDT 24
Finished Aug 06 07:06:59 PM PDT 24
Peak memory 215948 kb
Host smart-aa74d3e6-8275-4ad0-b0bd-9a7a26f87b45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659451897 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1659451897
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4233844561
Short name T400
Test name
Test status
Simulation time 127624781 ps
CPU time 4.94 seconds
Started Aug 06 07:06:46 PM PDT 24
Finished Aug 06 07:06:51 PM PDT 24
Peak memory 211256 kb
Host smart-09ac3c44-f453-45b0-8dd4-53305edd67c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233844561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4233844561
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.263515413
Short name T365
Test name
Test status
Simulation time 396726340 ps
CPU time 4.37 seconds
Started Aug 06 07:06:37 PM PDT 24
Finished Aug 06 07:06:42 PM PDT 24
Peak memory 211192 kb
Host smart-ea3bde3b-f7e2-4bbe-aff5-d4ab6277049b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263515413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.263515413
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1505885681
Short name T339
Test name
Test status
Simulation time 879029403 ps
CPU time 4.94 seconds
Started Aug 06 07:06:33 PM PDT 24
Finished Aug 06 07:06:38 PM PDT 24
Peak memory 211156 kb
Host smart-99ba184a-15e3-48d4-95cd-91fa2040e667
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505885681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1505885681
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.731892376
Short name T81
Test name
Test status
Simulation time 365770662 ps
CPU time 4.24 seconds
Started Aug 06 07:06:45 PM PDT 24
Finished Aug 06 07:06:49 PM PDT 24
Peak memory 211256 kb
Host smart-0dff4dbf-ddc1-4af8-89f3-628c23bcfc01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731892376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.731892376
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1642695552
Short name T344
Test name
Test status
Simulation time 133455638 ps
CPU time 7.64 seconds
Started Aug 06 07:06:40 PM PDT 24
Finished Aug 06 07:06:48 PM PDT 24
Peak memory 219632 kb
Host smart-78d85779-3d2f-41f8-b2ab-4c77640a7efa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642695552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1642695552
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3932018857
Short name T98
Test name
Test status
Simulation time 748346671 ps
CPU time 70.54 seconds
Started Aug 06 07:06:37 PM PDT 24
Finished Aug 06 07:07:48 PM PDT 24
Peak memory 213008 kb
Host smart-53a1cd8d-3b6a-4e73-b277-d60f112f419d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932018857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3932018857
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.274694580
Short name T414
Test name
Test status
Simulation time 187229316 ps
CPU time 5.08 seconds
Started Aug 06 07:07:20 PM PDT 24
Finished Aug 06 07:07:25 PM PDT 24
Peak memory 215844 kb
Host smart-59458982-3110-49bf-8da9-a334f15ac02b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274694580 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.274694580
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.903851331
Short name T82
Test name
Test status
Simulation time 523885901 ps
CPU time 4.98 seconds
Started Aug 06 07:07:22 PM PDT 24
Finished Aug 06 07:07:27 PM PDT 24
Peak memory 218236 kb
Host smart-ad301d0e-a9fb-4d82-9196-3297d0a784f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903851331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.903851331
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3940033635
Short name T96
Test name
Test status
Simulation time 2361743470 ps
CPU time 27.44 seconds
Started Aug 06 07:07:21 PM PDT 24
Finished Aug 06 07:07:48 PM PDT 24
Peak memory 211476 kb
Host smart-76b9d9d8-93ee-456c-822e-43516b11a01e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940033635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3940033635
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4033324036
Short name T382
Test name
Test status
Simulation time 518839333 ps
CPU time 4.37 seconds
Started Aug 06 07:07:20 PM PDT 24
Finished Aug 06 07:07:24 PM PDT 24
Peak memory 211324 kb
Host smart-bfd11f57-2cc7-4114-ac7a-136426f93670
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033324036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.4033324036
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3872976579
Short name T393
Test name
Test status
Simulation time 130335459 ps
CPU time 7.29 seconds
Started Aug 06 07:07:19 PM PDT 24
Finished Aug 06 07:07:26 PM PDT 24
Peak memory 216056 kb
Host smart-ad953674-4676-4af4-96fb-540bde209d87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872976579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3872976579
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2164718786
Short name T370
Test name
Test status
Simulation time 649228047 ps
CPU time 36.63 seconds
Started Aug 06 07:07:18 PM PDT 24
Finished Aug 06 07:07:55 PM PDT 24
Peak memory 211992 kb
Host smart-e51ffd99-4aca-48ef-a37b-3c525caaea19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164718786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2164718786
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2473736449
Short name T389
Test name
Test status
Simulation time 103023426 ps
CPU time 5.05 seconds
Started Aug 06 07:07:42 PM PDT 24
Finished Aug 06 07:07:47 PM PDT 24
Peak memory 215924 kb
Host smart-de32a30b-6878-4677-933d-b0fac80fc5a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473736449 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2473736449
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3402817742
Short name T78
Test name
Test status
Simulation time 90648076 ps
CPU time 4.31 seconds
Started Aug 06 07:07:27 PM PDT 24
Finished Aug 06 07:07:31 PM PDT 24
Peak memory 211276 kb
Host smart-50d6ea03-ae9c-4ddc-b660-7e7f4a6688f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402817742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3402817742
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3699194655
Short name T399
Test name
Test status
Simulation time 127188557 ps
CPU time 5.15 seconds
Started Aug 06 07:07:22 PM PDT 24
Finished Aug 06 07:07:28 PM PDT 24
Peak memory 218800 kb
Host smart-a5583c3b-c178-4e30-8001-4fef4c5c0c7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699194655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3699194655
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2965451017
Short name T353
Test name
Test status
Simulation time 87555845 ps
CPU time 7.57 seconds
Started Aug 06 07:07:19 PM PDT 24
Finished Aug 06 07:07:27 PM PDT 24
Peak memory 216508 kb
Host smart-ec4833b5-cc47-4022-8bdd-231d3e3a5c09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965451017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2965451017
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1906839220
Short name T405
Test name
Test status
Simulation time 848245627 ps
CPU time 67.85 seconds
Started Aug 06 07:07:19 PM PDT 24
Finished Aug 06 07:08:27 PM PDT 24
Peak memory 213196 kb
Host smart-96a4f127-2c5a-4a72-b77f-cabb9fe70400
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906839220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1906839220
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2888178803
Short name T350
Test name
Test status
Simulation time 1542708005 ps
CPU time 5.95 seconds
Started Aug 06 07:07:39 PM PDT 24
Finished Aug 06 07:07:46 PM PDT 24
Peak memory 215124 kb
Host smart-d178397f-019f-471e-9a03-129bda72aba6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888178803 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2888178803
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2012646335
Short name T359
Test name
Test status
Simulation time 87869237 ps
CPU time 4.19 seconds
Started Aug 06 07:07:40 PM PDT 24
Finished Aug 06 07:07:44 PM PDT 24
Peak memory 211280 kb
Host smart-3712aa47-f400-425d-99ef-3515e908ce41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012646335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2012646335
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3324949171
Short name T379
Test name
Test status
Simulation time 128634124 ps
CPU time 5.26 seconds
Started Aug 06 07:07:43 PM PDT 24
Finished Aug 06 07:07:49 PM PDT 24
Peak memory 211332 kb
Host smart-04480957-d947-4440-b226-d88f0805f639
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324949171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3324949171
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1011913550
Short name T330
Test name
Test status
Simulation time 171505540 ps
CPU time 6.7 seconds
Started Aug 06 07:07:41 PM PDT 24
Finished Aug 06 07:07:48 PM PDT 24
Peak memory 219640 kb
Host smart-b0bd3b82-99e9-412b-bb01-6c9618b34c85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011913550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1011913550
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3267578248
Short name T106
Test name
Test status
Simulation time 798683504 ps
CPU time 37.54 seconds
Started Aug 06 07:07:44 PM PDT 24
Finished Aug 06 07:08:21 PM PDT 24
Peak memory 211264 kb
Host smart-abf77038-b94e-453a-8537-2ae8b08cd454
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267578248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3267578248
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.878068148
Short name T51
Test name
Test status
Simulation time 96022890 ps
CPU time 5.06 seconds
Started Aug 06 07:07:43 PM PDT 24
Finished Aug 06 07:07:49 PM PDT 24
Peak memory 219544 kb
Host smart-1b8ce30f-a743-4f7a-89a6-055d42bda8e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878068148 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.878068148
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.646492375
Short name T57
Test name
Test status
Simulation time 87390418 ps
CPU time 4.18 seconds
Started Aug 06 07:07:44 PM PDT 24
Finished Aug 06 07:07:48 PM PDT 24
Peak memory 211244 kb
Host smart-64bb75aa-088f-4d7c-8d04-579201307118
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646492375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.646492375
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1683526984
Short name T364
Test name
Test status
Simulation time 85787126 ps
CPU time 4.31 seconds
Started Aug 06 07:07:40 PM PDT 24
Finished Aug 06 07:07:44 PM PDT 24
Peak memory 218828 kb
Host smart-0071450b-8fb3-4fd5-9f75-5f0cbe02156b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683526984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1683526984
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1578486010
Short name T381
Test name
Test status
Simulation time 660694322 ps
CPU time 9.35 seconds
Started Aug 06 07:07:44 PM PDT 24
Finished Aug 06 07:07:53 PM PDT 24
Peak memory 219004 kb
Host smart-cb0b9460-3661-4343-a025-ef26837055ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578486010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1578486010
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1319888552
Short name T48
Test name
Test status
Simulation time 1030654396 ps
CPU time 68.66 seconds
Started Aug 06 07:07:41 PM PDT 24
Finished Aug 06 07:08:50 PM PDT 24
Peak memory 212828 kb
Host smart-01586cb1-d5dc-42dc-9491-b66b464680f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319888552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1319888552
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3047772846
Short name T354
Test name
Test status
Simulation time 566828228 ps
CPU time 5.8 seconds
Started Aug 06 07:07:45 PM PDT 24
Finished Aug 06 07:07:51 PM PDT 24
Peak memory 215580 kb
Host smart-4308da26-2fff-4a4f-aa21-1907111d69ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047772846 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3047772846
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2820335644
Short name T77
Test name
Test status
Simulation time 1987664231 ps
CPU time 7.37 seconds
Started Aug 06 07:07:41 PM PDT 24
Finished Aug 06 07:07:49 PM PDT 24
Peak memory 211280 kb
Host smart-7182a5d1-418c-4f6c-aa73-90302520a1ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820335644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2820335644
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.618889559
Short name T373
Test name
Test status
Simulation time 638149794 ps
CPU time 4.32 seconds
Started Aug 06 07:07:41 PM PDT 24
Finished Aug 06 07:07:45 PM PDT 24
Peak memory 211344 kb
Host smart-ec93f8f3-7216-40c0-9547-3592c403fc52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618889559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.618889559
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2223904849
Short name T374
Test name
Test status
Simulation time 181962529 ps
CPU time 7.45 seconds
Started Aug 06 07:07:40 PM PDT 24
Finished Aug 06 07:07:48 PM PDT 24
Peak memory 219596 kb
Host smart-3ad44d75-c366-4bb1-b5c9-0002eee3d2be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223904849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2223904849
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2831099151
Short name T100
Test name
Test status
Simulation time 288939364 ps
CPU time 36.54 seconds
Started Aug 06 07:07:42 PM PDT 24
Finished Aug 06 07:08:19 PM PDT 24
Peak memory 212960 kb
Host smart-df51fb23-648c-4067-aee4-83d5dda2c2b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831099151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2831099151
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4153087978
Short name T391
Test name
Test status
Simulation time 341735923 ps
CPU time 5.24 seconds
Started Aug 06 07:07:42 PM PDT 24
Finished Aug 06 07:07:47 PM PDT 24
Peak memory 219544 kb
Host smart-451768e5-abaa-47bc-9acd-1212e16886be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153087978 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.4153087978
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.770167466
Short name T390
Test name
Test status
Simulation time 144930904 ps
CPU time 6.9 seconds
Started Aug 06 07:07:41 PM PDT 24
Finished Aug 06 07:07:47 PM PDT 24
Peak memory 211328 kb
Host smart-8e3123fd-56ae-425d-9265-862ef1f8fe4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770167466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.770167466
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2538091757
Short name T360
Test name
Test status
Simulation time 319717863 ps
CPU time 9.74 seconds
Started Aug 06 07:07:42 PM PDT 24
Finished Aug 06 07:07:51 PM PDT 24
Peak memory 219624 kb
Host smart-0c2143a1-307e-4b06-bba5-62362cd5a2d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538091757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2538091757
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1476164974
Short name T104
Test name
Test status
Simulation time 345952768 ps
CPU time 71.34 seconds
Started Aug 06 07:07:42 PM PDT 24
Finished Aug 06 07:08:53 PM PDT 24
Peak memory 213156 kb
Host smart-17226ae9-dc6b-42bc-80a6-fd5fca85ceb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476164974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1476164974
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3950683955
Short name T367
Test name
Test status
Simulation time 190213973 ps
CPU time 4.85 seconds
Started Aug 06 07:07:40 PM PDT 24
Finished Aug 06 07:07:45 PM PDT 24
Peak memory 215860 kb
Host smart-a8962247-8a0a-4579-9f56-e0a8cff25a76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950683955 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3950683955
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1198912199
Short name T378
Test name
Test status
Simulation time 148004224 ps
CPU time 4.94 seconds
Started Aug 06 07:07:41 PM PDT 24
Finished Aug 06 07:07:46 PM PDT 24
Peak memory 211112 kb
Host smart-7e1ab1db-91c9-46db-8d22-0f83fe2e53b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198912199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1198912199
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2582842346
Short name T87
Test name
Test status
Simulation time 4133853352 ps
CPU time 7.6 seconds
Started Aug 06 07:07:45 PM PDT 24
Finished Aug 06 07:07:53 PM PDT 24
Peak memory 211428 kb
Host smart-5ef3f970-309b-4e1a-9eac-7556ae845fee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582842346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2582842346
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.869565843
Short name T410
Test name
Test status
Simulation time 182098940 ps
CPU time 11.56 seconds
Started Aug 06 07:07:42 PM PDT 24
Finished Aug 06 07:07:54 PM PDT 24
Peak memory 215444 kb
Host smart-06c4cab6-d287-4882-95bd-ade4cafe41f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869565843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.869565843
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.716733497
Short name T108
Test name
Test status
Simulation time 515467831 ps
CPU time 69.19 seconds
Started Aug 06 07:07:42 PM PDT 24
Finished Aug 06 07:08:51 PM PDT 24
Peak memory 213084 kb
Host smart-3663318f-daa0-4b56-bafa-1c2e0a9bf101
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716733497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.716733497
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.938235879
Short name T333
Test name
Test status
Simulation time 135088690 ps
CPU time 5.52 seconds
Started Aug 06 07:07:43 PM PDT 24
Finished Aug 06 07:07:49 PM PDT 24
Peak memory 219584 kb
Host smart-4518fb42-c427-49f7-954d-f69ab989c2a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938235879 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.938235879
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4032630824
Short name T88
Test name
Test status
Simulation time 128541871 ps
CPU time 5.03 seconds
Started Aug 06 07:07:43 PM PDT 24
Finished Aug 06 07:07:48 PM PDT 24
Peak memory 211284 kb
Host smart-dfb2ad95-6fa9-4955-bf15-979870eaeb01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032630824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.4032630824
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1638873380
Short name T361
Test name
Test status
Simulation time 384634612 ps
CPU time 18.08 seconds
Started Aug 06 07:07:41 PM PDT 24
Finished Aug 06 07:08:00 PM PDT 24
Peak memory 211244 kb
Host smart-9d2eae58-0b54-4d18-b649-1f157c79e5d7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638873380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1638873380
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3863752472
Short name T383
Test name
Test status
Simulation time 176066180 ps
CPU time 4.35 seconds
Started Aug 06 07:07:43 PM PDT 24
Finished Aug 06 07:07:47 PM PDT 24
Peak memory 211252 kb
Host smart-ce628437-e2f2-40fb-b85f-cd29eaf79769
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863752472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3863752472
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2249866158
Short name T332
Test name
Test status
Simulation time 514963478 ps
CPU time 7.41 seconds
Started Aug 06 07:07:43 PM PDT 24
Finished Aug 06 07:07:50 PM PDT 24
Peak memory 216652 kb
Host smart-570091a0-44ab-4b17-9e72-2d88110e0bad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249866158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2249866158
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2028175806
Short name T102
Test name
Test status
Simulation time 245049632 ps
CPU time 38.67 seconds
Started Aug 06 07:07:41 PM PDT 24
Finished Aug 06 07:08:20 PM PDT 24
Peak memory 219472 kb
Host smart-a71a1955-aaaf-4945-8d8a-5d29e64907bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028175806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2028175806
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1698044156
Short name T341
Test name
Test status
Simulation time 1056462877 ps
CPU time 8.04 seconds
Started Aug 06 07:07:41 PM PDT 24
Finished Aug 06 07:07:49 PM PDT 24
Peak memory 215064 kb
Host smart-c9165060-addb-4ff0-9e51-286b6e7c9d05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698044156 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1698044156
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2050797225
Short name T351
Test name
Test status
Simulation time 85489847 ps
CPU time 4.31 seconds
Started Aug 06 07:07:40 PM PDT 24
Finished Aug 06 07:07:44 PM PDT 24
Peak memory 211268 kb
Host smart-e674b41a-d7e7-4db7-bef1-0feea31475ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050797225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2050797225
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3764757393
Short name T377
Test name
Test status
Simulation time 263286446 ps
CPU time 6.09 seconds
Started Aug 06 07:07:45 PM PDT 24
Finished Aug 06 07:07:51 PM PDT 24
Peak memory 211324 kb
Host smart-2de6b2d9-0d15-45b0-a298-2fcd6d97eea2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764757393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3764757393
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3687461954
Short name T384
Test name
Test status
Simulation time 520006662 ps
CPU time 6.79 seconds
Started Aug 06 07:07:42 PM PDT 24
Finished Aug 06 07:07:49 PM PDT 24
Peak memory 219628 kb
Host smart-62a52fe0-dff1-4691-a331-fed7dc292407
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687461954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3687461954
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.233985340
Short name T109
Test name
Test status
Simulation time 1993206898 ps
CPU time 67.99 seconds
Started Aug 06 07:07:40 PM PDT 24
Finished Aug 06 07:08:48 PM PDT 24
Peak memory 213000 kb
Host smart-7865160a-01e5-4437-81a9-e2ad77cbb4b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233985340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.233985340
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.747446850
Short name T50
Test name
Test status
Simulation time 166617373 ps
CPU time 4.97 seconds
Started Aug 06 07:07:42 PM PDT 24
Finished Aug 06 07:07:47 PM PDT 24
Peak memory 216436 kb
Host smart-098d9321-80c8-4c4b-82c4-8401d215b7eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747446850 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.747446850
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4089907862
Short name T380
Test name
Test status
Simulation time 1770400392 ps
CPU time 5.08 seconds
Started Aug 06 07:07:45 PM PDT 24
Finished Aug 06 07:07:50 PM PDT 24
Peak memory 211276 kb
Host smart-9d22defb-e505-4f2e-941e-8172a6ce3757
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089907862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.4089907862
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.477343913
Short name T357
Test name
Test status
Simulation time 127143830 ps
CPU time 5.14 seconds
Started Aug 06 07:07:43 PM PDT 24
Finished Aug 06 07:07:48 PM PDT 24
Peak memory 211332 kb
Host smart-143a6ff3-3b3a-4e09-9e54-5d0a006fcc5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477343913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.477343913
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2887783895
Short name T356
Test name
Test status
Simulation time 1417346681 ps
CPU time 6.74 seconds
Started Aug 06 07:07:43 PM PDT 24
Finished Aug 06 07:07:49 PM PDT 24
Peak memory 216216 kb
Host smart-c8548d20-439f-418f-9c9c-4bbe7f5ef298
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887783895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2887783895
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1236243689
Short name T402
Test name
Test status
Simulation time 87515644 ps
CPU time 4.16 seconds
Started Aug 06 07:06:46 PM PDT 24
Finished Aug 06 07:06:50 PM PDT 24
Peak memory 219436 kb
Host smart-c0751d99-5ab7-4418-8790-2ab450617929
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236243689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1236243689
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1348173191
Short name T411
Test name
Test status
Simulation time 129722980 ps
CPU time 5.33 seconds
Started Aug 06 07:06:46 PM PDT 24
Finished Aug 06 07:06:52 PM PDT 24
Peak memory 218108 kb
Host smart-126f34aa-b71e-4a21-9687-70508a4c6830
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348173191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1348173191
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1377474877
Short name T413
Test name
Test status
Simulation time 536648100 ps
CPU time 8.18 seconds
Started Aug 06 07:06:48 PM PDT 24
Finished Aug 06 07:06:57 PM PDT 24
Peak memory 219412 kb
Host smart-fcaa85c2-9b94-4659-9b36-e4c70ce19b8c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377474877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1377474877
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.173214315
Short name T388
Test name
Test status
Simulation time 362686750 ps
CPU time 4.92 seconds
Started Aug 06 07:06:44 PM PDT 24
Finished Aug 06 07:06:49 PM PDT 24
Peak memory 219544 kb
Host smart-917ac4df-0d5a-4cf2-8a7c-678b624d93bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173214315 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.173214315
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.572851079
Short name T392
Test name
Test status
Simulation time 175467320 ps
CPU time 4.05 seconds
Started Aug 06 07:06:47 PM PDT 24
Finished Aug 06 07:06:52 PM PDT 24
Peak memory 219400 kb
Host smart-d19f1de9-52a4-4f47-81cc-39bd2cbecdc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572851079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.572851079
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2264269062
Short name T363
Test name
Test status
Simulation time 86527777 ps
CPU time 4.34 seconds
Started Aug 06 07:06:48 PM PDT 24
Finished Aug 06 07:06:52 PM PDT 24
Peak memory 211232 kb
Host smart-b09e098a-d734-4dd1-a58d-6f2f39411a82
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264269062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2264269062
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3896992918
Short name T412
Test name
Test status
Simulation time 332532284 ps
CPU time 4.1 seconds
Started Aug 06 07:06:46 PM PDT 24
Finished Aug 06 07:06:50 PM PDT 24
Peak memory 211188 kb
Host smart-af36b100-b30d-4b69-a9c2-65d66dde3b92
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896992918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3896992918
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3883400252
Short name T64
Test name
Test status
Simulation time 530439356 ps
CPU time 21.92 seconds
Started Aug 06 07:06:44 PM PDT 24
Finished Aug 06 07:07:06 PM PDT 24
Peak memory 211368 kb
Host smart-44bcdebe-768b-40e8-9411-27e12c20f21c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883400252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3883400252
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1657658125
Short name T63
Test name
Test status
Simulation time 93643502 ps
CPU time 5.82 seconds
Started Aug 06 07:06:44 PM PDT 24
Finished Aug 06 07:06:50 PM PDT 24
Peak memory 211212 kb
Host smart-24fccd83-74e4-4138-8eb8-11cb04da6dac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657658125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1657658125
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.888037600
Short name T334
Test name
Test status
Simulation time 91157452 ps
CPU time 8.05 seconds
Started Aug 06 07:06:45 PM PDT 24
Finished Aug 06 07:06:53 PM PDT 24
Peak memory 219656 kb
Host smart-8391c381-7163-4825-a6bc-e1b36d36a8a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888037600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.888037600
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2595096519
Short name T80
Test name
Test status
Simulation time 130564397 ps
CPU time 5.16 seconds
Started Aug 06 07:06:47 PM PDT 24
Finished Aug 06 07:06:52 PM PDT 24
Peak memory 218212 kb
Host smart-d6095bf5-9960-4d6f-8a2e-34dede2eaeab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595096519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2595096519
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3490793238
Short name T90
Test name
Test status
Simulation time 127545814 ps
CPU time 5.09 seconds
Started Aug 06 07:06:54 PM PDT 24
Finished Aug 06 07:06:59 PM PDT 24
Peak memory 211248 kb
Host smart-b78b9e3c-78ff-428e-ab51-638c635d5d6a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490793238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3490793238
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4110883362
Short name T349
Test name
Test status
Simulation time 140941800 ps
CPU time 8.23 seconds
Started Aug 06 07:06:46 PM PDT 24
Finished Aug 06 07:06:54 PM PDT 24
Peak memory 211248 kb
Host smart-47440151-ffc7-4371-929a-45ab6a71e0cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110883362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.4110883362
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2851958751
Short name T335
Test name
Test status
Simulation time 104806313 ps
CPU time 5.17 seconds
Started Aug 06 07:06:54 PM PDT 24
Finished Aug 06 07:06:59 PM PDT 24
Peak memory 219556 kb
Host smart-9a5d3cb1-3a9e-4b09-bf1a-7afea61dbfeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851958751 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2851958751
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.432193055
Short name T376
Test name
Test status
Simulation time 518306557 ps
CPU time 5.08 seconds
Started Aug 06 07:06:48 PM PDT 24
Finished Aug 06 07:06:53 PM PDT 24
Peak memory 211276 kb
Host smart-81554ec2-7e04-4591-88b5-3e4432657448
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432193055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.432193055
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2090516746
Short name T331
Test name
Test status
Simulation time 171819062 ps
CPU time 4.16 seconds
Started Aug 06 07:06:46 PM PDT 24
Finished Aug 06 07:06:50 PM PDT 24
Peak memory 211180 kb
Host smart-a7a32bd1-1d74-437a-8ce6-fbcaedeac9d3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090516746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2090516746
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.355432165
Short name T336
Test name
Test status
Simulation time 86270282 ps
CPU time 4.01 seconds
Started Aug 06 07:06:45 PM PDT 24
Finished Aug 06 07:06:49 PM PDT 24
Peak memory 211084 kb
Host smart-5fa4814c-7dab-4e6b-b872-14e11e222a50
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355432165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
355432165
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.518177902
Short name T84
Test name
Test status
Simulation time 2062984490 ps
CPU time 5.09 seconds
Started Aug 06 07:06:54 PM PDT 24
Finished Aug 06 07:07:00 PM PDT 24
Peak memory 218684 kb
Host smart-f8287342-2fae-4dad-90b6-3762bf3db16b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518177902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.518177902
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.41857732
Short name T397
Test name
Test status
Simulation time 171887929 ps
CPU time 8.43 seconds
Started Aug 06 07:06:47 PM PDT 24
Finished Aug 06 07:06:55 PM PDT 24
Peak memory 219624 kb
Host smart-5b2163ec-de08-4046-bea3-f8522c76b7b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41857732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.41857732
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3368199101
Short name T105
Test name
Test status
Simulation time 1125953133 ps
CPU time 35.53 seconds
Started Aug 06 07:06:45 PM PDT 24
Finished Aug 06 07:07:20 PM PDT 24
Peak memory 219508 kb
Host smart-53fe4c15-a40c-4a1e-8b29-fe710190b403
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368199101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3368199101
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2461370849
Short name T74
Test name
Test status
Simulation time 891394299 ps
CPU time 5.1 seconds
Started Aug 06 07:07:10 PM PDT 24
Finished Aug 06 07:07:16 PM PDT 24
Peak memory 211196 kb
Host smart-dc1a60ff-23e6-4ea4-81e9-8d0d287f5288
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461370849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2461370849
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.710877216
Short name T343
Test name
Test status
Simulation time 172128163 ps
CPU time 4.49 seconds
Started Aug 06 07:07:06 PM PDT 24
Finished Aug 06 07:07:11 PM PDT 24
Peak memory 211316 kb
Host smart-b922aea6-2afe-4a68-b256-26c1e991e1fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710877216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.710877216
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4060793701
Short name T346
Test name
Test status
Simulation time 502479015 ps
CPU time 8.95 seconds
Started Aug 06 07:07:06 PM PDT 24
Finished Aug 06 07:07:15 PM PDT 24
Peak memory 211316 kb
Host smart-f612dfd2-6a5a-42e5-ba0d-bc2f640e2674
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060793701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4060793701
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3506258970
Short name T338
Test name
Test status
Simulation time 103886671 ps
CPU time 4.73 seconds
Started Aug 06 07:07:10 PM PDT 24
Finished Aug 06 07:07:15 PM PDT 24
Peak memory 219568 kb
Host smart-7850f246-e20b-42f6-b5f6-dc5809059828
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506258970 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3506258970
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1923051016
Short name T61
Test name
Test status
Simulation time 127570079 ps
CPU time 5.07 seconds
Started Aug 06 07:07:03 PM PDT 24
Finished Aug 06 07:07:08 PM PDT 24
Peak memory 211288 kb
Host smart-4fd2020d-3453-4333-9ebf-7d7d9a29a74d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923051016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1923051016
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.958467071
Short name T366
Test name
Test status
Simulation time 175294451 ps
CPU time 4.04 seconds
Started Aug 06 07:07:10 PM PDT 24
Finished Aug 06 07:07:14 PM PDT 24
Peak memory 211212 kb
Host smart-7c63fab5-7b19-472b-87b8-885f4c7472c2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958467071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.958467071
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.697652097
Short name T386
Test name
Test status
Simulation time 89388239 ps
CPU time 4.12 seconds
Started Aug 06 07:07:05 PM PDT 24
Finished Aug 06 07:07:09 PM PDT 24
Peak memory 211152 kb
Host smart-694885d3-1649-4882-8573-e670390d851d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697652097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
697652097
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3971628852
Short name T85
Test name
Test status
Simulation time 292195255 ps
CPU time 4.34 seconds
Started Aug 06 07:07:04 PM PDT 24
Finished Aug 06 07:07:08 PM PDT 24
Peak memory 211352 kb
Host smart-fa358724-477d-4a4e-bf6f-e5d8028da76e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971628852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3971628852
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.862464560
Short name T340
Test name
Test status
Simulation time 127372576 ps
CPU time 7.88 seconds
Started Aug 06 07:06:44 PM PDT 24
Finished Aug 06 07:06:52 PM PDT 24
Peak memory 219640 kb
Host smart-fe1c7140-2891-4353-8ee1-adb0628fc8f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862464560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.862464560
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.142633489
Short name T404
Test name
Test status
Simulation time 304466426 ps
CPU time 68.94 seconds
Started Aug 06 07:06:54 PM PDT 24
Finished Aug 06 07:08:03 PM PDT 24
Peak memory 219484 kb
Host smart-2f99dba7-1d53-4017-8a16-0fe7e706502f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142633489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.142633489
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.220208526
Short name T398
Test name
Test status
Simulation time 581754192 ps
CPU time 5.88 seconds
Started Aug 06 07:07:11 PM PDT 24
Finished Aug 06 07:07:17 PM PDT 24
Peak memory 219472 kb
Host smart-c15a988f-0f17-48a7-a1aa-f0a80df46d26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220208526 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.220208526
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1795873199
Short name T368
Test name
Test status
Simulation time 518935508 ps
CPU time 4.97 seconds
Started Aug 06 07:07:08 PM PDT 24
Finished Aug 06 07:07:13 PM PDT 24
Peak memory 211280 kb
Host smart-dffcf36d-05ed-4a6d-be32-166b5d1fa9c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795873199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1795873199
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3281709438
Short name T408
Test name
Test status
Simulation time 173823598 ps
CPU time 4.32 seconds
Started Aug 06 07:07:11 PM PDT 24
Finished Aug 06 07:07:15 PM PDT 24
Peak memory 219392 kb
Host smart-8572e618-088e-4a86-948a-a247138e233e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281709438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3281709438
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.484540106
Short name T385
Test name
Test status
Simulation time 495584161 ps
CPU time 11.49 seconds
Started Aug 06 07:07:04 PM PDT 24
Finished Aug 06 07:07:15 PM PDT 24
Peak memory 216644 kb
Host smart-be14d10e-3cf5-4380-b272-78a50ab80fc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484540106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.484540106
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2701013233
Short name T396
Test name
Test status
Simulation time 392973400 ps
CPU time 36.85 seconds
Started Aug 06 07:07:04 PM PDT 24
Finished Aug 06 07:07:41 PM PDT 24
Peak memory 211560 kb
Host smart-3199f172-9803-43e3-926f-c18be7c7ea05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701013233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2701013233
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3960910093
Short name T375
Test name
Test status
Simulation time 893179651 ps
CPU time 5.02 seconds
Started Aug 06 07:07:05 PM PDT 24
Finished Aug 06 07:07:11 PM PDT 24
Peak memory 216388 kb
Host smart-1952921b-2ed3-4a1f-97e2-923f38d72273
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960910093 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3960910093
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3316006910
Short name T59
Test name
Test status
Simulation time 400373825 ps
CPU time 4.91 seconds
Started Aug 06 07:07:10 PM PDT 24
Finished Aug 06 07:07:15 PM PDT 24
Peak memory 218296 kb
Host smart-5e566b1f-f5be-483e-b6ba-c425f7fdb96b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316006910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3316006910
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2482314623
Short name T75
Test name
Test status
Simulation time 1499425276 ps
CPU time 18.55 seconds
Started Aug 06 07:07:04 PM PDT 24
Finished Aug 06 07:07:22 PM PDT 24
Peak memory 211368 kb
Host smart-c7765641-84aa-43e5-957d-cce5b6140479
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482314623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2482314623
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2409602300
Short name T387
Test name
Test status
Simulation time 439390499 ps
CPU time 4.38 seconds
Started Aug 06 07:07:03 PM PDT 24
Finished Aug 06 07:07:08 PM PDT 24
Peak memory 211256 kb
Host smart-e21ffd09-224c-478e-ad57-da4cb4c7d600
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409602300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2409602300
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1398239641
Short name T352
Test name
Test status
Simulation time 89277525 ps
CPU time 6.73 seconds
Started Aug 06 07:07:09 PM PDT 24
Finished Aug 06 07:07:16 PM PDT 24
Peak memory 216256 kb
Host smart-872eadfb-92cb-4e84-9a87-db7ab8779805
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398239641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1398239641
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3786402156
Short name T358
Test name
Test status
Simulation time 435835833 ps
CPU time 42.14 seconds
Started Aug 06 07:07:05 PM PDT 24
Finished Aug 06 07:07:47 PM PDT 24
Peak memory 213748 kb
Host smart-3772f31e-663e-411b-a4dc-f98ff07f9728
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786402156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3786402156
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3057607096
Short name T342
Test name
Test status
Simulation time 298472756 ps
CPU time 6.07 seconds
Started Aug 06 07:07:21 PM PDT 24
Finished Aug 06 07:07:27 PM PDT 24
Peak memory 219556 kb
Host smart-44d9c25f-08af-4efa-bc47-c60ac107f68a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057607096 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3057607096
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3038799488
Short name T76
Test name
Test status
Simulation time 265233653 ps
CPU time 5.03 seconds
Started Aug 06 07:07:05 PM PDT 24
Finished Aug 06 07:07:10 PM PDT 24
Peak memory 211284 kb
Host smart-1e14d957-2f1d-4328-9ad4-ac9010285f01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038799488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3038799488
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.724470478
Short name T60
Test name
Test status
Simulation time 383754777 ps
CPU time 18.5 seconds
Started Aug 06 07:07:09 PM PDT 24
Finished Aug 06 07:07:28 PM PDT 24
Peak memory 211376 kb
Host smart-8490b5a0-a101-40bd-963e-8a0937e8d94d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724470478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.724470478
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1823505608
Short name T83
Test name
Test status
Simulation time 132288765 ps
CPU time 5.03 seconds
Started Aug 06 07:07:11 PM PDT 24
Finished Aug 06 07:07:16 PM PDT 24
Peak memory 218420 kb
Host smart-efbb8eaf-906f-42a2-ad29-29edb9ebe7c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823505608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1823505608
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2173315364
Short name T348
Test name
Test status
Simulation time 117868364 ps
CPU time 7.27 seconds
Started Aug 06 07:07:03 PM PDT 24
Finished Aug 06 07:07:10 PM PDT 24
Peak memory 219600 kb
Host smart-cb22addc-c5d2-43aa-a086-fabb98bc1b70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173315364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2173315364
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1931353963
Short name T101
Test name
Test status
Simulation time 741589310 ps
CPU time 67.09 seconds
Started Aug 06 07:07:05 PM PDT 24
Finished Aug 06 07:08:12 PM PDT 24
Peak memory 213112 kb
Host smart-6b5e526e-7dbf-4a60-98d3-b77f6fe1b2c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931353963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1931353963
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1546740970
Short name T395
Test name
Test status
Simulation time 575000185 ps
CPU time 5.04 seconds
Started Aug 06 07:07:19 PM PDT 24
Finished Aug 06 07:07:24 PM PDT 24
Peak memory 212568 kb
Host smart-bf029256-e642-46c6-b0d5-6904b452966e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546740970 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1546740970
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3324095307
Short name T345
Test name
Test status
Simulation time 90291346 ps
CPU time 4.16 seconds
Started Aug 06 07:07:20 PM PDT 24
Finished Aug 06 07:07:24 PM PDT 24
Peak memory 219412 kb
Host smart-c432a25c-c291-4c09-abe2-4f2870e40a14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324095307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3324095307
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4231145555
Short name T86
Test name
Test status
Simulation time 606283026 ps
CPU time 6.04 seconds
Started Aug 06 07:07:22 PM PDT 24
Finished Aug 06 07:07:28 PM PDT 24
Peak memory 211448 kb
Host smart-0dac86b5-82ab-45c7-a135-2e0de4af4e81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231145555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.4231145555
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3302755151
Short name T372
Test name
Test status
Simulation time 86584267 ps
CPU time 6.15 seconds
Started Aug 06 07:07:21 PM PDT 24
Finished Aug 06 07:07:27 PM PDT 24
Peak memory 219608 kb
Host smart-d0a1b3db-1ccd-4a75-9a10-282b335369d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302755151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3302755151
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.644456639
Short name T107
Test name
Test status
Simulation time 343585405 ps
CPU time 67.7 seconds
Started Aug 06 07:07:20 PM PDT 24
Finished Aug 06 07:08:28 PM PDT 24
Peak memory 213208 kb
Host smart-5f101d39-3754-4262-9899-04d17f3dbc0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644456639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.644456639
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.302224924
Short name T355
Test name
Test status
Simulation time 109931332 ps
CPU time 5.39 seconds
Started Aug 06 07:07:22 PM PDT 24
Finished Aug 06 07:07:27 PM PDT 24
Peak memory 216436 kb
Host smart-cd88e2fc-544e-4b94-b408-0a2e502f5ed1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302224924 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.302224924
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1048588793
Short name T406
Test name
Test status
Simulation time 131068430 ps
CPU time 5 seconds
Started Aug 06 07:07:20 PM PDT 24
Finished Aug 06 07:07:25 PM PDT 24
Peak memory 211252 kb
Host smart-e9c949d8-2340-478f-ae4a-591e842f3e2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048588793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1048588793
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1040632613
Short name T58
Test name
Test status
Simulation time 367101616 ps
CPU time 18.88 seconds
Started Aug 06 07:07:22 PM PDT 24
Finished Aug 06 07:07:41 PM PDT 24
Peak memory 211428 kb
Host smart-316a27bf-d401-40cd-ba17-ca29659cd006
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040632613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1040632613
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1306153359
Short name T371
Test name
Test status
Simulation time 520254352 ps
CPU time 4.16 seconds
Started Aug 06 07:07:23 PM PDT 24
Finished Aug 06 07:07:27 PM PDT 24
Peak memory 211340 kb
Host smart-2e29f9cc-0c2b-4009-b314-bccf7fa6d993
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306153359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1306153359
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.551208597
Short name T362
Test name
Test status
Simulation time 491932000 ps
CPU time 8.89 seconds
Started Aug 06 07:07:19 PM PDT 24
Finished Aug 06 07:07:28 PM PDT 24
Peak memory 219660 kb
Host smart-99ebb1fa-bd4f-41f0-a587-25ff6c22e082
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551208597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.551208597
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2621698551
Short name T49
Test name
Test status
Simulation time 1744984168 ps
CPU time 36.29 seconds
Started Aug 06 07:07:21 PM PDT 24
Finished Aug 06 07:07:57 PM PDT 24
Peak memory 219480 kb
Host smart-a6c9fda9-aebb-4924-8f00-6229c1b8c47d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621698551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2621698551
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1490098116
Short name T248
Test name
Test status
Simulation time 3082342550 ps
CPU time 157.28 seconds
Started Aug 06 06:19:27 PM PDT 24
Finished Aug 06 06:22:05 PM PDT 24
Peak memory 228936 kb
Host smart-f0f7ff54-e9ca-4343-890f-82a7b069bfef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490098116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1490098116
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.540632234
Short name T218
Test name
Test status
Simulation time 169186599 ps
CPU time 9.39 seconds
Started Aug 06 06:19:27 PM PDT 24
Finished Aug 06 06:19:36 PM PDT 24
Peak memory 213300 kb
Host smart-43a009eb-4d09-4c70-8396-8a88083eba55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540632234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.540632234
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3647193696
Short name T226
Test name
Test status
Simulation time 285050637 ps
CPU time 6.42 seconds
Started Aug 06 06:19:26 PM PDT 24
Finished Aug 06 06:19:32 PM PDT 24
Peak memory 212120 kb
Host smart-ec55f5f8-56d5-4697-b521-0dc3c815b775
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3647193696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3647193696
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.889094773
Short name T21
Test name
Test status
Simulation time 3503442464 ps
CPU time 51.24 seconds
Started Aug 06 06:19:26 PM PDT 24
Finished Aug 06 06:20:18 PM PDT 24
Peak memory 237504 kb
Host smart-1b5a5cae-5c09-412d-8a13-e179d37456ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889094773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.889094773
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1802913883
Short name T177
Test name
Test status
Simulation time 142481290 ps
CPU time 6.74 seconds
Started Aug 06 06:19:06 PM PDT 24
Finished Aug 06 06:19:13 PM PDT 24
Peak memory 212164 kb
Host smart-a8c1c8bb-899b-4c51-8945-16dcbb9a9b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802913883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1802913883
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.454335146
Short name T72
Test name
Test status
Simulation time 311587227 ps
CPU time 16.44 seconds
Started Aug 06 06:19:06 PM PDT 24
Finished Aug 06 06:19:22 PM PDT 24
Peak memory 214464 kb
Host smart-586cf26c-b466-4ba1-acf9-5453902a23b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454335146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.454335146
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3186844944
Short name T136
Test name
Test status
Simulation time 347859780 ps
CPU time 4.18 seconds
Started Aug 06 06:19:29 PM PDT 24
Finished Aug 06 06:19:34 PM PDT 24
Peak memory 212036 kb
Host smart-d82e7762-3bb8-4647-ab9d-0a9140083b88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186844944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3186844944
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1448764259
Short name T32
Test name
Test status
Simulation time 4092539203 ps
CPU time 63.1 seconds
Started Aug 06 06:19:28 PM PDT 24
Finished Aug 06 06:20:31 PM PDT 24
Peak memory 238516 kb
Host smart-00d3c4ec-b6c2-4337-8aff-ed79a42bcf92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448764259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1448764259
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.977874908
Short name T118
Test name
Test status
Simulation time 266889513 ps
CPU time 6.21 seconds
Started Aug 06 06:19:28 PM PDT 24
Finished Aug 06 06:19:34 PM PDT 24
Peak memory 212156 kb
Host smart-7d7d0575-9cb1-4338-a4f3-d77d133008b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=977874908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.977874908
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3624938096
Short name T27
Test name
Test status
Simulation time 2585226945 ps
CPU time 98.67 seconds
Started Aug 06 06:19:28 PM PDT 24
Finished Aug 06 06:21:06 PM PDT 24
Peak memory 236908 kb
Host smart-eadef313-604a-46f7-9695-ba5626bfd52d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624938096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3624938096
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4113922460
Short name T207
Test name
Test status
Simulation time 192181604 ps
CPU time 5.73 seconds
Started Aug 06 06:19:28 PM PDT 24
Finished Aug 06 06:19:34 PM PDT 24
Peak memory 212156 kb
Host smart-2c3cc64e-aff1-47d9-b618-f04db21d14dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113922460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4113922460
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3474671487
Short name T213
Test name
Test status
Simulation time 938349923 ps
CPU time 10.75 seconds
Started Aug 06 06:19:28 PM PDT 24
Finished Aug 06 06:19:39 PM PDT 24
Peak memory 212108 kb
Host smart-72811eac-4f88-41c0-81eb-d0a7112087f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474671487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3474671487
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.534867833
Short name T44
Test name
Test status
Simulation time 64158873654 ps
CPU time 8465.26 seconds
Started Aug 06 06:19:29 PM PDT 24
Finished Aug 06 08:40:35 PM PDT 24
Peak memory 228480 kb
Host smart-8cfe14f6-3eb4-4e34-b300-17678b28b97c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534867833 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.534867833
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2286930456
Short name T181
Test name
Test status
Simulation time 88263548 ps
CPU time 4.26 seconds
Started Aug 06 06:20:54 PM PDT 24
Finished Aug 06 06:20:59 PM PDT 24
Peak memory 211996 kb
Host smart-63a7ffd2-f756-49ee-a8a9-9657e7359af4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286930456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2286930456
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3154762551
Short name T148
Test name
Test status
Simulation time 4723816959 ps
CPU time 62.22 seconds
Started Aug 06 06:20:54 PM PDT 24
Finished Aug 06 06:21:56 PM PDT 24
Peak memory 240740 kb
Host smart-643470e2-4e32-4099-ac81-d7ee589f2e76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154762551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3154762551
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.487093389
Short name T229
Test name
Test status
Simulation time 518988168 ps
CPU time 10.98 seconds
Started Aug 06 06:20:52 PM PDT 24
Finished Aug 06 06:21:03 PM PDT 24
Peak memory 213232 kb
Host smart-6f125673-06eb-480e-ba89-08b4ae856670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487093389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.487093389
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.841421173
Short name T17
Test name
Test status
Simulation time 640234599 ps
CPU time 6.42 seconds
Started Aug 06 06:20:38 PM PDT 24
Finished Aug 06 06:20:45 PM PDT 24
Peak memory 212136 kb
Host smart-acc5ac4f-09d1-4330-9d9f-a3ad8f9ec929
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=841421173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.841421173
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1617681955
Short name T294
Test name
Test status
Simulation time 571051611 ps
CPU time 16.07 seconds
Started Aug 06 06:20:39 PM PDT 24
Finished Aug 06 06:20:55 PM PDT 24
Peak memory 214968 kb
Host smart-f4abf289-e0b5-4777-b0d4-d3aebbb5a3b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617681955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1617681955
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3724856401
Short name T182
Test name
Test status
Simulation time 127398767991 ps
CPU time 2619.04 seconds
Started Aug 06 06:20:52 PM PDT 24
Finished Aug 06 07:04:32 PM PDT 24
Peak memory 251816 kb
Host smart-9b4f1679-d99b-487d-881d-2b676efd7f3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724856401 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3724856401
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.4004895035
Short name T260
Test name
Test status
Simulation time 574631766 ps
CPU time 5.04 seconds
Started Aug 06 06:21:02 PM PDT 24
Finished Aug 06 06:21:07 PM PDT 24
Peak memory 212044 kb
Host smart-e7f9cf01-4168-401a-9776-c992788767e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004895035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.4004895035
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.891784643
Short name T197
Test name
Test status
Simulation time 6169776864 ps
CPU time 79.73 seconds
Started Aug 06 06:20:54 PM PDT 24
Finished Aug 06 06:22:14 PM PDT 24
Peak memory 238328 kb
Host smart-adeb60f6-b42a-4621-a12d-37814f5ba222
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891784643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.891784643
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2008031599
Short name T251
Test name
Test status
Simulation time 189466271 ps
CPU time 5.45 seconds
Started Aug 06 06:20:52 PM PDT 24
Finished Aug 06 06:20:57 PM PDT 24
Peak memory 212176 kb
Host smart-c2f5268d-5903-4ad2-bf07-7227acbe91b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2008031599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2008031599
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1813973377
Short name T292
Test name
Test status
Simulation time 128999970 ps
CPU time 5.19 seconds
Started Aug 06 06:21:04 PM PDT 24
Finished Aug 06 06:21:09 PM PDT 24
Peak memory 212012 kb
Host smart-d11fb835-ffda-44ca-bdfa-bdd30407d1cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813973377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1813973377
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.915289846
Short name T220
Test name
Test status
Simulation time 990348042 ps
CPU time 15.45 seconds
Started Aug 06 06:21:03 PM PDT 24
Finished Aug 06 06:21:19 PM PDT 24
Peak memory 213056 kb
Host smart-1095aad2-3f14-4643-8184-d5e48ba29282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915289846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.915289846
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3177231075
Short name T116
Test name
Test status
Simulation time 1227588811 ps
CPU time 6.57 seconds
Started Aug 06 06:21:02 PM PDT 24
Finished Aug 06 06:21:09 PM PDT 24
Peak memory 212180 kb
Host smart-f543f5dd-3e14-487b-ae72-f6e3caa4da64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3177231075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3177231075
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1521977294
Short name T215
Test name
Test status
Simulation time 1177064824 ps
CPU time 13.38 seconds
Started Aug 06 06:21:02 PM PDT 24
Finished Aug 06 06:21:15 PM PDT 24
Peak memory 214952 kb
Host smart-9e69717e-f073-4f32-883a-bf52931b1108
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521977294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1521977294
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2899851837
Short name T117
Test name
Test status
Simulation time 251339111 ps
CPU time 5.19 seconds
Started Aug 06 06:21:21 PM PDT 24
Finished Aug 06 06:21:27 PM PDT 24
Peak memory 212060 kb
Host smart-3741963a-77b0-4dc0-a655-04e8a0916825
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899851837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2899851837
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.645951481
Short name T252
Test name
Test status
Simulation time 8397442399 ps
CPU time 98.3 seconds
Started Aug 06 06:21:21 PM PDT 24
Finished Aug 06 06:23:00 PM PDT 24
Peak memory 213460 kb
Host smart-6193b8d2-bb33-41d9-9d46-1b01d8180e32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645951481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.645951481
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2573698748
Short name T217
Test name
Test status
Simulation time 639702526 ps
CPU time 9.54 seconds
Started Aug 06 06:21:21 PM PDT 24
Finished Aug 06 06:21:31 PM PDT 24
Peak memory 213020 kb
Host smart-8297c247-e496-41b5-8e9a-db33bef49cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573698748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2573698748
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1675086342
Short name T112
Test name
Test status
Simulation time 141828459 ps
CPU time 6.59 seconds
Started Aug 06 06:21:21 PM PDT 24
Finished Aug 06 06:21:28 PM PDT 24
Peak memory 212180 kb
Host smart-00ff4108-51a9-4869-a781-8a84c2b6118b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1675086342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1675086342
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2875004368
Short name T185
Test name
Test status
Simulation time 371807949 ps
CPU time 21.69 seconds
Started Aug 06 06:21:21 PM PDT 24
Finished Aug 06 06:21:43 PM PDT 24
Peak memory 215840 kb
Host smart-2a495484-c9c2-48d2-ae63-42ffda9f37bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875004368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2875004368
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.884531589
Short name T144
Test name
Test status
Simulation time 496989949 ps
CPU time 5.18 seconds
Started Aug 06 06:21:23 PM PDT 24
Finished Aug 06 06:21:28 PM PDT 24
Peak memory 212072 kb
Host smart-422e1761-7a70-4c99-b5df-74295cb8a6b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884531589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.884531589
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4277061159
Short name T168
Test name
Test status
Simulation time 1807547964 ps
CPU time 81.91 seconds
Started Aug 06 06:21:21 PM PDT 24
Finished Aug 06 06:22:43 PM PDT 24
Peak memory 213320 kb
Host smart-39108db2-637a-4446-b14f-6b062f8c124a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277061159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.4277061159
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2660912383
Short name T261
Test name
Test status
Simulation time 251402241 ps
CPU time 11.09 seconds
Started Aug 06 06:21:23 PM PDT 24
Finished Aug 06 06:21:35 PM PDT 24
Peak memory 212760 kb
Host smart-b71480ac-5498-426e-aa53-737647bc74a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660912383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2660912383
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1109250478
Short name T208
Test name
Test status
Simulation time 198773986 ps
CPU time 5.63 seconds
Started Aug 06 06:21:22 PM PDT 24
Finished Aug 06 06:21:28 PM PDT 24
Peak memory 212144 kb
Host smart-fc032d03-ef63-4d31-9487-e003a422d128
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1109250478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1109250478
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2892514368
Short name T323
Test name
Test status
Simulation time 179457357 ps
CPU time 13.69 seconds
Started Aug 06 06:21:23 PM PDT 24
Finished Aug 06 06:21:36 PM PDT 24
Peak memory 212104 kb
Host smart-83679bd3-9460-445a-b80a-06188686c367
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892514368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2892514368
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3446787856
Short name T328
Test name
Test status
Simulation time 253782622 ps
CPU time 5.18 seconds
Started Aug 06 06:21:42 PM PDT 24
Finished Aug 06 06:21:47 PM PDT 24
Peak memory 211916 kb
Host smart-e1ae2518-36cc-4e00-83e6-05a63faed287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446787856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3446787856
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.147589216
Short name T33
Test name
Test status
Simulation time 2025563636 ps
CPU time 105.47 seconds
Started Aug 06 06:21:40 PM PDT 24
Finished Aug 06 06:23:25 PM PDT 24
Peak memory 234284 kb
Host smart-62e7dd50-4cec-446a-bdee-ba857cdb9274
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147589216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.147589216
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2619507888
Short name T138
Test name
Test status
Simulation time 497652707 ps
CPU time 11.29 seconds
Started Aug 06 06:21:40 PM PDT 24
Finished Aug 06 06:21:51 PM PDT 24
Peak memory 212844 kb
Host smart-dd80d60f-db73-4b6f-98f2-7e5386ef0d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619507888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2619507888
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3640120919
Short name T200
Test name
Test status
Simulation time 270736453 ps
CPU time 6.54 seconds
Started Aug 06 06:21:21 PM PDT 24
Finished Aug 06 06:21:27 PM PDT 24
Peak memory 212044 kb
Host smart-c46f23f1-81bd-4049-91ac-504904b7ce94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640120919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3640120919
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1652138303
Short name T280
Test name
Test status
Simulation time 12450999741 ps
CPU time 26.94 seconds
Started Aug 06 06:21:23 PM PDT 24
Finished Aug 06 06:21:50 PM PDT 24
Peak memory 220168 kb
Host smart-59ef8baa-5c0c-4ad0-94ac-61991d89c036
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652138303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1652138303
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1982268292
Short name T259
Test name
Test status
Simulation time 86259237 ps
CPU time 4.29 seconds
Started Aug 06 06:21:44 PM PDT 24
Finished Aug 06 06:21:48 PM PDT 24
Peak memory 212072 kb
Host smart-b57be1be-d27a-4b69-9855-e00f132dd548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982268292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1982268292
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.676402564
Short name T34
Test name
Test status
Simulation time 2888200462 ps
CPU time 79.99 seconds
Started Aug 06 06:21:41 PM PDT 24
Finished Aug 06 06:23:01 PM PDT 24
Peak memory 234448 kb
Host smart-72d8793d-b18a-4bd5-b0d9-4f4bb7abed63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676402564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.676402564
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2592438552
Short name T319
Test name
Test status
Simulation time 170245243 ps
CPU time 9.38 seconds
Started Aug 06 06:21:43 PM PDT 24
Finished Aug 06 06:21:53 PM PDT 24
Peak memory 213356 kb
Host smart-872b05b2-5336-48da-866d-12464475718b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592438552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2592438552
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3074445771
Short name T320
Test name
Test status
Simulation time 139083470 ps
CPU time 6.61 seconds
Started Aug 06 06:21:41 PM PDT 24
Finished Aug 06 06:21:47 PM PDT 24
Peak memory 212188 kb
Host smart-fbf2ed6f-e419-4d7c-a316-4aee1670a76f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3074445771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3074445771
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.82347300
Short name T156
Test name
Test status
Simulation time 540197243 ps
CPU time 15.1 seconds
Started Aug 06 06:21:39 PM PDT 24
Finished Aug 06 06:21:54 PM PDT 24
Peak memory 214236 kb
Host smart-3445ce95-720b-42be-b5a8-9ef3b181379a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82347300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 16.rom_ctrl_stress_all.82347300
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1928486734
Short name T276
Test name
Test status
Simulation time 14435834936 ps
CPU time 577.84 seconds
Started Aug 06 06:21:43 PM PDT 24
Finished Aug 06 06:31:21 PM PDT 24
Peak memory 229448 kb
Host smart-4e4cf4ba-dbf7-4fd8-84e1-376c95613bfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928486734 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1928486734
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3267455962
Short name T131
Test name
Test status
Simulation time 127378940 ps
CPU time 5.22 seconds
Started Aug 06 06:21:41 PM PDT 24
Finished Aug 06 06:21:47 PM PDT 24
Peak memory 212040 kb
Host smart-3d2e4c98-2798-4f1b-96d5-cf29db7b3e74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267455962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3267455962
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3623006860
Short name T234
Test name
Test status
Simulation time 8705918889 ps
CPU time 107.03 seconds
Started Aug 06 06:21:41 PM PDT 24
Finished Aug 06 06:23:28 PM PDT 24
Peak memory 238560 kb
Host smart-99ecbbf2-7228-463d-bfec-bdeadeea1e4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623006860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3623006860
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1848801082
Short name T254
Test name
Test status
Simulation time 348076424 ps
CPU time 9.47 seconds
Started Aug 06 06:21:40 PM PDT 24
Finished Aug 06 06:21:49 PM PDT 24
Peak memory 213208 kb
Host smart-d40f53ad-4ac1-439a-88db-136705e352be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848801082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1848801082
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.898083975
Short name T19
Test name
Test status
Simulation time 765789726 ps
CPU time 5.57 seconds
Started Aug 06 06:21:42 PM PDT 24
Finished Aug 06 06:21:48 PM PDT 24
Peak memory 212012 kb
Host smart-eb5e1210-2214-4292-841f-d6534815ef10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=898083975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.898083975
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2523774702
Short name T129
Test name
Test status
Simulation time 105502102 ps
CPU time 5.49 seconds
Started Aug 06 06:21:42 PM PDT 24
Finished Aug 06 06:21:47 PM PDT 24
Peak memory 212028 kb
Host smart-d5f97bcf-a896-4904-8bc1-33782df1dced
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523774702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2523774702
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.186304581
Short name T16
Test name
Test status
Simulation time 1975004454 ps
CPU time 7.46 seconds
Started Aug 06 06:21:53 PM PDT 24
Finished Aug 06 06:22:00 PM PDT 24
Peak memory 212052 kb
Host smart-e5754cfa-4f44-4e75-8b26-0892bc28cb4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186304581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.186304581
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.636395837
Short name T284
Test name
Test status
Simulation time 7953236701 ps
CPU time 199.06 seconds
Started Aug 06 06:21:40 PM PDT 24
Finished Aug 06 06:25:00 PM PDT 24
Peak memory 228912 kb
Host smart-8c209324-4aa0-4060-b6c0-cd2a22d71ed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636395837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.636395837
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.28044647
Short name T223
Test name
Test status
Simulation time 262792389 ps
CPU time 11.51 seconds
Started Aug 06 06:21:56 PM PDT 24
Finished Aug 06 06:22:08 PM PDT 24
Peak memory 212868 kb
Host smart-154eb639-db4b-4cce-a1ad-35f1cc1c1b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28044647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.28044647
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.4197055096
Short name T230
Test name
Test status
Simulation time 143627023 ps
CPU time 6.69 seconds
Started Aug 06 06:21:42 PM PDT 24
Finished Aug 06 06:21:49 PM PDT 24
Peak memory 212124 kb
Host smart-3fb5cf9f-a67c-43b4-9f57-9e9c5450edfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4197055096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.4197055096
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.544122887
Short name T161
Test name
Test status
Simulation time 2001392169 ps
CPU time 10.06 seconds
Started Aug 06 06:21:41 PM PDT 24
Finished Aug 06 06:21:51 PM PDT 24
Peak memory 212088 kb
Host smart-4a71adb1-41f1-4df8-b4b8-082f2a225070
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544122887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.544122887
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.678081582
Short name T95
Test name
Test status
Simulation time 11406411269 ps
CPU time 3704.46 seconds
Started Aug 06 06:21:50 PM PDT 24
Finished Aug 06 07:23:35 PM PDT 24
Peak memory 234600 kb
Host smart-1060098c-53bd-4509-826d-53c481ac88f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678081582 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.678081582
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2220146756
Short name T171
Test name
Test status
Simulation time 351869130 ps
CPU time 4.21 seconds
Started Aug 06 06:21:49 PM PDT 24
Finished Aug 06 06:21:53 PM PDT 24
Peak memory 212044 kb
Host smart-2219e102-d577-4b58-a0a2-27dc8886d303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220146756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2220146756
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1205529000
Short name T203
Test name
Test status
Simulation time 6571330186 ps
CPU time 96.44 seconds
Started Aug 06 06:21:49 PM PDT 24
Finished Aug 06 06:23:26 PM PDT 24
Peak memory 237468 kb
Host smart-68fe9d1f-1969-4240-91a3-762588e56285
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205529000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1205529000
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.388652600
Short name T145
Test name
Test status
Simulation time 923993591 ps
CPU time 11.12 seconds
Started Aug 06 06:21:49 PM PDT 24
Finished Aug 06 06:22:00 PM PDT 24
Peak memory 212900 kb
Host smart-2b0b200a-69d9-4bcc-9358-a2bd3482f2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388652600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.388652600
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1750536150
Short name T143
Test name
Test status
Simulation time 294015653 ps
CPU time 6.56 seconds
Started Aug 06 06:21:49 PM PDT 24
Finished Aug 06 06:21:56 PM PDT 24
Peak memory 212156 kb
Host smart-463fa11f-1c8d-4147-838b-306c45c766f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1750536150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1750536150
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.754586899
Short name T266
Test name
Test status
Simulation time 200695120 ps
CPU time 11.74 seconds
Started Aug 06 06:21:52 PM PDT 24
Finished Aug 06 06:22:04 PM PDT 24
Peak memory 213696 kb
Host smart-a70776d5-589e-478d-883e-a5c4732545db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754586899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.754586899
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2577297045
Short name T180
Test name
Test status
Simulation time 521583363 ps
CPU time 5.19 seconds
Started Aug 06 06:19:44 PM PDT 24
Finished Aug 06 06:19:49 PM PDT 24
Peak memory 212052 kb
Host smart-b741e5b8-2840-47b7-a85f-e5137aa6a351
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577297045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2577297045
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.782770835
Short name T35
Test name
Test status
Simulation time 6773325451 ps
CPU time 91.74 seconds
Started Aug 06 06:19:44 PM PDT 24
Finished Aug 06 06:21:16 PM PDT 24
Peak memory 213344 kb
Host smart-2bae513a-63df-464c-8cda-b474d45fcf87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782770835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.782770835
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1436988154
Short name T20
Test name
Test status
Simulation time 522507004 ps
CPU time 11.29 seconds
Started Aug 06 06:19:45 PM PDT 24
Finished Aug 06 06:19:56 PM PDT 24
Peak memory 212912 kb
Host smart-1aa0ef14-f0ff-4f2a-8db2-ffa1f4d93ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436988154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1436988154
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2538619021
Short name T275
Test name
Test status
Simulation time 474383817 ps
CPU time 6.41 seconds
Started Aug 06 06:19:30 PM PDT 24
Finished Aug 06 06:19:36 PM PDT 24
Peak memory 212140 kb
Host smart-84e3a81b-5f21-48a6-9289-fd56e42f6cc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2538619021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2538619021
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.264609969
Short name T26
Test name
Test status
Simulation time 226773615 ps
CPU time 99.93 seconds
Started Aug 06 06:19:44 PM PDT 24
Finished Aug 06 06:21:24 PM PDT 24
Peak memory 237364 kb
Host smart-6c05dce8-ac21-45a8-864e-504dd58241c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264609969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.264609969
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1652427789
Short name T137
Test name
Test status
Simulation time 359353625 ps
CPU time 5.32 seconds
Started Aug 06 06:19:27 PM PDT 24
Finished Aug 06 06:19:33 PM PDT 24
Peak memory 212168 kb
Host smart-517a8791-d976-457a-b465-c7a0eaae5cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652427789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1652427789
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.665367404
Short name T298
Test name
Test status
Simulation time 212741591 ps
CPU time 11.96 seconds
Started Aug 06 06:19:29 PM PDT 24
Finished Aug 06 06:19:41 PM PDT 24
Peak memory 215756 kb
Host smart-528c3c11-172b-44d7-af4f-4d42a9ef9d14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665367404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.665367404
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2176701748
Short name T2
Test name
Test status
Simulation time 332725134 ps
CPU time 4.24 seconds
Started Aug 06 06:22:03 PM PDT 24
Finished Aug 06 06:22:08 PM PDT 24
Peak memory 212060 kb
Host smart-9fc3f522-8edf-43c2-8c4f-11fbbc2502d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176701748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2176701748
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3802432129
Short name T111
Test name
Test status
Simulation time 3300606839 ps
CPU time 101.9 seconds
Started Aug 06 06:21:51 PM PDT 24
Finished Aug 06 06:23:33 PM PDT 24
Peak memory 239492 kb
Host smart-437cc6c4-d787-4fa0-8fc0-efca33d852a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802432129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3802432129
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1270622800
Short name T268
Test name
Test status
Simulation time 168366882 ps
CPU time 9.54 seconds
Started Aug 06 06:21:50 PM PDT 24
Finished Aug 06 06:22:00 PM PDT 24
Peak memory 212964 kb
Host smart-3eb901d5-a8a7-4075-ae79-f3653478c35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270622800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1270622800
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3656298994
Short name T326
Test name
Test status
Simulation time 559076924 ps
CPU time 6.77 seconds
Started Aug 06 06:21:51 PM PDT 24
Finished Aug 06 06:21:58 PM PDT 24
Peak memory 212108 kb
Host smart-fa5fa853-55f3-4c63-aa9e-60bd9c5e9f28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3656298994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3656298994
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.283836946
Short name T165
Test name
Test status
Simulation time 594792769 ps
CPU time 4.87 seconds
Started Aug 06 06:21:49 PM PDT 24
Finished Aug 06 06:21:54 PM PDT 24
Peak memory 212092 kb
Host smart-4fb39a2f-1a9c-4a85-b811-77af2c2898f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283836946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.283836946
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3356483479
Short name T42
Test name
Test status
Simulation time 15744991850 ps
CPU time 689.93 seconds
Started Aug 06 06:22:06 PM PDT 24
Finished Aug 06 06:33:36 PM PDT 24
Peak memory 236680 kb
Host smart-8acb9a5e-44f6-462a-8eb8-2449780eaad8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356483479 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3356483479
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3273168818
Short name T175
Test name
Test status
Simulation time 94940819 ps
CPU time 4.21 seconds
Started Aug 06 06:22:05 PM PDT 24
Finished Aug 06 06:22:09 PM PDT 24
Peak memory 212028 kb
Host smart-af8cc323-823a-403f-8153-07271ffe832a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273168818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3273168818
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1789292677
Short name T246
Test name
Test status
Simulation time 22383539370 ps
CPU time 136.19 seconds
Started Aug 06 06:22:04 PM PDT 24
Finished Aug 06 06:24:20 PM PDT 24
Peak memory 238440 kb
Host smart-3d5f3b6c-1543-4d47-8d34-c90377ee6b80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789292677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1789292677
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.121058617
Short name T305
Test name
Test status
Simulation time 510239254 ps
CPU time 11.12 seconds
Started Aug 06 06:22:03 PM PDT 24
Finished Aug 06 06:22:14 PM PDT 24
Peak memory 212832 kb
Host smart-d7dfd4d4-fdfd-4fd6-ab18-2db90444e2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121058617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.121058617
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3589495578
Short name T222
Test name
Test status
Simulation time 98505282 ps
CPU time 5.72 seconds
Started Aug 06 06:22:06 PM PDT 24
Finished Aug 06 06:22:12 PM PDT 24
Peak memory 212180 kb
Host smart-db132e02-a2dd-486a-9177-933a48fb7843
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3589495578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3589495578
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2882469029
Short name T317
Test name
Test status
Simulation time 762114546 ps
CPU time 11.88 seconds
Started Aug 06 06:22:03 PM PDT 24
Finished Aug 06 06:22:15 PM PDT 24
Peak memory 214684 kb
Host smart-95e4e7ab-db83-4c86-96eb-bc4fabd2da3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882469029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2882469029
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3172944616
Short name T46
Test name
Test status
Simulation time 249510881205 ps
CPU time 2688.87 seconds
Started Aug 06 06:22:03 PM PDT 24
Finished Aug 06 07:06:52 PM PDT 24
Peak memory 237876 kb
Host smart-c6912060-24a3-4bac-8e5e-caf91b3f40df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172944616 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.3172944616
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.885344134
Short name T162
Test name
Test status
Simulation time 168583742 ps
CPU time 4.31 seconds
Started Aug 06 06:22:21 PM PDT 24
Finished Aug 06 06:22:25 PM PDT 24
Peak memory 211608 kb
Host smart-463f1df9-a138-4ec7-b057-2ca72cff81d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885344134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.885344134
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3270995997
Short name T221
Test name
Test status
Simulation time 1382191056 ps
CPU time 103.42 seconds
Started Aug 06 06:22:17 PM PDT 24
Finished Aug 06 06:24:00 PM PDT 24
Peak memory 238348 kb
Host smart-0e90267b-6a4a-4475-a0d9-e6a43582895e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270995997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3270995997
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1097584770
Short name T290
Test name
Test status
Simulation time 1035690446 ps
CPU time 11.36 seconds
Started Aug 06 06:22:19 PM PDT 24
Finished Aug 06 06:22:31 PM PDT 24
Peak memory 213080 kb
Host smart-6df05b88-8bed-4892-9f91-2bd3064df962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097584770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1097584770
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.4222623373
Short name T210
Test name
Test status
Simulation time 195452074 ps
CPU time 5.13 seconds
Started Aug 06 06:22:16 PM PDT 24
Finished Aug 06 06:22:21 PM PDT 24
Peak memory 212116 kb
Host smart-e7d14e49-4bec-46cc-b71c-e49a3cd1811b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4222623373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.4222623373
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3036496208
Short name T67
Test name
Test status
Simulation time 133024595 ps
CPU time 6.42 seconds
Started Aug 06 06:22:18 PM PDT 24
Finished Aug 06 06:22:25 PM PDT 24
Peak memory 212028 kb
Host smart-1664caf2-eaa8-480b-8d77-d9ad44f0b8c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036496208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3036496208
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.62386265
Short name T178
Test name
Test status
Simulation time 349508080 ps
CPU time 4.24 seconds
Started Aug 06 06:22:21 PM PDT 24
Finished Aug 06 06:22:25 PM PDT 24
Peak memory 211644 kb
Host smart-1f09954c-c2d0-490c-b838-2154f4cf4e3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62386265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.62386265
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1445621415
Short name T5
Test name
Test status
Simulation time 3369195325 ps
CPU time 99.82 seconds
Started Aug 06 06:22:18 PM PDT 24
Finished Aug 06 06:23:58 PM PDT 24
Peak memory 229316 kb
Host smart-a6cea0fc-b40e-4af4-96c7-06a7085b5c45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445621415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1445621415
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1923744725
Short name T115
Test name
Test status
Simulation time 1288866573 ps
CPU time 9.56 seconds
Started Aug 06 06:22:18 PM PDT 24
Finished Aug 06 06:22:27 PM PDT 24
Peak memory 212912 kb
Host smart-d6d96118-cc7b-4e53-a4a5-e99e96312103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923744725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1923744725
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2903888888
Short name T253
Test name
Test status
Simulation time 94521219 ps
CPU time 5.25 seconds
Started Aug 06 06:22:18 PM PDT 24
Finished Aug 06 06:22:24 PM PDT 24
Peak memory 212208 kb
Host smart-5a31aa0e-c6d0-4168-95d7-580f72bddc45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2903888888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2903888888
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.865100671
Short name T240
Test name
Test status
Simulation time 1570969528 ps
CPU time 27.69 seconds
Started Aug 06 06:22:18 PM PDT 24
Finished Aug 06 06:22:46 PM PDT 24
Peak memory 216284 kb
Host smart-f922d485-cc54-4546-99e0-d1b20b3130b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865100671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.865100671
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3630310997
Short name T130
Test name
Test status
Simulation time 445542021 ps
CPU time 5.11 seconds
Started Aug 06 06:22:33 PM PDT 24
Finished Aug 06 06:22:38 PM PDT 24
Peak memory 212036 kb
Host smart-4b1fb09a-da90-457e-8d37-a732ca29ebac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630310997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3630310997
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3547278152
Short name T243
Test name
Test status
Simulation time 2274290105 ps
CPU time 71.13 seconds
Started Aug 06 06:22:30 PM PDT 24
Finished Aug 06 06:23:41 PM PDT 24
Peak memory 234404 kb
Host smart-a1740e89-ce52-4855-95ba-53a741a12e2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547278152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3547278152
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1648558544
Short name T193
Test name
Test status
Simulation time 542051752 ps
CPU time 11.25 seconds
Started Aug 06 06:22:32 PM PDT 24
Finished Aug 06 06:22:43 PM PDT 24
Peak memory 212916 kb
Host smart-b34eaee9-af09-4f52-aea3-dfdbcc1679f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648558544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1648558544
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3638109582
Short name T250
Test name
Test status
Simulation time 93418237 ps
CPU time 5.4 seconds
Started Aug 06 06:22:34 PM PDT 24
Finished Aug 06 06:22:39 PM PDT 24
Peak memory 212128 kb
Host smart-bb239c74-fc02-4b67-a5fa-777219451032
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3638109582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3638109582
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1180513240
Short name T170
Test name
Test status
Simulation time 1467804252 ps
CPU time 8.73 seconds
Started Aug 06 06:22:32 PM PDT 24
Finished Aug 06 06:22:41 PM PDT 24
Peak memory 213120 kb
Host smart-beaa6bb9-945f-4d9e-9ac4-51177bdb0392
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180513240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1180513240
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.683967748
Short name T304
Test name
Test status
Simulation time 247426730 ps
CPU time 5.21 seconds
Started Aug 06 06:22:32 PM PDT 24
Finished Aug 06 06:22:37 PM PDT 24
Peak memory 212060 kb
Host smart-9af43955-5123-49cf-b6b7-46514c87ee53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683967748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.683967748
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3087886814
Short name T172
Test name
Test status
Simulation time 2564007211 ps
CPU time 118.76 seconds
Started Aug 06 06:22:31 PM PDT 24
Finished Aug 06 06:24:30 PM PDT 24
Peak memory 237448 kb
Host smart-a28fdfd7-e1a0-4823-b276-18f0ccc01dd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087886814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3087886814
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2959016885
Short name T202
Test name
Test status
Simulation time 999510697 ps
CPU time 11.02 seconds
Started Aug 06 06:22:33 PM PDT 24
Finished Aug 06 06:22:44 PM PDT 24
Peak memory 212792 kb
Host smart-9409b204-010b-44f4-939f-c21c765ec0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959016885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2959016885
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3883756897
Short name T154
Test name
Test status
Simulation time 1025437870 ps
CPU time 6.53 seconds
Started Aug 06 06:22:32 PM PDT 24
Finished Aug 06 06:22:38 PM PDT 24
Peak memory 212076 kb
Host smart-e475e300-6d60-4249-9371-82d3d4817f32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3883756897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3883756897
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1458267306
Short name T69
Test name
Test status
Simulation time 867888464 ps
CPU time 13.17 seconds
Started Aug 06 06:22:33 PM PDT 24
Finished Aug 06 06:22:46 PM PDT 24
Peak memory 214964 kb
Host smart-64455649-baef-43ed-a138-ed80e7152eab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458267306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1458267306
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1081281273
Short name T194
Test name
Test status
Simulation time 440564004 ps
CPU time 4.22 seconds
Started Aug 06 06:22:47 PM PDT 24
Finished Aug 06 06:22:51 PM PDT 24
Peak memory 212080 kb
Host smart-8fb87370-db25-4404-be1b-b9b588236f43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081281273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1081281273
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.830172974
Short name T174
Test name
Test status
Simulation time 1384338824 ps
CPU time 11.16 seconds
Started Aug 06 06:22:47 PM PDT 24
Finished Aug 06 06:22:59 PM PDT 24
Peak memory 212904 kb
Host smart-8ed43857-126a-4258-8797-bdec34947b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830172974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.830172974
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.4134717942
Short name T191
Test name
Test status
Simulation time 271404958 ps
CPU time 12.75 seconds
Started Aug 06 06:22:30 PM PDT 24
Finished Aug 06 06:22:43 PM PDT 24
Peak memory 213948 kb
Host smart-59483175-71c1-43bb-9765-7dc43581db85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134717942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.4134717942
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1383564275
Short name T45
Test name
Test status
Simulation time 23705474005 ps
CPU time 10033.8 seconds
Started Aug 06 06:22:46 PM PDT 24
Finished Aug 06 09:10:01 PM PDT 24
Peak memory 236612 kb
Host smart-3faedda1-a886-458e-84e6-ec15244ddb30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383564275 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1383564275
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.774465720
Short name T158
Test name
Test status
Simulation time 86251343 ps
CPU time 4.3 seconds
Started Aug 06 06:22:45 PM PDT 24
Finished Aug 06 06:22:50 PM PDT 24
Peak memory 212028 kb
Host smart-7b8ef178-b5f0-4d04-8878-ca38a4f12c78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774465720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.774465720
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3803291666
Short name T201
Test name
Test status
Simulation time 4864107028 ps
CPU time 149.87 seconds
Started Aug 06 06:22:46 PM PDT 24
Finished Aug 06 06:25:16 PM PDT 24
Peak memory 234456 kb
Host smart-bf3bf1ae-f907-4dd6-bd96-766641d30a22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803291666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3803291666
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.789950335
Short name T135
Test name
Test status
Simulation time 554779542 ps
CPU time 11.02 seconds
Started Aug 06 06:22:46 PM PDT 24
Finished Aug 06 06:22:57 PM PDT 24
Peak memory 212848 kb
Host smart-61e88a7a-071f-4a13-bdc0-dd825f2cd257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789950335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.789950335
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.531703250
Short name T255
Test name
Test status
Simulation time 189959856 ps
CPU time 5.58 seconds
Started Aug 06 06:22:46 PM PDT 24
Finished Aug 06 06:22:51 PM PDT 24
Peak memory 212112 kb
Host smart-707678d0-3ae7-40ca-b2de-7340a9a1a790
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=531703250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.531703250
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3109623965
Short name T127
Test name
Test status
Simulation time 1226850694 ps
CPU time 13.19 seconds
Started Aug 06 06:22:47 PM PDT 24
Finished Aug 06 06:23:01 PM PDT 24
Peak memory 214856 kb
Host smart-ed1493c5-25aa-46b6-9dc8-3cfcdd055c8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109623965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3109623965
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1140175946
Short name T235
Test name
Test status
Simulation time 516939654 ps
CPU time 5 seconds
Started Aug 06 06:22:48 PM PDT 24
Finished Aug 06 06:22:53 PM PDT 24
Peak memory 212108 kb
Host smart-505ea6b1-9e7e-4889-abf2-6b3af5c80999
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140175946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1140175946
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3977561133
Short name T262
Test name
Test status
Simulation time 2472889268 ps
CPU time 141.95 seconds
Started Aug 06 06:22:47 PM PDT 24
Finished Aug 06 06:25:09 PM PDT 24
Peak memory 234448 kb
Host smart-b194aec9-207d-452e-9ebf-5a2ffd76d9a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977561133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3977561133
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2444734787
Short name T133
Test name
Test status
Simulation time 175381528 ps
CPU time 9.41 seconds
Started Aug 06 06:22:47 PM PDT 24
Finished Aug 06 06:22:56 PM PDT 24
Peak memory 212860 kb
Host smart-96532451-9195-4024-a77c-3b5b09a1381a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444734787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2444734787
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.4290655041
Short name T242
Test name
Test status
Simulation time 386560080 ps
CPU time 5.54 seconds
Started Aug 06 06:22:46 PM PDT 24
Finished Aug 06 06:22:51 PM PDT 24
Peak memory 212188 kb
Host smart-00f837dc-eef2-4718-8dce-a2a8836f3d3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4290655041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.4290655041
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1610676316
Short name T311
Test name
Test status
Simulation time 517524448 ps
CPU time 5.89 seconds
Started Aug 06 06:22:45 PM PDT 24
Finished Aug 06 06:22:51 PM PDT 24
Peak memory 212088 kb
Host smart-2267ecc0-3bad-4116-8b31-a9a50bab8a3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610676316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1610676316
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.4235094680
Short name T295
Test name
Test status
Simulation time 10573813962 ps
CPU time 442.83 seconds
Started Aug 06 06:22:46 PM PDT 24
Finished Aug 06 06:30:08 PM PDT 24
Peak memory 224380 kb
Host smart-81debad3-344b-4622-a4a7-a94d5fefd4d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235094680 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.4235094680
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1031339584
Short name T1
Test name
Test status
Simulation time 350547875 ps
CPU time 4.21 seconds
Started Aug 06 06:23:00 PM PDT 24
Finished Aug 06 06:23:04 PM PDT 24
Peak memory 211968 kb
Host smart-c0467c34-bce2-4736-983e-dc2e91bdb13c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031339584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1031339584
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1817814241
Short name T225
Test name
Test status
Simulation time 8000764601 ps
CPU time 88.26 seconds
Started Aug 06 06:23:01 PM PDT 24
Finished Aug 06 06:24:29 PM PDT 24
Peak memory 213704 kb
Host smart-c908f7ac-2256-4542-af0f-396eef6e456b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817814241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1817814241
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2315761776
Short name T301
Test name
Test status
Simulation time 370066443 ps
CPU time 11.35 seconds
Started Aug 06 06:22:59 PM PDT 24
Finished Aug 06 06:23:11 PM PDT 24
Peak memory 212880 kb
Host smart-4d337fc4-9591-4495-a7f6-5cc82222f40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315761776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2315761776
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.967610997
Short name T146
Test name
Test status
Simulation time 136791378 ps
CPU time 6.26 seconds
Started Aug 06 06:22:47 PM PDT 24
Finished Aug 06 06:22:53 PM PDT 24
Peak memory 212012 kb
Host smart-6004c6e6-65c0-4f82-aecd-ce2c41a6abfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=967610997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.967610997
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1232402659
Short name T73
Test name
Test status
Simulation time 236685539 ps
CPU time 6.11 seconds
Started Aug 06 06:22:48 PM PDT 24
Finished Aug 06 06:22:54 PM PDT 24
Peak memory 212300 kb
Host smart-8fa6b4ec-9635-4803-bdb5-02a7ec10e317
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232402659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1232402659
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3561775571
Short name T204
Test name
Test status
Simulation time 1037700561 ps
CPU time 5.18 seconds
Started Aug 06 06:19:55 PM PDT 24
Finished Aug 06 06:20:00 PM PDT 24
Peak memory 211908 kb
Host smart-7c1a7a48-9057-4900-b4dd-a65cb660e396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561775571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3561775571
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.711283480
Short name T249
Test name
Test status
Simulation time 1318002444 ps
CPU time 84.53 seconds
Started Aug 06 06:19:54 PM PDT 24
Finished Aug 06 06:21:19 PM PDT 24
Peak memory 229148 kb
Host smart-481c38c4-23aa-422f-a19d-105dccb8228a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711283480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.711283480
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4238340249
Short name T296
Test name
Test status
Simulation time 254652255 ps
CPU time 11.36 seconds
Started Aug 06 06:19:54 PM PDT 24
Finished Aug 06 06:20:05 PM PDT 24
Peak memory 212932 kb
Host smart-626b4fbe-3910-4d27-8091-31205511eccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238340249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4238340249
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3399416187
Short name T293
Test name
Test status
Simulation time 325837632 ps
CPU time 5.38 seconds
Started Aug 06 06:19:43 PM PDT 24
Finished Aug 06 06:19:48 PM PDT 24
Peak memory 212156 kb
Host smart-6ca2c53a-f5aa-45ee-b573-2752614b1d19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3399416187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3399416187
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2564731422
Short name T269
Test name
Test status
Simulation time 99815350 ps
CPU time 5.64 seconds
Started Aug 06 06:19:45 PM PDT 24
Finished Aug 06 06:19:50 PM PDT 24
Peak memory 212156 kb
Host smart-8ffeb1ec-95fb-4c50-ae61-7fe78e0d1e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564731422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2564731422
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3517138228
Short name T237
Test name
Test status
Simulation time 700903068 ps
CPU time 7.27 seconds
Started Aug 06 06:19:42 PM PDT 24
Finished Aug 06 06:19:50 PM PDT 24
Peak memory 212204 kb
Host smart-9e2645d1-af00-4d0f-80e9-c406502d6565
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517138228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3517138228
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3475370634
Short name T219
Test name
Test status
Simulation time 732269060 ps
CPU time 5.08 seconds
Started Aug 06 06:22:59 PM PDT 24
Finished Aug 06 06:23:04 PM PDT 24
Peak memory 212104 kb
Host smart-5e1bb171-11c9-4881-b0a4-2c25298faa8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475370634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3475370634
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2283661967
Short name T270
Test name
Test status
Simulation time 2463508052 ps
CPU time 59.94 seconds
Started Aug 06 06:23:00 PM PDT 24
Finished Aug 06 06:24:00 PM PDT 24
Peak memory 212456 kb
Host smart-17b8611b-52c5-4b7d-9787-fc262302c3bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283661967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2283661967
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3962876528
Short name T263
Test name
Test status
Simulation time 178287844 ps
CPU time 9.27 seconds
Started Aug 06 06:23:00 PM PDT 24
Finished Aug 06 06:23:09 PM PDT 24
Peak memory 212756 kb
Host smart-309c6156-e5ee-486c-bf09-bfa9c763b5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962876528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3962876528
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.4147925895
Short name T150
Test name
Test status
Simulation time 1022650167 ps
CPU time 6.16 seconds
Started Aug 06 06:23:00 PM PDT 24
Finished Aug 06 06:23:06 PM PDT 24
Peak memory 212180 kb
Host smart-01751919-8524-4d4f-b8cc-989d2b1d36b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4147925895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.4147925895
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3322625894
Short name T151
Test name
Test status
Simulation time 852094494 ps
CPU time 15.59 seconds
Started Aug 06 06:23:01 PM PDT 24
Finished Aug 06 06:23:16 PM PDT 24
Peak memory 215108 kb
Host smart-703e17eb-75ae-411c-9e06-d0399421bee5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322625894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3322625894
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.129379643
Short name T40
Test name
Test status
Simulation time 19901180965 ps
CPU time 6889.78 seconds
Started Aug 06 06:22:59 PM PDT 24
Finished Aug 06 08:17:50 PM PDT 24
Peak memory 236708 kb
Host smart-be1abe00-bb75-4dd1-94c0-4024e927d642
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129379643 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.129379643
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.11943972
Short name T119
Test name
Test status
Simulation time 298288503 ps
CPU time 5.19 seconds
Started Aug 06 06:23:17 PM PDT 24
Finished Aug 06 06:23:22 PM PDT 24
Peak memory 212056 kb
Host smart-1f0ffc8d-f50d-4758-964b-a70fd65fb397
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11943972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.11943972
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3696425940
Short name T173
Test name
Test status
Simulation time 8451561744 ps
CPU time 103.12 seconds
Started Aug 06 06:23:01 PM PDT 24
Finished Aug 06 06:24:44 PM PDT 24
Peak memory 228236 kb
Host smart-e56d3b3f-a884-4ef4-aa3d-91b62e304415
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696425940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3696425940
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.632107790
Short name T227
Test name
Test status
Simulation time 1460698674 ps
CPU time 11.43 seconds
Started Aug 06 06:22:59 PM PDT 24
Finished Aug 06 06:23:10 PM PDT 24
Peak memory 212932 kb
Host smart-ef01ce67-a6fc-493f-a0d0-51b5db226fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632107790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.632107790
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2703426833
Short name T190
Test name
Test status
Simulation time 97851766 ps
CPU time 5.67 seconds
Started Aug 06 06:23:00 PM PDT 24
Finished Aug 06 06:23:06 PM PDT 24
Peak memory 212172 kb
Host smart-31f3a9d9-e866-40b5-9895-1843b80e96a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2703426833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2703426833
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3811983036
Short name T306
Test name
Test status
Simulation time 956039402 ps
CPU time 15.08 seconds
Started Aug 06 06:23:00 PM PDT 24
Finished Aug 06 06:23:15 PM PDT 24
Peak memory 214716 kb
Host smart-85babde3-bd1e-4bf0-a886-15964f7329c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811983036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3811983036
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2051738777
Short name T122
Test name
Test status
Simulation time 176441090 ps
CPU time 4.21 seconds
Started Aug 06 06:23:18 PM PDT 24
Finished Aug 06 06:23:22 PM PDT 24
Peak memory 211996 kb
Host smart-d18f699a-d71a-40a2-9c92-2eba26c955af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051738777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2051738777
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.248839299
Short name T312
Test name
Test status
Simulation time 1223203755 ps
CPU time 79.12 seconds
Started Aug 06 06:23:17 PM PDT 24
Finished Aug 06 06:24:36 PM PDT 24
Peak memory 226260 kb
Host smart-915d88cd-4645-436a-875c-cdaf01a643b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248839299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.248839299
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3808235258
Short name T37
Test name
Test status
Simulation time 664290928 ps
CPU time 9.57 seconds
Started Aug 06 06:23:18 PM PDT 24
Finished Aug 06 06:23:28 PM PDT 24
Peak memory 212864 kb
Host smart-8fb92f05-042e-4be5-9b1d-af8b197518bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808235258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3808235258
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.4290625660
Short name T285
Test name
Test status
Simulation time 136125982 ps
CPU time 6.24 seconds
Started Aug 06 06:23:16 PM PDT 24
Finished Aug 06 06:23:23 PM PDT 24
Peak memory 212060 kb
Host smart-bed2dcde-d782-4b7b-bcb1-6020808ce98e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4290625660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.4290625660
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3743831606
Short name T70
Test name
Test status
Simulation time 423828012 ps
CPU time 7.42 seconds
Started Aug 06 06:23:17 PM PDT 24
Finished Aug 06 06:23:24 PM PDT 24
Peak memory 212088 kb
Host smart-b17119b5-363f-41d9-ac15-7ddf4b736d78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743831606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3743831606
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.725109560
Short name T231
Test name
Test status
Simulation time 261872808 ps
CPU time 5.06 seconds
Started Aug 06 06:23:17 PM PDT 24
Finished Aug 06 06:23:22 PM PDT 24
Peak memory 212016 kb
Host smart-e450ce02-1e1a-4b25-850b-19c5ff012d27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725109560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.725109560
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.84730792
Short name T232
Test name
Test status
Simulation time 2024494509 ps
CPU time 55.07 seconds
Started Aug 06 06:23:18 PM PDT 24
Finished Aug 06 06:24:13 PM PDT 24
Peak memory 212304 kb
Host smart-217cb8aa-ce78-4011-8738-a1cddcdef94a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84730792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_co
rrupt_sig_fatal_chk.84730792
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3874008030
Short name T169
Test name
Test status
Simulation time 169522485 ps
CPU time 9.62 seconds
Started Aug 06 06:23:17 PM PDT 24
Finished Aug 06 06:23:27 PM PDT 24
Peak memory 212820 kb
Host smart-4f9e756f-beff-4f86-baec-73b4cb4a40ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874008030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3874008030
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3083196136
Short name T321
Test name
Test status
Simulation time 797376840 ps
CPU time 6.57 seconds
Started Aug 06 06:23:18 PM PDT 24
Finished Aug 06 06:23:25 PM PDT 24
Peak memory 212124 kb
Host smart-3b5f86d6-95bc-496d-83d0-31e7dcf1cbb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3083196136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3083196136
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2925873257
Short name T277
Test name
Test status
Simulation time 1933210762 ps
CPU time 6.06 seconds
Started Aug 06 06:23:17 PM PDT 24
Finished Aug 06 06:23:23 PM PDT 24
Peak memory 212180 kb
Host smart-4859005b-3447-492b-96d5-fceee2d1ba69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925873257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2925873257
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.794911374
Short name T257
Test name
Test status
Simulation time 176203357 ps
CPU time 4.21 seconds
Started Aug 06 06:23:42 PM PDT 24
Finished Aug 06 06:23:46 PM PDT 24
Peak memory 212004 kb
Host smart-21dd9127-e46b-4b7b-abf6-241ee6a3a353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794911374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.794911374
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1375294606
Short name T39
Test name
Test status
Simulation time 17229809905 ps
CPU time 127.76 seconds
Started Aug 06 06:23:42 PM PDT 24
Finished Aug 06 06:25:50 PM PDT 24
Peak memory 238432 kb
Host smart-39e7fa69-e397-4669-bdd9-c185a935f395
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375294606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1375294606
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3342193754
Short name T160
Test name
Test status
Simulation time 174781100 ps
CPU time 9.62 seconds
Started Aug 06 06:23:42 PM PDT 24
Finished Aug 06 06:23:52 PM PDT 24
Peak memory 213000 kb
Host smart-cb09b15b-ad9f-49e2-873b-5dccbdc8d3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342193754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3342193754
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1844017381
Short name T155
Test name
Test status
Simulation time 101410045 ps
CPU time 5.89 seconds
Started Aug 06 06:23:43 PM PDT 24
Finished Aug 06 06:23:49 PM PDT 24
Peak memory 212176 kb
Host smart-fce2bb87-3bd1-438d-ac6e-6cac1d718038
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844017381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1844017381
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3181864369
Short name T152
Test name
Test status
Simulation time 623600876 ps
CPU time 14.96 seconds
Started Aug 06 06:23:43 PM PDT 24
Finished Aug 06 06:23:58 PM PDT 24
Peak memory 214584 kb
Host smart-d1005d0b-8d15-439d-aa03-880ed0bec9e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181864369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3181864369
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.666624454
Short name T206
Test name
Test status
Simulation time 600256128 ps
CPU time 4.32 seconds
Started Aug 06 06:23:42 PM PDT 24
Finished Aug 06 06:23:47 PM PDT 24
Peak memory 211944 kb
Host smart-12cded5d-ba90-402e-b911-c1132ba86a04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666624454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.666624454
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3109716855
Short name T236
Test name
Test status
Simulation time 6990257462 ps
CPU time 118.05 seconds
Started Aug 06 06:23:43 PM PDT 24
Finished Aug 06 06:25:41 PM PDT 24
Peak memory 238828 kb
Host smart-71af3cf1-f570-4b4c-91ba-36a45fd244eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109716855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3109716855
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.836194071
Short name T192
Test name
Test status
Simulation time 675924233 ps
CPU time 9.51 seconds
Started Aug 06 06:23:43 PM PDT 24
Finished Aug 06 06:23:53 PM PDT 24
Peak memory 215100 kb
Host smart-36a9adf1-f33b-47ae-a073-6f88adc75eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836194071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.836194071
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2638574117
Short name T300
Test name
Test status
Simulation time 1827318766 ps
CPU time 5.4 seconds
Started Aug 06 06:23:42 PM PDT 24
Finished Aug 06 06:23:47 PM PDT 24
Peak memory 212024 kb
Host smart-39e1eb97-5859-446a-8810-f1f646a89bb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2638574117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2638574117
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1242917324
Short name T238
Test name
Test status
Simulation time 851969436 ps
CPU time 11.97 seconds
Started Aug 06 06:23:43 PM PDT 24
Finished Aug 06 06:23:55 PM PDT 24
Peak memory 215192 kb
Host smart-51f6d3a2-ff18-49a2-9729-54214bfe71fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242917324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1242917324
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2606713577
Short name T52
Test name
Test status
Simulation time 129957224 ps
CPU time 5.14 seconds
Started Aug 06 06:23:41 PM PDT 24
Finished Aug 06 06:23:47 PM PDT 24
Peak memory 212068 kb
Host smart-107e2217-fbe0-436a-a598-35204709dc95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606713577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2606713577
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.116628712
Short name T271
Test name
Test status
Simulation time 5553003148 ps
CPU time 115.23 seconds
Started Aug 06 06:23:43 PM PDT 24
Finished Aug 06 06:25:38 PM PDT 24
Peak memory 238164 kb
Host smart-399c3ac2-2432-427b-9583-cdebbb6d9d38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116628712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.116628712
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1130724164
Short name T166
Test name
Test status
Simulation time 1783135938 ps
CPU time 11.18 seconds
Started Aug 06 06:23:42 PM PDT 24
Finished Aug 06 06:23:54 PM PDT 24
Peak memory 212992 kb
Host smart-f0f09fe4-1197-47ff-a4f0-5894009e61c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130724164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1130724164
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1221328968
Short name T212
Test name
Test status
Simulation time 403578152 ps
CPU time 5.78 seconds
Started Aug 06 06:23:44 PM PDT 24
Finished Aug 06 06:23:50 PM PDT 24
Peak memory 212108 kb
Host smart-2b9091ab-91d1-46ab-a1d4-e3ca2d75f53a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1221328968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1221328968
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3456397461
Short name T121
Test name
Test status
Simulation time 184156926 ps
CPU time 7.49 seconds
Started Aug 06 06:23:43 PM PDT 24
Finished Aug 06 06:23:50 PM PDT 24
Peak memory 212080 kb
Host smart-cb6f1e9c-6a25-4172-b65c-33d4a6ebf9a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456397461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3456397461
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1512016400
Short name T308
Test name
Test status
Simulation time 126623490 ps
CPU time 5.02 seconds
Started Aug 06 06:24:11 PM PDT 24
Finished Aug 06 06:24:16 PM PDT 24
Peak memory 212016 kb
Host smart-67561b5f-cc3e-4414-ad8a-876187f2e727
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512016400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1512016400
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3779048671
Short name T239
Test name
Test status
Simulation time 1829871674 ps
CPU time 111.6 seconds
Started Aug 06 06:24:07 PM PDT 24
Finished Aug 06 06:25:59 PM PDT 24
Peak memory 237672 kb
Host smart-5fce3e45-b777-4731-8666-1f519dc42480
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779048671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3779048671
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3257899057
Short name T29
Test name
Test status
Simulation time 1315914560 ps
CPU time 11.07 seconds
Started Aug 06 06:24:09 PM PDT 24
Finished Aug 06 06:24:20 PM PDT 24
Peak memory 212804 kb
Host smart-7897f2e8-0c26-4007-89f1-59cdb89ba26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257899057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3257899057
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4263790984
Short name T258
Test name
Test status
Simulation time 1265642922 ps
CPU time 5.39 seconds
Started Aug 06 06:24:09 PM PDT 24
Finished Aug 06 06:24:15 PM PDT 24
Peak memory 212072 kb
Host smart-ecb6fab9-5df0-47b2-9919-a9a89e994d7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4263790984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4263790984
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.513683480
Short name T283
Test name
Test status
Simulation time 2183005308 ps
CPU time 23.95 seconds
Started Aug 06 06:24:09 PM PDT 24
Finished Aug 06 06:24:33 PM PDT 24
Peak memory 217136 kb
Host smart-cccf44a9-9ad8-452d-8dae-da97c59f04b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513683480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.513683480
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.4051856183
Short name T149
Test name
Test status
Simulation time 85745930 ps
CPU time 4.31 seconds
Started Aug 06 06:24:08 PM PDT 24
Finished Aug 06 06:24:12 PM PDT 24
Peak memory 212044 kb
Host smart-f0756a81-fe64-43ac-98b9-68f54ac240a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051856183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4051856183
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.76167942
Short name T313
Test name
Test status
Simulation time 8035759279 ps
CPU time 108.81 seconds
Started Aug 06 06:24:09 PM PDT 24
Finished Aug 06 06:25:58 PM PDT 24
Peak memory 238372 kb
Host smart-b16a2ee1-2af5-42de-9764-755a85efca5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76167942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_co
rrupt_sig_fatal_chk.76167942
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.4145952821
Short name T318
Test name
Test status
Simulation time 1850894745 ps
CPU time 9.44 seconds
Started Aug 06 06:24:06 PM PDT 24
Finished Aug 06 06:24:16 PM PDT 24
Peak memory 212984 kb
Host smart-2757337b-0dd4-42d2-8b26-6c11845d4e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145952821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.4145952821
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2843203980
Short name T53
Test name
Test status
Simulation time 389184217 ps
CPU time 5.55 seconds
Started Aug 06 06:24:10 PM PDT 24
Finished Aug 06 06:24:16 PM PDT 24
Peak memory 212112 kb
Host smart-0aaf91c8-b509-41e3-9363-0075e692d152
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2843203980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2843203980
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2712675715
Short name T286
Test name
Test status
Simulation time 489217719 ps
CPU time 6.17 seconds
Started Aug 06 06:24:08 PM PDT 24
Finished Aug 06 06:24:14 PM PDT 24
Peak memory 212248 kb
Host smart-3f515442-6b49-456b-be85-a12fff5b3726
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712675715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2712675715
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1443962733
Short name T325
Test name
Test status
Simulation time 85620779 ps
CPU time 4.19 seconds
Started Aug 06 06:24:07 PM PDT 24
Finished Aug 06 06:24:11 PM PDT 24
Peak memory 212028 kb
Host smart-513688be-1aba-4298-a7be-dcc7dd8278da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443962733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1443962733
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2103016014
Short name T273
Test name
Test status
Simulation time 1699727986 ps
CPU time 79.82 seconds
Started Aug 06 06:24:07 PM PDT 24
Finished Aug 06 06:25:27 PM PDT 24
Peak memory 238260 kb
Host smart-8a221ee7-9b33-400e-bc06-31a68a1e8af9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103016014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2103016014
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1168880651
Short name T303
Test name
Test status
Simulation time 251867572 ps
CPU time 11.3 seconds
Started Aug 06 06:24:09 PM PDT 24
Finished Aug 06 06:24:20 PM PDT 24
Peak memory 212928 kb
Host smart-bb85a35e-62ae-4bd2-a065-b572b7fb8ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168880651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1168880651
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.899428994
Short name T309
Test name
Test status
Simulation time 1980749146 ps
CPU time 8.75 seconds
Started Aug 06 06:24:10 PM PDT 24
Finished Aug 06 06:24:19 PM PDT 24
Peak memory 212188 kb
Host smart-ccd35007-a77c-4bb4-872a-0522690c578c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=899428994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.899428994
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2424824669
Short name T68
Test name
Test status
Simulation time 757941572 ps
CPU time 12.3 seconds
Started Aug 06 06:24:09 PM PDT 24
Finished Aug 06 06:24:22 PM PDT 24
Peak memory 214712 kb
Host smart-81269838-a780-4485-a8d2-6ffb82f8213b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424824669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2424824669
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1137515814
Short name T92
Test name
Test status
Simulation time 492478703 ps
CPU time 7.46 seconds
Started Aug 06 06:20:10 PM PDT 24
Finished Aug 06 06:20:17 PM PDT 24
Peak memory 212068 kb
Host smart-4cf3d8e9-a6e2-4ca2-a8ab-1263b480ac65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137515814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1137515814
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3504731173
Short name T167
Test name
Test status
Simulation time 176124873 ps
CPU time 9.49 seconds
Started Aug 06 06:20:08 PM PDT 24
Finished Aug 06 06:20:17 PM PDT 24
Peak memory 212920 kb
Host smart-f6711b96-3b19-45bb-9cb7-c351031ea365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504731173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3504731173
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2924902160
Short name T18
Test name
Test status
Simulation time 138582784 ps
CPU time 6.48 seconds
Started Aug 06 06:19:53 PM PDT 24
Finished Aug 06 06:20:00 PM PDT 24
Peak memory 212180 kb
Host smart-7c1222e4-2632-4290-bb4b-ebf7ca833fb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2924902160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2924902160
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2690650645
Short name T23
Test name
Test status
Simulation time 923547343 ps
CPU time 99.15 seconds
Started Aug 06 06:20:08 PM PDT 24
Finished Aug 06 06:21:47 PM PDT 24
Peak memory 237292 kb
Host smart-2b51b805-92a3-4dae-8473-befb2bc5ed1b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690650645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2690650645
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1219937803
Short name T186
Test name
Test status
Simulation time 598076530 ps
CPU time 6.52 seconds
Started Aug 06 06:19:55 PM PDT 24
Finished Aug 06 06:20:02 PM PDT 24
Peak memory 212120 kb
Host smart-59552655-afef-42f3-b606-d376f75e0c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219937803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1219937803
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2765018940
Short name T310
Test name
Test status
Simulation time 834738101 ps
CPU time 7.99 seconds
Started Aug 06 06:19:55 PM PDT 24
Finished Aug 06 06:20:03 PM PDT 24
Peak memory 212132 kb
Host smart-bea2d808-c77e-475c-bd47-3d46e9eb61cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765018940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2765018940
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2548744784
Short name T128
Test name
Test status
Simulation time 544386362 ps
CPU time 5.13 seconds
Started Aug 06 06:24:10 PM PDT 24
Finished Aug 06 06:24:16 PM PDT 24
Peak memory 212040 kb
Host smart-a8efdeca-73ae-4055-adc3-9aa641915347
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548744784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2548744784
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.807910742
Short name T315
Test name
Test status
Simulation time 8459253156 ps
CPU time 145.21 seconds
Started Aug 06 06:24:08 PM PDT 24
Finished Aug 06 06:26:33 PM PDT 24
Peak memory 234852 kb
Host smart-5b0a11f0-0af6-409d-b15e-d4c4119c7f49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807910742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.807910742
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2805793809
Short name T205
Test name
Test status
Simulation time 1554763261 ps
CPU time 11.37 seconds
Started Aug 06 06:24:07 PM PDT 24
Finished Aug 06 06:24:18 PM PDT 24
Peak memory 212860 kb
Host smart-b6317eac-f000-4a01-ae87-abba6bb398dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805793809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2805793809
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.4087227433
Short name T316
Test name
Test status
Simulation time 95202343 ps
CPU time 5.47 seconds
Started Aug 06 06:24:11 PM PDT 24
Finished Aug 06 06:24:16 PM PDT 24
Peak memory 212188 kb
Host smart-dcbf702b-d5c0-4e17-8ca3-e07250bcd2ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4087227433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.4087227433
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.4176259513
Short name T11
Test name
Test status
Simulation time 1717001347 ps
CPU time 13.8 seconds
Started Aug 06 06:24:08 PM PDT 24
Finished Aug 06 06:24:22 PM PDT 24
Peak memory 214628 kb
Host smart-2085ba88-a8da-4e62-98db-9d63c091e1c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176259513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.4176259513
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3432130393
Short name T196
Test name
Test status
Simulation time 132175559 ps
CPU time 5.2 seconds
Started Aug 06 06:24:07 PM PDT 24
Finished Aug 06 06:24:13 PM PDT 24
Peak memory 212032 kb
Host smart-6e764e81-26ea-426a-8537-cb377f7d116b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432130393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3432130393
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.53017312
Short name T322
Test name
Test status
Simulation time 2495210098 ps
CPU time 144.74 seconds
Started Aug 06 06:24:08 PM PDT 24
Finished Aug 06 06:26:33 PM PDT 24
Peak memory 226348 kb
Host smart-796309f7-6326-478d-8a5e-164c80b5feb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53017312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_co
rrupt_sig_fatal_chk.53017312
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1954515021
Short name T297
Test name
Test status
Simulation time 251583973 ps
CPU time 11.28 seconds
Started Aug 06 06:24:09 PM PDT 24
Finished Aug 06 06:24:20 PM PDT 24
Peak memory 212904 kb
Host smart-5c7eb89b-976c-4e5a-aead-9fc023032432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954515021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1954515021
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2846019829
Short name T198
Test name
Test status
Simulation time 632110554 ps
CPU time 6.36 seconds
Started Aug 06 06:24:07 PM PDT 24
Finished Aug 06 06:24:14 PM PDT 24
Peak memory 212244 kb
Host smart-aac92b28-1c14-4235-8e6b-ebe842292bfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2846019829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2846019829
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1247868891
Short name T241
Test name
Test status
Simulation time 285160811 ps
CPU time 5.17 seconds
Started Aug 06 06:24:23 PM PDT 24
Finished Aug 06 06:24:28 PM PDT 24
Peak memory 211944 kb
Host smart-ac3b1d8d-8732-4054-81ca-e1f097d846fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247868891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1247868891
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1301662361
Short name T278
Test name
Test status
Simulation time 3669579695 ps
CPU time 170.56 seconds
Started Aug 06 06:24:10 PM PDT 24
Finished Aug 06 06:27:01 PM PDT 24
Peak memory 239416 kb
Host smart-61119236-2f5f-4c5e-9160-b65323ae532e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301662361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1301662361
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1806628545
Short name T134
Test name
Test status
Simulation time 992549059 ps
CPU time 11.17 seconds
Started Aug 06 06:24:22 PM PDT 24
Finished Aug 06 06:24:33 PM PDT 24
Peak memory 212932 kb
Host smart-58112152-9f66-431f-b70f-36e713cd7bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806628545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1806628545
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2241174782
Short name T123
Test name
Test status
Simulation time 142232554 ps
CPU time 6.47 seconds
Started Aug 06 06:24:10 PM PDT 24
Finished Aug 06 06:24:16 PM PDT 24
Peak memory 212200 kb
Host smart-bfedea67-83a1-4457-ad93-61910b8eda47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2241174782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2241174782
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.619556210
Short name T176
Test name
Test status
Simulation time 913501027 ps
CPU time 10.05 seconds
Started Aug 06 06:24:11 PM PDT 24
Finished Aug 06 06:24:21 PM PDT 24
Peak memory 212208 kb
Host smart-2eed7cf8-8d2d-423c-87aa-d4012bac4ac4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619556210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.619556210
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3749176103
Short name T179
Test name
Test status
Simulation time 223810704855 ps
CPU time 1838.17 seconds
Started Aug 06 06:24:22 PM PDT 24
Finished Aug 06 06:55:01 PM PDT 24
Peak memory 241348 kb
Host smart-4b071a99-1059-464e-b046-5205f827cc9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749176103 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.3749176103
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1401598689
Short name T120
Test name
Test status
Simulation time 497762855 ps
CPU time 5.15 seconds
Started Aug 06 06:24:22 PM PDT 24
Finished Aug 06 06:24:27 PM PDT 24
Peak memory 212024 kb
Host smart-8dba907a-14f8-4cb0-811b-9f0a8c5a4107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401598689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1401598689
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2015951118
Short name T187
Test name
Test status
Simulation time 1565562087 ps
CPU time 119.2 seconds
Started Aug 06 06:24:22 PM PDT 24
Finished Aug 06 06:26:21 PM PDT 24
Peak memory 238260 kb
Host smart-71376697-c3aa-4c93-baf3-05040b46bde9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015951118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2015951118
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3442807381
Short name T288
Test name
Test status
Simulation time 259160314 ps
CPU time 11.41 seconds
Started Aug 06 06:24:21 PM PDT 24
Finished Aug 06 06:24:33 PM PDT 24
Peak memory 212860 kb
Host smart-7e73ce0f-55a8-4a2d-89d4-7be6925e8463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442807381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3442807381
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.4205720185
Short name T125
Test name
Test status
Simulation time 1838702872 ps
CPU time 5.9 seconds
Started Aug 06 06:24:23 PM PDT 24
Finished Aug 06 06:24:29 PM PDT 24
Peak memory 212024 kb
Host smart-0f6ea3ba-566f-43bd-827c-ae255210fe96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4205720185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.4205720185
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2027376450
Short name T66
Test name
Test status
Simulation time 215825818 ps
CPU time 14.02 seconds
Started Aug 06 06:24:24 PM PDT 24
Finished Aug 06 06:24:38 PM PDT 24
Peak memory 214796 kb
Host smart-3036314c-020d-44fe-8bb7-91e017366831
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027376450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2027376450
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.919427221
Short name T307
Test name
Test status
Simulation time 175994308 ps
CPU time 4.13 seconds
Started Aug 06 06:24:21 PM PDT 24
Finished Aug 06 06:24:26 PM PDT 24
Peak memory 212072 kb
Host smart-14d5ab1d-c132-4c7f-b256-230e516455d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919427221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.919427221
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.231682001
Short name T216
Test name
Test status
Simulation time 2783899664 ps
CPU time 151.22 seconds
Started Aug 06 06:24:22 PM PDT 24
Finished Aug 06 06:26:54 PM PDT 24
Peak memory 238484 kb
Host smart-17b5c887-133f-45aa-9b86-0a1348019c01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231682001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.231682001
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2467583592
Short name T256
Test name
Test status
Simulation time 178626816 ps
CPU time 9.28 seconds
Started Aug 06 06:24:21 PM PDT 24
Finished Aug 06 06:24:30 PM PDT 24
Peak memory 212848 kb
Host smart-a1fa5328-bc06-4d9f-a636-b00ac14741d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467583592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2467583592
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3634746757
Short name T329
Test name
Test status
Simulation time 884344521 ps
CPU time 6.93 seconds
Started Aug 06 06:24:22 PM PDT 24
Finished Aug 06 06:24:29 PM PDT 24
Peak memory 212156 kb
Host smart-c4662b60-d24e-460c-a5ba-1c81626184b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3634746757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3634746757
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2649992440
Short name T211
Test name
Test status
Simulation time 309321600 ps
CPU time 8.32 seconds
Started Aug 06 06:24:25 PM PDT 24
Finished Aug 06 06:24:33 PM PDT 24
Peak memory 212976 kb
Host smart-6784236d-48d6-4963-8d14-5b984fb0de01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649992440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2649992440
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2935604164
Short name T214
Test name
Test status
Simulation time 595564595 ps
CPU time 5.08 seconds
Started Aug 06 06:24:24 PM PDT 24
Finished Aug 06 06:24:29 PM PDT 24
Peak memory 212080 kb
Host smart-d7e51d0e-a624-404a-835a-6feba7bb5cae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935604164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2935604164
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.908187328
Short name T159
Test name
Test status
Simulation time 5313274905 ps
CPU time 136.38 seconds
Started Aug 06 06:24:24 PM PDT 24
Finished Aug 06 06:26:40 PM PDT 24
Peak memory 238520 kb
Host smart-1e187107-d41d-43a8-b8c3-2190ef561311
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908187328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.908187328
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2194849861
Short name T38
Test name
Test status
Simulation time 348105397 ps
CPU time 9.39 seconds
Started Aug 06 06:24:24 PM PDT 24
Finished Aug 06 06:24:34 PM PDT 24
Peak memory 212932 kb
Host smart-e00c3dc8-a0b7-44e9-ba79-82bafa8f4885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194849861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2194849861
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1707821348
Short name T244
Test name
Test status
Simulation time 102185290 ps
CPU time 5.84 seconds
Started Aug 06 06:24:25 PM PDT 24
Finished Aug 06 06:24:31 PM PDT 24
Peak memory 212108 kb
Host smart-51f3ea80-9ff0-4dcd-ba43-b4e9285361a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1707821348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1707821348
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.89329618
Short name T141
Test name
Test status
Simulation time 577428112 ps
CPU time 8.07 seconds
Started Aug 06 06:24:21 PM PDT 24
Finished Aug 06 06:24:29 PM PDT 24
Peak memory 213224 kb
Host smart-0473f231-fcdb-4275-92d9-8d6024320ce2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89329618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 45.rom_ctrl_stress_all.89329618
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.54335615
Short name T10
Test name
Test status
Simulation time 181554949018 ps
CPU time 1577.97 seconds
Started Aug 06 06:24:24 PM PDT 24
Finished Aug 06 06:50:42 PM PDT 24
Peak memory 236680 kb
Host smart-de8658ce-03d3-4ba4-8220-3d3430cf0be9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54335615 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.54335615
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3392824596
Short name T9
Test name
Test status
Simulation time 346718393 ps
CPU time 4.33 seconds
Started Aug 06 06:24:45 PM PDT 24
Finished Aug 06 06:24:49 PM PDT 24
Peak memory 212052 kb
Host smart-349131b9-e11c-4a51-a242-bcf7813dc632
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392824596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3392824596
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3178133760
Short name T245
Test name
Test status
Simulation time 7254105229 ps
CPU time 167.04 seconds
Started Aug 06 06:24:44 PM PDT 24
Finished Aug 06 06:27:31 PM PDT 24
Peak memory 234296 kb
Host smart-c7899c79-f4af-4045-93f8-b86a23dfeaf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178133760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3178133760
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.515312438
Short name T54
Test name
Test status
Simulation time 830310443 ps
CPU time 11.22 seconds
Started Aug 06 06:24:44 PM PDT 24
Finished Aug 06 06:24:56 PM PDT 24
Peak memory 213004 kb
Host smart-8744f4e8-f8ff-41d8-9e41-b18fafa7e1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515312438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.515312438
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1407048371
Short name T139
Test name
Test status
Simulation time 139125503 ps
CPU time 6.27 seconds
Started Aug 06 06:24:45 PM PDT 24
Finished Aug 06 06:24:51 PM PDT 24
Peak memory 212156 kb
Host smart-e15cdd3d-d6a6-4d0b-a04f-8c028ddcbbca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1407048371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1407048371
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3206190875
Short name T13
Test name
Test status
Simulation time 29638400628 ps
CPU time 680.46 seconds
Started Aug 06 06:24:45 PM PDT 24
Finished Aug 06 06:36:06 PM PDT 24
Peak memory 229372 kb
Host smart-9d781e3c-bd79-4774-8320-3e8e9b651880
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206190875 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.3206190875
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.648870629
Short name T282
Test name
Test status
Simulation time 128570228 ps
CPU time 5.26 seconds
Started Aug 06 06:24:46 PM PDT 24
Finished Aug 06 06:24:51 PM PDT 24
Peak memory 212124 kb
Host smart-f16d8779-fbb7-4e64-88a5-eb2d44fa551e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648870629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.648870629
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1405402748
Short name T30
Test name
Test status
Simulation time 5372402855 ps
CPU time 79.99 seconds
Started Aug 06 06:24:45 PM PDT 24
Finished Aug 06 06:26:05 PM PDT 24
Peak memory 238496 kb
Host smart-d1d3ee1e-5467-496e-ae7b-e2b0c42d6bb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405402748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1405402748
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3061400386
Short name T287
Test name
Test status
Simulation time 858155258 ps
CPU time 11.25 seconds
Started Aug 06 06:24:45 PM PDT 24
Finished Aug 06 06:24:56 PM PDT 24
Peak memory 212864 kb
Host smart-e3148be6-5b32-4553-94af-cbf6c78fa3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061400386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3061400386
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.4208450897
Short name T264
Test name
Test status
Simulation time 546504977 ps
CPU time 5.67 seconds
Started Aug 06 06:24:44 PM PDT 24
Finished Aug 06 06:24:50 PM PDT 24
Peak memory 212124 kb
Host smart-952762c0-35b3-42bd-9e76-194cd04fb3db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4208450897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.4208450897
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2778394757
Short name T314
Test name
Test status
Simulation time 3129191749 ps
CPU time 21.11 seconds
Started Aug 06 06:24:44 PM PDT 24
Finished Aug 06 06:25:05 PM PDT 24
Peak memory 216816 kb
Host smart-fd8376e7-9f34-4af5-9ae3-9931060506fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778394757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2778394757
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3747272689
Short name T327
Test name
Test status
Simulation time 242416889628 ps
CPU time 1814.77 seconds
Started Aug 06 06:24:43 PM PDT 24
Finished Aug 06 06:54:58 PM PDT 24
Peak memory 239256 kb
Host smart-08cafb42-bada-4c9d-a50b-548dae7c422f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747272689 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.3747272689
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.11292393
Short name T124
Test name
Test status
Simulation time 346291285 ps
CPU time 4.18 seconds
Started Aug 06 06:24:45 PM PDT 24
Finished Aug 06 06:24:49 PM PDT 24
Peak memory 212036 kb
Host smart-02eb8b89-2f5e-46da-b3fa-fcd70a95a20e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11292393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.11292393
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1853815314
Short name T132
Test name
Test status
Simulation time 1760391751 ps
CPU time 121.99 seconds
Started Aug 06 06:24:45 PM PDT 24
Finished Aug 06 06:26:47 PM PDT 24
Peak memory 238340 kb
Host smart-4a95ca22-ba17-4232-b645-f5c0426d499e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853815314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1853815314
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1342523407
Short name T183
Test name
Test status
Simulation time 1132222037 ps
CPU time 11.11 seconds
Started Aug 06 06:24:45 PM PDT 24
Finished Aug 06 06:24:56 PM PDT 24
Peak memory 212880 kb
Host smart-2922875a-055a-4c14-859e-f26121101c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342523407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1342523407
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1043621260
Short name T93
Test name
Test status
Simulation time 97088360 ps
CPU time 5.63 seconds
Started Aug 06 06:24:47 PM PDT 24
Finished Aug 06 06:24:53 PM PDT 24
Peak memory 212148 kb
Host smart-e72fd5aa-e483-49c4-8a21-35fc5480b958
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1043621260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1043621260
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1066295648
Short name T302
Test name
Test status
Simulation time 150087652 ps
CPU time 8.29 seconds
Started Aug 06 06:24:43 PM PDT 24
Finished Aug 06 06:24:52 PM PDT 24
Peak memory 212120 kb
Host smart-fafe29d0-b8a6-4ee4-aa29-319b4ac79511
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066295648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1066295648
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2656560090
Short name T41
Test name
Test status
Simulation time 57952841281 ps
CPU time 2175.39 seconds
Started Aug 06 06:24:47 PM PDT 24
Finished Aug 06 07:01:02 PM PDT 24
Peak memory 239256 kb
Host smart-dc62517b-c194-4661-bcd0-c68bbc9c278b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656560090 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2656560090
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3079319010
Short name T289
Test name
Test status
Simulation time 257360233 ps
CPU time 5.14 seconds
Started Aug 06 06:24:56 PM PDT 24
Finished Aug 06 06:25:02 PM PDT 24
Peak memory 212060 kb
Host smart-5fe54321-a68b-4a73-a184-30a67229dbe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079319010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3079319010
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1464201576
Short name T299
Test name
Test status
Simulation time 4353530306 ps
CPU time 91.02 seconds
Started Aug 06 06:24:56 PM PDT 24
Finished Aug 06 06:26:27 PM PDT 24
Peak memory 229280 kb
Host smart-993c20df-2649-46bb-b3ac-c5ce202b5e5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464201576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1464201576
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1275193881
Short name T188
Test name
Test status
Simulation time 175237169 ps
CPU time 9.34 seconds
Started Aug 06 06:24:56 PM PDT 24
Finished Aug 06 06:25:05 PM PDT 24
Peak memory 212836 kb
Host smart-99757e81-4a49-4357-9e8a-3e1814ebb3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275193881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1275193881
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.220048314
Short name T247
Test name
Test status
Simulation time 387101836 ps
CPU time 5.46 seconds
Started Aug 06 06:24:58 PM PDT 24
Finished Aug 06 06:25:03 PM PDT 24
Peak memory 212180 kb
Host smart-0fd792ab-e786-4481-9b74-81443cdabe09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=220048314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.220048314
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3338520885
Short name T71
Test name
Test status
Simulation time 406810732 ps
CPU time 21.33 seconds
Started Aug 06 06:24:58 PM PDT 24
Finished Aug 06 06:25:19 PM PDT 24
Peak memory 216920 kb
Host smart-6e166ca1-0cda-43c1-a6b9-e32e89519604
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338520885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3338520885
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.4286146410
Short name T157
Test name
Test status
Simulation time 776198591 ps
CPU time 5.23 seconds
Started Aug 06 06:20:25 PM PDT 24
Finished Aug 06 06:20:30 PM PDT 24
Peak memory 212044 kb
Host smart-2a6b4be4-4570-4998-bbb8-bb46f90c6fdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286146410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.4286146410
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.61717565
Short name T8
Test name
Test status
Simulation time 1430999795 ps
CPU time 94.35 seconds
Started Aug 06 06:20:10 PM PDT 24
Finished Aug 06 06:21:44 PM PDT 24
Peak memory 228244 kb
Host smart-dc170076-33d2-4612-9ec2-7d02fb137264
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61717565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_cor
rupt_sig_fatal_chk.61717565
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4165644554
Short name T25
Test name
Test status
Simulation time 1039567201 ps
CPU time 11.02 seconds
Started Aug 06 06:20:25 PM PDT 24
Finished Aug 06 06:20:36 PM PDT 24
Peak memory 212772 kb
Host smart-05929da3-2b00-4c36-96a9-dc2cebfa08d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165644554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.4165644554
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2259990138
Short name T184
Test name
Test status
Simulation time 278994694 ps
CPU time 6.33 seconds
Started Aug 06 06:20:10 PM PDT 24
Finished Aug 06 06:20:16 PM PDT 24
Peak memory 212120 kb
Host smart-fcbf0be9-91d3-4617-8c3d-d5728849c581
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2259990138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2259990138
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1952548694
Short name T265
Test name
Test status
Simulation time 143504046 ps
CPU time 6.42 seconds
Started Aug 06 06:20:08 PM PDT 24
Finished Aug 06 06:20:15 PM PDT 24
Peak memory 212164 kb
Host smart-ba80571e-72a2-40f3-a6ac-88515cb06aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952548694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1952548694
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.4006814990
Short name T272
Test name
Test status
Simulation time 1165827527 ps
CPU time 15.72 seconds
Started Aug 06 06:20:10 PM PDT 24
Finished Aug 06 06:20:26 PM PDT 24
Peak memory 216320 kb
Host smart-d0292762-0988-4837-86c9-cb4db3e9194c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006814990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.4006814990
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1701123699
Short name T43
Test name
Test status
Simulation time 7545132179 ps
CPU time 19.1 seconds
Started Aug 06 06:20:24 PM PDT 24
Finished Aug 06 06:20:43 PM PDT 24
Peak memory 220572 kb
Host smart-1b454c72-0642-40e1-9806-a9891a5409e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701123699 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.1701123699
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.767076858
Short name T12
Test name
Test status
Simulation time 167852859 ps
CPU time 4.3 seconds
Started Aug 06 06:20:25 PM PDT 24
Finished Aug 06 06:20:30 PM PDT 24
Peak memory 211944 kb
Host smart-e5748417-86da-4f58-b932-83b840ceb81d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767076858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.767076858
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3528554042
Short name T142
Test name
Test status
Simulation time 7824905238 ps
CPU time 123.84 seconds
Started Aug 06 06:20:26 PM PDT 24
Finished Aug 06 06:22:30 PM PDT 24
Peak memory 238968 kb
Host smart-edf236f2-398b-488f-8966-7a6e63053c1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528554042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3528554042
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.524122368
Short name T140
Test name
Test status
Simulation time 204855499 ps
CPU time 9.44 seconds
Started Aug 06 06:20:25 PM PDT 24
Finished Aug 06 06:20:35 PM PDT 24
Peak memory 215140 kb
Host smart-5287c656-2c00-4112-96df-5e5d1c4edad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524122368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.524122368
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.4157748675
Short name T209
Test name
Test status
Simulation time 96266254 ps
CPU time 5.43 seconds
Started Aug 06 06:20:25 PM PDT 24
Finished Aug 06 06:20:31 PM PDT 24
Peak memory 212180 kb
Host smart-6129cc80-d8c6-4297-b8aa-ccb5b5063b1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4157748675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.4157748675
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.933038186
Short name T324
Test name
Test status
Simulation time 139407387 ps
CPU time 6.34 seconds
Started Aug 06 06:20:27 PM PDT 24
Finished Aug 06 06:20:33 PM PDT 24
Peak memory 212136 kb
Host smart-61531235-69ef-4ab8-93b5-cf975436b4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933038186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.933038186
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.4057912047
Short name T31
Test name
Test status
Simulation time 611315538 ps
CPU time 15.76 seconds
Started Aug 06 06:20:25 PM PDT 24
Finished Aug 06 06:20:41 PM PDT 24
Peak memory 214548 kb
Host smart-b5afc57c-cc0d-4d09-9aae-89fc92b60266
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057912047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.4057912047
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3066676118
Short name T113
Test name
Test status
Simulation time 254323512 ps
CPU time 5.12 seconds
Started Aug 06 06:20:27 PM PDT 24
Finished Aug 06 06:20:32 PM PDT 24
Peak memory 211904 kb
Host smart-fc6ed65a-cbc8-4996-b04c-cdc352bf7448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066676118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3066676118
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1801462365
Short name T126
Test name
Test status
Simulation time 4443629018 ps
CPU time 124.47 seconds
Started Aug 06 06:20:27 PM PDT 24
Finished Aug 06 06:22:31 PM PDT 24
Peak memory 237456 kb
Host smart-f69c6916-e066-4d79-931f-dc7dc57149ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801462365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1801462365
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.758299732
Short name T163
Test name
Test status
Simulation time 170270976 ps
CPU time 9.45 seconds
Started Aug 06 06:20:26 PM PDT 24
Finished Aug 06 06:20:36 PM PDT 24
Peak memory 212860 kb
Host smart-3405678e-3ac7-4a9f-ae27-4e1c3fa9dee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758299732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.758299732
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1653780450
Short name T189
Test name
Test status
Simulation time 142527802 ps
CPU time 6.77 seconds
Started Aug 06 06:20:26 PM PDT 24
Finished Aug 06 06:20:33 PM PDT 24
Peak memory 212156 kb
Host smart-cb4b888a-eba1-41ee-952b-fe45d4a20a76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1653780450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1653780450
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2240962650
Short name T28
Test name
Test status
Simulation time 290942863 ps
CPU time 6.17 seconds
Started Aug 06 06:20:25 PM PDT 24
Finished Aug 06 06:20:31 PM PDT 24
Peak memory 212212 kb
Host smart-5d0143e9-7661-4872-a876-3ea9f4f1553c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240962650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2240962650
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.759354261
Short name T164
Test name
Test status
Simulation time 1528790230 ps
CPU time 26.2 seconds
Started Aug 06 06:20:25 PM PDT 24
Finished Aug 06 06:20:52 PM PDT 24
Peak memory 215776 kb
Host smart-ac0ae731-1ac8-4995-a45c-c3c3c8a1d9c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759354261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.759354261
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1038478777
Short name T274
Test name
Test status
Simulation time 132946435 ps
CPU time 5.17 seconds
Started Aug 06 06:20:39 PM PDT 24
Finished Aug 06 06:20:44 PM PDT 24
Peak memory 212004 kb
Host smart-d95e9782-ae55-4ce6-b9b7-27f59bccea72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038478777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1038478777
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2250852213
Short name T291
Test name
Test status
Simulation time 7744274848 ps
CPU time 126.33 seconds
Started Aug 06 06:20:39 PM PDT 24
Finished Aug 06 06:22:45 PM PDT 24
Peak memory 234432 kb
Host smart-f505363f-2230-40e9-88da-f460a04cfa84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250852213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2250852213
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.801289969
Short name T24
Test name
Test status
Simulation time 667172983 ps
CPU time 9.56 seconds
Started Aug 06 06:20:40 PM PDT 24
Finished Aug 06 06:20:49 PM PDT 24
Peak memory 213432 kb
Host smart-c55875c9-521f-4de7-8b80-26019854d71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801289969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.801289969
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3258570707
Short name T281
Test name
Test status
Simulation time 559618794 ps
CPU time 6.35 seconds
Started Aug 06 06:20:25 PM PDT 24
Finished Aug 06 06:20:32 PM PDT 24
Peak memory 212112 kb
Host smart-0eb5bbd6-5fb9-4968-896a-3b3fd1a553cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3258570707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3258570707
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.4273264732
Short name T224
Test name
Test status
Simulation time 289484165 ps
CPU time 6.31 seconds
Started Aug 06 06:20:25 PM PDT 24
Finished Aug 06 06:20:32 PM PDT 24
Peak memory 212180 kb
Host smart-bd9da7a4-01df-44d8-af30-757b0085c3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273264732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4273264732
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1772530327
Short name T233
Test name
Test status
Simulation time 863208286 ps
CPU time 18.13 seconds
Started Aug 06 06:20:25 PM PDT 24
Finished Aug 06 06:20:43 PM PDT 24
Peak memory 215468 kb
Host smart-bb6e85c6-ca08-4ac7-ba47-9091c1267210
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772530327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1772530327
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1269216826
Short name T147
Test name
Test status
Simulation time 87348526 ps
CPU time 4.33 seconds
Started Aug 06 06:20:41 PM PDT 24
Finished Aug 06 06:20:45 PM PDT 24
Peak memory 212032 kb
Host smart-4b13cf0c-2e6f-42ef-beab-8d5a16ce642e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269216826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1269216826
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1341553864
Short name T195
Test name
Test status
Simulation time 2561727762 ps
CPU time 149.15 seconds
Started Aug 06 06:20:40 PM PDT 24
Finished Aug 06 06:23:09 PM PDT 24
Peak memory 229248 kb
Host smart-4a545f99-a6df-4302-8273-86533471ab20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341553864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1341553864
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2231298009
Short name T279
Test name
Test status
Simulation time 175525343 ps
CPU time 9.57 seconds
Started Aug 06 06:20:41 PM PDT 24
Finished Aug 06 06:20:51 PM PDT 24
Peak memory 212976 kb
Host smart-f7ccbc86-8ade-47f2-822c-d427e050b07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231298009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2231298009
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.682633817
Short name T267
Test name
Test status
Simulation time 178906519 ps
CPU time 5.57 seconds
Started Aug 06 06:20:40 PM PDT 24
Finished Aug 06 06:20:45 PM PDT 24
Peak memory 212184 kb
Host smart-223518f8-115a-4f95-b2e5-b54359b671b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=682633817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.682633817
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1647835647
Short name T228
Test name
Test status
Simulation time 270225553 ps
CPU time 6.57 seconds
Started Aug 06 06:20:41 PM PDT 24
Finished Aug 06 06:20:48 PM PDT 24
Peak memory 212152 kb
Host smart-d0f9ad69-2f62-4a66-8011-181c969124d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647835647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1647835647
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2706572310
Short name T153
Test name
Test status
Simulation time 602675351 ps
CPU time 15.28 seconds
Started Aug 06 06:20:39 PM PDT 24
Finished Aug 06 06:20:54 PM PDT 24
Peak memory 213660 kb
Host smart-55a83951-40f7-4a92-b5bb-d5b2a60f922f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706572310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2706572310
Directory /workspace/9.rom_ctrl_stress_all/latest
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