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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.32 96.89 92.42 97.67 100.00 98.62 97.30 98.37


Total test records in report: 423
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T294 /workspace/coverage/default/28.rom_ctrl_alert_test.1496419774 Aug 07 04:58:34 PM PDT 24 Aug 07 04:58:39 PM PDT 24 271057785 ps
T295 /workspace/coverage/default/14.rom_ctrl_stress_all.2286373042 Aug 07 04:57:59 PM PDT 24 Aug 07 04:58:12 PM PDT 24 263547698 ps
T296 /workspace/coverage/default/48.rom_ctrl_stress_all.3449608341 Aug 07 04:58:48 PM PDT 24 Aug 07 04:59:11 PM PDT 24 1633250301 ps
T297 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3812311772 Aug 07 04:58:32 PM PDT 24 Aug 07 05:02:02 PM PDT 24 17566693034 ps
T298 /workspace/coverage/default/25.rom_ctrl_stress_all.435006064 Aug 07 04:58:02 PM PDT 24 Aug 07 04:58:25 PM PDT 24 566935079 ps
T299 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.822163036 Aug 07 04:57:51 PM PDT 24 Aug 07 04:58:00 PM PDT 24 521315761 ps
T300 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.869788905 Aug 07 04:58:34 PM PDT 24 Aug 07 04:58:44 PM PDT 24 693195112 ps
T301 /workspace/coverage/default/20.rom_ctrl_alert_test.2310237156 Aug 07 04:58:02 PM PDT 24 Aug 07 04:58:06 PM PDT 24 88076689 ps
T302 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1194313666 Aug 07 04:58:29 PM PDT 24 Aug 07 04:58:41 PM PDT 24 1036378767 ps
T303 /workspace/coverage/default/26.rom_ctrl_alert_test.271574122 Aug 07 04:58:20 PM PDT 24 Aug 07 04:58:25 PM PDT 24 693333059 ps
T304 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1279219477 Aug 07 04:58:39 PM PDT 24 Aug 07 05:00:22 PM PDT 24 21555533093 ps
T305 /workspace/coverage/default/29.rom_ctrl_alert_test.557585196 Aug 07 04:58:28 PM PDT 24 Aug 07 04:58:32 PM PDT 24 95634911 ps
T306 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2074780031 Aug 07 04:57:47 PM PDT 24 Aug 07 04:57:58 PM PDT 24 641302187 ps
T307 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2843937336 Aug 07 04:58:23 PM PDT 24 Aug 07 06:23:46 PM PDT 24 478812970159 ps
T308 /workspace/coverage/default/44.rom_ctrl_alert_test.2936526620 Aug 07 04:58:49 PM PDT 24 Aug 07 04:58:53 PM PDT 24 349998011 ps
T309 /workspace/coverage/default/35.rom_ctrl_stress_all.2063428227 Aug 07 04:58:59 PM PDT 24 Aug 07 04:59:12 PM PDT 24 604621344 ps
T310 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.683542737 Aug 07 04:58:32 PM PDT 24 Aug 07 04:58:42 PM PDT 24 169713208 ps
T311 /workspace/coverage/default/17.rom_ctrl_alert_test.3523841381 Aug 07 04:58:16 PM PDT 24 Aug 07 04:58:21 PM PDT 24 621909236 ps
T312 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2674699500 Aug 07 04:58:13 PM PDT 24 Aug 07 04:58:19 PM PDT 24 338250817 ps
T313 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2175024855 Aug 07 04:58:28 PM PDT 24 Aug 07 04:59:48 PM PDT 24 7189318217 ps
T314 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3535976952 Aug 07 04:58:26 PM PDT 24 Aug 07 04:58:36 PM PDT 24 2779921849 ps
T315 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.497580177 Aug 07 04:58:42 PM PDT 24 Aug 07 04:58:53 PM PDT 24 1084430573 ps
T316 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3216644931 Aug 07 04:58:59 PM PDT 24 Aug 07 04:59:05 PM PDT 24 97829646 ps
T317 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2548838494 Aug 07 04:57:49 PM PDT 24 Aug 07 04:59:10 PM PDT 24 7636216877 ps
T318 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2360026130 Aug 07 04:57:58 PM PDT 24 Aug 07 04:58:04 PM PDT 24 100305838 ps
T319 /workspace/coverage/default/44.rom_ctrl_stress_all.4035956371 Aug 07 04:58:32 PM PDT 24 Aug 07 04:58:45 PM PDT 24 768957620 ps
T320 /workspace/coverage/default/21.rom_ctrl_alert_test.1836778099 Aug 07 04:58:15 PM PDT 24 Aug 07 04:58:23 PM PDT 24 1436821963 ps
T321 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1630822377 Aug 07 04:58:47 PM PDT 24 Aug 07 04:58:59 PM PDT 24 252499835 ps
T322 /workspace/coverage/default/9.rom_ctrl_alert_test.773827432 Aug 07 04:57:57 PM PDT 24 Aug 07 04:58:02 PM PDT 24 259742979 ps
T323 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2929293172 Aug 07 04:58:09 PM PDT 24 Aug 07 04:58:15 PM PDT 24 404866078 ps
T324 /workspace/coverage/default/13.rom_ctrl_alert_test.1725583633 Aug 07 04:57:59 PM PDT 24 Aug 07 04:58:06 PM PDT 24 521407332 ps
T325 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2023875230 Aug 07 04:57:49 PM PDT 24 Aug 07 04:57:54 PM PDT 24 652193671 ps
T326 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2921327208 Aug 07 04:58:43 PM PDT 24 Aug 07 04:58:49 PM PDT 24 288747747 ps
T327 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3135277853 Aug 07 04:58:12 PM PDT 24 Aug 07 04:58:18 PM PDT 24 194693934 ps
T328 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1617225395 Aug 07 04:58:44 PM PDT 24 Aug 07 04:58:51 PM PDT 24 143329834 ps
T329 /workspace/coverage/default/8.rom_ctrl_stress_all.1287003235 Aug 07 04:57:49 PM PDT 24 Aug 07 04:58:03 PM PDT 24 506265464 ps
T330 /workspace/coverage/default/49.rom_ctrl_stress_all.1012979996 Aug 07 04:58:38 PM PDT 24 Aug 07 04:58:49 PM PDT 24 382544882 ps
T90 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1734339204 Aug 07 04:58:24 PM PDT 24 Aug 07 06:44:38 PM PDT 24 19370545919 ps
T331 /workspace/coverage/default/38.rom_ctrl_stress_all.2634999445 Aug 07 04:58:34 PM PDT 24 Aug 07 04:58:50 PM PDT 24 293787252 ps
T332 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3443343347 Aug 07 04:58:57 PM PDT 24 Aug 07 05:00:26 PM PDT 24 1341811377 ps
T53 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2108252894 Aug 07 04:58:29 PM PDT 24 Aug 07 04:58:34 PM PDT 24 87130559 ps
T54 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.122975679 Aug 07 04:58:41 PM PDT 24 Aug 07 04:58:46 PM PDT 24 419788641 ps
T55 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3387805926 Aug 07 04:58:48 PM PDT 24 Aug 07 04:58:52 PM PDT 24 361734525 ps
T82 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4094420449 Aug 07 04:58:50 PM PDT 24 Aug 07 04:58:54 PM PDT 24 85566277 ps
T59 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3485540796 Aug 07 04:59:01 PM PDT 24 Aug 07 04:59:08 PM PDT 24 179576388 ps
T86 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2374293755 Aug 07 04:58:48 PM PDT 24 Aug 07 04:58:58 PM PDT 24 174890873 ps
T333 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.556508655 Aug 07 04:58:48 PM PDT 24 Aug 07 04:58:59 PM PDT 24 291341262 ps
T83 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3261137018 Aug 07 04:58:37 PM PDT 24 Aug 07 04:58:41 PM PDT 24 337912104 ps
T334 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2721576013 Aug 07 04:58:45 PM PDT 24 Aug 07 04:58:54 PM PDT 24 1036855742 ps
T49 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.540000107 Aug 07 04:58:33 PM PDT 24 Aug 07 04:59:48 PM PDT 24 488285990 ps
T60 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.287158860 Aug 07 04:58:49 PM PDT 24 Aug 07 04:58:53 PM PDT 24 348123985 ps
T335 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.627420342 Aug 07 04:58:30 PM PDT 24 Aug 07 04:58:37 PM PDT 24 1246326784 ps
T336 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2095898670 Aug 07 04:58:41 PM PDT 24 Aug 07 04:58:46 PM PDT 24 130932145 ps
T87 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3206290949 Aug 07 04:58:51 PM PDT 24 Aug 07 04:58:56 PM PDT 24 130396133 ps
T337 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4248748240 Aug 07 04:58:49 PM PDT 24 Aug 07 04:58:54 PM PDT 24 264010448 ps
T338 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3381139259 Aug 07 04:58:37 PM PDT 24 Aug 07 04:58:41 PM PDT 24 172844819 ps
T50 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1880179240 Aug 07 04:58:44 PM PDT 24 Aug 07 04:59:52 PM PDT 24 2249118080 ps
T88 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4251803917 Aug 07 04:59:07 PM PDT 24 Aug 07 04:59:12 PM PDT 24 86490212 ps
T61 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4062422027 Aug 07 04:58:33 PM PDT 24 Aug 07 04:59:00 PM PDT 24 2625007672 ps
T339 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3765134148 Aug 07 04:58:47 PM PDT 24 Aug 07 04:58:52 PM PDT 24 105112875 ps
T340 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1702877347 Aug 07 04:58:30 PM PDT 24 Aug 07 04:58:34 PM PDT 24 692840967 ps
T341 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.661072786 Aug 07 04:58:59 PM PDT 24 Aug 07 04:59:03 PM PDT 24 413577683 ps
T342 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2821262612 Aug 07 04:58:53 PM PDT 24 Aug 07 04:59:16 PM PDT 24 539092107 ps
T84 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3459099164 Aug 07 04:58:50 PM PDT 24 Aug 07 04:58:54 PM PDT 24 415107150 ps
T343 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2609522592 Aug 07 04:58:36 PM PDT 24 Aug 07 04:58:44 PM PDT 24 493780172 ps
T344 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.381262006 Aug 07 04:58:40 PM PDT 24 Aug 07 04:58:48 PM PDT 24 524577185 ps
T345 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2320342958 Aug 07 04:58:40 PM PDT 24 Aug 07 04:58:50 PM PDT 24 573460419 ps
T346 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1783422411 Aug 07 04:58:46 PM PDT 24 Aug 07 04:58:52 PM PDT 24 482044496 ps
T85 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1552725561 Aug 07 04:58:34 PM PDT 24 Aug 07 04:58:38 PM PDT 24 347780181 ps
T347 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3779845844 Aug 07 04:58:40 PM PDT 24 Aug 07 04:58:47 PM PDT 24 265886762 ps
T62 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1853150098 Aug 07 04:58:29 PM PDT 24 Aug 07 04:58:33 PM PDT 24 522118473 ps
T63 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1659656368 Aug 07 04:58:47 PM PDT 24 Aug 07 04:59:07 PM PDT 24 1436927865 ps
T64 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.428892630 Aug 07 04:58:45 PM PDT 24 Aug 07 04:59:07 PM PDT 24 3084955201 ps
T348 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2496803737 Aug 07 04:58:40 PM PDT 24 Aug 07 04:58:48 PM PDT 24 324222771 ps
T65 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2272515680 Aug 07 04:58:59 PM PDT 24 Aug 07 04:59:04 PM PDT 24 126564515 ps
T349 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2758388682 Aug 07 04:58:56 PM PDT 24 Aug 07 04:59:05 PM PDT 24 145553375 ps
T66 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.634251759 Aug 07 04:58:36 PM PDT 24 Aug 07 04:58:41 PM PDT 24 518035198 ps
T74 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.726468811 Aug 07 04:58:34 PM PDT 24 Aug 07 04:58:52 PM PDT 24 376186488 ps
T51 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2322720284 Aug 07 04:58:56 PM PDT 24 Aug 07 04:59:33 PM PDT 24 196709921 ps
T350 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1220710272 Aug 07 04:58:40 PM PDT 24 Aug 07 04:58:58 PM PDT 24 381106122 ps
T351 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2978499002 Aug 07 04:58:56 PM PDT 24 Aug 07 04:59:04 PM PDT 24 515401803 ps
T352 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4255957166 Aug 07 04:58:28 PM PDT 24 Aug 07 04:58:35 PM PDT 24 2512948409 ps
T353 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.240828058 Aug 07 04:58:58 PM PDT 24 Aug 07 04:59:10 PM PDT 24 1703934497 ps
T354 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2696146285 Aug 07 04:58:28 PM PDT 24 Aug 07 04:58:35 PM PDT 24 85811904 ps
T75 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.587432257 Aug 07 04:58:38 PM PDT 24 Aug 07 04:58:43 PM PDT 24 278910858 ps
T355 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2869323607 Aug 07 04:58:35 PM PDT 24 Aug 07 04:58:45 PM PDT 24 1003695581 ps
T76 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1081585268 Aug 07 04:58:35 PM PDT 24 Aug 07 04:58:41 PM PDT 24 179571132 ps
T91 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.438813531 Aug 07 04:58:41 PM PDT 24 Aug 07 04:59:19 PM PDT 24 240347519 ps
T356 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1415079212 Aug 07 04:58:57 PM PDT 24 Aug 07 04:59:06 PM PDT 24 261651949 ps
T357 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.510544033 Aug 07 04:58:45 PM PDT 24 Aug 07 04:58:49 PM PDT 24 298861129 ps
T92 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1298621979 Aug 07 04:58:30 PM PDT 24 Aug 07 04:59:40 PM PDT 24 505839658 ps
T358 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3898554238 Aug 07 04:58:25 PM PDT 24 Aug 07 04:58:32 PM PDT 24 627219386 ps
T95 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1456672045 Aug 07 04:58:49 PM PDT 24 Aug 07 04:59:24 PM PDT 24 570765869 ps
T359 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2651761017 Aug 07 04:58:31 PM PDT 24 Aug 07 04:58:35 PM PDT 24 171540973 ps
T360 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1082498628 Aug 07 04:58:38 PM PDT 24 Aug 07 04:58:43 PM PDT 24 87521289 ps
T361 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3216899224 Aug 07 04:58:54 PM PDT 24 Aug 07 04:58:58 PM PDT 24 334262912 ps
T93 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1566797537 Aug 07 04:58:33 PM PDT 24 Aug 07 04:59:42 PM PDT 24 287641077 ps
T98 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3716383662 Aug 07 04:58:39 PM PDT 24 Aug 07 04:59:16 PM PDT 24 611751030 ps
T362 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3388247942 Aug 07 04:58:35 PM PDT 24 Aug 07 04:58:45 PM PDT 24 632072767 ps
T363 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2174205440 Aug 07 04:58:50 PM PDT 24 Aug 07 04:58:55 PM PDT 24 520463057 ps
T364 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3236212235 Aug 07 04:58:31 PM PDT 24 Aug 07 04:58:36 PM PDT 24 150677729 ps
T365 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3643910617 Aug 07 04:58:56 PM PDT 24 Aug 07 04:59:01 PM PDT 24 272809807 ps
T366 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1830618300 Aug 07 04:58:43 PM PDT 24 Aug 07 04:58:50 PM PDT 24 142783572 ps
T367 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.790127600 Aug 07 04:58:27 PM PDT 24 Aug 07 04:58:32 PM PDT 24 129909626 ps
T368 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1288975534 Aug 07 04:58:54 PM PDT 24 Aug 07 04:59:00 PM PDT 24 141839264 ps
T369 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3818747942 Aug 07 04:58:41 PM PDT 24 Aug 07 04:58:46 PM PDT 24 108312905 ps
T370 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3817476517 Aug 07 04:58:32 PM PDT 24 Aug 07 04:58:37 PM PDT 24 133660060 ps
T371 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1782568813 Aug 07 04:58:53 PM PDT 24 Aug 07 04:58:58 PM PDT 24 88356474 ps
T77 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.730023071 Aug 07 04:58:52 PM PDT 24 Aug 07 04:59:10 PM PDT 24 375124153 ps
T372 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1838514277 Aug 07 04:58:37 PM PDT 24 Aug 07 04:58:41 PM PDT 24 90367063 ps
T373 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3307075050 Aug 07 04:58:46 PM PDT 24 Aug 07 04:58:53 PM PDT 24 153150505 ps
T374 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3738888019 Aug 07 04:58:41 PM PDT 24 Aug 07 04:58:45 PM PDT 24 309066215 ps
T375 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.120481625 Aug 07 04:58:41 PM PDT 24 Aug 07 04:58:48 PM PDT 24 88962017 ps
T99 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.573091703 Aug 07 04:58:51 PM PDT 24 Aug 07 05:00:00 PM PDT 24 234049362 ps
T102 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1556627124 Aug 07 04:59:00 PM PDT 24 Aug 07 04:59:39 PM PDT 24 1316392059 ps
T376 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1100739578 Aug 07 04:58:49 PM PDT 24 Aug 07 04:58:56 PM PDT 24 98417556 ps
T377 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3109844123 Aug 07 04:58:40 PM PDT 24 Aug 07 04:58:44 PM PDT 24 86318502 ps
T78 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.261012687 Aug 07 04:58:51 PM PDT 24 Aug 07 04:59:19 PM PDT 24 682336137 ps
T378 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1448642165 Aug 07 04:58:43 PM PDT 24 Aug 07 04:58:48 PM PDT 24 525668068 ps
T379 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4086583354 Aug 07 04:58:37 PM PDT 24 Aug 07 04:58:44 PM PDT 24 491379800 ps
T94 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.565169383 Aug 07 04:58:41 PM PDT 24 Aug 07 04:59:17 PM PDT 24 1293308517 ps
T380 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3604691403 Aug 07 04:58:49 PM PDT 24 Aug 07 04:58:55 PM PDT 24 524205384 ps
T381 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1383539341 Aug 07 04:58:41 PM PDT 24 Aug 07 04:58:47 PM PDT 24 102012319 ps
T382 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2041215323 Aug 07 04:58:46 PM PDT 24 Aug 07 04:58:50 PM PDT 24 89006577 ps
T383 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.614255071 Aug 07 04:58:32 PM PDT 24 Aug 07 04:58:37 PM PDT 24 660133701 ps
T103 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4120751174 Aug 07 04:58:40 PM PDT 24 Aug 07 04:59:50 PM PDT 24 2401633003 ps
T384 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3424549316 Aug 07 04:58:29 PM PDT 24 Aug 07 04:58:35 PM PDT 24 418421225 ps
T385 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3929813816 Aug 07 04:58:55 PM PDT 24 Aug 07 04:59:02 PM PDT 24 340104874 ps
T386 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2662454050 Aug 07 04:58:37 PM PDT 24 Aug 07 04:58:42 PM PDT 24 134251940 ps
T387 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2966325228 Aug 07 04:58:41 PM PDT 24 Aug 07 04:58:46 PM PDT 24 498570784 ps
T79 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.659880087 Aug 07 04:58:45 PM PDT 24 Aug 07 04:58:49 PM PDT 24 182470473 ps
T388 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1349235047 Aug 07 04:58:28 PM PDT 24 Aug 07 04:58:32 PM PDT 24 175556204 ps
T389 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2866251006 Aug 07 04:59:01 PM PDT 24 Aug 07 04:59:37 PM PDT 24 574137944 ps
T390 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1768815732 Aug 07 04:59:00 PM PDT 24 Aug 07 04:59:05 PM PDT 24 305091213 ps
T391 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2353114371 Aug 07 04:58:41 PM PDT 24 Aug 07 04:58:47 PM PDT 24 1230518819 ps
T80 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1268486935 Aug 07 04:58:39 PM PDT 24 Aug 07 04:58:44 PM PDT 24 356872513 ps
T392 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1767098302 Aug 07 04:58:41 PM PDT 24 Aug 07 04:58:47 PM PDT 24 500174274 ps
T393 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1551214261 Aug 07 04:58:41 PM PDT 24 Aug 07 04:58:46 PM PDT 24 1233817914 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1525307048 Aug 07 04:58:40 PM PDT 24 Aug 07 04:58:47 PM PDT 24 267656200 ps
T395 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2716347327 Aug 07 04:58:49 PM PDT 24 Aug 07 04:58:58 PM PDT 24 133480291 ps
T396 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3489542800 Aug 07 04:58:38 PM PDT 24 Aug 07 04:58:44 PM PDT 24 233875672 ps
T397 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2320840569 Aug 07 04:58:44 PM PDT 24 Aug 07 04:58:49 PM PDT 24 2061895862 ps
T398 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4188432734 Aug 07 04:58:38 PM PDT 24 Aug 07 04:58:44 PM PDT 24 277977027 ps
T399 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4063523004 Aug 07 04:58:41 PM PDT 24 Aug 07 04:58:46 PM PDT 24 446331730 ps
T400 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3795430841 Aug 07 04:59:00 PM PDT 24 Aug 07 04:59:05 PM PDT 24 89580959 ps
T401 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1868514420 Aug 07 04:58:39 PM PDT 24 Aug 07 04:58:48 PM PDT 24 159829409 ps
T81 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.837648458 Aug 07 04:58:46 PM PDT 24 Aug 07 04:58:51 PM PDT 24 88940680 ps
T402 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1341391487 Aug 07 04:58:39 PM PDT 24 Aug 07 04:58:44 PM PDT 24 186955921 ps
T100 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.832791118 Aug 07 04:58:32 PM PDT 24 Aug 07 04:59:23 PM PDT 24 2075012355 ps
T101 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.952801774 Aug 07 04:58:40 PM PDT 24 Aug 07 04:59:17 PM PDT 24 559624441 ps
T403 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3885927030 Aug 07 04:58:55 PM PDT 24 Aug 07 04:59:02 PM PDT 24 168240881 ps
T404 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1687757858 Aug 07 04:58:39 PM PDT 24 Aug 07 04:58:43 PM PDT 24 336694305 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1529567217 Aug 07 04:58:43 PM PDT 24 Aug 07 04:58:50 PM PDT 24 527273358 ps
T406 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1038405953 Aug 07 04:58:38 PM PDT 24 Aug 07 04:58:43 PM PDT 24 524433169 ps
T407 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.965201100 Aug 07 04:58:33 PM PDT 24 Aug 07 04:58:44 PM PDT 24 660169444 ps
T408 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.26399667 Aug 07 04:58:37 PM PDT 24 Aug 07 04:58:42 PM PDT 24 413156636 ps
T96 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2862998050 Aug 07 04:58:41 PM PDT 24 Aug 07 04:59:53 PM PDT 24 382218512 ps
T409 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3239442590 Aug 07 04:58:39 PM PDT 24 Aug 07 04:58:44 PM PDT 24 1331012821 ps
T410 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2133132766 Aug 07 04:58:32 PM PDT 24 Aug 07 04:58:37 PM PDT 24 174971091 ps
T411 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2354139100 Aug 07 04:58:46 PM PDT 24 Aug 07 04:58:51 PM PDT 24 132796868 ps
T412 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3560871744 Aug 07 04:58:58 PM PDT 24 Aug 07 04:59:04 PM PDT 24 141426735 ps
T413 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.610689554 Aug 07 04:58:51 PM PDT 24 Aug 07 04:58:55 PM PDT 24 89734213 ps
T414 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1690869098 Aug 07 04:58:43 PM PDT 24 Aug 07 04:58:48 PM PDT 24 192033363 ps
T415 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2338897526 Aug 07 04:58:52 PM PDT 24 Aug 07 04:59:28 PM PDT 24 730004496 ps
T416 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1729856689 Aug 07 04:58:39 PM PDT 24 Aug 07 04:59:16 PM PDT 24 372784051 ps
T417 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3384682046 Aug 07 04:58:47 PM PDT 24 Aug 07 04:58:51 PM PDT 24 756122056 ps
T418 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3509608923 Aug 07 04:58:39 PM PDT 24 Aug 07 04:58:44 PM PDT 24 528759461 ps
T97 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4250494380 Aug 07 04:58:43 PM PDT 24 Aug 07 04:59:59 PM PDT 24 798684616 ps
T419 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4048933152 Aug 07 04:58:43 PM PDT 24 Aug 07 04:59:52 PM PDT 24 312406793 ps
T420 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3625442020 Aug 07 04:58:40 PM PDT 24 Aug 07 04:58:44 PM PDT 24 336551131 ps
T421 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.388050799 Aug 07 04:58:43 PM PDT 24 Aug 07 04:58:50 PM PDT 24 478494887 ps
T422 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1207366923 Aug 07 04:58:44 PM PDT 24 Aug 07 04:58:51 PM PDT 24 134743106 ps
T423 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3085832709 Aug 07 04:58:39 PM PDT 24 Aug 07 04:58:43 PM PDT 24 378837039 ps

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2430045180
Short name T5
Test name
Test status
Simulation time 1718553561 ps
CPU time 104.82 seconds
Started Aug 07 04:58:57 PM PDT 24
Finished Aug 07 05:00:42 PM PDT 24
Peak memory 214300 kb
Host smart-d259a48f-3cc0-4eea-a39c-b2fa0e45f956
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430045180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2430045180
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.220012446
Short name T11
Test name
Test status
Simulation time 20167761594 ps
CPU time 8231.06 seconds
Started Aug 07 04:58:23 PM PDT 24
Finished Aug 07 07:15:35 PM PDT 24
Peak memory 228348 kb
Host smart-011b3ff8-6195-4fbf-b426-c6add47ee6a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220012446 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.220012446
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.172613017
Short name T14
Test name
Test status
Simulation time 2786962280 ps
CPU time 160.75 seconds
Started Aug 07 04:58:01 PM PDT 24
Finished Aug 07 05:00:42 PM PDT 24
Peak memory 234380 kb
Host smart-87fd1a56-a642-40cd-b9e3-609f9d9d3df5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172613017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.172613017
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.540000107
Short name T49
Test name
Test status
Simulation time 488285990 ps
CPU time 74.34 seconds
Started Aug 07 04:58:33 PM PDT 24
Finished Aug 07 04:59:48 PM PDT 24
Peak memory 214204 kb
Host smart-86248553-7df9-43eb-98cf-8e2f8baebcdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540000107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.540000107
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1853393081
Short name T6
Test name
Test status
Simulation time 261418056 ps
CPU time 5.16 seconds
Started Aug 07 04:58:01 PM PDT 24
Finished Aug 07 04:58:06 PM PDT 24
Peak memory 211976 kb
Host smart-ec057ebb-e6c1-4cff-98cf-75ceae0f14a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853393081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1853393081
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2862998050
Short name T96
Test name
Test status
Simulation time 382218512 ps
CPU time 72.07 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:59:53 PM PDT 24
Peak memory 213128 kb
Host smart-13a37682-4eb4-4ffd-9f9f-54681efc7d8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862998050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2862998050
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1991835877
Short name T18
Test name
Test status
Simulation time 244941115 ps
CPU time 55.1 seconds
Started Aug 07 04:57:53 PM PDT 24
Finished Aug 07 04:58:48 PM PDT 24
Peak memory 239156 kb
Host smart-3053a1b3-b0e9-4ba0-bccf-3908bcbfc2da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991835877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1991835877
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.428892630
Short name T64
Test name
Test status
Simulation time 3084955201 ps
CPU time 22.49 seconds
Started Aug 07 04:58:45 PM PDT 24
Finished Aug 07 04:59:07 PM PDT 24
Peak memory 211320 kb
Host smart-ee61f07f-04b2-4b81-b630-8f68a576145b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428892630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.428892630
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2468818718
Short name T44
Test name
Test status
Simulation time 32284160818 ps
CPU time 7007.4 seconds
Started Aug 07 04:58:00 PM PDT 24
Finished Aug 07 06:54:49 PM PDT 24
Peak memory 236640 kb
Host smart-b01190fa-6cb0-4490-a3ae-03afb18ff463
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468818718 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2468818718
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.346156062
Short name T38
Test name
Test status
Simulation time 534778962769 ps
CPU time 4764.71 seconds
Started Aug 07 04:57:51 PM PDT 24
Finished Aug 07 06:17:17 PM PDT 24
Peak memory 253052 kb
Host smart-7e54a7a9-7146-4fa2-9ef5-3ab4d306ad31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346156062 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.346156062
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1145556899
Short name T125
Test name
Test status
Simulation time 1136768162 ps
CPU time 11.46 seconds
Started Aug 07 04:58:11 PM PDT 24
Finished Aug 07 04:58:23 PM PDT 24
Peak memory 212672 kb
Host smart-7928baae-e9ad-4341-8b38-576f2eca58cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145556899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1145556899
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1648450249
Short name T192
Test name
Test status
Simulation time 1278767871 ps
CPU time 9.7 seconds
Started Aug 07 04:58:25 PM PDT 24
Finished Aug 07 04:58:35 PM PDT 24
Peak memory 212888 kb
Host smart-ee85b8fb-0ff5-453a-90d3-c3b398de119a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648450249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1648450249
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1525076172
Short name T73
Test name
Test status
Simulation time 2097447308 ps
CPU time 25.06 seconds
Started Aug 07 04:57:52 PM PDT 24
Finished Aug 07 04:58:17 PM PDT 24
Peak memory 215108 kb
Host smart-a1beb3d8-6f0e-4c9a-87a7-b7d4f418dc37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525076172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1525076172
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.573091703
Short name T99
Test name
Test status
Simulation time 234049362 ps
CPU time 68.48 seconds
Started Aug 07 04:58:51 PM PDT 24
Finished Aug 07 05:00:00 PM PDT 24
Peak memory 213044 kb
Host smart-3ffc03ba-ca17-4ef6-a0ef-68ae8762fcd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573091703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.573091703
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1149487244
Short name T1
Test name
Test status
Simulation time 278591072 ps
CPU time 6.44 seconds
Started Aug 07 04:58:11 PM PDT 24
Finished Aug 07 04:58:18 PM PDT 24
Peak memory 212000 kb
Host smart-1cd81457-4764-40e4-934e-0800c227cf43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1149487244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1149487244
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.287158860
Short name T60
Test name
Test status
Simulation time 348123985 ps
CPU time 4.14 seconds
Started Aug 07 04:58:49 PM PDT 24
Finished Aug 07 04:58:53 PM PDT 24
Peak memory 218148 kb
Host smart-eaa6ee2c-b5b4-4dd3-a08c-9a9ebe14b023
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287158860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.287158860
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3683428797
Short name T46
Test name
Test status
Simulation time 81377019406 ps
CPU time 9639.3 seconds
Started Aug 07 04:58:17 PM PDT 24
Finished Aug 07 07:38:57 PM PDT 24
Peak memory 236648 kb
Host smart-da4d03ea-6790-4dba-a683-62fff66af9f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683428797 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3683428797
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2651228987
Short name T24
Test name
Test status
Simulation time 161115764435 ps
CPU time 1497.95 seconds
Started Aug 07 04:58:25 PM PDT 24
Finished Aug 07 05:23:23 PM PDT 24
Peak memory 236664 kb
Host smart-8c496745-ab37-448b-a35e-0bc527265045
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651228987 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2651228987
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3387805926
Short name T55
Test name
Test status
Simulation time 361734525 ps
CPU time 4.22 seconds
Started Aug 07 04:58:48 PM PDT 24
Finished Aug 07 04:58:52 PM PDT 24
Peak memory 219256 kb
Host smart-a3de91dc-ad77-4f57-9d6b-293a322b2c59
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387805926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3387805926
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2374293755
Short name T86
Test name
Test status
Simulation time 174890873 ps
CPU time 4.48 seconds
Started Aug 07 04:58:48 PM PDT 24
Finished Aug 07 04:58:58 PM PDT 24
Peak memory 219284 kb
Host smart-f92cae6d-3c93-48fe-bc8b-11af5269dc1f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374293755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2374293755
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1081585268
Short name T76
Test name
Test status
Simulation time 179571132 ps
CPU time 5.78 seconds
Started Aug 07 04:58:35 PM PDT 24
Finished Aug 07 04:58:41 PM PDT 24
Peak memory 219420 kb
Host smart-d6bfe731-3e8c-4ff5-98f3-181ce274bb57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081585268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1081585268
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3381139259
Short name T338
Test name
Test status
Simulation time 172844819 ps
CPU time 4.25 seconds
Started Aug 07 04:58:37 PM PDT 24
Finished Aug 07 04:58:41 PM PDT 24
Peak memory 212976 kb
Host smart-d18f431c-848d-4ebd-b546-89b901ce1058
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381139259 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3381139259
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2320840569
Short name T397
Test name
Test status
Simulation time 2061895862 ps
CPU time 5.09 seconds
Started Aug 07 04:58:44 PM PDT 24
Finished Aug 07 04:58:49 PM PDT 24
Peak memory 211256 kb
Host smart-b8c898e1-40a3-429d-8ff5-03c9cddb056e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320840569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2320840569
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1702877347
Short name T340
Test name
Test status
Simulation time 692840967 ps
CPU time 4.24 seconds
Started Aug 07 04:58:30 PM PDT 24
Finished Aug 07 04:58:34 PM PDT 24
Peak memory 211188 kb
Host smart-5c5ed6e8-bbaa-46d8-8493-5ad668b9c9f2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702877347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1702877347
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2651761017
Short name T359
Test name
Test status
Simulation time 171540973 ps
CPU time 4.14 seconds
Started Aug 07 04:58:31 PM PDT 24
Finished Aug 07 04:58:35 PM PDT 24
Peak memory 211060 kb
Host smart-0db64448-a8a3-4bbf-990e-ec57fb1a4940
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651761017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2651761017
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1207366923
Short name T422
Test name
Test status
Simulation time 134743106 ps
CPU time 6.93 seconds
Started Aug 07 04:58:44 PM PDT 24
Finished Aug 07 04:58:51 PM PDT 24
Peak memory 211372 kb
Host smart-75813775-efcf-42de-8883-713a7fc00cfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207366923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1207366923
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3388247942
Short name T362
Test name
Test status
Simulation time 632072767 ps
CPU time 9.43 seconds
Started Aug 07 04:58:35 PM PDT 24
Finished Aug 07 04:58:45 PM PDT 24
Peak memory 215300 kb
Host smart-d966a2a3-dd59-4dbd-be4f-4395422e6f7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388247942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3388247942
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1556627124
Short name T102
Test name
Test status
Simulation time 1316392059 ps
CPU time 39.02 seconds
Started Aug 07 04:59:00 PM PDT 24
Finished Aug 07 04:59:39 PM PDT 24
Peak memory 212736 kb
Host smart-9da9022e-56c9-4ec3-9eef-931c9aed4343
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556627124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1556627124
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.510544033
Short name T357
Test name
Test status
Simulation time 298861129 ps
CPU time 4.21 seconds
Started Aug 07 04:58:45 PM PDT 24
Finished Aug 07 04:58:49 PM PDT 24
Peak memory 211244 kb
Host smart-1362b2e3-65c1-4156-8dff-c7fc8351fd7a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510544033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.510544033
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1838514277
Short name T372
Test name
Test status
Simulation time 90367063 ps
CPU time 4.38 seconds
Started Aug 07 04:58:37 PM PDT 24
Finished Aug 07 04:58:41 PM PDT 24
Peak memory 219368 kb
Host smart-a080e84b-aa21-4df8-9e92-ff87ae82f74c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838514277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1838514277
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1525307048
Short name T394
Test name
Test status
Simulation time 267656200 ps
CPU time 6.76 seconds
Started Aug 07 04:58:40 PM PDT 24
Finished Aug 07 04:58:47 PM PDT 24
Peak memory 211240 kb
Host smart-174eafd2-bdb1-450f-b352-7ff282a8393f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525307048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1525307048
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.556508655
Short name T333
Test name
Test status
Simulation time 291341262 ps
CPU time 5.83 seconds
Started Aug 07 04:58:48 PM PDT 24
Finished Aug 07 04:58:59 PM PDT 24
Peak memory 219444 kb
Host smart-227fbf08-89f1-4b9a-abee-4abe4e7110df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556508655 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.556508655
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1853150098
Short name T62
Test name
Test status
Simulation time 522118473 ps
CPU time 4.17 seconds
Started Aug 07 04:58:29 PM PDT 24
Finished Aug 07 04:58:33 PM PDT 24
Peak memory 219408 kb
Host smart-b7ae74ac-2598-44c6-b657-e795d7a78224
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853150098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1853150098
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2662454050
Short name T386
Test name
Test status
Simulation time 134251940 ps
CPU time 4.06 seconds
Started Aug 07 04:58:37 PM PDT 24
Finished Aug 07 04:58:42 PM PDT 24
Peak memory 211088 kb
Host smart-caaca3a0-ff26-47ab-bb3b-db54d1585736
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662454050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2662454050
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1448642165
Short name T378
Test name
Test status
Simulation time 525668068 ps
CPU time 4.92 seconds
Started Aug 07 04:58:43 PM PDT 24
Finished Aug 07 04:58:48 PM PDT 24
Peak memory 211188 kb
Host smart-75dcf397-5233-45c0-8eb1-776f44bf032b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448642165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1448642165
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1349235047
Short name T388
Test name
Test status
Simulation time 175556204 ps
CPU time 4.38 seconds
Started Aug 07 04:58:28 PM PDT 24
Finished Aug 07 04:58:32 PM PDT 24
Peak memory 218780 kb
Host smart-9d816b5f-e869-4d1d-b58e-e83e0bfd88ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349235047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1349235047
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3898554238
Short name T358
Test name
Test status
Simulation time 627219386 ps
CPU time 6.63 seconds
Started Aug 07 04:58:25 PM PDT 24
Finished Aug 07 04:58:32 PM PDT 24
Peak memory 219588 kb
Host smart-35a0fd01-b26f-46c3-8f71-549306e4db10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898554238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3898554238
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1551214261
Short name T393
Test name
Test status
Simulation time 1233817914 ps
CPU time 5.06 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:58:46 PM PDT 24
Peak memory 215644 kb
Host smart-6b198d1a-0070-42e9-a111-d7ef03e8d64c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551214261 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1551214261
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2174205440
Short name T363
Test name
Test status
Simulation time 520463057 ps
CPU time 5 seconds
Started Aug 07 04:58:50 PM PDT 24
Finished Aug 07 04:58:55 PM PDT 24
Peak memory 218112 kb
Host smart-74b2ef1a-d7a8-40ef-9b5e-ed1ed6ceb785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174205440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2174205440
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.730023071
Short name T77
Test name
Test status
Simulation time 375124153 ps
CPU time 18.58 seconds
Started Aug 07 04:58:52 PM PDT 24
Finished Aug 07 04:59:10 PM PDT 24
Peak memory 211280 kb
Host smart-6458670d-edc1-46c8-8c39-093863819ba6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730023071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.730023071
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3485540796
Short name T59
Test name
Test status
Simulation time 179576388 ps
CPU time 6.83 seconds
Started Aug 07 04:59:01 PM PDT 24
Finished Aug 07 04:59:08 PM PDT 24
Peak memory 219376 kb
Host smart-c04fd453-11d2-490f-b874-49d4cd23cd69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485540796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3485540796
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2320342958
Short name T345
Test name
Test status
Simulation time 573460419 ps
CPU time 10.23 seconds
Started Aug 07 04:58:40 PM PDT 24
Finished Aug 07 04:58:50 PM PDT 24
Peak memory 219512 kb
Host smart-1d7032c5-0685-459d-bbd9-451238c64563
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320342958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2320342958
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.565169383
Short name T94
Test name
Test status
Simulation time 1293308517 ps
CPU time 36.65 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:59:17 PM PDT 24
Peak memory 219396 kb
Host smart-54315899-8db2-4574-aefb-4dfd290ed74e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565169383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.565169383
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1690869098
Short name T414
Test name
Test status
Simulation time 192033363 ps
CPU time 4.76 seconds
Started Aug 07 04:58:43 PM PDT 24
Finished Aug 07 04:58:48 PM PDT 24
Peak memory 215796 kb
Host smart-6bf766ce-03e9-4693-a1d1-147f8867d14f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690869098 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1690869098
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1768815732
Short name T390
Test name
Test status
Simulation time 305091213 ps
CPU time 4.96 seconds
Started Aug 07 04:59:00 PM PDT 24
Finished Aug 07 04:59:05 PM PDT 24
Peak memory 211152 kb
Host smart-08b95a44-9805-4da2-993a-fb8f8af5ffb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768815732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1768815732
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2353114371
Short name T391
Test name
Test status
Simulation time 1230518819 ps
CPU time 5.56 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:58:47 PM PDT 24
Peak memory 219396 kb
Host smart-86fcbb73-9a4a-43d2-85e1-75b53835c76d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353114371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2353114371
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1415079212
Short name T356
Test name
Test status
Simulation time 261651949 ps
CPU time 8.63 seconds
Started Aug 07 04:58:57 PM PDT 24
Finished Aug 07 04:59:06 PM PDT 24
Peak memory 219568 kb
Host smart-d7cd6ed0-72a1-4bed-84e5-5c95f6b15a62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415079212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1415079212
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4048933152
Short name T419
Test name
Test status
Simulation time 312406793 ps
CPU time 68.66 seconds
Started Aug 07 04:58:43 PM PDT 24
Finished Aug 07 04:59:52 PM PDT 24
Peak memory 213120 kb
Host smart-5261aaeb-1cae-4c83-81b6-d5f994544294
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048933152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.4048933152
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1383539341
Short name T381
Test name
Test status
Simulation time 102012319 ps
CPU time 5.32 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:58:47 PM PDT 24
Peak memory 215896 kb
Host smart-0b496de3-1e71-4cd9-81dc-1df74e86fb8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383539341 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1383539341
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1830618300
Short name T366
Test name
Test status
Simulation time 142783572 ps
CPU time 6.79 seconds
Started Aug 07 04:58:43 PM PDT 24
Finished Aug 07 04:58:50 PM PDT 24
Peak memory 211336 kb
Host smart-e0e55499-2190-40e7-817a-7de9ec9b58ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830618300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1830618300
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.240828058
Short name T353
Test name
Test status
Simulation time 1703934497 ps
CPU time 12.28 seconds
Started Aug 07 04:58:58 PM PDT 24
Finished Aug 07 04:59:10 PM PDT 24
Peak memory 216544 kb
Host smart-01626498-253e-4696-b0c1-f424de72d51b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240828058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.240828058
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1880179240
Short name T50
Test name
Test status
Simulation time 2249118080 ps
CPU time 68.59 seconds
Started Aug 07 04:58:44 PM PDT 24
Finished Aug 07 04:59:52 PM PDT 24
Peak memory 219540 kb
Host smart-126fb804-3d35-43a7-8f57-aff908579eca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880179240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1880179240
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.381262006
Short name T344
Test name
Test status
Simulation time 524577185 ps
CPU time 7.77 seconds
Started Aug 07 04:58:40 PM PDT 24
Finished Aug 07 04:58:48 PM PDT 24
Peak memory 216264 kb
Host smart-209cc057-481c-48bf-9ebc-009a493b77d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381262006 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.381262006
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3206290949
Short name T87
Test name
Test status
Simulation time 130396133 ps
CPU time 4.22 seconds
Started Aug 07 04:58:51 PM PDT 24
Finished Aug 07 04:58:56 PM PDT 24
Peak memory 211148 kb
Host smart-df522df7-543a-4f68-aec0-76dd07fd4963
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206290949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3206290949
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2821262612
Short name T342
Test name
Test status
Simulation time 539092107 ps
CPU time 21.97 seconds
Started Aug 07 04:58:53 PM PDT 24
Finished Aug 07 04:59:16 PM PDT 24
Peak memory 211248 kb
Host smart-74759dfa-2f25-4ef0-8356-730ea3938b94
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821262612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2821262612
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3261137018
Short name T83
Test name
Test status
Simulation time 337912104 ps
CPU time 4.41 seconds
Started Aug 07 04:58:37 PM PDT 24
Finished Aug 07 04:58:41 PM PDT 24
Peak memory 219472 kb
Host smart-20748a52-8a78-4cb2-8d84-dcd5ff921284
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261137018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3261137018
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3929813816
Short name T385
Test name
Test status
Simulation time 340104874 ps
CPU time 7.45 seconds
Started Aug 07 04:58:55 PM PDT 24
Finished Aug 07 04:59:02 PM PDT 24
Peak memory 216392 kb
Host smart-961b0737-e512-4013-ad51-dffb08b6b946
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929813816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3929813816
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1566797537
Short name T93
Test name
Test status
Simulation time 287641077 ps
CPU time 69.02 seconds
Started Aug 07 04:58:33 PM PDT 24
Finished Aug 07 04:59:42 PM PDT 24
Peak memory 213024 kb
Host smart-3a43ecbe-12c1-4328-9a1e-9630dacfa708
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566797537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1566797537
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3818747942
Short name T369
Test name
Test status
Simulation time 108312905 ps
CPU time 4.93 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:58:46 PM PDT 24
Peak memory 215088 kb
Host smart-b21afdaf-673f-47e3-bf64-aa4f7d964f66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818747942 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3818747942
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3109844123
Short name T377
Test name
Test status
Simulation time 86318502 ps
CPU time 4.1 seconds
Started Aug 07 04:58:40 PM PDT 24
Finished Aug 07 04:58:44 PM PDT 24
Peak memory 219328 kb
Host smart-822c79b8-df09-458d-80f4-7c1e627c255f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109844123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3109844123
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3738888019
Short name T374
Test name
Test status
Simulation time 309066215 ps
CPU time 4.37 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:58:45 PM PDT 24
Peak memory 219448 kb
Host smart-8700d87d-b13d-4f43-b5e0-6cff1554be7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738888019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3738888019
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3885927030
Short name T403
Test name
Test status
Simulation time 168240881 ps
CPU time 6.07 seconds
Started Aug 07 04:58:55 PM PDT 24
Finished Aug 07 04:59:02 PM PDT 24
Peak memory 219504 kb
Host smart-6cbaed35-8dc0-41f8-b3be-7514b51fc01d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885927030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3885927030
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.952801774
Short name T101
Test name
Test status
Simulation time 559624441 ps
CPU time 36.52 seconds
Started Aug 07 04:58:40 PM PDT 24
Finished Aug 07 04:59:17 PM PDT 24
Peak memory 219476 kb
Host smart-14ce0d06-38b0-4ec9-bc4f-659ef7182bd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952801774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.952801774
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.661072786
Short name T341
Test name
Test status
Simulation time 413577683 ps
CPU time 4.8 seconds
Started Aug 07 04:58:59 PM PDT 24
Finished Aug 07 04:59:03 PM PDT 24
Peak memory 215412 kb
Host smart-42194bb9-4008-4163-b8d7-65d2e3398977
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661072786 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.661072786
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3643910617
Short name T365
Test name
Test status
Simulation time 272809807 ps
CPU time 5.02 seconds
Started Aug 07 04:58:56 PM PDT 24
Finished Aug 07 04:59:01 PM PDT 24
Peak memory 211140 kb
Host smart-5e3fd948-e639-437d-8369-6c282b02cbc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643910617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3643910617
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3216899224
Short name T361
Test name
Test status
Simulation time 334262912 ps
CPU time 4.09 seconds
Started Aug 07 04:58:54 PM PDT 24
Finished Aug 07 04:58:58 PM PDT 24
Peak memory 219332 kb
Host smart-c3238aad-6c33-4134-93fc-12f21b10728a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216899224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3216899224
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.120481625
Short name T375
Test name
Test status
Simulation time 88962017 ps
CPU time 6.64 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:58:48 PM PDT 24
Peak memory 216260 kb
Host smart-8d653bbd-1f84-4b8a-a2e6-d1853278bb8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120481625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.120481625
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3307075050
Short name T373
Test name
Test status
Simulation time 153150505 ps
CPU time 6.92 seconds
Started Aug 07 04:58:46 PM PDT 24
Finished Aug 07 04:58:53 PM PDT 24
Peak memory 216608 kb
Host smart-fe94bc7f-e90a-41e5-8947-8fb9f3ebfbc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307075050 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3307075050
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2041215323
Short name T382
Test name
Test status
Simulation time 89006577 ps
CPU time 4.07 seconds
Started Aug 07 04:58:46 PM PDT 24
Finished Aug 07 04:58:50 PM PDT 24
Peak memory 217972 kb
Host smart-ab1d7465-36c0-4654-b1a4-cddbcf78a858
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041215323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2041215323
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.122975679
Short name T54
Test name
Test status
Simulation time 419788641 ps
CPU time 4.26 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:58:46 PM PDT 24
Peak memory 211220 kb
Host smart-8fe3d496-10c1-4878-bc91-408a7aadff2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122975679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.122975679
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.388050799
Short name T421
Test name
Test status
Simulation time 478494887 ps
CPU time 7.19 seconds
Started Aug 07 04:58:43 PM PDT 24
Finished Aug 07 04:58:50 PM PDT 24
Peak memory 216124 kb
Host smart-d039eaf4-cad8-4f07-b41f-390b60c203cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388050799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.388050799
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4250494380
Short name T97
Test name
Test status
Simulation time 798684616 ps
CPU time 76.18 seconds
Started Aug 07 04:58:43 PM PDT 24
Finished Aug 07 04:59:59 PM PDT 24
Peak memory 213996 kb
Host smart-26bbca6f-bb78-4487-bdc2-45dd05855bc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250494380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.4250494380
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3560871744
Short name T412
Test name
Test status
Simulation time 141426735 ps
CPU time 5.54 seconds
Started Aug 07 04:58:58 PM PDT 24
Finished Aug 07 04:59:04 PM PDT 24
Peak memory 215108 kb
Host smart-37d9075a-9269-4325-8c55-54dcab009704
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560871744 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3560871744
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2272515680
Short name T65
Test name
Test status
Simulation time 126564515 ps
CPU time 4.99 seconds
Started Aug 07 04:58:59 PM PDT 24
Finished Aug 07 04:59:04 PM PDT 24
Peak memory 211152 kb
Host smart-97285a35-8197-4df5-8c1c-9bbbad7ce436
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272515680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2272515680
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1220710272
Short name T350
Test name
Test status
Simulation time 381106122 ps
CPU time 18.3 seconds
Started Aug 07 04:58:40 PM PDT 24
Finished Aug 07 04:58:58 PM PDT 24
Peak memory 211380 kb
Host smart-90c7571f-d654-4724-822b-b2c4271a58e9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220710272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1220710272
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3795430841
Short name T400
Test name
Test status
Simulation time 89580959 ps
CPU time 4.32 seconds
Started Aug 07 04:59:00 PM PDT 24
Finished Aug 07 04:59:05 PM PDT 24
Peak memory 219368 kb
Host smart-5d072538-a844-4719-affb-0a154cb7f8c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795430841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3795430841
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1868514420
Short name T401
Test name
Test status
Simulation time 159829409 ps
CPU time 9.27 seconds
Started Aug 07 04:58:39 PM PDT 24
Finished Aug 07 04:58:48 PM PDT 24
Peak memory 219600 kb
Host smart-1b9390e5-a5e4-4f0b-bf36-6bdc096a26bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868514420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1868514420
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2322720284
Short name T51
Test name
Test status
Simulation time 196709921 ps
CPU time 36.93 seconds
Started Aug 07 04:58:56 PM PDT 24
Finished Aug 07 04:59:33 PM PDT 24
Peak memory 212848 kb
Host smart-a330a541-06ac-4f60-88f4-dc02095493f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322720284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2322720284
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1783422411
Short name T346
Test name
Test status
Simulation time 482044496 ps
CPU time 6.19 seconds
Started Aug 07 04:58:46 PM PDT 24
Finished Aug 07 04:58:52 PM PDT 24
Peak memory 219552 kb
Host smart-061de2b6-e7c3-4570-b3ed-bb2dac14000d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783422411 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1783422411
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.837648458
Short name T81
Test name
Test status
Simulation time 88940680 ps
CPU time 4.07 seconds
Started Aug 07 04:58:46 PM PDT 24
Finished Aug 07 04:58:51 PM PDT 24
Peak memory 211224 kb
Host smart-512cfee3-b490-4f33-88fc-a32e08e11e10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837648458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.837648458
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3459099164
Short name T84
Test name
Test status
Simulation time 415107150 ps
CPU time 4.35 seconds
Started Aug 07 04:58:50 PM PDT 24
Finished Aug 07 04:58:54 PM PDT 24
Peak memory 211348 kb
Host smart-db6ad13e-ede2-4171-8549-a10ca56b48a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459099164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3459099164
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2758388682
Short name T349
Test name
Test status
Simulation time 145553375 ps
CPU time 8.86 seconds
Started Aug 07 04:58:56 PM PDT 24
Finished Aug 07 04:59:05 PM PDT 24
Peak memory 219568 kb
Host smart-704c6828-ecb4-4cfe-a731-8eddda245fb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758388682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2758388682
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3765134148
Short name T339
Test name
Test status
Simulation time 105112875 ps
CPU time 5.13 seconds
Started Aug 07 04:58:47 PM PDT 24
Finished Aug 07 04:58:52 PM PDT 24
Peak memory 219520 kb
Host smart-842729ae-58ec-4c7a-b522-8fe9504c8f33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765134148 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3765134148
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4251803917
Short name T88
Test name
Test status
Simulation time 86490212 ps
CPU time 4.21 seconds
Started Aug 07 04:59:07 PM PDT 24
Finished Aug 07 04:59:12 PM PDT 24
Peak memory 218188 kb
Host smart-3eaccfd8-3bda-4846-bb4f-4c98a8aa4b6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251803917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.4251803917
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.610689554
Short name T413
Test name
Test status
Simulation time 89734213 ps
CPU time 4.31 seconds
Started Aug 07 04:58:51 PM PDT 24
Finished Aug 07 04:58:55 PM PDT 24
Peak memory 211328 kb
Host smart-730dfe3b-7665-465d-8695-41879725a5a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610689554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.610689554
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2721576013
Short name T334
Test name
Test status
Simulation time 1036855742 ps
CPU time 8.57 seconds
Started Aug 07 04:58:45 PM PDT 24
Finished Aug 07 04:58:54 PM PDT 24
Peak memory 219572 kb
Host smart-240ea45e-57e0-48ed-ab9d-20e3dcf4e1ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721576013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2721576013
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2338897526
Short name T415
Test name
Test status
Simulation time 730004496 ps
CPU time 36.45 seconds
Started Aug 07 04:58:52 PM PDT 24
Finished Aug 07 04:59:28 PM PDT 24
Peak memory 212692 kb
Host smart-8e49d70b-d305-4634-806b-91b17f68dc1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338897526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2338897526
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3817476517
Short name T370
Test name
Test status
Simulation time 133660060 ps
CPU time 5.07 seconds
Started Aug 07 04:58:32 PM PDT 24
Finished Aug 07 04:58:37 PM PDT 24
Peak memory 211140 kb
Host smart-c32164b4-1a90-4b12-b035-8d27adae6535
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817476517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3817476517
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1767098302
Short name T392
Test name
Test status
Simulation time 500174274 ps
CPU time 5.22 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:58:47 PM PDT 24
Peak memory 211156 kb
Host smart-1c942501-e799-44a3-9efa-9a13742c5986
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767098302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1767098302
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1529567217
Short name T405
Test name
Test status
Simulation time 527273358 ps
CPU time 6.57 seconds
Started Aug 07 04:58:43 PM PDT 24
Finished Aug 07 04:58:50 PM PDT 24
Peak memory 211240 kb
Host smart-1bd4d3e6-b27b-4cfc-966b-4cf5375f7799
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529567217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1529567217
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4188432734
Short name T398
Test name
Test status
Simulation time 277977027 ps
CPU time 6.21 seconds
Started Aug 07 04:58:38 PM PDT 24
Finished Aug 07 04:58:44 PM PDT 24
Peak memory 219572 kb
Host smart-0b7d2283-5030-40c5-aecc-ca84b0bee3fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188432734 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4188432734
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4063523004
Short name T399
Test name
Test status
Simulation time 446331730 ps
CPU time 5.04 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:58:46 PM PDT 24
Peak memory 218588 kb
Host smart-e99cf8a8-d847-47b9-93db-383f5775e8a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063523004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.4063523004
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1687757858
Short name T404
Test name
Test status
Simulation time 336694305 ps
CPU time 4.16 seconds
Started Aug 07 04:58:39 PM PDT 24
Finished Aug 07 04:58:43 PM PDT 24
Peak memory 211172 kb
Host smart-e6ff204c-fa69-4c20-8c8a-f4b9f20158f7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687757858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1687757858
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1341391487
Short name T402
Test name
Test status
Simulation time 186955921 ps
CPU time 4.12 seconds
Started Aug 07 04:58:39 PM PDT 24
Finished Aug 07 04:58:44 PM PDT 24
Peak memory 211152 kb
Host smart-15caec64-d8bf-4aea-951b-f6c8db012e07
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341391487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1341391487
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2354139100
Short name T411
Test name
Test status
Simulation time 132796868 ps
CPU time 5.18 seconds
Started Aug 07 04:58:46 PM PDT 24
Finished Aug 07 04:58:51 PM PDT 24
Peak memory 218488 kb
Host smart-82d46191-cee5-4f7a-b151-2de302bceeeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354139100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2354139100
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2869323607
Short name T355
Test name
Test status
Simulation time 1003695581 ps
CPU time 9.84 seconds
Started Aug 07 04:58:35 PM PDT 24
Finished Aug 07 04:58:45 PM PDT 24
Peak memory 216316 kb
Host smart-f237e779-f8ae-4546-b3f1-add59b1dd854
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869323607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2869323607
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.438813531
Short name T91
Test name
Test status
Simulation time 240347519 ps
CPU time 37.93 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:59:19 PM PDT 24
Peak memory 214008 kb
Host smart-92c7b40f-a720-40fb-8979-4badb5c030b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438813531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.438813531
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.659880087
Short name T79
Test name
Test status
Simulation time 182470473 ps
CPU time 4.23 seconds
Started Aug 07 04:58:45 PM PDT 24
Finished Aug 07 04:58:49 PM PDT 24
Peak memory 211484 kb
Host smart-081ce58e-2c98-45d8-b077-0270009b0726
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659880087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.659880087
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3625442020
Short name T420
Test name
Test status
Simulation time 336551131 ps
CPU time 4.2 seconds
Started Aug 07 04:58:40 PM PDT 24
Finished Aug 07 04:58:44 PM PDT 24
Peak memory 219444 kb
Host smart-ad78bd4a-49b7-4cf5-ac5f-4b0120f20345
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625442020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3625442020
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3779845844
Short name T347
Test name
Test status
Simulation time 265886762 ps
CPU time 6.56 seconds
Started Aug 07 04:58:40 PM PDT 24
Finished Aug 07 04:58:47 PM PDT 24
Peak memory 211484 kb
Host smart-036e5cf2-0341-4142-b3ef-42fd3633945c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779845844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3779845844
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1288975534
Short name T368
Test name
Test status
Simulation time 141839264 ps
CPU time 5.82 seconds
Started Aug 07 04:58:54 PM PDT 24
Finished Aug 07 04:59:00 PM PDT 24
Peak memory 215956 kb
Host smart-4c7b9996-d4e6-4ead-8076-4903adf62fba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288975534 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1288975534
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4086583354
Short name T379
Test name
Test status
Simulation time 491379800 ps
CPU time 7.15 seconds
Started Aug 07 04:58:37 PM PDT 24
Finished Aug 07 04:58:44 PM PDT 24
Peak memory 217752 kb
Host smart-5ab48195-cfd9-4873-b454-bb2439f88a25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086583354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.4086583354
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1038405953
Short name T406
Test name
Test status
Simulation time 524433169 ps
CPU time 5.05 seconds
Started Aug 07 04:58:38 PM PDT 24
Finished Aug 07 04:58:43 PM PDT 24
Peak memory 211368 kb
Host smart-29f0be65-be26-4f6a-acd7-87a37f53afe1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038405953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1038405953
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2095898670
Short name T336
Test name
Test status
Simulation time 130932145 ps
CPU time 5.26 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:58:46 PM PDT 24
Peak memory 211184 kb
Host smart-7dc1b95e-40d3-4bbf-b240-91dc5a5d129a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095898670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2095898670
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4062422027
Short name T61
Test name
Test status
Simulation time 2625007672 ps
CPU time 22.43 seconds
Started Aug 07 04:58:33 PM PDT 24
Finished Aug 07 04:59:00 PM PDT 24
Peak memory 211440 kb
Host smart-2ac4359c-a223-4aa4-9f9d-8acb43f7dde0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062422027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.4062422027
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2108252894
Short name T53
Test name
Test status
Simulation time 87130559 ps
CPU time 4.26 seconds
Started Aug 07 04:58:29 PM PDT 24
Finished Aug 07 04:58:34 PM PDT 24
Peak memory 218580 kb
Host smart-a7a39a0f-c7ea-4f3f-912b-f9e62e19b192
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108252894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2108252894
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2496803737
Short name T348
Test name
Test status
Simulation time 324222771 ps
CPU time 7.54 seconds
Started Aug 07 04:58:40 PM PDT 24
Finished Aug 07 04:58:48 PM PDT 24
Peak memory 219620 kb
Host smart-d968cfe7-873f-4a23-a666-4e50a1491150
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496803737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2496803737
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1456672045
Short name T95
Test name
Test status
Simulation time 570765869 ps
CPU time 35.46 seconds
Started Aug 07 04:58:49 PM PDT 24
Finished Aug 07 04:59:24 PM PDT 24
Peak memory 219352 kb
Host smart-14365eac-0108-471c-b49c-3aa9ac0a6bfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456672045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1456672045
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1268486935
Short name T80
Test name
Test status
Simulation time 356872513 ps
CPU time 5.03 seconds
Started Aug 07 04:58:39 PM PDT 24
Finished Aug 07 04:58:44 PM PDT 24
Peak memory 211224 kb
Host smart-20f5c333-c8d3-47cb-98b4-99788c13f4d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268486935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1268486935
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2966325228
Short name T387
Test name
Test status
Simulation time 498570784 ps
CPU time 5.37 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:58:46 PM PDT 24
Peak memory 211248 kb
Host smart-40b46e53-4e0c-4b63-b34f-757742b64c32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966325228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2966325228
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4255957166
Short name T352
Test name
Test status
Simulation time 2512948409 ps
CPU time 6.66 seconds
Started Aug 07 04:58:28 PM PDT 24
Finished Aug 07 04:58:35 PM PDT 24
Peak memory 211248 kb
Host smart-dbe74147-cd7c-42bb-8f9a-daf399cd9e32
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255957166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4255957166
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3239442590
Short name T409
Test name
Test status
Simulation time 1331012821 ps
CPU time 5.39 seconds
Started Aug 07 04:58:39 PM PDT 24
Finished Aug 07 04:58:44 PM PDT 24
Peak memory 216140 kb
Host smart-4b5a0fc8-cf2e-4098-98aa-dae7b1b38c48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239442590 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3239442590
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2133132766
Short name T410
Test name
Test status
Simulation time 174971091 ps
CPU time 4.13 seconds
Started Aug 07 04:58:32 PM PDT 24
Finished Aug 07 04:58:37 PM PDT 24
Peak memory 219404 kb
Host smart-5090d629-0bb6-4d6f-b50e-b8675d30aaa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133132766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2133132766
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1782568813
Short name T371
Test name
Test status
Simulation time 88356474 ps
CPU time 4.21 seconds
Started Aug 07 04:58:53 PM PDT 24
Finished Aug 07 04:58:58 PM PDT 24
Peak memory 211024 kb
Host smart-3397531e-563b-47ad-b041-1690e774de9c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782568813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1782568813
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2609522592
Short name T343
Test name
Test status
Simulation time 493780172 ps
CPU time 7.06 seconds
Started Aug 07 04:58:36 PM PDT 24
Finished Aug 07 04:58:44 PM PDT 24
Peak memory 211120 kb
Host smart-6d0c2b00-e9e2-4366-bee0-76436952d5fe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609522592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2609522592
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.261012687
Short name T78
Test name
Test status
Simulation time 682336137 ps
CPU time 27.28 seconds
Started Aug 07 04:58:51 PM PDT 24
Finished Aug 07 04:59:19 PM PDT 24
Peak memory 211340 kb
Host smart-2cc9a4e1-d645-46a7-9bcb-ddc74682fc8c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261012687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.261012687
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1082498628
Short name T360
Test name
Test status
Simulation time 87521289 ps
CPU time 4.32 seconds
Started Aug 07 04:58:38 PM PDT 24
Finished Aug 07 04:58:43 PM PDT 24
Peak memory 219440 kb
Host smart-4ee5952a-a868-4e0a-a840-83880b0df168
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082498628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1082498628
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2696146285
Short name T354
Test name
Test status
Simulation time 85811904 ps
CPU time 6.62 seconds
Started Aug 07 04:58:28 PM PDT 24
Finished Aug 07 04:58:35 PM PDT 24
Peak memory 215296 kb
Host smart-605ddf56-ce82-443e-8d05-8987058b91de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696146285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2696146285
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2866251006
Short name T389
Test name
Test status
Simulation time 574137944 ps
CPU time 35.86 seconds
Started Aug 07 04:59:01 PM PDT 24
Finished Aug 07 04:59:37 PM PDT 24
Peak memory 211588 kb
Host smart-7c495c2e-c61b-45f5-898a-5f1dede7b2d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866251006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2866251006
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3424549316
Short name T384
Test name
Test status
Simulation time 418421225 ps
CPU time 5.13 seconds
Started Aug 07 04:58:29 PM PDT 24
Finished Aug 07 04:58:35 PM PDT 24
Peak memory 215840 kb
Host smart-73ed60f4-58a6-44b3-bbf8-078d2627a598
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424549316 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3424549316
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3085832709
Short name T423
Test name
Test status
Simulation time 378837039 ps
CPU time 4.16 seconds
Started Aug 07 04:58:39 PM PDT 24
Finished Aug 07 04:58:43 PM PDT 24
Peak memory 219376 kb
Host smart-e4da862c-1d44-40a9-afff-a865d31a8af0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085832709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3085832709
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3489542800
Short name T396
Test name
Test status
Simulation time 233875672 ps
CPU time 5.22 seconds
Started Aug 07 04:58:38 PM PDT 24
Finished Aug 07 04:58:44 PM PDT 24
Peak memory 211324 kb
Host smart-be76bdf6-4224-4315-8af5-3e371e57a966
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489542800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3489542800
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2716347327
Short name T395
Test name
Test status
Simulation time 133480291 ps
CPU time 9.08 seconds
Started Aug 07 04:58:49 PM PDT 24
Finished Aug 07 04:58:58 PM PDT 24
Peak memory 216764 kb
Host smart-0bc534ba-96f2-4bd1-8cd0-49bbdb6b2b3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716347327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2716347327
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1298621979
Short name T92
Test name
Test status
Simulation time 505839658 ps
CPU time 69.65 seconds
Started Aug 07 04:58:30 PM PDT 24
Finished Aug 07 04:59:40 PM PDT 24
Peak memory 219324 kb
Host smart-2acee44b-672c-49b1-b915-b4235e645465
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298621979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1298621979
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.26399667
Short name T408
Test name
Test status
Simulation time 413156636 ps
CPU time 5.09 seconds
Started Aug 07 04:58:37 PM PDT 24
Finished Aug 07 04:58:42 PM PDT 24
Peak memory 219568 kb
Host smart-e3c06f0e-1077-4911-bc77-35a4af2657e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26399667 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.26399667
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.790127600
Short name T367
Test name
Test status
Simulation time 129909626 ps
CPU time 4.94 seconds
Started Aug 07 04:58:27 PM PDT 24
Finished Aug 07 04:58:32 PM PDT 24
Peak memory 217780 kb
Host smart-f899477b-079f-473b-960d-521bf8af8329
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790127600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.790127600
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1659656368
Short name T63
Test name
Test status
Simulation time 1436927865 ps
CPU time 19.13 seconds
Started Aug 07 04:58:47 PM PDT 24
Finished Aug 07 04:59:07 PM PDT 24
Peak memory 211348 kb
Host smart-d2d68ede-0c76-40ac-9ecb-4dc307457ec8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659656368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1659656368
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.634251759
Short name T66
Test name
Test status
Simulation time 518035198 ps
CPU time 4.96 seconds
Started Aug 07 04:58:36 PM PDT 24
Finished Aug 07 04:58:41 PM PDT 24
Peak memory 218500 kb
Host smart-a3f4a725-d7a6-40a5-b2ed-705d2a6a9ba2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634251759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.634251759
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1100739578
Short name T376
Test name
Test status
Simulation time 98417556 ps
CPU time 7.34 seconds
Started Aug 07 04:58:49 PM PDT 24
Finished Aug 07 04:58:56 PM PDT 24
Peak memory 219624 kb
Host smart-15bd8d5c-d4c7-42b5-8263-0b31b61e1b46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100739578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1100739578
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4120751174
Short name T103
Test name
Test status
Simulation time 2401633003 ps
CPU time 69.82 seconds
Started Aug 07 04:58:40 PM PDT 24
Finished Aug 07 04:59:50 PM PDT 24
Peak memory 213156 kb
Host smart-c5800f25-aa5b-412c-9781-5a1a5bf80da5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120751174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.4120751174
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4248748240
Short name T337
Test name
Test status
Simulation time 264010448 ps
CPU time 5.28 seconds
Started Aug 07 04:58:49 PM PDT 24
Finished Aug 07 04:58:54 PM PDT 24
Peak memory 219468 kb
Host smart-8746f828-cda0-4c18-b252-6129a7ea8bdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248748240 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4248748240
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.587432257
Short name T75
Test name
Test status
Simulation time 278910858 ps
CPU time 5 seconds
Started Aug 07 04:58:38 PM PDT 24
Finished Aug 07 04:58:43 PM PDT 24
Peak memory 211248 kb
Host smart-9c76a04f-6e96-478b-bc1e-abc2ccabebe3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587432257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.587432257
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1552725561
Short name T85
Test name
Test status
Simulation time 347780181 ps
CPU time 4.51 seconds
Started Aug 07 04:58:34 PM PDT 24
Finished Aug 07 04:58:38 PM PDT 24
Peak memory 211312 kb
Host smart-52c28284-1ffc-4616-84a7-c2af6a64c0c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552725561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1552725561
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.627420342
Short name T335
Test name
Test status
Simulation time 1246326784 ps
CPU time 7.4 seconds
Started Aug 07 04:58:30 PM PDT 24
Finished Aug 07 04:58:37 PM PDT 24
Peak memory 219616 kb
Host smart-4a12491b-b3fa-4aad-ab56-fae68af8931f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627420342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.627420342
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3716383662
Short name T98
Test name
Test status
Simulation time 611751030 ps
CPU time 36.06 seconds
Started Aug 07 04:58:39 PM PDT 24
Finished Aug 07 04:59:16 PM PDT 24
Peak memory 212956 kb
Host smart-0ab9e59d-49b9-4bd6-8406-6fd7dfa1938f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716383662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3716383662
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3509608923
Short name T418
Test name
Test status
Simulation time 528759461 ps
CPU time 5.25 seconds
Started Aug 07 04:58:39 PM PDT 24
Finished Aug 07 04:58:44 PM PDT 24
Peak memory 219480 kb
Host smart-5ac1886c-b77f-4265-80d5-cabf80d4d322
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509608923 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3509608923
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3236212235
Short name T364
Test name
Test status
Simulation time 150677729 ps
CPU time 5.1 seconds
Started Aug 07 04:58:31 PM PDT 24
Finished Aug 07 04:58:36 PM PDT 24
Peak memory 211200 kb
Host smart-1d2f0f77-c69e-4c15-b4ae-1736d4668926
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236212235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3236212235
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.726468811
Short name T74
Test name
Test status
Simulation time 376186488 ps
CPU time 18.49 seconds
Started Aug 07 04:58:34 PM PDT 24
Finished Aug 07 04:58:52 PM PDT 24
Peak memory 211300 kb
Host smart-99200a08-11c8-4e83-9103-3406822b5e23
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726468811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.726468811
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.614255071
Short name T383
Test name
Test status
Simulation time 660133701 ps
CPU time 5.12 seconds
Started Aug 07 04:58:32 PM PDT 24
Finished Aug 07 04:58:37 PM PDT 24
Peak memory 211352 kb
Host smart-0165c400-126b-432b-a5e8-1e3189f7949d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614255071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.614255071
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2978499002
Short name T351
Test name
Test status
Simulation time 515401803 ps
CPU time 7.77 seconds
Started Aug 07 04:58:56 PM PDT 24
Finished Aug 07 04:59:04 PM PDT 24
Peak memory 217392 kb
Host smart-6f4beef4-0295-4ea7-9eb6-477f31e05db2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978499002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2978499002
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1729856689
Short name T416
Test name
Test status
Simulation time 372784051 ps
CPU time 36.7 seconds
Started Aug 07 04:58:39 PM PDT 24
Finished Aug 07 04:59:16 PM PDT 24
Peak memory 211908 kb
Host smart-4965d52b-f9ac-4dc1-9529-080372e0c284
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729856689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1729856689
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3604691403
Short name T380
Test name
Test status
Simulation time 524205384 ps
CPU time 5.47 seconds
Started Aug 07 04:58:49 PM PDT 24
Finished Aug 07 04:58:55 PM PDT 24
Peak memory 214140 kb
Host smart-a592764a-e6b4-4ba8-8c29-cff66905a20f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604691403 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3604691403
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3384682046
Short name T417
Test name
Test status
Simulation time 756122056 ps
CPU time 4.21 seconds
Started Aug 07 04:58:47 PM PDT 24
Finished Aug 07 04:58:51 PM PDT 24
Peak memory 211240 kb
Host smart-2a1aaf67-4e92-4c9f-b4fb-e7c59fdb1e02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384682046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3384682046
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4094420449
Short name T82
Test name
Test status
Simulation time 85566277 ps
CPU time 4.23 seconds
Started Aug 07 04:58:50 PM PDT 24
Finished Aug 07 04:58:54 PM PDT 24
Peak memory 211184 kb
Host smart-e01c9274-8be0-416c-b007-7cc98cfe002e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094420449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.4094420449
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.965201100
Short name T407
Test name
Test status
Simulation time 660169444 ps
CPU time 10.34 seconds
Started Aug 07 04:58:33 PM PDT 24
Finished Aug 07 04:58:44 PM PDT 24
Peak memory 217580 kb
Host smart-a13c25cf-a3d3-4c14-b960-c1c4547c2b64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965201100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.965201100
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.832791118
Short name T100
Test name
Test status
Simulation time 2075012355 ps
CPU time 45.07 seconds
Started Aug 07 04:58:32 PM PDT 24
Finished Aug 07 04:59:23 PM PDT 24
Peak memory 219484 kb
Host smart-54653e6e-0787-451d-ac3d-9e6000dbf345
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832791118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.832791118
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.986400774
Short name T108
Test name
Test status
Simulation time 497686929 ps
CPU time 5.18 seconds
Started Aug 07 04:58:34 PM PDT 24
Finished Aug 07 04:58:39 PM PDT 24
Peak memory 212028 kb
Host smart-6e383de9-52e9-4a4a-a051-87714a079787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986400774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.986400774
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.578440589
Short name T135
Test name
Test status
Simulation time 2280852495 ps
CPU time 128.46 seconds
Started Aug 07 04:57:58 PM PDT 24
Finished Aug 07 05:00:07 PM PDT 24
Peak memory 229080 kb
Host smart-e149abdc-fc51-49eb-84d3-af5b7cb0958f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578440589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.578440589
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3435634833
Short name T175
Test name
Test status
Simulation time 893505296 ps
CPU time 11.2 seconds
Started Aug 07 04:57:57 PM PDT 24
Finished Aug 07 04:58:08 PM PDT 24
Peak memory 212924 kb
Host smart-2ddd3c14-d76d-4adf-9eae-fc75c4b54361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435634833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3435634833
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2828622342
Short name T29
Test name
Test status
Simulation time 517906164 ps
CPU time 9.03 seconds
Started Aug 07 04:57:50 PM PDT 24
Finished Aug 07 04:57:59 PM PDT 24
Peak memory 212160 kb
Host smart-69084fe9-ac82-447e-a764-78fc9dc1ddb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2828622342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2828622342
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3539482485
Short name T19
Test name
Test status
Simulation time 764101593 ps
CPU time 53.2 seconds
Started Aug 07 04:58:38 PM PDT 24
Finished Aug 07 04:59:31 PM PDT 24
Peak memory 237300 kb
Host smart-d99766fe-9f2f-4c62-a0c5-8dba97c4d911
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539482485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3539482485
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.756930871
Short name T236
Test name
Test status
Simulation time 544050419 ps
CPU time 6.41 seconds
Started Aug 07 04:57:55 PM PDT 24
Finished Aug 07 04:58:01 PM PDT 24
Peak memory 212152 kb
Host smart-b57c6314-908d-460b-a761-593d846b422a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756930871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.756930871
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.485107534
Short name T190
Test name
Test status
Simulation time 174876972 ps
CPU time 4.32 seconds
Started Aug 07 04:57:51 PM PDT 24
Finished Aug 07 04:57:55 PM PDT 24
Peak memory 211872 kb
Host smart-28126bd3-7638-4555-8bd8-7f657c712bf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485107534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.485107534
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4121902976
Short name T204
Test name
Test status
Simulation time 8453235728 ps
CPU time 136.62 seconds
Started Aug 07 04:57:52 PM PDT 24
Finished Aug 07 05:00:08 PM PDT 24
Peak memory 215872 kb
Host smart-e7523b2f-dff9-4612-a109-9d1613a2b45b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121902976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.4121902976
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2683038857
Short name T292
Test name
Test status
Simulation time 1040424511 ps
CPU time 11.39 seconds
Started Aug 07 04:57:51 PM PDT 24
Finished Aug 07 04:58:02 PM PDT 24
Peak memory 212856 kb
Host smart-98356bec-a78a-4d02-9a65-79e1b585ab84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683038857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2683038857
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3940523763
Short name T117
Test name
Test status
Simulation time 142499611 ps
CPU time 6.54 seconds
Started Aug 07 04:57:56 PM PDT 24
Finished Aug 07 04:58:03 PM PDT 24
Peak memory 212036 kb
Host smart-a771b3d4-a87c-4cbb-b22e-8dd9c780d8e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3940523763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3940523763
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3796820495
Short name T25
Test name
Test status
Simulation time 1523411510 ps
CPU time 52.62 seconds
Started Aug 07 04:57:55 PM PDT 24
Finished Aug 07 04:58:48 PM PDT 24
Peak memory 237292 kb
Host smart-cc783ae1-3158-467e-bee1-d5a633d488b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796820495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3796820495
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3050261435
Short name T191
Test name
Test status
Simulation time 98270077 ps
CPU time 5.55 seconds
Started Aug 07 04:57:58 PM PDT 24
Finished Aug 07 04:58:03 PM PDT 24
Peak memory 211416 kb
Host smart-5d31566e-7d18-4504-a46b-f15aa0c52a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050261435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3050261435
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.4143923753
Short name T169
Test name
Test status
Simulation time 278319192 ps
CPU time 7.33 seconds
Started Aug 07 04:57:52 PM PDT 24
Finished Aug 07 04:58:00 PM PDT 24
Peak memory 212264 kb
Host smart-82803bf8-5d4e-488a-814a-9da81e23d6ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143923753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.4143923753
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3358312945
Short name T127
Test name
Test status
Simulation time 688757371 ps
CPU time 5.02 seconds
Started Aug 07 04:58:14 PM PDT 24
Finished Aug 07 04:58:19 PM PDT 24
Peak memory 211996 kb
Host smart-a9cb7e0a-a022-4d4f-8b88-a96223c746df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358312945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3358312945
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.11881219
Short name T30
Test name
Test status
Simulation time 2851256559 ps
CPU time 134.86 seconds
Started Aug 07 04:57:48 PM PDT 24
Finished Aug 07 05:00:03 PM PDT 24
Peak memory 213448 kb
Host smart-0fa75d87-3e83-4a54-a9bf-5be38bc1754a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11881219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_co
rrupt_sig_fatal_chk.11881219
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.361466624
Short name T227
Test name
Test status
Simulation time 3097220896 ps
CPU time 11.01 seconds
Started Aug 07 04:57:50 PM PDT 24
Finished Aug 07 04:58:01 PM PDT 24
Peak memory 212984 kb
Host smart-68b25ba8-5283-4a1a-b238-fc509b63f154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361466624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.361466624
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2023875230
Short name T325
Test name
Test status
Simulation time 652193671 ps
CPU time 5.5 seconds
Started Aug 07 04:57:49 PM PDT 24
Finished Aug 07 04:57:54 PM PDT 24
Peak memory 212172 kb
Host smart-2e1e6222-6e19-43e9-8503-82de30318c37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2023875230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2023875230
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4000222657
Short name T243
Test name
Test status
Simulation time 1007189975 ps
CPU time 18.97 seconds
Started Aug 07 04:58:32 PM PDT 24
Finished Aug 07 04:58:51 PM PDT 24
Peak memory 214488 kb
Host smart-c3359e3e-e173-49bf-9fa2-83c2404b77b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000222657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.4000222657
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2497220580
Short name T237
Test name
Test status
Simulation time 1546845182 ps
CPU time 5.02 seconds
Started Aug 07 04:58:07 PM PDT 24
Finished Aug 07 04:58:12 PM PDT 24
Peak memory 211984 kb
Host smart-2415578d-db7c-45bc-b9b6-e18cdfb418e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497220580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2497220580
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1780970902
Short name T131
Test name
Test status
Simulation time 5825915338 ps
CPU time 149.85 seconds
Started Aug 07 04:57:51 PM PDT 24
Finished Aug 07 05:00:21 PM PDT 24
Peak memory 228940 kb
Host smart-4bb0ab8d-e7e0-4a1a-a8d8-77b3fb692aca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780970902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1780970902
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3204778639
Short name T177
Test name
Test status
Simulation time 179035005 ps
CPU time 9.51 seconds
Started Aug 07 04:58:07 PM PDT 24
Finished Aug 07 04:58:16 PM PDT 24
Peak memory 212880 kb
Host smart-6fa0d4ef-4ecf-4977-95a4-897c43fb9b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204778639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3204778639
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1499790425
Short name T273
Test name
Test status
Simulation time 441750400 ps
CPU time 5.33 seconds
Started Aug 07 04:57:56 PM PDT 24
Finished Aug 07 04:58:01 PM PDT 24
Peak memory 212036 kb
Host smart-d513fedc-2a2b-4b94-a566-74c83ce7ebe5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1499790425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1499790425
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1541937127
Short name T109
Test name
Test status
Simulation time 180810361 ps
CPU time 13.62 seconds
Started Aug 07 04:57:51 PM PDT 24
Finished Aug 07 04:58:04 PM PDT 24
Peak memory 212528 kb
Host smart-a09bbd41-9218-4a4c-8e36-e551f3b9ec0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541937127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1541937127
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.332813808
Short name T42
Test name
Test status
Simulation time 72060663638 ps
CPU time 2390.54 seconds
Started Aug 07 04:57:58 PM PDT 24
Finished Aug 07 05:37:49 PM PDT 24
Peak memory 236436 kb
Host smart-823d518b-e644-4c0f-8c5d-9622f676f512
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332813808 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.332813808
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.664942781
Short name T4
Test name
Test status
Simulation time 126446627 ps
CPU time 5.21 seconds
Started Aug 07 04:58:05 PM PDT 24
Finished Aug 07 04:58:10 PM PDT 24
Peak memory 211984 kb
Host smart-44abc147-5f60-4e34-907c-775797f5ef57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664942781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.664942781
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.840589984
Short name T240
Test name
Test status
Simulation time 39507239191 ps
CPU time 157.89 seconds
Started Aug 07 04:57:59 PM PDT 24
Finished Aug 07 05:00:37 PM PDT 24
Peak memory 213556 kb
Host smart-8f8af7d2-ee9e-4c5b-b65a-45b8989821d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840589984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.840589984
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2314622330
Short name T261
Test name
Test status
Simulation time 170306889 ps
CPU time 9.35 seconds
Started Aug 07 04:58:21 PM PDT 24
Finished Aug 07 04:58:30 PM PDT 24
Peak memory 212816 kb
Host smart-339b89db-c727-471d-bcb3-0e32b23997e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314622330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2314622330
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.950359183
Short name T249
Test name
Test status
Simulation time 184427337 ps
CPU time 5.44 seconds
Started Aug 07 04:57:50 PM PDT 24
Finished Aug 07 04:57:56 PM PDT 24
Peak memory 212176 kb
Host smart-7096e4c9-e4bb-4c72-8fd5-3bb8ddf12f5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=950359183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.950359183
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.38859238
Short name T71
Test name
Test status
Simulation time 357377576 ps
CPU time 11.28 seconds
Started Aug 07 04:57:48 PM PDT 24
Finished Aug 07 04:58:00 PM PDT 24
Peak memory 214084 kb
Host smart-eb4f785a-5ea9-4b10-96ad-101266e71631
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38859238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 12.rom_ctrl_stress_all.38859238
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1725583633
Short name T324
Test name
Test status
Simulation time 521407332 ps
CPU time 7.43 seconds
Started Aug 07 04:57:59 PM PDT 24
Finished Aug 07 04:58:06 PM PDT 24
Peak memory 212080 kb
Host smart-459c1cb2-4c14-411c-a967-9d9821c55790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725583633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1725583633
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3812309295
Short name T222
Test name
Test status
Simulation time 3115490344 ps
CPU time 113.63 seconds
Started Aug 07 04:58:01 PM PDT 24
Finished Aug 07 04:59:55 PM PDT 24
Peak memory 238196 kb
Host smart-19f5278f-8791-403f-80f5-1ac8e2c1fc12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812309295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3812309295
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4274893721
Short name T161
Test name
Test status
Simulation time 552100096 ps
CPU time 6.3 seconds
Started Aug 07 04:58:05 PM PDT 24
Finished Aug 07 04:58:11 PM PDT 24
Peak memory 212152 kb
Host smart-aa87e0e4-7e10-4156-82c7-1541b2a1c88f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4274893721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4274893721
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.763990867
Short name T141
Test name
Test status
Simulation time 1113533484 ps
CPU time 16.74 seconds
Started Aug 07 04:58:16 PM PDT 24
Finished Aug 07 04:58:33 PM PDT 24
Peak memory 214824 kb
Host smart-5fc22b3c-f6f0-43a9-997c-e750183a4edc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763990867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.763990867
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.368182339
Short name T124
Test name
Test status
Simulation time 363841013 ps
CPU time 4.19 seconds
Started Aug 07 04:58:10 PM PDT 24
Finished Aug 07 04:58:15 PM PDT 24
Peak memory 211932 kb
Host smart-9b25ac4c-c013-44bb-8e9e-56b38e4d30c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368182339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.368182339
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1717550856
Short name T265
Test name
Test status
Simulation time 7923056497 ps
CPU time 117.55 seconds
Started Aug 07 04:58:20 PM PDT 24
Finished Aug 07 05:00:17 PM PDT 24
Peak memory 226284 kb
Host smart-de9f95b7-f3ae-46b7-8da1-05abd61486f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717550856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1717550856
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.973448135
Short name T214
Test name
Test status
Simulation time 697767050 ps
CPU time 9.47 seconds
Started Aug 07 04:57:59 PM PDT 24
Finished Aug 07 04:58:08 PM PDT 24
Peak memory 212880 kb
Host smart-9ef92aaf-9b2c-480a-a15e-195a0c2cb8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973448135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.973448135
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2231108309
Short name T121
Test name
Test status
Simulation time 98682224 ps
CPU time 5.94 seconds
Started Aug 07 04:58:19 PM PDT 24
Finished Aug 07 04:58:25 PM PDT 24
Peak memory 212152 kb
Host smart-8f3697d5-9057-4c26-8133-c0e8d5649215
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2231108309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2231108309
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2286373042
Short name T295
Test name
Test status
Simulation time 263547698 ps
CPU time 13.07 seconds
Started Aug 07 04:57:59 PM PDT 24
Finished Aug 07 04:58:12 PM PDT 24
Peak memory 214776 kb
Host smart-ed16ddee-2280-4bf6-9292-c7082374860a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286373042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2286373042
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2015701193
Short name T33
Test name
Test status
Simulation time 1655022965 ps
CPU time 4.17 seconds
Started Aug 07 04:58:00 PM PDT 24
Finished Aug 07 04:58:04 PM PDT 24
Peak memory 212044 kb
Host smart-13f08261-a688-4228-8cde-b504bfe3d0e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015701193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2015701193
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4014544068
Short name T143
Test name
Test status
Simulation time 2984349312 ps
CPU time 70.3 seconds
Started Aug 07 04:58:00 PM PDT 24
Finished Aug 07 04:59:11 PM PDT 24
Peak memory 213748 kb
Host smart-15a29154-04ac-4d00-b943-8bb3b717de40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014544068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.4014544068
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3829285835
Short name T114
Test name
Test status
Simulation time 251223049 ps
CPU time 11.35 seconds
Started Aug 07 04:58:11 PM PDT 24
Finished Aug 07 04:58:23 PM PDT 24
Peak memory 212784 kb
Host smart-43598dd7-fb74-43a1-beb8-e92e8c0d6d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829285835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3829285835
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1978449800
Short name T223
Test name
Test status
Simulation time 886805559 ps
CPU time 6.22 seconds
Started Aug 07 04:58:12 PM PDT 24
Finished Aug 07 04:58:18 PM PDT 24
Peak memory 212032 kb
Host smart-2b3ff3b1-1008-4a6b-be4c-7c7f4a550e6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1978449800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1978449800
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3242724478
Short name T188
Test name
Test status
Simulation time 537063423 ps
CPU time 11.53 seconds
Started Aug 07 04:57:58 PM PDT 24
Finished Aug 07 04:58:10 PM PDT 24
Peak memory 213300 kb
Host smart-f803a54e-6bf1-4568-bb3a-8aff9bc8e2cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242724478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3242724478
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2957198023
Short name T189
Test name
Test status
Simulation time 164865244285 ps
CPU time 1668.29 seconds
Started Aug 07 04:57:59 PM PDT 24
Finished Aug 07 05:25:48 PM PDT 24
Peak memory 239020 kb
Host smart-68a66df7-131e-430b-8a29-8867aaaa56fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957198023 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2957198023
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.290057996
Short name T285
Test name
Test status
Simulation time 89250265 ps
CPU time 4.33 seconds
Started Aug 07 04:57:58 PM PDT 24
Finished Aug 07 04:58:03 PM PDT 24
Peak memory 211968 kb
Host smart-85bc6c36-9757-47bf-84cd-52314eecc690
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290057996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.290057996
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3455530069
Short name T201
Test name
Test status
Simulation time 2249199491 ps
CPU time 134.77 seconds
Started Aug 07 04:58:09 PM PDT 24
Finished Aug 07 05:00:24 PM PDT 24
Peak memory 229000 kb
Host smart-ff8a1d13-5509-4656-8301-6f6335bca1e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455530069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3455530069
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.678593352
Short name T167
Test name
Test status
Simulation time 262226543 ps
CPU time 11.01 seconds
Started Aug 07 04:57:58 PM PDT 24
Finished Aug 07 04:58:10 PM PDT 24
Peak memory 212552 kb
Host smart-29226d2d-7219-40f2-8e68-994b65579c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678593352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.678593352
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2081441712
Short name T180
Test name
Test status
Simulation time 273497942 ps
CPU time 6.3 seconds
Started Aug 07 04:57:58 PM PDT 24
Finished Aug 07 04:58:04 PM PDT 24
Peak memory 212160 kb
Host smart-e4515493-f598-4b37-a4cd-2d5468319206
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2081441712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2081441712
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2697490211
Short name T13
Test name
Test status
Simulation time 446014386 ps
CPU time 9.17 seconds
Started Aug 07 04:58:23 PM PDT 24
Finished Aug 07 04:58:32 PM PDT 24
Peak memory 212300 kb
Host smart-8633ec0b-6463-4297-b314-6bbfda96283b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697490211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2697490211
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1734339204
Short name T90
Test name
Test status
Simulation time 19370545919 ps
CPU time 6373.12 seconds
Started Aug 07 04:58:24 PM PDT 24
Finished Aug 07 06:44:38 PM PDT 24
Peak memory 234860 kb
Host smart-3c3e0a6b-9c39-4d4c-9729-d5e7d7ea9846
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734339204 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1734339204
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3523841381
Short name T311
Test name
Test status
Simulation time 621909236 ps
CPU time 5.13 seconds
Started Aug 07 04:58:16 PM PDT 24
Finished Aug 07 04:58:21 PM PDT 24
Peak memory 211936 kb
Host smart-2d5875ea-6116-4133-a0c0-942c1d9b7306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523841381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3523841381
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4091303154
Short name T27
Test name
Test status
Simulation time 2322499027 ps
CPU time 69.24 seconds
Started Aug 07 04:58:00 PM PDT 24
Finished Aug 07 04:59:10 PM PDT 24
Peak memory 237508 kb
Host smart-d01ce9c1-752b-46e8-a899-bbfde81a0e04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091303154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.4091303154
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1826550012
Short name T9
Test name
Test status
Simulation time 1782935201 ps
CPU time 11.14 seconds
Started Aug 07 04:58:01 PM PDT 24
Finished Aug 07 04:58:12 PM PDT 24
Peak memory 212884 kb
Host smart-abd224d6-3139-4bd9-b87f-a0bc974c6cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826550012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1826550012
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2360026130
Short name T318
Test name
Test status
Simulation time 100305838 ps
CPU time 5.73 seconds
Started Aug 07 04:57:58 PM PDT 24
Finished Aug 07 04:58:04 PM PDT 24
Peak memory 212172 kb
Host smart-0fe3d4a5-929a-4b8a-83c1-3348724d14d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2360026130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2360026130
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.4287496442
Short name T115
Test name
Test status
Simulation time 1044853833 ps
CPU time 11.61 seconds
Started Aug 07 04:58:00 PM PDT 24
Finished Aug 07 04:58:12 PM PDT 24
Peak memory 213368 kb
Host smart-a7318ade-f774-48db-a8bd-2061157ff405
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287496442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.4287496442
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1140618125
Short name T32
Test name
Test status
Simulation time 90826692 ps
CPU time 4.26 seconds
Started Aug 07 04:57:59 PM PDT 24
Finished Aug 07 04:58:04 PM PDT 24
Peak memory 211980 kb
Host smart-51dff89b-6847-4987-8155-900a6a7b4656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140618125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1140618125
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2686793839
Short name T160
Test name
Test status
Simulation time 6935045772 ps
CPU time 102.24 seconds
Started Aug 07 04:57:58 PM PDT 24
Finished Aug 07 04:59:40 PM PDT 24
Peak memory 226360 kb
Host smart-23dae579-5ebe-4ca3-b2f7-5287ada70231
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686793839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2686793839
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.895785338
Short name T2
Test name
Test status
Simulation time 407978126 ps
CPU time 9.88 seconds
Started Aug 07 04:58:08 PM PDT 24
Finished Aug 07 04:58:18 PM PDT 24
Peak memory 212936 kb
Host smart-8823e762-2b7e-4095-b25d-f90f05e03997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895785338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.895785338
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.386033238
Short name T203
Test name
Test status
Simulation time 377524449 ps
CPU time 5.67 seconds
Started Aug 07 04:58:00 PM PDT 24
Finished Aug 07 04:58:06 PM PDT 24
Peak memory 212148 kb
Host smart-b720bb9f-5ed9-459e-9980-1ec56d8d00fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386033238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.386033238
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.440748235
Short name T179
Test name
Test status
Simulation time 1155438222 ps
CPU time 13.34 seconds
Started Aug 07 04:58:01 PM PDT 24
Finished Aug 07 04:58:15 PM PDT 24
Peak memory 214036 kb
Host smart-28c4f466-5613-4c0c-b973-32d6f469ca27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440748235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.440748235
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1608265085
Short name T224
Test name
Test status
Simulation time 12332032853 ps
CPU time 98.26 seconds
Started Aug 07 04:57:59 PM PDT 24
Finished Aug 07 04:59:38 PM PDT 24
Peak memory 234404 kb
Host smart-8ec82193-4407-4dfe-8652-b76113e58bba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608265085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1608265085
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1394916437
Short name T172
Test name
Test status
Simulation time 1471734277 ps
CPU time 11.25 seconds
Started Aug 07 04:58:08 PM PDT 24
Finished Aug 07 04:58:19 PM PDT 24
Peak memory 213380 kb
Host smart-9aa8bba4-dfb7-458e-9131-013e3b96063e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394916437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1394916437
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2674699500
Short name T312
Test name
Test status
Simulation time 338250817 ps
CPU time 5.63 seconds
Started Aug 07 04:58:13 PM PDT 24
Finished Aug 07 04:58:19 PM PDT 24
Peak memory 212152 kb
Host smart-57d6108e-b3e6-4466-959d-0c7c3c6a88ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2674699500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2674699500
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3646893925
Short name T293
Test name
Test status
Simulation time 4139184297 ps
CPU time 35.16 seconds
Started Aug 07 04:58:48 PM PDT 24
Finished Aug 07 04:59:24 PM PDT 24
Peak memory 217420 kb
Host smart-01c92c50-82c3-4114-839f-b8a316518974
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646893925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3646893925
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1391062307
Short name T89
Test name
Test status
Simulation time 152004043433 ps
CPU time 2735.07 seconds
Started Aug 07 04:58:04 PM PDT 24
Finished Aug 07 05:43:39 PM PDT 24
Peak memory 241664 kb
Host smart-186d9939-7695-4687-a461-c96c2cb1a44d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391062307 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1391062307
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2870351091
Short name T275
Test name
Test status
Simulation time 461248687 ps
CPU time 5.18 seconds
Started Aug 07 04:57:48 PM PDT 24
Finished Aug 07 04:57:53 PM PDT 24
Peak memory 212076 kb
Host smart-0a5f4f54-6187-4293-8135-7dfcc0f3b51a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870351091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2870351091
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1450280016
Short name T288
Test name
Test status
Simulation time 3582428914 ps
CPU time 110.91 seconds
Started Aug 07 04:57:51 PM PDT 24
Finished Aug 07 04:59:42 PM PDT 24
Peak memory 238676 kb
Host smart-404bf4a6-a7bf-4254-ada2-13eae8599f29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450280016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1450280016
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2074780031
Short name T306
Test name
Test status
Simulation time 641302187 ps
CPU time 11.25 seconds
Started Aug 07 04:57:47 PM PDT 24
Finished Aug 07 04:57:58 PM PDT 24
Peak memory 212840 kb
Host smart-30d49d14-e047-42d3-ab6e-9ff66c1f59c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074780031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2074780031
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2781406671
Short name T234
Test name
Test status
Simulation time 527668453 ps
CPU time 8.69 seconds
Started Aug 07 04:57:48 PM PDT 24
Finished Aug 07 04:57:56 PM PDT 24
Peak memory 212172 kb
Host smart-64ef62ce-2fc5-419c-bed2-b622efc1d384
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2781406671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2781406671
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2285318206
Short name T26
Test name
Test status
Simulation time 433045983 ps
CPU time 99.56 seconds
Started Aug 07 04:58:06 PM PDT 24
Finished Aug 07 04:59:46 PM PDT 24
Peak memory 237412 kb
Host smart-726d7396-d8cf-4f44-8eb7-48fa507cb2e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285318206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2285318206
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.474190831
Short name T165
Test name
Test status
Simulation time 98935595 ps
CPU time 5.4 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:58:47 PM PDT 24
Peak memory 212100 kb
Host smart-a3fdfc6f-7734-4099-b851-5099a76ee9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474190831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.474190831
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.301101226
Short name T140
Test name
Test status
Simulation time 104883380 ps
CPU time 8.72 seconds
Started Aug 07 04:58:04 PM PDT 24
Finished Aug 07 04:58:13 PM PDT 24
Peak memory 212080 kb
Host smart-53a14844-7721-4028-a649-87e8373b134f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301101226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.301101226
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2310237156
Short name T301
Test name
Test status
Simulation time 88076689 ps
CPU time 4.36 seconds
Started Aug 07 04:58:02 PM PDT 24
Finished Aug 07 04:58:06 PM PDT 24
Peak memory 211972 kb
Host smart-43c82b72-48cd-4c37-beec-477933f240bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310237156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2310237156
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2681036717
Short name T280
Test name
Test status
Simulation time 2101239686 ps
CPU time 104.18 seconds
Started Aug 07 04:58:50 PM PDT 24
Finished Aug 07 05:00:35 PM PDT 24
Peak memory 233232 kb
Host smart-5b57528c-260e-4b23-80d9-ebf73b33cf80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681036717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2681036717
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2628161501
Short name T126
Test name
Test status
Simulation time 262471957 ps
CPU time 11.43 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:58:53 PM PDT 24
Peak memory 212912 kb
Host smart-bd874c1a-c882-453e-b2da-6f35afb821b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628161501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2628161501
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.4244569127
Short name T187
Test name
Test status
Simulation time 560150027 ps
CPU time 6.28 seconds
Started Aug 07 04:58:44 PM PDT 24
Finished Aug 07 04:58:50 PM PDT 24
Peak memory 212128 kb
Host smart-a16b2640-89fc-4174-9133-bc03e0c8b3d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4244569127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.4244569127
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3239536252
Short name T262
Test name
Test status
Simulation time 320705799 ps
CPU time 14.68 seconds
Started Aug 07 04:58:12 PM PDT 24
Finished Aug 07 04:58:27 PM PDT 24
Peak memory 214904 kb
Host smart-8ee6978f-1a82-4636-a990-fde7262f8614
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239536252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3239536252
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1021609974
Short name T158
Test name
Test status
Simulation time 35848437679 ps
CPU time 2469.77 seconds
Started Aug 07 04:58:21 PM PDT 24
Finished Aug 07 05:39:31 PM PDT 24
Peak memory 233912 kb
Host smart-cb198bb7-369a-4a40-897e-f890b5b8f759
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021609974 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1021609974
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1836778099
Short name T320
Test name
Test status
Simulation time 1436821963 ps
CPU time 7.42 seconds
Started Aug 07 04:58:15 PM PDT 24
Finished Aug 07 04:58:23 PM PDT 24
Peak memory 212044 kb
Host smart-a92a245c-3617-4700-bbe0-c64c087847c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836778099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1836778099
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3837681041
Short name T163
Test name
Test status
Simulation time 256731819 ps
CPU time 11.18 seconds
Started Aug 07 04:58:53 PM PDT 24
Finished Aug 07 04:59:04 PM PDT 24
Peak memory 212076 kb
Host smart-7c9a21fd-56f7-45aa-b702-2e65f3d7bc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837681041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3837681041
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.896878679
Short name T250
Test name
Test status
Simulation time 385224550 ps
CPU time 5.19 seconds
Started Aug 07 04:58:00 PM PDT 24
Finished Aug 07 04:58:05 PM PDT 24
Peak memory 212064 kb
Host smart-4070351a-5b08-4d14-80ef-a765e7d1000a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896878679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.896878679
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1550410745
Short name T144
Test name
Test status
Simulation time 194831366 ps
CPU time 6.84 seconds
Started Aug 07 04:58:17 PM PDT 24
Finished Aug 07 04:58:24 PM PDT 24
Peak memory 211992 kb
Host smart-bedbecd7-7a39-46ac-a68a-b92811a76b20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550410745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1550410745
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3636883172
Short name T248
Test name
Test status
Simulation time 48795418429 ps
CPU time 459.07 seconds
Started Aug 07 04:58:14 PM PDT 24
Finished Aug 07 05:05:54 PM PDT 24
Peak memory 228932 kb
Host smart-8a4d7bdd-ce35-4bb6-9fb9-b488f2f46ad1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636883172 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.3636883172
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.318488119
Short name T21
Test name
Test status
Simulation time 85769328 ps
CPU time 4.29 seconds
Started Aug 07 04:58:11 PM PDT 24
Finished Aug 07 04:58:15 PM PDT 24
Peak memory 211928 kb
Host smart-79128734-7072-43e6-9bf1-f3a4e46f09b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318488119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.318488119
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.108067652
Short name T35
Test name
Test status
Simulation time 9016950891 ps
CPU time 187.55 seconds
Started Aug 07 04:58:16 PM PDT 24
Finished Aug 07 05:01:23 PM PDT 24
Peak memory 213504 kb
Host smart-2e42fbcb-a0e9-4a1c-96e4-a125aacc68e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108067652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.108067652
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3327246912
Short name T40
Test name
Test status
Simulation time 991273356 ps
CPU time 10.92 seconds
Started Aug 07 04:58:13 PM PDT 24
Finished Aug 07 04:58:24 PM PDT 24
Peak memory 212872 kb
Host smart-c88cdc8b-fe65-4462-a519-46aecc661b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327246912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3327246912
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3135277853
Short name T327
Test name
Test status
Simulation time 194693934 ps
CPU time 5.74 seconds
Started Aug 07 04:58:12 PM PDT 24
Finished Aug 07 04:58:18 PM PDT 24
Peak memory 212020 kb
Host smart-7bbe2ee8-b8ad-422e-8f90-7a02c0b35d60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3135277853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3135277853
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1605795601
Short name T146
Test name
Test status
Simulation time 281864319 ps
CPU time 15.1 seconds
Started Aug 07 04:58:09 PM PDT 24
Finished Aug 07 04:58:24 PM PDT 24
Peak memory 214508 kb
Host smart-39a61e4e-fb8d-4745-81b0-3cafece8e486
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605795601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1605795601
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2827813547
Short name T129
Test name
Test status
Simulation time 127419132 ps
CPU time 5.23 seconds
Started Aug 07 04:58:12 PM PDT 24
Finished Aug 07 04:58:17 PM PDT 24
Peak memory 211968 kb
Host smart-e5464c3b-7c79-4015-9e01-ef26b97e394f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827813547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2827813547
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3711628845
Short name T181
Test name
Test status
Simulation time 6916309103 ps
CPU time 106.46 seconds
Started Aug 07 04:58:31 PM PDT 24
Finished Aug 07 05:00:18 PM PDT 24
Peak memory 238492 kb
Host smart-96953caf-656c-40e6-b2a1-5cbb80244c6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711628845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3711628845
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.912019827
Short name T252
Test name
Test status
Simulation time 621750692 ps
CPU time 9.43 seconds
Started Aug 07 04:58:23 PM PDT 24
Finished Aug 07 04:58:33 PM PDT 24
Peak memory 212840 kb
Host smart-7e004236-67f8-45e5-b4bf-e56157496b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912019827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.912019827
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1661656863
Short name T136
Test name
Test status
Simulation time 1117873700 ps
CPU time 12.56 seconds
Started Aug 07 04:58:20 PM PDT 24
Finished Aug 07 04:58:33 PM PDT 24
Peak memory 214708 kb
Host smart-2e02c7d3-340b-420f-87ae-e7177ff2c854
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661656863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1661656863
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2770059165
Short name T245
Test name
Test status
Simulation time 132570434 ps
CPU time 5.32 seconds
Started Aug 07 04:58:48 PM PDT 24
Finished Aug 07 04:58:53 PM PDT 24
Peak memory 212052 kb
Host smart-e4b7575e-aa79-4135-b476-6e126cd8ff0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770059165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2770059165
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2269621853
Short name T148
Test name
Test status
Simulation time 2360313149 ps
CPU time 164.44 seconds
Started Aug 07 04:58:05 PM PDT 24
Finished Aug 07 05:00:50 PM PDT 24
Peak memory 238508 kb
Host smart-7c922c47-ee16-4427-a821-d8356de6b036
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269621853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2269621853
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3831468804
Short name T200
Test name
Test status
Simulation time 1129104640 ps
CPU time 11.26 seconds
Started Aug 07 04:58:03 PM PDT 24
Finished Aug 07 04:58:14 PM PDT 24
Peak memory 212928 kb
Host smart-f09f6b57-913f-4b63-81a6-341971771d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831468804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3831468804
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.776301072
Short name T247
Test name
Test status
Simulation time 101594262 ps
CPU time 5.88 seconds
Started Aug 07 04:58:12 PM PDT 24
Finished Aug 07 04:58:18 PM PDT 24
Peak memory 212072 kb
Host smart-6024661c-a6e4-4682-850b-3573189428ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776301072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.776301072
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.120777522
Short name T149
Test name
Test status
Simulation time 1944927700 ps
CPU time 24 seconds
Started Aug 07 04:58:02 PM PDT 24
Finished Aug 07 04:58:26 PM PDT 24
Peak memory 215516 kb
Host smart-19e6f5d0-1739-482b-ab92-316351cee561
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120777522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.120777522
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.11806508
Short name T164
Test name
Test status
Simulation time 519146245 ps
CPU time 4.2 seconds
Started Aug 07 04:58:26 PM PDT 24
Finished Aug 07 04:58:31 PM PDT 24
Peak memory 212028 kb
Host smart-7c6e49d1-1a22-416d-8d52-2b617da2fcbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11806508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.11806508
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1279219477
Short name T304
Test name
Test status
Simulation time 21555533093 ps
CPU time 101.92 seconds
Started Aug 07 04:58:39 PM PDT 24
Finished Aug 07 05:00:22 PM PDT 24
Peak memory 238108 kb
Host smart-00bc8df1-d4f6-40f5-a043-9e0f56aaa77b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279219477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1279219477
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1662756417
Short name T258
Test name
Test status
Simulation time 1030197219 ps
CPU time 11.51 seconds
Started Aug 07 04:58:21 PM PDT 24
Finished Aug 07 04:58:33 PM PDT 24
Peak memory 212952 kb
Host smart-e09e83a4-f998-4c99-a35b-edd7d44c1cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662756417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1662756417
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1617225395
Short name T328
Test name
Test status
Simulation time 143329834 ps
CPU time 6.47 seconds
Started Aug 07 04:58:44 PM PDT 24
Finished Aug 07 04:58:51 PM PDT 24
Peak memory 212380 kb
Host smart-66d80a64-9376-47c8-8e0a-1c1a967251c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1617225395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1617225395
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.435006064
Short name T298
Test name
Test status
Simulation time 566935079 ps
CPU time 23.04 seconds
Started Aug 07 04:58:02 PM PDT 24
Finished Aug 07 04:58:25 PM PDT 24
Peak memory 217336 kb
Host smart-78e157c5-62a5-46a7-89b1-ab37ea5380cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435006064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.435006064
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.271574122
Short name T303
Test name
Test status
Simulation time 693333059 ps
CPU time 5.06 seconds
Started Aug 07 04:58:20 PM PDT 24
Finished Aug 07 04:58:25 PM PDT 24
Peak memory 212060 kb
Host smart-9afeced0-0867-4e9b-9156-8387ecd7c6c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271574122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.271574122
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.6335543
Short name T228
Test name
Test status
Simulation time 992710175 ps
CPU time 11.33 seconds
Started Aug 07 04:58:27 PM PDT 24
Finished Aug 07 04:58:39 PM PDT 24
Peak memory 212816 kb
Host smart-2d56e177-f8a6-49e0-bda2-f40b622408b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6335543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.6335543
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2177792635
Short name T122
Test name
Test status
Simulation time 95497291 ps
CPU time 5.73 seconds
Started Aug 07 04:58:13 PM PDT 24
Finished Aug 07 04:58:19 PM PDT 24
Peak memory 212144 kb
Host smart-26a07588-370f-48ee-9953-2129bfae70df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2177792635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2177792635
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.828996540
Short name T68
Test name
Test status
Simulation time 346406442 ps
CPU time 13.6 seconds
Started Aug 07 04:58:23 PM PDT 24
Finished Aug 07 04:58:36 PM PDT 24
Peak memory 212952 kb
Host smart-2d92608c-7526-4a98-8854-b4bb1cbe0d0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828996540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.828996540
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2843937336
Short name T307
Test name
Test status
Simulation time 478812970159 ps
CPU time 5122.58 seconds
Started Aug 07 04:58:23 PM PDT 24
Finished Aug 07 06:23:46 PM PDT 24
Peak memory 253032 kb
Host smart-5c27c53b-8801-41d4-a0ec-17c388d606de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843937336 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.2843937336
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3632085799
Short name T233
Test name
Test status
Simulation time 89324614 ps
CPU time 4.29 seconds
Started Aug 07 04:58:29 PM PDT 24
Finished Aug 07 04:58:33 PM PDT 24
Peak memory 212048 kb
Host smart-820bb17a-567c-4674-b642-1f490332d3c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632085799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3632085799
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3363432230
Short name T34
Test name
Test status
Simulation time 7784354479 ps
CPU time 127.86 seconds
Started Aug 07 04:58:17 PM PDT 24
Finished Aug 07 05:00:25 PM PDT 24
Peak memory 226340 kb
Host smart-440432be-8c82-4a19-ad8a-5d150e9aa865
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363432230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3363432230
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2859632455
Short name T153
Test name
Test status
Simulation time 266257771 ps
CPU time 11.11 seconds
Started Aug 07 04:58:26 PM PDT 24
Finished Aug 07 04:58:37 PM PDT 24
Peak memory 213004 kb
Host smart-855cb252-93f1-46bf-922e-10a17deb974a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859632455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2859632455
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3354037228
Short name T3
Test name
Test status
Simulation time 139361384 ps
CPU time 6.16 seconds
Started Aug 07 04:58:20 PM PDT 24
Finished Aug 07 04:58:26 PM PDT 24
Peak memory 212152 kb
Host smart-e95b6662-b9a7-4b00-9eba-e309317d363e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3354037228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3354037228
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.692960852
Short name T174
Test name
Test status
Simulation time 4685842367 ps
CPU time 15.49 seconds
Started Aug 07 04:58:19 PM PDT 24
Finished Aug 07 04:58:35 PM PDT 24
Peak memory 215148 kb
Host smart-cedd6447-ac55-4550-8408-60d801b0be10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692960852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.692960852
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.899367361
Short name T23
Test name
Test status
Simulation time 123429185000 ps
CPU time 4657.46 seconds
Started Aug 07 04:58:20 PM PDT 24
Finished Aug 07 06:15:58 PM PDT 24
Peak memory 251000 kb
Host smart-667f7ce3-7bb2-442b-bdf1-e04d8f340907
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899367361 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.899367361
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1496419774
Short name T294
Test name
Test status
Simulation time 271057785 ps
CPU time 5.1 seconds
Started Aug 07 04:58:34 PM PDT 24
Finished Aug 07 04:58:39 PM PDT 24
Peak memory 211652 kb
Host smart-d8f10ea5-8c6c-40aa-aaad-ed8285bd7399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496419774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1496419774
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3443343347
Short name T332
Test name
Test status
Simulation time 1341811377 ps
CPU time 89.29 seconds
Started Aug 07 04:58:57 PM PDT 24
Finished Aug 07 05:00:26 PM PDT 24
Peak memory 228936 kb
Host smart-4406c7f4-98ca-4fea-877b-9772b709ed18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443343347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3443343347
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.683542737
Short name T310
Test name
Test status
Simulation time 169713208 ps
CPU time 9.49 seconds
Started Aug 07 04:58:32 PM PDT 24
Finished Aug 07 04:58:42 PM PDT 24
Peak memory 213128 kb
Host smart-8a7014c1-7d53-483e-ae87-a497bcdc4061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683542737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.683542737
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3371221679
Short name T176
Test name
Test status
Simulation time 477842661 ps
CPU time 6.57 seconds
Started Aug 07 04:58:19 PM PDT 24
Finished Aug 07 04:58:26 PM PDT 24
Peak memory 212192 kb
Host smart-34a8254b-e46d-4671-9750-ed16c706f020
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3371221679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3371221679
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2813225298
Short name T194
Test name
Test status
Simulation time 187323289 ps
CPU time 10.14 seconds
Started Aug 07 04:58:17 PM PDT 24
Finished Aug 07 04:58:27 PM PDT 24
Peak memory 215736 kb
Host smart-f7c47858-00a9-4ff2-bb8a-d06cd828b332
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813225298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2813225298
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.557585196
Short name T305
Test name
Test status
Simulation time 95634911 ps
CPU time 4.32 seconds
Started Aug 07 04:58:28 PM PDT 24
Finished Aug 07 04:58:32 PM PDT 24
Peak memory 211936 kb
Host smart-6e358155-a6de-4aa1-89f7-a0a573e664cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557585196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.557585196
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.140076381
Short name T159
Test name
Test status
Simulation time 11100711262 ps
CPU time 117.77 seconds
Started Aug 07 04:58:18 PM PDT 24
Finished Aug 07 05:00:16 PM PDT 24
Peak memory 238444 kb
Host smart-c333ad9c-c1ec-44b3-9e66-6f2a1c7ca50d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140076381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.140076381
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3882058821
Short name T183
Test name
Test status
Simulation time 568456001 ps
CPU time 6.28 seconds
Started Aug 07 04:58:27 PM PDT 24
Finished Aug 07 04:58:34 PM PDT 24
Peak memory 212112 kb
Host smart-c25ac8d1-8bd7-42e6-afbc-01f63ae83630
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3882058821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3882058821
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.4189600917
Short name T119
Test name
Test status
Simulation time 451423350 ps
CPU time 10.43 seconds
Started Aug 07 04:58:22 PM PDT 24
Finished Aug 07 04:58:32 PM PDT 24
Peak memory 212140 kb
Host smart-1e6c8686-016b-4df3-a4bb-f05b40ba5011
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189600917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.4189600917
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.653070544
Short name T105
Test name
Test status
Simulation time 86434159 ps
CPU time 4.24 seconds
Started Aug 07 04:57:48 PM PDT 24
Finished Aug 07 04:57:53 PM PDT 24
Peak memory 212008 kb
Host smart-a9cd1e40-0627-4187-a7b1-d50508a3c819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653070544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.653070544
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2987329322
Short name T116
Test name
Test status
Simulation time 72142385230 ps
CPU time 189 seconds
Started Aug 07 04:57:55 PM PDT 24
Finished Aug 07 05:01:04 PM PDT 24
Peak memory 229216 kb
Host smart-16648652-6580-4608-92dd-203ab60128d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987329322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2987329322
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3840663790
Short name T209
Test name
Test status
Simulation time 253460825 ps
CPU time 10.89 seconds
Started Aug 07 04:58:44 PM PDT 24
Finished Aug 07 04:58:55 PM PDT 24
Peak memory 212800 kb
Host smart-138490bc-f0eb-45ef-98d6-120549721c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840663790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3840663790
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1652941825
Short name T239
Test name
Test status
Simulation time 749037885 ps
CPU time 5.42 seconds
Started Aug 07 04:57:52 PM PDT 24
Finished Aug 07 04:57:57 PM PDT 24
Peak memory 212064 kb
Host smart-bf363508-7c5e-4c4c-aa82-882ac4a69184
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1652941825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1652941825
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3751002125
Short name T20
Test name
Test status
Simulation time 149580154 ps
CPU time 51.49 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:59:33 PM PDT 24
Peak memory 237432 kb
Host smart-26ea73dd-abd4-429e-9478-96a3deaf6746
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751002125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3751002125
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.4276212740
Short name T244
Test name
Test status
Simulation time 141625412 ps
CPU time 6.5 seconds
Started Aug 07 04:58:07 PM PDT 24
Finished Aug 07 04:58:13 PM PDT 24
Peak memory 212048 kb
Host smart-ed80a5a6-251b-4096-a139-541703464ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276212740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.4276212740
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3678934693
Short name T271
Test name
Test status
Simulation time 1610003273 ps
CPU time 21.44 seconds
Started Aug 07 04:57:44 PM PDT 24
Finished Aug 07 04:58:06 PM PDT 24
Peak memory 215604 kb
Host smart-c68e9352-7196-41d4-b598-c8401658e01e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678934693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3678934693
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.4253649618
Short name T154
Test name
Test status
Simulation time 90056121 ps
CPU time 4.18 seconds
Started Aug 07 04:58:29 PM PDT 24
Finished Aug 07 04:58:34 PM PDT 24
Peak memory 212068 kb
Host smart-1e1ad9a2-3788-4917-b67f-7634056f2395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253649618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.4253649618
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2704124187
Short name T139
Test name
Test status
Simulation time 17761700975 ps
CPU time 152.73 seconds
Started Aug 07 04:58:29 PM PDT 24
Finished Aug 07 05:01:02 PM PDT 24
Peak memory 218404 kb
Host smart-3e6c3722-553c-4970-9dda-75a792e271fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704124187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2704124187
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1023129539
Short name T225
Test name
Test status
Simulation time 337136439 ps
CPU time 9.49 seconds
Started Aug 07 04:58:52 PM PDT 24
Finished Aug 07 04:59:02 PM PDT 24
Peak memory 212928 kb
Host smart-2c8a6512-f7b1-4840-bde3-ddc5f6893cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023129539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1023129539
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1640969726
Short name T213
Test name
Test status
Simulation time 194868974 ps
CPU time 5.8 seconds
Started Aug 07 04:58:19 PM PDT 24
Finished Aug 07 04:58:25 PM PDT 24
Peak memory 212184 kb
Host smart-799c8c74-4d63-44c5-9f64-8cdc9172653a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1640969726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1640969726
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1712302334
Short name T282
Test name
Test status
Simulation time 1069201428 ps
CPU time 11.71 seconds
Started Aug 07 04:58:34 PM PDT 24
Finished Aug 07 04:58:45 PM PDT 24
Peak memory 214212 kb
Host smart-928c03d3-2148-4617-a84e-f7786b5ee711
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712302334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1712302334
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2499611209
Short name T229
Test name
Test status
Simulation time 27660756883 ps
CPU time 595.74 seconds
Started Aug 07 04:58:26 PM PDT 24
Finished Aug 07 05:08:22 PM PDT 24
Peak memory 236644 kb
Host smart-2a31d82c-0860-472a-a725-cc00a7147683
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499611209 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2499611209
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3424649893
Short name T152
Test name
Test status
Simulation time 131599135 ps
CPU time 5.12 seconds
Started Aug 07 04:58:21 PM PDT 24
Finished Aug 07 04:58:26 PM PDT 24
Peak memory 212068 kb
Host smart-0d25c5e1-a632-4afd-88b4-42e02a13a9bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424649893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3424649893
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2718457673
Short name T36
Test name
Test status
Simulation time 7607899928 ps
CPU time 99.32 seconds
Started Aug 07 04:58:26 PM PDT 24
Finished Aug 07 05:00:06 PM PDT 24
Peak memory 237480 kb
Host smart-06861c46-9ace-4fe7-a033-41d0e861c02f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718457673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2718457673
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.4119316476
Short name T259
Test name
Test status
Simulation time 1667362887 ps
CPU time 11.21 seconds
Started Aug 07 04:58:31 PM PDT 24
Finished Aug 07 04:58:43 PM PDT 24
Peak memory 212744 kb
Host smart-afb1cbd0-5480-41d2-8c1f-ae51a0f73ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119316476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.4119316476
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.26969407
Short name T151
Test name
Test status
Simulation time 98074377 ps
CPU time 5.57 seconds
Started Aug 07 04:59:13 PM PDT 24
Finished Aug 07 04:59:18 PM PDT 24
Peak memory 212044 kb
Host smart-31c474b6-adfe-4db8-81ab-a6bb8a43baaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=26969407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.26969407
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3318005011
Short name T284
Test name
Test status
Simulation time 641610482 ps
CPU time 17.44 seconds
Started Aug 07 04:58:52 PM PDT 24
Finished Aug 07 04:59:10 PM PDT 24
Peak memory 214492 kb
Host smart-cbc8529f-89bb-43e3-a328-6819ae5a420a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318005011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3318005011
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.427614454
Short name T279
Test name
Test status
Simulation time 74075852649 ps
CPU time 2736.42 seconds
Started Aug 07 04:58:25 PM PDT 24
Finished Aug 07 05:44:02 PM PDT 24
Peak memory 249732 kb
Host smart-94c5c6d6-1a2f-43b2-bf96-b0e1caae5029
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427614454 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.427614454
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1052693483
Short name T277
Test name
Test status
Simulation time 91333491 ps
CPU time 4.27 seconds
Started Aug 07 04:58:33 PM PDT 24
Finished Aug 07 04:58:37 PM PDT 24
Peak memory 212068 kb
Host smart-87c11ee6-2e78-4927-81d9-34e4663294db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052693483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1052693483
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1472897206
Short name T147
Test name
Test status
Simulation time 16431546577 ps
CPU time 203.56 seconds
Started Aug 07 04:58:40 PM PDT 24
Finished Aug 07 05:02:04 PM PDT 24
Peak memory 235468 kb
Host smart-fc518020-c4b3-46e8-8110-8d6ed2e87898
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472897206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1472897206
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3550494323
Short name T39
Test name
Test status
Simulation time 3332578813 ps
CPU time 9.65 seconds
Started Aug 07 04:58:23 PM PDT 24
Finished Aug 07 04:58:33 PM PDT 24
Peak memory 212956 kb
Host smart-42ea2a99-8914-4851-bba7-7762c986a6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550494323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3550494323
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.908552637
Short name T221
Test name
Test status
Simulation time 105486977 ps
CPU time 5.79 seconds
Started Aug 07 04:58:24 PM PDT 24
Finished Aug 07 04:58:30 PM PDT 24
Peak memory 212020 kb
Host smart-16bc6225-7379-4705-8b55-78afa6010f89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=908552637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.908552637
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2685747071
Short name T155
Test name
Test status
Simulation time 1753199325 ps
CPU time 19.73 seconds
Started Aug 07 04:58:29 PM PDT 24
Finished Aug 07 04:58:49 PM PDT 24
Peak memory 216884 kb
Host smart-17c493ab-5617-468c-81ea-93083cd7b7bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685747071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2685747071
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.159976818
Short name T47
Test name
Test status
Simulation time 14085302236 ps
CPU time 553.19 seconds
Started Aug 07 04:58:30 PM PDT 24
Finished Aug 07 05:07:43 PM PDT 24
Peak memory 236692 kb
Host smart-e254ce67-64d3-4438-b45b-9f8d57b3f523
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159976818 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.159976818
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2118670355
Short name T111
Test name
Test status
Simulation time 133040731 ps
CPU time 5.1 seconds
Started Aug 07 04:58:23 PM PDT 24
Finished Aug 07 04:58:28 PM PDT 24
Peak memory 212044 kb
Host smart-fcdd131e-2c58-4e9c-91bf-bf6b1fb2766b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118670355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2118670355
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1028001284
Short name T52
Test name
Test status
Simulation time 6690967105 ps
CPU time 57.38 seconds
Started Aug 07 04:58:46 PM PDT 24
Finished Aug 07 04:59:49 PM PDT 24
Peak memory 213396 kb
Host smart-f65a168d-88a1-4506-b87c-d34da31874d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028001284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1028001284
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4136110195
Short name T199
Test name
Test status
Simulation time 670088034 ps
CPU time 9.56 seconds
Started Aug 07 04:58:23 PM PDT 24
Finished Aug 07 04:58:33 PM PDT 24
Peak memory 212784 kb
Host smart-88ea1f9a-b13a-44a8-9607-fd4f6fc17d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136110195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.4136110195
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3320059616
Short name T198
Test name
Test status
Simulation time 1763369460 ps
CPU time 5.44 seconds
Started Aug 07 04:58:32 PM PDT 24
Finished Aug 07 04:58:37 PM PDT 24
Peak memory 212144 kb
Host smart-b2263c7f-9626-4a1e-b272-c3786ccd3270
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3320059616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3320059616
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3826268941
Short name T70
Test name
Test status
Simulation time 207447364 ps
CPU time 13.11 seconds
Started Aug 07 04:58:24 PM PDT 24
Finished Aug 07 04:58:38 PM PDT 24
Peak memory 214492 kb
Host smart-c0611321-f445-431e-89ec-cc287d362250
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826268941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3826268941
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2227307269
Short name T56
Test name
Test status
Simulation time 333916062 ps
CPU time 4.39 seconds
Started Aug 07 04:58:29 PM PDT 24
Finished Aug 07 04:58:34 PM PDT 24
Peak memory 212040 kb
Host smart-cf5aa848-7336-4a08-9e80-d60e71bdea91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227307269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2227307269
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3782763132
Short name T15
Test name
Test status
Simulation time 7268921819 ps
CPU time 105.18 seconds
Started Aug 07 04:58:33 PM PDT 24
Finished Aug 07 05:00:18 PM PDT 24
Peak memory 234384 kb
Host smart-75fea04c-4b4d-4c3f-bf98-df2041be114c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782763132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3782763132
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.869788905
Short name T300
Test name
Test status
Simulation time 693195112 ps
CPU time 9.62 seconds
Started Aug 07 04:58:34 PM PDT 24
Finished Aug 07 04:58:44 PM PDT 24
Peak memory 212880 kb
Host smart-be85f4df-9495-4b61-9e52-d70695644eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869788905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.869788905
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2921327208
Short name T326
Test name
Test status
Simulation time 288747747 ps
CPU time 6.69 seconds
Started Aug 07 04:58:43 PM PDT 24
Finished Aug 07 04:58:49 PM PDT 24
Peak memory 212064 kb
Host smart-ad7123f7-9277-42ca-87d1-678434a7603c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2921327208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2921327208
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3572692024
Short name T173
Test name
Test status
Simulation time 685387193 ps
CPU time 11.83 seconds
Started Aug 07 04:58:33 PM PDT 24
Finished Aug 07 04:58:45 PM PDT 24
Peak memory 214168 kb
Host smart-62592c8a-0f9a-47d6-bc53-8d944b9cf24a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572692024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3572692024
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.956800488
Short name T48
Test name
Test status
Simulation time 973462647688 ps
CPU time 2454.5 seconds
Started Aug 07 04:58:20 PM PDT 24
Finished Aug 07 05:39:15 PM PDT 24
Peak memory 251672 kb
Host smart-b658fc8e-644a-4a55-a666-880a566a139a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956800488 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.956800488
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.162629505
Short name T57
Test name
Test status
Simulation time 129560365 ps
CPU time 5.04 seconds
Started Aug 07 04:58:30 PM PDT 24
Finished Aug 07 04:58:36 PM PDT 24
Peak memory 212088 kb
Host smart-ddc89f95-29ed-4d30-98ea-4898ac68e2ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162629505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.162629505
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.161288970
Short name T206
Test name
Test status
Simulation time 1410609619 ps
CPU time 55.03 seconds
Started Aug 07 04:58:29 PM PDT 24
Finished Aug 07 04:59:24 PM PDT 24
Peak memory 236848 kb
Host smart-f4837cda-23b2-4bdf-aacd-acb3ca7b3973
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161288970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.161288970
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3671397953
Short name T208
Test name
Test status
Simulation time 176901499 ps
CPU time 9.6 seconds
Started Aug 07 04:58:20 PM PDT 24
Finished Aug 07 04:58:30 PM PDT 24
Peak memory 213048 kb
Host smart-59f39ad3-d1e9-4c75-a1c9-71f6e40859f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671397953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3671397953
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3924926213
Short name T128
Test name
Test status
Simulation time 141839186 ps
CPU time 6.84 seconds
Started Aug 07 04:58:26 PM PDT 24
Finished Aug 07 04:58:33 PM PDT 24
Peak memory 212152 kb
Host smart-5cd80aef-fbff-409c-bb58-0c6daebc10c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3924926213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3924926213
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2063428227
Short name T309
Test name
Test status
Simulation time 604621344 ps
CPU time 12.84 seconds
Started Aug 07 04:58:59 PM PDT 24
Finished Aug 07 04:59:12 PM PDT 24
Peak memory 215156 kb
Host smart-b877eca0-fb6b-46bc-b5f3-f1461aa1402c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063428227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2063428227
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1593911751
Short name T156
Test name
Test status
Simulation time 334246296521 ps
CPU time 8712.64 seconds
Started Aug 07 04:58:34 PM PDT 24
Finished Aug 07 07:23:48 PM PDT 24
Peak memory 230976 kb
Host smart-be7b0eb9-2fef-41e9-8e80-7dfe301f7368
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593911751 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.1593911751
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.572541089
Short name T289
Test name
Test status
Simulation time 363792592 ps
CPU time 4.31 seconds
Started Aug 07 04:58:55 PM PDT 24
Finished Aug 07 04:58:59 PM PDT 24
Peak memory 212056 kb
Host smart-7821e1c9-dd10-4aae-a35c-42713cb2f15d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572541089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.572541089
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1050977017
Short name T226
Test name
Test status
Simulation time 5154705707 ps
CPU time 84.33 seconds
Started Aug 07 04:58:58 PM PDT 24
Finished Aug 07 05:00:23 PM PDT 24
Peak memory 235596 kb
Host smart-1c0e4a6c-4f8b-4c9c-8265-8fb72c7d260c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050977017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1050977017
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3615141510
Short name T291
Test name
Test status
Simulation time 1036018051 ps
CPU time 11.22 seconds
Started Aug 07 04:58:35 PM PDT 24
Finished Aug 07 04:58:46 PM PDT 24
Peak memory 212920 kb
Host smart-ba410eb0-ffcf-4804-b1dd-fcc4ee5e286c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615141510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3615141510
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1546499661
Short name T17
Test name
Test status
Simulation time 560302665 ps
CPU time 6.52 seconds
Started Aug 07 04:58:27 PM PDT 24
Finished Aug 07 04:58:34 PM PDT 24
Peak memory 212160 kb
Host smart-e968d206-3899-456f-96cf-af66795e2ac0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1546499661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1546499661
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3407625648
Short name T263
Test name
Test status
Simulation time 2554395845 ps
CPU time 12.49 seconds
Started Aug 07 04:58:35 PM PDT 24
Finished Aug 07 04:58:48 PM PDT 24
Peak memory 214016 kb
Host smart-2c4b5e90-8d9a-4a67-a99e-1050e7c7f066
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407625648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3407625648
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2160400957
Short name T246
Test name
Test status
Simulation time 336887844 ps
CPU time 4.23 seconds
Started Aug 07 04:58:35 PM PDT 24
Finished Aug 07 04:58:39 PM PDT 24
Peak memory 211964 kb
Host smart-6438e672-beca-4371-8795-6374866309c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160400957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2160400957
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2320053976
Short name T170
Test name
Test status
Simulation time 2615478048 ps
CPU time 125.36 seconds
Started Aug 07 04:58:29 PM PDT 24
Finished Aug 07 05:00:35 PM PDT 24
Peak memory 229228 kb
Host smart-0122fc3c-6225-444c-b3db-5ea890ff47c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320053976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2320053976
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1552188352
Short name T212
Test name
Test status
Simulation time 170002107 ps
CPU time 9.8 seconds
Started Aug 07 04:58:36 PM PDT 24
Finished Aug 07 04:58:46 PM PDT 24
Peak memory 213096 kb
Host smart-4f1551ec-442f-4f8d-95bb-dd9dd6b463ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552188352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1552188352
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1556990948
Short name T166
Test name
Test status
Simulation time 142534613 ps
CPU time 6.27 seconds
Started Aug 07 04:58:40 PM PDT 24
Finished Aug 07 04:58:46 PM PDT 24
Peak memory 212192 kb
Host smart-dcabd517-c14e-4686-adba-00f4df4e4321
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1556990948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1556990948
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.541468376
Short name T58
Test name
Test status
Simulation time 679966729 ps
CPU time 8.44 seconds
Started Aug 07 04:58:43 PM PDT 24
Finished Aug 07 04:58:52 PM PDT 24
Peak memory 213272 kb
Host smart-74b6ef3c-5f83-4093-9e48-f27a61d314fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541468376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.541468376
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2033243595
Short name T251
Test name
Test status
Simulation time 77973396068 ps
CPU time 2865.25 seconds
Started Aug 07 04:58:27 PM PDT 24
Finished Aug 07 05:46:13 PM PDT 24
Peak memory 229692 kb
Host smart-8167901a-5fb3-474e-8206-d971162bac10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033243595 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2033243595
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.354905709
Short name T134
Test name
Test status
Simulation time 257241969 ps
CPU time 5.18 seconds
Started Aug 07 04:58:36 PM PDT 24
Finished Aug 07 04:58:41 PM PDT 24
Peak memory 212032 kb
Host smart-022e7c5d-314a-4fc0-b883-33bb0d73e0c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354905709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.354905709
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.513317067
Short name T145
Test name
Test status
Simulation time 3339923097 ps
CPU time 95.66 seconds
Started Aug 07 04:58:49 PM PDT 24
Finished Aug 07 05:00:25 PM PDT 24
Peak memory 229072 kb
Host smart-55bd90b2-3880-4950-af11-e32a2b3211f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513317067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.513317067
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3535976952
Short name T314
Test name
Test status
Simulation time 2779921849 ps
CPU time 9.8 seconds
Started Aug 07 04:58:26 PM PDT 24
Finished Aug 07 04:58:36 PM PDT 24
Peak memory 212880 kb
Host smart-0a574050-508e-4c65-afda-52ac6db3aa1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535976952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3535976952
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1014567020
Short name T196
Test name
Test status
Simulation time 1140243808 ps
CPU time 5.31 seconds
Started Aug 07 04:58:38 PM PDT 24
Finished Aug 07 04:58:43 PM PDT 24
Peak memory 212128 kb
Host smart-4cac046c-cb3c-4bdc-8265-179740ce9dca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1014567020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1014567020
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2634999445
Short name T331
Test name
Test status
Simulation time 293787252 ps
CPU time 15.42 seconds
Started Aug 07 04:58:34 PM PDT 24
Finished Aug 07 04:58:50 PM PDT 24
Peak memory 214092 kb
Host smart-78846348-232b-4576-a293-19cf9f157f37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634999445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2634999445
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1306265537
Short name T276
Test name
Test status
Simulation time 87506294 ps
CPU time 4.32 seconds
Started Aug 07 04:58:24 PM PDT 24
Finished Aug 07 04:58:28 PM PDT 24
Peak memory 212076 kb
Host smart-de1f6572-b62a-4a4b-aad0-4ccd4227c63a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306265537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1306265537
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2175024855
Short name T313
Test name
Test status
Simulation time 7189318217 ps
CPU time 79.83 seconds
Started Aug 07 04:58:28 PM PDT 24
Finished Aug 07 04:59:48 PM PDT 24
Peak memory 226144 kb
Host smart-78b03778-256f-4e01-a7f5-25fe00b847e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175024855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2175024855
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1194313666
Short name T302
Test name
Test status
Simulation time 1036378767 ps
CPU time 11.17 seconds
Started Aug 07 04:58:29 PM PDT 24
Finished Aug 07 04:58:41 PM PDT 24
Peak memory 212880 kb
Host smart-8cca6445-063a-4348-bb2f-a92e477b6776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194313666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1194313666
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3552240424
Short name T232
Test name
Test status
Simulation time 425976944 ps
CPU time 6.5 seconds
Started Aug 07 04:58:49 PM PDT 24
Finished Aug 07 04:58:56 PM PDT 24
Peak memory 212020 kb
Host smart-7d79ad51-0700-431e-a5e4-898aab294432
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3552240424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3552240424
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2033863955
Short name T264
Test name
Test status
Simulation time 320745988 ps
CPU time 9.17 seconds
Started Aug 07 04:58:29 PM PDT 24
Finished Aug 07 04:58:39 PM PDT 24
Peak memory 212260 kb
Host smart-4d76bdef-7a61-4e6e-a129-435759abb598
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033863955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2033863955
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1245681036
Short name T269
Test name
Test status
Simulation time 90275265612 ps
CPU time 963.04 seconds
Started Aug 07 04:58:30 PM PDT 24
Finished Aug 07 05:14:34 PM PDT 24
Peak memory 236660 kb
Host smart-cf240ab3-5cc5-4cd0-ade3-7f321c4eabc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245681036 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1245681036
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3445218616
Short name T110
Test name
Test status
Simulation time 564355038 ps
CPU time 5.16 seconds
Started Aug 07 04:58:02 PM PDT 24
Finished Aug 07 04:58:07 PM PDT 24
Peak memory 211304 kb
Host smart-bfeceb63-3419-49be-a6a8-622ad9eb06ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445218616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3445218616
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3522760059
Short name T106
Test name
Test status
Simulation time 6478960246 ps
CPU time 84.41 seconds
Started Aug 07 04:57:46 PM PDT 24
Finished Aug 07 04:59:10 PM PDT 24
Peak memory 214480 kb
Host smart-bfa786d7-8039-4164-96e5-0be0d79b7ace
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522760059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3522760059
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1992867247
Short name T266
Test name
Test status
Simulation time 255094838 ps
CPU time 11.24 seconds
Started Aug 07 04:57:58 PM PDT 24
Finished Aug 07 04:58:10 PM PDT 24
Peak memory 212844 kb
Host smart-805e1ecc-19b0-4e9c-8ae5-af2ba07ac551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992867247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1992867247
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.623678171
Short name T270
Test name
Test status
Simulation time 390452850 ps
CPU time 5.77 seconds
Started Aug 07 04:57:49 PM PDT 24
Finished Aug 07 04:57:54 PM PDT 24
Peak memory 212140 kb
Host smart-826a008c-7cc0-4c34-8d11-bb030f7bcf2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=623678171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.623678171
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3915418889
Short name T72
Test name
Test status
Simulation time 279008659 ps
CPU time 6.33 seconds
Started Aug 07 04:57:48 PM PDT 24
Finished Aug 07 04:57:55 PM PDT 24
Peak memory 212044 kb
Host smart-b6324c55-d5e6-43dc-af27-93adfca77222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915418889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3915418889
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1661256920
Short name T186
Test name
Test status
Simulation time 338200179 ps
CPU time 7.13 seconds
Started Aug 07 04:57:57 PM PDT 24
Finished Aug 07 04:58:05 PM PDT 24
Peak memory 212112 kb
Host smart-3da01bb8-0e01-4c92-a332-a5ea6d2dcc0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661256920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1661256920
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2826282164
Short name T268
Test name
Test status
Simulation time 36870061545 ps
CPU time 863.75 seconds
Started Aug 07 04:58:09 PM PDT 24
Finished Aug 07 05:12:33 PM PDT 24
Peak memory 236612 kb
Host smart-49321df8-8197-4847-8f11-88e5edb94f06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826282164 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2826282164
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3405412631
Short name T182
Test name
Test status
Simulation time 508641789 ps
CPU time 7.92 seconds
Started Aug 07 04:58:32 PM PDT 24
Finished Aug 07 04:58:40 PM PDT 24
Peak memory 212084 kb
Host smart-a4fb03b1-8d04-4b68-abe3-e7c4425c532f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405412631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3405412631
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1561899188
Short name T272
Test name
Test status
Simulation time 2638088176 ps
CPU time 57.84 seconds
Started Aug 07 04:58:51 PM PDT 24
Finished Aug 07 04:59:49 PM PDT 24
Peak memory 212440 kb
Host smart-b928fa3e-9590-42aa-9dca-4bfb3052b6fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561899188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1561899188
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1630822377
Short name T321
Test name
Test status
Simulation time 252499835 ps
CPU time 11.14 seconds
Started Aug 07 04:58:47 PM PDT 24
Finished Aug 07 04:58:59 PM PDT 24
Peak memory 212932 kb
Host smart-68708d7e-4659-40a1-9eee-113c5fb70d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630822377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1630822377
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2854308559
Short name T254
Test name
Test status
Simulation time 536685453 ps
CPU time 6.56 seconds
Started Aug 07 04:58:37 PM PDT 24
Finished Aug 07 04:58:43 PM PDT 24
Peak memory 212164 kb
Host smart-d9e1bf77-d06c-4edf-a6da-07805717a690
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2854308559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2854308559
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1202619483
Short name T138
Test name
Test status
Simulation time 149409079 ps
CPU time 6.7 seconds
Started Aug 07 04:58:29 PM PDT 24
Finished Aug 07 04:58:36 PM PDT 24
Peak memory 212204 kb
Host smart-f048e7bc-16c4-4aec-94e6-074747439c45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202619483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1202619483
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3645549597
Short name T195
Test name
Test status
Simulation time 132469703 ps
CPU time 5.04 seconds
Started Aug 07 04:58:40 PM PDT 24
Finished Aug 07 04:58:45 PM PDT 24
Peak memory 211988 kb
Host smart-2ee66381-edca-4209-9eda-895be93d1706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645549597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3645549597
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3307970432
Short name T112
Test name
Test status
Simulation time 16171317992 ps
CPU time 102.87 seconds
Started Aug 07 04:58:38 PM PDT 24
Finished Aug 07 05:00:21 PM PDT 24
Peak memory 238472 kb
Host smart-c78ac7cb-8c89-445f-af08-7ade60364bcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307970432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3307970432
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1411119503
Short name T107
Test name
Test status
Simulation time 263594263 ps
CPU time 11 seconds
Started Aug 07 04:58:58 PM PDT 24
Finished Aug 07 04:59:09 PM PDT 24
Peak memory 212832 kb
Host smart-7396e99d-2729-41c1-83a0-e565f2d4cea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411119503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1411119503
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3216644931
Short name T316
Test name
Test status
Simulation time 97829646 ps
CPU time 5.63 seconds
Started Aug 07 04:58:59 PM PDT 24
Finished Aug 07 04:59:05 PM PDT 24
Peak memory 212024 kb
Host smart-07db20bb-9175-4c9a-a4f7-cfd48d8c3541
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3216644931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3216644931
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.4247902731
Short name T31
Test name
Test status
Simulation time 211764142 ps
CPU time 13.91 seconds
Started Aug 07 04:58:50 PM PDT 24
Finished Aug 07 04:59:05 PM PDT 24
Peak memory 214888 kb
Host smart-4a6e5ecf-1f88-45cf-8847-5f1e43a211a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247902731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.4247902731
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1511220533
Short name T281
Test name
Test status
Simulation time 129860918 ps
CPU time 5.12 seconds
Started Aug 07 04:58:27 PM PDT 24
Finished Aug 07 04:58:37 PM PDT 24
Peak memory 211936 kb
Host smart-4f0f4d57-80fe-4e03-bfad-7a3c90c55705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511220533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1511220533
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3062247594
Short name T193
Test name
Test status
Simulation time 4971751005 ps
CPU time 120.37 seconds
Started Aug 07 04:58:29 PM PDT 24
Finished Aug 07 05:00:29 PM PDT 24
Peak memory 238980 kb
Host smart-70ccc4d2-a787-4487-b992-3c1ad3983342
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062247594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3062247594
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2200709089
Short name T218
Test name
Test status
Simulation time 342738012 ps
CPU time 9.6 seconds
Started Aug 07 04:58:30 PM PDT 24
Finished Aug 07 04:58:40 PM PDT 24
Peak memory 212936 kb
Host smart-5ecb40ba-ba1d-476e-96c6-8addb9d9476a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200709089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2200709089
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.904178646
Short name T287
Test name
Test status
Simulation time 578484420 ps
CPU time 5.94 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:58:47 PM PDT 24
Peak memory 212032 kb
Host smart-b443f430-4cd6-4fb7-979a-4bdb6145127e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=904178646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.904178646
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1381927040
Short name T230
Test name
Test status
Simulation time 168931112 ps
CPU time 13.25 seconds
Started Aug 07 04:58:33 PM PDT 24
Finished Aug 07 04:58:47 PM PDT 24
Peak memory 212092 kb
Host smart-1c7806af-c9a6-4965-bf40-c3557a1ad666
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381927040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1381927040
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1940996653
Short name T267
Test name
Test status
Simulation time 85880375 ps
CPU time 4.42 seconds
Started Aug 07 04:58:28 PM PDT 24
Finished Aug 07 04:58:33 PM PDT 24
Peak memory 212068 kb
Host smart-736001ba-77a3-4347-97de-f802279de963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940996653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1940996653
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3146791766
Short name T255
Test name
Test status
Simulation time 1346139448 ps
CPU time 102.38 seconds
Started Aug 07 04:58:34 PM PDT 24
Finished Aug 07 05:00:16 PM PDT 24
Peak memory 237920 kb
Host smart-217964a3-ab28-474e-a6a2-125413f31094
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146791766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3146791766
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.361054078
Short name T113
Test name
Test status
Simulation time 670991926 ps
CPU time 9.3 seconds
Started Aug 07 04:58:36 PM PDT 24
Finished Aug 07 04:58:45 PM PDT 24
Peak memory 212852 kb
Host smart-7523991d-a436-4f8a-89f6-0d0affbbfd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361054078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.361054078
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2284699558
Short name T10
Test name
Test status
Simulation time 228292607 ps
CPU time 5.11 seconds
Started Aug 07 04:58:45 PM PDT 24
Finished Aug 07 04:58:50 PM PDT 24
Peak memory 212032 kb
Host smart-dcb41360-ddf4-4a9d-a4d8-d7f2ede29d4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2284699558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2284699558
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2058571136
Short name T238
Test name
Test status
Simulation time 354112574 ps
CPU time 9.25 seconds
Started Aug 07 04:58:29 PM PDT 24
Finished Aug 07 04:58:39 PM PDT 24
Peak memory 212124 kb
Host smart-6758a53f-9382-46de-ac23-743769444e9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058571136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2058571136
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2936526620
Short name T308
Test name
Test status
Simulation time 349998011 ps
CPU time 4.12 seconds
Started Aug 07 04:58:49 PM PDT 24
Finished Aug 07 04:58:53 PM PDT 24
Peak memory 211916 kb
Host smart-4db44154-e531-4504-b7b2-c5f93b7ae20e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936526620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2936526620
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3812311772
Short name T297
Test name
Test status
Simulation time 17566693034 ps
CPU time 209.33 seconds
Started Aug 07 04:58:32 PM PDT 24
Finished Aug 07 05:02:02 PM PDT 24
Peak memory 226044 kb
Host smart-8ef72e1e-3b0b-485f-aaea-c53318f382ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812311772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3812311772
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2400790011
Short name T41
Test name
Test status
Simulation time 1509023490 ps
CPU time 9.32 seconds
Started Aug 07 04:58:39 PM PDT 24
Finished Aug 07 04:58:49 PM PDT 24
Peak memory 212848 kb
Host smart-fc4d7779-8f70-4144-bb33-1f59f5fdcb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400790011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2400790011
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.625898840
Short name T220
Test name
Test status
Simulation time 380233871 ps
CPU time 5.27 seconds
Started Aug 07 04:58:35 PM PDT 24
Finished Aug 07 04:58:41 PM PDT 24
Peak memory 212072 kb
Host smart-aa983056-832e-49a6-a304-0318ce386e14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625898840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.625898840
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4035956371
Short name T319
Test name
Test status
Simulation time 768957620 ps
CPU time 13.39 seconds
Started Aug 07 04:58:32 PM PDT 24
Finished Aug 07 04:58:45 PM PDT 24
Peak memory 214288 kb
Host smart-df36fedb-ea54-42eb-953e-fb8a34793237
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035956371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4035956371
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3488232660
Short name T171
Test name
Test status
Simulation time 130829429 ps
CPU time 5.2 seconds
Started Aug 07 04:58:26 PM PDT 24
Finished Aug 07 04:58:31 PM PDT 24
Peak memory 211912 kb
Host smart-c8a44e4a-67be-4b63-8f4b-01c62a1219a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488232660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3488232660
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2956230134
Short name T216
Test name
Test status
Simulation time 7005093124 ps
CPU time 63.85 seconds
Started Aug 07 04:58:30 PM PDT 24
Finished Aug 07 04:59:34 PM PDT 24
Peak memory 228540 kb
Host smart-11746b72-4ebd-48d1-b4b7-dd554fce45df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956230134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2956230134
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2361421801
Short name T257
Test name
Test status
Simulation time 1034379724 ps
CPU time 11.55 seconds
Started Aug 07 04:58:48 PM PDT 24
Finished Aug 07 04:59:05 PM PDT 24
Peak memory 212848 kb
Host smart-e4580aa3-da3b-4e52-927d-3684236f8ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361421801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2361421801
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1114562480
Short name T260
Test name
Test status
Simulation time 97342767 ps
CPU time 5.65 seconds
Started Aug 07 04:58:36 PM PDT 24
Finished Aug 07 04:58:42 PM PDT 24
Peak memory 212192 kb
Host smart-57182464-1d15-40d7-965e-c65baf20eb64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1114562480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1114562480
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1475053108
Short name T104
Test name
Test status
Simulation time 170814871 ps
CPU time 9.22 seconds
Started Aug 07 04:58:30 PM PDT 24
Finished Aug 07 04:58:39 PM PDT 24
Peak memory 212128 kb
Host smart-dd330fa4-73e1-4125-8c64-14fb57dba8ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475053108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1475053108
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2399718815
Short name T185
Test name
Test status
Simulation time 447751939 ps
CPU time 5.07 seconds
Started Aug 07 04:58:39 PM PDT 24
Finished Aug 07 04:58:44 PM PDT 24
Peak memory 211976 kb
Host smart-59cebcfe-48db-43a7-878b-f4d6ffadab46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399718815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2399718815
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.405063320
Short name T37
Test name
Test status
Simulation time 2464512492 ps
CPU time 136.74 seconds
Started Aug 07 04:58:39 PM PDT 24
Finished Aug 07 05:00:56 PM PDT 24
Peak memory 238384 kb
Host smart-377cfc30-03d7-4e05-833a-d56dbe93236e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405063320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.405063320
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3640224580
Short name T253
Test name
Test status
Simulation time 3931267603 ps
CPU time 16.68 seconds
Started Aug 07 04:58:55 PM PDT 24
Finished Aug 07 04:59:12 PM PDT 24
Peak memory 212956 kb
Host smart-28e53892-11ba-47cf-aec4-eb4c812a54b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640224580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3640224580
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1546410631
Short name T7
Test name
Test status
Simulation time 98777951 ps
CPU time 5.56 seconds
Started Aug 07 04:58:42 PM PDT 24
Finished Aug 07 04:58:47 PM PDT 24
Peak memory 212180 kb
Host smart-e87430bc-9636-4699-9080-1816edc5a365
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1546410631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1546410631
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1104253783
Short name T142
Test name
Test status
Simulation time 561066398 ps
CPU time 15.46 seconds
Started Aug 07 04:58:36 PM PDT 24
Finished Aug 07 04:58:52 PM PDT 24
Peak memory 214348 kb
Host smart-943e74cb-c433-4846-9741-c86ec009922c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104253783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1104253783
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.447394797
Short name T197
Test name
Test status
Simulation time 71720356319 ps
CPU time 1381.55 seconds
Started Aug 07 04:58:39 PM PDT 24
Finished Aug 07 05:21:41 PM PDT 24
Peak memory 236568 kb
Host smart-794915e2-4df1-4b9f-9767-64ab9aa1e6fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447394797 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.447394797
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1538899730
Short name T123
Test name
Test status
Simulation time 132126727 ps
CPU time 5.19 seconds
Started Aug 07 04:58:45 PM PDT 24
Finished Aug 07 04:58:50 PM PDT 24
Peak memory 211968 kb
Host smart-e667375d-2ede-49f7-ac82-bb2148f6dd2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538899730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1538899730
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3708905211
Short name T217
Test name
Test status
Simulation time 5684774390 ps
CPU time 80.72 seconds
Started Aug 07 04:58:32 PM PDT 24
Finished Aug 07 04:59:53 PM PDT 24
Peak memory 213480 kb
Host smart-5031c381-112a-48c1-8896-19bb0576cc99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708905211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3708905211
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.497580177
Short name T315
Test name
Test status
Simulation time 1084430573 ps
CPU time 10.61 seconds
Started Aug 07 04:58:42 PM PDT 24
Finished Aug 07 04:58:53 PM PDT 24
Peak memory 212824 kb
Host smart-48c5d98f-94b4-4d97-91f3-6eab52ffc5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497580177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.497580177
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2991690621
Short name T283
Test name
Test status
Simulation time 96845919 ps
CPU time 5.31 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:58:46 PM PDT 24
Peak memory 212192 kb
Host smart-f247efd2-53c1-4c3c-a6d1-69dde1312b61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2991690621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2991690621
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2144211324
Short name T286
Test name
Test status
Simulation time 291128318 ps
CPU time 19.55 seconds
Started Aug 07 04:58:46 PM PDT 24
Finished Aug 07 04:59:05 PM PDT 24
Peak memory 215368 kb
Host smart-e5086db8-f306-47a7-8189-0178b17351f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144211324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2144211324
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3916729456
Short name T235
Test name
Test status
Simulation time 159006963853 ps
CPU time 1574.67 seconds
Started Aug 07 04:58:36 PM PDT 24
Finished Aug 07 05:24:51 PM PDT 24
Peak memory 238600 kb
Host smart-5366272f-2c5f-4311-a1eb-cadcebcb287c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916729456 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.3916729456
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1551690308
Short name T120
Test name
Test status
Simulation time 200351785 ps
CPU time 4.16 seconds
Started Aug 07 04:58:40 PM PDT 24
Finished Aug 07 04:58:44 PM PDT 24
Peak memory 212260 kb
Host smart-e82dbbe0-f20d-419f-89d7-7e5372f80747
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551690308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1551690308
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1367172164
Short name T202
Test name
Test status
Simulation time 1403170651 ps
CPU time 89.59 seconds
Started Aug 07 04:58:40 PM PDT 24
Finished Aug 07 05:00:09 PM PDT 24
Peak memory 225196 kb
Host smart-21a12d3f-41e5-4799-9dc9-f19dfefc5b80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367172164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1367172164
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1894783532
Short name T22
Test name
Test status
Simulation time 1033717533 ps
CPU time 15.65 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:58:56 PM PDT 24
Peak memory 212792 kb
Host smart-dc71649e-c16b-400a-8c9c-db094fafcf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894783532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1894783532
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.585202608
Short name T162
Test name
Test status
Simulation time 738827814 ps
CPU time 6.35 seconds
Started Aug 07 04:58:38 PM PDT 24
Finished Aug 07 04:58:45 PM PDT 24
Peak memory 212184 kb
Host smart-299811eb-0e12-4744-bbbf-3a096c9ae353
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585202608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.585202608
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3449608341
Short name T296
Test name
Test status
Simulation time 1633250301 ps
CPU time 22.47 seconds
Started Aug 07 04:58:48 PM PDT 24
Finished Aug 07 04:59:11 PM PDT 24
Peak memory 216644 kb
Host smart-dfea02f6-590e-489e-aeeb-45f625a3909e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449608341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3449608341
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2531743022
Short name T132
Test name
Test status
Simulation time 251169284 ps
CPU time 5.13 seconds
Started Aug 07 04:58:44 PM PDT 24
Finished Aug 07 04:58:50 PM PDT 24
Peak memory 211960 kb
Host smart-5c9b7468-1ce1-4fc8-8b09-b3f3be0ab1b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531743022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2531743022
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3736693918
Short name T211
Test name
Test status
Simulation time 252010911 ps
CPU time 11.26 seconds
Started Aug 07 04:58:30 PM PDT 24
Finished Aug 07 04:58:42 PM PDT 24
Peak memory 212920 kb
Host smart-7777ad3d-be51-4bcd-bade-193fb6b3b6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736693918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3736693918
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.4257543537
Short name T184
Test name
Test status
Simulation time 254238972 ps
CPU time 6.62 seconds
Started Aug 07 04:58:41 PM PDT 24
Finished Aug 07 04:58:48 PM PDT 24
Peak memory 212380 kb
Host smart-ec394cae-dabd-415a-93b6-95fdf7ca5c5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4257543537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.4257543537
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1012979996
Short name T330
Test name
Test status
Simulation time 382544882 ps
CPU time 10.43 seconds
Started Aug 07 04:58:38 PM PDT 24
Finished Aug 07 04:58:49 PM PDT 24
Peak memory 215056 kb
Host smart-f6da5069-041a-4485-8c97-5c27bbf129f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012979996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1012979996
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2452829784
Short name T43
Test name
Test status
Simulation time 48431762418 ps
CPU time 1842.71 seconds
Started Aug 07 04:58:47 PM PDT 24
Finished Aug 07 05:29:30 PM PDT 24
Peak memory 236672 kb
Host smart-162b4332-5227-4bad-97e4-f06a29105786
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452829784 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2452829784
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2214755186
Short name T215
Test name
Test status
Simulation time 114679586 ps
CPU time 4.11 seconds
Started Aug 07 04:57:54 PM PDT 24
Finished Aug 07 04:57:58 PM PDT 24
Peak memory 212092 kb
Host smart-efde006b-357c-41a3-bb1e-1765bd1daa56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214755186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2214755186
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2548838494
Short name T317
Test name
Test status
Simulation time 7636216877 ps
CPU time 80.41 seconds
Started Aug 07 04:57:49 PM PDT 24
Finished Aug 07 04:59:10 PM PDT 24
Peak memory 238308 kb
Host smart-0fdbc8e5-d2a6-478e-96e3-a642c4b72218
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548838494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2548838494
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3079859489
Short name T178
Test name
Test status
Simulation time 1085051382 ps
CPU time 10.61 seconds
Started Aug 07 04:58:40 PM PDT 24
Finished Aug 07 04:58:51 PM PDT 24
Peak memory 212896 kb
Host smart-9ab675d9-c44e-4f50-9390-89d937d4aded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079859489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3079859489
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1964239481
Short name T8
Test name
Test status
Simulation time 1120180752 ps
CPU time 6.72 seconds
Started Aug 07 04:57:45 PM PDT 24
Finished Aug 07 04:57:52 PM PDT 24
Peak memory 212140 kb
Host smart-76ac1560-c8fa-4e8f-99db-5a96bb1e93f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1964239481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1964239481
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1191461610
Short name T137
Test name
Test status
Simulation time 551842750 ps
CPU time 6.51 seconds
Started Aug 07 04:58:03 PM PDT 24
Finished Aug 07 04:58:09 PM PDT 24
Peak memory 212184 kb
Host smart-c1fa0418-14cc-44ad-b6bd-2a84e97fc30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191461610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1191461610
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3168163046
Short name T290
Test name
Test status
Simulation time 818774190 ps
CPU time 12.05 seconds
Started Aug 07 04:57:55 PM PDT 24
Finished Aug 07 04:58:08 PM PDT 24
Peak memory 214344 kb
Host smart-e7dd4524-9345-44a3-9d0f-c7c365000876
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168163046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3168163046
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3444235416
Short name T274
Test name
Test status
Simulation time 146593455293 ps
CPU time 1208.43 seconds
Started Aug 07 04:58:01 PM PDT 24
Finished Aug 07 05:18:10 PM PDT 24
Peak memory 234180 kb
Host smart-5002afed-3171-4ed6-956a-69dd703a12bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444235416 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.3444235416
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.14176346
Short name T278
Test name
Test status
Simulation time 883718470 ps
CPU time 5.13 seconds
Started Aug 07 04:57:49 PM PDT 24
Finished Aug 07 04:57:55 PM PDT 24
Peak memory 212008 kb
Host smart-4d5701d7-7fa2-479c-b832-dea182929297
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14176346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.14176346
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3106923108
Short name T210
Test name
Test status
Simulation time 29040259617 ps
CPU time 125.56 seconds
Started Aug 07 04:58:03 PM PDT 24
Finished Aug 07 05:00:09 PM PDT 24
Peak memory 234964 kb
Host smart-f39eb780-32db-4d04-8687-d7893f1a352c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106923108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3106923108
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1682351264
Short name T157
Test name
Test status
Simulation time 1557278301 ps
CPU time 11.32 seconds
Started Aug 07 04:58:08 PM PDT 24
Finished Aug 07 04:58:19 PM PDT 24
Peak memory 212836 kb
Host smart-b0d22edd-5642-4fdf-b864-37ac2924f95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682351264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1682351264
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2929293172
Short name T323
Test name
Test status
Simulation time 404866078 ps
CPU time 5.63 seconds
Started Aug 07 04:58:09 PM PDT 24
Finished Aug 07 04:58:15 PM PDT 24
Peak memory 212076 kb
Host smart-f5f20a1f-2144-435d-805c-c046d56e008a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2929293172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2929293172
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.407491004
Short name T242
Test name
Test status
Simulation time 527394728 ps
CPU time 6.57 seconds
Started Aug 07 04:57:52 PM PDT 24
Finished Aug 07 04:57:58 PM PDT 24
Peak memory 212432 kb
Host smart-df36cbcb-60aa-4aab-9153-5b636dc81e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407491004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.407491004
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1106115892
Short name T256
Test name
Test status
Simulation time 578122645 ps
CPU time 16.89 seconds
Started Aug 07 04:58:02 PM PDT 24
Finished Aug 07 04:58:19 PM PDT 24
Peak memory 217088 kb
Host smart-0dd53461-9d30-4a2b-90ff-2fefc342954e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106115892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1106115892
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2080783158
Short name T133
Test name
Test status
Simulation time 308189579 ps
CPU time 4.35 seconds
Started Aug 07 04:58:03 PM PDT 24
Finished Aug 07 04:58:07 PM PDT 24
Peak memory 212068 kb
Host smart-b03a34ad-dec0-4c6d-9ea3-d290f310499b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080783158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2080783158
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2810520037
Short name T130
Test name
Test status
Simulation time 4011329268 ps
CPU time 132.93 seconds
Started Aug 07 04:58:55 PM PDT 24
Finished Aug 07 05:01:08 PM PDT 24
Peak memory 238388 kb
Host smart-a9c1c676-63b2-4c33-a32b-561387b4d279
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810520037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2810520037
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.153065891
Short name T219
Test name
Test status
Simulation time 510780075 ps
CPU time 11.16 seconds
Started Aug 07 04:57:49 PM PDT 24
Finished Aug 07 04:58:00 PM PDT 24
Peak memory 213104 kb
Host smart-a1d47362-0aa3-472d-9da3-0979db9405a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153065891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.153065891
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.822163036
Short name T299
Test name
Test status
Simulation time 521315761 ps
CPU time 8.86 seconds
Started Aug 07 04:57:51 PM PDT 24
Finished Aug 07 04:58:00 PM PDT 24
Peak memory 212144 kb
Host smart-2d98c399-a23a-4234-a119-0b6080a36961
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=822163036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.822163036
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2014696807
Short name T12
Test name
Test status
Simulation time 1035685512 ps
CPU time 5.62 seconds
Started Aug 07 04:58:25 PM PDT 24
Finished Aug 07 04:58:31 PM PDT 24
Peak memory 212100 kb
Host smart-430abc37-a625-48bc-bbae-2e13c9391ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014696807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2014696807
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3564437544
Short name T28
Test name
Test status
Simulation time 292739870 ps
CPU time 15.63 seconds
Started Aug 07 04:57:51 PM PDT 24
Finished Aug 07 04:58:06 PM PDT 24
Peak memory 214852 kb
Host smart-77e5028b-5e34-475f-83cb-98c7f8aaba13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564437544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3564437544
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.281879265
Short name T45
Test name
Test status
Simulation time 28686690010 ps
CPU time 6160.18 seconds
Started Aug 07 04:57:59 PM PDT 24
Finished Aug 07 06:40:40 PM PDT 24
Peak memory 230156 kb
Host smart-8382c991-4c7a-4049-8f6c-8309cd1a267f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281879265 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.281879265
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4248460329
Short name T207
Test name
Test status
Simulation time 350526144 ps
CPU time 4.23 seconds
Started Aug 07 04:57:46 PM PDT 24
Finished Aug 07 04:57:50 PM PDT 24
Peak memory 211968 kb
Host smart-653bed8e-1896-48ba-b9d2-23a166563f3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248460329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4248460329
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1022502725
Short name T241
Test name
Test status
Simulation time 7234812800 ps
CPU time 72.71 seconds
Started Aug 07 04:57:49 PM PDT 24
Finished Aug 07 04:59:02 PM PDT 24
Peak memory 213352 kb
Host smart-33c36e16-8673-45e7-ad5e-6d16c0d01c7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022502725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1022502725
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.4017092283
Short name T168
Test name
Test status
Simulation time 260928600 ps
CPU time 11.44 seconds
Started Aug 07 04:58:07 PM PDT 24
Finished Aug 07 04:58:19 PM PDT 24
Peak memory 212860 kb
Host smart-b82a2e80-6e30-451e-9236-cf66b7c61fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017092283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.4017092283
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1334715372
Short name T118
Test name
Test status
Simulation time 373329896 ps
CPU time 5.52 seconds
Started Aug 07 04:57:52 PM PDT 24
Finished Aug 07 04:57:57 PM PDT 24
Peak memory 212064 kb
Host smart-22931ef9-164e-45a0-8fad-47f5d93095a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1334715372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1334715372
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.626670180
Short name T150
Test name
Test status
Simulation time 204945111 ps
CPU time 5.66 seconds
Started Aug 07 04:58:11 PM PDT 24
Finished Aug 07 04:58:17 PM PDT 24
Peak memory 212056 kb
Host smart-6414dd8f-7be6-46b4-8b87-8dddbb216267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626670180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.626670180
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1287003235
Short name T329
Test name
Test status
Simulation time 506265464 ps
CPU time 14.26 seconds
Started Aug 07 04:57:49 PM PDT 24
Finished Aug 07 04:58:03 PM PDT 24
Peak memory 213180 kb
Host smart-1d65b279-5267-403c-b93d-b6cd8e0de68e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287003235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1287003235
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.773827432
Short name T322
Test name
Test status
Simulation time 259742979 ps
CPU time 5.04 seconds
Started Aug 07 04:57:57 PM PDT 24
Finished Aug 07 04:58:02 PM PDT 24
Peak memory 212028 kb
Host smart-87dd6ad3-9a80-4e65-af56-3f96a66cfd36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773827432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.773827432
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2228287314
Short name T16
Test name
Test status
Simulation time 4401175455 ps
CPU time 144.26 seconds
Started Aug 07 04:57:59 PM PDT 24
Finished Aug 07 05:00:23 PM PDT 24
Peak memory 238496 kb
Host smart-f7161f90-6d0b-415d-b510-7249d1d12161
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228287314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2228287314
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1771393380
Short name T205
Test name
Test status
Simulation time 256452637 ps
CPU time 11.2 seconds
Started Aug 07 04:59:00 PM PDT 24
Finished Aug 07 04:59:11 PM PDT 24
Peak memory 212948 kb
Host smart-b47900cb-73d3-4f9f-a498-38912e199b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771393380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1771393380
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1271498798
Short name T231
Test name
Test status
Simulation time 1011889000 ps
CPU time 8.85 seconds
Started Aug 07 04:57:55 PM PDT 24
Finished Aug 07 04:58:04 PM PDT 24
Peak memory 212184 kb
Host smart-fbd50819-e484-4367-8314-ea6f7704a2de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1271498798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1271498798
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.902494977
Short name T67
Test name
Test status
Simulation time 214462950 ps
CPU time 5.54 seconds
Started Aug 07 04:58:13 PM PDT 24
Finished Aug 07 04:58:18 PM PDT 24
Peak memory 212056 kb
Host smart-1ff51b57-9791-49e3-861a-f773995d4d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902494977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.902494977
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3692701658
Short name T69
Test name
Test status
Simulation time 624744091 ps
CPU time 14.73 seconds
Started Aug 07 04:58:16 PM PDT 24
Finished Aug 07 04:58:31 PM PDT 24
Peak memory 213984 kb
Host smart-a9138a9f-d784-4369-89a9-b09c48df14cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692701658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3692701658
Directory /workspace/9.rom_ctrl_stress_all/latest
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