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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.24 96.89 91.99 97.67 100.00 98.28 97.45 98.37


Total test records in report: 424
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T298 /workspace/coverage/default/29.rom_ctrl_alert_test.427329877 Aug 10 05:37:20 PM PDT 24 Aug 10 05:37:24 PM PDT 24 204952922 ps
T299 /workspace/coverage/default/17.rom_ctrl_stress_all.1947631787 Aug 10 05:37:00 PM PDT 24 Aug 10 05:37:20 PM PDT 24 1641247447 ps
T300 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2070650746 Aug 10 05:36:49 PM PDT 24 Aug 10 05:38:40 PM PDT 24 2290879027 ps
T301 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4036438475 Aug 10 05:37:12 PM PDT 24 Aug 10 05:37:23 PM PDT 24 252334987 ps
T302 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3966467476 Aug 10 05:36:35 PM PDT 24 Aug 10 05:36:41 PM PDT 24 142464315 ps
T303 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.230415030 Aug 10 05:37:18 PM PDT 24 Aug 10 05:39:18 PM PDT 24 1723675783 ps
T304 /workspace/coverage/default/15.rom_ctrl_stress_all.2501885817 Aug 10 05:36:50 PM PDT 24 Aug 10 05:37:11 PM PDT 24 1028850766 ps
T305 /workspace/coverage/default/5.rom_ctrl_stress_all.626164910 Aug 10 05:36:34 PM PDT 24 Aug 10 05:36:55 PM PDT 24 1459228760 ps
T306 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2830101872 Aug 10 05:37:46 PM PDT 24 Aug 10 05:37:57 PM PDT 24 256374229 ps
T307 /workspace/coverage/default/39.rom_ctrl_stress_all.2168756549 Aug 10 05:37:32 PM PDT 24 Aug 10 05:37:43 PM PDT 24 368973912 ps
T308 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1856917144 Aug 10 05:36:58 PM PDT 24 Aug 10 05:38:54 PM PDT 24 8194313635 ps
T309 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.148739870 Aug 10 05:37:33 PM PDT 24 Aug 10 05:37:49 PM PDT 24 4283221507 ps
T310 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2465346074 Aug 10 05:37:37 PM PDT 24 Aug 10 05:37:42 PM PDT 24 94941835 ps
T311 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.109556692 Aug 10 05:37:12 PM PDT 24 Aug 10 05:37:22 PM PDT 24 669281643 ps
T312 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.18070783 Aug 10 05:37:24 PM PDT 24 Aug 10 05:37:35 PM PDT 24 998422643 ps
T313 /workspace/coverage/default/0.rom_ctrl_stress_all.2802700370 Aug 10 05:36:19 PM PDT 24 Aug 10 05:36:32 PM PDT 24 1129616247 ps
T314 /workspace/coverage/default/23.rom_ctrl_stress_all.3150328758 Aug 10 05:37:08 PM PDT 24 Aug 10 05:37:20 PM PDT 24 564582461 ps
T315 /workspace/coverage/default/33.rom_ctrl_alert_test.1842804067 Aug 10 05:37:23 PM PDT 24 Aug 10 05:37:28 PM PDT 24 126389975 ps
T316 /workspace/coverage/default/28.rom_ctrl_alert_test.2198934377 Aug 10 05:37:15 PM PDT 24 Aug 10 05:37:20 PM PDT 24 518739251 ps
T317 /workspace/coverage/default/11.rom_ctrl_alert_test.3500992379 Aug 10 05:36:48 PM PDT 24 Aug 10 05:36:53 PM PDT 24 522961251 ps
T318 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1148260047 Aug 10 05:37:00 PM PDT 24 Aug 10 05:37:10 PM PDT 24 188472150 ps
T319 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2724480522 Aug 10 05:37:31 PM PDT 24 Aug 10 05:37:37 PM PDT 24 365397463 ps
T24 /workspace/coverage/default/1.rom_ctrl_sec_cm.487023277 Aug 10 05:36:28 PM PDT 24 Aug 10 05:37:22 PM PDT 24 1156775795 ps
T320 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2749186497 Aug 10 05:36:59 PM PDT 24 Aug 10 05:39:22 PM PDT 24 2639154082 ps
T321 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.387315626 Aug 10 05:37:32 PM PDT 24 Aug 10 05:37:49 PM PDT 24 4110739542 ps
T322 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2223754428 Aug 10 05:37:45 PM PDT 24 Aug 10 05:37:51 PM PDT 24 136304158 ps
T323 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1018070320 Aug 10 05:37:31 PM PDT 24 Aug 10 05:37:37 PM PDT 24 102611089 ps
T324 /workspace/coverage/default/25.rom_ctrl_stress_all.2195460366 Aug 10 05:37:08 PM PDT 24 Aug 10 05:37:26 PM PDT 24 1921850275 ps
T325 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1358153759 Aug 10 05:37:31 PM PDT 24 Aug 10 05:39:45 PM PDT 24 2109393225 ps
T56 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4191552402 Aug 10 05:38:11 PM PDT 24 Aug 10 05:38:16 PM PDT 24 132225747 ps
T57 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.232536708 Aug 10 05:38:03 PM PDT 24 Aug 10 05:38:08 PM PDT 24 1380617342 ps
T58 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3572033757 Aug 10 05:37:53 PM PDT 24 Aug 10 05:37:58 PM PDT 24 129758225 ps
T53 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3402912624 Aug 10 05:38:02 PM PDT 24 Aug 10 05:38:41 PM PDT 24 224544455 ps
T61 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2178766076 Aug 10 05:38:30 PM PDT 24 Aug 10 05:38:35 PM PDT 24 623831702 ps
T62 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2390556041 Aug 10 05:38:27 PM PDT 24 Aug 10 05:38:54 PM PDT 24 558861155 ps
T54 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.488207265 Aug 10 05:37:52 PM PDT 24 Aug 10 05:39:02 PM PDT 24 2418225169 ps
T91 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4026756737 Aug 10 05:38:19 PM PDT 24 Aug 10 05:38:24 PM PDT 24 192187256 ps
T326 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.433427658 Aug 10 05:38:19 PM PDT 24 Aug 10 05:38:28 PM PDT 24 130932589 ps
T327 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2188812648 Aug 10 05:38:10 PM PDT 24 Aug 10 05:38:15 PM PDT 24 138461459 ps
T55 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1475277848 Aug 10 05:38:03 PM PDT 24 Aug 10 05:39:13 PM PDT 24 1158285951 ps
T63 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.627892327 Aug 10 05:38:20 PM PDT 24 Aug 10 05:38:27 PM PDT 24 554957969 ps
T64 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1872789008 Aug 10 05:38:20 PM PDT 24 Aug 10 05:38:24 PM PDT 24 287237776 ps
T328 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2948063213 Aug 10 05:37:53 PM PDT 24 Aug 10 05:37:58 PM PDT 24 129265603 ps
T329 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.175448118 Aug 10 05:38:30 PM PDT 24 Aug 10 05:38:36 PM PDT 24 313118920 ps
T65 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4254759582 Aug 10 05:38:26 PM PDT 24 Aug 10 05:38:54 PM PDT 24 7709540103 ps
T97 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3025620901 Aug 10 05:38:04 PM PDT 24 Aug 10 05:38:09 PM PDT 24 126803757 ps
T66 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3265566406 Aug 10 05:38:36 PM PDT 24 Aug 10 05:38:41 PM PDT 24 345611118 ps
T330 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4260993074 Aug 10 05:38:02 PM PDT 24 Aug 10 05:38:10 PM PDT 24 134038970 ps
T331 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4114778315 Aug 10 05:38:05 PM PDT 24 Aug 10 05:38:09 PM PDT 24 173003719 ps
T67 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.454262502 Aug 10 05:38:03 PM PDT 24 Aug 10 05:38:08 PM PDT 24 127838669 ps
T109 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3937876911 Aug 10 05:38:03 PM PDT 24 Aug 10 05:38:40 PM PDT 24 370618937 ps
T332 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3969897392 Aug 10 05:38:26 PM PDT 24 Aug 10 05:38:32 PM PDT 24 551666578 ps
T333 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2130524853 Aug 10 05:38:04 PM PDT 24 Aug 10 05:38:09 PM PDT 24 86398403 ps
T68 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3025171604 Aug 10 05:38:18 PM PDT 24 Aug 10 05:38:23 PM PDT 24 132847509 ps
T334 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.540273230 Aug 10 05:38:27 PM PDT 24 Aug 10 05:38:32 PM PDT 24 266356936 ps
T103 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3188320391 Aug 10 05:38:11 PM PDT 24 Aug 10 05:38:43 PM PDT 24 3280900685 ps
T92 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3849989259 Aug 10 05:38:17 PM PDT 24 Aug 10 05:38:21 PM PDT 24 86419359 ps
T76 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2274134068 Aug 10 05:37:54 PM PDT 24 Aug 10 05:38:21 PM PDT 24 1102409396 ps
T93 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2952072324 Aug 10 05:38:03 PM PDT 24 Aug 10 05:38:08 PM PDT 24 250875976 ps
T113 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3837197724 Aug 10 05:38:36 PM PDT 24 Aug 10 05:39:46 PM PDT 24 1619889289 ps
T335 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.203739944 Aug 10 05:38:02 PM PDT 24 Aug 10 05:38:07 PM PDT 24 130695037 ps
T77 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.986341663 Aug 10 05:38:04 PM PDT 24 Aug 10 05:38:37 PM PDT 24 3278783009 ps
T336 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3097357335 Aug 10 05:38:28 PM PDT 24 Aug 10 05:38:36 PM PDT 24 162818863 ps
T337 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2890663258 Aug 10 05:38:18 PM PDT 24 Aug 10 05:38:24 PM PDT 24 145587566 ps
T106 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2719947728 Aug 10 05:38:36 PM PDT 24 Aug 10 05:39:50 PM PDT 24 400980454 ps
T94 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3702982348 Aug 10 05:38:13 PM PDT 24 Aug 10 05:38:18 PM PDT 24 133798313 ps
T338 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.858108673 Aug 10 05:38:19 PM PDT 24 Aug 10 05:38:26 PM PDT 24 131631932 ps
T339 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1790911750 Aug 10 05:38:04 PM PDT 24 Aug 10 05:38:08 PM PDT 24 332700261 ps
T340 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3214977689 Aug 10 05:38:04 PM PDT 24 Aug 10 05:38:11 PM PDT 24 293233194 ps
T78 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.590768037 Aug 10 05:37:55 PM PDT 24 Aug 10 05:38:00 PM PDT 24 569958289 ps
T341 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.223810276 Aug 10 05:38:18 PM PDT 24 Aug 10 05:38:40 PM PDT 24 1097407083 ps
T342 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1768849258 Aug 10 05:38:17 PM PDT 24 Aug 10 05:38:22 PM PDT 24 530274856 ps
T343 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4179251627 Aug 10 05:38:11 PM PDT 24 Aug 10 05:38:17 PM PDT 24 577671524 ps
T344 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3291312089 Aug 10 05:38:03 PM PDT 24 Aug 10 05:38:08 PM PDT 24 499895295 ps
T115 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.703844601 Aug 10 05:38:02 PM PDT 24 Aug 10 05:38:40 PM PDT 24 211677780 ps
T345 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3872200876 Aug 10 05:38:24 PM PDT 24 Aug 10 05:38:52 PM PDT 24 2839917052 ps
T346 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2292747239 Aug 10 05:38:19 PM PDT 24 Aug 10 05:38:59 PM PDT 24 2293172330 ps
T347 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1357947861 Aug 10 05:37:54 PM PDT 24 Aug 10 05:37:59 PM PDT 24 499420409 ps
T348 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2582881831 Aug 10 05:38:27 PM PDT 24 Aug 10 05:38:31 PM PDT 24 90040986 ps
T349 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1952701677 Aug 10 05:38:25 PM PDT 24 Aug 10 05:38:30 PM PDT 24 132474404 ps
T350 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.980229330 Aug 10 05:38:02 PM PDT 24 Aug 10 05:38:07 PM PDT 24 153081846 ps
T79 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1962107113 Aug 10 05:38:05 PM PDT 24 Aug 10 05:38:09 PM PDT 24 85835554 ps
T351 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3792381983 Aug 10 05:38:12 PM PDT 24 Aug 10 05:38:21 PM PDT 24 129872657 ps
T352 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.833683217 Aug 10 05:38:35 PM PDT 24 Aug 10 05:38:39 PM PDT 24 169282171 ps
T80 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1466837840 Aug 10 05:37:55 PM PDT 24 Aug 10 05:38:04 PM PDT 24 135034918 ps
T353 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.226665091 Aug 10 05:38:35 PM PDT 24 Aug 10 05:38:41 PM PDT 24 104126791 ps
T354 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.867277250 Aug 10 05:38:27 PM PDT 24 Aug 10 05:38:36 PM PDT 24 1217109832 ps
T81 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4026040811 Aug 10 05:38:29 PM PDT 24 Aug 10 05:38:57 PM PDT 24 539712026 ps
T82 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.508585961 Aug 10 05:38:04 PM PDT 24 Aug 10 05:38:32 PM PDT 24 565055770 ps
T355 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2781210916 Aug 10 05:38:20 PM PDT 24 Aug 10 05:38:25 PM PDT 24 249279363 ps
T110 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3783715804 Aug 10 05:38:18 PM PDT 24 Aug 10 05:38:55 PM PDT 24 1363076095 ps
T356 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3970495621 Aug 10 05:38:29 PM PDT 24 Aug 10 05:38:35 PM PDT 24 2253797982 ps
T357 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3808377206 Aug 10 05:38:11 PM PDT 24 Aug 10 05:38:16 PM PDT 24 457907879 ps
T358 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.618642813 Aug 10 05:37:55 PM PDT 24 Aug 10 05:38:00 PM PDT 24 362765759 ps
T114 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2691314708 Aug 10 05:38:27 PM PDT 24 Aug 10 05:39:36 PM PDT 24 995484312 ps
T359 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2914001780 Aug 10 05:38:34 PM PDT 24 Aug 10 05:39:06 PM PDT 24 827062872 ps
T360 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.967043673 Aug 10 05:38:19 PM PDT 24 Aug 10 05:38:26 PM PDT 24 127658189 ps
T361 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1700813855 Aug 10 05:38:25 PM PDT 24 Aug 10 05:38:31 PM PDT 24 2640528317 ps
T86 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1632163711 Aug 10 05:38:13 PM PDT 24 Aug 10 05:38:40 PM PDT 24 567395143 ps
T362 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3512321031 Aug 10 05:38:02 PM PDT 24 Aug 10 05:38:08 PM PDT 24 577847755 ps
T363 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.786774633 Aug 10 05:38:10 PM PDT 24 Aug 10 05:38:15 PM PDT 24 127187636 ps
T364 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3384641166 Aug 10 05:38:04 PM PDT 24 Aug 10 05:38:13 PM PDT 24 435203439 ps
T365 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1022084398 Aug 10 05:38:05 PM PDT 24 Aug 10 05:38:09 PM PDT 24 86826795 ps
T87 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1771451646 Aug 10 05:38:02 PM PDT 24 Aug 10 05:38:30 PM PDT 24 2997566723 ps
T366 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.776949297 Aug 10 05:38:04 PM PDT 24 Aug 10 05:38:11 PM PDT 24 578958298 ps
T367 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4098102149 Aug 10 05:38:21 PM PDT 24 Aug 10 05:38:28 PM PDT 24 1953655360 ps
T368 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2400616086 Aug 10 05:38:10 PM PDT 24 Aug 10 05:38:18 PM PDT 24 88948222 ps
T369 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3931534834 Aug 10 05:38:09 PM PDT 24 Aug 10 05:38:14 PM PDT 24 1020550798 ps
T370 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3118263306 Aug 10 05:37:53 PM PDT 24 Aug 10 05:37:58 PM PDT 24 100618707 ps
T371 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2924656992 Aug 10 05:37:53 PM PDT 24 Aug 10 05:37:58 PM PDT 24 251225452 ps
T90 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2151900168 Aug 10 05:37:55 PM PDT 24 Aug 10 05:38:28 PM PDT 24 3422444872 ps
T372 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2487338062 Aug 10 05:38:03 PM PDT 24 Aug 10 05:38:08 PM PDT 24 415666101 ps
T373 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3391873769 Aug 10 05:38:31 PM PDT 24 Aug 10 05:38:53 PM PDT 24 6503131475 ps
T374 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4211912521 Aug 10 05:38:11 PM PDT 24 Aug 10 05:38:49 PM PDT 24 655240508 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3700145247 Aug 10 05:37:53 PM PDT 24 Aug 10 05:37:58 PM PDT 24 86721075 ps
T376 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1806301228 Aug 10 05:38:13 PM PDT 24 Aug 10 05:38:17 PM PDT 24 321651256 ps
T377 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1099261875 Aug 10 05:38:09 PM PDT 24 Aug 10 05:38:13 PM PDT 24 89521375 ps
T378 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.62531404 Aug 10 05:38:04 PM PDT 24 Aug 10 05:38:09 PM PDT 24 1569913730 ps
T379 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.535399504 Aug 10 05:38:02 PM PDT 24 Aug 10 05:38:07 PM PDT 24 89643096 ps
T88 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2899251922 Aug 10 05:37:53 PM PDT 24 Aug 10 05:38:16 PM PDT 24 548055618 ps
T380 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1108579743 Aug 10 05:38:27 PM PDT 24 Aug 10 05:38:32 PM PDT 24 776886565 ps
T381 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.625629930 Aug 10 05:37:54 PM PDT 24 Aug 10 05:38:32 PM PDT 24 449906277 ps
T382 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.496825729 Aug 10 05:38:26 PM PDT 24 Aug 10 05:38:33 PM PDT 24 692334008 ps
T83 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3519269196 Aug 10 05:38:20 PM PDT 24 Aug 10 05:38:38 PM PDT 24 2225625432 ps
T383 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2065122522 Aug 10 05:38:04 PM PDT 24 Aug 10 05:38:12 PM PDT 24 2064120793 ps
T89 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3447874521 Aug 10 05:38:03 PM PDT 24 Aug 10 05:38:11 PM PDT 24 94858226 ps
T384 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3026173904 Aug 10 05:38:13 PM PDT 24 Aug 10 05:38:32 PM PDT 24 782498126 ps
T116 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2882866520 Aug 10 05:38:28 PM PDT 24 Aug 10 05:39:05 PM PDT 24 386105882 ps
T385 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4104546448 Aug 10 05:38:31 PM PDT 24 Aug 10 05:38:35 PM PDT 24 88293785 ps
T386 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1118257888 Aug 10 05:38:02 PM PDT 24 Aug 10 05:38:07 PM PDT 24 1785436414 ps
T387 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1373047037 Aug 10 05:37:54 PM PDT 24 Aug 10 05:37:59 PM PDT 24 953406272 ps
T112 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1536967703 Aug 10 05:38:09 PM PDT 24 Aug 10 05:38:46 PM PDT 24 219241043 ps
T388 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3819833712 Aug 10 05:38:27 PM PDT 24 Aug 10 05:38:36 PM PDT 24 742832476 ps
T389 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1208420948 Aug 10 05:38:05 PM PDT 24 Aug 10 05:38:16 PM PDT 24 285877749 ps
T390 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2221171340 Aug 10 05:38:18 PM PDT 24 Aug 10 05:38:22 PM PDT 24 166304185 ps
T391 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4062884757 Aug 10 05:38:20 PM PDT 24 Aug 10 05:38:48 PM PDT 24 1123695868 ps
T392 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3739511651 Aug 10 05:38:35 PM PDT 24 Aug 10 05:38:44 PM PDT 24 1032991675 ps
T393 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.936026734 Aug 10 05:38:03 PM PDT 24 Aug 10 05:38:09 PM PDT 24 827956138 ps
T394 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1120335204 Aug 10 05:38:03 PM PDT 24 Aug 10 05:38:09 PM PDT 24 571529138 ps
T395 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2138721869 Aug 10 05:38:28 PM PDT 24 Aug 10 05:38:33 PM PDT 24 2066335924 ps
T396 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2329302710 Aug 10 05:38:18 PM PDT 24 Aug 10 05:39:02 PM PDT 24 454235070 ps
T397 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.459185506 Aug 10 05:38:21 PM PDT 24 Aug 10 05:38:27 PM PDT 24 204222135 ps
T84 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3983562769 Aug 10 05:37:52 PM PDT 24 Aug 10 05:37:57 PM PDT 24 89359551 ps
T398 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1627047259 Aug 10 05:38:10 PM PDT 24 Aug 10 05:38:15 PM PDT 24 257220022 ps
T399 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2268293800 Aug 10 05:37:53 PM PDT 24 Aug 10 05:37:58 PM PDT 24 183871457 ps
T400 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2657739709 Aug 10 05:38:29 PM PDT 24 Aug 10 05:39:39 PM PDT 24 382000766 ps
T401 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.607123530 Aug 10 05:37:55 PM PDT 24 Aug 10 05:38:03 PM PDT 24 1129649229 ps
T402 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1824191913 Aug 10 05:38:28 PM PDT 24 Aug 10 05:38:35 PM PDT 24 518461151 ps
T403 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1623608264 Aug 10 05:37:53 PM PDT 24 Aug 10 05:38:02 PM PDT 24 2287798624 ps
T404 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3267415702 Aug 10 05:38:25 PM PDT 24 Aug 10 05:38:30 PM PDT 24 85664894 ps
T405 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1558586285 Aug 10 05:38:10 PM PDT 24 Aug 10 05:38:17 PM PDT 24 141059218 ps
T406 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.290127140 Aug 10 05:37:53 PM PDT 24 Aug 10 05:37:59 PM PDT 24 89685147 ps
T407 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2551954248 Aug 10 05:38:26 PM PDT 24 Aug 10 05:38:33 PM PDT 24 252169862 ps
T408 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2131707867 Aug 10 05:38:30 PM PDT 24 Aug 10 05:39:03 PM PDT 24 791079783 ps
T409 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1767142223 Aug 10 05:37:56 PM PDT 24 Aug 10 05:38:04 PM PDT 24 354032780 ps
T107 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1596298300 Aug 10 05:38:25 PM PDT 24 Aug 10 05:39:34 PM PDT 24 1174798857 ps
T85 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.688979199 Aug 10 05:38:21 PM PDT 24 Aug 10 05:38:52 PM PDT 24 7975834397 ps
T410 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2064327897 Aug 10 05:38:19 PM PDT 24 Aug 10 05:38:25 PM PDT 24 140967054 ps
T411 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1340865153 Aug 10 05:38:05 PM PDT 24 Aug 10 05:38:10 PM PDT 24 131633223 ps
T412 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2648037180 Aug 10 05:38:20 PM PDT 24 Aug 10 05:38:26 PM PDT 24 1095273334 ps
T413 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1712381443 Aug 10 05:38:31 PM PDT 24 Aug 10 05:38:37 PM PDT 24 601875526 ps
T414 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2972559915 Aug 10 05:38:34 PM PDT 24 Aug 10 05:38:39 PM PDT 24 188346895 ps
T415 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.203411049 Aug 10 05:38:34 PM PDT 24 Aug 10 05:38:39 PM PDT 24 95878668 ps
T416 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1257582340 Aug 10 05:37:55 PM PDT 24 Aug 10 05:38:03 PM PDT 24 1030790917 ps
T417 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1229007486 Aug 10 05:38:34 PM PDT 24 Aug 10 05:38:39 PM PDT 24 327084919 ps
T418 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2948787255 Aug 10 05:38:26 PM PDT 24 Aug 10 05:38:31 PM PDT 24 252701712 ps
T419 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1540270207 Aug 10 05:37:56 PM PDT 24 Aug 10 05:38:03 PM PDT 24 334037813 ps
T420 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4266164894 Aug 10 05:37:55 PM PDT 24 Aug 10 05:38:00 PM PDT 24 132310712 ps
T421 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2346654228 Aug 10 05:38:26 PM PDT 24 Aug 10 05:38:33 PM PDT 24 136831108 ps
T108 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3418736184 Aug 10 05:38:12 PM PDT 24 Aug 10 05:39:24 PM PDT 24 676995947 ps
T422 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1982597688 Aug 10 05:38:04 PM PDT 24 Aug 10 05:38:10 PM PDT 24 145506770 ps
T423 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1912224472 Aug 10 05:38:12 PM PDT 24 Aug 10 05:38:20 PM PDT 24 730817111 ps
T424 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3751206425 Aug 10 05:38:26 PM PDT 24 Aug 10 05:39:39 PM PDT 24 786040522 ps
T111 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2982834062 Aug 10 05:38:20 PM PDT 24 Aug 10 05:39:35 PM PDT 24 501665622 ps

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1264093132
Short name T8
Test name
Test status
Simulation time 1776362042 ps
CPU time 21.61 seconds
Started Aug 10 05:37:18 PM PDT 24
Finished Aug 10 05:37:40 PM PDT 24
Peak memory 215128 kb
Host smart-a268eaef-060a-44d6-bb41-17a481b74d0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264093132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1264093132
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2832550222
Short name T12
Test name
Test status
Simulation time 87423816902 ps
CPU time 3067.39 seconds
Started Aug 10 05:37:12 PM PDT 24
Finished Aug 10 06:28:20 PM PDT 24
Peak memory 253092 kb
Host smart-c9c0303b-a050-4e49-b8f7-ff4072fd330c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832550222 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.2832550222
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2717811361
Short name T19
Test name
Test status
Simulation time 15960812009 ps
CPU time 201.17 seconds
Started Aug 10 05:37:12 PM PDT 24
Finished Aug 10 05:40:33 PM PDT 24
Peak memory 238552 kb
Host smart-7816af4c-8355-42d3-84cc-9d8c5d78104b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717811361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2717811361
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.488207265
Short name T54
Test name
Test status
Simulation time 2418225169 ps
CPU time 70.1 seconds
Started Aug 10 05:37:52 PM PDT 24
Finished Aug 10 05:39:02 PM PDT 24
Peak memory 213208 kb
Host smart-742ce181-9cce-46bf-86ed-15bcf71241b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488207265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.488207265
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1318239999
Short name T21
Test name
Test status
Simulation time 1182120273 ps
CPU time 51.57 seconds
Started Aug 10 05:36:28 PM PDT 24
Finished Aug 10 05:37:20 PM PDT 24
Peak memory 236496 kb
Host smart-e19b5d5e-024f-4e3a-a1f4-1527e4bdb14d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318239999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1318239999
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2390556041
Short name T62
Test name
Test status
Simulation time 558861155 ps
CPU time 26.35 seconds
Started Aug 10 05:38:27 PM PDT 24
Finished Aug 10 05:38:54 PM PDT 24
Peak memory 211352 kb
Host smart-8447443f-c4f4-4127-8a6f-32cdea95e887
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390556041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2390556041
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2719947728
Short name T106
Test name
Test status
Simulation time 400980454 ps
CPU time 73.42 seconds
Started Aug 10 05:38:36 PM PDT 24
Finished Aug 10 05:39:50 PM PDT 24
Peak memory 213924 kb
Host smart-174cad19-b969-4aaf-a51b-d3d94c9a85bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719947728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2719947728
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.298294135
Short name T117
Test name
Test status
Simulation time 3908938181 ps
CPU time 16.28 seconds
Started Aug 10 05:37:45 PM PDT 24
Finished Aug 10 05:38:01 PM PDT 24
Peak memory 212920 kb
Host smart-fb1826b8-d59f-4553-82ee-0dc71c124367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298294135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.298294135
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3110531857
Short name T1
Test name
Test status
Simulation time 169267172 ps
CPU time 4.28 seconds
Started Aug 10 05:37:15 PM PDT 24
Finished Aug 10 05:37:20 PM PDT 24
Peak memory 211908 kb
Host smart-c2617d5c-9b70-4962-9a4f-4bee27607961
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110531857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3110531857
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2630032802
Short name T48
Test name
Test status
Simulation time 11427745245 ps
CPU time 4488.95 seconds
Started Aug 10 05:37:46 PM PDT 24
Finished Aug 10 06:52:35 PM PDT 24
Peak memory 228480 kb
Host smart-6d848e30-46bf-4015-9722-2cae396b9b0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630032802 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2630032802
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1067244517
Short name T122
Test name
Test status
Simulation time 173335432 ps
CPU time 9.75 seconds
Started Aug 10 05:36:27 PM PDT 24
Finished Aug 10 05:36:36 PM PDT 24
Peak memory 212532 kb
Host smart-947c2941-eb0c-4f9b-97c9-0116dc2c2429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067244517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1067244517
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2982834062
Short name T111
Test name
Test status
Simulation time 501665622 ps
CPU time 74.87 seconds
Started Aug 10 05:38:20 PM PDT 24
Finished Aug 10 05:39:35 PM PDT 24
Peak memory 214176 kb
Host smart-59403ad9-8227-43e0-a1f1-cfc336aa16ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982834062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2982834062
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4254759582
Short name T65
Test name
Test status
Simulation time 7709540103 ps
CPU time 27.84 seconds
Started Aug 10 05:38:26 PM PDT 24
Finished Aug 10 05:38:54 PM PDT 24
Peak memory 211440 kb
Host smart-3a7a05d8-66af-4490-ac92-052c8edfb6ec
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254759582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.4254759582
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2691314708
Short name T114
Test name
Test status
Simulation time 995484312 ps
CPU time 69.17 seconds
Started Aug 10 05:38:27 PM PDT 24
Finished Aug 10 05:39:36 PM PDT 24
Peak memory 219460 kb
Host smart-b5147e70-585a-412d-80b1-523c817da850
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691314708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2691314708
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1280954247
Short name T31
Test name
Test status
Simulation time 204852190 ps
CPU time 12.39 seconds
Started Aug 10 05:37:02 PM PDT 24
Finished Aug 10 05:37:15 PM PDT 24
Peak memory 214684 kb
Host smart-3d198aef-26fe-4543-8948-2b008603948e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280954247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1280954247
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1893730830
Short name T96
Test name
Test status
Simulation time 550512272 ps
CPU time 7.02 seconds
Started Aug 10 05:36:59 PM PDT 24
Finished Aug 10 05:37:06 PM PDT 24
Peak memory 212180 kb
Host smart-0cec7bce-f687-487e-830e-1c7c49319dc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1893730830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1893730830
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3080970040
Short name T16
Test name
Test status
Simulation time 57387517135 ps
CPU time 2180.87 seconds
Started Aug 10 05:37:46 PM PDT 24
Finished Aug 10 06:14:07 PM PDT 24
Peak memory 237056 kb
Host smart-8b1405ca-f86f-4e78-9e9a-5b6fdc671421
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080970040 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.3080970040
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3228958795
Short name T235
Test name
Test status
Simulation time 7458984710 ps
CPU time 236.41 seconds
Started Aug 10 05:36:27 PM PDT 24
Finished Aug 10 05:40:24 PM PDT 24
Peak memory 219336 kb
Host smart-680d0b52-aa38-4fac-a474-68b073818bf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228958795 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.3228958795
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3983562769
Short name T84
Test name
Test status
Simulation time 89359551 ps
CPU time 4.21 seconds
Started Aug 10 05:37:52 PM PDT 24
Finished Aug 10 05:37:57 PM PDT 24
Peak memory 211324 kb
Host smart-067d48e2-0d31-42d0-b5b5-58e375aa69aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983562769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3983562769
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.618642813
Short name T358
Test name
Test status
Simulation time 362765759 ps
CPU time 4.38 seconds
Started Aug 10 05:37:55 PM PDT 24
Finished Aug 10 05:38:00 PM PDT 24
Peak memory 217980 kb
Host smart-3f8df2b3-e3c8-43a9-a1d4-369fa0305c78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618642813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.618642813
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1767142223
Short name T409
Test name
Test status
Simulation time 354032780 ps
CPU time 7.41 seconds
Started Aug 10 05:37:56 PM PDT 24
Finished Aug 10 05:38:04 PM PDT 24
Peak memory 211284 kb
Host smart-2ef124c5-2e72-4632-8b3f-fde7754c262d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767142223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1767142223
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3118263306
Short name T370
Test name
Test status
Simulation time 100618707 ps
CPU time 4.75 seconds
Started Aug 10 05:37:53 PM PDT 24
Finished Aug 10 05:37:58 PM PDT 24
Peak memory 219588 kb
Host smart-118e56c6-c7b3-4724-bea3-8a29d03b04cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118263306 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3118263306
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3572033757
Short name T58
Test name
Test status
Simulation time 129758225 ps
CPU time 5.02 seconds
Started Aug 10 05:37:53 PM PDT 24
Finished Aug 10 05:37:58 PM PDT 24
Peak memory 211308 kb
Host smart-b6a559fc-7fd3-4872-98f4-3a7317150ae2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572033757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3572033757
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1373047037
Short name T387
Test name
Test status
Simulation time 953406272 ps
CPU time 5.01 seconds
Started Aug 10 05:37:54 PM PDT 24
Finished Aug 10 05:37:59 PM PDT 24
Peak memory 211208 kb
Host smart-df7212a1-b5e6-4fd0-b9a9-3e1a0ddfb055
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373047037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1373047037
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2924656992
Short name T371
Test name
Test status
Simulation time 251225452 ps
CPU time 4.88 seconds
Started Aug 10 05:37:53 PM PDT 24
Finished Aug 10 05:37:58 PM PDT 24
Peak memory 211204 kb
Host smart-963715e7-c507-43c9-b7ef-a3a4135a1c29
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924656992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2924656992
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2151900168
Short name T90
Test name
Test status
Simulation time 3422444872 ps
CPU time 33.07 seconds
Started Aug 10 05:37:55 PM PDT 24
Finished Aug 10 05:38:28 PM PDT 24
Peak memory 211496 kb
Host smart-2e78b311-9ca1-4694-9f45-f2e73bc5967c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151900168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2151900168
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1623608264
Short name T403
Test name
Test status
Simulation time 2287798624 ps
CPU time 9.19 seconds
Started Aug 10 05:37:53 PM PDT 24
Finished Aug 10 05:38:02 PM PDT 24
Peak memory 211596 kb
Host smart-089d26d0-f9ed-4ee8-9bc5-4cfc9d84a599
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623608264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1623608264
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.607123530
Short name T401
Test name
Test status
Simulation time 1129649229 ps
CPU time 7.95 seconds
Started Aug 10 05:37:55 PM PDT 24
Finished Aug 10 05:38:03 PM PDT 24
Peak memory 219552 kb
Host smart-a6fdec98-30f5-4619-8b3b-8ecb25019425
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607123530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.607123530
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.590768037
Short name T78
Test name
Test status
Simulation time 569958289 ps
CPU time 5 seconds
Started Aug 10 05:37:55 PM PDT 24
Finished Aug 10 05:38:00 PM PDT 24
Peak memory 211300 kb
Host smart-0083166d-4f80-44cf-8e3a-8fbb000f4730
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590768037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.590768037
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1257582340
Short name T416
Test name
Test status
Simulation time 1030790917 ps
CPU time 7.49 seconds
Started Aug 10 05:37:55 PM PDT 24
Finished Aug 10 05:38:03 PM PDT 24
Peak memory 211252 kb
Host smart-543e718d-afe1-42db-9236-7721cbdfc991
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257582340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1257582340
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1466837840
Short name T80
Test name
Test status
Simulation time 135034918 ps
CPU time 8.28 seconds
Started Aug 10 05:37:55 PM PDT 24
Finished Aug 10 05:38:04 PM PDT 24
Peak memory 211268 kb
Host smart-8b1494df-373b-4db8-90f6-a2931930acea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466837840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1466837840
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2268293800
Short name T399
Test name
Test status
Simulation time 183871457 ps
CPU time 4.88 seconds
Started Aug 10 05:37:53 PM PDT 24
Finished Aug 10 05:37:58 PM PDT 24
Peak memory 215876 kb
Host smart-cdcb918e-8886-4c20-8f2d-1e4d8c432af2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268293800 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2268293800
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4266164894
Short name T420
Test name
Test status
Simulation time 132310712 ps
CPU time 5.18 seconds
Started Aug 10 05:37:55 PM PDT 24
Finished Aug 10 05:38:00 PM PDT 24
Peak memory 211252 kb
Host smart-84bb2929-677c-464a-883e-70551e19fe7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266164894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4266164894
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2948063213
Short name T328
Test name
Test status
Simulation time 129265603 ps
CPU time 5.12 seconds
Started Aug 10 05:37:53 PM PDT 24
Finished Aug 10 05:37:58 PM PDT 24
Peak memory 211100 kb
Host smart-9a8c1298-83d5-48b5-9d41-992ec4491d40
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948063213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2948063213
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1357947861
Short name T347
Test name
Test status
Simulation time 499420409 ps
CPU time 5.02 seconds
Started Aug 10 05:37:54 PM PDT 24
Finished Aug 10 05:37:59 PM PDT 24
Peak memory 211224 kb
Host smart-b62c99e2-7ad9-40d2-87da-b2869d558e03
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357947861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1357947861
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2274134068
Short name T76
Test name
Test status
Simulation time 1102409396 ps
CPU time 27.02 seconds
Started Aug 10 05:37:54 PM PDT 24
Finished Aug 10 05:38:21 PM PDT 24
Peak memory 211376 kb
Host smart-88444d6d-d3ca-4ad0-80cb-1fd4e799a348
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274134068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2274134068
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3700145247
Short name T375
Test name
Test status
Simulation time 86721075 ps
CPU time 4.32 seconds
Started Aug 10 05:37:53 PM PDT 24
Finished Aug 10 05:37:58 PM PDT 24
Peak memory 219548 kb
Host smart-961dcca1-f96f-4f9b-9547-ce73437689eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700145247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3700145247
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1540270207
Short name T419
Test name
Test status
Simulation time 334037813 ps
CPU time 6.78 seconds
Started Aug 10 05:37:56 PM PDT 24
Finished Aug 10 05:38:03 PM PDT 24
Peak memory 219632 kb
Host smart-1f292288-778c-4607-958c-e179d40b8d0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540270207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1540270207
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.625629930
Short name T381
Test name
Test status
Simulation time 449906277 ps
CPU time 37.82 seconds
Started Aug 10 05:37:54 PM PDT 24
Finished Aug 10 05:38:32 PM PDT 24
Peak memory 211980 kb
Host smart-9cf38e43-66fb-4827-b949-10f8f956e852
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625629930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.625629930
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2890663258
Short name T337
Test name
Test status
Simulation time 145587566 ps
CPU time 5.71 seconds
Started Aug 10 05:38:18 PM PDT 24
Finished Aug 10 05:38:24 PM PDT 24
Peak memory 214344 kb
Host smart-4b6722df-b1a7-49fe-bbbe-507b6c8a29ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890663258 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2890663258
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2221171340
Short name T390
Test name
Test status
Simulation time 166304185 ps
CPU time 4.19 seconds
Started Aug 10 05:38:18 PM PDT 24
Finished Aug 10 05:38:22 PM PDT 24
Peak memory 211296 kb
Host smart-ac17bdd5-a71a-4717-b465-96911b320871
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221171340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2221171340
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4062884757
Short name T391
Test name
Test status
Simulation time 1123695868 ps
CPU time 27.69 seconds
Started Aug 10 05:38:20 PM PDT 24
Finished Aug 10 05:38:48 PM PDT 24
Peak memory 211288 kb
Host smart-77cc8589-81b3-4df1-9bfa-13d4ff362a9b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062884757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.4062884757
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.627892327
Short name T63
Test name
Test status
Simulation time 554957969 ps
CPU time 6.96 seconds
Started Aug 10 05:38:20 PM PDT 24
Finished Aug 10 05:38:27 PM PDT 24
Peak memory 219400 kb
Host smart-f846cca1-f596-43cb-a473-0a89295fbeb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627892327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.627892327
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.967043673
Short name T360
Test name
Test status
Simulation time 127658189 ps
CPU time 7.33 seconds
Started Aug 10 05:38:19 PM PDT 24
Finished Aug 10 05:38:26 PM PDT 24
Peak memory 219644 kb
Host smart-10c9a910-1515-40c7-bb5d-19bbf019e606
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967043673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.967043673
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3783715804
Short name T110
Test name
Test status
Simulation time 1363076095 ps
CPU time 37.24 seconds
Started Aug 10 05:38:18 PM PDT 24
Finished Aug 10 05:38:55 PM PDT 24
Peak memory 213652 kb
Host smart-5ec39fd1-d41c-4d74-b5dd-84a83486a2f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783715804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3783715804
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2648037180
Short name T412
Test name
Test status
Simulation time 1095273334 ps
CPU time 5.71 seconds
Started Aug 10 05:38:20 PM PDT 24
Finished Aug 10 05:38:26 PM PDT 24
Peak memory 215272 kb
Host smart-72de5a4e-8eb2-484b-bac1-c518cedfc7be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648037180 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2648037180
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4098102149
Short name T367
Test name
Test status
Simulation time 1953655360 ps
CPU time 7.62 seconds
Started Aug 10 05:38:21 PM PDT 24
Finished Aug 10 05:38:28 PM PDT 24
Peak memory 211300 kb
Host smart-8fa95fd0-f4b5-4bdd-883d-9868a8029ca6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098102149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.4098102149
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.223810276
Short name T341
Test name
Test status
Simulation time 1097407083 ps
CPU time 21.65 seconds
Started Aug 10 05:38:18 PM PDT 24
Finished Aug 10 05:38:40 PM PDT 24
Peak memory 211412 kb
Host smart-f269e0da-0cdf-45ea-9664-af3774751793
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223810276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.223810276
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4026756737
Short name T91
Test name
Test status
Simulation time 192187256 ps
CPU time 4.38 seconds
Started Aug 10 05:38:19 PM PDT 24
Finished Aug 10 05:38:24 PM PDT 24
Peak memory 219500 kb
Host smart-c7dd8fd3-0b45-46c7-812d-1554827fb6cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026756737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.4026756737
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.459185506
Short name T397
Test name
Test status
Simulation time 204222135 ps
CPU time 6.44 seconds
Started Aug 10 05:38:21 PM PDT 24
Finished Aug 10 05:38:27 PM PDT 24
Peak memory 216488 kb
Host smart-2f7e4e66-a723-4217-8d00-fd85414ed47f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459185506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.459185506
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1768849258
Short name T342
Test name
Test status
Simulation time 530274856 ps
CPU time 5.51 seconds
Started Aug 10 05:38:17 PM PDT 24
Finished Aug 10 05:38:22 PM PDT 24
Peak memory 219560 kb
Host smart-e3b1a067-fe5e-4a7e-a841-327bb0c3f8bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768849258 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1768849258
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1872789008
Short name T64
Test name
Test status
Simulation time 287237776 ps
CPU time 4.19 seconds
Started Aug 10 05:38:20 PM PDT 24
Finished Aug 10 05:38:24 PM PDT 24
Peak memory 211208 kb
Host smart-a5231096-59a0-482f-b6c7-907fa16a78c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872789008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1872789008
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3519269196
Short name T83
Test name
Test status
Simulation time 2225625432 ps
CPU time 18.52 seconds
Started Aug 10 05:38:20 PM PDT 24
Finished Aug 10 05:38:38 PM PDT 24
Peak memory 211496 kb
Host smart-618c4a6b-3fce-46b7-82fc-162c4d3e2344
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519269196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3519269196
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3025171604
Short name T68
Test name
Test status
Simulation time 132847509 ps
CPU time 5.24 seconds
Started Aug 10 05:38:18 PM PDT 24
Finished Aug 10 05:38:23 PM PDT 24
Peak memory 211388 kb
Host smart-926a7535-6744-4b0b-b322-30e6dca99a44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025171604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3025171604
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.858108673
Short name T338
Test name
Test status
Simulation time 131631932 ps
CPU time 7.59 seconds
Started Aug 10 05:38:19 PM PDT 24
Finished Aug 10 05:38:26 PM PDT 24
Peak memory 216324 kb
Host smart-2f0396d6-13fd-47d9-80ab-a010ea96e646
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858108673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.858108673
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2292747239
Short name T346
Test name
Test status
Simulation time 2293172330 ps
CPU time 39.27 seconds
Started Aug 10 05:38:19 PM PDT 24
Finished Aug 10 05:38:59 PM PDT 24
Peak memory 219540 kb
Host smart-37a44581-8235-4fc6-bc7c-ffea015d149d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292747239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2292747239
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3969897392
Short name T332
Test name
Test status
Simulation time 551666578 ps
CPU time 5.48 seconds
Started Aug 10 05:38:26 PM PDT 24
Finished Aug 10 05:38:32 PM PDT 24
Peak memory 214768 kb
Host smart-e13502d5-1986-49d3-9ff7-980e04fea9f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969897392 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3969897392
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.540273230
Short name T334
Test name
Test status
Simulation time 266356936 ps
CPU time 5.13 seconds
Started Aug 10 05:38:27 PM PDT 24
Finished Aug 10 05:38:32 PM PDT 24
Peak memory 211292 kb
Host smart-a8315cbf-2913-4cd0-88f2-f28d541c14d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540273230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.540273230
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1108579743
Short name T380
Test name
Test status
Simulation time 776886565 ps
CPU time 5.05 seconds
Started Aug 10 05:38:27 PM PDT 24
Finished Aug 10 05:38:32 PM PDT 24
Peak memory 211388 kb
Host smart-7ccf51ce-89c9-4df3-8abf-71f3cdaf224e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108579743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1108579743
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3097357335
Short name T336
Test name
Test status
Simulation time 162818863 ps
CPU time 8.32 seconds
Started Aug 10 05:38:28 PM PDT 24
Finished Aug 10 05:38:36 PM PDT 24
Peak memory 219576 kb
Host smart-2dcd9275-a568-4888-a149-1aaeae94e413
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097357335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3097357335
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1596298300
Short name T107
Test name
Test status
Simulation time 1174798857 ps
CPU time 69.42 seconds
Started Aug 10 05:38:25 PM PDT 24
Finished Aug 10 05:39:34 PM PDT 24
Peak memory 213068 kb
Host smart-32975b6e-c9ac-4cd1-a49c-df373381f655
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596298300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1596298300
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3970495621
Short name T356
Test name
Test status
Simulation time 2253797982 ps
CPU time 5.66 seconds
Started Aug 10 05:38:29 PM PDT 24
Finished Aug 10 05:38:35 PM PDT 24
Peak memory 215480 kb
Host smart-82943509-0258-4ae6-b233-7f23e8a9f26d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970495621 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3970495621
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2138721869
Short name T395
Test name
Test status
Simulation time 2066335924 ps
CPU time 5.09 seconds
Started Aug 10 05:38:28 PM PDT 24
Finished Aug 10 05:38:33 PM PDT 24
Peak memory 218436 kb
Host smart-e4787755-0737-4ff1-984a-f1f8e94f6a2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138721869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2138721869
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3872200876
Short name T345
Test name
Test status
Simulation time 2839917052 ps
CPU time 28.16 seconds
Started Aug 10 05:38:24 PM PDT 24
Finished Aug 10 05:38:52 PM PDT 24
Peak memory 211440 kb
Host smart-7ff1c623-42b6-46a5-95ef-457fd2745af0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872200876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3872200876
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2178766076
Short name T61
Test name
Test status
Simulation time 623831702 ps
CPU time 5.13 seconds
Started Aug 10 05:38:30 PM PDT 24
Finished Aug 10 05:38:35 PM PDT 24
Peak memory 210896 kb
Host smart-cbb930f0-dca8-4d80-9ae6-29266f8f0d4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178766076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2178766076
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1824191913
Short name T402
Test name
Test status
Simulation time 518461151 ps
CPU time 7.06 seconds
Started Aug 10 05:38:28 PM PDT 24
Finished Aug 10 05:38:35 PM PDT 24
Peak memory 219612 kb
Host smart-952f5429-5bf4-4997-9123-c3293fc4348c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824191913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1824191913
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2882866520
Short name T116
Test name
Test status
Simulation time 386105882 ps
CPU time 36.86 seconds
Started Aug 10 05:38:28 PM PDT 24
Finished Aug 10 05:39:05 PM PDT 24
Peak memory 219496 kb
Host smart-d1c65931-ccef-468d-8e42-2c8fe214b9b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882866520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2882866520
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.175448118
Short name T329
Test name
Test status
Simulation time 313118920 ps
CPU time 5.39 seconds
Started Aug 10 05:38:30 PM PDT 24
Finished Aug 10 05:38:36 PM PDT 24
Peak memory 219560 kb
Host smart-eabf74ed-99e0-46a2-8b56-59dbe50ada99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175448118 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.175448118
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2948787255
Short name T418
Test name
Test status
Simulation time 252701712 ps
CPU time 4.97 seconds
Started Aug 10 05:38:26 PM PDT 24
Finished Aug 10 05:38:31 PM PDT 24
Peak memory 211220 kb
Host smart-fb60b018-9f81-43c6-a505-9d9af5b2cfbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948787255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2948787255
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2346654228
Short name T421
Test name
Test status
Simulation time 136831108 ps
CPU time 6.97 seconds
Started Aug 10 05:38:26 PM PDT 24
Finished Aug 10 05:38:33 PM PDT 24
Peak memory 211324 kb
Host smart-ed79a126-8cbe-4017-aa9b-5313f3006261
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346654228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2346654228
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3819833712
Short name T388
Test name
Test status
Simulation time 742832476 ps
CPU time 8.9 seconds
Started Aug 10 05:38:27 PM PDT 24
Finished Aug 10 05:38:36 PM PDT 24
Peak memory 215556 kb
Host smart-00bab42b-0e8c-4627-96ee-f9f19b52b3ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819833712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3819833712
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3751206425
Short name T424
Test name
Test status
Simulation time 786040522 ps
CPU time 72.8 seconds
Started Aug 10 05:38:26 PM PDT 24
Finished Aug 10 05:39:39 PM PDT 24
Peak memory 213028 kb
Host smart-79996b56-cf1a-4722-ae23-af92d42ef6bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751206425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3751206425
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1700813855
Short name T361
Test name
Test status
Simulation time 2640528317 ps
CPU time 5.78 seconds
Started Aug 10 05:38:25 PM PDT 24
Finished Aug 10 05:38:31 PM PDT 24
Peak memory 219624 kb
Host smart-eac7b1e0-a11c-490f-9470-3a8bafb29a06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700813855 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1700813855
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4104546448
Short name T385
Test name
Test status
Simulation time 88293785 ps
CPU time 4.23 seconds
Started Aug 10 05:38:31 PM PDT 24
Finished Aug 10 05:38:35 PM PDT 24
Peak memory 217988 kb
Host smart-c432a35a-0a81-4d32-8a03-0d452bfac1d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104546448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4104546448
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3391873769
Short name T373
Test name
Test status
Simulation time 6503131475 ps
CPU time 22.07 seconds
Started Aug 10 05:38:31 PM PDT 24
Finished Aug 10 05:38:53 PM PDT 24
Peak memory 212480 kb
Host smart-1d0b8fa3-75fd-496b-b4a8-421b4f32156c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391873769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3391873769
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3267415702
Short name T404
Test name
Test status
Simulation time 85664894 ps
CPU time 4.39 seconds
Started Aug 10 05:38:25 PM PDT 24
Finished Aug 10 05:38:30 PM PDT 24
Peak memory 211368 kb
Host smart-6b74d458-1643-4061-91a7-5337863a5031
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267415702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3267415702
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2551954248
Short name T407
Test name
Test status
Simulation time 252169862 ps
CPU time 7.12 seconds
Started Aug 10 05:38:26 PM PDT 24
Finished Aug 10 05:38:33 PM PDT 24
Peak memory 216288 kb
Host smart-0d26ddc3-b3de-4ceb-8cd8-870608609452
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551954248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2551954248
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1712381443
Short name T413
Test name
Test status
Simulation time 601875526 ps
CPU time 5.81 seconds
Started Aug 10 05:38:31 PM PDT 24
Finished Aug 10 05:38:37 PM PDT 24
Peak memory 219584 kb
Host smart-52eeda28-d201-4982-9a8f-099bad6c7880
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712381443 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1712381443
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1952701677
Short name T349
Test name
Test status
Simulation time 132474404 ps
CPU time 4.98 seconds
Started Aug 10 05:38:25 PM PDT 24
Finished Aug 10 05:38:30 PM PDT 24
Peak memory 211252 kb
Host smart-25139690-9daa-4f85-934d-ec06195038be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952701677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1952701677
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4026040811
Short name T81
Test name
Test status
Simulation time 539712026 ps
CPU time 27.13 seconds
Started Aug 10 05:38:29 PM PDT 24
Finished Aug 10 05:38:57 PM PDT 24
Peak memory 211408 kb
Host smart-22f6d6e1-6833-47ae-8af6-e2150d945d1e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026040811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4026040811
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2582881831
Short name T348
Test name
Test status
Simulation time 90040986 ps
CPU time 4.28 seconds
Started Aug 10 05:38:27 PM PDT 24
Finished Aug 10 05:38:31 PM PDT 24
Peak memory 211520 kb
Host smart-eced88ae-bc9b-4f2e-b6a8-8efc01bb58a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582881831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2582881831
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.867277250
Short name T354
Test name
Test status
Simulation time 1217109832 ps
CPU time 9.26 seconds
Started Aug 10 05:38:27 PM PDT 24
Finished Aug 10 05:38:36 PM PDT 24
Peak memory 219648 kb
Host smart-b4fe349d-2a97-44a9-9f2b-ebf6ca56421c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867277250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.867277250
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2657739709
Short name T400
Test name
Test status
Simulation time 382000766 ps
CPU time 69.95 seconds
Started Aug 10 05:38:29 PM PDT 24
Finished Aug 10 05:39:39 PM PDT 24
Peak memory 213028 kb
Host smart-e528ba69-3f31-4812-a90d-90c68f9d279e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657739709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2657739709
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.226665091
Short name T353
Test name
Test status
Simulation time 104126791 ps
CPU time 5.37 seconds
Started Aug 10 05:38:35 PM PDT 24
Finished Aug 10 05:38:41 PM PDT 24
Peak memory 216008 kb
Host smart-f17dff7c-fa38-4a32-b02e-d581bab9b01b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226665091 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.226665091
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.833683217
Short name T352
Test name
Test status
Simulation time 169282171 ps
CPU time 4.18 seconds
Started Aug 10 05:38:35 PM PDT 24
Finished Aug 10 05:38:39 PM PDT 24
Peak memory 211316 kb
Host smart-b2467cd5-ba4c-43e6-8a6a-d57db856cded
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833683217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.833683217
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2131707867
Short name T408
Test name
Test status
Simulation time 791079783 ps
CPU time 32.83 seconds
Started Aug 10 05:38:30 PM PDT 24
Finished Aug 10 05:39:03 PM PDT 24
Peak memory 210888 kb
Host smart-9fd025d2-7533-48e6-8b89-08083f4a6d3e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131707867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2131707867
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2972559915
Short name T414
Test name
Test status
Simulation time 188346895 ps
CPU time 5.18 seconds
Started Aug 10 05:38:34 PM PDT 24
Finished Aug 10 05:38:39 PM PDT 24
Peak memory 211388 kb
Host smart-1fe6c6da-06b5-47f5-bcee-b7726dfd9199
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972559915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2972559915
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.496825729
Short name T382
Test name
Test status
Simulation time 692334008 ps
CPU time 6.88 seconds
Started Aug 10 05:38:26 PM PDT 24
Finished Aug 10 05:38:33 PM PDT 24
Peak memory 219664 kb
Host smart-3d0fc154-abd2-4913-add9-8fbfdd94f8ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496825729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.496825729
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.203411049
Short name T415
Test name
Test status
Simulation time 95878668 ps
CPU time 5.25 seconds
Started Aug 10 05:38:34 PM PDT 24
Finished Aug 10 05:38:39 PM PDT 24
Peak memory 219608 kb
Host smart-8dd26e14-c6cc-4ecd-b807-fa0e79e8b4ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203411049 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.203411049
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3265566406
Short name T66
Test name
Test status
Simulation time 345611118 ps
CPU time 5.02 seconds
Started Aug 10 05:38:36 PM PDT 24
Finished Aug 10 05:38:41 PM PDT 24
Peak memory 211300 kb
Host smart-684d279d-2e3e-4296-bdd1-93de4725ba05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265566406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3265566406
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2914001780
Short name T359
Test name
Test status
Simulation time 827062872 ps
CPU time 32.08 seconds
Started Aug 10 05:38:34 PM PDT 24
Finished Aug 10 05:39:06 PM PDT 24
Peak memory 211400 kb
Host smart-e31ef3bf-bfce-4b0c-b1db-d29d02c618d9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914001780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2914001780
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1229007486
Short name T417
Test name
Test status
Simulation time 327084919 ps
CPU time 5.07 seconds
Started Aug 10 05:38:34 PM PDT 24
Finished Aug 10 05:38:39 PM PDT 24
Peak memory 211384 kb
Host smart-b368a96b-06ab-4435-8b62-c357f1812c62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229007486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1229007486
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3739511651
Short name T392
Test name
Test status
Simulation time 1032991675 ps
CPU time 8.23 seconds
Started Aug 10 05:38:35 PM PDT 24
Finished Aug 10 05:38:44 PM PDT 24
Peak memory 219608 kb
Host smart-6635b87e-6425-4137-9734-4fcbcfea4cad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739511651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3739511651
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3837197724
Short name T113
Test name
Test status
Simulation time 1619889289 ps
CPU time 69.78 seconds
Started Aug 10 05:38:36 PM PDT 24
Finished Aug 10 05:39:46 PM PDT 24
Peak memory 213264 kb
Host smart-ec6c54ed-c221-4f66-afd8-e418b6cb68fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837197724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3837197724
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.454262502
Short name T67
Test name
Test status
Simulation time 127838669 ps
CPU time 5.07 seconds
Started Aug 10 05:38:03 PM PDT 24
Finished Aug 10 05:38:08 PM PDT 24
Peak memory 211324 kb
Host smart-37312afd-62d9-48f9-a809-84a74a65a6c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454262502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.454262502
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2487338062
Short name T372
Test name
Test status
Simulation time 415666101 ps
CPU time 4.57 seconds
Started Aug 10 05:38:03 PM PDT 24
Finished Aug 10 05:38:08 PM PDT 24
Peak memory 211236 kb
Host smart-7426bda4-2f71-4bbb-942d-d70f1af38202
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487338062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2487338062
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.776949297
Short name T366
Test name
Test status
Simulation time 578958298 ps
CPU time 6.92 seconds
Started Aug 10 05:38:04 PM PDT 24
Finished Aug 10 05:38:11 PM PDT 24
Peak memory 211324 kb
Host smart-e76e93f9-e92e-4cb4-8af2-e540a393bf1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776949297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.776949297
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3512321031
Short name T362
Test name
Test status
Simulation time 577847755 ps
CPU time 6.04 seconds
Started Aug 10 05:38:02 PM PDT 24
Finished Aug 10 05:38:08 PM PDT 24
Peak memory 215972 kb
Host smart-c44cea7b-8111-4b64-9cd7-e2ced08dcbc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512321031 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3512321031
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2952072324
Short name T93
Test name
Test status
Simulation time 250875976 ps
CPU time 5.11 seconds
Started Aug 10 05:38:03 PM PDT 24
Finished Aug 10 05:38:08 PM PDT 24
Peak memory 211360 kb
Host smart-b1aea56f-09d2-4338-a5be-9de83fb2472c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952072324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2952072324
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.62531404
Short name T378
Test name
Test status
Simulation time 1569913730 ps
CPU time 4.95 seconds
Started Aug 10 05:38:04 PM PDT 24
Finished Aug 10 05:38:09 PM PDT 24
Peak memory 211216 kb
Host smart-ea23acd6-f775-449e-a3c0-148cce83b1e7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62531404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_
mem_partial_access.62531404
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.203739944
Short name T335
Test name
Test status
Simulation time 130695037 ps
CPU time 4.93 seconds
Started Aug 10 05:38:02 PM PDT 24
Finished Aug 10 05:38:07 PM PDT 24
Peak memory 211172 kb
Host smart-adc50dce-b178-41a9-abb4-f4c6001a7194
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203739944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
203739944
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2899251922
Short name T88
Test name
Test status
Simulation time 548055618 ps
CPU time 22.58 seconds
Started Aug 10 05:37:53 PM PDT 24
Finished Aug 10 05:38:16 PM PDT 24
Peak memory 211380 kb
Host smart-dd207d6e-3d97-4cde-8452-0c71b85da71d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899251922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2899251922
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3291312089
Short name T344
Test name
Test status
Simulation time 499895295 ps
CPU time 5.05 seconds
Started Aug 10 05:38:03 PM PDT 24
Finished Aug 10 05:38:08 PM PDT 24
Peak memory 218572 kb
Host smart-5c863269-c869-480f-ba25-5f27a3c55953
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291312089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3291312089
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.290127140
Short name T406
Test name
Test status
Simulation time 89685147 ps
CPU time 6.39 seconds
Started Aug 10 05:37:53 PM PDT 24
Finished Aug 10 05:37:59 PM PDT 24
Peak memory 216284 kb
Host smart-b785c11c-f114-46da-a4ac-ece9699a6cb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290127140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.290127140
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1475277848
Short name T55
Test name
Test status
Simulation time 1158285951 ps
CPU time 70.14 seconds
Started Aug 10 05:38:03 PM PDT 24
Finished Aug 10 05:39:13 PM PDT 24
Peak memory 219516 kb
Host smart-3b3db88e-1ba2-4c3a-a8dd-d2b8244509f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475277848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1475277848
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1962107113
Short name T79
Test name
Test status
Simulation time 85835554 ps
CPU time 4.24 seconds
Started Aug 10 05:38:05 PM PDT 24
Finished Aug 10 05:38:09 PM PDT 24
Peak memory 218164 kb
Host smart-f7572e2f-cb8e-4418-b0c0-d932c2d5e9a2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962107113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1962107113
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2065122522
Short name T383
Test name
Test status
Simulation time 2064120793 ps
CPU time 7.79 seconds
Started Aug 10 05:38:04 PM PDT 24
Finished Aug 10 05:38:12 PM PDT 24
Peak memory 218028 kb
Host smart-6178ee3f-d661-4d9e-8bf1-db9357accc8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065122522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2065122522
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4260993074
Short name T330
Test name
Test status
Simulation time 134038970 ps
CPU time 8 seconds
Started Aug 10 05:38:02 PM PDT 24
Finished Aug 10 05:38:10 PM PDT 24
Peak memory 211324 kb
Host smart-5d1bec1c-3b6d-40cc-8518-706fc6b02fc9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260993074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.4260993074
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1120335204
Short name T394
Test name
Test status
Simulation time 571529138 ps
CPU time 6.23 seconds
Started Aug 10 05:38:03 PM PDT 24
Finished Aug 10 05:38:09 PM PDT 24
Peak memory 219548 kb
Host smart-672ce04b-3a2e-424d-9f51-c5bb1b0cdc9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120335204 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1120335204
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3025620901
Short name T97
Test name
Test status
Simulation time 126803757 ps
CPU time 5.19 seconds
Started Aug 10 05:38:04 PM PDT 24
Finished Aug 10 05:38:09 PM PDT 24
Peak memory 218048 kb
Host smart-1ed5e2c8-e27f-4e6b-91b3-c9cab74a18c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025620901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3025620901
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4114778315
Short name T331
Test name
Test status
Simulation time 173003719 ps
CPU time 4.13 seconds
Started Aug 10 05:38:05 PM PDT 24
Finished Aug 10 05:38:09 PM PDT 24
Peak memory 211216 kb
Host smart-320a1f28-61ca-42bc-9c74-cec438c821fc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114778315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.4114778315
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2130524853
Short name T333
Test name
Test status
Simulation time 86398403 ps
CPU time 4.14 seconds
Started Aug 10 05:38:04 PM PDT 24
Finished Aug 10 05:38:09 PM PDT 24
Peak memory 211228 kb
Host smart-a74836cb-4c25-4a05-83be-0a5341dfc727
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130524853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2130524853
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.986341663
Short name T77
Test name
Test status
Simulation time 3278783009 ps
CPU time 32.87 seconds
Started Aug 10 05:38:04 PM PDT 24
Finished Aug 10 05:38:37 PM PDT 24
Peak memory 211500 kb
Host smart-25753ff9-74e3-44c3-98be-61ad0e4e5840
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986341663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.986341663
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1022084398
Short name T365
Test name
Test status
Simulation time 86826795 ps
CPU time 4.41 seconds
Started Aug 10 05:38:05 PM PDT 24
Finished Aug 10 05:38:09 PM PDT 24
Peak memory 211308 kb
Host smart-541ec504-a0a2-49c0-8f68-928fe5b72732
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022084398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1022084398
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3214977689
Short name T340
Test name
Test status
Simulation time 293233194 ps
CPU time 7.55 seconds
Started Aug 10 05:38:04 PM PDT 24
Finished Aug 10 05:38:11 PM PDT 24
Peak memory 219672 kb
Host smart-ad9653df-f065-4e9a-8977-06ee95d864aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214977689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3214977689
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3402912624
Short name T53
Test name
Test status
Simulation time 224544455 ps
CPU time 38.17 seconds
Started Aug 10 05:38:02 PM PDT 24
Finished Aug 10 05:38:41 PM PDT 24
Peak memory 213708 kb
Host smart-a08edf3f-a307-4523-aaf6-ddca2e89e71b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402912624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3402912624
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.535399504
Short name T379
Test name
Test status
Simulation time 89643096 ps
CPU time 4.22 seconds
Started Aug 10 05:38:02 PM PDT 24
Finished Aug 10 05:38:07 PM PDT 24
Peak memory 211284 kb
Host smart-f93eb1f8-4977-46a8-94fd-c03eac16bab9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535399504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.535399504
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.936026734
Short name T393
Test name
Test status
Simulation time 827956138 ps
CPU time 5.52 seconds
Started Aug 10 05:38:03 PM PDT 24
Finished Aug 10 05:38:09 PM PDT 24
Peak memory 211280 kb
Host smart-40773fb6-62da-4981-a8cb-99fbf21cf0eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936026734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.936026734
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3447874521
Short name T89
Test name
Test status
Simulation time 94858226 ps
CPU time 7.4 seconds
Started Aug 10 05:38:03 PM PDT 24
Finished Aug 10 05:38:11 PM PDT 24
Peak memory 219140 kb
Host smart-b64feb53-702e-45e8-97f7-5ee1361dd866
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447874521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3447874521
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1982597688
Short name T422
Test name
Test status
Simulation time 145506770 ps
CPU time 5.99 seconds
Started Aug 10 05:38:04 PM PDT 24
Finished Aug 10 05:38:10 PM PDT 24
Peak memory 215856 kb
Host smart-d4da89e0-4a1a-4b88-a123-08d889c259e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982597688 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1982597688
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.232536708
Short name T57
Test name
Test status
Simulation time 1380617342 ps
CPU time 5.14 seconds
Started Aug 10 05:38:03 PM PDT 24
Finished Aug 10 05:38:08 PM PDT 24
Peak memory 211284 kb
Host smart-f7043fbb-148d-4625-93d3-4d06e5ced74c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232536708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.232536708
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.980229330
Short name T350
Test name
Test status
Simulation time 153081846 ps
CPU time 4.99 seconds
Started Aug 10 05:38:02 PM PDT 24
Finished Aug 10 05:38:07 PM PDT 24
Peak memory 211168 kb
Host smart-e03dc952-1f13-4760-bb4a-8a13b9814ee2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980229330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.980229330
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1340865153
Short name T411
Test name
Test status
Simulation time 131633223 ps
CPU time 5.1 seconds
Started Aug 10 05:38:05 PM PDT 24
Finished Aug 10 05:38:10 PM PDT 24
Peak memory 211208 kb
Host smart-c96da27d-30f4-4734-bd55-270bc44e0e84
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340865153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1340865153
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.508585961
Short name T82
Test name
Test status
Simulation time 565055770 ps
CPU time 27.58 seconds
Started Aug 10 05:38:04 PM PDT 24
Finished Aug 10 05:38:32 PM PDT 24
Peak memory 211388 kb
Host smart-714ee3f8-e55d-4331-a99f-649937ad53c6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508585961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.508585961
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1790911750
Short name T339
Test name
Test status
Simulation time 332700261 ps
CPU time 4.31 seconds
Started Aug 10 05:38:04 PM PDT 24
Finished Aug 10 05:38:08 PM PDT 24
Peak memory 211376 kb
Host smart-5cf1756c-9064-4115-866c-253cad7bec00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790911750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1790911750
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3384641166
Short name T364
Test name
Test status
Simulation time 435203439 ps
CPU time 9.06 seconds
Started Aug 10 05:38:04 PM PDT 24
Finished Aug 10 05:38:13 PM PDT 24
Peak memory 216516 kb
Host smart-a290cfe8-84fc-4c15-ab9e-7ab1413ad314
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384641166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3384641166
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3937876911
Short name T109
Test name
Test status
Simulation time 370618937 ps
CPU time 36.8 seconds
Started Aug 10 05:38:03 PM PDT 24
Finished Aug 10 05:38:40 PM PDT 24
Peak memory 219468 kb
Host smart-62822fd2-2d81-4359-b73a-d05e0dfd72f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937876911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3937876911
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3808377206
Short name T357
Test name
Test status
Simulation time 457907879 ps
CPU time 4.54 seconds
Started Aug 10 05:38:11 PM PDT 24
Finished Aug 10 05:38:16 PM PDT 24
Peak memory 214192 kb
Host smart-1e4c3677-2e27-412d-9a79-723a20081b63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808377206 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3808377206
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1118257888
Short name T386
Test name
Test status
Simulation time 1785436414 ps
CPU time 5.08 seconds
Started Aug 10 05:38:02 PM PDT 24
Finished Aug 10 05:38:07 PM PDT 24
Peak memory 211228 kb
Host smart-bae5c2a1-128e-4cba-8711-764f5c704629
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118257888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1118257888
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1771451646
Short name T87
Test name
Test status
Simulation time 2997566723 ps
CPU time 27.7 seconds
Started Aug 10 05:38:02 PM PDT 24
Finished Aug 10 05:38:30 PM PDT 24
Peak memory 211476 kb
Host smart-b1051b7c-f768-4f5d-b28b-430090977c40
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771451646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1771451646
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1558586285
Short name T405
Test name
Test status
Simulation time 141059218 ps
CPU time 7.2 seconds
Started Aug 10 05:38:10 PM PDT 24
Finished Aug 10 05:38:17 PM PDT 24
Peak memory 211372 kb
Host smart-f845a7b3-3c77-4ac6-80f3-1f0f19f55ef8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558586285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1558586285
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1208420948
Short name T389
Test name
Test status
Simulation time 285877749 ps
CPU time 10.29 seconds
Started Aug 10 05:38:05 PM PDT 24
Finished Aug 10 05:38:16 PM PDT 24
Peak memory 219636 kb
Host smart-e2f8ec6c-322b-4ec9-89cd-9137ec3caf7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208420948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1208420948
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.703844601
Short name T115
Test name
Test status
Simulation time 211677780 ps
CPU time 37.3 seconds
Started Aug 10 05:38:02 PM PDT 24
Finished Aug 10 05:38:40 PM PDT 24
Peak memory 219496 kb
Host smart-4e3ead9b-6615-453b-92ea-6913f02c0157
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703844601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.703844601
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2188812648
Short name T327
Test name
Test status
Simulation time 138461459 ps
CPU time 5.47 seconds
Started Aug 10 05:38:10 PM PDT 24
Finished Aug 10 05:38:15 PM PDT 24
Peak memory 219464 kb
Host smart-16cad35f-a9ee-4a5c-a1de-4c02ca154872
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188812648 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2188812648
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4191552402
Short name T56
Test name
Test status
Simulation time 132225747 ps
CPU time 5.17 seconds
Started Aug 10 05:38:11 PM PDT 24
Finished Aug 10 05:38:16 PM PDT 24
Peak memory 211296 kb
Host smart-5edc60b4-56ed-445c-be04-de69dc6f7fc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191552402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.4191552402
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3026173904
Short name T384
Test name
Test status
Simulation time 782498126 ps
CPU time 19.09 seconds
Started Aug 10 05:38:13 PM PDT 24
Finished Aug 10 05:38:32 PM PDT 24
Peak memory 211388 kb
Host smart-2f17276f-6362-4715-bf95-b188b30f1e9c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026173904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3026173904
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1806301228
Short name T376
Test name
Test status
Simulation time 321651256 ps
CPU time 4.3 seconds
Started Aug 10 05:38:13 PM PDT 24
Finished Aug 10 05:38:17 PM PDT 24
Peak memory 210728 kb
Host smart-6871fc67-7ab2-41f3-aac4-c99e43f7e4bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806301228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1806301228
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2400616086
Short name T368
Test name
Test status
Simulation time 88948222 ps
CPU time 7.02 seconds
Started Aug 10 05:38:10 PM PDT 24
Finished Aug 10 05:38:18 PM PDT 24
Peak memory 215236 kb
Host smart-e8b78955-8424-44dd-9582-17c19a4586b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400616086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2400616086
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4211912521
Short name T374
Test name
Test status
Simulation time 655240508 ps
CPU time 37.82 seconds
Started Aug 10 05:38:11 PM PDT 24
Finished Aug 10 05:38:49 PM PDT 24
Peak memory 213652 kb
Host smart-e94436c2-155f-4dce-9f7e-4d699b1fd5f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211912521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.4211912521
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3931534834
Short name T369
Test name
Test status
Simulation time 1020550798 ps
CPU time 4.66 seconds
Started Aug 10 05:38:09 PM PDT 24
Finished Aug 10 05:38:14 PM PDT 24
Peak memory 214828 kb
Host smart-63c7df42-2806-4c50-a972-b72498fc873d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931534834 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3931534834
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.786774633
Short name T363
Test name
Test status
Simulation time 127187636 ps
CPU time 5.09 seconds
Started Aug 10 05:38:10 PM PDT 24
Finished Aug 10 05:38:15 PM PDT 24
Peak memory 218104 kb
Host smart-16ec7389-722a-47fa-bb5a-e06b9fa7f0f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786774633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.786774633
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1632163711
Short name T86
Test name
Test status
Simulation time 567395143 ps
CPU time 27.43 seconds
Started Aug 10 05:38:13 PM PDT 24
Finished Aug 10 05:38:40 PM PDT 24
Peak memory 210784 kb
Host smart-6bad7961-8315-4f08-ba86-8fdf2c4fbb72
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632163711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1632163711
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1099261875
Short name T377
Test name
Test status
Simulation time 89521375 ps
CPU time 4.25 seconds
Started Aug 10 05:38:09 PM PDT 24
Finished Aug 10 05:38:13 PM PDT 24
Peak memory 219512 kb
Host smart-8ed76eb9-4b7f-4394-901d-e0b07528cea7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099261875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1099261875
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3792381983
Short name T351
Test name
Test status
Simulation time 129872657 ps
CPU time 8.38 seconds
Started Aug 10 05:38:12 PM PDT 24
Finished Aug 10 05:38:21 PM PDT 24
Peak memory 215328 kb
Host smart-b5b8b1a4-06be-4624-a69d-76755a2e203c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792381983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3792381983
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1536967703
Short name T112
Test name
Test status
Simulation time 219241043 ps
CPU time 36.45 seconds
Started Aug 10 05:38:09 PM PDT 24
Finished Aug 10 05:38:46 PM PDT 24
Peak memory 212060 kb
Host smart-57ceafad-f38b-48bf-8114-c4c90e75aa58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536967703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1536967703
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4179251627
Short name T343
Test name
Test status
Simulation time 577671524 ps
CPU time 5.77 seconds
Started Aug 10 05:38:11 PM PDT 24
Finished Aug 10 05:38:17 PM PDT 24
Peak memory 215304 kb
Host smart-5c22b476-a237-4835-b8eb-d837fd950972
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179251627 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4179251627
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1627047259
Short name T398
Test name
Test status
Simulation time 257220022 ps
CPU time 4.89 seconds
Started Aug 10 05:38:10 PM PDT 24
Finished Aug 10 05:38:15 PM PDT 24
Peak memory 218744 kb
Host smart-a16b2826-f354-4463-8f5e-b14af84d6b8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627047259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1627047259
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3188320391
Short name T103
Test name
Test status
Simulation time 3280900685 ps
CPU time 31.83 seconds
Started Aug 10 05:38:11 PM PDT 24
Finished Aug 10 05:38:43 PM PDT 24
Peak memory 219632 kb
Host smart-29df6cba-b530-4961-819c-1f7e0efc6d04
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188320391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3188320391
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3702982348
Short name T94
Test name
Test status
Simulation time 133798313 ps
CPU time 5.17 seconds
Started Aug 10 05:38:13 PM PDT 24
Finished Aug 10 05:38:18 PM PDT 24
Peak memory 218836 kb
Host smart-389cb10f-0b50-4d11-bb67-42a5bb4cd811
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702982348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3702982348
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1912224472
Short name T423
Test name
Test status
Simulation time 730817111 ps
CPU time 8.03 seconds
Started Aug 10 05:38:12 PM PDT 24
Finished Aug 10 05:38:20 PM PDT 24
Peak memory 216556 kb
Host smart-6fe38844-eb3b-48fd-bd11-c217bb0eb8e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912224472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1912224472
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3418736184
Short name T108
Test name
Test status
Simulation time 676995947 ps
CPU time 72.07 seconds
Started Aug 10 05:38:12 PM PDT 24
Finished Aug 10 05:39:24 PM PDT 24
Peak memory 213108 kb
Host smart-be659d24-502b-4120-b25e-177395ad6678
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418736184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3418736184
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2064327897
Short name T410
Test name
Test status
Simulation time 140967054 ps
CPU time 5.65 seconds
Started Aug 10 05:38:19 PM PDT 24
Finished Aug 10 05:38:25 PM PDT 24
Peak memory 214428 kb
Host smart-9788218e-afbc-4db1-8e3e-6d541172cc41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064327897 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2064327897
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2781210916
Short name T355
Test name
Test status
Simulation time 249279363 ps
CPU time 4.97 seconds
Started Aug 10 05:38:20 PM PDT 24
Finished Aug 10 05:38:25 PM PDT 24
Peak memory 218192 kb
Host smart-4a53ba62-db52-4daa-a9e1-91302f017d51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781210916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2781210916
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.688979199
Short name T85
Test name
Test status
Simulation time 7975834397 ps
CPU time 31.54 seconds
Started Aug 10 05:38:21 PM PDT 24
Finished Aug 10 05:38:52 PM PDT 24
Peak memory 212480 kb
Host smart-b1fdf0c1-37d6-40c5-98e9-3b14d87c8949
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688979199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.688979199
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3849989259
Short name T92
Test name
Test status
Simulation time 86419359 ps
CPU time 4.2 seconds
Started Aug 10 05:38:17 PM PDT 24
Finished Aug 10 05:38:21 PM PDT 24
Peak memory 218360 kb
Host smart-b6f97f35-d1a6-4e3d-95e9-e1839b76008c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849989259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3849989259
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.433427658
Short name T326
Test name
Test status
Simulation time 130932589 ps
CPU time 9.2 seconds
Started Aug 10 05:38:19 PM PDT 24
Finished Aug 10 05:38:28 PM PDT 24
Peak memory 216548 kb
Host smart-257ccfe7-a296-4dd4-abd7-1b6ec5219d87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433427658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.433427658
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2329302710
Short name T396
Test name
Test status
Simulation time 454235070 ps
CPU time 43.96 seconds
Started Aug 10 05:38:18 PM PDT 24
Finished Aug 10 05:39:02 PM PDT 24
Peak memory 213120 kb
Host smart-7593ed33-85bb-470f-9069-1a756cb690f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329302710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2329302710
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1317974971
Short name T124
Test name
Test status
Simulation time 626512900 ps
CPU time 5.34 seconds
Started Aug 10 05:36:30 PM PDT 24
Finished Aug 10 05:36:35 PM PDT 24
Peak memory 212052 kb
Host smart-f0667717-9492-48aa-9eb4-81ba2d606dbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317974971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1317974971
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.841933719
Short name T163
Test name
Test status
Simulation time 1728999186 ps
CPU time 91.01 seconds
Started Aug 10 05:36:26 PM PDT 24
Finished Aug 10 05:37:57 PM PDT 24
Peak memory 238440 kb
Host smart-44264676-7753-4025-9a5f-5c22deb6f257
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841933719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.841933719
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.984396414
Short name T184
Test name
Test status
Simulation time 576213462 ps
CPU time 6.24 seconds
Started Aug 10 05:36:23 PM PDT 24
Finished Aug 10 05:36:29 PM PDT 24
Peak memory 212188 kb
Host smart-efd0cbc7-2a91-47c9-9831-4e8f7bbf7565
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=984396414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.984396414
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.549462583
Short name T74
Test name
Test status
Simulation time 140237098 ps
CPU time 6.49 seconds
Started Aug 10 05:36:19 PM PDT 24
Finished Aug 10 05:36:25 PM PDT 24
Peak memory 212128 kb
Host smart-2f38b986-9c97-4b88-8d1e-f35d02abb5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549462583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.549462583
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2802700370
Short name T313
Test name
Test status
Simulation time 1129616247 ps
CPU time 13.3 seconds
Started Aug 10 05:36:19 PM PDT 24
Finished Aug 10 05:36:32 PM PDT 24
Peak memory 213904 kb
Host smart-40661a2a-aa06-4d87-a43b-6fc22eb2cf55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802700370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2802700370
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1773581006
Short name T27
Test name
Test status
Simulation time 552551243 ps
CPU time 4.24 seconds
Started Aug 10 05:36:27 PM PDT 24
Finished Aug 10 05:36:32 PM PDT 24
Peak memory 212104 kb
Host smart-47c4affe-8650-47de-8ce4-bfaae95819bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773581006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1773581006
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2596440021
Short name T177
Test name
Test status
Simulation time 995042407 ps
CPU time 57.08 seconds
Started Aug 10 05:36:26 PM PDT 24
Finished Aug 10 05:37:23 PM PDT 24
Peak memory 237288 kb
Host smart-a0e5c960-3a04-4671-b897-c97c4be6dc39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596440021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2596440021
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3157486848
Short name T222
Test name
Test status
Simulation time 962535991 ps
CPU time 10.95 seconds
Started Aug 10 05:36:28 PM PDT 24
Finished Aug 10 05:36:39 PM PDT 24
Peak memory 213040 kb
Host smart-9d18cc55-e60f-4f0d-b659-4045199a64c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157486848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3157486848
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3095409527
Short name T26
Test name
Test status
Simulation time 2633301327 ps
CPU time 6.62 seconds
Started Aug 10 05:36:29 PM PDT 24
Finished Aug 10 05:36:36 PM PDT 24
Peak memory 212336 kb
Host smart-5d7ce97f-e95d-4469-a355-8c7e310b1ce2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3095409527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3095409527
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.487023277
Short name T24
Test name
Test status
Simulation time 1156775795 ps
CPU time 54.42 seconds
Started Aug 10 05:36:28 PM PDT 24
Finished Aug 10 05:37:22 PM PDT 24
Peak memory 237336 kb
Host smart-792ded92-6125-48f7-a043-f9d112f3ce6e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487023277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.487023277
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1860718049
Short name T225
Test name
Test status
Simulation time 265163597 ps
CPU time 6.08 seconds
Started Aug 10 05:36:29 PM PDT 24
Finished Aug 10 05:36:35 PM PDT 24
Peak memory 212168 kb
Host smart-b63bf570-bbc6-4229-a67a-0f4cdc7dd9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860718049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1860718049
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3414658726
Short name T32
Test name
Test status
Simulation time 158645321 ps
CPU time 10.99 seconds
Started Aug 10 05:36:27 PM PDT 24
Finished Aug 10 05:36:38 PM PDT 24
Peak memory 212116 kb
Host smart-09166af3-5d53-4926-91f0-9d9cd7479f28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414658726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3414658726
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.502991742
Short name T59
Test name
Test status
Simulation time 131909598 ps
CPU time 5.08 seconds
Started Aug 10 05:36:51 PM PDT 24
Finished Aug 10 05:36:56 PM PDT 24
Peak memory 212044 kb
Host smart-69463709-df9c-4649-96ed-663bc4d84d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502991742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.502991742
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.101252668
Short name T191
Test name
Test status
Simulation time 5227044775 ps
CPU time 57.99 seconds
Started Aug 10 05:36:48 PM PDT 24
Finished Aug 10 05:37:47 PM PDT 24
Peak memory 213440 kb
Host smart-2de89f70-4eb0-47ef-bf6e-d5eea41b2b4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101252668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.101252668
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3781659852
Short name T43
Test name
Test status
Simulation time 665635235 ps
CPU time 9.9 seconds
Started Aug 10 05:36:48 PM PDT 24
Finished Aug 10 05:36:58 PM PDT 24
Peak memory 212896 kb
Host smart-e115046b-223f-43ca-96e6-de91f1c7a938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781659852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3781659852
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.279098106
Short name T102
Test name
Test status
Simulation time 99858918 ps
CPU time 5.3 seconds
Started Aug 10 05:36:51 PM PDT 24
Finished Aug 10 05:36:56 PM PDT 24
Peak memory 212188 kb
Host smart-93a74688-0d47-4906-bd67-3ba5ae1afba2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=279098106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.279098106
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3147729698
Short name T291
Test name
Test status
Simulation time 1695095784 ps
CPU time 18.97 seconds
Started Aug 10 05:36:51 PM PDT 24
Finished Aug 10 05:37:10 PM PDT 24
Peak memory 215800 kb
Host smart-e980d1d6-3ae9-4f76-b467-75306a54f71f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147729698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3147729698
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3500992379
Short name T317
Test name
Test status
Simulation time 522961251 ps
CPU time 5.06 seconds
Started Aug 10 05:36:48 PM PDT 24
Finished Aug 10 05:36:53 PM PDT 24
Peak memory 212096 kb
Host smart-c9deea5d-7579-4d37-be09-94d15d620309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500992379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3500992379
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4130747849
Short name T220
Test name
Test status
Simulation time 3942764830 ps
CPU time 94.13 seconds
Started Aug 10 05:36:49 PM PDT 24
Finished Aug 10 05:38:23 PM PDT 24
Peak memory 238608 kb
Host smart-52dc8250-2076-4264-b016-09bde4676147
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130747849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.4130747849
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2489602477
Short name T296
Test name
Test status
Simulation time 1315650266 ps
CPU time 11.34 seconds
Started Aug 10 05:36:48 PM PDT 24
Finished Aug 10 05:37:00 PM PDT 24
Peak memory 212944 kb
Host smart-3e5c4129-c5ab-4237-8ce6-86738c6fdc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489602477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2489602477
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.781714317
Short name T264
Test name
Test status
Simulation time 566221581 ps
CPU time 6.7 seconds
Started Aug 10 05:36:53 PM PDT 24
Finished Aug 10 05:37:00 PM PDT 24
Peak memory 212184 kb
Host smart-4713c13f-a1b6-4912-a0d1-0cd4ac190b39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=781714317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.781714317
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1574165072
Short name T196
Test name
Test status
Simulation time 302762075 ps
CPU time 13.09 seconds
Started Aug 10 05:36:50 PM PDT 24
Finished Aug 10 05:37:04 PM PDT 24
Peak memory 215252 kb
Host smart-c1bb9f79-71ca-4634-bd26-cc3704802c75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574165072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1574165072
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3577872696
Short name T25
Test name
Test status
Simulation time 347402375 ps
CPU time 4.22 seconds
Started Aug 10 05:36:49 PM PDT 24
Finished Aug 10 05:36:53 PM PDT 24
Peak memory 212108 kb
Host smart-9b7d0168-94ef-4165-8dda-ba582c1ddf76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577872696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3577872696
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3832823874
Short name T162
Test name
Test status
Simulation time 4232944114 ps
CPU time 111.71 seconds
Started Aug 10 05:36:48 PM PDT 24
Finished Aug 10 05:38:40 PM PDT 24
Peak memory 234448 kb
Host smart-bc1298e6-db3a-4147-88cd-50819b4ad58d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832823874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3832823874
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.680106194
Short name T283
Test name
Test status
Simulation time 286953470 ps
CPU time 11.45 seconds
Started Aug 10 05:36:51 PM PDT 24
Finished Aug 10 05:37:02 PM PDT 24
Peak memory 212884 kb
Host smart-a5f282cf-245f-4a39-9543-d2359df77c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680106194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.680106194
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.841169249
Short name T198
Test name
Test status
Simulation time 186904307 ps
CPU time 5.76 seconds
Started Aug 10 05:36:51 PM PDT 24
Finished Aug 10 05:36:56 PM PDT 24
Peak memory 212140 kb
Host smart-5a07ebea-22da-40d3-872c-4750d29824a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=841169249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.841169249
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2683246291
Short name T98
Test name
Test status
Simulation time 1213905834 ps
CPU time 12.52 seconds
Started Aug 10 05:36:50 PM PDT 24
Finished Aug 10 05:37:02 PM PDT 24
Peak memory 214884 kb
Host smart-ab6530fe-f367-4cc4-a5c0-2f1101a13b7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683246291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2683246291
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.725061947
Short name T139
Test name
Test status
Simulation time 297945365 ps
CPU time 4.3 seconds
Started Aug 10 05:36:51 PM PDT 24
Finished Aug 10 05:36:56 PM PDT 24
Peak memory 212080 kb
Host smart-074f441f-598a-45cb-b037-6ea95ead664f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725061947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.725061947
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2070650746
Short name T300
Test name
Test status
Simulation time 2290879027 ps
CPU time 110.96 seconds
Started Aug 10 05:36:49 PM PDT 24
Finished Aug 10 05:38:40 PM PDT 24
Peak memory 237472 kb
Host smart-34f7cf45-1966-4b16-a983-bf793755fd4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070650746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2070650746
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1369151816
Short name T187
Test name
Test status
Simulation time 175674889 ps
CPU time 9.22 seconds
Started Aug 10 05:36:49 PM PDT 24
Finished Aug 10 05:36:58 PM PDT 24
Peak memory 212856 kb
Host smart-7ee0c473-4ce1-42ee-bd51-01011235b51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369151816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1369151816
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1517790375
Short name T126
Test name
Test status
Simulation time 137884763 ps
CPU time 6.52 seconds
Started Aug 10 05:36:51 PM PDT 24
Finished Aug 10 05:36:57 PM PDT 24
Peak memory 212204 kb
Host smart-6001822c-1d8d-46e7-8b65-cfbf48e42617
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1517790375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1517790375
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1997860486
Short name T73
Test name
Test status
Simulation time 1696022958 ps
CPU time 12.01 seconds
Started Aug 10 05:36:51 PM PDT 24
Finished Aug 10 05:37:03 PM PDT 24
Peak memory 213244 kb
Host smart-f337fd5b-fde1-412f-a792-df3845d5ded1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997860486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1997860486
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3181163075
Short name T282
Test name
Test status
Simulation time 168614714 ps
CPU time 4.29 seconds
Started Aug 10 05:36:49 PM PDT 24
Finished Aug 10 05:36:54 PM PDT 24
Peak memory 212072 kb
Host smart-65902cba-4174-41de-ba93-fa33fae4a4f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181163075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3181163075
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4102156539
Short name T248
Test name
Test status
Simulation time 1528651282 ps
CPU time 93.88 seconds
Started Aug 10 05:36:52 PM PDT 24
Finished Aug 10 05:38:26 PM PDT 24
Peak memory 228644 kb
Host smart-0f879e0a-7399-496d-af0b-f17b2e0e4403
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102156539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.4102156539
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3471715435
Short name T228
Test name
Test status
Simulation time 4101463383 ps
CPU time 16.05 seconds
Started Aug 10 05:36:50 PM PDT 24
Finished Aug 10 05:37:07 PM PDT 24
Peak memory 212884 kb
Host smart-44926842-d4b9-40af-be3e-4f708a1f628e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471715435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3471715435
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4139536667
Short name T100
Test name
Test status
Simulation time 148188502 ps
CPU time 5.79 seconds
Started Aug 10 05:36:48 PM PDT 24
Finished Aug 10 05:36:54 PM PDT 24
Peak memory 212180 kb
Host smart-0a6fcad5-6326-4a5d-93fc-7b9639cbcdb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4139536667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4139536667
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.252527786
Short name T189
Test name
Test status
Simulation time 282074013 ps
CPU time 9.26 seconds
Started Aug 10 05:36:52 PM PDT 24
Finished Aug 10 05:37:01 PM PDT 24
Peak memory 212148 kb
Host smart-3dd85615-b6a7-49a6-870a-e3f625b3de9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252527786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.252527786
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3209875857
Short name T203
Test name
Test status
Simulation time 132909068 ps
CPU time 5.26 seconds
Started Aug 10 05:37:01 PM PDT 24
Finished Aug 10 05:37:06 PM PDT 24
Peak memory 212072 kb
Host smart-41355f3c-8233-4eb0-8d4f-8a27f946559e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209875857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3209875857
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1856917144
Short name T308
Test name
Test status
Simulation time 8194313635 ps
CPU time 116.25 seconds
Started Aug 10 05:36:58 PM PDT 24
Finished Aug 10 05:38:54 PM PDT 24
Peak memory 233736 kb
Host smart-09419fb2-6672-4936-8590-742f62d52057
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856917144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1856917144
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1412615020
Short name T4
Test name
Test status
Simulation time 342924962 ps
CPU time 9.4 seconds
Started Aug 10 05:36:59 PM PDT 24
Finished Aug 10 05:37:09 PM PDT 24
Peak memory 212500 kb
Host smart-72e775c2-d4bf-4afe-83d7-0bba2d6e1f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412615020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1412615020
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3852383724
Short name T101
Test name
Test status
Simulation time 100804612 ps
CPU time 5.62 seconds
Started Aug 10 05:36:57 PM PDT 24
Finished Aug 10 05:37:03 PM PDT 24
Peak memory 212180 kb
Host smart-dc389c83-27b3-495d-bb11-742e0a1e904a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3852383724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3852383724
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2501885817
Short name T304
Test name
Test status
Simulation time 1028850766 ps
CPU time 21.03 seconds
Started Aug 10 05:36:50 PM PDT 24
Finished Aug 10 05:37:11 PM PDT 24
Peak memory 215940 kb
Host smart-d6cbe094-df10-4088-a299-51236c2880ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501885817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2501885817
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1147214240
Short name T260
Test name
Test status
Simulation time 4945874558 ps
CPU time 7.52 seconds
Started Aug 10 05:36:59 PM PDT 24
Finished Aug 10 05:37:06 PM PDT 24
Peak memory 212028 kb
Host smart-b774384b-5d17-4ad5-a32c-9a427834fe4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147214240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1147214240
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3662206582
Short name T273
Test name
Test status
Simulation time 1542420238 ps
CPU time 93.31 seconds
Started Aug 10 05:37:00 PM PDT 24
Finished Aug 10 05:38:33 PM PDT 24
Peak memory 237416 kb
Host smart-d9cd91e6-d22b-49e2-af55-9a481e2b2b31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662206582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3662206582
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.4173301050
Short name T180
Test name
Test status
Simulation time 619089537 ps
CPU time 9.32 seconds
Started Aug 10 05:37:00 PM PDT 24
Finished Aug 10 05:37:10 PM PDT 24
Peak memory 212872 kb
Host smart-59e007bf-a5b5-4202-8ad0-7fc662ce687a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173301050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.4173301050
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1056524857
Short name T194
Test name
Test status
Simulation time 141398895 ps
CPU time 12.47 seconds
Started Aug 10 05:37:02 PM PDT 24
Finished Aug 10 05:37:14 PM PDT 24
Peak memory 212184 kb
Host smart-c8bd200e-5d87-4bd7-a6e0-5b7a0bc70564
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056524857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1056524857
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.443739015
Short name T295
Test name
Test status
Simulation time 594642975 ps
CPU time 5.12 seconds
Started Aug 10 05:37:00 PM PDT 24
Finished Aug 10 05:37:06 PM PDT 24
Peak memory 212036 kb
Host smart-9b3bcfcb-9491-4a74-af15-95859753558c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443739015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.443739015
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2749186497
Short name T320
Test name
Test status
Simulation time 2639154082 ps
CPU time 142.13 seconds
Started Aug 10 05:36:59 PM PDT 24
Finished Aug 10 05:39:22 PM PDT 24
Peak memory 229308 kb
Host smart-b5f4da1d-337f-4bc6-9400-98c5ae5612f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749186497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2749186497
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1148260047
Short name T318
Test name
Test status
Simulation time 188472150 ps
CPU time 9.44 seconds
Started Aug 10 05:37:00 PM PDT 24
Finished Aug 10 05:37:10 PM PDT 24
Peak memory 213016 kb
Host smart-a089fd75-641b-44fa-981a-79bd14622ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148260047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1148260047
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.862812689
Short name T226
Test name
Test status
Simulation time 370668238 ps
CPU time 5.65 seconds
Started Aug 10 05:36:59 PM PDT 24
Finished Aug 10 05:37:05 PM PDT 24
Peak memory 212212 kb
Host smart-dd5d0f49-9ea6-4e89-b7ba-007bf4c66411
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=862812689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.862812689
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1947631787
Short name T299
Test name
Test status
Simulation time 1641247447 ps
CPU time 20.41 seconds
Started Aug 10 05:37:00 PM PDT 24
Finished Aug 10 05:37:20 PM PDT 24
Peak memory 216288 kb
Host smart-bb906ea1-6e38-4be8-8195-bb2803921c15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947631787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1947631787
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2125167110
Short name T185
Test name
Test status
Simulation time 417209446 ps
CPU time 4.46 seconds
Started Aug 10 05:36:58 PM PDT 24
Finished Aug 10 05:37:03 PM PDT 24
Peak memory 212044 kb
Host smart-ec45beb6-abca-4472-b334-b1792d8ba179
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125167110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2125167110
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1959763638
Short name T223
Test name
Test status
Simulation time 10739853162 ps
CPU time 133.2 seconds
Started Aug 10 05:37:02 PM PDT 24
Finished Aug 10 05:39:15 PM PDT 24
Peak memory 225740 kb
Host smart-7e4e75be-b27e-450d-b04d-ea28edaa9ea8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959763638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1959763638
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.518150016
Short name T233
Test name
Test status
Simulation time 1183489142 ps
CPU time 9.46 seconds
Started Aug 10 05:36:58 PM PDT 24
Finished Aug 10 05:37:08 PM PDT 24
Peak memory 212996 kb
Host smart-8f77945d-e36e-408e-a034-10366db487f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518150016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.518150016
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2548423612
Short name T250
Test name
Test status
Simulation time 141940064 ps
CPU time 6.46 seconds
Started Aug 10 05:36:59 PM PDT 24
Finished Aug 10 05:37:06 PM PDT 24
Peak memory 212212 kb
Host smart-4cf73934-ce6e-4c75-bd17-2ab45320bc10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2548423612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2548423612
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3180018482
Short name T217
Test name
Test status
Simulation time 305631783 ps
CPU time 15.62 seconds
Started Aug 10 05:36:59 PM PDT 24
Finished Aug 10 05:37:15 PM PDT 24
Peak memory 215096 kb
Host smart-8b804900-9ec8-4432-b009-6f68c119eee2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180018482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3180018482
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.4258904778
Short name T246
Test name
Test status
Simulation time 179073197609 ps
CPU time 1668.44 seconds
Started Aug 10 05:37:00 PM PDT 24
Finished Aug 10 06:04:49 PM PDT 24
Peak memory 236696 kb
Host smart-f1eb0776-de88-436a-8918-8aae47aff1aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258904778 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.4258904778
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.4267775872
Short name T242
Test name
Test status
Simulation time 248773992 ps
CPU time 5.19 seconds
Started Aug 10 05:36:59 PM PDT 24
Finished Aug 10 05:37:05 PM PDT 24
Peak memory 212104 kb
Host smart-0d26b75a-30f6-4af4-9654-54134de5afe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267775872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.4267775872
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3419630942
Short name T219
Test name
Test status
Simulation time 2994828328 ps
CPU time 146.31 seconds
Started Aug 10 05:37:00 PM PDT 24
Finished Aug 10 05:39:27 PM PDT 24
Peak memory 228532 kb
Host smart-5ea27720-ecfe-4e62-8231-02ae2ffd9176
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419630942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3419630942
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3472266961
Short name T30
Test name
Test status
Simulation time 757680856 ps
CPU time 9.73 seconds
Started Aug 10 05:37:00 PM PDT 24
Finished Aug 10 05:37:10 PM PDT 24
Peak memory 212892 kb
Host smart-12ab3a9d-eff3-4f71-9a8c-000538dfba19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472266961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3472266961
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.73431461
Short name T119
Test name
Test status
Simulation time 1028225769 ps
CPU time 9.07 seconds
Started Aug 10 05:36:59 PM PDT 24
Finished Aug 10 05:37:08 PM PDT 24
Peak memory 212200 kb
Host smart-b971a990-7491-42f9-bf64-4561084e5129
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=73431461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.73431461
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2684823032
Short name T245
Test name
Test status
Simulation time 433223923 ps
CPU time 8.63 seconds
Started Aug 10 05:37:01 PM PDT 24
Finished Aug 10 05:37:10 PM PDT 24
Peak memory 212152 kb
Host smart-11aa29b2-543d-42ea-bfb5-825d3880d8e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684823032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2684823032
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3871912741
Short name T123
Test name
Test status
Simulation time 828133850 ps
CPU time 5.19 seconds
Started Aug 10 05:36:33 PM PDT 24
Finished Aug 10 05:36:38 PM PDT 24
Peak memory 212052 kb
Host smart-639b9204-d034-48ae-9af1-f634040ce3ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871912741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3871912741
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3306203312
Short name T285
Test name
Test status
Simulation time 1699098904 ps
CPU time 113.84 seconds
Started Aug 10 05:36:28 PM PDT 24
Finished Aug 10 05:38:22 PM PDT 24
Peak memory 238376 kb
Host smart-02102b3b-5234-4262-b2a0-320d5aad0ad4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306203312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3306203312
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.451525991
Short name T125
Test name
Test status
Simulation time 999177802 ps
CPU time 11.28 seconds
Started Aug 10 05:36:25 PM PDT 24
Finished Aug 10 05:36:37 PM PDT 24
Peak memory 212872 kb
Host smart-3ed9c50b-5a3c-4603-ad87-c9064801a1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451525991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.451525991
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3373620319
Short name T208
Test name
Test status
Simulation time 376654881 ps
CPU time 5.56 seconds
Started Aug 10 05:36:26 PM PDT 24
Finished Aug 10 05:36:32 PM PDT 24
Peak memory 212192 kb
Host smart-57e2d4b4-9a6b-4c3c-9b0c-6b90c35cce35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3373620319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3373620319
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2894613
Short name T23
Test name
Test status
Simulation time 357688848 ps
CPU time 51.73 seconds
Started Aug 10 05:36:26 PM PDT 24
Finished Aug 10 05:37:17 PM PDT 24
Peak memory 237396 kb
Host smart-1f98a71e-b523-4641-a7a6-37c77f9ffb2d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2894613
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2096635558
Short name T271
Test name
Test status
Simulation time 574016707 ps
CPU time 6.46 seconds
Started Aug 10 05:36:27 PM PDT 24
Finished Aug 10 05:36:34 PM PDT 24
Peak memory 212240 kb
Host smart-140825d8-ac5c-4548-a4b7-3b265d8b86c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096635558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2096635558
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2283452299
Short name T127
Test name
Test status
Simulation time 472436307 ps
CPU time 24.54 seconds
Started Aug 10 05:36:29 PM PDT 24
Finished Aug 10 05:36:53 PM PDT 24
Peak memory 215988 kb
Host smart-15b17864-7e1d-4cd2-9918-76a31ab3a8dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283452299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2283452299
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3465886939
Short name T50
Test name
Test status
Simulation time 69714619687 ps
CPU time 7158.37 seconds
Started Aug 10 05:36:30 PM PDT 24
Finished Aug 10 07:35:49 PM PDT 24
Peak memory 236664 kb
Host smart-53f926c7-687e-4de0-8881-b0c5c6d11251
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465886939 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3465886939
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3999747311
Short name T221
Test name
Test status
Simulation time 167984092 ps
CPU time 4.47 seconds
Started Aug 10 05:37:00 PM PDT 24
Finished Aug 10 05:37:04 PM PDT 24
Peak memory 212072 kb
Host smart-c9a0877b-80a5-4f43-91a8-e7958a31da4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999747311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3999747311
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3847329943
Short name T259
Test name
Test status
Simulation time 8353382100 ps
CPU time 120.45 seconds
Started Aug 10 05:37:02 PM PDT 24
Finished Aug 10 05:39:02 PM PDT 24
Peak memory 238544 kb
Host smart-99450f1f-74ab-41ec-afed-390f521c60a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847329943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3847329943
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.720063800
Short name T199
Test name
Test status
Simulation time 252160836 ps
CPU time 11.55 seconds
Started Aug 10 05:37:02 PM PDT 24
Finished Aug 10 05:37:13 PM PDT 24
Peak memory 213052 kb
Host smart-8e6fd710-62fd-418a-93f0-afe8bfa48e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720063800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.720063800
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2518305079
Short name T136
Test name
Test status
Simulation time 431820319 ps
CPU time 5.95 seconds
Started Aug 10 05:36:58 PM PDT 24
Finished Aug 10 05:37:04 PM PDT 24
Peak memory 212152 kb
Host smart-03b01c70-c879-4f10-9f0f-8383c18153e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2518305079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2518305079
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3543384113
Short name T105
Test name
Test status
Simulation time 30805192410 ps
CPU time 620.74 seconds
Started Aug 10 05:37:00 PM PDT 24
Finished Aug 10 05:47:21 PM PDT 24
Peak memory 228432 kb
Host smart-4cf825bf-b61e-48b8-8739-2c4ef2ff13a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543384113 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3543384113
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2081118909
Short name T267
Test name
Test status
Simulation time 337317998 ps
CPU time 4.26 seconds
Started Aug 10 05:37:00 PM PDT 24
Finished Aug 10 05:37:05 PM PDT 24
Peak memory 212072 kb
Host smart-4fe45371-21e9-489e-a77f-8d6582b9f920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081118909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2081118909
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.762840203
Short name T204
Test name
Test status
Simulation time 1512659452 ps
CPU time 84.36 seconds
Started Aug 10 05:36:59 PM PDT 24
Finished Aug 10 05:38:24 PM PDT 24
Peak memory 213312 kb
Host smart-6e07e133-9bba-437c-96b2-28dfa154a50a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762840203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.762840203
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3705611137
Short name T142
Test name
Test status
Simulation time 694234589 ps
CPU time 9.5 seconds
Started Aug 10 05:37:02 PM PDT 24
Finished Aug 10 05:37:11 PM PDT 24
Peak memory 213036 kb
Host smart-cee8d04e-f8df-446d-932f-c0767902c2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705611137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3705611137
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1193918033
Short name T148
Test name
Test status
Simulation time 466902464 ps
CPU time 6.17 seconds
Started Aug 10 05:37:00 PM PDT 24
Finished Aug 10 05:37:06 PM PDT 24
Peak memory 212184 kb
Host smart-cc14a9cb-29b8-4dd0-8b13-9e066759381e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1193918033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1193918033
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3428813989
Short name T227
Test name
Test status
Simulation time 1120295003 ps
CPU time 15.04 seconds
Started Aug 10 05:37:02 PM PDT 24
Finished Aug 10 05:37:17 PM PDT 24
Peak memory 212812 kb
Host smart-d6af0b82-8820-49f0-a44d-ea57863bf986
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428813989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3428813989
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3336368176
Short name T47
Test name
Test status
Simulation time 567457179895 ps
CPU time 2186.65 seconds
Started Aug 10 05:37:02 PM PDT 24
Finished Aug 10 06:13:29 PM PDT 24
Peak memory 244552 kb
Host smart-16ab5a93-4887-43fd-8301-021c55a86ac9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336368176 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.3336368176
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3292940535
Short name T167
Test name
Test status
Simulation time 501866627 ps
CPU time 5.09 seconds
Started Aug 10 05:37:09 PM PDT 24
Finished Aug 10 05:37:15 PM PDT 24
Peak memory 212092 kb
Host smart-bf3984cc-a193-4f49-bfc8-12761fd00295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292940535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3292940535
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.493637215
Short name T277
Test name
Test status
Simulation time 5004744251 ps
CPU time 81.54 seconds
Started Aug 10 05:36:58 PM PDT 24
Finished Aug 10 05:38:20 PM PDT 24
Peak memory 225320 kb
Host smart-a48cc9c7-c368-43ac-8f82-1b7c01cb7119
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493637215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.493637215
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4188594259
Short name T276
Test name
Test status
Simulation time 170342977 ps
CPU time 9.56 seconds
Started Aug 10 05:37:08 PM PDT 24
Finished Aug 10 05:37:17 PM PDT 24
Peak memory 212872 kb
Host smart-9eb01a44-dcc9-4b2c-93ae-50a7c271caff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188594259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4188594259
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1750382760
Short name T281
Test name
Test status
Simulation time 139398792 ps
CPU time 6.9 seconds
Started Aug 10 05:36:59 PM PDT 24
Finished Aug 10 05:37:06 PM PDT 24
Peak memory 212260 kb
Host smart-14cfa157-3f21-4e87-b17a-2fa7d3b380ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1750382760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1750382760
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3419216532
Short name T190
Test name
Test status
Simulation time 1671835401 ps
CPU time 19.62 seconds
Started Aug 10 05:37:01 PM PDT 24
Finished Aug 10 05:37:20 PM PDT 24
Peak memory 214332 kb
Host smart-3fd20d58-857d-4904-a94c-ffea5cf346ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419216532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3419216532
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2858046258
Short name T261
Test name
Test status
Simulation time 164792118 ps
CPU time 5.17 seconds
Started Aug 10 05:37:09 PM PDT 24
Finished Aug 10 05:37:14 PM PDT 24
Peak memory 212044 kb
Host smart-670cc37b-3fd9-460c-be00-f997739c4503
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858046258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2858046258
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1991754213
Short name T169
Test name
Test status
Simulation time 8063396286 ps
CPU time 81.48 seconds
Started Aug 10 05:37:09 PM PDT 24
Finished Aug 10 05:38:30 PM PDT 24
Peak memory 241360 kb
Host smart-869399ab-0560-4266-9363-c8548b3e0ce3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991754213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1991754213
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.109556692
Short name T311
Test name
Test status
Simulation time 669281643 ps
CPU time 9.4 seconds
Started Aug 10 05:37:12 PM PDT 24
Finished Aug 10 05:37:22 PM PDT 24
Peak memory 212888 kb
Host smart-83e24caf-e0ae-49ce-bef1-3863fcda9a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109556692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.109556692
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.761122222
Short name T197
Test name
Test status
Simulation time 417533475 ps
CPU time 5.37 seconds
Started Aug 10 05:37:10 PM PDT 24
Finished Aug 10 05:37:15 PM PDT 24
Peak memory 212196 kb
Host smart-e10bc2cb-43b9-4084-9b72-53b5ac315e68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=761122222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.761122222
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3150328758
Short name T314
Test name
Test status
Simulation time 564582461 ps
CPU time 12.16 seconds
Started Aug 10 05:37:08 PM PDT 24
Finished Aug 10 05:37:20 PM PDT 24
Peak memory 214892 kb
Host smart-b59f9121-d4e0-4fe3-96d8-8158a3b2272b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150328758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3150328758
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2161947615
Short name T212
Test name
Test status
Simulation time 5456252843 ps
CPU time 8.05 seconds
Started Aug 10 05:37:09 PM PDT 24
Finished Aug 10 05:37:17 PM PDT 24
Peak memory 212156 kb
Host smart-99ea6bc6-83c8-45e2-9e07-25bea99fb205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161947615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2161947615
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2269294620
Short name T45
Test name
Test status
Simulation time 261904392 ps
CPU time 11.11 seconds
Started Aug 10 05:37:10 PM PDT 24
Finished Aug 10 05:37:21 PM PDT 24
Peak memory 212900 kb
Host smart-e4be2202-092c-4947-99d0-8036917e21b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269294620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2269294620
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.83010963
Short name T147
Test name
Test status
Simulation time 531118915 ps
CPU time 6 seconds
Started Aug 10 05:37:08 PM PDT 24
Finished Aug 10 05:37:14 PM PDT 24
Peak memory 212208 kb
Host smart-12fbb92d-9e3f-470d-81e5-97c473b5587b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=83010963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.83010963
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.320418892
Short name T262
Test name
Test status
Simulation time 3482461702 ps
CPU time 20.48 seconds
Started Aug 10 05:37:11 PM PDT 24
Finished Aug 10 05:37:31 PM PDT 24
Peak memory 214720 kb
Host smart-811d99a9-48ec-4619-a410-7203e1c8c3a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320418892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.320418892
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3747588128
Short name T255
Test name
Test status
Simulation time 132577643 ps
CPU time 5.2 seconds
Started Aug 10 05:37:13 PM PDT 24
Finished Aug 10 05:37:18 PM PDT 24
Peak memory 212076 kb
Host smart-d7fe598d-414d-43bc-9637-75b8fbc76cfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747588128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3747588128
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2298783634
Short name T231
Test name
Test status
Simulation time 1662260566 ps
CPU time 9.82 seconds
Started Aug 10 05:37:06 PM PDT 24
Finished Aug 10 05:37:15 PM PDT 24
Peak memory 213336 kb
Host smart-ece8e5ec-1200-46bd-9bf3-c204e333ca16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298783634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2298783634
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3346566602
Short name T183
Test name
Test status
Simulation time 559665735 ps
CPU time 6.34 seconds
Started Aug 10 05:37:07 PM PDT 24
Finished Aug 10 05:37:14 PM PDT 24
Peak memory 212168 kb
Host smart-fe0725b3-8685-466b-b918-aedf5c84186b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3346566602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3346566602
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2195460366
Short name T324
Test name
Test status
Simulation time 1921850275 ps
CPU time 17.85 seconds
Started Aug 10 05:37:08 PM PDT 24
Finished Aug 10 05:37:26 PM PDT 24
Peak memory 217372 kb
Host smart-b0c5ad32-6e1a-43ef-939b-91cc80ee40ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195460366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2195460366
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3506300962
Short name T33
Test name
Test status
Simulation time 1556450556 ps
CPU time 5.1 seconds
Started Aug 10 05:37:12 PM PDT 24
Finished Aug 10 05:37:17 PM PDT 24
Peak memory 212080 kb
Host smart-e4e0a73c-48d3-4b1e-b8e8-d6f73501e109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506300962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3506300962
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3176306307
Short name T287
Test name
Test status
Simulation time 6046638570 ps
CPU time 93.13 seconds
Started Aug 10 05:37:11 PM PDT 24
Finished Aug 10 05:38:45 PM PDT 24
Peak memory 238160 kb
Host smart-baf8ccec-cc96-47e8-95aa-295f5cfa79b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176306307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3176306307
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3128200757
Short name T131
Test name
Test status
Simulation time 275048654 ps
CPU time 9.67 seconds
Started Aug 10 05:37:08 PM PDT 24
Finished Aug 10 05:37:18 PM PDT 24
Peak memory 212932 kb
Host smart-7b4d5d8b-53b7-40e6-8c15-a02e707de7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128200757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3128200757
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3161939287
Short name T286
Test name
Test status
Simulation time 362584416 ps
CPU time 5.4 seconds
Started Aug 10 05:37:12 PM PDT 24
Finished Aug 10 05:37:18 PM PDT 24
Peak memory 212208 kb
Host smart-91a17cdc-0dd5-4308-954f-741ed6b3f4f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3161939287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3161939287
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.888424585
Short name T75
Test name
Test status
Simulation time 2063077277 ps
CPU time 11.46 seconds
Started Aug 10 05:37:08 PM PDT 24
Finished Aug 10 05:37:20 PM PDT 24
Peak memory 213420 kb
Host smart-327693cc-cd2c-4354-8ca7-42d5b5a5affd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888424585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.888424585
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2187007077
Short name T118
Test name
Test status
Simulation time 492202108 ps
CPU time 7.47 seconds
Started Aug 10 05:37:09 PM PDT 24
Finished Aug 10 05:37:17 PM PDT 24
Peak memory 212080 kb
Host smart-b6cee5e2-1bfc-43d0-905c-030ad2374ffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187007077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2187007077
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2390071494
Short name T274
Test name
Test status
Simulation time 2086950983 ps
CPU time 123.33 seconds
Started Aug 10 05:37:11 PM PDT 24
Finished Aug 10 05:39:14 PM PDT 24
Peak memory 213344 kb
Host smart-a58d6407-93d4-4496-a5ec-c7835851fcea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390071494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2390071494
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4036438475
Short name T301
Test name
Test status
Simulation time 252334987 ps
CPU time 11.11 seconds
Started Aug 10 05:37:12 PM PDT 24
Finished Aug 10 05:37:23 PM PDT 24
Peak memory 212984 kb
Host smart-08b53c11-9917-4192-ade6-a216711b0694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036438475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.4036438475
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2387198245
Short name T149
Test name
Test status
Simulation time 137848842 ps
CPU time 6.68 seconds
Started Aug 10 05:37:07 PM PDT 24
Finished Aug 10 05:37:14 PM PDT 24
Peak memory 212164 kb
Host smart-07d0bde4-864d-4f92-ba7a-4c5376c45ffb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2387198245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2387198245
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3579549789
Short name T193
Test name
Test status
Simulation time 637724480 ps
CPU time 8.6 seconds
Started Aug 10 05:37:11 PM PDT 24
Finished Aug 10 05:37:20 PM PDT 24
Peak memory 212160 kb
Host smart-c16451f0-6a4f-4ec2-a766-26cfe3520430
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579549789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3579549789
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2198934377
Short name T316
Test name
Test status
Simulation time 518739251 ps
CPU time 5.25 seconds
Started Aug 10 05:37:15 PM PDT 24
Finished Aug 10 05:37:20 PM PDT 24
Peak memory 212028 kb
Host smart-22c6ff44-f809-4c8e-b45f-452d0aa1fe97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198934377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2198934377
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2827525518
Short name T186
Test name
Test status
Simulation time 162374769336 ps
CPU time 190.05 seconds
Started Aug 10 05:37:15 PM PDT 24
Finished Aug 10 05:40:25 PM PDT 24
Peak memory 241520 kb
Host smart-5477152b-6358-4662-b0b5-056d307d2e91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827525518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2827525518
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2175905301
Short name T240
Test name
Test status
Simulation time 799766546 ps
CPU time 9.46 seconds
Started Aug 10 05:37:15 PM PDT 24
Finished Aug 10 05:37:25 PM PDT 24
Peak memory 212912 kb
Host smart-1aa12150-59d3-4a87-bed2-1b0794e17b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175905301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2175905301
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3343019526
Short name T137
Test name
Test status
Simulation time 378984486 ps
CPU time 5.33 seconds
Started Aug 10 05:37:18 PM PDT 24
Finished Aug 10 05:37:23 PM PDT 24
Peak memory 212188 kb
Host smart-ed1c6a21-dc9d-442a-8018-71be6032ec29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3343019526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3343019526
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.952369304
Short name T40
Test name
Test status
Simulation time 110516482 ps
CPU time 10.32 seconds
Started Aug 10 05:37:12 PM PDT 24
Finished Aug 10 05:37:23 PM PDT 24
Peak memory 212124 kb
Host smart-af7314ad-2d35-49bc-b084-63ac68c1d333
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952369304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.952369304
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.427329877
Short name T298
Test name
Test status
Simulation time 204952922 ps
CPU time 4.27 seconds
Started Aug 10 05:37:20 PM PDT 24
Finished Aug 10 05:37:24 PM PDT 24
Peak memory 212096 kb
Host smart-cc607172-c2b2-4979-99ec-6ad292bfc8b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427329877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.427329877
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.230415030
Short name T303
Test name
Test status
Simulation time 1723675783 ps
CPU time 119.89 seconds
Started Aug 10 05:37:18 PM PDT 24
Finished Aug 10 05:39:18 PM PDT 24
Peak memory 238256 kb
Host smart-23550701-f8f9-4276-8de4-040bc78fca7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230415030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.230415030
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3094871722
Short name T134
Test name
Test status
Simulation time 3102574344 ps
CPU time 11.47 seconds
Started Aug 10 05:37:15 PM PDT 24
Finished Aug 10 05:37:27 PM PDT 24
Peak memory 213052 kb
Host smart-e6b7b82a-86fa-4c3f-8793-b052cc8d60b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094871722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3094871722
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2999685441
Short name T249
Test name
Test status
Simulation time 292480513 ps
CPU time 6.68 seconds
Started Aug 10 05:37:15 PM PDT 24
Finished Aug 10 05:37:22 PM PDT 24
Peak memory 212136 kb
Host smart-f52b0e9a-0bc2-4891-a7c2-6e331d4835b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2999685441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2999685441
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1630082057
Short name T244
Test name
Test status
Simulation time 772229033 ps
CPU time 11.69 seconds
Started Aug 10 05:37:15 PM PDT 24
Finished Aug 10 05:37:26 PM PDT 24
Peak memory 214768 kb
Host smart-6c64047e-580e-4a51-92a4-b870dbb96e18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630082057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1630082057
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2353388673
Short name T51
Test name
Test status
Simulation time 145410942056 ps
CPU time 1564.73 seconds
Started Aug 10 05:37:16 PM PDT 24
Finished Aug 10 06:03:21 PM PDT 24
Peak memory 237456 kb
Host smart-437aa952-d7e8-4c62-91c2-f5045606f374
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353388673 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.2353388673
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2161251249
Short name T239
Test name
Test status
Simulation time 333864818 ps
CPU time 4.24 seconds
Started Aug 10 05:36:36 PM PDT 24
Finished Aug 10 05:36:40 PM PDT 24
Peak memory 212072 kb
Host smart-8a9c231d-a8b3-4885-85fb-c01acc31bb71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161251249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2161251249
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.544135557
Short name T38
Test name
Test status
Simulation time 3458055673 ps
CPU time 178.31 seconds
Started Aug 10 05:36:33 PM PDT 24
Finished Aug 10 05:39:32 PM PDT 24
Peak memory 235788 kb
Host smart-6c885b7b-3ca7-4f50-8087-589f604033bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544135557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.544135557
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2773319124
Short name T270
Test name
Test status
Simulation time 1037561827 ps
CPU time 11.32 seconds
Started Aug 10 05:36:34 PM PDT 24
Finished Aug 10 05:36:45 PM PDT 24
Peak memory 212860 kb
Host smart-a51c18ac-b6eb-4d92-b97e-5b069b346c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773319124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2773319124
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3149982604
Short name T166
Test name
Test status
Simulation time 282407065 ps
CPU time 6.89 seconds
Started Aug 10 05:36:38 PM PDT 24
Finished Aug 10 05:36:45 PM PDT 24
Peak memory 212124 kb
Host smart-1b62617f-86d1-4ee1-8985-eddc520a112a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3149982604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3149982604
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3405097595
Short name T20
Test name
Test status
Simulation time 162806654 ps
CPU time 51.91 seconds
Started Aug 10 05:36:35 PM PDT 24
Finished Aug 10 05:37:27 PM PDT 24
Peak memory 237368 kb
Host smart-d06c0184-9a19-486f-be7a-962b5040fe28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405097595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3405097595
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3484286021
Short name T165
Test name
Test status
Simulation time 527158065 ps
CPU time 6.43 seconds
Started Aug 10 05:36:33 PM PDT 24
Finished Aug 10 05:36:40 PM PDT 24
Peak memory 212184 kb
Host smart-dfc91ecf-30d7-4c11-85ad-ccb69c48b6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484286021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3484286021
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2417866226
Short name T293
Test name
Test status
Simulation time 286453738 ps
CPU time 12.19 seconds
Started Aug 10 05:36:34 PM PDT 24
Finished Aug 10 05:36:46 PM PDT 24
Peak memory 214520 kb
Host smart-10d6af2e-de64-4068-a84a-c6890bed3ed1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417866226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2417866226
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.929668756
Short name T173
Test name
Test status
Simulation time 2422601780 ps
CPU time 138.02 seconds
Started Aug 10 05:37:17 PM PDT 24
Finished Aug 10 05:39:35 PM PDT 24
Peak memory 225820 kb
Host smart-864a14de-a500-4b1e-934d-0288e4a4103d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929668756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.929668756
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1550690065
Short name T41
Test name
Test status
Simulation time 252117888 ps
CPU time 11.31 seconds
Started Aug 10 05:37:18 PM PDT 24
Finished Aug 10 05:37:30 PM PDT 24
Peak memory 213004 kb
Host smart-b67807d2-cd09-4481-8cd5-24953cfa2ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550690065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1550690065
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3980530589
Short name T269
Test name
Test status
Simulation time 1463289494 ps
CPU time 6.82 seconds
Started Aug 10 05:37:17 PM PDT 24
Finished Aug 10 05:37:24 PM PDT 24
Peak memory 212100 kb
Host smart-024715ad-3909-48ee-82d8-d02f35085af7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3980530589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3980530589
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3268606648
Short name T153
Test name
Test status
Simulation time 129594111 ps
CPU time 5.1 seconds
Started Aug 10 05:37:20 PM PDT 24
Finished Aug 10 05:37:25 PM PDT 24
Peak memory 212096 kb
Host smart-b1d4487c-0d5e-4c07-b246-afafca3a9772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268606648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3268606648
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.408221155
Short name T144
Test name
Test status
Simulation time 5649766294 ps
CPU time 140 seconds
Started Aug 10 05:37:16 PM PDT 24
Finished Aug 10 05:39:36 PM PDT 24
Peak memory 235588 kb
Host smart-1a2ca41e-c674-4b35-b1e1-2b88624e3620
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408221155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.408221155
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2808564876
Short name T279
Test name
Test status
Simulation time 928321505 ps
CPU time 9.7 seconds
Started Aug 10 05:37:16 PM PDT 24
Finished Aug 10 05:37:25 PM PDT 24
Peak memory 212888 kb
Host smart-781a2c1e-ba9e-48aa-977f-ade3b7c90419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808564876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2808564876
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.96435822
Short name T17
Test name
Test status
Simulation time 334648407 ps
CPU time 5.89 seconds
Started Aug 10 05:37:16 PM PDT 24
Finished Aug 10 05:37:22 PM PDT 24
Peak memory 212176 kb
Host smart-e953c022-2064-4649-9e24-7c99bca82ad8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96435822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.96435822
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1940640996
Short name T159
Test name
Test status
Simulation time 305370439 ps
CPU time 19.04 seconds
Started Aug 10 05:37:20 PM PDT 24
Finished Aug 10 05:37:39 PM PDT 24
Peak memory 216172 kb
Host smart-f811ef03-d4e4-49a5-a5be-958a99697f5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940640996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1940640996
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1198483992
Short name T238
Test name
Test status
Simulation time 2048103059 ps
CPU time 7.56 seconds
Started Aug 10 05:37:27 PM PDT 24
Finished Aug 10 05:37:35 PM PDT 24
Peak memory 212040 kb
Host smart-4275cb2c-5354-4c44-83df-f8ac1f8f06db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198483992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1198483992
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2463931539
Short name T146
Test name
Test status
Simulation time 3708404527 ps
CPU time 66.72 seconds
Started Aug 10 05:37:18 PM PDT 24
Finished Aug 10 05:38:25 PM PDT 24
Peak memory 240404 kb
Host smart-15f03592-b114-4cdf-9ef7-585ef4096bbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463931539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2463931539
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.587831786
Short name T141
Test name
Test status
Simulation time 439946089 ps
CPU time 9.54 seconds
Started Aug 10 05:37:23 PM PDT 24
Finished Aug 10 05:37:32 PM PDT 24
Peak memory 212900 kb
Host smart-ed3f9d96-c4fe-4323-adc5-cb40cef9b6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587831786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.587831786
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1393649580
Short name T230
Test name
Test status
Simulation time 1911450825 ps
CPU time 6.56 seconds
Started Aug 10 05:37:16 PM PDT 24
Finished Aug 10 05:37:23 PM PDT 24
Peak memory 212260 kb
Host smart-468ac743-3506-4c11-946c-71e2e93f455d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1393649580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1393649580
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.4125644904
Short name T211
Test name
Test status
Simulation time 19119721195 ps
CPU time 29.95 seconds
Started Aug 10 05:37:16 PM PDT 24
Finished Aug 10 05:37:46 PM PDT 24
Peak memory 218068 kb
Host smart-8753a780-6576-4297-bcdc-793cdc895bb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125644904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.4125644904
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1842804067
Short name T315
Test name
Test status
Simulation time 126389975 ps
CPU time 5.15 seconds
Started Aug 10 05:37:23 PM PDT 24
Finished Aug 10 05:37:28 PM PDT 24
Peak memory 212092 kb
Host smart-219abf3e-1e40-4fd6-8a68-42d7b204739a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842804067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1842804067
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.691012949
Short name T207
Test name
Test status
Simulation time 1388043569 ps
CPU time 45.75 seconds
Started Aug 10 05:37:23 PM PDT 24
Finished Aug 10 05:38:09 PM PDT 24
Peak memory 212380 kb
Host smart-040e01db-79d7-4337-9385-d2003a408922
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691012949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.691012949
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.18070783
Short name T312
Test name
Test status
Simulation time 998422643 ps
CPU time 10.93 seconds
Started Aug 10 05:37:24 PM PDT 24
Finished Aug 10 05:37:35 PM PDT 24
Peak memory 212976 kb
Host smart-7210ff1b-ff84-4ea7-82a3-5c65c5e8b56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18070783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.18070783
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2191534472
Short name T140
Test name
Test status
Simulation time 495497705 ps
CPU time 6.51 seconds
Started Aug 10 05:37:22 PM PDT 24
Finished Aug 10 05:37:29 PM PDT 24
Peak memory 212124 kb
Host smart-476cd7f3-7fba-4020-ba81-89cbac16f995
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2191534472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2191534472
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.388891885
Short name T13
Test name
Test status
Simulation time 314142767 ps
CPU time 14.18 seconds
Started Aug 10 05:37:23 PM PDT 24
Finished Aug 10 05:37:37 PM PDT 24
Peak memory 214548 kb
Host smart-5259337b-4f3c-4a4a-8e83-21fc580e4726
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388891885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.388891885
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4133242179
Short name T143
Test name
Test status
Simulation time 132313918 ps
CPU time 5.21 seconds
Started Aug 10 05:37:24 PM PDT 24
Finished Aug 10 05:37:30 PM PDT 24
Peak memory 212044 kb
Host smart-60fbc46a-9e75-49a7-8d29-469630c32e55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133242179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4133242179
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.4275259725
Short name T256
Test name
Test status
Simulation time 3437309762 ps
CPU time 110.14 seconds
Started Aug 10 05:37:23 PM PDT 24
Finished Aug 10 05:39:13 PM PDT 24
Peak memory 238576 kb
Host smart-01b23e5d-b98a-4663-8a3a-429bca632357
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275259725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.4275259725
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.981129071
Short name T243
Test name
Test status
Simulation time 797693770 ps
CPU time 9.49 seconds
Started Aug 10 05:37:23 PM PDT 24
Finished Aug 10 05:37:33 PM PDT 24
Peak memory 213068 kb
Host smart-42aba05c-a309-405f-84db-d705eff787ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981129071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.981129071
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2320984092
Short name T213
Test name
Test status
Simulation time 455571472 ps
CPU time 6.78 seconds
Started Aug 10 05:37:22 PM PDT 24
Finished Aug 10 05:37:29 PM PDT 24
Peak memory 212064 kb
Host smart-7a162a9e-a78b-4c37-921c-744679a5d692
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2320984092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2320984092
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3967222815
Short name T69
Test name
Test status
Simulation time 2410689466 ps
CPU time 27.01 seconds
Started Aug 10 05:37:26 PM PDT 24
Finished Aug 10 05:37:53 PM PDT 24
Peak memory 215076 kb
Host smart-30e38c5b-ff10-4033-9a07-5b229ef92f97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967222815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3967222815
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2380246326
Short name T104
Test name
Test status
Simulation time 31174189154 ps
CPU time 602.39 seconds
Started Aug 10 05:37:24 PM PDT 24
Finished Aug 10 05:47:26 PM PDT 24
Peak memory 229456 kb
Host smart-913834d6-c92b-42fa-a9e7-1178b22fabb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380246326 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2380246326
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.4293513153
Short name T60
Test name
Test status
Simulation time 126347624 ps
CPU time 5.27 seconds
Started Aug 10 05:37:31 PM PDT 24
Finished Aug 10 05:37:37 PM PDT 24
Peak memory 212064 kb
Host smart-61bd5044-892f-4109-8597-06b459095d62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293513153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.4293513153
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1988104623
Short name T36
Test name
Test status
Simulation time 2273782141 ps
CPU time 145.66 seconds
Started Aug 10 05:37:31 PM PDT 24
Finished Aug 10 05:39:57 PM PDT 24
Peak memory 238460 kb
Host smart-9bf8501b-bf64-4549-94c3-a7da1719452b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988104623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1988104623
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.387315626
Short name T321
Test name
Test status
Simulation time 4110739542 ps
CPU time 16.6 seconds
Started Aug 10 05:37:32 PM PDT 24
Finished Aug 10 05:37:49 PM PDT 24
Peak memory 212920 kb
Host smart-8b1fe3d8-4527-459a-9ba0-0ccd72005e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387315626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.387315626
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.247167705
Short name T284
Test name
Test status
Simulation time 1014003015 ps
CPU time 6.13 seconds
Started Aug 10 05:37:22 PM PDT 24
Finished Aug 10 05:37:28 PM PDT 24
Peak memory 212188 kb
Host smart-d67b6809-0583-4871-b9e5-7637c0ed9f64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=247167705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.247167705
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1048467771
Short name T224
Test name
Test status
Simulation time 571766421 ps
CPU time 14.53 seconds
Started Aug 10 05:37:25 PM PDT 24
Finished Aug 10 05:37:40 PM PDT 24
Peak memory 215584 kb
Host smart-c9b117ad-474d-4311-8b27-18d035ea613f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048467771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1048467771
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2071453807
Short name T174
Test name
Test status
Simulation time 381923120 ps
CPU time 4.23 seconds
Started Aug 10 05:37:35 PM PDT 24
Finished Aug 10 05:37:39 PM PDT 24
Peak memory 212108 kb
Host smart-0baec6b1-cd72-48f8-9a25-9ed6849882cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071453807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2071453807
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3485376474
Short name T188
Test name
Test status
Simulation time 3283295011 ps
CPU time 103.22 seconds
Started Aug 10 05:37:30 PM PDT 24
Finished Aug 10 05:39:14 PM PDT 24
Peak memory 237396 kb
Host smart-ad1cac34-7792-4207-ae9c-f0dd5df9fd31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485376474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3485376474
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.148739870
Short name T309
Test name
Test status
Simulation time 4283221507 ps
CPU time 16.3 seconds
Started Aug 10 05:37:33 PM PDT 24
Finished Aug 10 05:37:49 PM PDT 24
Peak memory 213228 kb
Host smart-22452787-60ca-4df8-9849-452128729289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148739870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.148739870
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1018070320
Short name T323
Test name
Test status
Simulation time 102611089 ps
CPU time 5.78 seconds
Started Aug 10 05:37:31 PM PDT 24
Finished Aug 10 05:37:37 PM PDT 24
Peak memory 212212 kb
Host smart-30329e47-9931-45ff-b6ec-606f1741dafc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1018070320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1018070320
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.4017219635
Short name T3
Test name
Test status
Simulation time 525568238 ps
CPU time 17.78 seconds
Started Aug 10 05:37:31 PM PDT 24
Finished Aug 10 05:37:49 PM PDT 24
Peak memory 215296 kb
Host smart-50400fcc-2f8b-458b-b581-6705ff2f751b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017219635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.4017219635
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1517080820
Short name T135
Test name
Test status
Simulation time 86125889 ps
CPU time 4.34 seconds
Started Aug 10 05:37:31 PM PDT 24
Finished Aug 10 05:37:36 PM PDT 24
Peak memory 212068 kb
Host smart-e5b6d55f-3d40-4fa5-84db-c1781d11720d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517080820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1517080820
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1358153759
Short name T325
Test name
Test status
Simulation time 2109393225 ps
CPU time 133.62 seconds
Started Aug 10 05:37:31 PM PDT 24
Finished Aug 10 05:39:45 PM PDT 24
Peak memory 228988 kb
Host smart-9eba32b0-b8c6-4f7b-b2f1-75cfd27b8dd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358153759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1358153759
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3119665549
Short name T121
Test name
Test status
Simulation time 1380311484 ps
CPU time 11.43 seconds
Started Aug 10 05:37:31 PM PDT 24
Finished Aug 10 05:37:42 PM PDT 24
Peak memory 212876 kb
Host smart-5f9e8942-c2d3-4b01-b6c0-4babbd6f9368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119665549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3119665549
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2949569090
Short name T210
Test name
Test status
Simulation time 1499135317 ps
CPU time 5.28 seconds
Started Aug 10 05:37:32 PM PDT 24
Finished Aug 10 05:37:38 PM PDT 24
Peak memory 212160 kb
Host smart-56f3cc25-d25f-451e-8d4c-1f1ee67b552d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2949569090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2949569090
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1789045260
Short name T71
Test name
Test status
Simulation time 793595646 ps
CPU time 15.59 seconds
Started Aug 10 05:37:31 PM PDT 24
Finished Aug 10 05:37:47 PM PDT 24
Peak memory 214236 kb
Host smart-4d2b3070-bd1e-4565-9ce6-aa54e9ea3168
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789045260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1789045260
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1428649972
Short name T5
Test name
Test status
Simulation time 553238346 ps
CPU time 4.32 seconds
Started Aug 10 05:37:32 PM PDT 24
Finished Aug 10 05:37:37 PM PDT 24
Peak memory 212084 kb
Host smart-bbfbe7a7-6683-42d5-8425-dc5a93e9fcfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428649972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1428649972
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3429265420
Short name T251
Test name
Test status
Simulation time 2604105728 ps
CPU time 123.5 seconds
Started Aug 10 05:37:30 PM PDT 24
Finished Aug 10 05:39:34 PM PDT 24
Peak memory 225876 kb
Host smart-1abdbd71-f02f-48c0-9e15-50c1070596de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429265420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3429265420
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.279454380
Short name T152
Test name
Test status
Simulation time 415012749 ps
CPU time 11.29 seconds
Started Aug 10 05:37:31 PM PDT 24
Finished Aug 10 05:37:42 PM PDT 24
Peak memory 213088 kb
Host smart-9a1acb74-3391-423c-bd9f-99e5e7e4bd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279454380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.279454380
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2724480522
Short name T319
Test name
Test status
Simulation time 365397463 ps
CPU time 5.58 seconds
Started Aug 10 05:37:31 PM PDT 24
Finished Aug 10 05:37:37 PM PDT 24
Peak memory 212120 kb
Host smart-ef9ede9b-6ef5-451e-abb4-d26fadf69437
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2724480522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2724480522
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.322709156
Short name T288
Test name
Test status
Simulation time 4432728949 ps
CPU time 23.35 seconds
Started Aug 10 05:37:30 PM PDT 24
Finished Aug 10 05:37:53 PM PDT 24
Peak memory 218068 kb
Host smart-1ae20ab1-652b-44c6-8729-d47148995b8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322709156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.322709156
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1288077223
Short name T49
Test name
Test status
Simulation time 7578962800 ps
CPU time 318.5 seconds
Started Aug 10 05:37:34 PM PDT 24
Finished Aug 10 05:42:53 PM PDT 24
Peak memory 220284 kb
Host smart-0853b190-22d6-428c-ab7c-bac004a14277
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288077223 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1288077223
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1530427523
Short name T275
Test name
Test status
Simulation time 86221669 ps
CPU time 4.84 seconds
Started Aug 10 05:37:37 PM PDT 24
Finished Aug 10 05:37:41 PM PDT 24
Peak memory 212028 kb
Host smart-03b5f25d-ec29-485e-ac24-474e203a09b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530427523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1530427523
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1620973082
Short name T195
Test name
Test status
Simulation time 6943331503 ps
CPU time 87.83 seconds
Started Aug 10 05:37:35 PM PDT 24
Finished Aug 10 05:39:03 PM PDT 24
Peak memory 238276 kb
Host smart-b15db361-0233-4e22-930f-65b0df9f281b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620973082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1620973082
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1834910674
Short name T292
Test name
Test status
Simulation time 1038742119 ps
CPU time 9.36 seconds
Started Aug 10 05:37:33 PM PDT 24
Finished Aug 10 05:37:42 PM PDT 24
Peak memory 212960 kb
Host smart-b7f66352-9c7c-4e32-b83a-e21f92bd9e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834910674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1834910674
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.348500738
Short name T99
Test name
Test status
Simulation time 2637416164 ps
CPU time 6.58 seconds
Started Aug 10 05:37:31 PM PDT 24
Finished Aug 10 05:37:38 PM PDT 24
Peak memory 212296 kb
Host smart-276fe830-1027-4122-abf9-826d3c81d15e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=348500738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.348500738
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2168756549
Short name T307
Test name
Test status
Simulation time 368973912 ps
CPU time 11.35 seconds
Started Aug 10 05:37:32 PM PDT 24
Finished Aug 10 05:37:43 PM PDT 24
Peak memory 214488 kb
Host smart-174dae68-e91a-43fe-9ec2-6a7da77a41f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168756549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2168756549
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.950720343
Short name T181
Test name
Test status
Simulation time 2064742299 ps
CPU time 7.84 seconds
Started Aug 10 05:36:33 PM PDT 24
Finished Aug 10 05:36:41 PM PDT 24
Peak memory 212096 kb
Host smart-380646c7-3a45-4d05-b44a-1d98c03226f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950720343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.950720343
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.350725525
Short name T35
Test name
Test status
Simulation time 4856935230 ps
CPU time 128.57 seconds
Started Aug 10 05:36:32 PM PDT 24
Finished Aug 10 05:38:41 PM PDT 24
Peak memory 226364 kb
Host smart-d5973188-0644-4e07-9716-f5b60f639027
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350725525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.350725525
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.4291655831
Short name T202
Test name
Test status
Simulation time 506316678 ps
CPU time 9.57 seconds
Started Aug 10 05:36:33 PM PDT 24
Finished Aug 10 05:36:42 PM PDT 24
Peak memory 213336 kb
Host smart-f658f3ee-59b0-4c87-9304-357e8c400f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291655831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.4291655831
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3966467476
Short name T302
Test name
Test status
Simulation time 142464315 ps
CPU time 6.43 seconds
Started Aug 10 05:36:35 PM PDT 24
Finished Aug 10 05:36:41 PM PDT 24
Peak memory 212172 kb
Host smart-4213acdc-a3f6-42df-bc95-9c4ef9e6947b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3966467476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3966467476
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.833137199
Short name T22
Test name
Test status
Simulation time 354485279 ps
CPU time 53.02 seconds
Started Aug 10 05:36:33 PM PDT 24
Finished Aug 10 05:37:26 PM PDT 24
Peak memory 237412 kb
Host smart-141bd313-44c2-4ad7-83ec-2d200f98d400
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833137199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.833137199
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.461066754
Short name T72
Test name
Test status
Simulation time 548855086 ps
CPU time 6.36 seconds
Started Aug 10 05:36:38 PM PDT 24
Finished Aug 10 05:36:44 PM PDT 24
Peak memory 212220 kb
Host smart-4caec27f-4ac1-4bb2-bd84-01dc79e6d069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461066754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.461066754
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3404531831
Short name T206
Test name
Test status
Simulation time 424936983 ps
CPU time 18.89 seconds
Started Aug 10 05:36:34 PM PDT 24
Finished Aug 10 05:36:53 PM PDT 24
Peak memory 216136 kb
Host smart-71bdaded-beb3-409b-b11e-efeed2a8bf15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404531831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3404531831
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.4106357965
Short name T44
Test name
Test status
Simulation time 463227653 ps
CPU time 5.24 seconds
Started Aug 10 05:37:38 PM PDT 24
Finished Aug 10 05:37:43 PM PDT 24
Peak memory 212100 kb
Host smart-02c6e75b-3a2d-4cb6-895e-f95d8e8dd0bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106357965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.4106357965
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4049435514
Short name T280
Test name
Test status
Simulation time 3601215762 ps
CPU time 92.92 seconds
Started Aug 10 05:37:37 PM PDT 24
Finished Aug 10 05:39:10 PM PDT 24
Peak memory 238500 kb
Host smart-748a1e46-9585-48f3-afe6-5965c9107472
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049435514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4049435514
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2191834551
Short name T241
Test name
Test status
Simulation time 710640513 ps
CPU time 11.39 seconds
Started Aug 10 05:37:40 PM PDT 24
Finished Aug 10 05:37:51 PM PDT 24
Peak memory 212904 kb
Host smart-5409c64c-7ed3-4e67-b228-e1153f102aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191834551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2191834551
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.809279129
Short name T192
Test name
Test status
Simulation time 539536594 ps
CPU time 6.5 seconds
Started Aug 10 05:37:39 PM PDT 24
Finished Aug 10 05:37:46 PM PDT 24
Peak memory 212152 kb
Host smart-da720375-3695-4b93-990a-a750ba71d6de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=809279129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.809279129
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2900117128
Short name T176
Test name
Test status
Simulation time 436910089 ps
CPU time 20.16 seconds
Started Aug 10 05:37:39 PM PDT 24
Finished Aug 10 05:38:00 PM PDT 24
Peak memory 216464 kb
Host smart-27af3eb6-92e0-4bcf-ac68-a94d71118668
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900117128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2900117128
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2937836250
Short name T266
Test name
Test status
Simulation time 146543917684 ps
CPU time 1643.72 seconds
Started Aug 10 05:37:43 PM PDT 24
Finished Aug 10 06:05:07 PM PDT 24
Peak memory 237324 kb
Host smart-ce664ba9-e942-47a7-9ff8-de1ad8c838c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937836250 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.2937836250
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2584605920
Short name T129
Test name
Test status
Simulation time 518148039 ps
CPU time 5.08 seconds
Started Aug 10 05:37:39 PM PDT 24
Finished Aug 10 05:37:45 PM PDT 24
Peak memory 212020 kb
Host smart-c1716244-a74f-4840-9c82-99394186275b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584605920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2584605920
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2315127597
Short name T34
Test name
Test status
Simulation time 13509467352 ps
CPU time 164.34 seconds
Started Aug 10 05:37:39 PM PDT 24
Finished Aug 10 05:40:23 PM PDT 24
Peak memory 228940 kb
Host smart-37c2804f-021d-4ee8-813d-7edc084ded59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315127597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2315127597
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2426108520
Short name T253
Test name
Test status
Simulation time 691813972 ps
CPU time 9.47 seconds
Started Aug 10 05:37:42 PM PDT 24
Finished Aug 10 05:37:52 PM PDT 24
Peak memory 212932 kb
Host smart-520268de-fdda-47c7-9687-fa84335511ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426108520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2426108520
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.58315825
Short name T175
Test name
Test status
Simulation time 142133474 ps
CPU time 6.17 seconds
Started Aug 10 05:37:37 PM PDT 24
Finished Aug 10 05:37:43 PM PDT 24
Peak memory 212156 kb
Host smart-8e6114d7-d4b6-466d-983b-c1695c6ddeb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58315825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.58315825
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3002062175
Short name T178
Test name
Test status
Simulation time 1078669631 ps
CPU time 13.89 seconds
Started Aug 10 05:37:36 PM PDT 24
Finished Aug 10 05:37:50 PM PDT 24
Peak memory 215496 kb
Host smart-a36cb2c6-ec3b-4c8b-b427-71a5578efd0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002062175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3002062175
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2321181058
Short name T7
Test name
Test status
Simulation time 131319282 ps
CPU time 5.12 seconds
Started Aug 10 05:37:43 PM PDT 24
Finished Aug 10 05:37:48 PM PDT 24
Peak memory 212080 kb
Host smart-e12e8558-6283-4929-bf33-723f51a304bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321181058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2321181058
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.221780866
Short name T11
Test name
Test status
Simulation time 7490101544 ps
CPU time 104.83 seconds
Started Aug 10 05:37:36 PM PDT 24
Finished Aug 10 05:39:21 PM PDT 24
Peak memory 237480 kb
Host smart-6dd81f72-d49b-4abe-9b14-6a23ec1ccab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221780866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.221780866
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.4178599271
Short name T215
Test name
Test status
Simulation time 255082464 ps
CPU time 11.23 seconds
Started Aug 10 05:37:37 PM PDT 24
Finished Aug 10 05:37:48 PM PDT 24
Peak memory 212964 kb
Host smart-774c5e17-c38c-4941-9e52-858df7a7c6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178599271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.4178599271
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3582949325
Short name T161
Test name
Test status
Simulation time 396279870 ps
CPU time 5.63 seconds
Started Aug 10 05:37:42 PM PDT 24
Finished Aug 10 05:37:48 PM PDT 24
Peak memory 212212 kb
Host smart-fcc1ed45-33e1-445b-bfec-cacf2dc98f3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3582949325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3582949325
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2998577962
Short name T234
Test name
Test status
Simulation time 270914707 ps
CPU time 13.21 seconds
Started Aug 10 05:37:42 PM PDT 24
Finished Aug 10 05:37:56 PM PDT 24
Peak memory 212732 kb
Host smart-3e8ace37-d940-4311-8832-08da1771ee57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998577962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2998577962
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.505460180
Short name T145
Test name
Test status
Simulation time 332909859 ps
CPU time 4.21 seconds
Started Aug 10 05:37:43 PM PDT 24
Finished Aug 10 05:37:47 PM PDT 24
Peak memory 212048 kb
Host smart-bdbbd6a1-b23a-494f-9949-35af20efe4d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505460180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.505460180
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3128658832
Short name T214
Test name
Test status
Simulation time 7169617985 ps
CPU time 96.03 seconds
Started Aug 10 05:37:37 PM PDT 24
Finished Aug 10 05:39:14 PM PDT 24
Peak memory 233508 kb
Host smart-2adf138f-a6e2-46a3-acc3-4860a9aada5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128658832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3128658832
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.931496312
Short name T29
Test name
Test status
Simulation time 259950220 ps
CPU time 11.22 seconds
Started Aug 10 05:37:38 PM PDT 24
Finished Aug 10 05:37:49 PM PDT 24
Peak memory 212900 kb
Host smart-a0c9f307-2e35-42a6-9d23-4d9ebda3cff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931496312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.931496312
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2465346074
Short name T310
Test name
Test status
Simulation time 94941835 ps
CPU time 5.55 seconds
Started Aug 10 05:37:37 PM PDT 24
Finished Aug 10 05:37:42 PM PDT 24
Peak memory 212112 kb
Host smart-636fc243-3501-495c-9c20-0d558ed7b2c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2465346074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2465346074
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3184767972
Short name T232
Test name
Test status
Simulation time 838520265 ps
CPU time 19.12 seconds
Started Aug 10 05:37:37 PM PDT 24
Finished Aug 10 05:37:56 PM PDT 24
Peak memory 215120 kb
Host smart-fb3c70d7-768e-454b-a5f4-f6205e7471d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184767972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3184767972
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3667781542
Short name T247
Test name
Test status
Simulation time 519031061 ps
CPU time 5.09 seconds
Started Aug 10 05:37:44 PM PDT 24
Finished Aug 10 05:37:49 PM PDT 24
Peak memory 212036 kb
Host smart-76ff727c-96c0-44ed-9b69-b633273472c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667781542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3667781542
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1092323647
Short name T130
Test name
Test status
Simulation time 2222077193 ps
CPU time 102.06 seconds
Started Aug 10 05:37:46 PM PDT 24
Finished Aug 10 05:39:29 PM PDT 24
Peak memory 229060 kb
Host smart-8b80e335-0e03-4294-8b0d-b58436a49dc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092323647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1092323647
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2163067081
Short name T95
Test name
Test status
Simulation time 528589915 ps
CPU time 8.95 seconds
Started Aug 10 05:37:44 PM PDT 24
Finished Aug 10 05:37:53 PM PDT 24
Peak memory 212180 kb
Host smart-384168d9-2fcc-40ad-8d33-95c9839ab883
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2163067081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2163067081
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3510592209
Short name T154
Test name
Test status
Simulation time 813568818 ps
CPU time 13.98 seconds
Started Aug 10 05:37:37 PM PDT 24
Finished Aug 10 05:37:51 PM PDT 24
Peak memory 213716 kb
Host smart-cecac0cd-0873-41ab-b319-7f2a31f19f16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510592209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3510592209
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3211914444
Short name T133
Test name
Test status
Simulation time 543074757 ps
CPU time 5.13 seconds
Started Aug 10 05:37:47 PM PDT 24
Finished Aug 10 05:37:52 PM PDT 24
Peak memory 212104 kb
Host smart-64628456-c945-4667-bcdf-1084ab506bac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211914444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3211914444
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.602588661
Short name T155
Test name
Test status
Simulation time 1383077637 ps
CPU time 77.34 seconds
Started Aug 10 05:37:44 PM PDT 24
Finished Aug 10 05:39:02 PM PDT 24
Peak memory 213376 kb
Host smart-db49eaae-2c10-4292-b447-4ddcc24d6e8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602588661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.602588661
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.352340332
Short name T120
Test name
Test status
Simulation time 251519916 ps
CPU time 11.08 seconds
Started Aug 10 05:37:46 PM PDT 24
Finished Aug 10 05:37:57 PM PDT 24
Peak memory 212848 kb
Host smart-de742a5f-9a92-4218-ac8a-561418fa1307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352340332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.352340332
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2223754428
Short name T322
Test name
Test status
Simulation time 136304158 ps
CPU time 6.1 seconds
Started Aug 10 05:37:45 PM PDT 24
Finished Aug 10 05:37:51 PM PDT 24
Peak memory 212160 kb
Host smart-2174fb2a-4d9c-4b7c-8025-4669b2f05dc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223754428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2223754428
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.830272017
Short name T168
Test name
Test status
Simulation time 472914604 ps
CPU time 6.14 seconds
Started Aug 10 05:37:45 PM PDT 24
Finished Aug 10 05:37:51 PM PDT 24
Peak memory 212136 kb
Host smart-130c3d9d-6129-40ba-adc9-179926551639
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830272017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.830272017
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.528885629
Short name T268
Test name
Test status
Simulation time 288893079 ps
CPU time 4.27 seconds
Started Aug 10 05:37:46 PM PDT 24
Finished Aug 10 05:37:51 PM PDT 24
Peak memory 212104 kb
Host smart-39880e0f-898d-4f26-9fcd-fe3be608af34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528885629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.528885629
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1518083305
Short name T37
Test name
Test status
Simulation time 2391077740 ps
CPU time 150.44 seconds
Started Aug 10 05:37:47 PM PDT 24
Finished Aug 10 05:40:17 PM PDT 24
Peak memory 238096 kb
Host smart-4bc8bdee-0c42-4966-bef3-3ac1bb0e7f07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518083305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1518083305
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1972619704
Short name T9
Test name
Test status
Simulation time 500063649 ps
CPU time 11.27 seconds
Started Aug 10 05:37:45 PM PDT 24
Finished Aug 10 05:37:56 PM PDT 24
Peak memory 213020 kb
Host smart-25abfb25-f8a2-418e-bb10-faf00eea2135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972619704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1972619704
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2982009068
Short name T209
Test name
Test status
Simulation time 390924999 ps
CPU time 5.41 seconds
Started Aug 10 05:37:45 PM PDT 24
Finished Aug 10 05:37:50 PM PDT 24
Peak memory 212180 kb
Host smart-43bca6cb-1b92-400b-a9d6-341ed6eab1e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2982009068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2982009068
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.47703782
Short name T297
Test name
Test status
Simulation time 1211740475 ps
CPU time 15.27 seconds
Started Aug 10 05:37:44 PM PDT 24
Finished Aug 10 05:37:59 PM PDT 24
Peak memory 215324 kb
Host smart-f260b7ea-7656-404e-8db9-51133016f835
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47703782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 46.rom_ctrl_stress_all.47703782
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3897779992
Short name T170
Test name
Test status
Simulation time 348478349 ps
CPU time 4.36 seconds
Started Aug 10 05:37:45 PM PDT 24
Finished Aug 10 05:37:49 PM PDT 24
Peak memory 212028 kb
Host smart-549a5f48-3dcb-4c0a-9701-bdc7e905c82e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897779992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3897779992
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2166686353
Short name T218
Test name
Test status
Simulation time 1400835734 ps
CPU time 69.64 seconds
Started Aug 10 05:37:47 PM PDT 24
Finished Aug 10 05:38:57 PM PDT 24
Peak memory 227904 kb
Host smart-3fd2cd63-4548-407e-a343-7fd5bf2415dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166686353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2166686353
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.146616760
Short name T290
Test name
Test status
Simulation time 171916669 ps
CPU time 9.44 seconds
Started Aug 10 05:37:46 PM PDT 24
Finished Aug 10 05:37:56 PM PDT 24
Peak memory 213020 kb
Host smart-33b82fce-aea9-4e88-9fd1-a4f08523669a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146616760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.146616760
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3235892759
Short name T179
Test name
Test status
Simulation time 274285578 ps
CPU time 6.24 seconds
Started Aug 10 05:37:47 PM PDT 24
Finished Aug 10 05:37:54 PM PDT 24
Peak memory 212104 kb
Host smart-b1a1cbdd-6b0a-41ce-a8e7-5937810af603
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3235892759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3235892759
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.251334393
Short name T70
Test name
Test status
Simulation time 183796958 ps
CPU time 10.99 seconds
Started Aug 10 05:37:46 PM PDT 24
Finished Aug 10 05:37:57 PM PDT 24
Peak memory 212132 kb
Host smart-317ff50c-2805-4141-848f-eb70dbcf98da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251334393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.251334393
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2361009237
Short name T201
Test name
Test status
Simulation time 255538769 ps
CPU time 5.08 seconds
Started Aug 10 05:37:44 PM PDT 24
Finished Aug 10 05:37:49 PM PDT 24
Peak memory 211980 kb
Host smart-9a579a53-20b5-4d04-bc3a-202639df1ecd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361009237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2361009237
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1515651609
Short name T138
Test name
Test status
Simulation time 8612867154 ps
CPU time 215.3 seconds
Started Aug 10 05:37:47 PM PDT 24
Finished Aug 10 05:41:22 PM PDT 24
Peak memory 226392 kb
Host smart-cd0c3e1a-6cef-48b2-bd33-69d8b7f6dcf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515651609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1515651609
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2830101872
Short name T306
Test name
Test status
Simulation time 256374229 ps
CPU time 11.18 seconds
Started Aug 10 05:37:46 PM PDT 24
Finished Aug 10 05:37:57 PM PDT 24
Peak memory 213448 kb
Host smart-de1279ac-bfba-422f-941d-78f993afb227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830101872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2830101872
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2268295915
Short name T258
Test name
Test status
Simulation time 97145537 ps
CPU time 5.59 seconds
Started Aug 10 05:37:46 PM PDT 24
Finished Aug 10 05:37:52 PM PDT 24
Peak memory 212204 kb
Host smart-86a01098-406c-4a6b-903a-e30efe7f5cf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2268295915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2268295915
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2505858137
Short name T182
Test name
Test status
Simulation time 1192481979 ps
CPU time 13.73 seconds
Started Aug 10 05:37:45 PM PDT 24
Finished Aug 10 05:37:59 PM PDT 24
Peak memory 214580 kb
Host smart-8094346a-4da3-4c49-a584-91b0df25996d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505858137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2505858137
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3576168575
Short name T289
Test name
Test status
Simulation time 131889134 ps
CPU time 5.1 seconds
Started Aug 10 05:37:56 PM PDT 24
Finished Aug 10 05:38:01 PM PDT 24
Peak memory 212080 kb
Host smart-16c8fca4-1a75-49e7-8d1d-b93b408fc049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576168575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3576168575
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.295846663
Short name T200
Test name
Test status
Simulation time 7895401909 ps
CPU time 143.99 seconds
Started Aug 10 05:37:46 PM PDT 24
Finished Aug 10 05:40:10 PM PDT 24
Peak memory 234252 kb
Host smart-fd4f8c3a-fc10-46b4-a0e4-6578b86db517
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295846663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.295846663
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3446689353
Short name T205
Test name
Test status
Simulation time 262777138 ps
CPU time 11.4 seconds
Started Aug 10 05:37:54 PM PDT 24
Finished Aug 10 05:38:05 PM PDT 24
Peak memory 212128 kb
Host smart-aee3961f-1e03-4a91-971a-e6eeac63888e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446689353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3446689353
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1835147812
Short name T294
Test name
Test status
Simulation time 2023933866 ps
CPU time 8.71 seconds
Started Aug 10 05:37:47 PM PDT 24
Finished Aug 10 05:37:56 PM PDT 24
Peak memory 212188 kb
Host smart-2c5a21dc-a48e-44e6-b5ca-a8ee80d2774a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1835147812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1835147812
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.213971367
Short name T164
Test name
Test status
Simulation time 194625187 ps
CPU time 13.4 seconds
Started Aug 10 05:37:44 PM PDT 24
Finished Aug 10 05:37:58 PM PDT 24
Peak memory 214500 kb
Host smart-ba541951-b9b1-4743-8e2d-1649f9a792ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213971367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.213971367
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.4148402535
Short name T15
Test name
Test status
Simulation time 151043609701 ps
CPU time 6409.34 seconds
Started Aug 10 05:37:52 PM PDT 24
Finished Aug 10 07:24:42 PM PDT 24
Peak memory 271588 kb
Host smart-501faa71-9b82-4ec4-9e07-a8bcf68663f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148402535 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.4148402535
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.4166203747
Short name T257
Test name
Test status
Simulation time 361883989 ps
CPU time 4.2 seconds
Started Aug 10 05:36:42 PM PDT 24
Finished Aug 10 05:36:46 PM PDT 24
Peak memory 212096 kb
Host smart-860f4e23-1b89-4923-b94d-7c6408df907f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166203747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.4166203747
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2215886260
Short name T46
Test name
Test status
Simulation time 8971505128 ps
CPU time 104.5 seconds
Started Aug 10 05:36:43 PM PDT 24
Finished Aug 10 05:38:28 PM PDT 24
Peak memory 238540 kb
Host smart-bd81a3c3-eba4-42fd-ae06-18904f35c681
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215886260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2215886260
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1483888555
Short name T236
Test name
Test status
Simulation time 4170158937 ps
CPU time 11.37 seconds
Started Aug 10 05:36:45 PM PDT 24
Finished Aug 10 05:36:56 PM PDT 24
Peak memory 215444 kb
Host smart-28b55618-a657-459f-94d6-26f32f28ae77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483888555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1483888555
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.4106727171
Short name T156
Test name
Test status
Simulation time 275530871 ps
CPU time 6.65 seconds
Started Aug 10 05:36:43 PM PDT 24
Finished Aug 10 05:36:50 PM PDT 24
Peak memory 212148 kb
Host smart-fce6cedb-1f9a-4e99-91af-34feb753f873
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4106727171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.4106727171
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2506931685
Short name T158
Test name
Test status
Simulation time 373271061 ps
CPU time 6.56 seconds
Started Aug 10 05:36:32 PM PDT 24
Finished Aug 10 05:36:39 PM PDT 24
Peak memory 212112 kb
Host smart-b9cc1735-0c35-4690-9133-b4ae6e1d4cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506931685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2506931685
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.626164910
Short name T305
Test name
Test status
Simulation time 1459228760 ps
CPU time 20.65 seconds
Started Aug 10 05:36:34 PM PDT 24
Finished Aug 10 05:36:55 PM PDT 24
Peak memory 216264 kb
Host smart-09c81681-852b-4b78-b923-64ab48a0a2a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626164910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.626164910
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1066732794
Short name T160
Test name
Test status
Simulation time 347621545 ps
CPU time 4.35 seconds
Started Aug 10 05:36:43 PM PDT 24
Finished Aug 10 05:36:47 PM PDT 24
Peak memory 212076 kb
Host smart-3d88a5af-0689-483d-818d-aba7df15415b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066732794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1066732794
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3724566876
Short name T252
Test name
Test status
Simulation time 3098306540 ps
CPU time 80.96 seconds
Started Aug 10 05:36:42 PM PDT 24
Finished Aug 10 05:38:03 PM PDT 24
Peak memory 238496 kb
Host smart-8ca14b10-ebf6-45d3-bfeb-8e7a5c8041dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724566876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3724566876
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.4192158389
Short name T10
Test name
Test status
Simulation time 616781933 ps
CPU time 9.63 seconds
Started Aug 10 05:36:44 PM PDT 24
Finished Aug 10 05:36:53 PM PDT 24
Peak memory 212780 kb
Host smart-0625d4cc-758e-4275-99ed-6b41bca5bd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192158389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.4192158389
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.843101053
Short name T229
Test name
Test status
Simulation time 382341543 ps
CPU time 5.4 seconds
Started Aug 10 05:36:43 PM PDT 24
Finished Aug 10 05:36:49 PM PDT 24
Peak memory 212172 kb
Host smart-783613ff-7342-49ca-aa54-d4274384cb97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=843101053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.843101053
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.574663286
Short name T132
Test name
Test status
Simulation time 270521844 ps
CPU time 6.17 seconds
Started Aug 10 05:36:46 PM PDT 24
Finished Aug 10 05:36:52 PM PDT 24
Peak memory 212164 kb
Host smart-2cf434a8-7ce1-4619-a6e3-3ef3172e9736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574663286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.574663286
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1052908373
Short name T216
Test name
Test status
Simulation time 1392891427 ps
CPU time 19.01 seconds
Started Aug 10 05:36:39 PM PDT 24
Finished Aug 10 05:36:59 PM PDT 24
Peak memory 216040 kb
Host smart-38ac45f3-2c41-4932-896a-7c873399b659
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052908373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1052908373
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.917330843
Short name T265
Test name
Test status
Simulation time 1049056342 ps
CPU time 4.36 seconds
Started Aug 10 05:36:43 PM PDT 24
Finished Aug 10 05:36:48 PM PDT 24
Peak memory 212056 kb
Host smart-5b481db3-f39c-44c9-bc6a-dcecd23dd845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917330843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.917330843
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1864413274
Short name T18
Test name
Test status
Simulation time 9149262047 ps
CPU time 104.58 seconds
Started Aug 10 05:36:40 PM PDT 24
Finished Aug 10 05:38:25 PM PDT 24
Peak memory 226252 kb
Host smart-e2beeced-95af-4b57-9e28-15a062a4ae44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864413274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1864413274
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.417805974
Short name T237
Test name
Test status
Simulation time 1378502759 ps
CPU time 11.5 seconds
Started Aug 10 05:36:45 PM PDT 24
Finished Aug 10 05:36:57 PM PDT 24
Peak memory 212904 kb
Host smart-14d11dda-5b71-40f8-b6d2-60efc634f548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417805974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.417805974
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3769652034
Short name T151
Test name
Test status
Simulation time 195063558 ps
CPU time 6.26 seconds
Started Aug 10 05:36:44 PM PDT 24
Finished Aug 10 05:36:50 PM PDT 24
Peak memory 212180 kb
Host smart-6474d3e2-0a34-4478-beac-fdf6884b1212
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3769652034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3769652034
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3469705470
Short name T2
Test name
Test status
Simulation time 557023630 ps
CPU time 6.53 seconds
Started Aug 10 05:36:40 PM PDT 24
Finished Aug 10 05:36:47 PM PDT 24
Peak memory 212168 kb
Host smart-8ae541ca-273e-40fb-8f82-1d42722d1204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469705470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3469705470
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1169738880
Short name T254
Test name
Test status
Simulation time 574743039 ps
CPU time 15.4 seconds
Started Aug 10 05:36:43 PM PDT 24
Finished Aug 10 05:36:59 PM PDT 24
Peak memory 214416 kb
Host smart-f994389c-28c8-4050-87ee-e2e834e07193
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169738880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1169738880
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3704572052
Short name T157
Test name
Test status
Simulation time 322024612 ps
CPU time 5.06 seconds
Started Aug 10 05:36:44 PM PDT 24
Finished Aug 10 05:36:49 PM PDT 24
Peak memory 212020 kb
Host smart-467f18ef-53ca-40f8-8583-11872d0eb360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704572052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3704572052
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.292129179
Short name T39
Test name
Test status
Simulation time 2616905247 ps
CPU time 121.78 seconds
Started Aug 10 05:36:43 PM PDT 24
Finished Aug 10 05:38:45 PM PDT 24
Peak memory 237420 kb
Host smart-f4e98aea-6186-46c4-8604-0e79a8ca26f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292129179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.292129179
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3467587280
Short name T128
Test name
Test status
Simulation time 1666993636 ps
CPU time 11.2 seconds
Started Aug 10 05:36:45 PM PDT 24
Finished Aug 10 05:36:57 PM PDT 24
Peak memory 212200 kb
Host smart-ca791b18-02cf-4b77-a0cd-3e4d9c0468c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467587280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3467587280
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1525603033
Short name T150
Test name
Test status
Simulation time 99610568 ps
CPU time 5.58 seconds
Started Aug 10 05:36:43 PM PDT 24
Finished Aug 10 05:36:49 PM PDT 24
Peak memory 212164 kb
Host smart-8c7e7879-9259-4b60-890d-1dade179d88b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1525603033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1525603033
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.4230856443
Short name T263
Test name
Test status
Simulation time 1359112501 ps
CPU time 5.55 seconds
Started Aug 10 05:36:46 PM PDT 24
Finished Aug 10 05:36:51 PM PDT 24
Peak memory 212296 kb
Host smart-2bd3a15c-9742-452b-9c8f-cdb788fe2eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230856443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4230856443
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.289668414
Short name T42
Test name
Test status
Simulation time 634151674 ps
CPU time 10.66 seconds
Started Aug 10 05:36:40 PM PDT 24
Finished Aug 10 05:36:51 PM PDT 24
Peak memory 213456 kb
Host smart-1a208442-3dbe-441d-a41b-06bc76fa9411
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289668414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.289668414
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2594378572
Short name T52
Test name
Test status
Simulation time 57448541215 ps
CPU time 410.22 seconds
Started Aug 10 05:36:41 PM PDT 24
Finished Aug 10 05:43:31 PM PDT 24
Peak memory 236716 kb
Host smart-c72914a5-1bbf-4ace-b3c7-6d6b34983d5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594378572 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.2594378572
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3227899520
Short name T278
Test name
Test status
Simulation time 246276698 ps
CPU time 4.21 seconds
Started Aug 10 05:36:50 PM PDT 24
Finished Aug 10 05:36:54 PM PDT 24
Peak memory 212068 kb
Host smart-b43844b9-1110-424a-91f0-b92088a683d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227899520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3227899520
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1078273502
Short name T28
Test name
Test status
Simulation time 8853617403 ps
CPU time 102.83 seconds
Started Aug 10 05:36:49 PM PDT 24
Finished Aug 10 05:38:32 PM PDT 24
Peak memory 226392 kb
Host smart-d69c7338-fbbf-4e3b-a53a-163ab2f2da4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078273502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1078273502
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4202257021
Short name T171
Test name
Test status
Simulation time 1108253194 ps
CPU time 9.56 seconds
Started Aug 10 05:36:50 PM PDT 24
Finished Aug 10 05:36:59 PM PDT 24
Peak memory 212796 kb
Host smart-f9eb8602-6417-4b30-ab15-b735c90b8d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202257021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4202257021
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3117806332
Short name T6
Test name
Test status
Simulation time 319175584 ps
CPU time 5.9 seconds
Started Aug 10 05:36:48 PM PDT 24
Finished Aug 10 05:36:54 PM PDT 24
Peak memory 212256 kb
Host smart-1e3b96c1-dbb4-4e09-ad43-a0d8d1972ab3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3117806332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3117806332
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1626216071
Short name T272
Test name
Test status
Simulation time 323001740 ps
CPU time 6.21 seconds
Started Aug 10 05:36:42 PM PDT 24
Finished Aug 10 05:36:48 PM PDT 24
Peak memory 212164 kb
Host smart-aa9ea57e-bc6c-4c13-8280-d89cac713a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626216071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1626216071
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.672613971
Short name T172
Test name
Test status
Simulation time 273715296 ps
CPU time 13.05 seconds
Started Aug 10 05:36:42 PM PDT 24
Finished Aug 10 05:36:55 PM PDT 24
Peak memory 214924 kb
Host smart-550e8709-901b-4afe-8b83-f5617f8151f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672613971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.672613971
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1337071007
Short name T14
Test name
Test status
Simulation time 17780783823 ps
CPU time 693.63 seconds
Started Aug 10 05:36:49 PM PDT 24
Finished Aug 10 05:48:23 PM PDT 24
Peak memory 234940 kb
Host smart-8e837795-d3d9-4779-8f93-5a570f666a2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337071007 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.1337071007
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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