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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.26 96.89 91.99 97.67 100.00 98.62 97.30 98.37


Total test records in report: 433
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T295 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.624256621 Aug 11 06:13:55 PM PDT 24 Aug 11 06:14:00 PM PDT 24 383781993 ps
T296 /workspace/coverage/default/0.rom_ctrl_smoke.688191024 Aug 11 06:13:27 PM PDT 24 Aug 11 06:13:34 PM PDT 24 299513559 ps
T297 /workspace/coverage/default/46.rom_ctrl_alert_test.1881189793 Aug 11 06:14:10 PM PDT 24 Aug 11 06:14:15 PM PDT 24 97946031 ps
T298 /workspace/coverage/default/17.rom_ctrl_alert_test.1308665631 Aug 11 06:13:36 PM PDT 24 Aug 11 06:13:41 PM PDT 24 85762356 ps
T299 /workspace/coverage/default/9.rom_ctrl_smoke.136555894 Aug 11 06:13:30 PM PDT 24 Aug 11 06:13:36 PM PDT 24 101522878 ps
T300 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1706099019 Aug 11 06:13:49 PM PDT 24 Aug 11 06:13:56 PM PDT 24 563297089 ps
T301 /workspace/coverage/default/11.rom_ctrl_stress_all.2990846626 Aug 11 06:13:36 PM PDT 24 Aug 11 06:13:45 PM PDT 24 251318638 ps
T302 /workspace/coverage/default/30.rom_ctrl_stress_all.3285016115 Aug 11 06:13:45 PM PDT 24 Aug 11 06:13:56 PM PDT 24 176258262 ps
T303 /workspace/coverage/default/26.rom_ctrl_stress_all.1805087930 Aug 11 06:13:47 PM PDT 24 Aug 11 06:13:56 PM PDT 24 611918238 ps
T304 /workspace/coverage/default/43.rom_ctrl_alert_test.3493778050 Aug 11 06:14:05 PM PDT 24 Aug 11 06:14:09 PM PDT 24 175083052 ps
T305 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.511040459 Aug 11 06:14:16 PM PDT 24 Aug 11 06:14:21 PM PDT 24 101255254 ps
T306 /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2519631162 Aug 11 06:13:48 PM PDT 24 Aug 11 06:31:14 PM PDT 24 98069385702 ps
T307 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1615169692 Aug 11 06:13:47 PM PDT 24 Aug 11 06:13:52 PM PDT 24 383559534 ps
T308 /workspace/coverage/default/7.rom_ctrl_stress_all.442818925 Aug 11 06:13:30 PM PDT 24 Aug 11 06:13:40 PM PDT 24 740092064 ps
T309 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3218494690 Aug 11 06:13:36 PM PDT 24 Aug 11 06:16:08 PM PDT 24 6193847776 ps
T310 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1948533018 Aug 11 06:13:37 PM PDT 24 Aug 11 06:15:00 PM PDT 24 6833071262 ps
T311 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.721645796 Aug 11 06:14:07 PM PDT 24 Aug 11 06:16:02 PM PDT 24 8791656998 ps
T312 /workspace/coverage/default/34.rom_ctrl_stress_all.2988397099 Aug 11 06:13:53 PM PDT 24 Aug 11 06:14:04 PM PDT 24 671805460 ps
T313 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2976831563 Aug 11 06:13:48 PM PDT 24 Aug 11 06:13:58 PM PDT 24 693197395 ps
T314 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3756451861 Aug 11 06:14:01 PM PDT 24 Aug 11 06:14:11 PM PDT 24 670735043 ps
T315 /workspace/coverage/default/37.rom_ctrl_stress_all.3525908855 Aug 11 06:13:50 PM PDT 24 Aug 11 06:14:03 PM PDT 24 562315560 ps
T316 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3026135829 Aug 11 06:13:36 PM PDT 24 Aug 11 06:16:00 PM PDT 24 8955138002 ps
T317 /workspace/coverage/default/40.rom_ctrl_stress_all.60564893 Aug 11 06:13:57 PM PDT 24 Aug 11 06:14:17 PM PDT 24 1534241410 ps
T318 /workspace/coverage/default/14.rom_ctrl_stress_all.2827005556 Aug 11 06:13:38 PM PDT 24 Aug 11 06:13:49 PM PDT 24 515224752 ps
T319 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1907866813 Aug 11 06:14:06 PM PDT 24 Aug 11 06:17:26 PM PDT 24 4177051110 ps
T320 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4196499951 Aug 11 06:13:56 PM PDT 24 Aug 11 06:14:03 PM PDT 24 563033834 ps
T321 /workspace/coverage/default/6.rom_ctrl_smoke.3573441792 Aug 11 06:13:27 PM PDT 24 Aug 11 06:13:34 PM PDT 24 270438606 ps
T322 /workspace/coverage/default/0.rom_ctrl_stress_all.279061048 Aug 11 06:13:32 PM PDT 24 Aug 11 06:13:41 PM PDT 24 168703894 ps
T323 /workspace/coverage/default/7.rom_ctrl_alert_test.4168479055 Aug 11 06:13:30 PM PDT 24 Aug 11 06:13:36 PM PDT 24 496935109 ps
T324 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2862110385 Aug 11 06:13:54 PM PDT 24 Aug 11 06:14:00 PM PDT 24 194292068 ps
T325 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2680675534 Aug 11 06:13:29 PM PDT 24 Aug 11 06:13:39 PM PDT 24 175181023 ps
T326 /workspace/coverage/default/16.rom_ctrl_stress_all.491499838 Aug 11 06:13:38 PM PDT 24 Aug 11 06:13:50 PM PDT 24 727376808 ps
T327 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.149632592 Aug 11 06:13:35 PM PDT 24 Aug 11 06:13:41 PM PDT 24 202316744 ps
T328 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.315424325 Aug 11 06:13:29 PM PDT 24 Aug 11 06:13:35 PM PDT 24 142403903 ps
T329 /workspace/coverage/default/3.rom_ctrl_smoke.3418771963 Aug 11 06:13:31 PM PDT 24 Aug 11 06:13:43 PM PDT 24 280765062 ps
T330 /workspace/coverage/default/28.rom_ctrl_stress_all.3756542853 Aug 11 06:13:58 PM PDT 24 Aug 11 06:14:16 PM PDT 24 1125051277 ps
T331 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1434794184 Aug 11 06:14:13 PM PDT 24 Aug 11 06:15:40 PM PDT 24 6450401404 ps
T332 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2002482173 Aug 11 06:13:31 PM PDT 24 Aug 11 06:13:41 PM PDT 24 341133297 ps
T62 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2731550187 Aug 11 07:07:22 PM PDT 24 Aug 11 07:07:29 PM PDT 24 544487885 ps
T63 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1066461931 Aug 11 07:07:10 PM PDT 24 Aug 11 07:07:58 PM PDT 24 12460220655 ps
T58 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3406836805 Aug 11 07:07:02 PM PDT 24 Aug 11 07:08:11 PM PDT 24 591357397 ps
T333 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1264679877 Aug 11 07:06:44 PM PDT 24 Aug 11 07:06:54 PM PDT 24 606446430 ps
T334 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.656768272 Aug 11 07:06:50 PM PDT 24 Aug 11 07:06:56 PM PDT 24 264265846 ps
T335 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1611225313 Aug 11 07:07:28 PM PDT 24 Aug 11 07:07:34 PM PDT 24 171848395 ps
T336 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3677589570 Aug 11 07:06:52 PM PDT 24 Aug 11 07:06:57 PM PDT 24 391781015 ps
T59 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1023019933 Aug 11 07:06:52 PM PDT 24 Aug 11 07:07:29 PM PDT 24 536500259 ps
T69 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1621848533 Aug 11 07:07:18 PM PDT 24 Aug 11 07:07:22 PM PDT 24 86679503 ps
T70 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1682220215 Aug 11 07:06:57 PM PDT 24 Aug 11 07:07:03 PM PDT 24 499815719 ps
T337 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.245667796 Aug 11 07:07:13 PM PDT 24 Aug 11 07:07:18 PM PDT 24 494386369 ps
T338 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1787544219 Aug 11 07:06:53 PM PDT 24 Aug 11 07:06:57 PM PDT 24 85798686 ps
T339 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1092889631 Aug 11 07:06:58 PM PDT 24 Aug 11 07:07:02 PM PDT 24 332695324 ps
T340 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2791326508 Aug 11 07:06:51 PM PDT 24 Aug 11 07:06:57 PM PDT 24 140179032 ps
T341 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2121855266 Aug 11 07:06:57 PM PDT 24 Aug 11 07:07:04 PM PDT 24 137573855 ps
T71 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.143906462 Aug 11 07:07:08 PM PDT 24 Aug 11 07:07:40 PM PDT 24 810658319 ps
T72 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1323680048 Aug 11 07:06:59 PM PDT 24 Aug 11 07:07:33 PM PDT 24 2532969569 ps
T97 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1493070224 Aug 11 07:06:44 PM PDT 24 Aug 11 07:06:49 PM PDT 24 919015236 ps
T73 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3629829601 Aug 11 07:07:07 PM PDT 24 Aug 11 07:07:12 PM PDT 24 127533174 ps
T74 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.320840706 Aug 11 07:07:00 PM PDT 24 Aug 11 07:07:06 PM PDT 24 128586216 ps
T92 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.558275726 Aug 11 07:07:26 PM PDT 24 Aug 11 07:07:30 PM PDT 24 88911342 ps
T75 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2075564170 Aug 11 07:07:10 PM PDT 24 Aug 11 07:07:16 PM PDT 24 1132276227 ps
T76 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1185083680 Aug 11 07:07:03 PM PDT 24 Aug 11 07:07:30 PM PDT 24 2238216199 ps
T60 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3125432025 Aug 11 07:07:10 PM PDT 24 Aug 11 07:07:49 PM PDT 24 583931618 ps
T342 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.984187248 Aug 11 07:07:01 PM PDT 24 Aug 11 07:07:06 PM PDT 24 177232948 ps
T343 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3009982717 Aug 11 07:07:36 PM PDT 24 Aug 11 07:07:42 PM PDT 24 512340883 ps
T344 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1281747821 Aug 11 07:07:19 PM PDT 24 Aug 11 07:07:24 PM PDT 24 277879115 ps
T345 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2803004801 Aug 11 07:06:46 PM PDT 24 Aug 11 07:06:54 PM PDT 24 92060138 ps
T346 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.488625866 Aug 11 07:06:44 PM PDT 24 Aug 11 07:06:49 PM PDT 24 619167255 ps
T347 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.669520072 Aug 11 07:07:14 PM PDT 24 Aug 11 07:07:19 PM PDT 24 298598794 ps
T348 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4165528230 Aug 11 07:07:23 PM PDT 24 Aug 11 07:07:28 PM PDT 24 572442102 ps
T105 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1529408690 Aug 11 07:07:01 PM PDT 24 Aug 11 07:07:40 PM PDT 24 274705923 ps
T349 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1678739962 Aug 11 07:07:01 PM PDT 24 Aug 11 07:07:06 PM PDT 24 813525327 ps
T350 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3375532517 Aug 11 07:06:57 PM PDT 24 Aug 11 07:07:03 PM PDT 24 92540428 ps
T106 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1706604279 Aug 11 07:07:27 PM PDT 24 Aug 11 07:08:36 PM PDT 24 213319115 ps
T93 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4202347433 Aug 11 07:07:28 PM PDT 24 Aug 11 07:07:34 PM PDT 24 654623589 ps
T351 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4129763440 Aug 11 07:07:09 PM PDT 24 Aug 11 07:07:18 PM PDT 24 136448930 ps
T107 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3110114294 Aug 11 07:06:59 PM PDT 24 Aug 11 07:07:37 PM PDT 24 1457816339 ps
T352 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3589017216 Aug 11 07:07:19 PM PDT 24 Aug 11 07:07:25 PM PDT 24 208385795 ps
T94 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3049531252 Aug 11 07:06:52 PM PDT 24 Aug 11 07:07:20 PM PDT 24 2154602647 ps
T102 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3559343714 Aug 11 07:07:20 PM PDT 24 Aug 11 07:07:39 PM PDT 24 370183449 ps
T95 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.981606808 Aug 11 07:07:15 PM PDT 24 Aug 11 07:07:19 PM PDT 24 321453097 ps
T353 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2034761778 Aug 11 07:07:22 PM PDT 24 Aug 11 07:07:30 PM PDT 24 126888648 ps
T96 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3663928081 Aug 11 07:07:14 PM PDT 24 Aug 11 07:07:34 PM PDT 24 1200939559 ps
T354 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2666901650 Aug 11 07:07:20 PM PDT 24 Aug 11 07:07:27 PM PDT 24 2061857166 ps
T355 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1348152234 Aug 11 07:06:57 PM PDT 24 Aug 11 07:07:02 PM PDT 24 283696714 ps
T77 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1243326971 Aug 11 07:07:14 PM PDT 24 Aug 11 07:07:48 PM PDT 24 804968535 ps
T356 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1707060516 Aug 11 07:06:52 PM PDT 24 Aug 11 07:06:57 PM PDT 24 85824297 ps
T357 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2980660664 Aug 11 07:06:45 PM PDT 24 Aug 11 07:06:50 PM PDT 24 131646071 ps
T358 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4108804488 Aug 11 07:07:09 PM PDT 24 Aug 11 07:07:19 PM PDT 24 602245848 ps
T359 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.49458441 Aug 11 07:07:19 PM PDT 24 Aug 11 07:07:24 PM PDT 24 252285521 ps
T108 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1698464978 Aug 11 07:07:17 PM PDT 24 Aug 11 07:08:26 PM PDT 24 439176158 ps
T360 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3539963385 Aug 11 07:07:08 PM PDT 24 Aug 11 07:07:12 PM PDT 24 87427358 ps
T361 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3343535448 Aug 11 07:06:57 PM PDT 24 Aug 11 07:07:09 PM PDT 24 1974293723 ps
T362 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3296431657 Aug 11 07:07:09 PM PDT 24 Aug 11 07:07:14 PM PDT 24 532805373 ps
T363 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2945272810 Aug 11 07:07:09 PM PDT 24 Aug 11 07:07:15 PM PDT 24 99023398 ps
T364 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1996095106 Aug 11 07:06:53 PM PDT 24 Aug 11 07:07:02 PM PDT 24 290026896 ps
T365 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3566314879 Aug 11 07:07:00 PM PDT 24 Aug 11 07:07:08 PM PDT 24 350937472 ps
T366 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.34696720 Aug 11 07:07:22 PM PDT 24 Aug 11 07:08:01 PM PDT 24 425864862 ps
T367 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3543167190 Aug 11 07:07:08 PM PDT 24 Aug 11 07:07:18 PM PDT 24 2437598636 ps
T368 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.319024843 Aug 11 07:07:26 PM PDT 24 Aug 11 07:07:32 PM PDT 24 131085089 ps
T111 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2135175397 Aug 11 07:06:56 PM PDT 24 Aug 11 07:07:34 PM PDT 24 345916626 ps
T369 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1518913503 Aug 11 07:07:15 PM PDT 24 Aug 11 07:07:19 PM PDT 24 347196472 ps
T370 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.550566293 Aug 11 07:07:26 PM PDT 24 Aug 11 07:07:36 PM PDT 24 295489268 ps
T371 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.462736109 Aug 11 07:07:20 PM PDT 24 Aug 11 07:07:24 PM PDT 24 90100011 ps
T80 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.644205199 Aug 11 07:07:21 PM PDT 24 Aug 11 07:07:49 PM PDT 24 570773691 ps
T104 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.727916394 Aug 11 07:07:24 PM PDT 24 Aug 11 07:08:00 PM PDT 24 355040288 ps
T372 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2752536649 Aug 11 07:07:03 PM PDT 24 Aug 11 07:07:07 PM PDT 24 85616302 ps
T373 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3156215152 Aug 11 07:07:19 PM PDT 24 Aug 11 07:07:27 PM PDT 24 104996603 ps
T374 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.876432322 Aug 11 07:07:09 PM PDT 24 Aug 11 07:07:14 PM PDT 24 89597235 ps
T81 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.591273319 Aug 11 07:06:57 PM PDT 24 Aug 11 07:07:19 PM PDT 24 2250187753 ps
T375 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1272170901 Aug 11 07:07:29 PM PDT 24 Aug 11 07:07:35 PM PDT 24 550725746 ps
T376 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1728220537 Aug 11 07:07:19 PM PDT 24 Aug 11 07:07:26 PM PDT 24 336470379 ps
T377 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2044214475 Aug 11 07:07:21 PM PDT 24 Aug 11 07:07:30 PM PDT 24 103054502 ps
T82 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2938096892 Aug 11 07:06:49 PM PDT 24 Aug 11 07:06:55 PM PDT 24 695087065 ps
T378 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.799450976 Aug 11 07:07:34 PM PDT 24 Aug 11 07:08:12 PM PDT 24 408925548 ps
T379 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3814991676 Aug 11 07:06:58 PM PDT 24 Aug 11 07:07:03 PM PDT 24 138657051 ps
T380 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3497315584 Aug 11 07:07:14 PM PDT 24 Aug 11 07:07:19 PM PDT 24 279415009 ps
T381 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1336255760 Aug 11 07:06:51 PM PDT 24 Aug 11 07:06:59 PM PDT 24 346480470 ps
T112 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1588323395 Aug 11 07:07:23 PM PDT 24 Aug 11 07:08:32 PM PDT 24 229345639 ps
T382 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1053215141 Aug 11 07:07:15 PM PDT 24 Aug 11 07:07:22 PM PDT 24 86595410 ps
T383 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1219850803 Aug 11 07:07:28 PM PDT 24 Aug 11 07:08:07 PM PDT 24 1195687845 ps
T384 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.865861638 Aug 11 07:07:14 PM PDT 24 Aug 11 07:07:23 PM PDT 24 251219152 ps
T83 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2972920169 Aug 11 07:07:23 PM PDT 24 Aug 11 07:07:27 PM PDT 24 1377954497 ps
T89 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3170848310 Aug 11 07:07:17 PM PDT 24 Aug 11 07:07:46 PM PDT 24 554792008 ps
T385 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1222933689 Aug 11 07:07:27 PM PDT 24 Aug 11 07:07:32 PM PDT 24 130844537 ps
T386 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2787547981 Aug 11 07:07:31 PM PDT 24 Aug 11 07:07:40 PM PDT 24 126991980 ps
T387 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1341757100 Aug 11 07:06:53 PM PDT 24 Aug 11 07:07:02 PM PDT 24 544323534 ps
T388 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1910097823 Aug 11 07:07:09 PM PDT 24 Aug 11 07:07:15 PM PDT 24 295790781 ps
T389 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3406581352 Aug 11 07:07:29 PM PDT 24 Aug 11 07:07:35 PM PDT 24 194742783 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3167487682 Aug 11 07:06:57 PM PDT 24 Aug 11 07:07:02 PM PDT 24 320107944 ps
T391 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2036642101 Aug 11 07:07:09 PM PDT 24 Aug 11 07:07:14 PM PDT 24 172827542 ps
T392 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.560645383 Aug 11 07:06:45 PM PDT 24 Aug 11 07:06:50 PM PDT 24 332669039 ps
T393 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2617109911 Aug 11 07:07:21 PM PDT 24 Aug 11 07:07:26 PM PDT 24 279415258 ps
T84 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3969398434 Aug 11 07:06:46 PM PDT 24 Aug 11 07:06:50 PM PDT 24 86750564 ps
T394 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.598454009 Aug 11 07:06:52 PM PDT 24 Aug 11 07:07:00 PM PDT 24 130888462 ps
T395 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1716712678 Aug 11 07:07:07 PM PDT 24 Aug 11 07:07:13 PM PDT 24 428417308 ps
T113 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1403801503 Aug 11 07:07:16 PM PDT 24 Aug 11 07:08:26 PM PDT 24 257069500 ps
T109 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.725162416 Aug 11 07:06:45 PM PDT 24 Aug 11 07:07:25 PM PDT 24 1098301452 ps
T85 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3434410186 Aug 11 07:07:01 PM PDT 24 Aug 11 07:07:05 PM PDT 24 167811022 ps
T396 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.523180779 Aug 11 07:07:02 PM PDT 24 Aug 11 07:07:08 PM PDT 24 520008305 ps
T397 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.743809364 Aug 11 07:07:33 PM PDT 24 Aug 11 07:07:38 PM PDT 24 86661389 ps
T398 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3569378467 Aug 11 07:06:38 PM PDT 24 Aug 11 07:07:12 PM PDT 24 1643866217 ps
T399 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.661412876 Aug 11 07:07:08 PM PDT 24 Aug 11 07:07:15 PM PDT 24 133557112 ps
T400 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3500680342 Aug 11 07:06:45 PM PDT 24 Aug 11 07:06:50 PM PDT 24 131457720 ps
T401 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1997902356 Aug 11 07:06:52 PM PDT 24 Aug 11 07:06:56 PM PDT 24 378197840 ps
T402 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2212230544 Aug 11 07:07:10 PM PDT 24 Aug 11 07:07:15 PM PDT 24 113708360 ps
T403 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2245506416 Aug 11 07:07:22 PM PDT 24 Aug 11 07:07:28 PM PDT 24 257732662 ps
T404 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.109006685 Aug 11 07:07:10 PM PDT 24 Aug 11 07:07:43 PM PDT 24 1569550374 ps
T110 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1642845280 Aug 11 07:07:08 PM PDT 24 Aug 11 07:08:30 PM PDT 24 1246917827 ps
T405 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1008826454 Aug 11 07:07:14 PM PDT 24 Aug 11 07:07:19 PM PDT 24 262531796 ps
T406 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2239862569 Aug 11 07:06:52 PM PDT 24 Aug 11 07:06:58 PM PDT 24 520460593 ps
T114 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.520531113 Aug 11 07:07:15 PM PDT 24 Aug 11 07:07:53 PM PDT 24 327794554 ps
T407 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1712327924 Aug 11 07:07:10 PM PDT 24 Aug 11 07:07:18 PM PDT 24 126979192 ps
T408 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.329284051 Aug 11 07:07:09 PM PDT 24 Aug 11 07:07:18 PM PDT 24 174750639 ps
T409 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1203743343 Aug 11 07:07:15 PM PDT 24 Aug 11 07:08:22 PM PDT 24 403524886 ps
T410 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.131747833 Aug 11 07:07:20 PM PDT 24 Aug 11 07:07:26 PM PDT 24 126558091 ps
T411 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.469549415 Aug 11 07:07:27 PM PDT 24 Aug 11 07:07:49 PM PDT 24 7441716316 ps
T412 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.987715873 Aug 11 07:06:51 PM PDT 24 Aug 11 07:07:24 PM PDT 24 2464985774 ps
T86 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.705587603 Aug 11 07:07:11 PM PDT 24 Aug 11 07:07:16 PM PDT 24 517660676 ps
T87 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2888401548 Aug 11 07:07:02 PM PDT 24 Aug 11 07:07:35 PM PDT 24 2721731198 ps
T413 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1951591376 Aug 11 07:07:36 PM PDT 24 Aug 11 07:07:41 PM PDT 24 129378079 ps
T91 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2835302717 Aug 11 07:07:17 PM PDT 24 Aug 11 07:07:50 PM PDT 24 1197075633 ps
T414 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.401356203 Aug 11 07:07:17 PM PDT 24 Aug 11 07:07:40 PM PDT 24 540318404 ps
T415 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2675850358 Aug 11 07:06:57 PM PDT 24 Aug 11 07:07:02 PM PDT 24 94929971 ps
T416 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3612837157 Aug 11 07:06:54 PM PDT 24 Aug 11 07:06:59 PM PDT 24 133113846 ps
T417 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.76641719 Aug 11 07:07:18 PM PDT 24 Aug 11 07:07:24 PM PDT 24 101631381 ps
T418 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4175963382 Aug 11 07:07:07 PM PDT 24 Aug 11 07:07:12 PM PDT 24 250529236 ps
T419 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4227161907 Aug 11 07:07:19 PM PDT 24 Aug 11 07:07:23 PM PDT 24 334384730 ps
T420 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.601596374 Aug 11 07:06:57 PM PDT 24 Aug 11 07:07:04 PM PDT 24 958906782 ps
T421 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3486695067 Aug 11 07:07:02 PM PDT 24 Aug 11 07:07:07 PM PDT 24 169288186 ps
T90 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3029665840 Aug 11 07:07:28 PM PDT 24 Aug 11 07:07:47 PM PDT 24 377048553 ps
T422 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2682873614 Aug 11 07:07:04 PM PDT 24 Aug 11 07:07:10 PM PDT 24 518301006 ps
T423 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2447843697 Aug 11 07:07:08 PM PDT 24 Aug 11 07:08:21 PM PDT 24 295399586 ps
T424 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4122155494 Aug 11 07:07:17 PM PDT 24 Aug 11 07:07:25 PM PDT 24 168531683 ps
T88 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.244748466 Aug 11 07:06:51 PM PDT 24 Aug 11 07:06:56 PM PDT 24 126585848 ps
T425 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.230042925 Aug 11 07:06:44 PM PDT 24 Aug 11 07:06:48 PM PDT 24 363817426 ps
T426 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4155951162 Aug 11 07:06:45 PM PDT 24 Aug 11 07:07:23 PM PDT 24 218631729 ps
T427 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1487645657 Aug 11 07:06:58 PM PDT 24 Aug 11 07:07:03 PM PDT 24 140214515 ps
T428 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3098651230 Aug 11 07:06:51 PM PDT 24 Aug 11 07:06:55 PM PDT 24 362116514 ps
T429 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3341154237 Aug 11 07:06:46 PM PDT 24 Aug 11 07:06:51 PM PDT 24 451104661 ps
T430 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1340497283 Aug 11 07:07:22 PM PDT 24 Aug 11 07:07:29 PM PDT 24 535245874 ps
T431 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.548140327 Aug 11 07:07:26 PM PDT 24 Aug 11 07:08:00 PM PDT 24 3275718774 ps
T432 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2137573455 Aug 11 07:06:51 PM PDT 24 Aug 11 07:06:56 PM PDT 24 271693762 ps
T433 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.679299298 Aug 11 07:06:51 PM PDT 24 Aug 11 07:06:59 PM PDT 24 1887374106 ps

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1723223105
Short name T5
Test name
Test status
Simulation time 29882714568 ps
CPU time 567.3 seconds
Started Aug 11 06:13:40 PM PDT 24
Finished Aug 11 06:23:07 PM PDT 24
Peak memory 236600 kb
Host smart-434e994c-7e96-4e5f-83bf-b00da1c72db0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723223105 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1723223105
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2138742848
Short name T35
Test name
Test status
Simulation time 9684353516 ps
CPU time 122.83 seconds
Started Aug 11 06:13:53 PM PDT 24
Finished Aug 11 06:15:56 PM PDT 24
Peak memory 238484 kb
Host smart-db7394f0-0a44-4a97-8c4f-28552011952e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138742848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2138742848
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1677344708
Short name T10
Test name
Test status
Simulation time 1161893357 ps
CPU time 15.57 seconds
Started Aug 11 06:13:30 PM PDT 24
Finished Aug 11 06:13:45 PM PDT 24
Peak memory 215604 kb
Host smart-34688f91-c5ba-4af0-93dd-049e8b7fe41c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677344708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1677344708
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1706604279
Short name T106
Test name
Test status
Simulation time 213319115 ps
CPU time 68.6 seconds
Started Aug 11 07:07:27 PM PDT 24
Finished Aug 11 07:08:36 PM PDT 24
Peak memory 213100 kb
Host smart-9b19a27e-d49d-4a1b-af3b-02d1a78e0084
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706604279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1706604279
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.821085659
Short name T39
Test name
Test status
Simulation time 12688179956 ps
CPU time 120.84 seconds
Started Aug 11 06:13:49 PM PDT 24
Finished Aug 11 06:15:50 PM PDT 24
Peak memory 234472 kb
Host smart-a731bd6a-1789-4b80-9eec-330e977e8b19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821085659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.821085659
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.9730729
Short name T11
Test name
Test status
Simulation time 144734374564 ps
CPU time 1273.1 seconds
Started Aug 11 06:13:36 PM PDT 24
Finished Aug 11 06:34:49 PM PDT 24
Peak memory 236588 kb
Host smart-970f502d-612d-47df-81f8-dc4edd91dd22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9730729 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.9730729
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3754418568
Short name T25
Test name
Test status
Simulation time 650888333 ps
CPU time 101.95 seconds
Started Aug 11 06:13:36 PM PDT 24
Finished Aug 11 06:15:18 PM PDT 24
Peak memory 237864 kb
Host smart-a77f5a93-42e6-4639-803e-54e8ba445d48
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754418568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3754418568
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2512430807
Short name T4
Test name
Test status
Simulation time 309382115 ps
CPU time 4.21 seconds
Started Aug 11 06:13:30 PM PDT 24
Finished Aug 11 06:13:35 PM PDT 24
Peak memory 212032 kb
Host smart-ad989fe5-590b-4b0f-9964-3e17671770df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512430807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2512430807
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1682220215
Short name T70
Test name
Test status
Simulation time 499815719 ps
CPU time 5.11 seconds
Started Aug 11 07:06:57 PM PDT 24
Finished Aug 11 07:07:03 PM PDT 24
Peak memory 211244 kb
Host smart-71d3c41c-c25c-4346-ba4c-cb34939ceb56
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682220215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1682220215
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3406836805
Short name T58
Test name
Test status
Simulation time 591357397 ps
CPU time 69.02 seconds
Started Aug 11 07:07:02 PM PDT 24
Finished Aug 11 07:08:11 PM PDT 24
Peak memory 212960 kb
Host smart-84592bdd-fc8c-4961-84fc-4fb5a286bd26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406836805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3406836805
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3041252772
Short name T6
Test name
Test status
Simulation time 341794109 ps
CPU time 9.62 seconds
Started Aug 11 06:14:05 PM PDT 24
Finished Aug 11 06:14:15 PM PDT 24
Peak memory 212924 kb
Host smart-a199def2-4474-4dbd-a40c-a2004e04f3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041252772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3041252772
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2862545422
Short name T52
Test name
Test status
Simulation time 251029873 ps
CPU time 11.2 seconds
Started Aug 11 06:13:33 PM PDT 24
Finished Aug 11 06:13:44 PM PDT 24
Peak memory 213064 kb
Host smart-750778eb-10e3-4221-b8a4-1e530c3bc599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862545422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2862545422
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4083477973
Short name T51
Test name
Test status
Simulation time 258573344 ps
CPU time 10.93 seconds
Started Aug 11 06:13:38 PM PDT 24
Finished Aug 11 06:13:49 PM PDT 24
Peak memory 213024 kb
Host smart-a8fe2cd8-8af3-4d54-83e7-531366b26032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083477973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4083477973
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1403801503
Short name T113
Test name
Test status
Simulation time 257069500 ps
CPU time 70.49 seconds
Started Aug 11 07:07:16 PM PDT 24
Finished Aug 11 07:08:26 PM PDT 24
Peak memory 219480 kb
Host smart-9273cb2c-8a11-46f8-96ae-b83bc2cb087d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403801503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1403801503
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1066461931
Short name T63
Test name
Test status
Simulation time 12460220655 ps
CPU time 48.14 seconds
Started Aug 11 07:07:10 PM PDT 24
Finished Aug 11 07:07:58 PM PDT 24
Peak memory 211524 kb
Host smart-32862f5a-f626-4895-bdf0-b38131d04d1f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066461931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1066461931
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1698464978
Short name T108
Test name
Test status
Simulation time 439176158 ps
CPU time 69.63 seconds
Started Aug 11 07:07:17 PM PDT 24
Finished Aug 11 07:08:26 PM PDT 24
Peak memory 213064 kb
Host smart-a9c52eb3-24d5-4dea-8c7e-dc5a7d21c30e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698464978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1698464978
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1588323395
Short name T112
Test name
Test status
Simulation time 229345639 ps
CPU time 68.27 seconds
Started Aug 11 07:07:23 PM PDT 24
Finished Aug 11 07:08:32 PM PDT 24
Peak memory 219532 kb
Host smart-d8a0c9f3-7790-47b4-abdf-8b88666120b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588323395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1588323395
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.727916394
Short name T104
Test name
Test status
Simulation time 355040288 ps
CPU time 36.06 seconds
Started Aug 11 07:07:24 PM PDT 24
Finished Aug 11 07:08:00 PM PDT 24
Peak memory 219532 kb
Host smart-d93fa382-1860-493d-bb76-db177505300d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727916394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.727916394
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.981606808
Short name T95
Test name
Test status
Simulation time 321453097 ps
CPU time 4.31 seconds
Started Aug 11 07:07:15 PM PDT 24
Finished Aug 11 07:07:19 PM PDT 24
Peak memory 219476 kb
Host smart-cf0212ad-24da-4cbc-a9f5-34c9606be82f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981606808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.981606808
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.560645383
Short name T392
Test name
Test status
Simulation time 332669039 ps
CPU time 4.51 seconds
Started Aug 11 07:06:45 PM PDT 24
Finished Aug 11 07:06:50 PM PDT 24
Peak memory 211276 kb
Host smart-4c49726d-ec0a-40af-a34f-2b9edd0e2e85
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560645383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.560645383
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1493070224
Short name T97
Test name
Test status
Simulation time 919015236 ps
CPU time 4.56 seconds
Started Aug 11 07:06:44 PM PDT 24
Finished Aug 11 07:06:49 PM PDT 24
Peak memory 211320 kb
Host smart-7b162936-05db-4cb7-9a36-4e38c21ec45f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493070224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1493070224
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2803004801
Short name T345
Test name
Test status
Simulation time 92060138 ps
CPU time 7.35 seconds
Started Aug 11 07:06:46 PM PDT 24
Finished Aug 11 07:06:54 PM PDT 24
Peak memory 219396 kb
Host smart-8c8c4302-4979-47d1-9efb-745d6b7e7b0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803004801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2803004801
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3341154237
Short name T429
Test name
Test status
Simulation time 451104661 ps
CPU time 5.02 seconds
Started Aug 11 07:06:46 PM PDT 24
Finished Aug 11 07:06:51 PM PDT 24
Peak memory 216528 kb
Host smart-df19d443-ad04-4edf-a746-88397a23da88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341154237 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3341154237
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3969398434
Short name T84
Test name
Test status
Simulation time 86750564 ps
CPU time 4.14 seconds
Started Aug 11 07:06:46 PM PDT 24
Finished Aug 11 07:06:50 PM PDT 24
Peak memory 211288 kb
Host smart-d3f53f4b-cb40-4673-99a6-50b5aa1e1bf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969398434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3969398434
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3500680342
Short name T400
Test name
Test status
Simulation time 131457720 ps
CPU time 4.97 seconds
Started Aug 11 07:06:45 PM PDT 24
Finished Aug 11 07:06:50 PM PDT 24
Peak memory 211164 kb
Host smart-03181e36-10f0-4cfb-8ca0-5b1c5462e794
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500680342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3500680342
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.488625866
Short name T346
Test name
Test status
Simulation time 619167255 ps
CPU time 5.18 seconds
Started Aug 11 07:06:44 PM PDT 24
Finished Aug 11 07:06:49 PM PDT 24
Peak memory 211176 kb
Host smart-222802c1-5ef1-46bf-838b-4b702d3a6ce6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488625866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
488625866
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3569378467
Short name T398
Test name
Test status
Simulation time 1643866217 ps
CPU time 33.45 seconds
Started Aug 11 07:06:38 PM PDT 24
Finished Aug 11 07:07:12 PM PDT 24
Peak memory 211384 kb
Host smart-30a3dd3f-7732-4fa8-b903-32b43086989e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569378467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3569378467
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2980660664
Short name T357
Test name
Test status
Simulation time 131646071 ps
CPU time 5.45 seconds
Started Aug 11 07:06:45 PM PDT 24
Finished Aug 11 07:06:50 PM PDT 24
Peak memory 211324 kb
Host smart-3fd2b6a8-f716-4cd4-b138-8009cb730ef7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980660664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2980660664
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1336255760
Short name T381
Test name
Test status
Simulation time 346480470 ps
CPU time 7.65 seconds
Started Aug 11 07:06:51 PM PDT 24
Finished Aug 11 07:06:59 PM PDT 24
Peak memory 217680 kb
Host smart-0eb0e303-ae12-4912-ab14-cd192359d9f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336255760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1336255760
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4155951162
Short name T426
Test name
Test status
Simulation time 218631729 ps
CPU time 38.78 seconds
Started Aug 11 07:06:45 PM PDT 24
Finished Aug 11 07:07:23 PM PDT 24
Peak memory 211956 kb
Host smart-f887e110-2dfc-4298-b2b7-1dce75d86fcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155951162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.4155951162
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2938096892
Short name T82
Test name
Test status
Simulation time 695087065 ps
CPU time 5.12 seconds
Started Aug 11 07:06:49 PM PDT 24
Finished Aug 11 07:06:55 PM PDT 24
Peak memory 211308 kb
Host smart-42748d4d-7f46-473d-aa8f-d4447cec9ad2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938096892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2938096892
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.679299298
Short name T433
Test name
Test status
Simulation time 1887374106 ps
CPU time 7.77 seconds
Started Aug 11 07:06:51 PM PDT 24
Finished Aug 11 07:06:59 PM PDT 24
Peak memory 218220 kb
Host smart-a893c2bf-c8e2-41c6-bbfc-013905a71bb4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679299298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.679299298
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1341757100
Short name T387
Test name
Test status
Simulation time 544323534 ps
CPU time 8.25 seconds
Started Aug 11 07:06:53 PM PDT 24
Finished Aug 11 07:07:02 PM PDT 24
Peak memory 218956 kb
Host smart-eb17da34-56c1-4c12-b33d-f8302da09710
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341757100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1341757100
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.656768272
Short name T334
Test name
Test status
Simulation time 264265846 ps
CPU time 5.83 seconds
Started Aug 11 07:06:50 PM PDT 24
Finished Aug 11 07:06:56 PM PDT 24
Peak memory 219612 kb
Host smart-1814fe6b-2035-4213-94d0-408bfd669550
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656768272 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.656768272
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1997902356
Short name T401
Test name
Test status
Simulation time 378197840 ps
CPU time 4.24 seconds
Started Aug 11 07:06:52 PM PDT 24
Finished Aug 11 07:06:56 PM PDT 24
Peak memory 211284 kb
Host smart-5b4921c9-a0c6-4426-b982-f9546a732c87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997902356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1997902356
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3098651230
Short name T428
Test name
Test status
Simulation time 362116514 ps
CPU time 4.15 seconds
Started Aug 11 07:06:51 PM PDT 24
Finished Aug 11 07:06:55 PM PDT 24
Peak memory 211180 kb
Host smart-9dbe6114-e141-4091-b5ff-e95df2a4de18
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098651230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3098651230
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.230042925
Short name T425
Test name
Test status
Simulation time 363817426 ps
CPU time 4.14 seconds
Started Aug 11 07:06:44 PM PDT 24
Finished Aug 11 07:06:48 PM PDT 24
Peak memory 211224 kb
Host smart-f0c4da98-b5a2-4d5c-ac17-f555690dbd89
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230042925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
230042925
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.987715873
Short name T412
Test name
Test status
Simulation time 2464985774 ps
CPU time 32.81 seconds
Started Aug 11 07:06:51 PM PDT 24
Finished Aug 11 07:07:24 PM PDT 24
Peak memory 211428 kb
Host smart-f9bdb596-0376-4a01-aefa-8e24df0f82f8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987715873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.987715873
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3612837157
Short name T416
Test name
Test status
Simulation time 133113846 ps
CPU time 5.21 seconds
Started Aug 11 07:06:54 PM PDT 24
Finished Aug 11 07:06:59 PM PDT 24
Peak memory 211360 kb
Host smart-0ad612b4-1d6b-4516-916c-98beda6afd8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612837157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3612837157
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1264679877
Short name T333
Test name
Test status
Simulation time 606446430 ps
CPU time 9.62 seconds
Started Aug 11 07:06:44 PM PDT 24
Finished Aug 11 07:06:54 PM PDT 24
Peak memory 216508 kb
Host smart-26b37246-8c82-47bc-8ea5-8de5d982cd12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264679877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1264679877
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.725162416
Short name T109
Test name
Test status
Simulation time 1098301452 ps
CPU time 39.26 seconds
Started Aug 11 07:06:45 PM PDT 24
Finished Aug 11 07:07:25 PM PDT 24
Peak memory 219520 kb
Host smart-292683c7-c6e4-4c44-ba8e-b2c5a9dbb181
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725162416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.725162416
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3589017216
Short name T352
Test name
Test status
Simulation time 208385795 ps
CPU time 5.78 seconds
Started Aug 11 07:07:19 PM PDT 24
Finished Aug 11 07:07:25 PM PDT 24
Peak memory 215716 kb
Host smart-a93c18ab-a03f-40f9-b685-6b67fdafe677
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589017216 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3589017216
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1621848533
Short name T69
Test name
Test status
Simulation time 86679503 ps
CPU time 4.32 seconds
Started Aug 11 07:07:18 PM PDT 24
Finished Aug 11 07:07:22 PM PDT 24
Peak memory 211264 kb
Host smart-afcbb350-20d0-4943-8e49-6e167acc83b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621848533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1621848533
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.401356203
Short name T414
Test name
Test status
Simulation time 540318404 ps
CPU time 23.01 seconds
Started Aug 11 07:07:17 PM PDT 24
Finished Aug 11 07:07:40 PM PDT 24
Peak memory 211388 kb
Host smart-7a475b42-4838-4bd4-8cde-16e3a464b432
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401356203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.401356203
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4122155494
Short name T424
Test name
Test status
Simulation time 168531683 ps
CPU time 8.21 seconds
Started Aug 11 07:07:17 PM PDT 24
Finished Aug 11 07:07:25 PM PDT 24
Peak memory 216668 kb
Host smart-335e7b2a-88f1-44cf-8731-c61f62b6ed3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122155494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.4122155494
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.520531113
Short name T114
Test name
Test status
Simulation time 327794554 ps
CPU time 37.23 seconds
Started Aug 11 07:07:15 PM PDT 24
Finished Aug 11 07:07:53 PM PDT 24
Peak memory 219452 kb
Host smart-64879c26-b491-444b-8aba-9358ce562d41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520531113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.520531113
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.245667796
Short name T337
Test name
Test status
Simulation time 494386369 ps
CPU time 5.3 seconds
Started Aug 11 07:07:13 PM PDT 24
Finished Aug 11 07:07:18 PM PDT 24
Peak memory 216588 kb
Host smart-c679324c-7f5f-4233-bf83-7f12c96ed1f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245667796 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.245667796
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1008826454
Short name T405
Test name
Test status
Simulation time 262531796 ps
CPU time 5.1 seconds
Started Aug 11 07:07:14 PM PDT 24
Finished Aug 11 07:07:19 PM PDT 24
Peak memory 217824 kb
Host smart-d2686fd8-3a6c-4300-9d9c-dd4f90f4187b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008826454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1008826454
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3663928081
Short name T96
Test name
Test status
Simulation time 1200939559 ps
CPU time 19.18 seconds
Started Aug 11 07:07:14 PM PDT 24
Finished Aug 11 07:07:34 PM PDT 24
Peak memory 211392 kb
Host smart-148efe0c-b3b5-4c21-9617-745cd6c48fab
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663928081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3663928081
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1518913503
Short name T369
Test name
Test status
Simulation time 347196472 ps
CPU time 4.32 seconds
Started Aug 11 07:07:15 PM PDT 24
Finished Aug 11 07:07:19 PM PDT 24
Peak memory 211380 kb
Host smart-021ae804-cab9-4322-8101-1bfac85af818
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518913503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1518913503
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.865861638
Short name T384
Test name
Test status
Simulation time 251219152 ps
CPU time 8.92 seconds
Started Aug 11 07:07:14 PM PDT 24
Finished Aug 11 07:07:23 PM PDT 24
Peak memory 216540 kb
Host smart-6082f0b7-e35d-4a0e-a1c0-5046c0dd7023
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865861638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.865861638
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1203743343
Short name T409
Test name
Test status
Simulation time 403524886 ps
CPU time 67.69 seconds
Started Aug 11 07:07:15 PM PDT 24
Finished Aug 11 07:08:22 PM PDT 24
Peak memory 213140 kb
Host smart-d24add2f-81f5-48a7-84a0-01cbcc1f70cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203743343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1203743343
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1281747821
Short name T344
Test name
Test status
Simulation time 277879115 ps
CPU time 5.28 seconds
Started Aug 11 07:07:19 PM PDT 24
Finished Aug 11 07:07:24 PM PDT 24
Peak memory 219460 kb
Host smart-c843a7bd-6f98-4ce1-bfd4-34b1f25608c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281747821 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1281747821
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4227161907
Short name T419
Test name
Test status
Simulation time 334384730 ps
CPU time 4.22 seconds
Started Aug 11 07:07:19 PM PDT 24
Finished Aug 11 07:07:23 PM PDT 24
Peak memory 219424 kb
Host smart-9c014481-7f0b-4413-b7e7-6563e75ce6bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227161907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.4227161907
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1243326971
Short name T77
Test name
Test status
Simulation time 804968535 ps
CPU time 33.13 seconds
Started Aug 11 07:07:14 PM PDT 24
Finished Aug 11 07:07:48 PM PDT 24
Peak memory 212660 kb
Host smart-a50b1629-46e6-4ecd-ac2b-efdfd0db8c4f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243326971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1243326971
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.76641719
Short name T417
Test name
Test status
Simulation time 101631381 ps
CPU time 6.37 seconds
Started Aug 11 07:07:18 PM PDT 24
Finished Aug 11 07:07:24 PM PDT 24
Peak memory 219524 kb
Host smart-ec7f22ac-edd7-458d-9095-62bf070a3599
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76641719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ct
rl_same_csr_outstanding.76641719
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1053215141
Short name T382
Test name
Test status
Simulation time 86595410 ps
CPU time 6.21 seconds
Started Aug 11 07:07:15 PM PDT 24
Finished Aug 11 07:07:22 PM PDT 24
Peak memory 217392 kb
Host smart-29edabdd-7e34-49d0-a836-b375ccc13858
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053215141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1053215141
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3497315584
Short name T380
Test name
Test status
Simulation time 279415009 ps
CPU time 5.5 seconds
Started Aug 11 07:07:14 PM PDT 24
Finished Aug 11 07:07:19 PM PDT 24
Peak memory 215092 kb
Host smart-120a99d0-b55c-4b3e-9d03-a49892a12376
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497315584 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3497315584
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.669520072
Short name T347
Test name
Test status
Simulation time 298598794 ps
CPU time 4.24 seconds
Started Aug 11 07:07:14 PM PDT 24
Finished Aug 11 07:07:19 PM PDT 24
Peak memory 218592 kb
Host smart-9a247e05-b255-4885-909e-59dd6b4028c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669520072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.669520072
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2835302717
Short name T91
Test name
Test status
Simulation time 1197075633 ps
CPU time 33.01 seconds
Started Aug 11 07:07:17 PM PDT 24
Finished Aug 11 07:07:50 PM PDT 24
Peak memory 211372 kb
Host smart-f459cbed-2092-4bc2-b856-56e2ad73494b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835302717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2835302717
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.49458441
Short name T359
Test name
Test status
Simulation time 252285521 ps
CPU time 5.12 seconds
Started Aug 11 07:07:19 PM PDT 24
Finished Aug 11 07:07:24 PM PDT 24
Peak memory 219096 kb
Host smart-558910a2-11fa-4ee7-bacb-c9787034477e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49458441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ct
rl_same_csr_outstanding.49458441
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1728220537
Short name T376
Test name
Test status
Simulation time 336470379 ps
CPU time 6.7 seconds
Started Aug 11 07:07:19 PM PDT 24
Finished Aug 11 07:07:26 PM PDT 24
Peak memory 215252 kb
Host smart-08a0dbee-1bc8-4766-8baa-b26c38a5b36c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728220537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1728220537
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2666901650
Short name T354
Test name
Test status
Simulation time 2061857166 ps
CPU time 7.13 seconds
Started Aug 11 07:07:20 PM PDT 24
Finished Aug 11 07:07:27 PM PDT 24
Peak memory 216756 kb
Host smart-4e206276-4798-4f48-8f40-0a845428cc94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666901650 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2666901650
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2245506416
Short name T403
Test name
Test status
Simulation time 257732662 ps
CPU time 5.22 seconds
Started Aug 11 07:07:22 PM PDT 24
Finished Aug 11 07:07:28 PM PDT 24
Peak memory 211264 kb
Host smart-45dc0a2a-5e23-4a55-a8cd-27017eb19439
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245506416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2245506416
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3170848310
Short name T89
Test name
Test status
Simulation time 554792008 ps
CPU time 28.56 seconds
Started Aug 11 07:07:17 PM PDT 24
Finished Aug 11 07:07:46 PM PDT 24
Peak memory 211448 kb
Host smart-8ae7e6ec-ea58-4ea7-a743-9777493aab0a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170848310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3170848310
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1340497283
Short name T430
Test name
Test status
Simulation time 535245874 ps
CPU time 6.58 seconds
Started Aug 11 07:07:22 PM PDT 24
Finished Aug 11 07:07:29 PM PDT 24
Peak memory 219496 kb
Host smart-bb56c906-b5c8-4344-932c-68d8bd2d50e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340497283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1340497283
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3156215152
Short name T373
Test name
Test status
Simulation time 104996603 ps
CPU time 8.11 seconds
Started Aug 11 07:07:19 PM PDT 24
Finished Aug 11 07:07:27 PM PDT 24
Peak memory 219640 kb
Host smart-6dc29277-79af-4938-b016-b1df840d274d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156215152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3156215152
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.34696720
Short name T366
Test name
Test status
Simulation time 425864862 ps
CPU time 38.21 seconds
Started Aug 11 07:07:22 PM PDT 24
Finished Aug 11 07:08:01 PM PDT 24
Peak memory 219520 kb
Host smart-1343b46d-5867-448d-b6a3-76adda7bf743
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34696720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_int
g_err.34696720
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2617109911
Short name T393
Test name
Test status
Simulation time 279415258 ps
CPU time 5.61 seconds
Started Aug 11 07:07:21 PM PDT 24
Finished Aug 11 07:07:26 PM PDT 24
Peak memory 215324 kb
Host smart-b382669f-e150-4157-9324-a7d365c05041
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617109911 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2617109911
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2972920169
Short name T83
Test name
Test status
Simulation time 1377954497 ps
CPU time 4.2 seconds
Started Aug 11 07:07:23 PM PDT 24
Finished Aug 11 07:07:27 PM PDT 24
Peak memory 218672 kb
Host smart-2d2ea6ef-6e2d-4615-aa8a-cc0ae088bccf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972920169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2972920169
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.644205199
Short name T80
Test name
Test status
Simulation time 570773691 ps
CPU time 27.57 seconds
Started Aug 11 07:07:21 PM PDT 24
Finished Aug 11 07:07:49 PM PDT 24
Peak memory 211368 kb
Host smart-77ab1074-f76d-4fa2-88ee-fe135c051d57
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644205199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.644205199
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.462736109
Short name T371
Test name
Test status
Simulation time 90100011 ps
CPU time 4.59 seconds
Started Aug 11 07:07:20 PM PDT 24
Finished Aug 11 07:07:24 PM PDT 24
Peak memory 211312 kb
Host smart-66e21247-1cb8-44b4-8ed3-741b121eefdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462736109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.462736109
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2044214475
Short name T377
Test name
Test status
Simulation time 103054502 ps
CPU time 8.17 seconds
Started Aug 11 07:07:21 PM PDT 24
Finished Aug 11 07:07:30 PM PDT 24
Peak memory 219600 kb
Host smart-3ebb32b0-f316-48b9-b11b-3049acf54f05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044214475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2044214475
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4165528230
Short name T348
Test name
Test status
Simulation time 572442102 ps
CPU time 5.86 seconds
Started Aug 11 07:07:23 PM PDT 24
Finished Aug 11 07:07:28 PM PDT 24
Peak memory 219612 kb
Host smart-9c7488df-1fcd-497e-b830-6930c6f735c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165528230 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.4165528230
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.131747833
Short name T410
Test name
Test status
Simulation time 126558091 ps
CPU time 5.17 seconds
Started Aug 11 07:07:20 PM PDT 24
Finished Aug 11 07:07:26 PM PDT 24
Peak memory 218336 kb
Host smart-5e882e7e-71bb-41c8-9692-dd707f1c2348
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131747833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.131747833
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3559343714
Short name T102
Test name
Test status
Simulation time 370183449 ps
CPU time 18.5 seconds
Started Aug 11 07:07:20 PM PDT 24
Finished Aug 11 07:07:39 PM PDT 24
Peak memory 211380 kb
Host smart-824f060a-3a08-45a9-9f66-df446d2571fa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559343714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3559343714
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2731550187
Short name T62
Test name
Test status
Simulation time 544487885 ps
CPU time 7.04 seconds
Started Aug 11 07:07:22 PM PDT 24
Finished Aug 11 07:07:29 PM PDT 24
Peak memory 218884 kb
Host smart-ebbaa03b-84ec-4b37-865e-e8eaa1c3fd7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731550187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2731550187
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2034761778
Short name T353
Test name
Test status
Simulation time 126888648 ps
CPU time 7.77 seconds
Started Aug 11 07:07:22 PM PDT 24
Finished Aug 11 07:07:30 PM PDT 24
Peak memory 219644 kb
Host smart-09b6c3a7-4cab-4eec-a289-1463c72d9855
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034761778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2034761778
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3406581352
Short name T389
Test name
Test status
Simulation time 194742783 ps
CPU time 5.62 seconds
Started Aug 11 07:07:29 PM PDT 24
Finished Aug 11 07:07:35 PM PDT 24
Peak memory 215864 kb
Host smart-d3fb0fe5-948f-46bb-9f0d-93ea4efd7ebf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406581352 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3406581352
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.319024843
Short name T368
Test name
Test status
Simulation time 131085089 ps
CPU time 4.96 seconds
Started Aug 11 07:07:26 PM PDT 24
Finished Aug 11 07:07:32 PM PDT 24
Peak memory 211232 kb
Host smart-5cb7fc21-262d-40f5-9da3-1e20a1ada35c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319024843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.319024843
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.469549415
Short name T411
Test name
Test status
Simulation time 7441716316 ps
CPU time 21.99 seconds
Started Aug 11 07:07:27 PM PDT 24
Finished Aug 11 07:07:49 PM PDT 24
Peak memory 211500 kb
Host smart-c83631d1-fd05-4fae-be6b-4609772aa16b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469549415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.469549415
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1222933689
Short name T385
Test name
Test status
Simulation time 130844537 ps
CPU time 5.09 seconds
Started Aug 11 07:07:27 PM PDT 24
Finished Aug 11 07:07:32 PM PDT 24
Peak memory 211556 kb
Host smart-08d0a1ed-14fa-402e-b8b0-173d6743603b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222933689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1222933689
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2787547981
Short name T386
Test name
Test status
Simulation time 126991980 ps
CPU time 8.73 seconds
Started Aug 11 07:07:31 PM PDT 24
Finished Aug 11 07:07:40 PM PDT 24
Peak memory 216544 kb
Host smart-fb19b255-0303-4935-8b83-211308ee6060
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787547981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2787547981
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1272170901
Short name T375
Test name
Test status
Simulation time 550725746 ps
CPU time 5.34 seconds
Started Aug 11 07:07:29 PM PDT 24
Finished Aug 11 07:07:35 PM PDT 24
Peak memory 219608 kb
Host smart-4f5f9a6f-e8f1-4a93-b42b-30b85fd9d6d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272170901 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1272170901
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4202347433
Short name T93
Test name
Test status
Simulation time 654623589 ps
CPU time 5.21 seconds
Started Aug 11 07:07:28 PM PDT 24
Finished Aug 11 07:07:34 PM PDT 24
Peak memory 211284 kb
Host smart-3a5458b3-3028-43b5-8375-30e01db8520c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202347433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.4202347433
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.548140327
Short name T431
Test name
Test status
Simulation time 3275718774 ps
CPU time 33.13 seconds
Started Aug 11 07:07:26 PM PDT 24
Finished Aug 11 07:08:00 PM PDT 24
Peak memory 211464 kb
Host smart-df16dcb3-e106-4b86-a28c-1478801ac997
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548140327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.548140327
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.558275726
Short name T92
Test name
Test status
Simulation time 88911342 ps
CPU time 4.23 seconds
Started Aug 11 07:07:26 PM PDT 24
Finished Aug 11 07:07:30 PM PDT 24
Peak memory 218700 kb
Host smart-40cb8939-2b5d-4746-b858-fb3e836e51dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558275726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.558275726
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.550566293
Short name T370
Test name
Test status
Simulation time 295489268 ps
CPU time 10.06 seconds
Started Aug 11 07:07:26 PM PDT 24
Finished Aug 11 07:07:36 PM PDT 24
Peak memory 216484 kb
Host smart-6176e302-a450-470b-a551-fff7347059f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550566293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.550566293
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1219850803
Short name T383
Test name
Test status
Simulation time 1195687845 ps
CPU time 38.69 seconds
Started Aug 11 07:07:28 PM PDT 24
Finished Aug 11 07:08:07 PM PDT 24
Peak memory 211876 kb
Host smart-2112b629-307a-4e26-bf04-8362ad640b83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219850803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1219850803
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3009982717
Short name T343
Test name
Test status
Simulation time 512340883 ps
CPU time 5.56 seconds
Started Aug 11 07:07:36 PM PDT 24
Finished Aug 11 07:07:42 PM PDT 24
Peak memory 219628 kb
Host smart-337640e1-2014-418e-8418-d1115c27ba06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009982717 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3009982717
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.743809364
Short name T397
Test name
Test status
Simulation time 86661389 ps
CPU time 4.3 seconds
Started Aug 11 07:07:33 PM PDT 24
Finished Aug 11 07:07:38 PM PDT 24
Peak memory 219420 kb
Host smart-237bc25f-7319-41e0-aba4-0c2cbef1481f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743809364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.743809364
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3029665840
Short name T90
Test name
Test status
Simulation time 377048553 ps
CPU time 18.47 seconds
Started Aug 11 07:07:28 PM PDT 24
Finished Aug 11 07:07:47 PM PDT 24
Peak memory 211340 kb
Host smart-18331486-272a-4524-af5c-79e1386db67d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029665840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3029665840
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1951591376
Short name T413
Test name
Test status
Simulation time 129378079 ps
CPU time 5.25 seconds
Started Aug 11 07:07:36 PM PDT 24
Finished Aug 11 07:07:41 PM PDT 24
Peak memory 218764 kb
Host smart-c7477ff6-ffeb-4313-a372-38d5448c9668
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951591376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1951591376
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1611225313
Short name T335
Test name
Test status
Simulation time 171848395 ps
CPU time 6.54 seconds
Started Aug 11 07:07:28 PM PDT 24
Finished Aug 11 07:07:34 PM PDT 24
Peak memory 219544 kb
Host smart-8fce96ed-1c20-46b9-9125-bca3ef5913d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611225313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1611225313
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.799450976
Short name T378
Test name
Test status
Simulation time 408925548 ps
CPU time 38.3 seconds
Started Aug 11 07:07:34 PM PDT 24
Finished Aug 11 07:08:12 PM PDT 24
Peak memory 212988 kb
Host smart-7ccecff0-e4a3-430b-947e-c534b3689d22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799450976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.799450976
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1707060516
Short name T356
Test name
Test status
Simulation time 85824297 ps
CPU time 4.34 seconds
Started Aug 11 07:06:52 PM PDT 24
Finished Aug 11 07:06:57 PM PDT 24
Peak memory 211228 kb
Host smart-19e6509c-8ee4-44b9-8b33-f77d276e501b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707060516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1707060516
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2137573455
Short name T432
Test name
Test status
Simulation time 271693762 ps
CPU time 5.33 seconds
Started Aug 11 07:06:51 PM PDT 24
Finished Aug 11 07:06:56 PM PDT 24
Peak memory 217688 kb
Host smart-f1087da5-eea6-458f-af17-5161143a30c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137573455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2137573455
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.598454009
Short name T394
Test name
Test status
Simulation time 130888462 ps
CPU time 8.13 seconds
Started Aug 11 07:06:52 PM PDT 24
Finished Aug 11 07:07:00 PM PDT 24
Peak memory 211312 kb
Host smart-da232a15-8f21-4e19-b645-221d34af17e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598454009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.598454009
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2791326508
Short name T340
Test name
Test status
Simulation time 140179032 ps
CPU time 6.05 seconds
Started Aug 11 07:06:51 PM PDT 24
Finished Aug 11 07:06:57 PM PDT 24
Peak memory 219544 kb
Host smart-67f749c6-6e55-4acc-99e9-e0d6ce41fbc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791326508 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2791326508
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.244748466
Short name T88
Test name
Test status
Simulation time 126585848 ps
CPU time 5.2 seconds
Started Aug 11 07:06:51 PM PDT 24
Finished Aug 11 07:06:56 PM PDT 24
Peak memory 211260 kb
Host smart-ef5a7263-33ac-4220-b89f-7d1675efb71b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244748466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.244748466
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3677589570
Short name T336
Test name
Test status
Simulation time 391781015 ps
CPU time 5.1 seconds
Started Aug 11 07:06:52 PM PDT 24
Finished Aug 11 07:06:57 PM PDT 24
Peak memory 211232 kb
Host smart-760ec631-3e0a-4a44-b458-329deb9dffb6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677589570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3677589570
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1787544219
Short name T338
Test name
Test status
Simulation time 85798686 ps
CPU time 4.28 seconds
Started Aug 11 07:06:53 PM PDT 24
Finished Aug 11 07:06:57 PM PDT 24
Peak memory 211232 kb
Host smart-53b8fca1-2c7c-4ebd-9dd9-183d27bdcea4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787544219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1787544219
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3049531252
Short name T94
Test name
Test status
Simulation time 2154602647 ps
CPU time 27.53 seconds
Started Aug 11 07:06:52 PM PDT 24
Finished Aug 11 07:07:20 PM PDT 24
Peak memory 211476 kb
Host smart-fa32e826-9420-4f9c-9095-06a4df0c4ab4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049531252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3049531252
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2239862569
Short name T406
Test name
Test status
Simulation time 520460593 ps
CPU time 5.18 seconds
Started Aug 11 07:06:52 PM PDT 24
Finished Aug 11 07:06:58 PM PDT 24
Peak memory 218456 kb
Host smart-78b50f30-6ac4-46c6-9f29-c5253f7dec04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239862569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2239862569
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1996095106
Short name T364
Test name
Test status
Simulation time 290026896 ps
CPU time 9.36 seconds
Started Aug 11 07:06:53 PM PDT 24
Finished Aug 11 07:07:02 PM PDT 24
Peak memory 215712 kb
Host smart-947555b8-f840-4aa0-9350-a3a9621abd40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996095106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1996095106
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1023019933
Short name T59
Test name
Test status
Simulation time 536500259 ps
CPU time 37.51 seconds
Started Aug 11 07:06:52 PM PDT 24
Finished Aug 11 07:07:29 PM PDT 24
Peak memory 211844 kb
Host smart-8c937941-e201-498f-a31a-3f09ab532008
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023019933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1023019933
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1348152234
Short name T355
Test name
Test status
Simulation time 283696714 ps
CPU time 5.09 seconds
Started Aug 11 07:06:57 PM PDT 24
Finished Aug 11 07:07:02 PM PDT 24
Peak memory 211312 kb
Host smart-1b5d1e50-5061-4449-aa05-7333026c26e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348152234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1348152234
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3375532517
Short name T350
Test name
Test status
Simulation time 92540428 ps
CPU time 5.9 seconds
Started Aug 11 07:06:57 PM PDT 24
Finished Aug 11 07:07:03 PM PDT 24
Peak memory 211312 kb
Host smart-eab9de5e-8e62-4c3d-925f-8ff469c33b22
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375532517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3375532517
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3814991676
Short name T379
Test name
Test status
Simulation time 138657051 ps
CPU time 5.63 seconds
Started Aug 11 07:06:58 PM PDT 24
Finished Aug 11 07:07:03 PM PDT 24
Peak memory 219624 kb
Host smart-9e713bca-0ae0-4f21-8a35-53b86a0fc74d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814991676 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3814991676
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1487645657
Short name T427
Test name
Test status
Simulation time 140214515 ps
CPU time 4.86 seconds
Started Aug 11 07:06:58 PM PDT 24
Finished Aug 11 07:07:03 PM PDT 24
Peak memory 217852 kb
Host smart-3a42da74-5355-4b51-8cca-7051fdc9bfcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487645657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1487645657
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2675850358
Short name T415
Test name
Test status
Simulation time 94929971 ps
CPU time 4.18 seconds
Started Aug 11 07:06:57 PM PDT 24
Finished Aug 11 07:07:02 PM PDT 24
Peak memory 211256 kb
Host smart-4963a7fd-a1f0-46dc-a608-5f7e8ccfd2b9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675850358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2675850358
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1092889631
Short name T339
Test name
Test status
Simulation time 332695324 ps
CPU time 4.12 seconds
Started Aug 11 07:06:58 PM PDT 24
Finished Aug 11 07:07:02 PM PDT 24
Peak memory 211152 kb
Host smart-c1151e94-71ca-4c5d-bcdf-f76b6aef910e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092889631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1092889631
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.591273319
Short name T81
Test name
Test status
Simulation time 2250187753 ps
CPU time 21.91 seconds
Started Aug 11 07:06:57 PM PDT 24
Finished Aug 11 07:07:19 PM PDT 24
Peak memory 211472 kb
Host smart-05fa4139-d307-4b8d-a3cc-5434f628542f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591273319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.591273319
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.601596374
Short name T420
Test name
Test status
Simulation time 958906782 ps
CPU time 6.91 seconds
Started Aug 11 07:06:57 PM PDT 24
Finished Aug 11 07:07:04 PM PDT 24
Peak memory 211364 kb
Host smart-3eb3f658-c60f-4ba3-98bd-420e46a3059f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601596374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.601596374
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2121855266
Short name T341
Test name
Test status
Simulation time 137573855 ps
CPU time 7.66 seconds
Started Aug 11 07:06:57 PM PDT 24
Finished Aug 11 07:07:04 PM PDT 24
Peak memory 219568 kb
Host smart-6a317584-b05d-4e2f-9e57-5315d4d27485
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121855266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2121855266
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3110114294
Short name T107
Test name
Test status
Simulation time 1457816339 ps
CPU time 37.68 seconds
Started Aug 11 07:06:59 PM PDT 24
Finished Aug 11 07:07:37 PM PDT 24
Peak memory 219468 kb
Host smart-3de396e0-d3c8-478d-bd8f-265f02a57112
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110114294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3110114294
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3434410186
Short name T85
Test name
Test status
Simulation time 167811022 ps
CPU time 4.26 seconds
Started Aug 11 07:07:01 PM PDT 24
Finished Aug 11 07:07:05 PM PDT 24
Peak memory 211188 kb
Host smart-8361553d-e216-4cde-98c8-a02b609aa41d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434410186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3434410186
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.984187248
Short name T342
Test name
Test status
Simulation time 177232948 ps
CPU time 4.42 seconds
Started Aug 11 07:07:01 PM PDT 24
Finished Aug 11 07:07:06 PM PDT 24
Peak memory 219408 kb
Host smart-6c48e4d5-d953-4129-bd7e-c405f5698373
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984187248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.984187248
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3566314879
Short name T365
Test name
Test status
Simulation time 350937472 ps
CPU time 7.41 seconds
Started Aug 11 07:07:00 PM PDT 24
Finished Aug 11 07:07:08 PM PDT 24
Peak memory 211244 kb
Host smart-24f567f0-4802-4b9f-b89f-d95ace5fef76
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566314879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3566314879
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1678739962
Short name T349
Test name
Test status
Simulation time 813525327 ps
CPU time 5.31 seconds
Started Aug 11 07:07:01 PM PDT 24
Finished Aug 11 07:07:06 PM PDT 24
Peak memory 213844 kb
Host smart-02f4df8d-259b-4fcf-8234-710111253d3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678739962 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1678739962
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.320840706
Short name T74
Test name
Test status
Simulation time 128586216 ps
CPU time 5.11 seconds
Started Aug 11 07:07:00 PM PDT 24
Finished Aug 11 07:07:06 PM PDT 24
Peak memory 211268 kb
Host smart-8fb158ad-09ee-4052-b0a8-979a11eb8540
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320840706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.320840706
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2752536649
Short name T372
Test name
Test status
Simulation time 85616302 ps
CPU time 4.2 seconds
Started Aug 11 07:07:03 PM PDT 24
Finished Aug 11 07:07:07 PM PDT 24
Peak memory 211248 kb
Host smart-88fb1026-da3f-4730-963e-20a2e7cc78fa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752536649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2752536649
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3167487682
Short name T390
Test name
Test status
Simulation time 320107944 ps
CPU time 4.26 seconds
Started Aug 11 07:06:57 PM PDT 24
Finished Aug 11 07:07:02 PM PDT 24
Peak memory 211156 kb
Host smart-c3d271b7-b674-431e-96ad-4d917380f0b7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167487682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3167487682
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1323680048
Short name T72
Test name
Test status
Simulation time 2532969569 ps
CPU time 33.66 seconds
Started Aug 11 07:06:59 PM PDT 24
Finished Aug 11 07:07:33 PM PDT 24
Peak memory 211432 kb
Host smart-be4ea6ce-d6d0-4a2a-bc45-6ea1e45ceebf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323680048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1323680048
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.523180779
Short name T396
Test name
Test status
Simulation time 520008305 ps
CPU time 5.23 seconds
Started Aug 11 07:07:02 PM PDT 24
Finished Aug 11 07:07:08 PM PDT 24
Peak memory 218780 kb
Host smart-1a58ad2c-8c63-4c34-9fe7-027b9806ccbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523180779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.523180779
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3343535448
Short name T361
Test name
Test status
Simulation time 1974293723 ps
CPU time 11.85 seconds
Started Aug 11 07:06:57 PM PDT 24
Finished Aug 11 07:07:09 PM PDT 24
Peak memory 216572 kb
Host smart-0bec84a2-e97e-4b20-ac0a-331943c8e2e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343535448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3343535448
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2135175397
Short name T111
Test name
Test status
Simulation time 345916626 ps
CPU time 38.21 seconds
Started Aug 11 07:06:56 PM PDT 24
Finished Aug 11 07:07:34 PM PDT 24
Peak memory 213004 kb
Host smart-8710e0d6-0f26-4586-9b31-699ec931c235
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135175397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2135175397
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1910097823
Short name T388
Test name
Test status
Simulation time 295790781 ps
CPU time 6.03 seconds
Started Aug 11 07:07:09 PM PDT 24
Finished Aug 11 07:07:15 PM PDT 24
Peak memory 215968 kb
Host smart-a54a25f3-9acd-4423-b14b-b54bc32cfea5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910097823 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1910097823
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3486695067
Short name T421
Test name
Test status
Simulation time 169288186 ps
CPU time 4.43 seconds
Started Aug 11 07:07:02 PM PDT 24
Finished Aug 11 07:07:07 PM PDT 24
Peak memory 211252 kb
Host smart-1da4da9a-7a47-4f81-90c7-9be970ba81dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486695067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3486695067
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2888401548
Short name T87
Test name
Test status
Simulation time 2721731198 ps
CPU time 32.88 seconds
Started Aug 11 07:07:02 PM PDT 24
Finished Aug 11 07:07:35 PM PDT 24
Peak memory 211492 kb
Host smart-53230636-3b6e-4dd5-a530-f6648bd4ca93
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888401548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2888401548
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2682873614
Short name T422
Test name
Test status
Simulation time 518301006 ps
CPU time 5.02 seconds
Started Aug 11 07:07:04 PM PDT 24
Finished Aug 11 07:07:10 PM PDT 24
Peak memory 211368 kb
Host smart-80daee18-2f22-45d9-844e-60f05fcea769
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682873614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2682873614
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4129763440
Short name T351
Test name
Test status
Simulation time 136448930 ps
CPU time 8.43 seconds
Started Aug 11 07:07:09 PM PDT 24
Finished Aug 11 07:07:18 PM PDT 24
Peak memory 216640 kb
Host smart-bd68d970-2ec7-4cd3-a668-b02384db44d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129763440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.4129763440
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.876432322
Short name T374
Test name
Test status
Simulation time 89597235 ps
CPU time 4.65 seconds
Started Aug 11 07:07:09 PM PDT 24
Finished Aug 11 07:07:14 PM PDT 24
Peak memory 219576 kb
Host smart-8e4ea015-a2c7-4347-8ee6-50db8c6395c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876432322 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.876432322
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4175963382
Short name T418
Test name
Test status
Simulation time 250529236 ps
CPU time 4.97 seconds
Started Aug 11 07:07:07 PM PDT 24
Finished Aug 11 07:07:12 PM PDT 24
Peak memory 217908 kb
Host smart-f47a98e1-ee33-4c9b-be36-abc6021aefd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175963382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.4175963382
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1185083680
Short name T76
Test name
Test status
Simulation time 2238216199 ps
CPU time 27.65 seconds
Started Aug 11 07:07:03 PM PDT 24
Finished Aug 11 07:07:30 PM PDT 24
Peak memory 211388 kb
Host smart-f05a3ba9-1b88-4551-b728-f8d0d56ee57a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185083680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1185083680
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3629829601
Short name T73
Test name
Test status
Simulation time 127533174 ps
CPU time 5.09 seconds
Started Aug 11 07:07:07 PM PDT 24
Finished Aug 11 07:07:12 PM PDT 24
Peak memory 211320 kb
Host smart-f1bcef8c-70b3-4c41-9fa5-a0a810e35abb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629829601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3629829601
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.329284051
Short name T408
Test name
Test status
Simulation time 174750639 ps
CPU time 8.67 seconds
Started Aug 11 07:07:09 PM PDT 24
Finished Aug 11 07:07:18 PM PDT 24
Peak memory 215880 kb
Host smart-5087d601-f5d2-486f-8e3a-8d42d03d958c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329284051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.329284051
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1529408690
Short name T105
Test name
Test status
Simulation time 274705923 ps
CPU time 39.48 seconds
Started Aug 11 07:07:01 PM PDT 24
Finished Aug 11 07:07:40 PM PDT 24
Peak memory 214120 kb
Host smart-da57dc18-4043-4621-a93b-7cd2307725bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529408690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1529408690
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3296431657
Short name T362
Test name
Test status
Simulation time 532805373 ps
CPU time 5.73 seconds
Started Aug 11 07:07:09 PM PDT 24
Finished Aug 11 07:07:14 PM PDT 24
Peak memory 214372 kb
Host smart-7fd49266-4cfa-4e52-88f1-4fb0a7781f1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296431657 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3296431657
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.705587603
Short name T86
Test name
Test status
Simulation time 517660676 ps
CPU time 5.06 seconds
Started Aug 11 07:07:11 PM PDT 24
Finished Aug 11 07:07:16 PM PDT 24
Peak memory 218336 kb
Host smart-e3e997dc-2b6b-481a-b219-cba080848185
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705587603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.705587603
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.109006685
Short name T404
Test name
Test status
Simulation time 1569550374 ps
CPU time 32.95 seconds
Started Aug 11 07:07:10 PM PDT 24
Finished Aug 11 07:07:43 PM PDT 24
Peak memory 211412 kb
Host smart-1f836fab-d458-40da-ab71-9b26fb17347d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109006685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.109006685
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2075564170
Short name T75
Test name
Test status
Simulation time 1132276227 ps
CPU time 5.28 seconds
Started Aug 11 07:07:10 PM PDT 24
Finished Aug 11 07:07:16 PM PDT 24
Peak memory 218832 kb
Host smart-ea0c7f8b-0fd2-48ed-8161-44d3a494d02c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075564170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2075564170
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4108804488
Short name T358
Test name
Test status
Simulation time 602245848 ps
CPU time 9.75 seconds
Started Aug 11 07:07:09 PM PDT 24
Finished Aug 11 07:07:19 PM PDT 24
Peak memory 219664 kb
Host smart-3afa1af3-d67b-480d-af82-15581b123cbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108804488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.4108804488
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3125432025
Short name T60
Test name
Test status
Simulation time 583931618 ps
CPU time 39.3 seconds
Started Aug 11 07:07:10 PM PDT 24
Finished Aug 11 07:07:49 PM PDT 24
Peak memory 219472 kb
Host smart-cb54c50f-d70e-4b4c-9be1-e00ccaf5fe1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125432025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3125432025
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1716712678
Short name T395
Test name
Test status
Simulation time 428417308 ps
CPU time 5.34 seconds
Started Aug 11 07:07:07 PM PDT 24
Finished Aug 11 07:07:13 PM PDT 24
Peak memory 216300 kb
Host smart-db72b5ae-15dc-49f8-93d7-6b854b1a0a0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716712678 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1716712678
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2036642101
Short name T391
Test name
Test status
Simulation time 172827542 ps
CPU time 4.32 seconds
Started Aug 11 07:07:09 PM PDT 24
Finished Aug 11 07:07:14 PM PDT 24
Peak memory 219392 kb
Host smart-a2928ebe-59c6-4a0f-828d-1988906835fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036642101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2036642101
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.143906462
Short name T71
Test name
Test status
Simulation time 810658319 ps
CPU time 32.39 seconds
Started Aug 11 07:07:08 PM PDT 24
Finished Aug 11 07:07:40 PM PDT 24
Peak memory 211380 kb
Host smart-6e383e83-8a10-4146-bb07-dc3b73885eed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143906462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.143906462
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3543167190
Short name T367
Test name
Test status
Simulation time 2437598636 ps
CPU time 9.33 seconds
Started Aug 11 07:07:08 PM PDT 24
Finished Aug 11 07:07:18 PM PDT 24
Peak memory 219568 kb
Host smart-89d188ec-45d8-4c32-910c-4cf00c95027c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543167190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3543167190
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1712327924
Short name T407
Test name
Test status
Simulation time 126979192 ps
CPU time 7.73 seconds
Started Aug 11 07:07:10 PM PDT 24
Finished Aug 11 07:07:18 PM PDT 24
Peak memory 216308 kb
Host smart-a541952d-1b8b-4564-8822-38fc7e494831
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712327924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1712327924
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1642845280
Short name T110
Test name
Test status
Simulation time 1246917827 ps
CPU time 82.2 seconds
Started Aug 11 07:07:08 PM PDT 24
Finished Aug 11 07:08:30 PM PDT 24
Peak memory 214220 kb
Host smart-800f8d61-a54f-4180-bd59-2362f7117f58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642845280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1642845280
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2212230544
Short name T402
Test name
Test status
Simulation time 113708360 ps
CPU time 5.5 seconds
Started Aug 11 07:07:10 PM PDT 24
Finished Aug 11 07:07:15 PM PDT 24
Peak memory 215964 kb
Host smart-51a28079-7d32-461c-8b4b-a3e2980fe29c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212230544 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2212230544
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3539963385
Short name T360
Test name
Test status
Simulation time 87427358 ps
CPU time 4.25 seconds
Started Aug 11 07:07:08 PM PDT 24
Finished Aug 11 07:07:12 PM PDT 24
Peak memory 211312 kb
Host smart-2c98a3ac-682d-4917-b450-b89c3b6820c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539963385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3539963385
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2945272810
Short name T363
Test name
Test status
Simulation time 99023398 ps
CPU time 6.3 seconds
Started Aug 11 07:07:09 PM PDT 24
Finished Aug 11 07:07:15 PM PDT 24
Peak memory 211384 kb
Host smart-5554a4b9-dc44-4dc0-bcdf-b0ad81f5888d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945272810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2945272810
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.661412876
Short name T399
Test name
Test status
Simulation time 133557112 ps
CPU time 7.08 seconds
Started Aug 11 07:07:08 PM PDT 24
Finished Aug 11 07:07:15 PM PDT 24
Peak memory 219608 kb
Host smart-fe5e5840-6a57-4d2d-bfae-ad494b5716f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661412876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.661412876
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2447843697
Short name T423
Test name
Test status
Simulation time 295399586 ps
CPU time 72.09 seconds
Started Aug 11 07:07:08 PM PDT 24
Finished Aug 11 07:08:21 PM PDT 24
Peak memory 219536 kb
Host smart-947119a2-1d37-4e11-9da1-809c887cf561
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447843697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2447843697
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2560068724
Short name T193
Test name
Test status
Simulation time 260508132 ps
CPU time 5.17 seconds
Started Aug 11 06:13:34 PM PDT 24
Finished Aug 11 06:13:39 PM PDT 24
Peak memory 212028 kb
Host smart-07d02d37-35f5-4423-9d0e-c346df266fb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560068724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2560068724
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3311712144
Short name T37
Test name
Test status
Simulation time 1972254791 ps
CPU time 114.12 seconds
Started Aug 11 06:13:29 PM PDT 24
Finished Aug 11 06:15:23 PM PDT 24
Peak memory 225528 kb
Host smart-900862ce-35a5-41e7-a1ab-1e8ade29823c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311712144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3311712144
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2118750594
Short name T203
Test name
Test status
Simulation time 276821115 ps
CPU time 11.3 seconds
Started Aug 11 06:13:37 PM PDT 24
Finished Aug 11 06:13:48 PM PDT 24
Peak memory 212860 kb
Host smart-8301c376-8c64-4639-9f98-c656e31a5a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118750594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2118750594
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2830982323
Short name T68
Test name
Test status
Simulation time 358686758 ps
CPU time 5.52 seconds
Started Aug 11 06:13:24 PM PDT 24
Finished Aug 11 06:13:29 PM PDT 24
Peak memory 212336 kb
Host smart-afb57007-7edc-4cd1-9d32-846b6ee9c1c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2830982323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2830982323
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3922635891
Short name T22
Test name
Test status
Simulation time 557178518 ps
CPU time 101.26 seconds
Started Aug 11 06:13:23 PM PDT 24
Finished Aug 11 06:15:05 PM PDT 24
Peak memory 239136 kb
Host smart-95a851cb-9ac9-4332-92fa-50441dbcd755
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922635891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3922635891
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.688191024
Short name T296
Test name
Test status
Simulation time 299513559 ps
CPU time 6.32 seconds
Started Aug 11 06:13:27 PM PDT 24
Finished Aug 11 06:13:34 PM PDT 24
Peak memory 212136 kb
Host smart-ba145df9-bd44-493c-9b47-25ce7c4fdd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688191024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.688191024
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.279061048
Short name T322
Test name
Test status
Simulation time 168703894 ps
CPU time 9.77 seconds
Started Aug 11 06:13:32 PM PDT 24
Finished Aug 11 06:13:41 PM PDT 24
Peak memory 212100 kb
Host smart-3a0c704c-931b-4d08-ba10-56b8c431305e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279061048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.279061048
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2994554807
Short name T208
Test name
Test status
Simulation time 160793605083 ps
CPU time 1543.15 seconds
Started Aug 11 06:13:25 PM PDT 24
Finished Aug 11 06:39:08 PM PDT 24
Peak memory 236688 kb
Host smart-69e47714-800a-43a2-ac6a-bc7eb22c5982
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994554807 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.2994554807
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3422106973
Short name T223
Test name
Test status
Simulation time 254950946 ps
CPU time 5.19 seconds
Started Aug 11 06:13:24 PM PDT 24
Finished Aug 11 06:13:29 PM PDT 24
Peak memory 212076 kb
Host smart-9e4b2924-8d88-4db5-8336-599f79a1a4bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422106973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3422106973
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.184959310
Short name T265
Test name
Test status
Simulation time 3787723630 ps
CPU time 115.77 seconds
Started Aug 11 06:13:29 PM PDT 24
Finished Aug 11 06:15:25 PM PDT 24
Peak memory 234432 kb
Host smart-d05fd6f4-93b2-4137-87c8-0dde1edc56b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184959310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.184959310
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2699249504
Short name T224
Test name
Test status
Simulation time 512294087 ps
CPU time 11.4 seconds
Started Aug 11 06:13:21 PM PDT 24
Finished Aug 11 06:13:33 PM PDT 24
Peak memory 212856 kb
Host smart-15be73c2-8de6-47e0-83e3-da0f7e3f4aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699249504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2699249504
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.97094578
Short name T145
Test name
Test status
Simulation time 273599084 ps
CPU time 6.25 seconds
Started Aug 11 06:13:33 PM PDT 24
Finished Aug 11 06:13:39 PM PDT 24
Peak memory 212188 kb
Host smart-10c29c13-6b29-4679-9486-90c73f78bb54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97094578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.97094578
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3848597784
Short name T23
Test name
Test status
Simulation time 1891921594 ps
CPU time 113.91 seconds
Started Aug 11 06:13:33 PM PDT 24
Finished Aug 11 06:15:27 PM PDT 24
Peak memory 239512 kb
Host smart-33924d1e-b728-4d36-ae4b-98e8dbcd3cc9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848597784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3848597784
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.413824053
Short name T215
Test name
Test status
Simulation time 138173486 ps
CPU time 6.28 seconds
Started Aug 11 06:13:20 PM PDT 24
Finished Aug 11 06:13:26 PM PDT 24
Peak memory 212176 kb
Host smart-79dd42f9-a1b9-411a-b480-6a2c5a169a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413824053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.413824053
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2280304331
Short name T220
Test name
Test status
Simulation time 1181041977 ps
CPU time 14.32 seconds
Started Aug 11 06:13:31 PM PDT 24
Finished Aug 11 06:13:45 PM PDT 24
Peak memory 212352 kb
Host smart-37054471-a215-4785-8138-eaf61860e6c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280304331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2280304331
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2902955491
Short name T272
Test name
Test status
Simulation time 429544499 ps
CPU time 5.08 seconds
Started Aug 11 06:13:39 PM PDT 24
Finished Aug 11 06:13:44 PM PDT 24
Peak memory 212056 kb
Host smart-be9c8d96-b780-4f00-8077-0110d5f5149b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902955491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2902955491
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4154488496
Short name T263
Test name
Test status
Simulation time 25151507675 ps
CPU time 131.5 seconds
Started Aug 11 06:13:35 PM PDT 24
Finished Aug 11 06:15:47 PM PDT 24
Peak memory 213188 kb
Host smart-ba815b61-d2e4-47c9-9e9f-1a4290ca746d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154488496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4154488496
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2952424269
Short name T245
Test name
Test status
Simulation time 251770259 ps
CPU time 11.47 seconds
Started Aug 11 06:13:22 PM PDT 24
Finished Aug 11 06:13:34 PM PDT 24
Peak memory 211936 kb
Host smart-2540fd97-5161-4898-82be-e0775fbb81a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952424269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2952424269
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3228822807
Short name T100
Test name
Test status
Simulation time 135127295 ps
CPU time 6.33 seconds
Started Aug 11 06:13:29 PM PDT 24
Finished Aug 11 06:13:36 PM PDT 24
Peak memory 212136 kb
Host smart-d3d52c4b-64de-4ea5-abeb-e4b1b62e8e71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3228822807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3228822807
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3555412670
Short name T186
Test name
Test status
Simulation time 210585397 ps
CPU time 12.71 seconds
Started Aug 11 06:13:33 PM PDT 24
Finished Aug 11 06:13:46 PM PDT 24
Peak memory 214292 kb
Host smart-68d6d9f5-6c11-4c22-8bc8-1d4f6cd5ffff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555412670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3555412670
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3359740804
Short name T280
Test name
Test status
Simulation time 521439558 ps
CPU time 5.02 seconds
Started Aug 11 06:13:36 PM PDT 24
Finished Aug 11 06:13:41 PM PDT 24
Peak memory 211900 kb
Host smart-ac9995c5-bfc4-43d2-a5d5-35fbdc6d55ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359740804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3359740804
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2049863944
Short name T251
Test name
Test status
Simulation time 6906415792 ps
CPU time 211.23 seconds
Started Aug 11 06:13:34 PM PDT 24
Finished Aug 11 06:17:05 PM PDT 24
Peak memory 234852 kb
Host smart-d36f7340-87cf-4f3d-842d-3c7ed1f52c19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049863944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2049863944
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.149632592
Short name T327
Test name
Test status
Simulation time 202316744 ps
CPU time 5.82 seconds
Started Aug 11 06:13:35 PM PDT 24
Finished Aug 11 06:13:41 PM PDT 24
Peak memory 211804 kb
Host smart-44afaba2-c5b7-4e70-9fa2-359bee1d7295
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=149632592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.149632592
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2990846626
Short name T301
Test name
Test status
Simulation time 251318638 ps
CPU time 9.11 seconds
Started Aug 11 06:13:36 PM PDT 24
Finished Aug 11 06:13:45 PM PDT 24
Peak memory 212132 kb
Host smart-0a12c5ce-45f8-46a1-8e30-9833e0bb9f1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990846626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2990846626
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.281473868
Short name T178
Test name
Test status
Simulation time 1774337592 ps
CPU time 83.84 seconds
Started Aug 11 06:13:34 PM PDT 24
Finished Aug 11 06:14:59 PM PDT 24
Peak memory 236320 kb
Host smart-3ead3f60-eb97-41ff-adcd-1d1defcbd6c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281473868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.281473868
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3896770158
Short name T46
Test name
Test status
Simulation time 341359095 ps
CPU time 9.51 seconds
Started Aug 11 06:13:27 PM PDT 24
Finished Aug 11 06:13:36 PM PDT 24
Peak memory 213044 kb
Host smart-1e582cce-8c7d-452f-9d86-3d5ec7642014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896770158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3896770158
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3660077061
Short name T115
Test name
Test status
Simulation time 505587717 ps
CPU time 8.79 seconds
Started Aug 11 06:13:29 PM PDT 24
Finished Aug 11 06:13:38 PM PDT 24
Peak memory 212136 kb
Host smart-415f6724-4d92-4a08-83dc-4be4b447a3aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3660077061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3660077061
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.4118278554
Short name T234
Test name
Test status
Simulation time 458869029 ps
CPU time 8.92 seconds
Started Aug 11 06:13:32 PM PDT 24
Finished Aug 11 06:13:41 PM PDT 24
Peak memory 212208 kb
Host smart-bf16711e-edd0-474b-b6e6-e176c629283f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118278554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.4118278554
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3005342942
Short name T64
Test name
Test status
Simulation time 332728115 ps
CPU time 4.25 seconds
Started Aug 11 06:13:36 PM PDT 24
Finished Aug 11 06:13:40 PM PDT 24
Peak memory 212064 kb
Host smart-d8d8b967-f24f-47e2-9553-6d84329ce070
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005342942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3005342942
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1948533018
Short name T310
Test name
Test status
Simulation time 6833071262 ps
CPU time 83.34 seconds
Started Aug 11 06:13:37 PM PDT 24
Finished Aug 11 06:15:00 PM PDT 24
Peak memory 213504 kb
Host smart-8a74b6d4-4bd0-4e34-94b5-368bf7cf42fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948533018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1948533018
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3901438989
Short name T233
Test name
Test status
Simulation time 198129805 ps
CPU time 9.57 seconds
Started Aug 11 06:13:33 PM PDT 24
Finished Aug 11 06:13:43 PM PDT 24
Peak memory 212868 kb
Host smart-b6ef0075-2a5d-4736-91b7-7106ffea0420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901438989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3901438989
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.997737098
Short name T158
Test name
Test status
Simulation time 246945771 ps
CPU time 6.29 seconds
Started Aug 11 06:13:34 PM PDT 24
Finished Aug 11 06:13:41 PM PDT 24
Peak memory 212136 kb
Host smart-a13b1be2-9d09-403d-93b7-93db48e42e6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=997737098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.997737098
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3899638462
Short name T2
Test name
Test status
Simulation time 304295181 ps
CPU time 14.8 seconds
Started Aug 11 06:13:37 PM PDT 24
Finished Aug 11 06:13:52 PM PDT 24
Peak memory 213772 kb
Host smart-1e3f06e1-a1fe-4a9a-b602-9609334d8793
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899638462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3899638462
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.4232082450
Short name T216
Test name
Test status
Simulation time 337527841 ps
CPU time 4.3 seconds
Started Aug 11 06:13:31 PM PDT 24
Finished Aug 11 06:13:35 PM PDT 24
Peak memory 212048 kb
Host smart-a91df752-4760-49e9-b73d-4e09d63997a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232082450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.4232082450
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2770206199
Short name T155
Test name
Test status
Simulation time 3418049567 ps
CPU time 109.22 seconds
Started Aug 11 06:13:36 PM PDT 24
Finished Aug 11 06:15:26 PM PDT 24
Peak memory 238544 kb
Host smart-ca5f5234-bba6-4503-a7af-8a64145e542b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770206199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2770206199
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3844226790
Short name T260
Test name
Test status
Simulation time 334067751 ps
CPU time 9.43 seconds
Started Aug 11 06:13:35 PM PDT 24
Finished Aug 11 06:13:44 PM PDT 24
Peak memory 212960 kb
Host smart-3ff67e75-7ffa-4272-9578-e96aedd179a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844226790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3844226790
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.255934322
Short name T212
Test name
Test status
Simulation time 376091703 ps
CPU time 5.23 seconds
Started Aug 11 06:13:38 PM PDT 24
Finished Aug 11 06:13:43 PM PDT 24
Peak memory 212004 kb
Host smart-b7aa78d9-fcb5-4cbf-a389-1015c928e4d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=255934322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.255934322
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2827005556
Short name T318
Test name
Test status
Simulation time 515224752 ps
CPU time 11.78 seconds
Started Aug 11 06:13:38 PM PDT 24
Finished Aug 11 06:13:49 PM PDT 24
Peak memory 214036 kb
Host smart-3531199d-d576-4a41-900a-fd791a3beb24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827005556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2827005556
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1421604541
Short name T267
Test name
Test status
Simulation time 87952028 ps
CPU time 4.2 seconds
Started Aug 11 06:13:40 PM PDT 24
Finished Aug 11 06:13:44 PM PDT 24
Peak memory 212028 kb
Host smart-aee98c85-9ecc-4579-a44f-389c604d24be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421604541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1421604541
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1821657498
Short name T287
Test name
Test status
Simulation time 5101518180 ps
CPU time 111.55 seconds
Started Aug 11 06:13:36 PM PDT 24
Finished Aug 11 06:15:28 PM PDT 24
Peak memory 238032 kb
Host smart-9be8c098-8087-42f1-a83e-64359dae3558
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821657498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1821657498
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2973989979
Short name T133
Test name
Test status
Simulation time 378431721 ps
CPU time 5.45 seconds
Started Aug 11 06:13:37 PM PDT 24
Finished Aug 11 06:13:42 PM PDT 24
Peak memory 212184 kb
Host smart-2f841ea1-ec6f-436d-9ad2-35de4f66ac3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2973989979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2973989979
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2045507319
Short name T18
Test name
Test status
Simulation time 519495843 ps
CPU time 6.34 seconds
Started Aug 11 06:13:39 PM PDT 24
Finished Aug 11 06:13:45 PM PDT 24
Peak memory 212132 kb
Host smart-2f1edf03-6b73-4dd8-b0ba-c2e2033b6f83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045507319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2045507319
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.112945497
Short name T284
Test name
Test status
Simulation time 273033012641 ps
CPU time 4589.45 seconds
Started Aug 11 06:13:33 PM PDT 24
Finished Aug 11 07:30:03 PM PDT 24
Peak memory 261188 kb
Host smart-bcc263f3-a8d6-4c3e-af5b-c0c971e1af3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112945497 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.112945497
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3840755390
Short name T157
Test name
Test status
Simulation time 362261753 ps
CPU time 4.22 seconds
Started Aug 11 06:13:40 PM PDT 24
Finished Aug 11 06:13:44 PM PDT 24
Peak memory 212084 kb
Host smart-2a5af723-b214-4b43-8f84-f3daba7c36ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840755390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3840755390
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3218494690
Short name T309
Test name
Test status
Simulation time 6193847776 ps
CPU time 151.85 seconds
Started Aug 11 06:13:36 PM PDT 24
Finished Aug 11 06:16:08 PM PDT 24
Peak memory 213244 kb
Host smart-dca160ad-8174-4a35-a12c-1f1f69f01e04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218494690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3218494690
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.970659472
Short name T34
Test name
Test status
Simulation time 174377479 ps
CPU time 9.46 seconds
Started Aug 11 06:13:33 PM PDT 24
Finished Aug 11 06:13:42 PM PDT 24
Peak memory 213408 kb
Host smart-a4eb963d-590e-47f3-9208-92b28c0c1ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970659472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.970659472
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.89727681
Short name T274
Test name
Test status
Simulation time 454003525 ps
CPU time 5.82 seconds
Started Aug 11 06:13:42 PM PDT 24
Finished Aug 11 06:13:48 PM PDT 24
Peak memory 212148 kb
Host smart-e862063f-dbd3-49ec-a1c5-17a43379e418
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89727681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.89727681
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.491499838
Short name T326
Test name
Test status
Simulation time 727376808 ps
CPU time 11.64 seconds
Started Aug 11 06:13:38 PM PDT 24
Finished Aug 11 06:13:50 PM PDT 24
Peak memory 213456 kb
Host smart-8d4b8b7f-4bc1-4724-969f-f107a9638ccf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491499838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.491499838
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.249287780
Short name T231
Test name
Test status
Simulation time 88581664266 ps
CPU time 511.19 seconds
Started Aug 11 06:13:37 PM PDT 24
Finished Aug 11 06:22:08 PM PDT 24
Peak memory 236648 kb
Host smart-4b7964de-46db-4d9e-9aa6-d74d0a75ab22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249287780 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.249287780
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1308665631
Short name T298
Test name
Test status
Simulation time 85762356 ps
CPU time 4.2 seconds
Started Aug 11 06:13:36 PM PDT 24
Finished Aug 11 06:13:41 PM PDT 24
Peak memory 212096 kb
Host smart-a132f082-a5fb-4698-a681-02fcc4d9ca46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308665631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1308665631
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3026135829
Short name T316
Test name
Test status
Simulation time 8955138002 ps
CPU time 143.7 seconds
Started Aug 11 06:13:36 PM PDT 24
Finished Aug 11 06:16:00 PM PDT 24
Peak memory 213516 kb
Host smart-1cdd665a-bb68-4626-acdc-ee66ed97147a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026135829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3026135829
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1588794246
Short name T250
Test name
Test status
Simulation time 472530909 ps
CPU time 11.04 seconds
Started Aug 11 06:13:32 PM PDT 24
Finished Aug 11 06:13:44 PM PDT 24
Peak memory 212940 kb
Host smart-74dbdac3-1643-4dbe-acf5-ae63be55bbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588794246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1588794246
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.389489222
Short name T204
Test name
Test status
Simulation time 189764278 ps
CPU time 5.33 seconds
Started Aug 11 06:13:37 PM PDT 24
Finished Aug 11 06:13:42 PM PDT 24
Peak memory 212184 kb
Host smart-02c16d5b-f1b6-479b-911f-fff9c220545a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=389489222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.389489222
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.367358292
Short name T101
Test name
Test status
Simulation time 488632408 ps
CPU time 7.37 seconds
Started Aug 11 06:13:35 PM PDT 24
Finished Aug 11 06:13:43 PM PDT 24
Peak memory 212076 kb
Host smart-a3247386-0ca4-4af4-ad6d-0b2c74ef8733
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367358292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.367358292
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.519004021
Short name T206
Test name
Test status
Simulation time 64181890317 ps
CPU time 2448.82 seconds
Started Aug 11 06:13:37 PM PDT 24
Finished Aug 11 06:54:26 PM PDT 24
Peak memory 240452 kb
Host smart-01f26715-e96f-4104-afbc-8b59f1b5ddcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519004021 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.519004021
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1301219725
Short name T137
Test name
Test status
Simulation time 348123307 ps
CPU time 4.17 seconds
Started Aug 11 06:13:39 PM PDT 24
Finished Aug 11 06:13:43 PM PDT 24
Peak memory 212080 kb
Host smart-5bd86dad-4301-4d15-8891-5bd0e374542d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301219725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1301219725
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.4110290349
Short name T170
Test name
Test status
Simulation time 11152050748 ps
CPU time 108.31 seconds
Started Aug 11 06:13:33 PM PDT 24
Finished Aug 11 06:15:21 PM PDT 24
Peak memory 215340 kb
Host smart-ef15dd4b-8392-4ca5-a1c4-d0ed6265d8ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110290349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.4110290349
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2680675534
Short name T325
Test name
Test status
Simulation time 175181023 ps
CPU time 9.87 seconds
Started Aug 11 06:13:29 PM PDT 24
Finished Aug 11 06:13:39 PM PDT 24
Peak memory 213064 kb
Host smart-5854d0bd-c68f-4498-a4de-d084cd52c52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680675534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2680675534
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3164334829
Short name T172
Test name
Test status
Simulation time 190791779 ps
CPU time 5.55 seconds
Started Aug 11 06:13:38 PM PDT 24
Finished Aug 11 06:13:44 PM PDT 24
Peak memory 212080 kb
Host smart-4bc49a98-192c-4d8f-96a4-661f31774b71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3164334829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3164334829
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2547610973
Short name T65
Test name
Test status
Simulation time 88845207 ps
CPU time 4.25 seconds
Started Aug 11 06:13:39 PM PDT 24
Finished Aug 11 06:13:44 PM PDT 24
Peak memory 212092 kb
Host smart-96a22018-ef8d-4d53-9c75-cf6a94d2ca1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547610973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2547610973
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4037751143
Short name T36
Test name
Test status
Simulation time 2983845763 ps
CPU time 95.1 seconds
Started Aug 11 06:13:37 PM PDT 24
Finished Aug 11 06:15:12 PM PDT 24
Peak memory 229308 kb
Host smart-446413f1-d013-445f-b089-943311aaab74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037751143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.4037751143
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3964149586
Short name T184
Test name
Test status
Simulation time 1042527340 ps
CPU time 9.7 seconds
Started Aug 11 06:13:45 PM PDT 24
Finished Aug 11 06:13:55 PM PDT 24
Peak memory 212816 kb
Host smart-7eabe63d-fada-4366-ba6c-dd59cb50a734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964149586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3964149586
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4081003107
Short name T140
Test name
Test status
Simulation time 367861710 ps
CPU time 5.58 seconds
Started Aug 11 06:13:39 PM PDT 24
Finished Aug 11 06:13:45 PM PDT 24
Peak memory 212184 kb
Host smart-f320d22d-4890-4011-92e1-96b218554864
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4081003107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4081003107
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2724360075
Short name T270
Test name
Test status
Simulation time 154866157 ps
CPU time 7.01 seconds
Started Aug 11 06:13:34 PM PDT 24
Finished Aug 11 06:13:42 PM PDT 24
Peak memory 212296 kb
Host smart-3a845df4-ee1d-4c76-96a3-3a127131983d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724360075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2724360075
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2108318479
Short name T121
Test name
Test status
Simulation time 255932255 ps
CPU time 5.08 seconds
Started Aug 11 06:13:35 PM PDT 24
Finished Aug 11 06:13:40 PM PDT 24
Peak memory 211112 kb
Host smart-9b964f95-d98c-41c0-b415-9ced715c6f83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108318479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2108318479
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3128681583
Short name T222
Test name
Test status
Simulation time 5979155281 ps
CPU time 89.15 seconds
Started Aug 11 06:13:24 PM PDT 24
Finished Aug 11 06:14:54 PM PDT 24
Peak memory 239860 kb
Host smart-d20bd78a-837a-4f18-86f4-b2f5c16154e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128681583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3128681583
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2712122567
Short name T201
Test name
Test status
Simulation time 250955870 ps
CPU time 10.86 seconds
Started Aug 11 06:13:29 PM PDT 24
Finished Aug 11 06:13:40 PM PDT 24
Peak memory 212904 kb
Host smart-443f9947-b3b2-49a8-8e84-5fc27e75b60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712122567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2712122567
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.451266209
Short name T194
Test name
Test status
Simulation time 139641244 ps
CPU time 6.48 seconds
Started Aug 11 06:13:31 PM PDT 24
Finished Aug 11 06:13:38 PM PDT 24
Peak memory 212164 kb
Host smart-690961dc-d92f-4a0c-9566-f00819e28d6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=451266209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.451266209
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2279130450
Short name T26
Test name
Test status
Simulation time 858351168 ps
CPU time 98.13 seconds
Started Aug 11 06:13:29 PM PDT 24
Finished Aug 11 06:15:07 PM PDT 24
Peak memory 237376 kb
Host smart-62cd9c9b-e85e-4b6e-825e-b0e0c916d342
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279130450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2279130450
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2065466961
Short name T166
Test name
Test status
Simulation time 142934127 ps
CPU time 6.38 seconds
Started Aug 11 06:13:33 PM PDT 24
Finished Aug 11 06:13:40 PM PDT 24
Peak memory 212180 kb
Host smart-4099250a-41c8-45f4-b9fd-d3ca90349d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065466961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2065466961
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2344980465
Short name T154
Test name
Test status
Simulation time 215700150 ps
CPU time 12.16 seconds
Started Aug 11 06:13:37 PM PDT 24
Finished Aug 11 06:13:49 PM PDT 24
Peak memory 214824 kb
Host smart-3cf0cb8a-0797-4d4d-9d58-bcd7cab7f384
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344980465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2344980465
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1407592347
Short name T286
Test name
Test status
Simulation time 13627126609 ps
CPU time 545.89 seconds
Started Aug 11 06:13:34 PM PDT 24
Finished Aug 11 06:22:40 PM PDT 24
Peak memory 229052 kb
Host smart-c6f51975-7380-457f-8bf6-147f993bc7c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407592347 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1407592347
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1443382466
Short name T139
Test name
Test status
Simulation time 260673267 ps
CPU time 5.22 seconds
Started Aug 11 06:13:38 PM PDT 24
Finished Aug 11 06:13:43 PM PDT 24
Peak memory 212092 kb
Host smart-9c826391-1f1a-40c5-b75a-a8e934802629
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443382466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1443382466
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2512411236
Short name T168
Test name
Test status
Simulation time 4807336987 ps
CPU time 74.4 seconds
Started Aug 11 06:13:39 PM PDT 24
Finished Aug 11 06:14:54 PM PDT 24
Peak memory 235584 kb
Host smart-cc01fb09-7bcc-4cfa-a054-19293098f098
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512411236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2512411236
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1099077892
Short name T179
Test name
Test status
Simulation time 702821088 ps
CPU time 9.58 seconds
Started Aug 11 06:13:36 PM PDT 24
Finished Aug 11 06:13:46 PM PDT 24
Peak memory 214648 kb
Host smart-df3d4e4f-0ec4-4c16-9ff4-1acfde5fd818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099077892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1099077892
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.302972222
Short name T67
Test name
Test status
Simulation time 273870197 ps
CPU time 6.32 seconds
Started Aug 11 06:13:39 PM PDT 24
Finished Aug 11 06:13:46 PM PDT 24
Peak memory 212196 kb
Host smart-499077d8-1ce3-4140-ae61-a6692c75ca34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=302972222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.302972222
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.717640736
Short name T149
Test name
Test status
Simulation time 303558606 ps
CPU time 13.59 seconds
Started Aug 11 06:13:39 PM PDT 24
Finished Aug 11 06:13:52 PM PDT 24
Peak memory 214400 kb
Host smart-d89da42c-5c5e-496e-adb0-eb7baf0c8604
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717640736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.717640736
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1848541390
Short name T50
Test name
Test status
Simulation time 83639289479 ps
CPU time 10151.1 seconds
Started Aug 11 06:13:37 PM PDT 24
Finished Aug 11 09:02:49 PM PDT 24
Peak memory 236680 kb
Host smart-66d9fb1b-af0e-4ac0-8a1c-c8ba6058bcd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848541390 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1848541390
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.4108091783
Short name T171
Test name
Test status
Simulation time 496831577 ps
CPU time 5.05 seconds
Started Aug 11 06:13:40 PM PDT 24
Finished Aug 11 06:13:45 PM PDT 24
Peak memory 212072 kb
Host smart-fbb2f156-799e-48ea-aefe-778e4689dc58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108091783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.4108091783
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3664356680
Short name T14
Test name
Test status
Simulation time 2536969811 ps
CPU time 78.85 seconds
Started Aug 11 06:13:38 PM PDT 24
Finished Aug 11 06:14:57 PM PDT 24
Peak memory 238508 kb
Host smart-59affd53-9888-4cf5-a127-5424a43ad965
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664356680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3664356680
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.736777789
Short name T169
Test name
Test status
Simulation time 1673502345 ps
CPU time 9.67 seconds
Started Aug 11 06:13:41 PM PDT 24
Finished Aug 11 06:13:51 PM PDT 24
Peak memory 212852 kb
Host smart-f99bb582-b4d2-4f37-888a-fc3306f8d593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736777789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.736777789
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1134089348
Short name T199
Test name
Test status
Simulation time 535241373 ps
CPU time 6.62 seconds
Started Aug 11 06:13:35 PM PDT 24
Finished Aug 11 06:13:42 PM PDT 24
Peak memory 212068 kb
Host smart-0bf164a9-4063-4d6c-945c-6dbab5fadb07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1134089348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1134089348
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1709934644
Short name T175
Test name
Test status
Simulation time 1772796391 ps
CPU time 20.02 seconds
Started Aug 11 06:13:43 PM PDT 24
Finished Aug 11 06:14:03 PM PDT 24
Peak memory 215072 kb
Host smart-efc2f7c0-7b63-4e36-89a6-bc0a390182fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709934644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1709934644
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1335998636
Short name T217
Test name
Test status
Simulation time 333460185 ps
CPU time 4.18 seconds
Started Aug 11 06:13:39 PM PDT 24
Finished Aug 11 06:13:43 PM PDT 24
Peak memory 212084 kb
Host smart-b92f00b4-c724-4e22-95d3-0e5187ae7567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335998636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1335998636
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2906527798
Short name T167
Test name
Test status
Simulation time 6460617117 ps
CPU time 117.52 seconds
Started Aug 11 06:13:37 PM PDT 24
Finished Aug 11 06:15:35 PM PDT 24
Peak memory 229296 kb
Host smart-6c1820c4-eef7-467b-9f37-e8a165a28f19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906527798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2906527798
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.494530041
Short name T269
Test name
Test status
Simulation time 671234873 ps
CPU time 9.4 seconds
Started Aug 11 06:13:43 PM PDT 24
Finished Aug 11 06:13:52 PM PDT 24
Peak memory 213008 kb
Host smart-f675d354-fe8d-4002-83fd-521382f6e74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494530041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.494530041
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.877637622
Short name T214
Test name
Test status
Simulation time 189649384 ps
CPU time 5.93 seconds
Started Aug 11 06:13:35 PM PDT 24
Finished Aug 11 06:13:41 PM PDT 24
Peak memory 212152 kb
Host smart-2db49dd5-1db6-4a9b-9414-582c413736ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=877637622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.877637622
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3248546571
Short name T262
Test name
Test status
Simulation time 773706005 ps
CPU time 14.9 seconds
Started Aug 11 06:13:41 PM PDT 24
Finished Aug 11 06:13:56 PM PDT 24
Peak memory 213280 kb
Host smart-f1bc7791-6882-4ba4-a12c-c20c4f938765
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248546571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3248546571
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1248565468
Short name T240
Test name
Test status
Simulation time 81074349761 ps
CPU time 553.09 seconds
Started Aug 11 06:13:42 PM PDT 24
Finished Aug 11 06:22:55 PM PDT 24
Peak memory 236636 kb
Host smart-4bde68fa-ba69-4ffc-986d-a2e83e72e42e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248565468 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.1248565468
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.669996688
Short name T125
Test name
Test status
Simulation time 238950952 ps
CPU time 4.27 seconds
Started Aug 11 06:13:41 PM PDT 24
Finished Aug 11 06:13:46 PM PDT 24
Peak memory 211992 kb
Host smart-401d58cf-997d-436e-9ee7-74f4016af0a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669996688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.669996688
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.286044778
Short name T276
Test name
Test status
Simulation time 9562310591 ps
CPU time 91.69 seconds
Started Aug 11 06:13:35 PM PDT 24
Finished Aug 11 06:15:07 PM PDT 24
Peak memory 238480 kb
Host smart-9f05a184-e850-4841-af8c-1ca5914336c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286044778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.286044778
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3872643230
Short name T195
Test name
Test status
Simulation time 261852343 ps
CPU time 11.47 seconds
Started Aug 11 06:13:48 PM PDT 24
Finished Aug 11 06:14:00 PM PDT 24
Peak memory 212776 kb
Host smart-4d3010ea-5713-4c62-b74b-53f9bba9668f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872643230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3872643230
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3109221917
Short name T99
Test name
Test status
Simulation time 383494078 ps
CPU time 6.05 seconds
Started Aug 11 06:13:42 PM PDT 24
Finished Aug 11 06:13:49 PM PDT 24
Peak memory 212168 kb
Host smart-400378a0-ee4e-4770-9d4e-f537417d4995
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3109221917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3109221917
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2874941065
Short name T33
Test name
Test status
Simulation time 302738104 ps
CPU time 15.85 seconds
Started Aug 11 06:13:33 PM PDT 24
Finished Aug 11 06:13:49 PM PDT 24
Peak memory 215128 kb
Host smart-3b3d77af-8a6c-4ce9-beb8-4aa2bcddc2de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874941065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2874941065
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1082435272
Short name T103
Test name
Test status
Simulation time 27730715029 ps
CPU time 513.37 seconds
Started Aug 11 06:13:43 PM PDT 24
Finished Aug 11 06:22:17 PM PDT 24
Peak memory 236672 kb
Host smart-049538ef-4503-4ce7-ae64-05ab4cd24997
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082435272 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1082435272
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1894562613
Short name T29
Test name
Test status
Simulation time 130970882 ps
CPU time 5.08 seconds
Started Aug 11 06:13:36 PM PDT 24
Finished Aug 11 06:13:41 PM PDT 24
Peak memory 212060 kb
Host smart-1f1febc7-a135-4374-b1cf-63095452ce11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894562613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1894562613
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.951633468
Short name T20
Test name
Test status
Simulation time 2574852596 ps
CPU time 88.67 seconds
Started Aug 11 06:13:43 PM PDT 24
Finished Aug 11 06:15:12 PM PDT 24
Peak memory 229176 kb
Host smart-45b58a51-3783-4ecf-b1b2-1fa602929fba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951633468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.951633468
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1511214593
Short name T146
Test name
Test status
Simulation time 170422383 ps
CPU time 9.72 seconds
Started Aug 11 06:13:40 PM PDT 24
Finished Aug 11 06:13:50 PM PDT 24
Peak memory 212756 kb
Host smart-9882e687-eaef-42f4-b111-411ba273784c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511214593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1511214593
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1525407822
Short name T98
Test name
Test status
Simulation time 94800745 ps
CPU time 5.43 seconds
Started Aug 11 06:13:37 PM PDT 24
Finished Aug 11 06:13:42 PM PDT 24
Peak memory 212100 kb
Host smart-aa92db09-0a26-429f-bcad-351745a159ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1525407822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1525407822
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.884921959
Short name T226
Test name
Test status
Simulation time 1802306339 ps
CPU time 18.6 seconds
Started Aug 11 06:13:32 PM PDT 24
Finished Aug 11 06:13:51 PM PDT 24
Peak memory 215912 kb
Host smart-d026ccab-17dc-436b-8838-f9dc7030fdbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884921959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.884921959
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2849547964
Short name T221
Test name
Test status
Simulation time 299565540 ps
CPU time 5.03 seconds
Started Aug 11 06:13:51 PM PDT 24
Finished Aug 11 06:13:56 PM PDT 24
Peak memory 212056 kb
Host smart-90184cea-1bba-4e29-8788-21c2d698e736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849547964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2849547964
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1675626113
Short name T41
Test name
Test status
Simulation time 4299745087 ps
CPU time 84.02 seconds
Started Aug 11 06:13:36 PM PDT 24
Finished Aug 11 06:15:01 PM PDT 24
Peak memory 236072 kb
Host smart-bbaf797e-3e2f-4bac-8a3e-dff5cfa283f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675626113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1675626113
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1818177010
Short name T285
Test name
Test status
Simulation time 498900496 ps
CPU time 11.09 seconds
Started Aug 11 06:13:44 PM PDT 24
Finished Aug 11 06:13:55 PM PDT 24
Peak memory 212972 kb
Host smart-bc3644da-beab-4e36-ad62-08fdcadf0519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818177010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1818177010
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.491039136
Short name T230
Test name
Test status
Simulation time 284229325 ps
CPU time 6.6 seconds
Started Aug 11 06:13:42 PM PDT 24
Finished Aug 11 06:13:48 PM PDT 24
Peak memory 212176 kb
Host smart-cbf6cb6f-c2c4-473c-88d3-06786244729a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=491039136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.491039136
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2799513912
Short name T17
Test name
Test status
Simulation time 147193001 ps
CPU time 10.01 seconds
Started Aug 11 06:13:37 PM PDT 24
Finished Aug 11 06:13:47 PM PDT 24
Peak memory 212108 kb
Host smart-c4c36711-a25e-452b-bc2c-2b00e1cb3044
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799513912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2799513912
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.520897111
Short name T258
Test name
Test status
Simulation time 2088571574 ps
CPU time 5.18 seconds
Started Aug 11 06:13:43 PM PDT 24
Finished Aug 11 06:13:49 PM PDT 24
Peak memory 212064 kb
Host smart-87456681-4263-45ba-972c-05ba578bd752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520897111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.520897111
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4245178005
Short name T174
Test name
Test status
Simulation time 301142401 ps
CPU time 9.61 seconds
Started Aug 11 06:14:04 PM PDT 24
Finished Aug 11 06:14:14 PM PDT 24
Peak memory 212920 kb
Host smart-ab6c592a-d993-4a6f-83f9-d78c2a534f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245178005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4245178005
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.472523704
Short name T189
Test name
Test status
Simulation time 789010582 ps
CPU time 6.02 seconds
Started Aug 11 06:13:50 PM PDT 24
Finished Aug 11 06:13:56 PM PDT 24
Peak memory 212148 kb
Host smart-83eba48d-18f3-4ddc-868b-d5cb69adc95a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=472523704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.472523704
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1805087930
Short name T303
Test name
Test status
Simulation time 611918238 ps
CPU time 8.67 seconds
Started Aug 11 06:13:47 PM PDT 24
Finished Aug 11 06:13:56 PM PDT 24
Peak memory 213276 kb
Host smart-23537375-10e1-4bab-92a1-092cbd45114d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805087930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1805087930
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3525918080
Short name T150
Test name
Test status
Simulation time 86539571 ps
CPU time 4.23 seconds
Started Aug 11 06:13:42 PM PDT 24
Finished Aug 11 06:13:47 PM PDT 24
Peak memory 212104 kb
Host smart-aea3ac62-45b8-49ef-a089-cb351a9333d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525918080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3525918080
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1237094515
Short name T268
Test name
Test status
Simulation time 2391535731 ps
CPU time 9.59 seconds
Started Aug 11 06:13:52 PM PDT 24
Finished Aug 11 06:14:02 PM PDT 24
Peak memory 212968 kb
Host smart-9654c4e1-37aa-484a-8578-dbec94fdd46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237094515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1237094515
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4196499951
Short name T320
Test name
Test status
Simulation time 563033834 ps
CPU time 6.67 seconds
Started Aug 11 06:13:56 PM PDT 24
Finished Aug 11 06:14:03 PM PDT 24
Peak memory 212160 kb
Host smart-62854fb2-47da-4644-b227-485d33c28a50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4196499951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4196499951
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3606917205
Short name T259
Test name
Test status
Simulation time 3099018384 ps
CPU time 14.36 seconds
Started Aug 11 06:13:41 PM PDT 24
Finished Aug 11 06:13:56 PM PDT 24
Peak memory 215156 kb
Host smart-da256a03-c76a-44f8-a8ad-fa538d582ab7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606917205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3606917205
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2222111158
Short name T49
Test name
Test status
Simulation time 459533669 ps
CPU time 5.09 seconds
Started Aug 11 06:14:00 PM PDT 24
Finished Aug 11 06:14:05 PM PDT 24
Peak memory 212012 kb
Host smart-6d4ea8e3-4e6d-45b3-9cee-af7ed49f3093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222111158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2222111158
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3563138037
Short name T142
Test name
Test status
Simulation time 32147453772 ps
CPU time 166.52 seconds
Started Aug 11 06:13:44 PM PDT 24
Finished Aug 11 06:16:31 PM PDT 24
Peak memory 238452 kb
Host smart-0533b9da-0869-4124-aae6-1f714b0dca97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563138037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3563138037
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1578014250
Short name T207
Test name
Test status
Simulation time 251397908 ps
CPU time 11.52 seconds
Started Aug 11 06:13:39 PM PDT 24
Finished Aug 11 06:13:51 PM PDT 24
Peak memory 213176 kb
Host smart-d8643c62-92a4-4493-935d-c3e49db36868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578014250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1578014250
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1693226143
Short name T28
Test name
Test status
Simulation time 250447379 ps
CPU time 6.3 seconds
Started Aug 11 06:13:50 PM PDT 24
Finished Aug 11 06:13:56 PM PDT 24
Peak memory 212208 kb
Host smart-25a6ff35-3274-4305-84a5-9debc7606ac3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1693226143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1693226143
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3756542853
Short name T330
Test name
Test status
Simulation time 1125051277 ps
CPU time 17.53 seconds
Started Aug 11 06:13:58 PM PDT 24
Finished Aug 11 06:14:16 PM PDT 24
Peak memory 216108 kb
Host smart-13fd4303-5ebb-4195-8907-d5945b785b55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756542853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3756542853
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3447911835
Short name T244
Test name
Test status
Simulation time 66834141936 ps
CPU time 675.15 seconds
Started Aug 11 06:13:42 PM PDT 24
Finished Aug 11 06:24:57 PM PDT 24
Peak memory 236676 kb
Host smart-2f8a5c9e-9a82-43b9-9ec6-59c5d6ca588d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447911835 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3447911835
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1244361382
Short name T1
Test name
Test status
Simulation time 90850284 ps
CPU time 4.3 seconds
Started Aug 11 06:13:43 PM PDT 24
Finished Aug 11 06:13:48 PM PDT 24
Peak memory 212092 kb
Host smart-313d6cfb-d7dc-4f05-bd3d-f9b942f814aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244361382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1244361382
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3644398864
Short name T246
Test name
Test status
Simulation time 1972365374 ps
CPU time 104.88 seconds
Started Aug 11 06:13:50 PM PDT 24
Finished Aug 11 06:15:35 PM PDT 24
Peak memory 238396 kb
Host smart-b85ccd3a-6f27-49fd-a88c-97a563040fb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644398864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3644398864
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.913023172
Short name T163
Test name
Test status
Simulation time 259183719 ps
CPU time 11.02 seconds
Started Aug 11 06:13:56 PM PDT 24
Finished Aug 11 06:14:07 PM PDT 24
Peak memory 212920 kb
Host smart-ecdd82ac-a5a6-438e-aaaa-164c40a28571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913023172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.913023172
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1615169692
Short name T307
Test name
Test status
Simulation time 383559534 ps
CPU time 5.47 seconds
Started Aug 11 06:13:47 PM PDT 24
Finished Aug 11 06:13:52 PM PDT 24
Peak memory 212128 kb
Host smart-28cec5b2-d6f6-41cb-a6f1-b1b78a7a1d6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1615169692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1615169692
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2209235252
Short name T202
Test name
Test status
Simulation time 289818435 ps
CPU time 12.71 seconds
Started Aug 11 06:13:40 PM PDT 24
Finished Aug 11 06:13:53 PM PDT 24
Peak memory 215644 kb
Host smart-e295f551-9e51-48b1-b378-f76a33e7acae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209235252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2209235252
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1300111085
Short name T8
Test name
Test status
Simulation time 518091280 ps
CPU time 5.08 seconds
Started Aug 11 06:13:31 PM PDT 24
Finished Aug 11 06:13:36 PM PDT 24
Peak memory 212092 kb
Host smart-2722287d-d9f6-4b41-8b9d-31322bd8adc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300111085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1300111085
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1324736958
Short name T229
Test name
Test status
Simulation time 1187909331 ps
CPU time 75.92 seconds
Started Aug 11 06:13:30 PM PDT 24
Finished Aug 11 06:14:46 PM PDT 24
Peak memory 238428 kb
Host smart-242a3275-e322-4b28-b4e8-0b85a7182296
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324736958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1324736958
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.86308351
Short name T236
Test name
Test status
Simulation time 176476482 ps
CPU time 9.27 seconds
Started Aug 11 06:13:35 PM PDT 24
Finished Aug 11 06:13:44 PM PDT 24
Peak memory 213032 kb
Host smart-262c9c7c-e2a3-4d0a-b40f-b1806308883b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86308351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.86308351
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.315424325
Short name T328
Test name
Test status
Simulation time 142403903 ps
CPU time 6.5 seconds
Started Aug 11 06:13:29 PM PDT 24
Finished Aug 11 06:13:35 PM PDT 24
Peak memory 212176 kb
Host smart-53402e7a-9f75-4322-815a-3dd4fe02916b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=315424325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.315424325
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3418771963
Short name T329
Test name
Test status
Simulation time 280765062 ps
CPU time 6.21 seconds
Started Aug 11 06:13:31 PM PDT 24
Finished Aug 11 06:13:43 PM PDT 24
Peak memory 212140 kb
Host smart-fb776c45-c229-4b03-9e42-2a0282a5c9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418771963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3418771963
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3216375900
Short name T126
Test name
Test status
Simulation time 124008869 ps
CPU time 9.43 seconds
Started Aug 11 06:13:28 PM PDT 24
Finished Aug 11 06:13:38 PM PDT 24
Peak memory 212328 kb
Host smart-5de3fa70-3eec-4d1e-9350-aa985fe6a5c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216375900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3216375900
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.668073582
Short name T228
Test name
Test status
Simulation time 115469300949 ps
CPU time 2308.01 seconds
Started Aug 11 06:13:43 PM PDT 24
Finished Aug 11 06:52:11 PM PDT 24
Peak memory 243580 kb
Host smart-ad118f23-b0f0-4076-b69c-78d4b7c2db62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668073582 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.668073582
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.488462692
Short name T294
Test name
Test status
Simulation time 377469515 ps
CPU time 4.34 seconds
Started Aug 11 06:14:01 PM PDT 24
Finished Aug 11 06:14:05 PM PDT 24
Peak memory 212028 kb
Host smart-bafa77ef-95e4-44b1-8704-1875dd3bac2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488462692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.488462692
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3999494766
Short name T200
Test name
Test status
Simulation time 6172845274 ps
CPU time 100.1 seconds
Started Aug 11 06:13:58 PM PDT 24
Finished Aug 11 06:15:39 PM PDT 24
Peak memory 238144 kb
Host smart-844066d7-ba4f-4edb-9abb-1d2c08ba628d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999494766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3999494766
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2421845075
Short name T185
Test name
Test status
Simulation time 358565799 ps
CPU time 9.69 seconds
Started Aug 11 06:13:55 PM PDT 24
Finished Aug 11 06:14:05 PM PDT 24
Peak memory 213124 kb
Host smart-cf41fc88-71bc-4719-bc3b-bed430cbbba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421845075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2421845075
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2861162700
Short name T211
Test name
Test status
Simulation time 565402739 ps
CPU time 6.59 seconds
Started Aug 11 06:13:51 PM PDT 24
Finished Aug 11 06:13:58 PM PDT 24
Peak memory 212156 kb
Host smart-d85cbd2f-d364-4314-9e88-68d508c13915
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2861162700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2861162700
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3285016115
Short name T302
Test name
Test status
Simulation time 176258262 ps
CPU time 9.95 seconds
Started Aug 11 06:13:45 PM PDT 24
Finished Aug 11 06:13:56 PM PDT 24
Peak memory 213940 kb
Host smart-70982565-048a-4da5-ba4a-fff23b91136c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285016115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3285016115
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1547586656
Short name T32
Test name
Test status
Simulation time 86739634707 ps
CPU time 9512.07 seconds
Started Aug 11 06:13:45 PM PDT 24
Finished Aug 11 08:52:18 PM PDT 24
Peak memory 236696 kb
Host smart-d6b6286f-d002-4540-a860-bd01a54b2f53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547586656 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1547586656
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3190066246
Short name T42
Test name
Test status
Simulation time 333792837 ps
CPU time 4.25 seconds
Started Aug 11 06:13:51 PM PDT 24
Finished Aug 11 06:13:55 PM PDT 24
Peak memory 212084 kb
Host smart-bbea541c-fdfe-424b-8449-06e0d8864189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190066246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3190066246
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.567651817
Short name T196
Test name
Test status
Simulation time 9055748728 ps
CPU time 57.7 seconds
Started Aug 11 06:13:53 PM PDT 24
Finished Aug 11 06:14:51 PM PDT 24
Peak memory 234880 kb
Host smart-86520cda-9fe5-4bed-9e00-dfd7121ff0d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567651817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.567651817
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.901221468
Short name T119
Test name
Test status
Simulation time 170096487 ps
CPU time 9.54 seconds
Started Aug 11 06:13:50 PM PDT 24
Finished Aug 11 06:14:00 PM PDT 24
Peak memory 212992 kb
Host smart-940ad3a5-20dc-49bd-871a-c6303becf300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901221468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.901221468
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.624256621
Short name T295
Test name
Test status
Simulation time 383781993 ps
CPU time 5.79 seconds
Started Aug 11 06:13:55 PM PDT 24
Finished Aug 11 06:14:00 PM PDT 24
Peak memory 212188 kb
Host smart-7b72e1c8-d24f-469d-b3a0-ce59a24ac45e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=624256621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.624256621
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.840317648
Short name T44
Test name
Test status
Simulation time 831790551 ps
CPU time 12.32 seconds
Started Aug 11 06:13:57 PM PDT 24
Finished Aug 11 06:14:09 PM PDT 24
Peak memory 214724 kb
Host smart-6f5086b1-0a63-495c-99ef-0045f425a71a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840317648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.840317648
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2519631162
Short name T306
Test name
Test status
Simulation time 98069385702 ps
CPU time 1046 seconds
Started Aug 11 06:13:48 PM PDT 24
Finished Aug 11 06:31:14 PM PDT 24
Peak memory 236700 kb
Host smart-73f43a81-eb9e-47cd-929f-b80b32f58c08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519631162 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2519631162
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.939464652
Short name T243
Test name
Test status
Simulation time 499636296 ps
CPU time 5.1 seconds
Started Aug 11 06:13:49 PM PDT 24
Finished Aug 11 06:13:54 PM PDT 24
Peak memory 212028 kb
Host smart-90d761be-ae6e-4060-a84d-6f70bcded64e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939464652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.939464652
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1260067888
Short name T181
Test name
Test status
Simulation time 2309287020 ps
CPU time 119.91 seconds
Started Aug 11 06:13:43 PM PDT 24
Finished Aug 11 06:15:43 PM PDT 24
Peak memory 238324 kb
Host smart-f0782f0b-4dc4-4610-b81f-13235fbbcb1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260067888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1260067888
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3708844440
Short name T30
Test name
Test status
Simulation time 183248763 ps
CPU time 9.52 seconds
Started Aug 11 06:13:54 PM PDT 24
Finished Aug 11 06:14:04 PM PDT 24
Peak memory 212920 kb
Host smart-0c238888-d209-4323-aa6a-a09f86ae9a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708844440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3708844440
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2963172591
Short name T191
Test name
Test status
Simulation time 134191764 ps
CPU time 6.21 seconds
Started Aug 11 06:13:48 PM PDT 24
Finished Aug 11 06:13:54 PM PDT 24
Peak memory 212208 kb
Host smart-aae0ec30-912f-4488-9014-f7d1c5b89c2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2963172591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2963172591
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.516954359
Short name T271
Test name
Test status
Simulation time 434264776 ps
CPU time 23.27 seconds
Started Aug 11 06:13:46 PM PDT 24
Finished Aug 11 06:14:09 PM PDT 24
Peak memory 214892 kb
Host smart-6a776365-f76a-4c05-b028-e25fd50c9125
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516954359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.516954359
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2878146947
Short name T57
Test name
Test status
Simulation time 16085063098 ps
CPU time 5551.14 seconds
Started Aug 11 06:13:51 PM PDT 24
Finished Aug 11 07:46:23 PM PDT 24
Peak memory 227116 kb
Host smart-2fc54189-3f53-4a1b-9539-a7900c423019
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878146947 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.2878146947
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1632849873
Short name T138
Test name
Test status
Simulation time 518842793 ps
CPU time 5.08 seconds
Started Aug 11 06:13:45 PM PDT 24
Finished Aug 11 06:13:50 PM PDT 24
Peak memory 212096 kb
Host smart-c23f9524-0bc9-4be6-99b2-df4666786e07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632849873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1632849873
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.227947182
Short name T289
Test name
Test status
Simulation time 39454128920 ps
CPU time 193.31 seconds
Started Aug 11 06:13:43 PM PDT 24
Finished Aug 11 06:16:57 PM PDT 24
Peak memory 238436 kb
Host smart-4c73e54d-cfab-4eb5-bf63-3a9139eb96f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227947182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.227947182
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1688341964
Short name T129
Test name
Test status
Simulation time 693975541 ps
CPU time 9.56 seconds
Started Aug 11 06:13:44 PM PDT 24
Finished Aug 11 06:13:54 PM PDT 24
Peak memory 212864 kb
Host smart-dedc6a4b-cb99-4ff6-a99e-c302697a223f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688341964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1688341964
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.4164476120
Short name T218
Test name
Test status
Simulation time 191205787 ps
CPU time 6.26 seconds
Started Aug 11 06:13:54 PM PDT 24
Finished Aug 11 06:14:00 PM PDT 24
Peak memory 212088 kb
Host smart-aca0bd58-e26b-421d-a621-1ff0853b2c33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164476120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.4164476120
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2832184075
Short name T16
Test name
Test status
Simulation time 979105887 ps
CPU time 13.67 seconds
Started Aug 11 06:13:45 PM PDT 24
Finished Aug 11 06:13:59 PM PDT 24
Peak memory 214680 kb
Host smart-03030a58-6864-4449-90f8-64a9ae034bbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832184075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2832184075
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.460234519
Short name T66
Test name
Test status
Simulation time 129633909 ps
CPU time 5.29 seconds
Started Aug 11 06:13:56 PM PDT 24
Finished Aug 11 06:14:02 PM PDT 24
Peak memory 212016 kb
Host smart-3fef3263-2cef-4697-b7a2-f7d0b5d4511e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460234519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.460234519
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2207688423
Short name T7
Test name
Test status
Simulation time 4817362272 ps
CPU time 70.04 seconds
Started Aug 11 06:14:04 PM PDT 24
Finished Aug 11 06:15:14 PM PDT 24
Peak memory 225704 kb
Host smart-5265ef12-2aee-4027-8fac-e49cd483d6bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207688423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2207688423
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4276647771
Short name T283
Test name
Test status
Simulation time 349929745 ps
CPU time 9.67 seconds
Started Aug 11 06:13:50 PM PDT 24
Finished Aug 11 06:14:00 PM PDT 24
Peak memory 213144 kb
Host smart-643c4146-a92e-406f-a2b3-056246346cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276647771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.4276647771
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2302964622
Short name T134
Test name
Test status
Simulation time 147037109 ps
CPU time 6.64 seconds
Started Aug 11 06:13:57 PM PDT 24
Finished Aug 11 06:14:04 PM PDT 24
Peak memory 212164 kb
Host smart-e4bfd035-8bf7-46ef-bf16-5586b7018671
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2302964622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2302964622
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2988397099
Short name T312
Test name
Test status
Simulation time 671805460 ps
CPU time 10.85 seconds
Started Aug 11 06:13:53 PM PDT 24
Finished Aug 11 06:14:04 PM PDT 24
Peak memory 212092 kb
Host smart-d8769fe9-1faa-4687-94c4-e3179b08255d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988397099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2988397099
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.664061220
Short name T241
Test name
Test status
Simulation time 86705272 ps
CPU time 4.36 seconds
Started Aug 11 06:13:56 PM PDT 24
Finished Aug 11 06:14:00 PM PDT 24
Peak memory 212084 kb
Host smart-32390897-76c1-4ca1-a9fc-3aa31e3fb345
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664061220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.664061220
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3833616413
Short name T161
Test name
Test status
Simulation time 2606756183 ps
CPU time 164.59 seconds
Started Aug 11 06:14:00 PM PDT 24
Finished Aug 11 06:16:45 PM PDT 24
Peak memory 237516 kb
Host smart-361b81b6-28d2-4e86-8bb4-e9e5964d679b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833616413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3833616413
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1183699156
Short name T232
Test name
Test status
Simulation time 982472538 ps
CPU time 9.73 seconds
Started Aug 11 06:14:04 PM PDT 24
Finished Aug 11 06:14:13 PM PDT 24
Peak memory 212828 kb
Host smart-90d6e871-0932-44d2-a853-66c8a824b492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183699156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1183699156
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2470576247
Short name T47
Test name
Test status
Simulation time 377838075 ps
CPU time 5.42 seconds
Started Aug 11 06:13:56 PM PDT 24
Finished Aug 11 06:14:01 PM PDT 24
Peak memory 212100 kb
Host smart-fc065920-3bf0-4ea1-bbb6-4d1929eb7a93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2470576247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2470576247
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.603351268
Short name T176
Test name
Test status
Simulation time 152209567 ps
CPU time 7.9 seconds
Started Aug 11 06:13:49 PM PDT 24
Finished Aug 11 06:13:57 PM PDT 24
Peak memory 212080 kb
Host smart-29a50071-c4ea-4925-8a03-642aa2e9c457
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603351268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.603351268
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2146741986
Short name T54
Test name
Test status
Simulation time 36345091592 ps
CPU time 1420.28 seconds
Started Aug 11 06:14:01 PM PDT 24
Finished Aug 11 06:37:42 PM PDT 24
Peak memory 232404 kb
Host smart-30913c02-0482-4b32-bf2c-69c9b35a94f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146741986 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2146741986
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2911092937
Short name T27
Test name
Test status
Simulation time 133590155 ps
CPU time 5.23 seconds
Started Aug 11 06:13:51 PM PDT 24
Finished Aug 11 06:13:56 PM PDT 24
Peak memory 211984 kb
Host smart-6b3f08a7-f3f0-48c0-b549-afa49ed8c48b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911092937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2911092937
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2319885237
Short name T131
Test name
Test status
Simulation time 4870889091 ps
CPU time 116.49 seconds
Started Aug 11 06:13:51 PM PDT 24
Finished Aug 11 06:15:48 PM PDT 24
Peak memory 238512 kb
Host smart-bb7d5bd4-98ff-4289-bb32-537f22c727ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319885237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2319885237
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3745215718
Short name T177
Test name
Test status
Simulation time 996629357 ps
CPU time 11.13 seconds
Started Aug 11 06:13:52 PM PDT 24
Finished Aug 11 06:14:03 PM PDT 24
Peak memory 213176 kb
Host smart-77df96e8-5a1c-44b9-9b60-6530bd54a1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745215718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3745215718
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.675377457
Short name T45
Test name
Test status
Simulation time 603673842 ps
CPU time 6.46 seconds
Started Aug 11 06:13:50 PM PDT 24
Finished Aug 11 06:13:57 PM PDT 24
Peak memory 212176 kb
Host smart-75807323-eba5-4def-a99b-b3ba47ea0a17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=675377457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.675377457
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2357213573
Short name T147
Test name
Test status
Simulation time 330560499 ps
CPU time 9.9 seconds
Started Aug 11 06:13:50 PM PDT 24
Finished Aug 11 06:14:00 PM PDT 24
Peak memory 213184 kb
Host smart-966e768e-468f-4220-98f0-170451c23f3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357213573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2357213573
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2949196581
Short name T261
Test name
Test status
Simulation time 256964285 ps
CPU time 5.24 seconds
Started Aug 11 06:13:51 PM PDT 24
Finished Aug 11 06:13:57 PM PDT 24
Peak memory 212092 kb
Host smart-99ebc431-6880-4d97-aef2-cd90da9b9c5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949196581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2949196581
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3091693818
Short name T180
Test name
Test status
Simulation time 12847979640 ps
CPU time 117.84 seconds
Started Aug 11 06:13:54 PM PDT 24
Finished Aug 11 06:15:52 PM PDT 24
Peak memory 226352 kb
Host smart-ba4a07e7-1776-4eaf-9642-2355fc8421b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091693818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3091693818
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2976831563
Short name T313
Test name
Test status
Simulation time 693197395 ps
CPU time 9.64 seconds
Started Aug 11 06:13:48 PM PDT 24
Finished Aug 11 06:13:58 PM PDT 24
Peak memory 212760 kb
Host smart-a7e8dd1c-1d75-40fd-9d81-3ca4662e96e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976831563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2976831563
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2862110385
Short name T324
Test name
Test status
Simulation time 194292068 ps
CPU time 5.2 seconds
Started Aug 11 06:13:54 PM PDT 24
Finished Aug 11 06:14:00 PM PDT 24
Peak memory 212156 kb
Host smart-144a7cd4-0a46-48be-89b4-48614aeeb8ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2862110385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2862110385
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3525908855
Short name T315
Test name
Test status
Simulation time 562315560 ps
CPU time 12.45 seconds
Started Aug 11 06:13:50 PM PDT 24
Finished Aug 11 06:14:03 PM PDT 24
Peak memory 212116 kb
Host smart-1afb6652-b981-4345-939b-6de5ddf76dd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525908855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3525908855
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.81029618
Short name T12
Test name
Test status
Simulation time 37682348350 ps
CPU time 1453.58 seconds
Started Aug 11 06:13:56 PM PDT 24
Finished Aug 11 06:38:10 PM PDT 24
Peak memory 236676 kb
Host smart-dcf2915c-cc6d-45c9-af54-1ddf8c7e4e9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81029618 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.81029618
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.351458850
Short name T162
Test name
Test status
Simulation time 260293281 ps
CPU time 5.24 seconds
Started Aug 11 06:14:04 PM PDT 24
Finished Aug 11 06:14:10 PM PDT 24
Peak memory 211996 kb
Host smart-9786608e-5cc6-4778-ba78-3f2514d99261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351458850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.351458850
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2251462957
Short name T38
Test name
Test status
Simulation time 13388311878 ps
CPU time 176.25 seconds
Started Aug 11 06:14:01 PM PDT 24
Finished Aug 11 06:16:57 PM PDT 24
Peak memory 234396 kb
Host smart-76b22709-b599-4de8-9c41-4acb9ac799c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251462957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2251462957
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.268904716
Short name T254
Test name
Test status
Simulation time 698808156 ps
CPU time 9.64 seconds
Started Aug 11 06:13:56 PM PDT 24
Finished Aug 11 06:14:06 PM PDT 24
Peak memory 213348 kb
Host smart-f0f21876-2905-4985-8d11-98bc9959681e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268904716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.268904716
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1706099019
Short name T300
Test name
Test status
Simulation time 563297089 ps
CPU time 6.67 seconds
Started Aug 11 06:13:49 PM PDT 24
Finished Aug 11 06:13:56 PM PDT 24
Peak memory 212196 kb
Host smart-c1cf2b81-0b13-40e4-9172-a2cceea26587
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1706099019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1706099019
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3524966066
Short name T219
Test name
Test status
Simulation time 389422343 ps
CPU time 6.66 seconds
Started Aug 11 06:13:49 PM PDT 24
Finished Aug 11 06:13:56 PM PDT 24
Peak memory 212108 kb
Host smart-39457d2e-3655-46e9-a920-21a32da9186e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524966066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3524966066
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1249432027
Short name T56
Test name
Test status
Simulation time 230403359959 ps
CPU time 2457 seconds
Started Aug 11 06:14:02 PM PDT 24
Finished Aug 11 06:55:00 PM PDT 24
Peak memory 244904 kb
Host smart-8f0a2f90-a8d8-4503-8213-2c95ad4db2be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249432027 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1249432027
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2229619296
Short name T225
Test name
Test status
Simulation time 498888863 ps
CPU time 5.24 seconds
Started Aug 11 06:13:58 PM PDT 24
Finished Aug 11 06:14:03 PM PDT 24
Peak memory 212092 kb
Host smart-e42ee8f9-5855-4495-b042-4fcb15dff063
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229619296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2229619296
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1959348410
Short name T290
Test name
Test status
Simulation time 7209415935 ps
CPU time 130.78 seconds
Started Aug 11 06:14:00 PM PDT 24
Finished Aug 11 06:16:11 PM PDT 24
Peak memory 238456 kb
Host smart-158a3ca0-138a-4f12-9471-ff3c5bf9c3e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959348410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1959348410
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3756451861
Short name T314
Test name
Test status
Simulation time 670735043 ps
CPU time 9.66 seconds
Started Aug 11 06:14:01 PM PDT 24
Finished Aug 11 06:14:11 PM PDT 24
Peak memory 213232 kb
Host smart-6ff73cf9-533d-4191-876a-3005686af82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756451861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3756451861
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.217812017
Short name T227
Test name
Test status
Simulation time 401811128 ps
CPU time 5.42 seconds
Started Aug 11 06:13:58 PM PDT 24
Finished Aug 11 06:14:03 PM PDT 24
Peak memory 212160 kb
Host smart-e652af13-d033-43a8-a177-9590dc89d68d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=217812017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.217812017
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.415717516
Short name T273
Test name
Test status
Simulation time 1239910488 ps
CPU time 14.08 seconds
Started Aug 11 06:14:02 PM PDT 24
Finished Aug 11 06:14:16 PM PDT 24
Peak memory 215476 kb
Host smart-b58b07ee-56f8-4662-a8cd-d1dcd997e63e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415717516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.415717516
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.96096967
Short name T122
Test name
Test status
Simulation time 772411962 ps
CPU time 5.14 seconds
Started Aug 11 06:13:38 PM PDT 24
Finished Aug 11 06:13:43 PM PDT 24
Peak memory 212028 kb
Host smart-c6669cc8-b437-4877-85e4-acf2d57ef0aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96096967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.96096967
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1728342752
Short name T153
Test name
Test status
Simulation time 1715871444 ps
CPU time 98.77 seconds
Started Aug 11 06:13:32 PM PDT 24
Finished Aug 11 06:15:11 PM PDT 24
Peak memory 213384 kb
Host smart-fac09047-ec7e-40d3-a5d0-9104e9ccc7fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728342752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1728342752
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2060709028
Short name T151
Test name
Test status
Simulation time 996811191 ps
CPU time 11.02 seconds
Started Aug 11 06:13:27 PM PDT 24
Finished Aug 11 06:13:38 PM PDT 24
Peak memory 213024 kb
Host smart-38599129-d49a-4131-be34-b06a1b6efe10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060709028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2060709028
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.976565568
Short name T152
Test name
Test status
Simulation time 139381991 ps
CPU time 6.71 seconds
Started Aug 11 06:13:34 PM PDT 24
Finished Aug 11 06:13:40 PM PDT 24
Peak memory 212088 kb
Host smart-147fc7db-b5b8-4d81-97d2-06eb8be574eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=976565568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.976565568
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2828049923
Short name T21
Test name
Test status
Simulation time 633601293 ps
CPU time 52.46 seconds
Started Aug 11 06:13:26 PM PDT 24
Finished Aug 11 06:14:19 PM PDT 24
Peak memory 237968 kb
Host smart-e6657a12-d018-4ac1-bf1d-b213e023210b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828049923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2828049923
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.504998506
Short name T13
Test name
Test status
Simulation time 443887252 ps
CPU time 5.46 seconds
Started Aug 11 06:13:31 PM PDT 24
Finished Aug 11 06:13:37 PM PDT 24
Peak memory 212220 kb
Host smart-009e840b-f37f-4aa3-8794-9c6838f9c5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504998506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.504998506
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1427787852
Short name T182
Test name
Test status
Simulation time 1135063204 ps
CPU time 14.96 seconds
Started Aug 11 06:13:30 PM PDT 24
Finished Aug 11 06:13:45 PM PDT 24
Peak memory 215708 kb
Host smart-74ee454c-40c4-4d69-bb39-c8e1ba56fe4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427787852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1427787852
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3579263373
Short name T278
Test name
Test status
Simulation time 140433136 ps
CPU time 5.25 seconds
Started Aug 11 06:13:58 PM PDT 24
Finished Aug 11 06:14:03 PM PDT 24
Peak memory 212068 kb
Host smart-0095fc56-968a-4099-b3ce-36d803e9cd68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579263373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3579263373
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3554540765
Short name T242
Test name
Test status
Simulation time 1542537917 ps
CPU time 105.09 seconds
Started Aug 11 06:13:59 PM PDT 24
Finished Aug 11 06:15:45 PM PDT 24
Peak memory 237596 kb
Host smart-f101d514-45cb-417c-97a6-e5895ac7bdb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554540765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3554540765
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2189551637
Short name T135
Test name
Test status
Simulation time 1037356864 ps
CPU time 11.2 seconds
Started Aug 11 06:13:59 PM PDT 24
Finished Aug 11 06:14:11 PM PDT 24
Peak memory 212860 kb
Host smart-1e1e1d14-b290-44ae-8e18-b423cc664d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189551637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2189551637
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.511040459
Short name T305
Test name
Test status
Simulation time 101255254 ps
CPU time 5.78 seconds
Started Aug 11 06:14:16 PM PDT 24
Finished Aug 11 06:14:21 PM PDT 24
Peak memory 212188 kb
Host smart-e0cad55d-4f99-48ba-9e0e-be91dfdc5045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=511040459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.511040459
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.60564893
Short name T317
Test name
Test status
Simulation time 1534241410 ps
CPU time 19.6 seconds
Started Aug 11 06:13:57 PM PDT 24
Finished Aug 11 06:14:17 PM PDT 24
Peak memory 216628 kb
Host smart-5fdb8e72-4461-48cd-83c0-9f3e34c20c06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60564893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 40.rom_ctrl_stress_all.60564893
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2151951802
Short name T156
Test name
Test status
Simulation time 129096503 ps
CPU time 5.07 seconds
Started Aug 11 06:13:57 PM PDT 24
Finished Aug 11 06:14:02 PM PDT 24
Peak memory 212104 kb
Host smart-ea612f21-edb9-4344-a4cb-d0e9d4f05002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151951802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2151951802
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1279639709
Short name T239
Test name
Test status
Simulation time 2490574503 ps
CPU time 126.89 seconds
Started Aug 11 06:14:00 PM PDT 24
Finished Aug 11 06:16:07 PM PDT 24
Peak memory 237588 kb
Host smart-ab402873-1a3d-4164-80c8-06c71e920f54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279639709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1279639709
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3826976557
Short name T235
Test name
Test status
Simulation time 856075811 ps
CPU time 11.21 seconds
Started Aug 11 06:14:09 PM PDT 24
Finished Aug 11 06:14:20 PM PDT 24
Peak memory 212840 kb
Host smart-d3d85de3-ef8f-4ea2-a50f-a74b2aad74f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826976557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3826976557
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1755885659
Short name T48
Test name
Test status
Simulation time 540330954 ps
CPU time 6.76 seconds
Started Aug 11 06:14:02 PM PDT 24
Finished Aug 11 06:14:08 PM PDT 24
Peak memory 212152 kb
Host smart-62f14924-5ac2-457b-a0f0-2877ddde5378
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1755885659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1755885659
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.504781634
Short name T79
Test name
Test status
Simulation time 1175661784 ps
CPU time 13.39 seconds
Started Aug 11 06:14:03 PM PDT 24
Finished Aug 11 06:14:16 PM PDT 24
Peak memory 213780 kb
Host smart-b236fc25-8480-4b9c-87a9-97dcca628bfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504781634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.504781634
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4102360346
Short name T292
Test name
Test status
Simulation time 336179631 ps
CPU time 4.3 seconds
Started Aug 11 06:14:05 PM PDT 24
Finished Aug 11 06:14:09 PM PDT 24
Peak memory 212092 kb
Host smart-01e5f284-9063-41b6-8653-08af3f50172c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102360346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4102360346
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1907866813
Short name T319
Test name
Test status
Simulation time 4177051110 ps
CPU time 199.25 seconds
Started Aug 11 06:14:06 PM PDT 24
Finished Aug 11 06:17:26 PM PDT 24
Peak memory 239164 kb
Host smart-f0b43bf9-e4f6-4063-94ef-a48d7f035f45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907866813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1907866813
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2524487561
Short name T253
Test name
Test status
Simulation time 694949625 ps
CPU time 9.57 seconds
Started Aug 11 06:14:01 PM PDT 24
Finished Aug 11 06:14:11 PM PDT 24
Peak memory 213116 kb
Host smart-a81638d9-c86e-4a77-acd1-9c7d555f3353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524487561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2524487561
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.25814365
Short name T128
Test name
Test status
Simulation time 138985417 ps
CPU time 6.59 seconds
Started Aug 11 06:14:04 PM PDT 24
Finished Aug 11 06:14:10 PM PDT 24
Peak memory 212176 kb
Host smart-e1d9a7f9-2bdf-4e94-a5de-3727cbef837b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=25814365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.25814365
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2653854298
Short name T277
Test name
Test status
Simulation time 419316428 ps
CPU time 19.67 seconds
Started Aug 11 06:14:02 PM PDT 24
Finished Aug 11 06:14:22 PM PDT 24
Peak memory 214824 kb
Host smart-c87c9354-157a-4baa-a2dd-8764bdc0c4b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653854298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2653854298
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3493778050
Short name T304
Test name
Test status
Simulation time 175083052 ps
CPU time 4.34 seconds
Started Aug 11 06:14:05 PM PDT 24
Finished Aug 11 06:14:09 PM PDT 24
Peak memory 212236 kb
Host smart-8d051bf4-0182-4159-b479-20eb6db3bd27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493778050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3493778050
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1038352569
Short name T237
Test name
Test status
Simulation time 24250955986 ps
CPU time 106.89 seconds
Started Aug 11 06:14:02 PM PDT 24
Finished Aug 11 06:15:49 PM PDT 24
Peak memory 238180 kb
Host smart-75ca7d31-0f1f-438a-bce0-5613fa3b77b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038352569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1038352569
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.169362933
Short name T275
Test name
Test status
Simulation time 195342135 ps
CPU time 5.45 seconds
Started Aug 11 06:14:04 PM PDT 24
Finished Aug 11 06:14:10 PM PDT 24
Peak memory 212108 kb
Host smart-1b326498-7a4e-45e6-944c-c03469ddaa27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=169362933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.169362933
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.631537918
Short name T279
Test name
Test status
Simulation time 392402077 ps
CPU time 23.66 seconds
Started Aug 11 06:14:04 PM PDT 24
Finished Aug 11 06:14:28 PM PDT 24
Peak memory 214964 kb
Host smart-cb9fa7a4-dbd2-4c72-9ef3-bded16027056
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631537918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.631537918
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1851460609
Short name T256
Test name
Test status
Simulation time 174027569557 ps
CPU time 965.29 seconds
Started Aug 11 06:14:01 PM PDT 24
Finished Aug 11 06:30:07 PM PDT 24
Peak memory 236696 kb
Host smart-f4e236a3-ff67-4236-aed8-b0996e54eabf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851460609 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1851460609
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2063870958
Short name T144
Test name
Test status
Simulation time 168134475 ps
CPU time 4.47 seconds
Started Aug 11 06:14:00 PM PDT 24
Finished Aug 11 06:14:05 PM PDT 24
Peak memory 212040 kb
Host smart-e4688d1d-dc4a-40ed-9195-b47a1937247c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063870958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2063870958
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1517999793
Short name T159
Test name
Test status
Simulation time 9300349750 ps
CPU time 115.96 seconds
Started Aug 11 06:14:04 PM PDT 24
Finished Aug 11 06:16:00 PM PDT 24
Peak memory 239356 kb
Host smart-e41102f5-1068-4f8c-82a5-fe299b4ddefa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517999793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1517999793
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3020519311
Short name T143
Test name
Test status
Simulation time 188951321 ps
CPU time 9.54 seconds
Started Aug 11 06:14:04 PM PDT 24
Finished Aug 11 06:14:14 PM PDT 24
Peak memory 212816 kb
Host smart-5d972440-3f85-4c0a-a7db-5f47ff214a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020519311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3020519311
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3795268716
Short name T43
Test name
Test status
Simulation time 136968475 ps
CPU time 6.41 seconds
Started Aug 11 06:14:03 PM PDT 24
Finished Aug 11 06:14:09 PM PDT 24
Peak memory 212340 kb
Host smart-e25b9d62-44f6-4374-b2ff-70060a38dd40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795268716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3795268716
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2365348118
Short name T205
Test name
Test status
Simulation time 349886304 ps
CPU time 18.04 seconds
Started Aug 11 06:14:03 PM PDT 24
Finished Aug 11 06:14:21 PM PDT 24
Peak memory 215452 kb
Host smart-99bb3ace-3bb9-409a-bd02-d8a6d3d85d45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365348118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2365348118
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1820543351
Short name T19
Test name
Test status
Simulation time 169891480 ps
CPU time 4.43 seconds
Started Aug 11 06:14:12 PM PDT 24
Finished Aug 11 06:14:16 PM PDT 24
Peak memory 212044 kb
Host smart-ab277255-68aa-4e4c-93c2-0ef1a00d8a9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820543351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1820543351
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.721645796
Short name T311
Test name
Test status
Simulation time 8791656998 ps
CPU time 115.08 seconds
Started Aug 11 06:14:07 PM PDT 24
Finished Aug 11 06:16:02 PM PDT 24
Peak memory 234756 kb
Host smart-889fb4e8-74f1-4c3d-bde4-6a31c19b58aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721645796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.721645796
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.4040210007
Short name T266
Test name
Test status
Simulation time 169521354 ps
CPU time 9.73 seconds
Started Aug 11 06:14:04 PM PDT 24
Finished Aug 11 06:14:14 PM PDT 24
Peak memory 212824 kb
Host smart-0158e0b2-cf62-4703-9411-31ec11dff29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040210007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.4040210007
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1083673741
Short name T118
Test name
Test status
Simulation time 607521153 ps
CPU time 6.27 seconds
Started Aug 11 06:14:02 PM PDT 24
Finished Aug 11 06:14:09 PM PDT 24
Peak memory 212040 kb
Host smart-df7c251d-969e-4fb9-9608-9e52f2bdfeb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1083673741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1083673741
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1647372025
Short name T127
Test name
Test status
Simulation time 405592691 ps
CPU time 10.67 seconds
Started Aug 11 06:14:03 PM PDT 24
Finished Aug 11 06:14:14 PM PDT 24
Peak memory 214712 kb
Host smart-e8c20132-a951-47ba-883f-74e9650b192b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647372025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1647372025
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1881189793
Short name T297
Test name
Test status
Simulation time 97946031 ps
CPU time 4.39 seconds
Started Aug 11 06:14:10 PM PDT 24
Finished Aug 11 06:14:15 PM PDT 24
Peak memory 212016 kb
Host smart-2bb2d681-750e-45a1-a539-601780b5fd51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881189793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1881189793
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.956927330
Short name T40
Test name
Test status
Simulation time 2115314615 ps
CPU time 118.15 seconds
Started Aug 11 06:14:09 PM PDT 24
Finished Aug 11 06:16:07 PM PDT 24
Peak memory 237360 kb
Host smart-a537f4a5-ff6c-4af2-8e15-576147972572
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956927330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.956927330
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2846160932
Short name T3
Test name
Test status
Simulation time 261790609 ps
CPU time 10.98 seconds
Started Aug 11 06:14:12 PM PDT 24
Finished Aug 11 06:14:23 PM PDT 24
Peak memory 213008 kb
Host smart-5d570252-6673-49a6-9404-d8f63d846259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846160932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2846160932
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.4155155549
Short name T31
Test name
Test status
Simulation time 197181449 ps
CPU time 6 seconds
Started Aug 11 06:14:12 PM PDT 24
Finished Aug 11 06:14:18 PM PDT 24
Peak memory 212108 kb
Host smart-a1ca1d78-53f5-44f6-acf4-044b26d16b8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4155155549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.4155155549
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3119021470
Short name T120
Test name
Test status
Simulation time 2090268131 ps
CPU time 13.97 seconds
Started Aug 11 06:14:12 PM PDT 24
Finished Aug 11 06:14:26 PM PDT 24
Peak memory 214844 kb
Host smart-e83dfba0-beb2-434d-b923-70563caa0fb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119021470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3119021470
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2520817535
Short name T198
Test name
Test status
Simulation time 181091969 ps
CPU time 4.34 seconds
Started Aug 11 06:14:14 PM PDT 24
Finished Aug 11 06:14:18 PM PDT 24
Peak memory 212076 kb
Host smart-f235c760-0e8f-469c-9618-f17ca8c497d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520817535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2520817535
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.437400672
Short name T291
Test name
Test status
Simulation time 10678660276 ps
CPU time 188.61 seconds
Started Aug 11 06:14:13 PM PDT 24
Finished Aug 11 06:17:22 PM PDT 24
Peak memory 229256 kb
Host smart-58c4f405-bf59-4446-8819-ae04ce3cb2b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437400672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.437400672
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2738373519
Short name T24
Test name
Test status
Simulation time 697220375 ps
CPU time 9.38 seconds
Started Aug 11 06:14:12 PM PDT 24
Finished Aug 11 06:14:22 PM PDT 24
Peak memory 213248 kb
Host smart-e598fb66-3d02-48c9-a9b2-71c459283752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738373519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2738373519
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.574693548
Short name T165
Test name
Test status
Simulation time 136479971 ps
CPU time 6.53 seconds
Started Aug 11 06:14:12 PM PDT 24
Finished Aug 11 06:14:18 PM PDT 24
Peak memory 212152 kb
Host smart-4301f1f0-0fd6-4bdd-832c-a64b42023e02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=574693548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.574693548
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.4102906869
Short name T78
Test name
Test status
Simulation time 454439753 ps
CPU time 11.78 seconds
Started Aug 11 06:14:10 PM PDT 24
Finished Aug 11 06:14:22 PM PDT 24
Peak memory 213956 kb
Host smart-dc47b13e-d101-476e-b04a-fb5a335fb5ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102906869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.4102906869
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1640503607
Short name T53
Test name
Test status
Simulation time 78775037218 ps
CPU time 2865.02 seconds
Started Aug 11 06:14:13 PM PDT 24
Finished Aug 11 07:01:58 PM PDT 24
Peak memory 248556 kb
Host smart-95e179b8-c7b6-4c26-a3ce-b16415c41468
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640503607 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1640503607
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3316473424
Short name T288
Test name
Test status
Simulation time 90847878 ps
CPU time 4.23 seconds
Started Aug 11 06:14:10 PM PDT 24
Finished Aug 11 06:14:14 PM PDT 24
Peak memory 211992 kb
Host smart-8a3997bb-f446-48d8-9fa0-313bcc57e453
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316473424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3316473424
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1434794184
Short name T331
Test name
Test status
Simulation time 6450401404 ps
CPU time 87.06 seconds
Started Aug 11 06:14:13 PM PDT 24
Finished Aug 11 06:15:40 PM PDT 24
Peak memory 213444 kb
Host smart-135bfe85-d08d-4426-853c-284dc813210d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434794184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1434794184
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.448520932
Short name T257
Test name
Test status
Simulation time 501433838 ps
CPU time 11.49 seconds
Started Aug 11 06:14:12 PM PDT 24
Finished Aug 11 06:14:24 PM PDT 24
Peak memory 212768 kb
Host smart-c39125f9-118f-40f1-8ffd-d14380d57eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448520932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.448520932
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.5970422
Short name T136
Test name
Test status
Simulation time 819235645 ps
CPU time 5.27 seconds
Started Aug 11 06:14:14 PM PDT 24
Finished Aug 11 06:14:20 PM PDT 24
Peak memory 212136 kb
Host smart-1ab37f47-2211-4a5a-b027-d06a43dc23ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5970422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.5970422
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3064705775
Short name T248
Test name
Test status
Simulation time 135811459 ps
CPU time 7.91 seconds
Started Aug 11 06:14:17 PM PDT 24
Finished Aug 11 06:14:25 PM PDT 24
Peak memory 212120 kb
Host smart-8eb443b7-3bed-4e45-840e-8473b90768c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064705775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3064705775
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1069556237
Short name T247
Test name
Test status
Simulation time 96599079579 ps
CPU time 7104.49 seconds
Started Aug 11 06:14:15 PM PDT 24
Finished Aug 11 08:12:40 PM PDT 24
Peak memory 231008 kb
Host smart-745745d6-29ee-4f03-bb5f-c2c6c23a6ec8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069556237 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.1069556237
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3417634254
Short name T238
Test name
Test status
Simulation time 126951019 ps
CPU time 5.32 seconds
Started Aug 11 06:14:17 PM PDT 24
Finished Aug 11 06:14:22 PM PDT 24
Peak memory 211900 kb
Host smart-d46541d1-5efa-4b87-80e9-e528f023c773
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417634254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3417634254
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2462961228
Short name T173
Test name
Test status
Simulation time 2120311171 ps
CPU time 144.19 seconds
Started Aug 11 06:14:14 PM PDT 24
Finished Aug 11 06:16:39 PM PDT 24
Peak memory 238372 kb
Host smart-c5d146b8-634d-4bc2-804a-0edac9d1ac85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462961228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2462961228
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.387324965
Short name T124
Test name
Test status
Simulation time 510067759 ps
CPU time 11.28 seconds
Started Aug 11 06:14:14 PM PDT 24
Finished Aug 11 06:14:26 PM PDT 24
Peak memory 212912 kb
Host smart-56887a42-70d7-4fbc-9b5b-22ca770a61f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387324965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.387324965
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1522079988
Short name T123
Test name
Test status
Simulation time 387816479 ps
CPU time 5.63 seconds
Started Aug 11 06:14:14 PM PDT 24
Finished Aug 11 06:14:20 PM PDT 24
Peak memory 212160 kb
Host smart-55edca51-07a5-432b-beef-d9551a0c5496
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1522079988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1522079988
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2521386982
Short name T192
Test name
Test status
Simulation time 667068914 ps
CPU time 14.33 seconds
Started Aug 11 06:14:15 PM PDT 24
Finished Aug 11 06:14:29 PM PDT 24
Peak memory 215452 kb
Host smart-2a27eb0d-01a4-47c3-88ae-cd44e955b02c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521386982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2521386982
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1257656270
Short name T210
Test name
Test status
Simulation time 497753175 ps
CPU time 5.23 seconds
Started Aug 11 06:13:30 PM PDT 24
Finished Aug 11 06:13:36 PM PDT 24
Peak memory 212056 kb
Host smart-2545ed88-ec6d-4f07-a7dd-aee1fcafa58b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257656270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1257656270
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4125377245
Short name T132
Test name
Test status
Simulation time 7843085958 ps
CPU time 109.92 seconds
Started Aug 11 06:13:38 PM PDT 24
Finished Aug 11 06:15:28 PM PDT 24
Peak memory 240880 kb
Host smart-959351a8-6872-4656-91a6-e3fe80057add
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125377245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.4125377245
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2685555697
Short name T183
Test name
Test status
Simulation time 1038433519 ps
CPU time 11.46 seconds
Started Aug 11 06:13:35 PM PDT 24
Finished Aug 11 06:13:46 PM PDT 24
Peak memory 212972 kb
Host smart-8793b5f2-ae17-4334-92dc-468144b2eecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685555697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2685555697
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3165646554
Short name T282
Test name
Test status
Simulation time 521775361 ps
CPU time 6.42 seconds
Started Aug 11 06:13:36 PM PDT 24
Finished Aug 11 06:13:43 PM PDT 24
Peak memory 212164 kb
Host smart-2b8ec882-e7f7-4605-bed5-bb79f868d1ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3165646554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3165646554
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2789152732
Short name T148
Test name
Test status
Simulation time 561227790 ps
CPU time 6.17 seconds
Started Aug 11 06:13:37 PM PDT 24
Finished Aug 11 06:13:44 PM PDT 24
Peak memory 212124 kb
Host smart-72262aaf-2bf0-484d-b9d9-14d3b91d0a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789152732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2789152732
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3191307714
Short name T15
Test name
Test status
Simulation time 666317270 ps
CPU time 10.75 seconds
Started Aug 11 06:13:39 PM PDT 24
Finished Aug 11 06:13:50 PM PDT 24
Peak memory 212420 kb
Host smart-600efcde-3a24-4de5-9fd4-3230c54dc063
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191307714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3191307714
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.366304808
Short name T252
Test name
Test status
Simulation time 32673908559 ps
CPU time 3798.79 seconds
Started Aug 11 06:13:36 PM PDT 24
Finished Aug 11 07:16:55 PM PDT 24
Peak memory 220244 kb
Host smart-bd9e9a9c-b4d4-4938-8307-0c57d2114a40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366304808 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.366304808
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.540336343
Short name T130
Test name
Test status
Simulation time 90231919 ps
CPU time 4.17 seconds
Started Aug 11 06:13:34 PM PDT 24
Finished Aug 11 06:13:39 PM PDT 24
Peak memory 212072 kb
Host smart-e382dba8-a69b-4e96-9271-a4d7337a8380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540336343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.540336343
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4097273576
Short name T209
Test name
Test status
Simulation time 2404777100 ps
CPU time 115.93 seconds
Started Aug 11 06:13:30 PM PDT 24
Finished Aug 11 06:15:26 PM PDT 24
Peak memory 213504 kb
Host smart-a5222779-5a0c-404f-9a92-1dd1ae484598
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097273576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.4097273576
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2002482173
Short name T332
Test name
Test status
Simulation time 341133297 ps
CPU time 9.54 seconds
Started Aug 11 06:13:31 PM PDT 24
Finished Aug 11 06:13:41 PM PDT 24
Peak memory 212972 kb
Host smart-d7f9e2ad-1889-4e6e-9750-dbadb89f3fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002482173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2002482173
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3101247625
Short name T188
Test name
Test status
Simulation time 440487785 ps
CPU time 6.04 seconds
Started Aug 11 06:13:34 PM PDT 24
Finished Aug 11 06:13:40 PM PDT 24
Peak memory 212164 kb
Host smart-17819ad6-0fbb-4f65-8aca-7d3aa854353d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3101247625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3101247625
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3573441792
Short name T321
Test name
Test status
Simulation time 270438606 ps
CPU time 6.41 seconds
Started Aug 11 06:13:27 PM PDT 24
Finished Aug 11 06:13:34 PM PDT 24
Peak memory 212208 kb
Host smart-5793032d-b79f-4cf4-9244-f2e84fa97573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573441792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3573441792
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.4168880106
Short name T293
Test name
Test status
Simulation time 1052854288 ps
CPU time 11.15 seconds
Started Aug 11 06:13:31 PM PDT 24
Finished Aug 11 06:13:42 PM PDT 24
Peak memory 214764 kb
Host smart-cf855a4f-7333-4284-9442-11f0d52b6e93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168880106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.4168880106
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.4189193769
Short name T55
Test name
Test status
Simulation time 49440450703 ps
CPU time 1997.16 seconds
Started Aug 11 06:13:38 PM PDT 24
Finished Aug 11 06:46:55 PM PDT 24
Peak memory 238812 kb
Host smart-bd2d86a7-57ca-4efd-9ea6-c6d8701b15cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189193769 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.4189193769
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.4168479055
Short name T323
Test name
Test status
Simulation time 496935109 ps
CPU time 5.12 seconds
Started Aug 11 06:13:30 PM PDT 24
Finished Aug 11 06:13:36 PM PDT 24
Peak memory 212064 kb
Host smart-ec02a27c-2fbd-467f-ace7-82ddb19fc53e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168479055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.4168479055
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2054157378
Short name T141
Test name
Test status
Simulation time 4481543590 ps
CPU time 112.45 seconds
Started Aug 11 06:13:29 PM PDT 24
Finished Aug 11 06:15:21 PM PDT 24
Peak memory 229012 kb
Host smart-41b8fab6-0674-47a4-831f-948c575708e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054157378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2054157378
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3264366895
Short name T213
Test name
Test status
Simulation time 795349651 ps
CPU time 9.46 seconds
Started Aug 11 06:13:37 PM PDT 24
Finished Aug 11 06:13:47 PM PDT 24
Peak memory 212908 kb
Host smart-e85887a8-493e-45e4-a96c-6e9ab70ff0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264366895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3264366895
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3118360882
Short name T164
Test name
Test status
Simulation time 138200885 ps
CPU time 6.3 seconds
Started Aug 11 06:13:32 PM PDT 24
Finished Aug 11 06:13:38 PM PDT 24
Peak memory 212124 kb
Host smart-34a9c13c-59fa-4053-bc26-17998c5f8f1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3118360882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3118360882
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2103177597
Short name T61
Test name
Test status
Simulation time 137035949 ps
CPU time 6.53 seconds
Started Aug 11 06:13:35 PM PDT 24
Finished Aug 11 06:13:42 PM PDT 24
Peak memory 212208 kb
Host smart-29b3399d-2ca0-411d-8a93-de5fb954a1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103177597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2103177597
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.442818925
Short name T308
Test name
Test status
Simulation time 740092064 ps
CPU time 10.31 seconds
Started Aug 11 06:13:30 PM PDT 24
Finished Aug 11 06:13:40 PM PDT 24
Peak memory 213584 kb
Host smart-cc48d606-e713-4005-ab3c-e8947c173cce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442818925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.442818925
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2475525712
Short name T255
Test name
Test status
Simulation time 128823929 ps
CPU time 5.04 seconds
Started Aug 11 06:13:37 PM PDT 24
Finished Aug 11 06:13:42 PM PDT 24
Peak memory 212044 kb
Host smart-f2f066ed-68dd-4f4f-b9e6-a04e22d72955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475525712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2475525712
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2744768624
Short name T160
Test name
Test status
Simulation time 1885895395 ps
CPU time 87.52 seconds
Started Aug 11 06:13:34 PM PDT 24
Finished Aug 11 06:15:02 PM PDT 24
Peak memory 238252 kb
Host smart-3a6a1301-5fd3-4c90-9e79-07b7a419e438
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744768624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2744768624
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3070800434
Short name T190
Test name
Test status
Simulation time 251205323 ps
CPU time 10.81 seconds
Started Aug 11 06:13:28 PM PDT 24
Finished Aug 11 06:13:39 PM PDT 24
Peak memory 212952 kb
Host smart-eb4671cb-7743-4448-85c7-0555e1fb00c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070800434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3070800434
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3346426242
Short name T264
Test name
Test status
Simulation time 132595601 ps
CPU time 5.45 seconds
Started Aug 11 06:13:38 PM PDT 24
Finished Aug 11 06:13:44 PM PDT 24
Peak memory 212120 kb
Host smart-cf20d69d-c516-4971-83e2-f25106ed91d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3346426242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3346426242
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1310413257
Short name T9
Test name
Test status
Simulation time 193506004 ps
CPU time 5.48 seconds
Started Aug 11 06:13:33 PM PDT 24
Finished Aug 11 06:13:38 PM PDT 24
Peak memory 212172 kb
Host smart-1314be91-8f7d-438f-9a33-93731f2e0bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310413257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1310413257
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3069703898
Short name T281
Test name
Test status
Simulation time 3079611908 ps
CPU time 17.84 seconds
Started Aug 11 06:13:35 PM PDT 24
Finished Aug 11 06:13:53 PM PDT 24
Peak memory 215548 kb
Host smart-4cf14195-243f-41d6-bec5-ad531021dee1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069703898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3069703898
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.641427868
Short name T116
Test name
Test status
Simulation time 979574618 ps
CPU time 7.86 seconds
Started Aug 11 06:13:31 PM PDT 24
Finished Aug 11 06:13:39 PM PDT 24
Peak memory 211996 kb
Host smart-8df7835a-a3cf-4343-a2e8-26551520c291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641427868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.641427868
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3083391270
Short name T197
Test name
Test status
Simulation time 9918967557 ps
CPU time 118.4 seconds
Started Aug 11 06:13:24 PM PDT 24
Finished Aug 11 06:15:22 PM PDT 24
Peak memory 225744 kb
Host smart-261db6c3-2c58-4c85-ad2d-67c2cfc7399c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083391270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3083391270
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.488216039
Short name T117
Test name
Test status
Simulation time 1035524408 ps
CPU time 16.34 seconds
Started Aug 11 06:13:37 PM PDT 24
Finished Aug 11 06:13:54 PM PDT 24
Peak memory 212892 kb
Host smart-7cb95cdd-b22f-4e66-a10d-20327d2c793a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488216039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.488216039
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3346982905
Short name T249
Test name
Test status
Simulation time 205538330 ps
CPU time 5.62 seconds
Started Aug 11 06:13:34 PM PDT 24
Finished Aug 11 06:13:40 PM PDT 24
Peak memory 212164 kb
Host smart-11dc4ff1-77dd-4bb9-aec6-339c136ba93c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3346982905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3346982905
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.136555894
Short name T299
Test name
Test status
Simulation time 101522878 ps
CPU time 5.69 seconds
Started Aug 11 06:13:30 PM PDT 24
Finished Aug 11 06:13:36 PM PDT 24
Peak memory 212232 kb
Host smart-e5ab8797-c136-46cb-ab53-9c81e933a32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136555894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.136555894
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.671827769
Short name T187
Test name
Test status
Simulation time 2343327608 ps
CPU time 15.85 seconds
Started Aug 11 06:13:36 PM PDT 24
Finished Aug 11 06:13:52 PM PDT 24
Peak memory 216988 kb
Host smart-fa97dbfa-96df-4db7-a63b-74274b73703b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671827769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.671827769
Directory /workspace/9.rom_ctrl_stress_all/latest
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