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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.19 96.89 91.85 97.67 100.00 98.28 97.30 98.37


Total test records in report: 412
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T300 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1588218231 Aug 12 05:08:21 PM PDT 24 Aug 12 05:08:32 PM PDT 24 261132070 ps
T301 /workspace/coverage/default/46.rom_ctrl_alert_test.2746900704 Aug 12 05:08:21 PM PDT 24 Aug 12 05:08:26 PM PDT 24 86443634 ps
T302 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.962506578 Aug 12 05:07:52 PM PDT 24 Aug 12 05:10:20 PM PDT 24 4795078871 ps
T303 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2155083226 Aug 12 05:08:19 PM PDT 24 Aug 12 05:11:18 PM PDT 24 44215282668 ps
T304 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.365448217 Aug 12 05:07:34 PM PDT 24 Aug 12 05:07:44 PM PDT 24 178186453 ps
T305 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2316894832 Aug 12 05:08:13 PM PDT 24 Aug 12 05:10:23 PM PDT 24 11122846357 ps
T306 /workspace/coverage/default/33.rom_ctrl_stress_all.4190274302 Aug 12 05:08:03 PM PDT 24 Aug 12 05:08:20 PM PDT 24 812541760 ps
T307 /workspace/coverage/default/8.rom_ctrl_smoke.1711182448 Aug 12 05:07:28 PM PDT 24 Aug 12 05:07:35 PM PDT 24 531517294 ps
T308 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3755744746 Aug 12 05:07:31 PM PDT 24 Aug 12 05:07:37 PM PDT 24 1884869911 ps
T309 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3548665176 Aug 12 05:07:36 PM PDT 24 Aug 12 05:07:46 PM PDT 24 174627093 ps
T310 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2875948559 Aug 12 05:07:21 PM PDT 24 Aug 12 05:07:32 PM PDT 24 252234204 ps
T311 /workspace/coverage/default/10.rom_ctrl_stress_all.1369522537 Aug 12 05:07:38 PM PDT 24 Aug 12 05:07:46 PM PDT 24 433533681 ps
T312 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4136292551 Aug 12 05:07:21 PM PDT 24 Aug 12 05:07:30 PM PDT 24 168194383 ps
T313 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3306679932 Aug 12 05:07:28 PM PDT 24 Aug 12 05:07:38 PM PDT 24 178642103 ps
T314 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3751232101 Aug 12 05:08:19 PM PDT 24 Aug 12 05:08:25 PM PDT 24 358733083 ps
T315 /workspace/coverage/default/34.rom_ctrl_alert_test.1008448572 Aug 12 05:08:19 PM PDT 24 Aug 12 05:08:23 PM PDT 24 834585898 ps
T316 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.4260919294 Aug 12 05:08:01 PM PDT 24 Aug 12 05:09:23 PM PDT 24 1347537494 ps
T62 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3169458897 Aug 12 05:49:20 PM PDT 24 Aug 12 05:49:25 PM PDT 24 350965530 ps
T63 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.521781719 Aug 12 05:49:42 PM PDT 24 Aug 12 05:49:47 PM PDT 24 287252401 ps
T64 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3411517899 Aug 12 05:49:12 PM PDT 24 Aug 12 05:49:17 PM PDT 24 461021101 ps
T72 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3024515680 Aug 12 05:49:04 PM PDT 24 Aug 12 05:49:31 PM PDT 24 1120027344 ps
T47 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2417029162 Aug 12 05:49:19 PM PDT 24 Aug 12 05:49:24 PM PDT 24 328960694 ps
T73 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1762188597 Aug 12 05:49:15 PM PDT 24 Aug 12 05:49:43 PM PDT 24 542904346 ps
T74 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1301633226 Aug 12 05:49:00 PM PDT 24 Aug 12 05:49:07 PM PDT 24 133937180 ps
T98 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3779570104 Aug 12 05:49:27 PM PDT 24 Aug 12 05:49:34 PM PDT 24 347003721 ps
T48 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3573564725 Aug 12 05:49:30 PM PDT 24 Aug 12 05:50:09 PM PDT 24 464196401 ps
T317 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2022075920 Aug 12 05:49:13 PM PDT 24 Aug 12 05:49:21 PM PDT 24 4493800316 ps
T49 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.850971361 Aug 12 05:48:56 PM PDT 24 Aug 12 05:49:33 PM PDT 24 230884572 ps
T75 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3761415317 Aug 12 05:49:21 PM PDT 24 Aug 12 05:49:40 PM PDT 24 488355507 ps
T50 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3442037503 Aug 12 05:49:40 PM PDT 24 Aug 12 05:49:46 PM PDT 24 272111241 ps
T51 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2825467803 Aug 12 05:49:24 PM PDT 24 Aug 12 05:50:34 PM PDT 24 847779157 ps
T76 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1426281894 Aug 12 05:49:31 PM PDT 24 Aug 12 05:49:36 PM PDT 24 499541068 ps
T318 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4033159987 Aug 12 05:48:59 PM PDT 24 Aug 12 05:49:03 PM PDT 24 320157377 ps
T52 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2387762570 Aug 12 05:49:29 PM PDT 24 Aug 12 05:50:39 PM PDT 24 600583033 ps
T99 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3173273633 Aug 12 05:49:14 PM PDT 24 Aug 12 05:49:19 PM PDT 24 131799808 ps
T53 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.406488332 Aug 12 05:49:19 PM PDT 24 Aug 12 05:49:29 PM PDT 24 505208579 ps
T100 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3583413446 Aug 12 05:49:29 PM PDT 24 Aug 12 05:49:34 PM PDT 24 126376980 ps
T319 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4066673672 Aug 12 05:48:59 PM PDT 24 Aug 12 05:49:07 PM PDT 24 133735645 ps
T69 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2349907019 Aug 12 05:49:28 PM PDT 24 Aug 12 05:49:37 PM PDT 24 132854287 ps
T77 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2467136406 Aug 12 05:49:33 PM PDT 24 Aug 12 05:50:07 PM PDT 24 828247032 ps
T70 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2267604297 Aug 12 05:49:17 PM PDT 24 Aug 12 05:49:23 PM PDT 24 136206610 ps
T71 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2161233067 Aug 12 05:49:38 PM PDT 24 Aug 12 05:49:48 PM PDT 24 134406694 ps
T78 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2611573980 Aug 12 05:49:36 PM PDT 24 Aug 12 05:50:04 PM PDT 24 4135824767 ps
T320 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3984094910 Aug 12 05:48:59 PM PDT 24 Aug 12 05:49:04 PM PDT 24 175819943 ps
T104 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2090559882 Aug 12 05:49:39 PM PDT 24 Aug 12 05:50:48 PM PDT 24 1068238253 ps
T79 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4246639614 Aug 12 05:49:08 PM PDT 24 Aug 12 05:49:14 PM PDT 24 133539711 ps
T101 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3627396565 Aug 12 05:49:42 PM PDT 24 Aug 12 05:49:48 PM PDT 24 104027889 ps
T321 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3907501489 Aug 12 05:49:24 PM PDT 24 Aug 12 05:49:31 PM PDT 24 886871170 ps
T322 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4022839073 Aug 12 05:48:59 PM PDT 24 Aug 12 05:49:09 PM PDT 24 522540140 ps
T323 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.808796423 Aug 12 05:49:38 PM PDT 24 Aug 12 05:49:44 PM PDT 24 249092361 ps
T80 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4181184777 Aug 12 05:49:11 PM PDT 24 Aug 12 05:49:19 PM PDT 24 181929141 ps
T84 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1766585425 Aug 12 05:49:30 PM PDT 24 Aug 12 05:49:53 PM PDT 24 2371700698 ps
T103 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.519594043 Aug 12 05:49:20 PM PDT 24 Aug 12 05:50:28 PM PDT 24 1264580125 ps
T324 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3500741569 Aug 12 05:49:03 PM PDT 24 Aug 12 05:49:41 PM PDT 24 215468026 ps
T325 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2856688711 Aug 12 05:49:23 PM PDT 24 Aug 12 05:50:01 PM PDT 24 227602395 ps
T326 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2162640609 Aug 12 05:49:04 PM PDT 24 Aug 12 05:49:12 PM PDT 24 266429412 ps
T327 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2566669597 Aug 12 05:49:29 PM PDT 24 Aug 12 05:49:39 PM PDT 24 289036999 ps
T328 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.280396587 Aug 12 05:49:29 PM PDT 24 Aug 12 05:49:35 PM PDT 24 149275045 ps
T329 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3964305679 Aug 12 05:49:31 PM PDT 24 Aug 12 05:49:41 PM PDT 24 648296203 ps
T330 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.855994063 Aug 12 05:48:57 PM PDT 24 Aug 12 05:49:02 PM PDT 24 146284566 ps
T331 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3506815134 Aug 12 05:49:28 PM PDT 24 Aug 12 05:49:33 PM PDT 24 86679598 ps
T85 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3671800953 Aug 12 05:49:13 PM PDT 24 Aug 12 05:49:18 PM PDT 24 127532055 ps
T332 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3598366153 Aug 12 05:49:38 PM PDT 24 Aug 12 05:49:47 PM PDT 24 2232331092 ps
T333 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1180691378 Aug 12 05:49:23 PM PDT 24 Aug 12 05:49:45 PM PDT 24 1073792675 ps
T334 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3977238255 Aug 12 05:49:39 PM PDT 24 Aug 12 05:49:44 PM PDT 24 754986975 ps
T335 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1904928223 Aug 12 05:49:20 PM PDT 24 Aug 12 05:49:42 PM PDT 24 544060787 ps
T86 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1014588456 Aug 12 05:49:23 PM PDT 24 Aug 12 05:49:46 PM PDT 24 1209072723 ps
T336 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3349635534 Aug 12 05:49:42 PM PDT 24 Aug 12 05:50:16 PM PDT 24 1603405631 ps
T337 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.582727881 Aug 12 05:49:00 PM PDT 24 Aug 12 05:49:05 PM PDT 24 127746689 ps
T338 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4253154010 Aug 12 05:49:14 PM PDT 24 Aug 12 05:49:22 PM PDT 24 129086065 ps
T339 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3250691321 Aug 12 05:49:15 PM PDT 24 Aug 12 05:49:53 PM PDT 24 193555198 ps
T107 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1909832976 Aug 12 05:49:35 PM PDT 24 Aug 12 05:50:45 PM PDT 24 321649489 ps
T340 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1295930431 Aug 12 05:49:39 PM PDT 24 Aug 12 05:49:45 PM PDT 24 172450954 ps
T341 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1986557345 Aug 12 05:49:15 PM PDT 24 Aug 12 05:49:22 PM PDT 24 138612083 ps
T342 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2576052918 Aug 12 05:49:27 PM PDT 24 Aug 12 05:49:32 PM PDT 24 364056746 ps
T343 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2863419264 Aug 12 05:49:25 PM PDT 24 Aug 12 05:49:30 PM PDT 24 2469618792 ps
T105 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2158264985 Aug 12 05:49:23 PM PDT 24 Aug 12 05:50:01 PM PDT 24 394359417 ps
T106 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3219734622 Aug 12 05:49:08 PM PDT 24 Aug 12 05:50:17 PM PDT 24 283733317 ps
T344 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2393815754 Aug 12 05:49:24 PM PDT 24 Aug 12 05:49:34 PM PDT 24 2348225170 ps
T345 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1293678676 Aug 12 05:49:24 PM PDT 24 Aug 12 05:49:29 PM PDT 24 131829343 ps
T346 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1704032694 Aug 12 05:49:27 PM PDT 24 Aug 12 05:49:32 PM PDT 24 334392273 ps
T87 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3547196899 Aug 12 05:49:06 PM PDT 24 Aug 12 05:49:24 PM PDT 24 1275297106 ps
T347 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3414702476 Aug 12 05:49:28 PM PDT 24 Aug 12 05:49:34 PM PDT 24 573958399 ps
T348 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1068985749 Aug 12 05:49:14 PM PDT 24 Aug 12 05:49:20 PM PDT 24 323122346 ps
T349 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1258306651 Aug 12 05:49:05 PM PDT 24 Aug 12 05:49:10 PM PDT 24 87144215 ps
T350 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2483965233 Aug 12 05:49:25 PM PDT 24 Aug 12 05:49:31 PM PDT 24 1126161532 ps
T351 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2013433638 Aug 12 05:49:11 PM PDT 24 Aug 12 05:49:16 PM PDT 24 498996655 ps
T352 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2056084784 Aug 12 05:49:00 PM PDT 24 Aug 12 05:49:06 PM PDT 24 143635833 ps
T88 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1798069905 Aug 12 05:49:27 PM PDT 24 Aug 12 05:49:32 PM PDT 24 126017386 ps
T353 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.225874863 Aug 12 05:49:14 PM PDT 24 Aug 12 05:49:19 PM PDT 24 153379315 ps
T354 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3055212240 Aug 12 05:49:12 PM PDT 24 Aug 12 05:49:16 PM PDT 24 89409943 ps
T355 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3176881451 Aug 12 05:49:25 PM PDT 24 Aug 12 05:49:34 PM PDT 24 497732476 ps
T356 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.105451863 Aug 12 05:48:58 PM PDT 24 Aug 12 05:49:03 PM PDT 24 501791757 ps
T357 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3383240523 Aug 12 05:49:06 PM PDT 24 Aug 12 05:49:39 PM PDT 24 789915858 ps
T89 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2957295517 Aug 12 05:49:37 PM PDT 24 Aug 12 05:49:43 PM PDT 24 593583692 ps
T358 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3625231954 Aug 12 05:49:20 PM PDT 24 Aug 12 05:49:25 PM PDT 24 2502742337 ps
T359 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3409869883 Aug 12 05:49:19 PM PDT 24 Aug 12 05:49:23 PM PDT 24 320435331 ps
T360 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.806100279 Aug 12 05:49:08 PM PDT 24 Aug 12 05:49:14 PM PDT 24 129654147 ps
T361 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.170732408 Aug 12 05:48:59 PM PDT 24 Aug 12 05:49:04 PM PDT 24 175509705 ps
T362 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3112130239 Aug 12 05:49:28 PM PDT 24 Aug 12 05:49:33 PM PDT 24 126910566 ps
T363 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2302648843 Aug 12 05:49:04 PM PDT 24 Aug 12 05:49:09 PM PDT 24 499147735 ps
T90 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3182873439 Aug 12 05:49:05 PM PDT 24 Aug 12 05:49:10 PM PDT 24 128638522 ps
T364 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4146768817 Aug 12 05:49:21 PM PDT 24 Aug 12 05:49:25 PM PDT 24 89159210 ps
T365 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2850832065 Aug 12 05:49:27 PM PDT 24 Aug 12 05:49:32 PM PDT 24 420450601 ps
T366 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3955800364 Aug 12 05:48:56 PM PDT 24 Aug 12 05:49:01 PM PDT 24 495586786 ps
T367 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.810980575 Aug 12 05:49:16 PM PDT 24 Aug 12 05:49:21 PM PDT 24 129603138 ps
T368 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2528546301 Aug 12 05:49:27 PM PDT 24 Aug 12 05:49:37 PM PDT 24 247090364 ps
T94 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2624949458 Aug 12 05:49:19 PM PDT 24 Aug 12 05:49:23 PM PDT 24 347044104 ps
T369 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3071889546 Aug 12 05:49:28 PM PDT 24 Aug 12 05:49:35 PM PDT 24 309667396 ps
T370 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3936289342 Aug 12 05:49:12 PM PDT 24 Aug 12 05:50:23 PM PDT 24 631038149 ps
T371 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.727620647 Aug 12 05:49:36 PM PDT 24 Aug 12 05:49:58 PM PDT 24 4332733501 ps
T372 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3145665757 Aug 12 05:49:27 PM PDT 24 Aug 12 05:49:50 PM PDT 24 3477391083 ps
T373 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3840377877 Aug 12 05:49:04 PM PDT 24 Aug 12 05:49:10 PM PDT 24 135061873 ps
T374 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2159713862 Aug 12 05:49:01 PM PDT 24 Aug 12 05:49:10 PM PDT 24 250382829 ps
T109 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3270570065 Aug 12 05:49:19 PM PDT 24 Aug 12 05:50:28 PM PDT 24 1363765387 ps
T375 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2659556684 Aug 12 05:49:30 PM PDT 24 Aug 12 05:49:36 PM PDT 24 622887095 ps
T376 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1083786702 Aug 12 05:49:28 PM PDT 24 Aug 12 05:49:33 PM PDT 24 495522421 ps
T377 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3156123988 Aug 12 05:49:39 PM PDT 24 Aug 12 05:49:44 PM PDT 24 399416350 ps
T378 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1343028094 Aug 12 05:49:28 PM PDT 24 Aug 12 05:49:34 PM PDT 24 220864018 ps
T379 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.741613993 Aug 12 05:49:38 PM PDT 24 Aug 12 05:49:44 PM PDT 24 540712804 ps
T95 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1299280968 Aug 12 05:49:22 PM PDT 24 Aug 12 05:49:54 PM PDT 24 796555822 ps
T110 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.622347073 Aug 12 05:49:37 PM PDT 24 Aug 12 05:50:48 PM PDT 24 1067191713 ps
T380 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2902014677 Aug 12 05:49:30 PM PDT 24 Aug 12 05:49:52 PM PDT 24 538165609 ps
T381 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3466260175 Aug 12 05:49:28 PM PDT 24 Aug 12 05:49:34 PM PDT 24 135089169 ps
T382 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1173846004 Aug 12 05:49:19 PM PDT 24 Aug 12 05:49:51 PM PDT 24 788922114 ps
T383 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1699735436 Aug 12 05:49:15 PM PDT 24 Aug 12 05:49:20 PM PDT 24 89395034 ps
T384 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3521915508 Aug 12 05:49:16 PM PDT 24 Aug 12 05:49:21 PM PDT 24 127331077 ps
T385 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1116181266 Aug 12 05:49:12 PM PDT 24 Aug 12 05:49:18 PM PDT 24 382544620 ps
T386 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3192278782 Aug 12 05:49:05 PM PDT 24 Aug 12 05:49:09 PM PDT 24 272749598 ps
T387 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2929536136 Aug 12 05:49:11 PM PDT 24 Aug 12 05:49:15 PM PDT 24 347454904 ps
T96 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4269284629 Aug 12 05:49:19 PM PDT 24 Aug 12 05:49:23 PM PDT 24 103572085 ps
T388 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3898836145 Aug 12 05:49:23 PM PDT 24 Aug 12 05:49:30 PM PDT 24 273569957 ps
T389 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2551401158 Aug 12 05:49:32 PM PDT 24 Aug 12 05:49:37 PM PDT 24 531592002 ps
T97 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1348094500 Aug 12 05:49:14 PM PDT 24 Aug 12 05:49:42 PM PDT 24 5388952316 ps
T111 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1448013162 Aug 12 05:49:32 PM PDT 24 Aug 12 05:50:41 PM PDT 24 860227414 ps
T390 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.55049517 Aug 12 05:49:20 PM PDT 24 Aug 12 05:49:28 PM PDT 24 172534367 ps
T91 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3951237296 Aug 12 05:49:13 PM PDT 24 Aug 12 05:49:18 PM PDT 24 919232749 ps
T391 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3082829667 Aug 12 05:48:58 PM PDT 24 Aug 12 05:49:03 PM PDT 24 125743881 ps
T392 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4027921579 Aug 12 05:49:13 PM PDT 24 Aug 12 05:49:18 PM PDT 24 519860104 ps
T393 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.666299262 Aug 12 05:49:22 PM PDT 24 Aug 12 05:49:29 PM PDT 24 266214669 ps
T394 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3912854898 Aug 12 05:49:14 PM PDT 24 Aug 12 05:49:20 PM PDT 24 426970533 ps
T92 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1405634632 Aug 12 05:49:12 PM PDT 24 Aug 12 05:49:20 PM PDT 24 709062507 ps
T395 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.526944087 Aug 12 05:49:14 PM PDT 24 Aug 12 05:49:24 PM PDT 24 306114710 ps
T396 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2256768792 Aug 12 05:49:20 PM PDT 24 Aug 12 05:49:25 PM PDT 24 133138526 ps
T108 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1788838979 Aug 12 05:49:01 PM PDT 24 Aug 12 05:50:11 PM PDT 24 727644384 ps
T397 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3736275097 Aug 12 05:49:20 PM PDT 24 Aug 12 05:49:25 PM PDT 24 249773077 ps
T398 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3238586453 Aug 12 05:49:15 PM PDT 24 Aug 12 05:49:22 PM PDT 24 333556122 ps
T399 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2501638594 Aug 12 05:49:20 PM PDT 24 Aug 12 05:49:26 PM PDT 24 100577703 ps
T400 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3477769381 Aug 12 05:49:23 PM PDT 24 Aug 12 05:49:29 PM PDT 24 98084378 ps
T401 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.647026361 Aug 12 05:49:40 PM PDT 24 Aug 12 05:49:49 PM PDT 24 130605009 ps
T402 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.832527838 Aug 12 05:49:32 PM PDT 24 Aug 12 05:49:38 PM PDT 24 145985606 ps
T403 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.88723889 Aug 12 05:49:28 PM PDT 24 Aug 12 05:49:38 PM PDT 24 9840671381 ps
T404 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.174953660 Aug 12 05:49:23 PM PDT 24 Aug 12 05:50:01 PM PDT 24 204635010 ps
T405 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2121440369 Aug 12 05:48:59 PM PDT 24 Aug 12 05:49:05 PM PDT 24 525936897 ps
T406 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.704542807 Aug 12 05:49:22 PM PDT 24 Aug 12 05:50:01 PM PDT 24 281953947 ps
T407 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.809255448 Aug 12 05:49:26 PM PDT 24 Aug 12 05:50:14 PM PDT 24 19894102787 ps
T408 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2452021404 Aug 12 05:49:28 PM PDT 24 Aug 12 05:49:32 PM PDT 24 89772942 ps
T409 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2813671901 Aug 12 05:49:15 PM PDT 24 Aug 12 05:49:23 PM PDT 24 255230476 ps
T410 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1239671892 Aug 12 05:49:30 PM PDT 24 Aug 12 05:50:39 PM PDT 24 494978254 ps
T93 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1137879709 Aug 12 05:48:58 PM PDT 24 Aug 12 05:49:26 PM PDT 24 2319430638 ps
T411 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2093840497 Aug 12 05:49:11 PM PDT 24 Aug 12 05:49:17 PM PDT 24 502225563 ps
T412 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3940850566 Aug 12 05:49:01 PM PDT 24 Aug 12 05:49:05 PM PDT 24 161892727 ps

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3164524235
Short name T9
Test name
Test status
Simulation time 5043869976 ps
CPU time 78.45 seconds
Started Aug 12 05:07:35 PM PDT 24
Finished Aug 12 05:08:54 PM PDT 24
Peak memory 228168 kb
Host smart-7d09253e-9a93-4bd4-911d-51de576f5344
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164524235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3164524235
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3834909522
Short name T14
Test name
Test status
Simulation time 2850326917 ps
CPU time 117.96 seconds
Started Aug 12 05:07:44 PM PDT 24
Finished Aug 12 05:09:42 PM PDT 24
Peak memory 221568 kb
Host smart-3dafca4c-5187-4fca-82e6-6389655e4a99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834909522 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3834909522
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3245018895
Short name T11
Test name
Test status
Simulation time 213060842 ps
CPU time 12.3 seconds
Started Aug 12 05:07:36 PM PDT 24
Finished Aug 12 05:07:49 PM PDT 24
Peak memory 213960 kb
Host smart-4ed47130-8aec-463a-b63b-cc09dc9a0fa7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245018895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3245018895
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.428907327
Short name T113
Test name
Test status
Simulation time 277365430 ps
CPU time 6.65 seconds
Started Aug 12 05:07:13 PM PDT 24
Finished Aug 12 05:07:20 PM PDT 24
Peak memory 211408 kb
Host smart-e79ba1ee-cc58-4cec-a17f-1cfd9a495354
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=428907327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.428907327
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3430511795
Short name T29
Test name
Test status
Simulation time 277872734 ps
CPU time 54.22 seconds
Started Aug 12 05:07:21 PM PDT 24
Finished Aug 12 05:08:15 PM PDT 24
Peak memory 235844 kb
Host smart-8c552f09-863a-452e-92bc-d3d77492c1d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430511795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3430511795
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.679509972
Short name T2
Test name
Test status
Simulation time 830775729 ps
CPU time 5.09 seconds
Started Aug 12 05:08:09 PM PDT 24
Finished Aug 12 05:08:15 PM PDT 24
Peak memory 211556 kb
Host smart-3fc5d501-5cd5-4469-9cac-3e4c0e8d9d0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679509972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.679509972
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2170771803
Short name T45
Test name
Test status
Simulation time 31745967319 ps
CPU time 299.87 seconds
Started Aug 12 05:07:46 PM PDT 24
Finished Aug 12 05:12:46 PM PDT 24
Peak memory 234488 kb
Host smart-6c05b8ba-ee67-4b23-9b2b-b94f0517404f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170771803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2170771803
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2387762570
Short name T52
Test name
Test status
Simulation time 600583033 ps
CPU time 70.11 seconds
Started Aug 12 05:49:29 PM PDT 24
Finished Aug 12 05:50:39 PM PDT 24
Peak memory 219116 kb
Host smart-063ca098-8099-4f4f-99a0-f171df4014ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387762570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2387762570
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.59214992
Short name T19
Test name
Test status
Simulation time 4172761245 ps
CPU time 12.65 seconds
Started Aug 12 05:08:01 PM PDT 24
Finished Aug 12 05:08:14 PM PDT 24
Peak memory 214360 kb
Host smart-cd19cb49-33c8-4ab8-b34d-0f9527aa9400
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59214992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 34.rom_ctrl_stress_all.59214992
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.859598845
Short name T7
Test name
Test status
Simulation time 292503945 ps
CPU time 6.78 seconds
Started Aug 12 05:07:47 PM PDT 24
Finished Aug 12 05:07:54 PM PDT 24
Peak memory 211444 kb
Host smart-22e68ef3-07dc-477d-a558-aceb0dcfa31e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=859598845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.859598845
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3761415317
Short name T75
Test name
Test status
Simulation time 488355507 ps
CPU time 18.87 seconds
Started Aug 12 05:49:21 PM PDT 24
Finished Aug 12 05:49:40 PM PDT 24
Peak memory 211132 kb
Host smart-d9b26ca1-82a3-4338-8d55-980798159c95
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761415317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3761415317
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1449061009
Short name T124
Test name
Test status
Simulation time 3827881972 ps
CPU time 12.02 seconds
Started Aug 12 05:07:48 PM PDT 24
Finished Aug 12 05:08:00 PM PDT 24
Peak memory 213108 kb
Host smart-c7b61ce3-0f87-4888-8a0a-49a97953bc76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449061009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1449061009
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.519594043
Short name T103
Test name
Test status
Simulation time 1264580125 ps
CPU time 68.62 seconds
Started Aug 12 05:49:20 PM PDT 24
Finished Aug 12 05:50:28 PM PDT 24
Peak memory 211864 kb
Host smart-2a0826e5-421c-4c86-9422-1b9a0bac4e3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519594043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.519594043
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3029689230
Short name T139
Test name
Test status
Simulation time 1043212362 ps
CPU time 11.26 seconds
Started Aug 12 05:07:54 PM PDT 24
Finished Aug 12 05:08:05 PM PDT 24
Peak memory 212280 kb
Host smart-0fbbaa8e-7625-41e2-ac5c-84d1e97821bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029689230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3029689230
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2961521140
Short name T159
Test name
Test status
Simulation time 175605736 ps
CPU time 9.62 seconds
Started Aug 12 05:07:20 PM PDT 24
Finished Aug 12 05:07:29 PM PDT 24
Peak memory 212248 kb
Host smart-ebee9e43-0a15-4eab-9a47-de51460be8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961521140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2961521140
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1766585425
Short name T84
Test name
Test status
Simulation time 2371700698 ps
CPU time 22 seconds
Started Aug 12 05:49:30 PM PDT 24
Finished Aug 12 05:49:53 PM PDT 24
Peak memory 211088 kb
Host smart-0ae4052c-2836-4c52-9459-407c102ee004
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766585425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1766585425
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3024515680
Short name T72
Test name
Test status
Simulation time 1120027344 ps
CPU time 27.77 seconds
Started Aug 12 05:49:04 PM PDT 24
Finished Aug 12 05:49:31 PM PDT 24
Peak memory 211100 kb
Host smart-e7e68685-f8e8-4934-9cc4-e80b0892bc08
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024515680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3024515680
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1788838979
Short name T108
Test name
Test status
Simulation time 727644384 ps
CPU time 69.43 seconds
Started Aug 12 05:49:01 PM PDT 24
Finished Aug 12 05:50:11 PM PDT 24
Peak memory 212944 kb
Host smart-2e82015f-3123-487f-9929-728e60d8763e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788838979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1788838979
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3270570065
Short name T109
Test name
Test status
Simulation time 1363765387 ps
CPU time 68.63 seconds
Started Aug 12 05:49:19 PM PDT 24
Finished Aug 12 05:50:28 PM PDT 24
Peak memory 211784 kb
Host smart-4457cc70-5933-42f1-a1f8-3843d784fc25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270570065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3270570065
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.182337233
Short name T15
Test name
Test status
Simulation time 9238073868 ps
CPU time 153.36 seconds
Started Aug 12 05:07:25 PM PDT 24
Finished Aug 12 05:09:58 PM PDT 24
Peak memory 231960 kb
Host smart-93ac1473-1b3a-422a-a7e5-b9ddbda2071c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182337233 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.182337233
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3754332204
Short name T35
Test name
Test status
Simulation time 517989561 ps
CPU time 5.22 seconds
Started Aug 12 05:07:45 PM PDT 24
Finished Aug 12 05:07:50 PM PDT 24
Peak memory 211484 kb
Host smart-27b7b9fa-df29-4876-abd0-152b22f7e7b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754332204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3754332204
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1134381341
Short name T117
Test name
Test status
Simulation time 644975422 ps
CPU time 8.95 seconds
Started Aug 12 05:07:42 PM PDT 24
Finished Aug 12 05:07:51 PM PDT 24
Peak memory 211536 kb
Host smart-489f677c-71d2-4b47-8d66-22883c9ba69d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134381341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1134381341
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.582727881
Short name T337
Test name
Test status
Simulation time 127746689 ps
CPU time 5.32 seconds
Started Aug 12 05:49:00 PM PDT 24
Finished Aug 12 05:49:05 PM PDT 24
Peak memory 217892 kb
Host smart-1bcc3fa9-fe4f-49cb-a975-07b98fbf0afc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582727881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.582727881
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3984094910
Short name T320
Test name
Test status
Simulation time 175819943 ps
CPU time 4.43 seconds
Started Aug 12 05:48:59 PM PDT 24
Finished Aug 12 05:49:04 PM PDT 24
Peak memory 219172 kb
Host smart-b159d0c7-9046-499e-a9cf-87679f47d227
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984094910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3984094910
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4066673672
Short name T319
Test name
Test status
Simulation time 133735645 ps
CPU time 8.33 seconds
Started Aug 12 05:48:59 PM PDT 24
Finished Aug 12 05:49:07 PM PDT 24
Peak memory 211024 kb
Host smart-74434ddd-f6fa-406b-82f2-4250bd1b6aef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066673672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.4066673672
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2056084784
Short name T352
Test name
Test status
Simulation time 143635833 ps
CPU time 6.27 seconds
Started Aug 12 05:49:00 PM PDT 24
Finished Aug 12 05:49:06 PM PDT 24
Peak memory 219216 kb
Host smart-be8ea7a0-561a-4ec4-924d-0f1c3d71baad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056084784 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2056084784
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3082829667
Short name T391
Test name
Test status
Simulation time 125743881 ps
CPU time 5.01 seconds
Started Aug 12 05:48:58 PM PDT 24
Finished Aug 12 05:49:03 PM PDT 24
Peak memory 211036 kb
Host smart-56a95bf7-ccfd-4d60-9724-537c9fd52ffa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082829667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3082829667
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.855994063
Short name T330
Test name
Test status
Simulation time 146284566 ps
CPU time 5.12 seconds
Started Aug 12 05:48:57 PM PDT 24
Finished Aug 12 05:49:02 PM PDT 24
Peak memory 210852 kb
Host smart-28aff2d1-66d5-4f80-b6da-2c22004269f1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855994063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.855994063
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4033159987
Short name T318
Test name
Test status
Simulation time 320157377 ps
CPU time 4.14 seconds
Started Aug 12 05:48:59 PM PDT 24
Finished Aug 12 05:49:03 PM PDT 24
Peak memory 210896 kb
Host smart-42fae92b-f31d-4425-923b-027cf1195c9c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033159987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.4033159987
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3940850566
Short name T412
Test name
Test status
Simulation time 161892727 ps
CPU time 4.46 seconds
Started Aug 12 05:49:01 PM PDT 24
Finished Aug 12 05:49:05 PM PDT 24
Peak memory 211044 kb
Host smart-84b63b43-7c69-41f4-a885-402774f4761f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940850566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3940850566
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2159713862
Short name T374
Test name
Test status
Simulation time 250382829 ps
CPU time 9.13 seconds
Started Aug 12 05:49:01 PM PDT 24
Finished Aug 12 05:49:10 PM PDT 24
Peak memory 216360 kb
Host smart-e7e37bf1-ad71-49d4-97dc-16f3798eb870
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159713862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2159713862
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.850971361
Short name T49
Test name
Test status
Simulation time 230884572 ps
CPU time 37.66 seconds
Started Aug 12 05:48:56 PM PDT 24
Finished Aug 12 05:49:33 PM PDT 24
Peak memory 211252 kb
Host smart-bf3cb6a1-0ff4-4e76-8b5e-7454b248c560
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850971361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.850971361
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4246639614
Short name T79
Test name
Test status
Simulation time 133539711 ps
CPU time 5.33 seconds
Started Aug 12 05:49:08 PM PDT 24
Finished Aug 12 05:49:14 PM PDT 24
Peak memory 211028 kb
Host smart-ee0ae3e9-1335-4653-9049-b68fb7e590a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246639614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.4246639614
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.170732408
Short name T361
Test name
Test status
Simulation time 175509705 ps
CPU time 4.91 seconds
Started Aug 12 05:48:59 PM PDT 24
Finished Aug 12 05:49:04 PM PDT 24
Peak memory 211036 kb
Host smart-ca0c1796-ccae-4267-86f5-090276b5bb95
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170732408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.170732408
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1301633226
Short name T74
Test name
Test status
Simulation time 133937180 ps
CPU time 6.57 seconds
Started Aug 12 05:49:00 PM PDT 24
Finished Aug 12 05:49:07 PM PDT 24
Peak memory 218624 kb
Host smart-664359ce-e84b-484d-bb23-e3662978cfe2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301633226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1301633226
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3840377877
Short name T373
Test name
Test status
Simulation time 135061873 ps
CPU time 5.61 seconds
Started Aug 12 05:49:04 PM PDT 24
Finished Aug 12 05:49:10 PM PDT 24
Peak memory 219144 kb
Host smart-9628efe7-4354-47aa-b44c-f2687bfca699
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840377877 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3840377877
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.105451863
Short name T356
Test name
Test status
Simulation time 501791757 ps
CPU time 5.08 seconds
Started Aug 12 05:48:58 PM PDT 24
Finished Aug 12 05:49:03 PM PDT 24
Peak memory 210980 kb
Host smart-3ba73ec1-484d-4897-a63a-5ded1e47a386
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105451863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.105451863
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2121440369
Short name T405
Test name
Test status
Simulation time 525936897 ps
CPU time 5.19 seconds
Started Aug 12 05:48:59 PM PDT 24
Finished Aug 12 05:49:05 PM PDT 24
Peak memory 210828 kb
Host smart-cd8f8408-47b6-4ba6-a64e-03ee88ac70d1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121440369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2121440369
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3955800364
Short name T366
Test name
Test status
Simulation time 495586786 ps
CPU time 5.07 seconds
Started Aug 12 05:48:56 PM PDT 24
Finished Aug 12 05:49:01 PM PDT 24
Peak memory 210856 kb
Host smart-8805c429-93a7-4d8e-a6b3-b6c5a7dcbd83
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955800364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3955800364
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1137879709
Short name T93
Test name
Test status
Simulation time 2319430638 ps
CPU time 28.03 seconds
Started Aug 12 05:48:58 PM PDT 24
Finished Aug 12 05:49:26 PM PDT 24
Peak memory 211112 kb
Host smart-accb73e5-9df2-45c6-9924-2b595062ef26
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137879709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1137879709
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1258306651
Short name T349
Test name
Test status
Simulation time 87144215 ps
CPU time 4.41 seconds
Started Aug 12 05:49:05 PM PDT 24
Finished Aug 12 05:49:10 PM PDT 24
Peak memory 219164 kb
Host smart-a6deb297-2fc4-4844-b387-8ff55f1fa088
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258306651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1258306651
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4022839073
Short name T322
Test name
Test status
Simulation time 522540140 ps
CPU time 9.27 seconds
Started Aug 12 05:48:59 PM PDT 24
Finished Aug 12 05:49:09 PM PDT 24
Peak memory 216272 kb
Host smart-bb05f963-7c95-44ad-9c0a-38184f39395d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022839073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.4022839073
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2483965233
Short name T350
Test name
Test status
Simulation time 1126161532 ps
CPU time 5.67 seconds
Started Aug 12 05:49:25 PM PDT 24
Finished Aug 12 05:49:31 PM PDT 24
Peak memory 219200 kb
Host smart-c260514c-50c7-4462-a2c9-08384c6a4614
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483965233 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2483965233
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3625231954
Short name T358
Test name
Test status
Simulation time 2502742337 ps
CPU time 5.25 seconds
Started Aug 12 05:49:20 PM PDT 24
Finished Aug 12 05:49:25 PM PDT 24
Peak memory 218360 kb
Host smart-1956206b-f4b0-4e9c-ad20-707917899a40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625231954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3625231954
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1904928223
Short name T335
Test name
Test status
Simulation time 544060787 ps
CPU time 22.07 seconds
Started Aug 12 05:49:20 PM PDT 24
Finished Aug 12 05:49:42 PM PDT 24
Peak memory 210992 kb
Host smart-9108614c-70a7-433a-9ec4-b28dfa2ce680
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904928223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1904928223
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3169458897
Short name T62
Test name
Test status
Simulation time 350965530 ps
CPU time 4.25 seconds
Started Aug 12 05:49:20 PM PDT 24
Finished Aug 12 05:49:25 PM PDT 24
Peak memory 211056 kb
Host smart-1369c334-8a47-4be5-a235-c7e5facc101a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169458897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3169458897
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.88723889
Short name T403
Test name
Test status
Simulation time 9840671381 ps
CPU time 9.9 seconds
Started Aug 12 05:49:28 PM PDT 24
Finished Aug 12 05:49:38 PM PDT 24
Peak memory 216480 kb
Host smart-6490d77d-3854-4f50-8efd-6e6be2b7a276
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88723889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.88723889
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.704542807
Short name T406
Test name
Test status
Simulation time 281953947 ps
CPU time 39.51 seconds
Started Aug 12 05:49:22 PM PDT 24
Finished Aug 12 05:50:01 PM PDT 24
Peak memory 211412 kb
Host smart-c41d2842-63a9-49a1-b9d0-c66ba892724b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704542807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.704542807
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2576052918
Short name T342
Test name
Test status
Simulation time 364056746 ps
CPU time 4.57 seconds
Started Aug 12 05:49:27 PM PDT 24
Finished Aug 12 05:49:32 PM PDT 24
Peak memory 214356 kb
Host smart-0f3cf380-0912-4bef-80d3-a46afd4f1ab5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576052918 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2576052918
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2256768792
Short name T396
Test name
Test status
Simulation time 133138526 ps
CPU time 5.53 seconds
Started Aug 12 05:49:20 PM PDT 24
Finished Aug 12 05:49:25 PM PDT 24
Peak memory 211020 kb
Host smart-080c6c9d-a251-45f9-b6ec-13f696d137e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256768792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2256768792
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1180691378
Short name T333
Test name
Test status
Simulation time 1073792675 ps
CPU time 21.56 seconds
Started Aug 12 05:49:23 PM PDT 24
Finished Aug 12 05:49:45 PM PDT 24
Peak memory 211064 kb
Host smart-cc7e4f9b-f0ae-4aa0-843f-4bfb6a0d15cd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180691378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1180691378
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4146768817
Short name T364
Test name
Test status
Simulation time 89159210 ps
CPU time 4.34 seconds
Started Aug 12 05:49:21 PM PDT 24
Finished Aug 12 05:49:25 PM PDT 24
Peak memory 210992 kb
Host smart-6fed73f1-e97d-4aef-8379-0ab408ae7fc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146768817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.4146768817
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3176881451
Short name T355
Test name
Test status
Simulation time 497732476 ps
CPU time 8.85 seconds
Started Aug 12 05:49:25 PM PDT 24
Finished Aug 12 05:49:34 PM PDT 24
Peak memory 219152 kb
Host smart-ba2f0f50-69cf-4454-87a2-38ff7b43b193
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176881451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3176881451
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2551401158
Short name T389
Test name
Test status
Simulation time 531592002 ps
CPU time 5.35 seconds
Started Aug 12 05:49:32 PM PDT 24
Finished Aug 12 05:49:37 PM PDT 24
Peak memory 219188 kb
Host smart-1978b773-f832-4e1e-adfd-f3645688bb54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551401158 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2551401158
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3112130239
Short name T362
Test name
Test status
Simulation time 126910566 ps
CPU time 4.97 seconds
Started Aug 12 05:49:28 PM PDT 24
Finished Aug 12 05:49:33 PM PDT 24
Peak memory 210920 kb
Host smart-873fd320-a809-4731-9ee3-03892c3e0b33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112130239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3112130239
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3145665757
Short name T372
Test name
Test status
Simulation time 3477391083 ps
CPU time 22.11 seconds
Started Aug 12 05:49:27 PM PDT 24
Finished Aug 12 05:49:50 PM PDT 24
Peak memory 211124 kb
Host smart-d7954070-5c2e-474d-991d-6faec4a7fb4b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145665757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3145665757
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2863419264
Short name T343
Test name
Test status
Simulation time 2469618792 ps
CPU time 5.36 seconds
Started Aug 12 05:49:25 PM PDT 24
Finished Aug 12 05:49:30 PM PDT 24
Peak memory 211028 kb
Host smart-50aa5ff4-837a-46b8-8527-4aed02604a88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863419264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2863419264
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3907501489
Short name T321
Test name
Test status
Simulation time 886871170 ps
CPU time 7.25 seconds
Started Aug 12 05:49:24 PM PDT 24
Finished Aug 12 05:49:31 PM PDT 24
Peak memory 219220 kb
Host smart-f64892b8-12a3-4852-836b-b010f983d8b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907501489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3907501489
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3414702476
Short name T347
Test name
Test status
Simulation time 573958399 ps
CPU time 5.88 seconds
Started Aug 12 05:49:28 PM PDT 24
Finished Aug 12 05:49:34 PM PDT 24
Peak memory 215644 kb
Host smart-6f426abe-fd62-4be8-8a0c-6247895c4b5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414702476 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3414702476
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3506815134
Short name T331
Test name
Test status
Simulation time 86679598 ps
CPU time 4.35 seconds
Started Aug 12 05:49:28 PM PDT 24
Finished Aug 12 05:49:33 PM PDT 24
Peak memory 210944 kb
Host smart-9ae26f0a-c9a4-4784-a573-eab6d0e4e77e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506815134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3506815134
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3466260175
Short name T381
Test name
Test status
Simulation time 135089169 ps
CPU time 5.16 seconds
Started Aug 12 05:49:28 PM PDT 24
Finished Aug 12 05:49:34 PM PDT 24
Peak memory 218308 kb
Host smart-2cec6db4-a990-478f-b860-1995444be211
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466260175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3466260175
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2349907019
Short name T69
Test name
Test status
Simulation time 132854287 ps
CPU time 8.8 seconds
Started Aug 12 05:49:28 PM PDT 24
Finished Aug 12 05:49:37 PM PDT 24
Peak memory 219220 kb
Host smart-78472614-18f4-43b5-ae4b-7061396badd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349907019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2349907019
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1343028094
Short name T378
Test name
Test status
Simulation time 220864018 ps
CPU time 5.46 seconds
Started Aug 12 05:49:28 PM PDT 24
Finished Aug 12 05:49:34 PM PDT 24
Peak memory 219140 kb
Host smart-b4d1aeb6-5c28-43ca-bfd6-86b78da7e738
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343028094 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1343028094
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1426281894
Short name T76
Test name
Test status
Simulation time 499541068 ps
CPU time 5.11 seconds
Started Aug 12 05:49:31 PM PDT 24
Finished Aug 12 05:49:36 PM PDT 24
Peak memory 217888 kb
Host smart-5cc0b482-7bdc-4ed0-8eba-5f6cd4364c01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426281894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1426281894
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2902014677
Short name T380
Test name
Test status
Simulation time 538165609 ps
CPU time 22.08 seconds
Started Aug 12 05:49:30 PM PDT 24
Finished Aug 12 05:49:52 PM PDT 24
Peak memory 211084 kb
Host smart-911fd31d-baaa-4fd7-a611-01d480a7b9fd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902014677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2902014677
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2659556684
Short name T375
Test name
Test status
Simulation time 622887095 ps
CPU time 6 seconds
Started Aug 12 05:49:30 PM PDT 24
Finished Aug 12 05:49:36 PM PDT 24
Peak memory 211460 kb
Host smart-b366a004-0f2a-4c8d-acbc-86a8c41a9019
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659556684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2659556684
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2566669597
Short name T327
Test name
Test status
Simulation time 289036999 ps
CPU time 10.16 seconds
Started Aug 12 05:49:29 PM PDT 24
Finished Aug 12 05:49:39 PM PDT 24
Peak memory 219232 kb
Host smart-f7555af8-2166-498c-b85a-3d10e330efd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566669597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2566669597
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1448013162
Short name T111
Test name
Test status
Simulation time 860227414 ps
CPU time 68.36 seconds
Started Aug 12 05:49:32 PM PDT 24
Finished Aug 12 05:50:41 PM PDT 24
Peak memory 212864 kb
Host smart-27c55769-0a52-41ac-bc4a-2d0b6617f9ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448013162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1448013162
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.832527838
Short name T402
Test name
Test status
Simulation time 145985606 ps
CPU time 5.77 seconds
Started Aug 12 05:49:32 PM PDT 24
Finished Aug 12 05:49:38 PM PDT 24
Peak memory 219264 kb
Host smart-0cf94eb1-1624-47ab-8dd9-23607103e30d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832527838 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.832527838
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1798069905
Short name T88
Test name
Test status
Simulation time 126017386 ps
CPU time 5.11 seconds
Started Aug 12 05:49:27 PM PDT 24
Finished Aug 12 05:49:32 PM PDT 24
Peak memory 211056 kb
Host smart-d9ed1072-cf30-46d0-a01d-33dbc2c5846c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798069905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1798069905
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2467136406
Short name T77
Test name
Test status
Simulation time 828247032 ps
CPU time 33.41 seconds
Started Aug 12 05:49:33 PM PDT 24
Finished Aug 12 05:50:07 PM PDT 24
Peak memory 211100 kb
Host smart-4dc55213-e9a3-47b8-840f-6bb1f252decb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467136406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2467136406
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3779570104
Short name T98
Test name
Test status
Simulation time 347003721 ps
CPU time 6.18 seconds
Started Aug 12 05:49:27 PM PDT 24
Finished Aug 12 05:49:34 PM PDT 24
Peak memory 219172 kb
Host smart-4566c2df-8000-4fd2-97db-6c10ddcda4bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779570104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3779570104
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2528546301
Short name T368
Test name
Test status
Simulation time 247090364 ps
CPU time 9.44 seconds
Started Aug 12 05:49:27 PM PDT 24
Finished Aug 12 05:49:37 PM PDT 24
Peak memory 215988 kb
Host smart-53653e2d-6667-4ba5-8885-65541a26f513
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528546301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2528546301
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3573564725
Short name T48
Test name
Test status
Simulation time 464196401 ps
CPU time 39.12 seconds
Started Aug 12 05:49:30 PM PDT 24
Finished Aug 12 05:50:09 PM PDT 24
Peak memory 213648 kb
Host smart-54836f80-92b4-4a87-8026-b623d34faa80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573564725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3573564725
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.280396587
Short name T328
Test name
Test status
Simulation time 149275045 ps
CPU time 5.95 seconds
Started Aug 12 05:49:29 PM PDT 24
Finished Aug 12 05:49:35 PM PDT 24
Peak memory 215624 kb
Host smart-8b5b9f4f-b51d-4943-804f-ef74d9b4b4d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280396587 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.280396587
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2452021404
Short name T408
Test name
Test status
Simulation time 89772942 ps
CPU time 4.15 seconds
Started Aug 12 05:49:28 PM PDT 24
Finished Aug 12 05:49:32 PM PDT 24
Peak memory 210940 kb
Host smart-bafc7278-6629-4117-b8a7-bb9ec5efd5dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452021404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2452021404
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.809255448
Short name T407
Test name
Test status
Simulation time 19894102787 ps
CPU time 48.17 seconds
Started Aug 12 05:49:26 PM PDT 24
Finished Aug 12 05:50:14 PM PDT 24
Peak memory 211076 kb
Host smart-9f9abaad-d463-4f0b-8fa8-d0261f8e40a3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809255448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.809255448
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3583413446
Short name T100
Test name
Test status
Simulation time 126376980 ps
CPU time 5.22 seconds
Started Aug 12 05:49:29 PM PDT 24
Finished Aug 12 05:49:34 PM PDT 24
Peak memory 211036 kb
Host smart-cdc8d4ac-b6d1-4b3f-99b4-c5874d2aed1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583413446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3583413446
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3964305679
Short name T329
Test name
Test status
Simulation time 648296203 ps
CPU time 10.1 seconds
Started Aug 12 05:49:31 PM PDT 24
Finished Aug 12 05:49:41 PM PDT 24
Peak memory 216252 kb
Host smart-e8b74e0c-7f7d-45f2-b44d-1ff648861e84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964305679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3964305679
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1239671892
Short name T410
Test name
Test status
Simulation time 494978254 ps
CPU time 69.33 seconds
Started Aug 12 05:49:30 PM PDT 24
Finished Aug 12 05:50:39 PM PDT 24
Peak memory 212580 kb
Host smart-e5742bc4-4957-45b6-92f5-8d312c12cd6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239671892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1239671892
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3442037503
Short name T50
Test name
Test status
Simulation time 272111241 ps
CPU time 5.96 seconds
Started Aug 12 05:49:40 PM PDT 24
Finished Aug 12 05:49:46 PM PDT 24
Peak memory 215904 kb
Host smart-196b05b7-aa02-41cc-a9fe-20fd3444792a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442037503 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3442037503
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.808796423
Short name T323
Test name
Test status
Simulation time 249092361 ps
CPU time 5.24 seconds
Started Aug 12 05:49:38 PM PDT 24
Finished Aug 12 05:49:44 PM PDT 24
Peak memory 211024 kb
Host smart-dd8003b7-9592-4389-971d-dc0f1656e9a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808796423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.808796423
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3349635534
Short name T336
Test name
Test status
Simulation time 1603405631 ps
CPU time 33.43 seconds
Started Aug 12 05:49:42 PM PDT 24
Finished Aug 12 05:50:16 PM PDT 24
Peak memory 211060 kb
Host smart-aab63718-8baf-44e0-a682-4ccb7ab26ae0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349635534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3349635534
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1295930431
Short name T340
Test name
Test status
Simulation time 172450954 ps
CPU time 5.29 seconds
Started Aug 12 05:49:39 PM PDT 24
Finished Aug 12 05:49:45 PM PDT 24
Peak memory 210968 kb
Host smart-647752e2-b98f-4a9f-a1a6-ccba26f71cc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295930431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1295930431
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3598366153
Short name T332
Test name
Test status
Simulation time 2232331092 ps
CPU time 9.13 seconds
Started Aug 12 05:49:38 PM PDT 24
Finished Aug 12 05:49:47 PM PDT 24
Peak memory 216012 kb
Host smart-550d0ea1-2f30-4981-b32c-56065c54385a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598366153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3598366153
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.622347073
Short name T110
Test name
Test status
Simulation time 1067191713 ps
CPU time 70.18 seconds
Started Aug 12 05:49:37 PM PDT 24
Finished Aug 12 05:50:48 PM PDT 24
Peak memory 219220 kb
Host smart-42cb6a14-68e4-476c-923d-024af51ca945
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622347073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.622347073
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3156123988
Short name T377
Test name
Test status
Simulation time 399416350 ps
CPU time 4.55 seconds
Started Aug 12 05:49:39 PM PDT 24
Finished Aug 12 05:49:44 PM PDT 24
Peak memory 213268 kb
Host smart-cae9c185-4c22-4682-b704-bc51b8090c03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156123988 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3156123988
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.521781719
Short name T63
Test name
Test status
Simulation time 287252401 ps
CPU time 4.96 seconds
Started Aug 12 05:49:42 PM PDT 24
Finished Aug 12 05:49:47 PM PDT 24
Peak memory 211020 kb
Host smart-6d26a8d0-4348-42ba-94f3-5bae69ec2aa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521781719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.521781719
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2611573980
Short name T78
Test name
Test status
Simulation time 4135824767 ps
CPU time 27.54 seconds
Started Aug 12 05:49:36 PM PDT 24
Finished Aug 12 05:50:04 PM PDT 24
Peak memory 211008 kb
Host smart-c1ae3b2d-b12e-4031-8936-32bfe22eccd1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611573980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2611573980
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3627396565
Short name T101
Test name
Test status
Simulation time 104027889 ps
CPU time 6.11 seconds
Started Aug 12 05:49:42 PM PDT 24
Finished Aug 12 05:49:48 PM PDT 24
Peak memory 211188 kb
Host smart-fb901e4c-c21a-4ec0-ab4f-3778e88790c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627396565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3627396565
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2161233067
Short name T71
Test name
Test status
Simulation time 134406694 ps
CPU time 9.52 seconds
Started Aug 12 05:49:38 PM PDT 24
Finished Aug 12 05:49:48 PM PDT 24
Peak memory 216184 kb
Host smart-77605067-ab06-43bf-bbba-9c6909b8291b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161233067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2161233067
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2090559882
Short name T104
Test name
Test status
Simulation time 1068238253 ps
CPU time 68.36 seconds
Started Aug 12 05:49:39 PM PDT 24
Finished Aug 12 05:50:48 PM PDT 24
Peak memory 212900 kb
Host smart-53e2b41a-3863-41aa-aef4-dafde33eaf05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090559882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2090559882
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.741613993
Short name T379
Test name
Test status
Simulation time 540712804 ps
CPU time 6.24 seconds
Started Aug 12 05:49:38 PM PDT 24
Finished Aug 12 05:49:44 PM PDT 24
Peak memory 219256 kb
Host smart-174c5a9c-5181-4760-983a-b7375ce2386a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741613993 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.741613993
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2957295517
Short name T89
Test name
Test status
Simulation time 593583692 ps
CPU time 5.06 seconds
Started Aug 12 05:49:37 PM PDT 24
Finished Aug 12 05:49:43 PM PDT 24
Peak memory 211032 kb
Host smart-fa5780b8-c64e-437e-bf0c-0bbb85c7cd5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957295517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2957295517
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.727620647
Short name T371
Test name
Test status
Simulation time 4332733501 ps
CPU time 21.78 seconds
Started Aug 12 05:49:36 PM PDT 24
Finished Aug 12 05:49:58 PM PDT 24
Peak memory 211140 kb
Host smart-1b0ac07f-992a-467e-970f-613c06fac998
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727620647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.727620647
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3977238255
Short name T334
Test name
Test status
Simulation time 754986975 ps
CPU time 4.34 seconds
Started Aug 12 05:49:39 PM PDT 24
Finished Aug 12 05:49:44 PM PDT 24
Peak memory 218648 kb
Host smart-9276482d-6a66-452e-8d51-8d4417acaae3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977238255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3977238255
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.647026361
Short name T401
Test name
Test status
Simulation time 130605009 ps
CPU time 8.57 seconds
Started Aug 12 05:49:40 PM PDT 24
Finished Aug 12 05:49:49 PM PDT 24
Peak memory 219376 kb
Host smart-5532bbbf-ae0d-4245-90fc-418ed8721d26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647026361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.647026361
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1909832976
Short name T107
Test name
Test status
Simulation time 321649489 ps
CPU time 69.77 seconds
Started Aug 12 05:49:35 PM PDT 24
Finished Aug 12 05:50:45 PM PDT 24
Peak memory 219124 kb
Host smart-8fd2a16b-fed6-4c3f-852e-bd89d380abcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909832976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1909832976
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3182873439
Short name T90
Test name
Test status
Simulation time 128638522 ps
CPU time 5.12 seconds
Started Aug 12 05:49:05 PM PDT 24
Finished Aug 12 05:49:10 PM PDT 24
Peak memory 210972 kb
Host smart-802d73e1-98b2-4a8a-8681-e20b738971ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182873439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3182873439
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.806100279
Short name T360
Test name
Test status
Simulation time 129654147 ps
CPU time 5.38 seconds
Started Aug 12 05:49:08 PM PDT 24
Finished Aug 12 05:49:14 PM PDT 24
Peak memory 211060 kb
Host smart-6406a8bd-3760-49a1-93ec-7aafb128e8fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806100279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.806100279
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2162640609
Short name T326
Test name
Test status
Simulation time 266429412 ps
CPU time 8.34 seconds
Started Aug 12 05:49:04 PM PDT 24
Finished Aug 12 05:49:12 PM PDT 24
Peak memory 211032 kb
Host smart-95fcb96c-4a96-4195-afe2-7e05a3dc265c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162640609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2162640609
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3912854898
Short name T394
Test name
Test status
Simulation time 426970533 ps
CPU time 6.09 seconds
Started Aug 12 05:49:14 PM PDT 24
Finished Aug 12 05:49:20 PM PDT 24
Peak memory 216720 kb
Host smart-a75778f6-b120-4d17-a486-8fe11f130be0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912854898 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3912854898
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2302648843
Short name T363
Test name
Test status
Simulation time 499147735 ps
CPU time 5.27 seconds
Started Aug 12 05:49:04 PM PDT 24
Finished Aug 12 05:49:09 PM PDT 24
Peak memory 218284 kb
Host smart-d5b3bee6-b979-484e-ac26-e4a86e4d4012
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302648843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2302648843
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3192278782
Short name T386
Test name
Test status
Simulation time 272749598 ps
CPU time 4.18 seconds
Started Aug 12 05:49:05 PM PDT 24
Finished Aug 12 05:49:09 PM PDT 24
Peak memory 210860 kb
Host smart-ec813b14-c005-4daa-adcb-4aaeafac9e32
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192278782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3192278782
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.225874863
Short name T353
Test name
Test status
Simulation time 153379315 ps
CPU time 5.11 seconds
Started Aug 12 05:49:14 PM PDT 24
Finished Aug 12 05:49:19 PM PDT 24
Peak memory 210928 kb
Host smart-61b506e6-c0fa-4a7d-b291-52a6229d619e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225874863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
225874863
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3383240523
Short name T357
Test name
Test status
Simulation time 789915858 ps
CPU time 33.15 seconds
Started Aug 12 05:49:06 PM PDT 24
Finished Aug 12 05:49:39 PM PDT 24
Peak memory 211064 kb
Host smart-065faafd-c35a-4caa-8f98-1b2a5e96ad0f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383240523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3383240523
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3173273633
Short name T99
Test name
Test status
Simulation time 131799808 ps
CPU time 4.97 seconds
Started Aug 12 05:49:14 PM PDT 24
Finished Aug 12 05:49:19 PM PDT 24
Peak memory 211056 kb
Host smart-8f3e9c86-c74b-4974-9b17-2411b26ecb78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173273633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3173273633
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4253154010
Short name T338
Test name
Test status
Simulation time 129086065 ps
CPU time 7.58 seconds
Started Aug 12 05:49:14 PM PDT 24
Finished Aug 12 05:49:22 PM PDT 24
Peak memory 216176 kb
Host smart-d7ab377c-78f5-4aea-85ac-ddeecc843f0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253154010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.4253154010
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3219734622
Short name T106
Test name
Test status
Simulation time 283733317 ps
CPU time 69.11 seconds
Started Aug 12 05:49:08 PM PDT 24
Finished Aug 12 05:50:17 PM PDT 24
Peak memory 219192 kb
Host smart-377ffdf5-5d18-4a47-ac41-e5e0a7eb5025
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219734622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3219734622
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3951237296
Short name T91
Test name
Test status
Simulation time 919232749 ps
CPU time 4.38 seconds
Started Aug 12 05:49:13 PM PDT 24
Finished Aug 12 05:49:18 PM PDT 24
Peak memory 217740 kb
Host smart-ee3b2275-6bde-4b18-8741-7cd9002a4cbe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951237296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3951237296
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2093840497
Short name T411
Test name
Test status
Simulation time 502225563 ps
CPU time 5.19 seconds
Started Aug 12 05:49:11 PM PDT 24
Finished Aug 12 05:49:17 PM PDT 24
Peak memory 217764 kb
Host smart-90a669b3-d528-4973-b076-6413da25f117
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093840497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2093840497
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4181184777
Short name T80
Test name
Test status
Simulation time 181929141 ps
CPU time 7.23 seconds
Started Aug 12 05:49:11 PM PDT 24
Finished Aug 12 05:49:19 PM PDT 24
Peak memory 211052 kb
Host smart-b11447b6-c00f-4f77-b748-2bca9c8cb853
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181184777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.4181184777
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1116181266
Short name T385
Test name
Test status
Simulation time 382544620 ps
CPU time 5.14 seconds
Started Aug 12 05:49:12 PM PDT 24
Finished Aug 12 05:49:18 PM PDT 24
Peak memory 219216 kb
Host smart-af60f78d-dfc1-4e15-ad88-529261b4363a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116181266 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1116181266
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3521915508
Short name T384
Test name
Test status
Simulation time 127331077 ps
CPU time 5.31 seconds
Started Aug 12 05:49:16 PM PDT 24
Finished Aug 12 05:49:21 PM PDT 24
Peak memory 218060 kb
Host smart-556b8998-5074-4873-bf7b-f18737a53446
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521915508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3521915508
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4027921579
Short name T392
Test name
Test status
Simulation time 519860104 ps
CPU time 4.97 seconds
Started Aug 12 05:49:13 PM PDT 24
Finished Aug 12 05:49:18 PM PDT 24
Peak memory 210832 kb
Host smart-65167128-8642-4d27-8cde-f0e246e73174
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027921579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.4027921579
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2022075920
Short name T317
Test name
Test status
Simulation time 4493800316 ps
CPU time 7.52 seconds
Started Aug 12 05:49:13 PM PDT 24
Finished Aug 12 05:49:21 PM PDT 24
Peak memory 210960 kb
Host smart-20455e52-2992-4306-889c-d43b948dd649
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022075920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2022075920
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3547196899
Short name T87
Test name
Test status
Simulation time 1275297106 ps
CPU time 18.44 seconds
Started Aug 12 05:49:06 PM PDT 24
Finished Aug 12 05:49:24 PM PDT 24
Peak memory 211036 kb
Host smart-177fbd6e-d919-41e5-aae4-df59703384a7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547196899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3547196899
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3411517899
Short name T64
Test name
Test status
Simulation time 461021101 ps
CPU time 4.33 seconds
Started Aug 12 05:49:12 PM PDT 24
Finished Aug 12 05:49:17 PM PDT 24
Peak memory 210964 kb
Host smart-8237ded1-7353-47a2-8b70-74325be74152
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411517899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3411517899
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.526944087
Short name T395
Test name
Test status
Simulation time 306114710 ps
CPU time 10.03 seconds
Started Aug 12 05:49:14 PM PDT 24
Finished Aug 12 05:49:24 PM PDT 24
Peak memory 219264 kb
Host smart-1d662e7f-859d-4e18-bfb3-6630e9e63ecc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526944087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.526944087
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3500741569
Short name T324
Test name
Test status
Simulation time 215468026 ps
CPU time 37.35 seconds
Started Aug 12 05:49:03 PM PDT 24
Finished Aug 12 05:49:41 PM PDT 24
Peak memory 211692 kb
Host smart-ccb9d086-b3c2-459d-878b-6b5a17ef7144
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500741569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3500741569
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3671800953
Short name T85
Test name
Test status
Simulation time 127532055 ps
CPU time 5.06 seconds
Started Aug 12 05:49:13 PM PDT 24
Finished Aug 12 05:49:18 PM PDT 24
Peak memory 210992 kb
Host smart-935620fc-9031-4ed8-8e4a-ce3e3f34f5fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671800953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3671800953
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1068985749
Short name T348
Test name
Test status
Simulation time 323122346 ps
CPU time 5.36 seconds
Started Aug 12 05:49:14 PM PDT 24
Finished Aug 12 05:49:20 PM PDT 24
Peak memory 217976 kb
Host smart-847bc40c-4327-4625-a748-254302ee06e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068985749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1068985749
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1405634632
Short name T92
Test name
Test status
Simulation time 709062507 ps
CPU time 8.23 seconds
Started Aug 12 05:49:12 PM PDT 24
Finished Aug 12 05:49:20 PM PDT 24
Peak memory 219120 kb
Host smart-e7ead5b1-c6f3-4276-83dc-02b6bbb05511
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405634632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1405634632
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2267604297
Short name T70
Test name
Test status
Simulation time 136206610 ps
CPU time 5.62 seconds
Started Aug 12 05:49:17 PM PDT 24
Finished Aug 12 05:49:23 PM PDT 24
Peak memory 214816 kb
Host smart-3a0d9a4a-5c5b-406c-92b0-19db22450cc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267604297 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2267604297
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3055212240
Short name T354
Test name
Test status
Simulation time 89409943 ps
CPU time 4.22 seconds
Started Aug 12 05:49:12 PM PDT 24
Finished Aug 12 05:49:16 PM PDT 24
Peak memory 210980 kb
Host smart-c9333096-7c7b-4bd0-8301-28e1bb2474e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055212240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3055212240
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2929536136
Short name T387
Test name
Test status
Simulation time 347454904 ps
CPU time 4.06 seconds
Started Aug 12 05:49:11 PM PDT 24
Finished Aug 12 05:49:15 PM PDT 24
Peak memory 210852 kb
Host smart-4bda2fd9-a57e-40f8-92b8-e2b2bdc1bb2e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929536136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2929536136
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.810980575
Short name T367
Test name
Test status
Simulation time 129603138 ps
CPU time 5.03 seconds
Started Aug 12 05:49:16 PM PDT 24
Finished Aug 12 05:49:21 PM PDT 24
Peak memory 210876 kb
Host smart-348e765c-9c13-46c6-9f25-a0605c6296f8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810980575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
810980575
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1762188597
Short name T73
Test name
Test status
Simulation time 542904346 ps
CPU time 27.44 seconds
Started Aug 12 05:49:15 PM PDT 24
Finished Aug 12 05:49:43 PM PDT 24
Peak memory 211044 kb
Host smart-ef81996d-b218-4618-8a0f-68020876c9b1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762188597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1762188597
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2013433638
Short name T351
Test name
Test status
Simulation time 498996655 ps
CPU time 5.23 seconds
Started Aug 12 05:49:11 PM PDT 24
Finished Aug 12 05:49:16 PM PDT 24
Peak memory 218584 kb
Host smart-6023e2d7-e912-4dc8-a43a-af2b6ffa4bce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013433638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2013433638
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2813671901
Short name T409
Test name
Test status
Simulation time 255230476 ps
CPU time 7.56 seconds
Started Aug 12 05:49:15 PM PDT 24
Finished Aug 12 05:49:23 PM PDT 24
Peak memory 219188 kb
Host smart-aa0f5551-2349-41d1-b6f5-fe4c6384f264
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813671901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2813671901
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3250691321
Short name T339
Test name
Test status
Simulation time 193555198 ps
CPU time 38.43 seconds
Started Aug 12 05:49:15 PM PDT 24
Finished Aug 12 05:49:53 PM PDT 24
Peak memory 211552 kb
Host smart-706cb240-5d59-4031-8f1b-2cf1ef5aa1a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250691321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3250691321
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2850832065
Short name T365
Test name
Test status
Simulation time 420450601 ps
CPU time 4.69 seconds
Started Aug 12 05:49:27 PM PDT 24
Finished Aug 12 05:49:32 PM PDT 24
Peak memory 219216 kb
Host smart-ebee1403-53e7-4394-b380-82dbfe0adfd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850832065 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2850832065
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1699735436
Short name T383
Test name
Test status
Simulation time 89395034 ps
CPU time 4.27 seconds
Started Aug 12 05:49:15 PM PDT 24
Finished Aug 12 05:49:20 PM PDT 24
Peak memory 210972 kb
Host smart-4f9cf6ad-d928-421e-b76d-efd5cb975698
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699735436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1699735436
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1348094500
Short name T97
Test name
Test status
Simulation time 5388952316 ps
CPU time 27.87 seconds
Started Aug 12 05:49:14 PM PDT 24
Finished Aug 12 05:49:42 PM PDT 24
Peak memory 211144 kb
Host smart-4cb4b578-3f62-4036-80d8-fa538bec113f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348094500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1348094500
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1986557345
Short name T341
Test name
Test status
Simulation time 138612083 ps
CPU time 6.94 seconds
Started Aug 12 05:49:15 PM PDT 24
Finished Aug 12 05:49:22 PM PDT 24
Peak memory 218580 kb
Host smart-e5a9d811-e6d5-4cc6-8720-7e5a40ffceca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986557345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1986557345
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3238586453
Short name T398
Test name
Test status
Simulation time 333556122 ps
CPU time 6.49 seconds
Started Aug 12 05:49:15 PM PDT 24
Finished Aug 12 05:49:22 PM PDT 24
Peak memory 219248 kb
Host smart-8a6991d6-6b57-4880-9c86-7bb7ba48f6f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238586453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3238586453
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3936289342
Short name T370
Test name
Test status
Simulation time 631038149 ps
CPU time 70.63 seconds
Started Aug 12 05:49:12 PM PDT 24
Finished Aug 12 05:50:23 PM PDT 24
Peak memory 219172 kb
Host smart-8e621087-a73b-43e6-b0f8-614d7176e828
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936289342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3936289342
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2501638594
Short name T399
Test name
Test status
Simulation time 100577703 ps
CPU time 5.57 seconds
Started Aug 12 05:49:20 PM PDT 24
Finished Aug 12 05:49:26 PM PDT 24
Peak memory 219212 kb
Host smart-0982adec-24cf-4014-a04a-08a79b099c55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501638594 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2501638594
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3736275097
Short name T397
Test name
Test status
Simulation time 249773077 ps
CPU time 5.08 seconds
Started Aug 12 05:49:20 PM PDT 24
Finished Aug 12 05:49:25 PM PDT 24
Peak memory 211012 kb
Host smart-66d73922-b05c-42dc-b9e8-3900424daf4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736275097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3736275097
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1299280968
Short name T95
Test name
Test status
Simulation time 796555822 ps
CPU time 32.18 seconds
Started Aug 12 05:49:22 PM PDT 24
Finished Aug 12 05:49:54 PM PDT 24
Peak memory 211036 kb
Host smart-397d0fcf-2a31-4769-aab1-d52b83f3b2d5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299280968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1299280968
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3409869883
Short name T359
Test name
Test status
Simulation time 320435331 ps
CPU time 4.32 seconds
Started Aug 12 05:49:19 PM PDT 24
Finished Aug 12 05:49:23 PM PDT 24
Peak memory 211028 kb
Host smart-931ff18f-aa4d-4b15-a8b5-2d1d57f6430c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409869883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3409869883
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.406488332
Short name T53
Test name
Test status
Simulation time 505208579 ps
CPU time 9.87 seconds
Started Aug 12 05:49:19 PM PDT 24
Finished Aug 12 05:49:29 PM PDT 24
Peak memory 219264 kb
Host smart-56477722-1996-4ac6-a232-e24f9306bdff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406488332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.406488332
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2825467803
Short name T51
Test name
Test status
Simulation time 847779157 ps
CPU time 69.81 seconds
Started Aug 12 05:49:24 PM PDT 24
Finished Aug 12 05:50:34 PM PDT 24
Peak memory 219348 kb
Host smart-587ee9d5-701b-4fa2-801e-d85060e1f541
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825467803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2825467803
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3898836145
Short name T388
Test name
Test status
Simulation time 273569957 ps
CPU time 6.2 seconds
Started Aug 12 05:49:23 PM PDT 24
Finished Aug 12 05:49:30 PM PDT 24
Peak memory 219260 kb
Host smart-f8fc9071-2c91-487c-8613-8451f5c41f59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898836145 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3898836145
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1083786702
Short name T376
Test name
Test status
Simulation time 495522421 ps
CPU time 5.03 seconds
Started Aug 12 05:49:28 PM PDT 24
Finished Aug 12 05:49:33 PM PDT 24
Peak memory 218164 kb
Host smart-a24f52bb-d587-4c16-bc2f-b86f7df9affc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083786702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1083786702
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1293678676
Short name T345
Test name
Test status
Simulation time 131829343 ps
CPU time 5.16 seconds
Started Aug 12 05:49:24 PM PDT 24
Finished Aug 12 05:49:29 PM PDT 24
Peak memory 211016 kb
Host smart-b4bc71c2-bbd3-47df-adf5-eb61fbf3e2ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293678676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1293678676
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.55049517
Short name T390
Test name
Test status
Simulation time 172534367 ps
CPU time 8.4 seconds
Started Aug 12 05:49:20 PM PDT 24
Finished Aug 12 05:49:28 PM PDT 24
Peak memory 219256 kb
Host smart-6f43d8fa-f5f8-406a-ac75-6e4cf18a1d96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55049517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.55049517
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2158264985
Short name T105
Test name
Test status
Simulation time 394359417 ps
CPU time 37.87 seconds
Started Aug 12 05:49:23 PM PDT 24
Finished Aug 12 05:50:01 PM PDT 24
Peak memory 219176 kb
Host smart-07c1998e-5eb2-43c0-8868-ded0f60310b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158264985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2158264985
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2417029162
Short name T47
Test name
Test status
Simulation time 328960694 ps
CPU time 4.69 seconds
Started Aug 12 05:49:19 PM PDT 24
Finished Aug 12 05:49:24 PM PDT 24
Peak memory 215268 kb
Host smart-27dec01b-250c-4342-8b63-fc7e9fe85e07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417029162 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2417029162
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2624949458
Short name T94
Test name
Test status
Simulation time 347044104 ps
CPU time 4.25 seconds
Started Aug 12 05:49:19 PM PDT 24
Finished Aug 12 05:49:23 PM PDT 24
Peak memory 218268 kb
Host smart-5dd83078-2ae3-4828-8bf4-95a3138cc612
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624949458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2624949458
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1173846004
Short name T382
Test name
Test status
Simulation time 788922114 ps
CPU time 32.02 seconds
Started Aug 12 05:49:19 PM PDT 24
Finished Aug 12 05:49:51 PM PDT 24
Peak memory 211068 kb
Host smart-7619b450-51fe-416c-b208-fa27bcaebc6b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173846004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1173846004
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1704032694
Short name T346
Test name
Test status
Simulation time 334392273 ps
CPU time 4.31 seconds
Started Aug 12 05:49:27 PM PDT 24
Finished Aug 12 05:49:32 PM PDT 24
Peak memory 210988 kb
Host smart-737835fc-1ee1-4d1c-8b87-0270c5d7d912
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704032694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1704032694
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3071889546
Short name T369
Test name
Test status
Simulation time 309667396 ps
CPU time 6.75 seconds
Started Aug 12 05:49:28 PM PDT 24
Finished Aug 12 05:49:35 PM PDT 24
Peak memory 219232 kb
Host smart-223ed2c7-7ce5-408d-bf03-197edc8fc71d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071889546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3071889546
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.174953660
Short name T404
Test name
Test status
Simulation time 204635010 ps
CPU time 38.1 seconds
Started Aug 12 05:49:23 PM PDT 24
Finished Aug 12 05:50:01 PM PDT 24
Peak memory 212664 kb
Host smart-5b9dad15-e800-4428-8780-491d385f9f2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174953660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.174953660
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3477769381
Short name T400
Test name
Test status
Simulation time 98084378 ps
CPU time 4.86 seconds
Started Aug 12 05:49:23 PM PDT 24
Finished Aug 12 05:49:29 PM PDT 24
Peak memory 219224 kb
Host smart-08deeda5-deb7-4385-905b-6a2c2d9cf642
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477769381 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3477769381
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4269284629
Short name T96
Test name
Test status
Simulation time 103572085 ps
CPU time 4.18 seconds
Started Aug 12 05:49:19 PM PDT 24
Finished Aug 12 05:49:23 PM PDT 24
Peak memory 217572 kb
Host smart-4989ee7f-6e47-4d9c-a251-5731791fdf0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269284629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.4269284629
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1014588456
Short name T86
Test name
Test status
Simulation time 1209072723 ps
CPU time 22.24 seconds
Started Aug 12 05:49:23 PM PDT 24
Finished Aug 12 05:49:46 PM PDT 24
Peak memory 211064 kb
Host smart-87888c0f-75c5-4f07-8aa5-b6c03d854476
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014588456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1014588456
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.666299262
Short name T393
Test name
Test status
Simulation time 266214669 ps
CPU time 7.04 seconds
Started Aug 12 05:49:22 PM PDT 24
Finished Aug 12 05:49:29 PM PDT 24
Peak memory 211024 kb
Host smart-ab872c59-f772-4dca-8459-870111278124
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666299262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.666299262
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2393815754
Short name T344
Test name
Test status
Simulation time 2348225170 ps
CPU time 9.77 seconds
Started Aug 12 05:49:24 PM PDT 24
Finished Aug 12 05:49:34 PM PDT 24
Peak memory 219284 kb
Host smart-4ad1580a-fb01-4011-885e-71707d1853e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393815754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2393815754
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2856688711
Short name T325
Test name
Test status
Simulation time 227602395 ps
CPU time 37.97 seconds
Started Aug 12 05:49:23 PM PDT 24
Finished Aug 12 05:50:01 PM PDT 24
Peak memory 212428 kb
Host smart-bd808c79-9d29-46e3-ba59-854dde3b88c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856688711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2856688711
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3931576749
Short name T202
Test name
Test status
Simulation time 260248058 ps
CPU time 5.27 seconds
Started Aug 12 05:07:19 PM PDT 24
Finished Aug 12 05:07:24 PM PDT 24
Peak memory 211704 kb
Host smart-a2745ffd-d5d4-42c3-9b35-307d70e0ff99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931576749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3931576749
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2169969582
Short name T176
Test name
Test status
Simulation time 1569282529 ps
CPU time 91.27 seconds
Started Aug 12 05:07:12 PM PDT 24
Finished Aug 12 05:08:43 PM PDT 24
Peak memory 228440 kb
Host smart-fb119897-ff58-464b-b727-6f59a5da06b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169969582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2169969582
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2209704736
Short name T261
Test name
Test status
Simulation time 425964947 ps
CPU time 11.09 seconds
Started Aug 12 05:07:13 PM PDT 24
Finished Aug 12 05:07:25 PM PDT 24
Peak memory 212516 kb
Host smart-fa122482-ba05-4f8a-9813-04d90649c19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209704736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2209704736
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.365219740
Short name T258
Test name
Test status
Simulation time 190261181 ps
CPU time 5.73 seconds
Started Aug 12 05:07:12 PM PDT 24
Finished Aug 12 05:07:18 PM PDT 24
Peak memory 211372 kb
Host smart-3bcb0aa2-9e80-4e79-90a6-03ec6d2cafef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365219740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.365219740
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2636635341
Short name T161
Test name
Test status
Simulation time 243314940 ps
CPU time 6.44 seconds
Started Aug 12 05:07:12 PM PDT 24
Finished Aug 12 05:07:19 PM PDT 24
Peak memory 211412 kb
Host smart-bb537ed7-4b99-47a5-83b7-240476947949
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636635341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2636635341
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2493221174
Short name T293
Test name
Test status
Simulation time 90993129 ps
CPU time 4.45 seconds
Started Aug 12 05:07:20 PM PDT 24
Finished Aug 12 05:07:24 PM PDT 24
Peak memory 211572 kb
Host smart-297da4b4-547a-46b1-83ba-2845417c0758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493221174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2493221174
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1210154964
Short name T260
Test name
Test status
Simulation time 7414001924 ps
CPU time 122.47 seconds
Started Aug 12 05:07:21 PM PDT 24
Finished Aug 12 05:09:23 PM PDT 24
Peak memory 237512 kb
Host smart-1df3ab39-daf6-4ebc-80ae-2a0b81f28806
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210154964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1210154964
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.745367935
Short name T239
Test name
Test status
Simulation time 614547696 ps
CPU time 5.69 seconds
Started Aug 12 05:07:20 PM PDT 24
Finished Aug 12 05:07:26 PM PDT 24
Peak memory 211432 kb
Host smart-5840982e-8ead-4d56-b4ee-1338f7d946c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=745367935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.745367935
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2068111861
Short name T23
Test name
Test status
Simulation time 179114862 ps
CPU time 53.48 seconds
Started Aug 12 05:07:19 PM PDT 24
Finished Aug 12 05:08:13 PM PDT 24
Peak memory 236740 kb
Host smart-92c26402-2c42-4841-a2a7-a5211b038b10
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068111861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2068111861
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2022207406
Short name T131
Test name
Test status
Simulation time 131767944 ps
CPU time 5.58 seconds
Started Aug 12 05:07:21 PM PDT 24
Finished Aug 12 05:07:26 PM PDT 24
Peak memory 211340 kb
Host smart-57d8a0c1-9bab-4097-9326-0082d8439bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022207406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2022207406
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3803485749
Short name T229
Test name
Test status
Simulation time 1130867981 ps
CPU time 16.27 seconds
Started Aug 12 05:07:21 PM PDT 24
Finished Aug 12 05:07:37 PM PDT 24
Peak memory 213020 kb
Host smart-71a47bc8-d448-4a91-9872-879b26324c10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803485749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3803485749
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1729176929
Short name T199
Test name
Test status
Simulation time 522165539 ps
CPU time 5.01 seconds
Started Aug 12 05:07:38 PM PDT 24
Finished Aug 12 05:07:43 PM PDT 24
Peak memory 211544 kb
Host smart-3ee1b05c-f646-4220-98b9-1df3dd8c6840
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729176929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1729176929
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1614333585
Short name T122
Test name
Test status
Simulation time 1598642206 ps
CPU time 93.62 seconds
Started Aug 12 05:07:34 PM PDT 24
Finished Aug 12 05:09:08 PM PDT 24
Peak memory 236628 kb
Host smart-78e233ab-a26e-4b45-ae9f-12b37bc4e799
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614333585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1614333585
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.365448217
Short name T304
Test name
Test status
Simulation time 178186453 ps
CPU time 9.53 seconds
Started Aug 12 05:07:34 PM PDT 24
Finished Aug 12 05:07:44 PM PDT 24
Peak memory 212264 kb
Host smart-a6919e00-5084-43d3-b3e5-b15f27b99635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365448217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.365448217
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.762023353
Short name T256
Test name
Test status
Simulation time 280630570 ps
CPU time 6.68 seconds
Started Aug 12 05:07:36 PM PDT 24
Finished Aug 12 05:07:42 PM PDT 24
Peak memory 211340 kb
Host smart-acd5669c-c57f-4c2a-b237-be1444b21815
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=762023353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.762023353
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1369522537
Short name T311
Test name
Test status
Simulation time 433533681 ps
CPU time 8.48 seconds
Started Aug 12 05:07:38 PM PDT 24
Finished Aug 12 05:07:46 PM PDT 24
Peak memory 211508 kb
Host smart-5c2fa52a-82c2-431a-9b45-c9cf35f3437b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369522537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1369522537
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3087076490
Short name T169
Test name
Test status
Simulation time 259774443 ps
CPU time 5.27 seconds
Started Aug 12 05:07:35 PM PDT 24
Finished Aug 12 05:07:41 PM PDT 24
Peak memory 211460 kb
Host smart-a6b7a5ad-66ee-422c-b198-98b0275de4a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087076490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3087076490
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2732564888
Short name T298
Test name
Test status
Simulation time 5920272961 ps
CPU time 103.56 seconds
Started Aug 12 05:07:35 PM PDT 24
Finished Aug 12 05:09:19 PM PDT 24
Peak memory 225552 kb
Host smart-889406e5-aaf3-4fbb-a72c-d469a48e76a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732564888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2732564888
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2753664337
Short name T182
Test name
Test status
Simulation time 1659179050 ps
CPU time 9.46 seconds
Started Aug 12 05:07:35 PM PDT 24
Finished Aug 12 05:07:45 PM PDT 24
Peak memory 212276 kb
Host smart-d9376337-f011-4597-92f3-279725b500d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753664337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2753664337
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.627482260
Short name T296
Test name
Test status
Simulation time 99122325 ps
CPU time 5.38 seconds
Started Aug 12 05:07:35 PM PDT 24
Finished Aug 12 05:07:40 PM PDT 24
Peak memory 211372 kb
Host smart-62f7801f-145c-4d69-8ea8-db430624ce50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=627482260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.627482260
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2907789757
Short name T200
Test name
Test status
Simulation time 437953127 ps
CPU time 21.77 seconds
Started Aug 12 05:07:35 PM PDT 24
Finished Aug 12 05:07:57 PM PDT 24
Peak memory 214232 kb
Host smart-2ffb55ef-65da-423d-87bb-dcdb07049b2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907789757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2907789757
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.4039527140
Short name T136
Test name
Test status
Simulation time 1676614832 ps
CPU time 4.36 seconds
Started Aug 12 05:07:35 PM PDT 24
Finished Aug 12 05:07:40 PM PDT 24
Peak memory 211512 kb
Host smart-4e4b98f1-e464-4e10-af79-d81ea947e761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039527140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4039527140
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4096830965
Short name T247
Test name
Test status
Simulation time 14028917756 ps
CPU time 141 seconds
Started Aug 12 05:07:35 PM PDT 24
Finished Aug 12 05:09:56 PM PDT 24
Peak memory 228496 kb
Host smart-9395a6dc-c75c-441f-9ad4-6aced687f9c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096830965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.4096830965
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3548665176
Short name T309
Test name
Test status
Simulation time 174627093 ps
CPU time 9.63 seconds
Started Aug 12 05:07:36 PM PDT 24
Finished Aug 12 05:07:46 PM PDT 24
Peak memory 212256 kb
Host smart-f486de55-4ad8-4456-b32d-998b79b2889e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548665176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3548665176
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2264284881
Short name T248
Test name
Test status
Simulation time 99303518 ps
CPU time 5.48 seconds
Started Aug 12 05:07:37 PM PDT 24
Finished Aug 12 05:07:43 PM PDT 24
Peak memory 211448 kb
Host smart-925e130b-9b99-4293-bdc8-c327af558140
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2264284881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2264284881
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2560790308
Short name T142
Test name
Test status
Simulation time 1068644146 ps
CPU time 19.41 seconds
Started Aug 12 05:07:37 PM PDT 24
Finished Aug 12 05:07:56 PM PDT 24
Peak memory 214052 kb
Host smart-05b6ede9-278f-4464-8c32-d68ea7d5671c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560790308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2560790308
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1889305865
Short name T280
Test name
Test status
Simulation time 257617231 ps
CPU time 5.32 seconds
Started Aug 12 05:07:35 PM PDT 24
Finished Aug 12 05:07:41 PM PDT 24
Peak memory 211576 kb
Host smart-5c7670b2-28ce-4647-85b3-98b70f235e91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889305865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1889305865
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3812546294
Short name T22
Test name
Test status
Simulation time 2258001767 ps
CPU time 11.08 seconds
Started Aug 12 05:07:36 PM PDT 24
Finished Aug 12 05:07:47 PM PDT 24
Peak memory 212516 kb
Host smart-8f64f2a3-cf41-4702-acac-cf645aa9edff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812546294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3812546294
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4197118039
Short name T257
Test name
Test status
Simulation time 393196245 ps
CPU time 5.48 seconds
Started Aug 12 05:07:36 PM PDT 24
Finished Aug 12 05:07:42 PM PDT 24
Peak memory 211392 kb
Host smart-0ac5651a-6898-4c7f-95d8-44a853064d96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4197118039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4197118039
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1482693502
Short name T187
Test name
Test status
Simulation time 304434316 ps
CPU time 18.15 seconds
Started Aug 12 05:07:35 PM PDT 24
Finished Aug 12 05:07:53 PM PDT 24
Peak memory 214436 kb
Host smart-62ba8fec-79cb-4d7a-a274-7dd8da39b3a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482693502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1482693502
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1104000853
Short name T153
Test name
Test status
Simulation time 252647560 ps
CPU time 5.14 seconds
Started Aug 12 05:07:42 PM PDT 24
Finished Aug 12 05:07:48 PM PDT 24
Peak memory 211496 kb
Host smart-e91fc65f-8ebe-4b8b-ad2c-e0c21cf91a35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104000853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1104000853
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2962372848
Short name T138
Test name
Test status
Simulation time 3163733068 ps
CPU time 66.7 seconds
Started Aug 12 05:07:37 PM PDT 24
Finished Aug 12 05:08:44 PM PDT 24
Peak memory 228268 kb
Host smart-0c36b714-4503-4e85-9db7-a027a357a1fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962372848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2962372848
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3302849168
Short name T143
Test name
Test status
Simulation time 667261260 ps
CPU time 9.39 seconds
Started Aug 12 05:07:43 PM PDT 24
Finished Aug 12 05:07:52 PM PDT 24
Peak memory 212292 kb
Host smart-6bf068b9-f118-44cf-9cad-2f2284ca4bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302849168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3302849168
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3980443610
Short name T177
Test name
Test status
Simulation time 193333952 ps
CPU time 5.82 seconds
Started Aug 12 05:07:35 PM PDT 24
Finished Aug 12 05:07:41 PM PDT 24
Peak memory 211372 kb
Host smart-cb1aa965-218d-4a24-aa50-8a4f4e1f3e23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3980443610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3980443610
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2659877540
Short name T186
Test name
Test status
Simulation time 132459371 ps
CPU time 5.09 seconds
Started Aug 12 05:07:44 PM PDT 24
Finished Aug 12 05:07:49 PM PDT 24
Peak memory 211580 kb
Host smart-fb8c73bc-8579-4ca4-971a-b8f67f83bef8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659877540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2659877540
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1827723189
Short name T118
Test name
Test status
Simulation time 6728445171 ps
CPU time 177.44 seconds
Started Aug 12 05:07:42 PM PDT 24
Finished Aug 12 05:10:40 PM PDT 24
Peak memory 213960 kb
Host smart-985106a1-9c15-4774-b058-5b361986419b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827723189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1827723189
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.972998719
Short name T219
Test name
Test status
Simulation time 257362916 ps
CPU time 11.38 seconds
Started Aug 12 05:07:45 PM PDT 24
Finished Aug 12 05:07:56 PM PDT 24
Peak memory 212436 kb
Host smart-de69d2e5-4c78-43ad-bb51-0ab0a03ae022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972998719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.972998719
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1042837095
Short name T226
Test name
Test status
Simulation time 138606248 ps
CPU time 6.34 seconds
Started Aug 12 05:07:45 PM PDT 24
Finished Aug 12 05:07:51 PM PDT 24
Peak memory 211316 kb
Host smart-9c43ae93-8ebe-4a0f-ab85-0d3fd2ec6d25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1042837095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1042837095
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2624584180
Short name T253
Test name
Test status
Simulation time 825213134 ps
CPU time 10.57 seconds
Started Aug 12 05:07:45 PM PDT 24
Finished Aug 12 05:07:56 PM PDT 24
Peak memory 213932 kb
Host smart-bb12709c-8c32-4134-937f-6a08b0d6c93b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624584180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2624584180
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2166444802
Short name T295
Test name
Test status
Simulation time 85885058 ps
CPU time 4.18 seconds
Started Aug 12 05:07:44 PM PDT 24
Finished Aug 12 05:07:48 PM PDT 24
Peak memory 211516 kb
Host smart-8eb97304-18d0-4a81-99bb-fccdd7513439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166444802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2166444802
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2013342384
Short name T254
Test name
Test status
Simulation time 1738159270 ps
CPU time 110.68 seconds
Started Aug 12 05:07:43 PM PDT 24
Finished Aug 12 05:09:34 PM PDT 24
Peak memory 236660 kb
Host smart-c14a133f-af4e-452d-a88b-77a78837aa4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013342384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2013342384
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1452113809
Short name T155
Test name
Test status
Simulation time 285356132 ps
CPU time 11.64 seconds
Started Aug 12 05:07:53 PM PDT 24
Finished Aug 12 05:08:05 PM PDT 24
Peak memory 212376 kb
Host smart-9c443ef9-f627-4633-a31e-cfe65b823d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452113809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1452113809
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2697400889
Short name T189
Test name
Test status
Simulation time 97153642 ps
CPU time 5.56 seconds
Started Aug 12 05:07:43 PM PDT 24
Finished Aug 12 05:07:48 PM PDT 24
Peak memory 211268 kb
Host smart-45fe03ae-3c5b-4d01-805b-78c4651d4d55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2697400889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2697400889
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1387699787
Short name T259
Test name
Test status
Simulation time 320873266 ps
CPU time 16.27 seconds
Started Aug 12 05:07:45 PM PDT 24
Finished Aug 12 05:08:02 PM PDT 24
Peak memory 214016 kb
Host smart-94bc3e0a-96fd-4dba-8620-f6497302de99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387699787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1387699787
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1316996114
Short name T220
Test name
Test status
Simulation time 168526786 ps
CPU time 4.25 seconds
Started Aug 12 05:07:43 PM PDT 24
Finished Aug 12 05:07:48 PM PDT 24
Peak memory 211560 kb
Host smart-f7346229-8495-41dc-9f73-76d4fd742d49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316996114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1316996114
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1008527476
Short name T276
Test name
Test status
Simulation time 13636317404 ps
CPU time 127.48 seconds
Started Aug 12 05:07:44 PM PDT 24
Finished Aug 12 05:09:52 PM PDT 24
Peak memory 225628 kb
Host smart-51c633cb-2f51-4b03-bbdd-27727f6a67ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008527476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1008527476
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2263310911
Short name T174
Test name
Test status
Simulation time 3117514244 ps
CPU time 11.08 seconds
Started Aug 12 05:07:42 PM PDT 24
Finished Aug 12 05:07:54 PM PDT 24
Peak memory 212436 kb
Host smart-44489b20-0a1f-4162-b063-f3c40ac389fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263310911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2263310911
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3143388274
Short name T231
Test name
Test status
Simulation time 135881282 ps
CPU time 6.6 seconds
Started Aug 12 05:07:46 PM PDT 24
Finished Aug 12 05:07:52 PM PDT 24
Peak memory 211368 kb
Host smart-da795cd0-45a5-4492-bcd0-ca626a0b1dab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3143388274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3143388274
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.908702856
Short name T192
Test name
Test status
Simulation time 500918720 ps
CPU time 5.03 seconds
Started Aug 12 05:07:44 PM PDT 24
Finished Aug 12 05:07:49 PM PDT 24
Peak memory 211512 kb
Host smart-c447f3f0-dfa5-4407-80d5-2b6a03a01a74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908702856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.908702856
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2489455328
Short name T241
Test name
Test status
Simulation time 5761719580 ps
CPU time 104.84 seconds
Started Aug 12 05:07:46 PM PDT 24
Finished Aug 12 05:09:31 PM PDT 24
Peak memory 228548 kb
Host smart-130bfc97-fbd5-479c-83c7-790814d3ce2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489455328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2489455328
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2899372665
Short name T240
Test name
Test status
Simulation time 727715149 ps
CPU time 9.44 seconds
Started Aug 12 05:07:46 PM PDT 24
Finished Aug 12 05:07:55 PM PDT 24
Peak memory 212360 kb
Host smart-92f8ee03-2ab5-4f5d-8264-c29b15c5ec13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899372665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2899372665
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.192048843
Short name T238
Test name
Test status
Simulation time 140510097 ps
CPU time 6.53 seconds
Started Aug 12 05:07:45 PM PDT 24
Finished Aug 12 05:07:52 PM PDT 24
Peak memory 211428 kb
Host smart-bf6bd403-6926-43f6-b663-3b03032fcdbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=192048843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.192048843
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1389203481
Short name T152
Test name
Test status
Simulation time 1497355793 ps
CPU time 90.44 seconds
Started Aug 12 05:07:45 PM PDT 24
Finished Aug 12 05:09:16 PM PDT 24
Peak memory 236688 kb
Host smart-05ecb8dd-fdd3-4be6-9d2b-e09bade4af52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389203481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1389203481
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.4211984576
Short name T249
Test name
Test status
Simulation time 2501063628 ps
CPU time 11.2 seconds
Started Aug 12 05:07:45 PM PDT 24
Finished Aug 12 05:07:57 PM PDT 24
Peak memory 212656 kb
Host smart-108920a1-435f-49a0-ad9f-dc7bf33eec2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211984576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.4211984576
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1279347044
Short name T115
Test name
Test status
Simulation time 946023518 ps
CPU time 6.37 seconds
Started Aug 12 05:07:47 PM PDT 24
Finished Aug 12 05:07:53 PM PDT 24
Peak memory 211368 kb
Host smart-2730eefb-5ae8-44c5-9555-50344bc7b6d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1279347044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1279347044
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3330947531
Short name T132
Test name
Test status
Simulation time 211565042 ps
CPU time 13.82 seconds
Started Aug 12 05:07:44 PM PDT 24
Finished Aug 12 05:07:57 PM PDT 24
Peak memory 214220 kb
Host smart-b40452a3-1ec9-4243-9cd6-b99821333fb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330947531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3330947531
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.873523395
Short name T272
Test name
Test status
Simulation time 333712101 ps
CPU time 4.13 seconds
Started Aug 12 05:07:21 PM PDT 24
Finished Aug 12 05:07:26 PM PDT 24
Peak memory 211484 kb
Host smart-001e3090-71bc-48ce-ab20-bf99f750830e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873523395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.873523395
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.353352261
Short name T235
Test name
Test status
Simulation time 3372006195 ps
CPU time 51.53 seconds
Started Aug 12 05:07:22 PM PDT 24
Finished Aug 12 05:08:14 PM PDT 24
Peak memory 237848 kb
Host smart-ced8f358-498b-4a7a-9bcd-11fbc2edb0f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353352261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.353352261
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4136292551
Short name T312
Test name
Test status
Simulation time 168194383 ps
CPU time 9.49 seconds
Started Aug 12 05:07:21 PM PDT 24
Finished Aug 12 05:07:30 PM PDT 24
Peak memory 212280 kb
Host smart-f866ee62-bd41-43aa-8de7-957c2c020d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136292551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.4136292551
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4119276137
Short name T120
Test name
Test status
Simulation time 199769600 ps
CPU time 5.96 seconds
Started Aug 12 05:07:22 PM PDT 24
Finished Aug 12 05:07:28 PM PDT 24
Peak memory 211412 kb
Host smart-73f78fc9-e31b-42ff-be26-7d791434e039
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4119276137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.4119276137
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1981518487
Short name T30
Test name
Test status
Simulation time 803686628 ps
CPU time 100.25 seconds
Started Aug 12 05:07:20 PM PDT 24
Finished Aug 12 05:09:01 PM PDT 24
Peak memory 238808 kb
Host smart-db7f9b3e-ca48-48e3-b012-94fc6b4b44dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981518487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1981518487
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3479198317
Short name T8
Test name
Test status
Simulation time 280319093 ps
CPU time 6.48 seconds
Started Aug 12 05:07:21 PM PDT 24
Finished Aug 12 05:07:27 PM PDT 24
Peak memory 211356 kb
Host smart-ce57b11b-b4e4-4e16-b171-c9add57d035a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479198317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3479198317
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.857984455
Short name T83
Test name
Test status
Simulation time 704298426 ps
CPU time 10.12 seconds
Started Aug 12 05:07:21 PM PDT 24
Finished Aug 12 05:07:31 PM PDT 24
Peak memory 213384 kb
Host smart-eea7fd27-b182-467f-91f4-38ad9a89a10f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857984455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.857984455
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.515859876
Short name T128
Test name
Test status
Simulation time 177072256 ps
CPU time 4.29 seconds
Started Aug 12 05:07:45 PM PDT 24
Finished Aug 12 05:07:49 PM PDT 24
Peak memory 211560 kb
Host smart-8787648b-b254-49c3-934b-3ecd6722e81f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515859876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.515859876
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2921160637
Short name T129
Test name
Test status
Simulation time 5596088884 ps
CPU time 71.63 seconds
Started Aug 12 05:07:44 PM PDT 24
Finished Aug 12 05:08:55 PM PDT 24
Peak memory 236736 kb
Host smart-19f4f4d5-5836-4592-8f8f-e6c3a3e53aa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921160637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2921160637
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3227886880
Short name T154
Test name
Test status
Simulation time 1316110727 ps
CPU time 11.2 seconds
Started Aug 12 05:07:44 PM PDT 24
Finished Aug 12 05:07:55 PM PDT 24
Peak memory 212224 kb
Host smart-7a0f5ead-099b-4b1c-b105-3393f05b6234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227886880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3227886880
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2013090031
Short name T4
Test name
Test status
Simulation time 436726526 ps
CPU time 8.42 seconds
Started Aug 12 05:07:47 PM PDT 24
Finished Aug 12 05:07:55 PM PDT 24
Peak memory 211368 kb
Host smart-a7ed8d0a-dfae-4aab-a992-dc9a8c67b2a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013090031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2013090031
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3530972064
Short name T246
Test name
Test status
Simulation time 89984262 ps
CPU time 4.38 seconds
Started Aug 12 05:07:53 PM PDT 24
Finished Aug 12 05:07:58 PM PDT 24
Peak memory 211488 kb
Host smart-3586608e-1eae-458a-8be6-d93b57df7c0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530972064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3530972064
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4052478434
Short name T156
Test name
Test status
Simulation time 255776772 ps
CPU time 11.17 seconds
Started Aug 12 05:07:44 PM PDT 24
Finished Aug 12 05:07:55 PM PDT 24
Peak memory 212160 kb
Host smart-579a9d97-20ee-40a0-b583-362e458dcf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052478434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4052478434
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4054918990
Short name T215
Test name
Test status
Simulation time 333877186 ps
CPU time 5.85 seconds
Started Aug 12 05:07:48 PM PDT 24
Finished Aug 12 05:07:54 PM PDT 24
Peak memory 211444 kb
Host smart-e0566dd3-f8d0-4408-aa7b-c6ac5a182087
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4054918990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.4054918990
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2983529972
Short name T185
Test name
Test status
Simulation time 603323065 ps
CPU time 11.78 seconds
Started Aug 12 05:07:45 PM PDT 24
Finished Aug 12 05:07:57 PM PDT 24
Peak memory 211956 kb
Host smart-72950ef1-e6a8-459f-bc5e-981a8b41ba88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983529972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2983529972
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2623802481
Short name T67
Test name
Test status
Simulation time 1068127602 ps
CPU time 7.75 seconds
Started Aug 12 05:07:53 PM PDT 24
Finished Aug 12 05:08:01 PM PDT 24
Peak memory 211580 kb
Host smart-cdfe153e-8158-4514-bfdd-f2bb3891addc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623802481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2623802481
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2076597683
Short name T167
Test name
Test status
Simulation time 22246940169 ps
CPU time 108.02 seconds
Started Aug 12 05:07:51 PM PDT 24
Finished Aug 12 05:09:39 PM PDT 24
Peak memory 212796 kb
Host smart-19f34968-bd77-4647-84ff-93b45edb2078
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076597683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2076597683
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3685177075
Short name T251
Test name
Test status
Simulation time 4473376657 ps
CPU time 16.54 seconds
Started Aug 12 05:07:51 PM PDT 24
Finished Aug 12 05:08:08 PM PDT 24
Peak memory 212524 kb
Host smart-6b117042-1939-4755-9abe-de0e980e22b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685177075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3685177075
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.451811543
Short name T180
Test name
Test status
Simulation time 426376828 ps
CPU time 5.76 seconds
Started Aug 12 05:07:54 PM PDT 24
Finished Aug 12 05:08:00 PM PDT 24
Peak memory 211368 kb
Host smart-5c5073c2-a1f7-40f6-9a17-40e752d22c7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=451811543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.451811543
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.585763619
Short name T126
Test name
Test status
Simulation time 610739397 ps
CPU time 14.17 seconds
Started Aug 12 05:07:52 PM PDT 24
Finished Aug 12 05:08:07 PM PDT 24
Peak memory 215012 kb
Host smart-d63c53e8-b9df-4274-978b-6be92ad180a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585763619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.585763619
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3137726123
Short name T196
Test name
Test status
Simulation time 518212514 ps
CPU time 5.16 seconds
Started Aug 12 05:07:51 PM PDT 24
Finished Aug 12 05:07:56 PM PDT 24
Peak memory 211464 kb
Host smart-2886c558-b743-4d0a-8a77-0fcf56dd351f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137726123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3137726123
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2622897639
Short name T201
Test name
Test status
Simulation time 1328229047 ps
CPU time 95.94 seconds
Started Aug 12 05:07:53 PM PDT 24
Finished Aug 12 05:09:29 PM PDT 24
Peak memory 237660 kb
Host smart-c775c643-eb2d-4799-83aa-e5f753f53202
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622897639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2622897639
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1053869484
Short name T42
Test name
Test status
Simulation time 1508878653 ps
CPU time 9.61 seconds
Started Aug 12 05:07:52 PM PDT 24
Finished Aug 12 05:08:02 PM PDT 24
Peak memory 212164 kb
Host smart-54ad0a29-650f-4394-8379-a664678c4714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053869484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1053869484
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1505162679
Short name T43
Test name
Test status
Simulation time 272844933 ps
CPU time 6.39 seconds
Started Aug 12 05:07:52 PM PDT 24
Finished Aug 12 05:07:58 PM PDT 24
Peak memory 211368 kb
Host smart-88fc8f0d-9d3d-4808-a089-0b799c1461c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1505162679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1505162679
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1592472609
Short name T283
Test name
Test status
Simulation time 224057658 ps
CPU time 13.61 seconds
Started Aug 12 05:07:57 PM PDT 24
Finished Aug 12 05:08:11 PM PDT 24
Peak memory 214512 kb
Host smart-d011a19d-8c1b-438b-acd0-3aefa1959c25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592472609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1592472609
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2336133982
Short name T281
Test name
Test status
Simulation time 127337216 ps
CPU time 5.3 seconds
Started Aug 12 05:07:52 PM PDT 24
Finished Aug 12 05:07:58 PM PDT 24
Peak memory 211576 kb
Host smart-75405264-666a-4199-805b-74151eb08594
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336133982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2336133982
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.962506578
Short name T302
Test name
Test status
Simulation time 4795078871 ps
CPU time 147.86 seconds
Started Aug 12 05:07:52 PM PDT 24
Finished Aug 12 05:10:20 PM PDT 24
Peak memory 237428 kb
Host smart-eedbe0ac-1eb8-4f3a-b0be-20105cf6dc18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962506578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.962506578
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4097706043
Short name T266
Test name
Test status
Simulation time 262907877 ps
CPU time 11.04 seconds
Started Aug 12 05:08:05 PM PDT 24
Finished Aug 12 05:08:16 PM PDT 24
Peak memory 212176 kb
Host smart-c0a09ded-08a2-4159-a3cc-a432c4b43525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097706043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4097706043
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1410480184
Short name T214
Test name
Test status
Simulation time 326442118 ps
CPU time 5.63 seconds
Started Aug 12 05:07:54 PM PDT 24
Finished Aug 12 05:07:59 PM PDT 24
Peak memory 211408 kb
Host smart-dff255af-a505-4a4e-b638-9a3b1d51bc2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1410480184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1410480184
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2382241874
Short name T268
Test name
Test status
Simulation time 437841198 ps
CPU time 8.46 seconds
Started Aug 12 05:08:05 PM PDT 24
Finished Aug 12 05:08:13 PM PDT 24
Peak memory 211372 kb
Host smart-710db5b5-bb32-40a2-b474-55b744123464
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382241874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2382241874
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3581414293
Short name T270
Test name
Test status
Simulation time 279567271 ps
CPU time 5.18 seconds
Started Aug 12 05:07:52 PM PDT 24
Finished Aug 12 05:07:57 PM PDT 24
Peak memory 211708 kb
Host smart-9cf6dc29-4d6b-4192-8a3e-e0f4b4f659a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581414293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3581414293
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1205775541
Short name T123
Test name
Test status
Simulation time 8225778097 ps
CPU time 127.56 seconds
Started Aug 12 05:07:53 PM PDT 24
Finished Aug 12 05:10:01 PM PDT 24
Peak memory 225572 kb
Host smart-b9676730-3570-47e4-89c6-dc233a7695b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205775541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1205775541
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1278667350
Short name T221
Test name
Test status
Simulation time 1310171357 ps
CPU time 11.02 seconds
Started Aug 12 05:08:05 PM PDT 24
Finished Aug 12 05:08:16 PM PDT 24
Peak memory 212224 kb
Host smart-fbfd7e84-3fc2-42f4-9287-bca9e59dc359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278667350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1278667350
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.325521132
Short name T227
Test name
Test status
Simulation time 254580310 ps
CPU time 5.13 seconds
Started Aug 12 05:07:51 PM PDT 24
Finished Aug 12 05:07:57 PM PDT 24
Peak memory 211348 kb
Host smart-ad7ff58a-24e9-4677-b39a-fd776e3b1008
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=325521132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.325521132
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1499097279
Short name T137
Test name
Test status
Simulation time 126814339 ps
CPU time 9.46 seconds
Started Aug 12 05:07:59 PM PDT 24
Finished Aug 12 05:08:08 PM PDT 24
Peak memory 211344 kb
Host smart-715bb6a8-6245-4a12-9ac6-296f16a078ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499097279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1499097279
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2881278888
Short name T3
Test name
Test status
Simulation time 86123742 ps
CPU time 4.21 seconds
Started Aug 12 05:08:04 PM PDT 24
Finished Aug 12 05:08:08 PM PDT 24
Peak memory 211516 kb
Host smart-74fbde81-7fc6-4203-9ad4-6d77b6b0ed79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881278888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2881278888
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2600427624
Short name T121
Test name
Test status
Simulation time 2049621970 ps
CPU time 73.39 seconds
Started Aug 12 05:07:51 PM PDT 24
Finished Aug 12 05:09:05 PM PDT 24
Peak memory 236944 kb
Host smart-780e4002-c83d-4cf5-b804-20b320c26e55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600427624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2600427624
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1327989062
Short name T216
Test name
Test status
Simulation time 618004801 ps
CPU time 6.24 seconds
Started Aug 12 05:07:56 PM PDT 24
Finished Aug 12 05:08:02 PM PDT 24
Peak memory 211256 kb
Host smart-1d3531ff-c8f7-444f-ab9a-4e37e7079cf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1327989062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1327989062
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3252059172
Short name T21
Test name
Test status
Simulation time 752113986 ps
CPU time 10.83 seconds
Started Aug 12 05:08:05 PM PDT 24
Finished Aug 12 05:08:16 PM PDT 24
Peak memory 211372 kb
Host smart-98eba31e-f611-4098-b875-0acb2e8bd28a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252059172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3252059172
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1308476344
Short name T291
Test name
Test status
Simulation time 1675164035 ps
CPU time 4.31 seconds
Started Aug 12 05:08:02 PM PDT 24
Finished Aug 12 05:08:06 PM PDT 24
Peak memory 211596 kb
Host smart-85cf81e8-81ad-4747-9807-0bd8ee8f8c71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308476344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1308476344
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1831918963
Short name T125
Test name
Test status
Simulation time 1784588879 ps
CPU time 124.4 seconds
Started Aug 12 05:08:00 PM PDT 24
Finished Aug 12 05:10:05 PM PDT 24
Peak memory 237744 kb
Host smart-73f42e97-63aa-4d9b-bca8-7becb21f60cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831918963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1831918963
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3221399589
Short name T148
Test name
Test status
Simulation time 1916326222 ps
CPU time 11.29 seconds
Started Aug 12 05:08:02 PM PDT 24
Finished Aug 12 05:08:14 PM PDT 24
Peak memory 212220 kb
Host smart-1eec4f63-65f1-4e67-b034-24f88942b24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221399589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3221399589
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3001190447
Short name T112
Test name
Test status
Simulation time 275607643 ps
CPU time 6.23 seconds
Started Aug 12 05:08:05 PM PDT 24
Finished Aug 12 05:08:12 PM PDT 24
Peak memory 211372 kb
Host smart-452380dd-b051-4a39-814a-a297d1d8a915
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3001190447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3001190447
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.613750682
Short name T133
Test name
Test status
Simulation time 580110890 ps
CPU time 15.99 seconds
Started Aug 12 05:07:53 PM PDT 24
Finished Aug 12 05:08:09 PM PDT 24
Peak memory 215348 kb
Host smart-5890d37e-061e-4c78-b652-ae50389a20e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613750682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.613750682
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3903321028
Short name T242
Test name
Test status
Simulation time 88950298 ps
CPU time 4.29 seconds
Started Aug 12 05:08:16 PM PDT 24
Finished Aug 12 05:08:21 PM PDT 24
Peak memory 211484 kb
Host smart-775decfb-a7a6-4b7b-8053-f53e90111309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903321028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3903321028
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.68103170
Short name T6
Test name
Test status
Simulation time 6620089957 ps
CPU time 82.67 seconds
Started Aug 12 05:08:01 PM PDT 24
Finished Aug 12 05:09:24 PM PDT 24
Peak memory 213784 kb
Host smart-6ad23d30-eb2d-44c5-b05b-f0cd4cd5040f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68103170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_co
rrupt_sig_fatal_chk.68103170
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.797847785
Short name T59
Test name
Test status
Simulation time 978979639 ps
CPU time 9.48 seconds
Started Aug 12 05:08:03 PM PDT 24
Finished Aug 12 05:08:13 PM PDT 24
Peak memory 212312 kb
Host smart-baf51cdd-1037-4ce0-b102-5019a773e91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797847785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.797847785
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1932867551
Short name T287
Test name
Test status
Simulation time 142990819 ps
CPU time 6.41 seconds
Started Aug 12 05:08:02 PM PDT 24
Finished Aug 12 05:08:09 PM PDT 24
Peak memory 211388 kb
Host smart-c860d787-f1d1-4fef-b4de-b4f11050d1bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1932867551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1932867551
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1145556683
Short name T274
Test name
Test status
Simulation time 146696421 ps
CPU time 8.39 seconds
Started Aug 12 05:08:01 PM PDT 24
Finished Aug 12 05:08:10 PM PDT 24
Peak memory 211452 kb
Host smart-5b2393df-b0a8-4972-8bb8-15816148be6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145556683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1145556683
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1339197210
Short name T181
Test name
Test status
Simulation time 825610917 ps
CPU time 5.07 seconds
Started Aug 12 05:08:01 PM PDT 24
Finished Aug 12 05:08:06 PM PDT 24
Peak memory 211708 kb
Host smart-577cc510-611e-4408-8a44-f6d968b4e89e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339197210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1339197210
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2577895640
Short name T237
Test name
Test status
Simulation time 4101511536 ps
CPU time 125.76 seconds
Started Aug 12 05:08:02 PM PDT 24
Finished Aug 12 05:10:08 PM PDT 24
Peak memory 228524 kb
Host smart-81176a06-e6aa-4a64-9f80-f26caeedc3ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577895640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2577895640
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2755761303
Short name T168
Test name
Test status
Simulation time 341421330 ps
CPU time 9.57 seconds
Started Aug 12 05:08:02 PM PDT 24
Finished Aug 12 05:08:12 PM PDT 24
Peak memory 212572 kb
Host smart-8adb4bdb-0c9c-43f1-85ee-514e93bf8e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755761303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2755761303
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1876745427
Short name T158
Test name
Test status
Simulation time 1312025889 ps
CPU time 5.36 seconds
Started Aug 12 05:08:01 PM PDT 24
Finished Aug 12 05:08:07 PM PDT 24
Peak memory 211296 kb
Host smart-8b749eba-739c-4a85-a135-e54e60349aef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1876745427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1876745427
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2121352531
Short name T197
Test name
Test status
Simulation time 421030897 ps
CPU time 17.89 seconds
Started Aug 12 05:08:01 PM PDT 24
Finished Aug 12 05:08:18 PM PDT 24
Peak memory 214220 kb
Host smart-64c22cf8-f61f-4565-84a8-770133f1c8cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121352531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2121352531
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1419762310
Short name T212
Test name
Test status
Simulation time 1338580305 ps
CPU time 7.61 seconds
Started Aug 12 05:07:19 PM PDT 24
Finished Aug 12 05:07:27 PM PDT 24
Peak memory 211476 kb
Host smart-c9e2d466-5a5f-446d-b654-1d3a82195d4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419762310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1419762310
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.727741047
Short name T263
Test name
Test status
Simulation time 21062790391 ps
CPU time 79.06 seconds
Started Aug 12 05:07:20 PM PDT 24
Finished Aug 12 05:08:40 PM PDT 24
Peak memory 233608 kb
Host smart-d4470f90-d4c9-44ae-8ede-4e0a73e347cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727741047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.727741047
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2875948559
Short name T310
Test name
Test status
Simulation time 252234204 ps
CPU time 11.07 seconds
Started Aug 12 05:07:21 PM PDT 24
Finished Aug 12 05:07:32 PM PDT 24
Peak memory 212252 kb
Host smart-78abecde-bde9-4dae-8419-7efcc937d7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875948559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2875948559
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2888671362
Short name T190
Test name
Test status
Simulation time 1104924575 ps
CPU time 6.65 seconds
Started Aug 12 05:07:20 PM PDT 24
Finished Aug 12 05:07:27 PM PDT 24
Peak memory 211448 kb
Host smart-3c9de277-b753-4db6-9b9c-e2d0343bde8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2888671362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2888671362
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3059586892
Short name T25
Test name
Test status
Simulation time 1271832648 ps
CPU time 106.46 seconds
Started Aug 12 05:07:22 PM PDT 24
Finished Aug 12 05:09:09 PM PDT 24
Peak memory 240744 kb
Host smart-d641ead8-248d-4422-9718-35a727e042f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059586892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3059586892
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2929562799
Short name T57
Test name
Test status
Simulation time 270867413 ps
CPU time 6.62 seconds
Started Aug 12 05:07:23 PM PDT 24
Finished Aug 12 05:07:30 PM PDT 24
Peak memory 211384 kb
Host smart-a6845335-e341-4128-902e-6eb1f60c2deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929562799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2929562799
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3372107761
Short name T12
Test name
Test status
Simulation time 2258169956 ps
CPU time 12.27 seconds
Started Aug 12 05:07:21 PM PDT 24
Finished Aug 12 05:07:33 PM PDT 24
Peak memory 213380 kb
Host smart-c601681d-1e90-4e6a-91b8-5d892a1803b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372107761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3372107761
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1699913031
Short name T245
Test name
Test status
Simulation time 126660121 ps
CPU time 5.22 seconds
Started Aug 12 05:08:00 PM PDT 24
Finished Aug 12 05:08:06 PM PDT 24
Peak memory 211512 kb
Host smart-23d00058-02fe-491a-80c9-e037a11bed08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699913031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1699913031
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.4260919294
Short name T316
Test name
Test status
Simulation time 1347537494 ps
CPU time 81.28 seconds
Started Aug 12 05:08:01 PM PDT 24
Finished Aug 12 05:09:23 PM PDT 24
Peak memory 226600 kb
Host smart-c34b85f2-e0de-43df-be9f-c306ebae83e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260919294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.4260919294
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.73270938
Short name T41
Test name
Test status
Simulation time 334075649 ps
CPU time 9.36 seconds
Started Aug 12 05:08:17 PM PDT 24
Finished Aug 12 05:08:26 PM PDT 24
Peak memory 212140 kb
Host smart-dafb570a-60f9-4048-87fa-dc2f5736a61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73270938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.73270938
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.696209307
Short name T61
Test name
Test status
Simulation time 377645060 ps
CPU time 5.19 seconds
Started Aug 12 05:08:00 PM PDT 24
Finished Aug 12 05:08:05 PM PDT 24
Peak memory 211420 kb
Host smart-8cbc054b-c0ca-4470-969d-e645ea865056
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=696209307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.696209307
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3923589854
Short name T130
Test name
Test status
Simulation time 302824099 ps
CPU time 13.94 seconds
Started Aug 12 05:08:02 PM PDT 24
Finished Aug 12 05:08:17 PM PDT 24
Peak memory 213804 kb
Host smart-569b1eb5-c63e-4702-9295-a38e21a8f2c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923589854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3923589854
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1472027483
Short name T188
Test name
Test status
Simulation time 332642233 ps
CPU time 4.25 seconds
Started Aug 12 05:08:01 PM PDT 24
Finished Aug 12 05:08:05 PM PDT 24
Peak memory 211564 kb
Host smart-c69e6a5d-df31-47d7-8841-4e8b922a6d6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472027483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1472027483
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2322002897
Short name T233
Test name
Test status
Simulation time 2031367267 ps
CPU time 120.86 seconds
Started Aug 12 05:07:59 PM PDT 24
Finished Aug 12 05:10:00 PM PDT 24
Peak memory 237728 kb
Host smart-93a13729-5253-44f0-abcd-964123fc1e38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322002897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2322002897
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1788502250
Short name T211
Test name
Test status
Simulation time 183201028 ps
CPU time 9.49 seconds
Started Aug 12 05:08:00 PM PDT 24
Finished Aug 12 05:08:09 PM PDT 24
Peak memory 212160 kb
Host smart-e57337cd-cc9e-4daf-8c61-f28a2f95bfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788502250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1788502250
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2890970153
Short name T250
Test name
Test status
Simulation time 99128971 ps
CPU time 5.63 seconds
Started Aug 12 05:08:03 PM PDT 24
Finished Aug 12 05:08:09 PM PDT 24
Peak memory 211432 kb
Host smart-92babf79-1880-4a24-9d25-c0523bfce1ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890970153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2890970153
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.438966457
Short name T255
Test name
Test status
Simulation time 428704627 ps
CPU time 19.98 seconds
Started Aug 12 05:08:02 PM PDT 24
Finished Aug 12 05:08:23 PM PDT 24
Peak memory 216296 kb
Host smart-833e09f1-1899-464c-8d8c-bdf43aebda86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438966457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.438966457
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.801664214
Short name T26
Test name
Test status
Simulation time 127921885 ps
CPU time 5.25 seconds
Started Aug 12 05:08:01 PM PDT 24
Finished Aug 12 05:08:06 PM PDT 24
Peak memory 211524 kb
Host smart-ac1b56a3-3483-4069-aa8d-d5d50d53accc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801664214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.801664214
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1028882189
Short name T203
Test name
Test status
Simulation time 4379578873 ps
CPU time 209.62 seconds
Started Aug 12 05:08:02 PM PDT 24
Finished Aug 12 05:11:32 PM PDT 24
Peak memory 214060 kb
Host smart-838d02ef-8301-4b7d-9022-2e6e168e8d30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028882189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1028882189
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3342504446
Short name T160
Test name
Test status
Simulation time 177229734 ps
CPU time 9.68 seconds
Started Aug 12 05:08:03 PM PDT 24
Finished Aug 12 05:08:13 PM PDT 24
Peak memory 212296 kb
Host smart-501b601e-1f3a-4c24-aab3-c3b272f12da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342504446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3342504446
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1037349929
Short name T163
Test name
Test status
Simulation time 99580445 ps
CPU time 5.87 seconds
Started Aug 12 05:08:03 PM PDT 24
Finished Aug 12 05:08:09 PM PDT 24
Peak memory 211432 kb
Host smart-c0866443-690f-46fe-b4d7-36d12b4e4d30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1037349929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1037349929
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1624060080
Short name T234
Test name
Test status
Simulation time 966331013 ps
CPU time 8.7 seconds
Started Aug 12 05:08:02 PM PDT 24
Finished Aug 12 05:08:11 PM PDT 24
Peak memory 212408 kb
Host smart-260aeb00-96b6-4205-a929-c7f549b9d8e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624060080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1624060080
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1896219718
Short name T282
Test name
Test status
Simulation time 378304650 ps
CPU time 4.38 seconds
Started Aug 12 05:08:01 PM PDT 24
Finished Aug 12 05:08:06 PM PDT 24
Peak memory 211460 kb
Host smart-dc2a9323-d7f4-4854-b870-5593136dadb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896219718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1896219718
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.438104496
Short name T164
Test name
Test status
Simulation time 4385874198 ps
CPU time 99.33 seconds
Started Aug 12 05:08:03 PM PDT 24
Finished Aug 12 05:09:42 PM PDT 24
Peak memory 212408 kb
Host smart-73a30a9e-95c4-4424-8d98-9b7931fc13b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438104496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.438104496
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2185567642
Short name T277
Test name
Test status
Simulation time 498964539 ps
CPU time 11.13 seconds
Started Aug 12 05:08:16 PM PDT 24
Finished Aug 12 05:08:28 PM PDT 24
Peak memory 212128 kb
Host smart-218382a3-3427-4ce5-8a3f-b8479ec1494c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185567642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2185567642
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2134938591
Short name T54
Test name
Test status
Simulation time 278171751 ps
CPU time 6.26 seconds
Started Aug 12 05:08:01 PM PDT 24
Finished Aug 12 05:08:08 PM PDT 24
Peak memory 211448 kb
Host smart-2920daab-b323-479e-911c-b0b651ba3e1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2134938591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2134938591
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.4190274302
Short name T306
Test name
Test status
Simulation time 812541760 ps
CPU time 16.53 seconds
Started Aug 12 05:08:03 PM PDT 24
Finished Aug 12 05:08:20 PM PDT 24
Peak memory 212276 kb
Host smart-9c7193e7-e894-42e5-9616-8ac94814f7de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190274302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.4190274302
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1008448572
Short name T315
Test name
Test status
Simulation time 834585898 ps
CPU time 4.21 seconds
Started Aug 12 05:08:19 PM PDT 24
Finished Aug 12 05:08:23 PM PDT 24
Peak memory 211484 kb
Host smart-f2bd39b7-b9f7-436c-9508-439005834b92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008448572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1008448572
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3221220024
Short name T140
Test name
Test status
Simulation time 1872172886 ps
CPU time 107.56 seconds
Started Aug 12 05:08:09 PM PDT 24
Finished Aug 12 05:09:56 PM PDT 24
Peak memory 212056 kb
Host smart-87f16d6e-9fc4-4ac4-bd9e-6856b334c123
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221220024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3221220024
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.592462235
Short name T40
Test name
Test status
Simulation time 251481876 ps
CPU time 9.46 seconds
Started Aug 12 05:08:09 PM PDT 24
Finished Aug 12 05:08:19 PM PDT 24
Peak memory 212160 kb
Host smart-6da61536-fd42-4cda-b8aa-781700ab8089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592462235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.592462235
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3660990602
Short name T166
Test name
Test status
Simulation time 201863956 ps
CPU time 5.74 seconds
Started Aug 12 05:08:08 PM PDT 24
Finished Aug 12 05:08:14 PM PDT 24
Peak memory 211320 kb
Host smart-cbd5fc02-6b3a-456c-87f5-7cfa08bf8e4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3660990602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3660990602
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.741011673
Short name T58
Test name
Test status
Simulation time 121054901 ps
CPU time 4.22 seconds
Started Aug 12 05:08:12 PM PDT 24
Finished Aug 12 05:08:16 PM PDT 24
Peak memory 211584 kb
Host smart-15c46709-02be-4cac-b33a-542f731df141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741011673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.741011673
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2567360991
Short name T224
Test name
Test status
Simulation time 7619142477 ps
CPU time 132.16 seconds
Started Aug 12 05:08:10 PM PDT 24
Finished Aug 12 05:10:23 PM PDT 24
Peak memory 234840 kb
Host smart-67b6563e-a05c-48fe-925c-e1880f4494f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567360991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2567360991
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1449455178
Short name T265
Test name
Test status
Simulation time 334366564 ps
CPU time 9.5 seconds
Started Aug 12 05:08:09 PM PDT 24
Finished Aug 12 05:08:19 PM PDT 24
Peak memory 212516 kb
Host smart-c590ae0a-fc41-484d-9330-dd5676d7672e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449455178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1449455178
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1445157637
Short name T116
Test name
Test status
Simulation time 184277831 ps
CPU time 5.44 seconds
Started Aug 12 05:08:08 PM PDT 24
Finished Aug 12 05:08:14 PM PDT 24
Peak memory 211436 kb
Host smart-d7eb471e-4869-4745-81b4-fe59b5ea3d6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1445157637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1445157637
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1047745232
Short name T17
Test name
Test status
Simulation time 1644049909 ps
CPU time 19.14 seconds
Started Aug 12 05:08:09 PM PDT 24
Finished Aug 12 05:08:28 PM PDT 24
Peak memory 214576 kb
Host smart-05fa64cd-c32e-40ad-90b2-0f1ee41d61b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047745232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1047745232
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2574430057
Short name T172
Test name
Test status
Simulation time 1566447772 ps
CPU time 5.23 seconds
Started Aug 12 05:08:09 PM PDT 24
Finished Aug 12 05:08:14 PM PDT 24
Peak memory 211488 kb
Host smart-8ddb448a-c495-4e7d-9e2d-24ef4370e01d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574430057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2574430057
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1903637269
Short name T286
Test name
Test status
Simulation time 254570763 ps
CPU time 11.31 seconds
Started Aug 12 05:08:09 PM PDT 24
Finished Aug 12 05:08:21 PM PDT 24
Peak memory 212216 kb
Host smart-5430ed9c-b7b3-41ca-99a2-f7b0b6b46522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903637269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1903637269
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1803686548
Short name T33
Test name
Test status
Simulation time 281092245 ps
CPU time 6.61 seconds
Started Aug 12 05:08:13 PM PDT 24
Finished Aug 12 05:08:19 PM PDT 24
Peak memory 211332 kb
Host smart-25cf48ed-ac9a-444d-b20d-61c0d8d8bf9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1803686548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1803686548
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.471638662
Short name T162
Test name
Test status
Simulation time 163120719 ps
CPU time 8.3 seconds
Started Aug 12 05:08:09 PM PDT 24
Finished Aug 12 05:08:17 PM PDT 24
Peak memory 212000 kb
Host smart-32c6d7fb-9df1-4ad6-ac03-76a7c3b46d9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471638662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.471638662
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2072052868
Short name T56
Test name
Test status
Simulation time 827474140 ps
CPU time 5.16 seconds
Started Aug 12 05:08:12 PM PDT 24
Finished Aug 12 05:08:17 PM PDT 24
Peak memory 211424 kb
Host smart-dea3f437-fc48-4ae2-ae51-21d6297832a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072052868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2072052868
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2804343917
Short name T39
Test name
Test status
Simulation time 10588248518 ps
CPU time 141.41 seconds
Started Aug 12 05:08:14 PM PDT 24
Finished Aug 12 05:10:36 PM PDT 24
Peak memory 228212 kb
Host smart-86ed7943-e4e2-4b7f-aafe-63646dec8403
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804343917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2804343917
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.772948294
Short name T278
Test name
Test status
Simulation time 730193410 ps
CPU time 9.54 seconds
Started Aug 12 05:08:11 PM PDT 24
Finished Aug 12 05:08:20 PM PDT 24
Peak memory 212152 kb
Host smart-f8815286-12d8-4c6e-b0da-647108a59b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772948294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.772948294
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2153334293
Short name T236
Test name
Test status
Simulation time 121909260 ps
CPU time 5.76 seconds
Started Aug 12 05:08:09 PM PDT 24
Finished Aug 12 05:08:15 PM PDT 24
Peak memory 211448 kb
Host smart-9d9f9736-daa7-452b-9c11-47e7651b9ea1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2153334293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2153334293
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1418056475
Short name T134
Test name
Test status
Simulation time 7681411149 ps
CPU time 32.25 seconds
Started Aug 12 05:08:14 PM PDT 24
Finished Aug 12 05:08:46 PM PDT 24
Peak memory 217340 kb
Host smart-78a1c9a6-5c92-43b7-9bb3-a610dd53c714
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418056475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1418056475
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3342741829
Short name T213
Test name
Test status
Simulation time 756012494 ps
CPU time 4.22 seconds
Started Aug 12 05:08:11 PM PDT 24
Finished Aug 12 05:08:16 PM PDT 24
Peak memory 211580 kb
Host smart-703bcd72-414d-47a9-b29e-60e674a0268f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342741829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3342741829
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2668515233
Short name T149
Test name
Test status
Simulation time 2737739441 ps
CPU time 128.49 seconds
Started Aug 12 05:08:08 PM PDT 24
Finished Aug 12 05:10:16 PM PDT 24
Peak memory 237732 kb
Host smart-85e5b16a-dff1-4911-befe-d9ec992782b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668515233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2668515233
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2185974339
Short name T222
Test name
Test status
Simulation time 448105989 ps
CPU time 11.45 seconds
Started Aug 12 05:08:08 PM PDT 24
Finished Aug 12 05:08:20 PM PDT 24
Peak memory 212288 kb
Host smart-c14af534-5a2b-45be-96a0-3e166e36331e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185974339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2185974339
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.857712752
Short name T273
Test name
Test status
Simulation time 544402874 ps
CPU time 6.16 seconds
Started Aug 12 05:08:09 PM PDT 24
Finished Aug 12 05:08:15 PM PDT 24
Peak memory 211384 kb
Host smart-d9a8eadb-eb30-4c9f-b40d-eacd86ff1434
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=857712752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.857712752
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2654920213
Short name T252
Test name
Test status
Simulation time 1003343380 ps
CPU time 13.53 seconds
Started Aug 12 05:08:10 PM PDT 24
Finished Aug 12 05:08:24 PM PDT 24
Peak memory 213996 kb
Host smart-04746a3e-0d87-4e35-84fa-fbe0e27f295b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654920213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2654920213
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2316894832
Short name T305
Test name
Test status
Simulation time 11122846357 ps
CPU time 129.51 seconds
Started Aug 12 05:08:13 PM PDT 24
Finished Aug 12 05:10:23 PM PDT 24
Peak memory 212856 kb
Host smart-0b10a287-e57b-4b92-bdb5-e35d3b4df356
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316894832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2316894832
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2330850688
Short name T225
Test name
Test status
Simulation time 251956419 ps
CPU time 11 seconds
Started Aug 12 05:08:11 PM PDT 24
Finished Aug 12 05:08:22 PM PDT 24
Peak memory 211564 kb
Host smart-ae6ee83d-ae35-4800-9b82-c0f83b0f0019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330850688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2330850688
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.820287211
Short name T208
Test name
Test status
Simulation time 103635089 ps
CPU time 5.91 seconds
Started Aug 12 05:08:11 PM PDT 24
Finished Aug 12 05:08:17 PM PDT 24
Peak memory 211448 kb
Host smart-e3154cfb-d696-4f22-9f91-3dc2571cda0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=820287211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.820287211
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3772175472
Short name T36
Test name
Test status
Simulation time 2013510626 ps
CPU time 35.29 seconds
Started Aug 12 05:08:13 PM PDT 24
Finished Aug 12 05:08:49 PM PDT 24
Peak memory 216352 kb
Host smart-ae9c9404-96d6-44d5-bb63-bb306374ede0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772175472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3772175472
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3116956929
Short name T269
Test name
Test status
Simulation time 88197602 ps
CPU time 4.31 seconds
Started Aug 12 05:07:29 PM PDT 24
Finished Aug 12 05:07:33 PM PDT 24
Peak memory 211564 kb
Host smart-570f004a-cbcf-483b-8a51-f5545b7f6f45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116956929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3116956929
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.225089467
Short name T46
Test name
Test status
Simulation time 1003991190 ps
CPU time 56.85 seconds
Started Aug 12 05:07:27 PM PDT 24
Finished Aug 12 05:08:24 PM PDT 24
Peak memory 227100 kb
Host smart-ffae30d2-aa50-4b8f-bb1e-173285b093fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225089467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.225089467
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3306679932
Short name T313
Test name
Test status
Simulation time 178642103 ps
CPU time 9.36 seconds
Started Aug 12 05:07:28 PM PDT 24
Finished Aug 12 05:07:38 PM PDT 24
Peak memory 212224 kb
Host smart-9bfc0213-2692-4f9e-9a3b-88d58c5f4331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306679932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3306679932
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.477757016
Short name T230
Test name
Test status
Simulation time 97689181 ps
CPU time 5.46 seconds
Started Aug 12 05:07:19 PM PDT 24
Finished Aug 12 05:07:25 PM PDT 24
Peak memory 211444 kb
Host smart-96ac24fa-53bc-4bef-b1b1-a772e76eebde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=477757016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.477757016
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1738476428
Short name T24
Test name
Test status
Simulation time 837193116 ps
CPU time 98.72 seconds
Started Aug 12 05:07:29 PM PDT 24
Finished Aug 12 05:09:08 PM PDT 24
Peak memory 236708 kb
Host smart-40178dab-338a-48ed-853a-461ebf6fd8b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738476428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1738476428
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.851445473
Short name T81
Test name
Test status
Simulation time 279333729 ps
CPU time 6.57 seconds
Started Aug 12 05:07:19 PM PDT 24
Finished Aug 12 05:07:26 PM PDT 24
Peak memory 211632 kb
Host smart-fd3562ae-ed93-4573-87b9-f41fa0f367b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851445473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.851445473
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.589207399
Short name T18
Test name
Test status
Simulation time 322149979 ps
CPU time 11.49 seconds
Started Aug 12 05:07:21 PM PDT 24
Finished Aug 12 05:07:32 PM PDT 24
Peak memory 212412 kb
Host smart-97b312a3-3322-4b68-9dd9-6d23c78ab817
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589207399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.589207399
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1182631427
Short name T285
Test name
Test status
Simulation time 521666508 ps
CPU time 5.13 seconds
Started Aug 12 05:08:11 PM PDT 24
Finished Aug 12 05:08:17 PM PDT 24
Peak memory 211592 kb
Host smart-0d987b67-fa33-4d4c-b881-89e8bc2d4203
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182631427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1182631427
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4199350392
Short name T198
Test name
Test status
Simulation time 1498386322 ps
CPU time 84.2 seconds
Started Aug 12 05:08:19 PM PDT 24
Finished Aug 12 05:09:43 PM PDT 24
Peak memory 236612 kb
Host smart-c7c550ad-f647-4bd3-b9c4-d243a8fecb80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199350392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4199350392
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3939995313
Short name T289
Test name
Test status
Simulation time 340901439 ps
CPU time 9.41 seconds
Started Aug 12 05:08:09 PM PDT 24
Finished Aug 12 05:08:19 PM PDT 24
Peak memory 212228 kb
Host smart-62554f9d-1739-4241-bad9-04d5064eb302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939995313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3939995313
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3770238377
Short name T102
Test name
Test status
Simulation time 135965766 ps
CPU time 6.28 seconds
Started Aug 12 05:08:08 PM PDT 24
Finished Aug 12 05:08:14 PM PDT 24
Peak memory 211344 kb
Host smart-4c5244b8-095a-41ff-ae0e-b1691d4c48d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3770238377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3770238377
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.276716593
Short name T243
Test name
Test status
Simulation time 1336651146 ps
CPU time 8.57 seconds
Started Aug 12 05:08:12 PM PDT 24
Finished Aug 12 05:08:21 PM PDT 24
Peak memory 211284 kb
Host smart-79ee307d-a8bd-4cb1-8379-7447258c49d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276716593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.276716593
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.24142467
Short name T146
Test name
Test status
Simulation time 126909389 ps
CPU time 5.16 seconds
Started Aug 12 05:08:19 PM PDT 24
Finished Aug 12 05:08:24 PM PDT 24
Peak memory 211484 kb
Host smart-6b7e5d86-6216-4dd1-8429-f4dee5cba53c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24142467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.24142467
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2132391786
Short name T183
Test name
Test status
Simulation time 1346108959 ps
CPU time 90.62 seconds
Started Aug 12 05:08:12 PM PDT 24
Finished Aug 12 05:09:43 PM PDT 24
Peak memory 234728 kb
Host smart-9935e152-d778-4c9e-8fba-80443c9b2a5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132391786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2132391786
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2320101730
Short name T271
Test name
Test status
Simulation time 1040890926 ps
CPU time 11.21 seconds
Started Aug 12 05:08:10 PM PDT 24
Finished Aug 12 05:08:21 PM PDT 24
Peak memory 212176 kb
Host smart-f24c8696-f812-4fe8-82bf-9d152af657db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320101730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2320101730
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3529660549
Short name T10
Test name
Test status
Simulation time 98743777 ps
CPU time 6.07 seconds
Started Aug 12 05:08:13 PM PDT 24
Finished Aug 12 05:08:19 PM PDT 24
Peak memory 211428 kb
Host smart-c8f44cdd-034c-4dbe-998c-3dce6b15ca11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3529660549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3529660549
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1195533744
Short name T173
Test name
Test status
Simulation time 403598256 ps
CPU time 18.87 seconds
Started Aug 12 05:08:12 PM PDT 24
Finished Aug 12 05:08:32 PM PDT 24
Peak memory 214628 kb
Host smart-f22faa84-3708-442d-bac2-de5e90e64562
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195533744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1195533744
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3751248831
Short name T135
Test name
Test status
Simulation time 500036517 ps
CPU time 5.21 seconds
Started Aug 12 05:08:19 PM PDT 24
Finished Aug 12 05:08:24 PM PDT 24
Peak memory 211484 kb
Host smart-88965292-5331-49af-8979-14470a6e1253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751248831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3751248831
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3940174591
Short name T38
Test name
Test status
Simulation time 2295357521 ps
CPU time 106.15 seconds
Started Aug 12 05:08:11 PM PDT 24
Finished Aug 12 05:09:58 PM PDT 24
Peak memory 233588 kb
Host smart-b9b9df89-6869-40fa-8d5e-c1c366322bd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940174591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3940174591
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3989860726
Short name T34
Test name
Test status
Simulation time 1034784098 ps
CPU time 11.21 seconds
Started Aug 12 05:08:11 PM PDT 24
Finished Aug 12 05:08:23 PM PDT 24
Peak memory 212300 kb
Host smart-e2ee7e08-4577-4544-a9f0-84745798175c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989860726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3989860726
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3171457809
Short name T194
Test name
Test status
Simulation time 507404389 ps
CPU time 6.13 seconds
Started Aug 12 05:08:13 PM PDT 24
Finished Aug 12 05:08:19 PM PDT 24
Peak memory 211332 kb
Host smart-e0e172f5-c53c-4bd3-b949-3305fb1e61a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3171457809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3171457809
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1166426595
Short name T31
Test name
Test status
Simulation time 1767055705 ps
CPU time 13.24 seconds
Started Aug 12 05:08:12 PM PDT 24
Finished Aug 12 05:08:25 PM PDT 24
Peak memory 214908 kb
Host smart-e5ec1093-6b45-476a-abf7-4629156a84d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166426595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1166426595
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2256410153
Short name T141
Test name
Test status
Simulation time 463141503 ps
CPU time 5.24 seconds
Started Aug 12 05:08:20 PM PDT 24
Finished Aug 12 05:08:25 PM PDT 24
Peak memory 211596 kb
Host smart-dee6dfca-84c9-4354-8b62-ff99589fea22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256410153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2256410153
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1862374941
Short name T184
Test name
Test status
Simulation time 36557128885 ps
CPU time 131.95 seconds
Started Aug 12 05:08:20 PM PDT 24
Finished Aug 12 05:10:32 PM PDT 24
Peak memory 213092 kb
Host smart-2fff7da3-b77e-4815-af24-64849534b307
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862374941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1862374941
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1612478714
Short name T284
Test name
Test status
Simulation time 977931153 ps
CPU time 9.54 seconds
Started Aug 12 05:08:20 PM PDT 24
Finished Aug 12 05:08:30 PM PDT 24
Peak memory 212272 kb
Host smart-2cef5b2a-322f-4058-a0c4-ee8fd9d5ce8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612478714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1612478714
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3785372631
Short name T175
Test name
Test status
Simulation time 140346086 ps
CPU time 6.53 seconds
Started Aug 12 05:08:23 PM PDT 24
Finished Aug 12 05:08:30 PM PDT 24
Peak memory 211448 kb
Host smart-43ff0e24-1650-41aa-9e3a-6e59d84baf8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3785372631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3785372631
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.855420792
Short name T82
Test name
Test status
Simulation time 456081257 ps
CPU time 14.32 seconds
Started Aug 12 05:08:20 PM PDT 24
Finished Aug 12 05:08:34 PM PDT 24
Peak memory 213652 kb
Host smart-828186b1-80c4-43c8-8503-ecaa3d74e144
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855420792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.855420792
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1063720151
Short name T16
Test name
Test status
Simulation time 3310100075 ps
CPU time 135.39 seconds
Started Aug 12 05:08:18 PM PDT 24
Finished Aug 12 05:10:33 PM PDT 24
Peak memory 221868 kb
Host smart-28357415-7204-4def-82c8-913fe31218d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063720151 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1063720151
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2419613929
Short name T68
Test name
Test status
Simulation time 89865640 ps
CPU time 4.39 seconds
Started Aug 12 05:08:24 PM PDT 24
Finished Aug 12 05:08:28 PM PDT 24
Peak memory 211512 kb
Host smart-ac02f8ca-fd00-4a5b-90d3-0c40faa6f0f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419613929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2419613929
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2066506247
Short name T204
Test name
Test status
Simulation time 8065176280 ps
CPU time 104.5 seconds
Started Aug 12 05:08:18 PM PDT 24
Finished Aug 12 05:10:03 PM PDT 24
Peak memory 237464 kb
Host smart-2157ad6a-4b7f-4e9f-a789-07df2f5eda92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066506247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2066506247
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3964009455
Short name T206
Test name
Test status
Simulation time 789954832 ps
CPU time 9.39 seconds
Started Aug 12 05:08:17 PM PDT 24
Finished Aug 12 05:08:27 PM PDT 24
Peak memory 212504 kb
Host smart-806288d5-c8d7-4abf-a20f-0bd4445bfc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964009455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3964009455
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.781165129
Short name T205
Test name
Test status
Simulation time 268185148 ps
CPU time 6.23 seconds
Started Aug 12 05:08:19 PM PDT 24
Finished Aug 12 05:08:26 PM PDT 24
Peak memory 211340 kb
Host smart-e2c45309-564e-4489-b62d-206816ac557c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=781165129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.781165129
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3744322992
Short name T157
Test name
Test status
Simulation time 198194488 ps
CPU time 6.86 seconds
Started Aug 12 05:08:16 PM PDT 24
Finished Aug 12 05:08:23 PM PDT 24
Peak memory 211344 kb
Host smart-69a5fc88-987f-462d-ae8c-cd3fd02bf914
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744322992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3744322992
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3605438555
Short name T144
Test name
Test status
Simulation time 930386271 ps
CPU time 4.33 seconds
Started Aug 12 05:08:19 PM PDT 24
Finished Aug 12 05:08:23 PM PDT 24
Peak memory 211588 kb
Host smart-857b522d-2fe6-4dff-9f7a-0df49ed5b3fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605438555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3605438555
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.525401008
Short name T290
Test name
Test status
Simulation time 15676165019 ps
CPU time 177.43 seconds
Started Aug 12 05:08:21 PM PDT 24
Finished Aug 12 05:11:19 PM PDT 24
Peak memory 234880 kb
Host smart-40410e88-1cd8-424e-bfd8-1dd88fdbf927
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525401008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.525401008
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1588218231
Short name T300
Test name
Test status
Simulation time 261132070 ps
CPU time 11.28 seconds
Started Aug 12 05:08:21 PM PDT 24
Finished Aug 12 05:08:32 PM PDT 24
Peak memory 212340 kb
Host smart-ab42a2fd-0852-4a30-88fe-224467f19429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588218231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1588218231
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2661259378
Short name T170
Test name
Test status
Simulation time 376316590 ps
CPU time 5.27 seconds
Started Aug 12 05:08:20 PM PDT 24
Finished Aug 12 05:08:26 PM PDT 24
Peak memory 211400 kb
Host smart-4bc1328c-83ea-43ee-99b1-69b3711ad0f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2661259378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2661259378
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2266065825
Short name T44
Test name
Test status
Simulation time 788136252 ps
CPU time 18.74 seconds
Started Aug 12 05:08:17 PM PDT 24
Finished Aug 12 05:08:36 PM PDT 24
Peak memory 213928 kb
Host smart-1eca1979-2989-42e9-91dd-89b74a52ed84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266065825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2266065825
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2746900704
Short name T301
Test name
Test status
Simulation time 86443634 ps
CPU time 4.3 seconds
Started Aug 12 05:08:21 PM PDT 24
Finished Aug 12 05:08:26 PM PDT 24
Peak memory 211620 kb
Host smart-648a0fe1-fcae-4243-b554-451c18a3307e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746900704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2746900704
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4221507961
Short name T13
Test name
Test status
Simulation time 2504315976 ps
CPU time 74.9 seconds
Started Aug 12 05:08:22 PM PDT 24
Finished Aug 12 05:09:37 PM PDT 24
Peak memory 236652 kb
Host smart-c4ecb8b4-1f9f-478a-9989-2f9521a59ffd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221507961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4221507961
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1823855178
Short name T1
Test name
Test status
Simulation time 670896992 ps
CPU time 9.53 seconds
Started Aug 12 05:08:18 PM PDT 24
Finished Aug 12 05:08:28 PM PDT 24
Peak memory 212512 kb
Host smart-5c421a56-81b0-409d-a8c2-ac1046aa85a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823855178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1823855178
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.255949568
Short name T165
Test name
Test status
Simulation time 139723070 ps
CPU time 6.78 seconds
Started Aug 12 05:08:19 PM PDT 24
Finished Aug 12 05:08:25 PM PDT 24
Peak memory 211376 kb
Host smart-5a14cdf0-3235-4973-9917-ec2de68c888a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=255949568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.255949568
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2510285967
Short name T191
Test name
Test status
Simulation time 303934932 ps
CPU time 19.54 seconds
Started Aug 12 05:08:20 PM PDT 24
Finished Aug 12 05:08:40 PM PDT 24
Peak memory 212808 kb
Host smart-e04841d0-f532-40c7-80d5-b929b0975432
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510285967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2510285967
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.579176335
Short name T299
Test name
Test status
Simulation time 172644857 ps
CPU time 4.37 seconds
Started Aug 12 05:08:19 PM PDT 24
Finished Aug 12 05:08:23 PM PDT 24
Peak memory 211588 kb
Host smart-53da2b0d-7392-421c-a981-9091d76531ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579176335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.579176335
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2611633465
Short name T150
Test name
Test status
Simulation time 1620539472 ps
CPU time 98.26 seconds
Started Aug 12 05:08:19 PM PDT 24
Finished Aug 12 05:09:58 PM PDT 24
Peak memory 237756 kb
Host smart-9d6bf89a-faa3-4e64-a6bf-063086abfba3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611633465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2611633465
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.648807275
Short name T60
Test name
Test status
Simulation time 508613246 ps
CPU time 11.36 seconds
Started Aug 12 05:08:17 PM PDT 24
Finished Aug 12 05:08:29 PM PDT 24
Peak memory 212164 kb
Host smart-8920799b-6a2a-44c9-a065-16cfb2734a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648807275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.648807275
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3751232101
Short name T314
Test name
Test status
Simulation time 358733083 ps
CPU time 5.35 seconds
Started Aug 12 05:08:19 PM PDT 24
Finished Aug 12 05:08:25 PM PDT 24
Peak memory 211364 kb
Host smart-45418691-c24a-4acd-baa0-a8a92cc369da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3751232101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3751232101
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2441906176
Short name T297
Test name
Test status
Simulation time 3994458013 ps
CPU time 16.81 seconds
Started Aug 12 05:08:19 PM PDT 24
Finished Aug 12 05:08:36 PM PDT 24
Peak memory 213872 kb
Host smart-43b2a120-316a-4cd3-b9a7-166dd3b7c473
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441906176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2441906176
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2077952349
Short name T66
Test name
Test status
Simulation time 1893085447 ps
CPU time 7.59 seconds
Started Aug 12 05:08:18 PM PDT 24
Finished Aug 12 05:08:25 PM PDT 24
Peak memory 211512 kb
Host smart-9a7d7e19-8c98-46eb-aa33-80390d0cfd76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077952349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2077952349
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1439848330
Short name T37
Test name
Test status
Simulation time 1793669297 ps
CPU time 111.96 seconds
Started Aug 12 05:08:23 PM PDT 24
Finished Aug 12 05:10:15 PM PDT 24
Peak memory 228496 kb
Host smart-aee3ddff-cd58-4265-8a5d-75ca920dff99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439848330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1439848330
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2071714558
Short name T279
Test name
Test status
Simulation time 666969359 ps
CPU time 9.7 seconds
Started Aug 12 05:08:23 PM PDT 24
Finished Aug 12 05:08:33 PM PDT 24
Peak memory 212284 kb
Host smart-13ef62da-ae4f-47e0-9983-a671e6341776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071714558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2071714558
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2274912727
Short name T207
Test name
Test status
Simulation time 93738201 ps
CPU time 5.34 seconds
Started Aug 12 05:08:18 PM PDT 24
Finished Aug 12 05:08:23 PM PDT 24
Peak memory 211428 kb
Host smart-e98470e0-0d44-4ae3-8ae5-529450a0ea5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2274912727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2274912727
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2317219252
Short name T127
Test name
Test status
Simulation time 222613609 ps
CPU time 7.22 seconds
Started Aug 12 05:08:19 PM PDT 24
Finished Aug 12 05:08:26 PM PDT 24
Peak memory 211344 kb
Host smart-85cab5e8-c563-463a-bd3c-5bcb03566f80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317219252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2317219252
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.854744353
Short name T179
Test name
Test status
Simulation time 127051301 ps
CPU time 5.23 seconds
Started Aug 12 05:08:20 PM PDT 24
Finished Aug 12 05:08:25 PM PDT 24
Peak memory 211560 kb
Host smart-b41eb430-2e45-4e43-af80-37e66391dd20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854744353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.854744353
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2155083226
Short name T303
Test name
Test status
Simulation time 44215282668 ps
CPU time 179.03 seconds
Started Aug 12 05:08:19 PM PDT 24
Finished Aug 12 05:11:18 PM PDT 24
Peak memory 212836 kb
Host smart-7e052d2d-3fe1-461e-8ec5-077106572f7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155083226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2155083226
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2548499993
Short name T228
Test name
Test status
Simulation time 1040456441 ps
CPU time 16.32 seconds
Started Aug 12 05:08:21 PM PDT 24
Finished Aug 12 05:08:38 PM PDT 24
Peak memory 212504 kb
Host smart-4b7cdf23-6c4b-411c-b4e7-1a9b0171e42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548499993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2548499993
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.345508229
Short name T275
Test name
Test status
Simulation time 351562126 ps
CPU time 6.68 seconds
Started Aug 12 05:08:19 PM PDT 24
Finished Aug 12 05:08:26 PM PDT 24
Peak memory 211316 kb
Host smart-a6d75bc5-a9c6-47e7-9e84-a6d43f451cab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=345508229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.345508229
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1238065410
Short name T145
Test name
Test status
Simulation time 1083726889 ps
CPU time 15.79 seconds
Started Aug 12 05:08:19 PM PDT 24
Finished Aug 12 05:08:35 PM PDT 24
Peak memory 213744 kb
Host smart-26cb8488-8137-4dd4-975e-1c51832a6844
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238065410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1238065410
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2377749275
Short name T65
Test name
Test status
Simulation time 261990663 ps
CPU time 5.01 seconds
Started Aug 12 05:07:30 PM PDT 24
Finished Aug 12 05:07:35 PM PDT 24
Peak memory 211508 kb
Host smart-bd62eccf-eaa9-4c50-aa8e-7c1fb4b68d53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377749275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2377749275
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3555870311
Short name T147
Test name
Test status
Simulation time 4411325991 ps
CPU time 125.02 seconds
Started Aug 12 05:07:30 PM PDT 24
Finished Aug 12 05:09:35 PM PDT 24
Peak memory 225408 kb
Host smart-ea9e569d-b5d0-469d-ba41-d8c9211d71b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555870311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3555870311
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3906607612
Short name T171
Test name
Test status
Simulation time 3094499851 ps
CPU time 10.72 seconds
Started Aug 12 05:07:32 PM PDT 24
Finished Aug 12 05:07:43 PM PDT 24
Peak memory 212528 kb
Host smart-e13f9431-ab8f-4344-8d07-2248915c8cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906607612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3906607612
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3409220141
Short name T244
Test name
Test status
Simulation time 711495250 ps
CPU time 5.49 seconds
Started Aug 12 05:07:30 PM PDT 24
Finished Aug 12 05:07:36 PM PDT 24
Peak memory 211352 kb
Host smart-ad62ebdc-76da-4e4b-a87e-0774a3a26e9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3409220141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3409220141
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1626116811
Short name T210
Test name
Test status
Simulation time 344287690 ps
CPU time 6.47 seconds
Started Aug 12 05:07:31 PM PDT 24
Finished Aug 12 05:07:38 PM PDT 24
Peak memory 211360 kb
Host smart-0ce18ebe-49e3-4c26-b212-23351da7650f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626116811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1626116811
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2615379390
Short name T178
Test name
Test status
Simulation time 280716836 ps
CPU time 13.96 seconds
Started Aug 12 05:07:27 PM PDT 24
Finished Aug 12 05:07:41 PM PDT 24
Peak memory 213952 kb
Host smart-a6454066-6af8-4c6a-ae83-52c8fa2da1b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615379390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2615379390
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3639254333
Short name T28
Test name
Test status
Simulation time 348292812 ps
CPU time 4.24 seconds
Started Aug 12 05:07:29 PM PDT 24
Finished Aug 12 05:07:34 PM PDT 24
Peak memory 211576 kb
Host smart-a8572a0f-70a0-4b1c-8705-75fb7465f36d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639254333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3639254333
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2142730939
Short name T151
Test name
Test status
Simulation time 5388166095 ps
CPU time 87.92 seconds
Started Aug 12 05:07:28 PM PDT 24
Finished Aug 12 05:08:56 PM PDT 24
Peak memory 212832 kb
Host smart-8495fa32-afb4-4065-8533-73c2d6c2675f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142730939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2142730939
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.4269894398
Short name T5
Test name
Test status
Simulation time 256609064 ps
CPU time 11.38 seconds
Started Aug 12 05:07:27 PM PDT 24
Finished Aug 12 05:07:39 PM PDT 24
Peak memory 212332 kb
Host smart-7bc5a700-3c45-4079-b81e-1e7c97ca1a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269894398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.4269894398
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2702195804
Short name T267
Test name
Test status
Simulation time 779520933 ps
CPU time 8.52 seconds
Started Aug 12 05:07:28 PM PDT 24
Finished Aug 12 05:07:37 PM PDT 24
Peak memory 211392 kb
Host smart-5cae3a7f-e2c5-4f5e-8b21-af536515fd56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2702195804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2702195804
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1609482361
Short name T193
Test name
Test status
Simulation time 143493573 ps
CPU time 6.32 seconds
Started Aug 12 05:07:30 PM PDT 24
Finished Aug 12 05:07:36 PM PDT 24
Peak memory 211352 kb
Host smart-9c48049d-7dad-4f4e-af93-48a2b0bc202b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609482361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1609482361
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3093436940
Short name T292
Test name
Test status
Simulation time 453979502 ps
CPU time 18.32 seconds
Started Aug 12 05:07:33 PM PDT 24
Finished Aug 12 05:07:51 PM PDT 24
Peak memory 215032 kb
Host smart-4aae6025-0ff4-48aa-8363-2e6cc0e77ac6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093436940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3093436940
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1609909498
Short name T27
Test name
Test status
Simulation time 169027312 ps
CPU time 4.33 seconds
Started Aug 12 05:07:28 PM PDT 24
Finished Aug 12 05:07:32 PM PDT 24
Peak memory 211572 kb
Host smart-57e73965-9c72-4d70-9e29-20892e10e62b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609909498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1609909498
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1693135757
Short name T232
Test name
Test status
Simulation time 4396976522 ps
CPU time 108.81 seconds
Started Aug 12 05:07:30 PM PDT 24
Finished Aug 12 05:09:19 PM PDT 24
Peak memory 237472 kb
Host smart-a14dd8a8-c826-4319-801d-be570813a92e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693135757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1693135757
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2395147581
Short name T32
Test name
Test status
Simulation time 1036118861 ps
CPU time 11.05 seconds
Started Aug 12 05:07:27 PM PDT 24
Finished Aug 12 05:07:39 PM PDT 24
Peak memory 212132 kb
Host smart-45a015d5-4a9a-4b24-8931-ddecfbc7c1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395147581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2395147581
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.686903082
Short name T119
Test name
Test status
Simulation time 491520406 ps
CPU time 6.33 seconds
Started Aug 12 05:07:29 PM PDT 24
Finished Aug 12 05:07:36 PM PDT 24
Peak memory 211456 kb
Host smart-79e952dd-8f24-4f21-b8c7-3d17111d07c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=686903082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.686903082
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3752646194
Short name T262
Test name
Test status
Simulation time 135927936 ps
CPU time 6.48 seconds
Started Aug 12 05:07:27 PM PDT 24
Finished Aug 12 05:07:34 PM PDT 24
Peak memory 211252 kb
Host smart-2b2eaa84-c206-44b1-a18f-52de3b3cb664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752646194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3752646194
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2075760292
Short name T218
Test name
Test status
Simulation time 520130829 ps
CPU time 12.67 seconds
Started Aug 12 05:07:29 PM PDT 24
Finished Aug 12 05:07:42 PM PDT 24
Peak memory 214728 kb
Host smart-36ce6764-2c03-4083-a6fc-75a732c261b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075760292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2075760292
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4201976235
Short name T223
Test name
Test status
Simulation time 1982674634 ps
CPU time 7.25 seconds
Started Aug 12 05:07:30 PM PDT 24
Finished Aug 12 05:07:37 PM PDT 24
Peak memory 211504 kb
Host smart-38eb326f-8cda-45c9-9306-b980d0facea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201976235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4201976235
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.337704246
Short name T20
Test name
Test status
Simulation time 1848896790 ps
CPU time 109.41 seconds
Started Aug 12 05:07:26 PM PDT 24
Finished Aug 12 05:09:16 PM PDT 24
Peak memory 236892 kb
Host smart-27cd140b-8c6e-48e3-b6f2-fbd7a0d3e38b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337704246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.337704246
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3536161921
Short name T55
Test name
Test status
Simulation time 1394599431 ps
CPU time 9.57 seconds
Started Aug 12 05:07:30 PM PDT 24
Finished Aug 12 05:07:40 PM PDT 24
Peak memory 212324 kb
Host smart-56731b85-c797-4d30-bb98-ae77d0d736bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536161921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3536161921
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1010172231
Short name T114
Test name
Test status
Simulation time 145611630 ps
CPU time 6.34 seconds
Started Aug 12 05:07:33 PM PDT 24
Finished Aug 12 05:07:39 PM PDT 24
Peak memory 211476 kb
Host smart-a04a1caa-a462-457a-8abe-71bbda9b8838
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1010172231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1010172231
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1711182448
Short name T307
Test name
Test status
Simulation time 531517294 ps
CPU time 6.29 seconds
Started Aug 12 05:07:28 PM PDT 24
Finished Aug 12 05:07:35 PM PDT 24
Peak memory 211424 kb
Host smart-0033ab12-3240-4f3d-90dc-52e8b0d3d54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711182448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1711182448
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3819011548
Short name T209
Test name
Test status
Simulation time 141389212 ps
CPU time 9.46 seconds
Started Aug 12 05:07:31 PM PDT 24
Finished Aug 12 05:07:41 PM PDT 24
Peak memory 211368 kb
Host smart-0b34838d-ec09-4c9e-9461-f365b05ff761
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819011548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3819011548
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2904690217
Short name T288
Test name
Test status
Simulation time 620001010 ps
CPU time 4.93 seconds
Started Aug 12 05:07:37 PM PDT 24
Finished Aug 12 05:07:42 PM PDT 24
Peak memory 211576 kb
Host smart-87f0dff0-5215-4c16-8272-c37909e69b61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904690217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2904690217
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1397243925
Short name T217
Test name
Test status
Simulation time 3392094455 ps
CPU time 149.52 seconds
Started Aug 12 05:07:29 PM PDT 24
Finished Aug 12 05:09:59 PM PDT 24
Peak memory 228600 kb
Host smart-408b4649-3f2c-42f3-bb84-9fec048f04d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397243925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1397243925
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4225785308
Short name T195
Test name
Test status
Simulation time 722159798 ps
CPU time 9.51 seconds
Started Aug 12 05:07:38 PM PDT 24
Finished Aug 12 05:07:47 PM PDT 24
Peak memory 212452 kb
Host smart-a3623ba9-a24a-428c-8362-0881433de691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225785308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4225785308
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3755744746
Short name T308
Test name
Test status
Simulation time 1884869911 ps
CPU time 6.45 seconds
Started Aug 12 05:07:31 PM PDT 24
Finished Aug 12 05:07:37 PM PDT 24
Peak memory 211476 kb
Host smart-72576d5f-e7f0-4aa0-9699-a00e58b7b69e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3755744746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3755744746
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1274798860
Short name T294
Test name
Test status
Simulation time 539281980 ps
CPU time 6.59 seconds
Started Aug 12 05:07:27 PM PDT 24
Finished Aug 12 05:07:33 PM PDT 24
Peak memory 211340 kb
Host smart-758ca048-28a7-4ad3-baea-9b3f2acdf4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274798860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1274798860
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2332821909
Short name T264
Test name
Test status
Simulation time 1996680393 ps
CPU time 11.78 seconds
Started Aug 12 05:07:27 PM PDT 24
Finished Aug 12 05:07:39 PM PDT 24
Peak memory 214344 kb
Host smart-dc481201-827a-4e40-8ae0-ed7ed087e42d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332821909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2332821909
Directory /workspace/9.rom_ctrl_stress_all/latest
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