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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.22 96.89 91.85 97.67 100.00 98.28 97.45 98.37


Total test records in report: 412
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T306 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.157943180 Aug 13 06:44:25 PM PDT 24 Aug 13 06:44:31 PM PDT 24 145811292 ps
T307 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1931334505 Aug 13 06:43:53 PM PDT 24 Aug 13 06:43:58 PM PDT 24 382489515 ps
T308 /workspace/coverage/default/44.rom_ctrl_alert_test.1743533768 Aug 13 06:44:33 PM PDT 24 Aug 13 06:44:38 PM PDT 24 87302336 ps
T309 /workspace/coverage/default/44.rom_ctrl_stress_all.2288628138 Aug 13 06:44:29 PM PDT 24 Aug 13 06:44:45 PM PDT 24 276257583 ps
T310 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2662000505 Aug 13 06:44:46 PM PDT 24 Aug 13 06:47:36 PM PDT 24 13828582809 ps
T311 /workspace/coverage/default/34.rom_ctrl_alert_test.2321785113 Aug 13 06:44:33 PM PDT 24 Aug 13 06:44:38 PM PDT 24 132799744 ps
T312 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.286635017 Aug 13 06:44:32 PM PDT 24 Aug 13 06:46:20 PM PDT 24 3126839140 ps
T313 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1740030793 Aug 13 06:45:01 PM PDT 24 Aug 13 06:46:18 PM PDT 24 3938852724 ps
T314 /workspace/coverage/default/35.rom_ctrl_stress_all.121210810 Aug 13 06:45:04 PM PDT 24 Aug 13 06:45:24 PM PDT 24 4471829489 ps
T315 /workspace/coverage/default/13.rom_ctrl_stress_all.3438371748 Aug 13 06:44:29 PM PDT 24 Aug 13 06:44:41 PM PDT 24 214827620 ps
T316 /workspace/coverage/default/33.rom_ctrl_stress_all.2841096916 Aug 13 06:44:28 PM PDT 24 Aug 13 06:44:41 PM PDT 24 833613572 ps
T317 /workspace/coverage/default/2.rom_ctrl_stress_all.3212150395 Aug 13 06:44:15 PM PDT 24 Aug 13 06:44:29 PM PDT 24 2266569969 ps
T29 /workspace/coverage/default/3.rom_ctrl_sec_cm.3683391484 Aug 13 06:44:15 PM PDT 24 Aug 13 06:45:11 PM PDT 24 637778892 ps
T318 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.434902454 Aug 13 06:44:39 PM PDT 24 Aug 13 06:44:50 PM PDT 24 861586210 ps
T319 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.742537098 Aug 13 06:44:07 PM PDT 24 Aug 13 06:46:25 PM PDT 24 8918702023 ps
T320 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3144480802 Aug 13 06:45:02 PM PDT 24 Aug 13 06:45:14 PM PDT 24 1089350437 ps
T321 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1266844637 Aug 13 06:44:35 PM PDT 24 Aug 13 06:46:47 PM PDT 24 2259916535 ps
T70 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3453706169 Aug 13 06:26:31 PM PDT 24 Aug 13 06:26:40 PM PDT 24 571327305 ps
T71 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3222194823 Aug 13 06:26:35 PM PDT 24 Aug 13 06:26:40 PM PDT 24 272775621 ps
T72 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2951753033 Aug 13 06:26:30 PM PDT 24 Aug 13 06:26:52 PM PDT 24 1919207387 ps
T79 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.494459264 Aug 13 06:26:42 PM PDT 24 Aug 13 06:26:47 PM PDT 24 127061547 ps
T80 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3690975994 Aug 13 06:26:50 PM PDT 24 Aug 13 06:26:57 PM PDT 24 490535630 ps
T27 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3150244053 Aug 13 06:26:24 PM PDT 24 Aug 13 06:27:00 PM PDT 24 1597459849 ps
T54 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2077415503 Aug 13 06:26:46 PM PDT 24 Aug 13 06:26:52 PM PDT 24 149383416 ps
T81 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.801992509 Aug 13 06:26:38 PM PDT 24 Aug 13 06:26:43 PM PDT 24 136086583 ps
T322 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1844603415 Aug 13 06:26:31 PM PDT 24 Aug 13 06:26:35 PM PDT 24 86495955 ps
T82 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2788159139 Aug 13 06:26:35 PM PDT 24 Aug 13 06:26:40 PM PDT 24 403542484 ps
T323 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.338660340 Aug 13 06:26:25 PM PDT 24 Aug 13 06:26:31 PM PDT 24 688591629 ps
T83 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3909022427 Aug 13 06:26:20 PM PDT 24 Aug 13 06:26:51 PM PDT 24 12521745239 ps
T84 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.4178636612 Aug 13 06:26:34 PM PDT 24 Aug 13 06:26:56 PM PDT 24 551986365 ps
T55 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3009247679 Aug 13 06:26:31 PM PDT 24 Aug 13 06:27:09 PM PDT 24 165725815 ps
T85 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2156306718 Aug 13 06:26:35 PM PDT 24 Aug 13 06:26:39 PM PDT 24 172226852 ps
T56 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4138784313 Aug 13 06:26:43 PM PDT 24 Aug 13 06:28:00 PM PDT 24 504360523 ps
T324 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2644499817 Aug 13 06:26:32 PM PDT 24 Aug 13 06:26:39 PM PDT 24 1343411909 ps
T57 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.671604785 Aug 13 06:26:33 PM PDT 24 Aug 13 06:26:38 PM PDT 24 431177928 ps
T58 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.652416859 Aug 13 06:26:40 PM PDT 24 Aug 13 06:27:51 PM PDT 24 914932199 ps
T116 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3240298067 Aug 13 06:26:46 PM PDT 24 Aug 13 06:26:50 PM PDT 24 86437760 ps
T59 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2709736659 Aug 13 06:26:41 PM PDT 24 Aug 13 06:26:46 PM PDT 24 93324476 ps
T325 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3830653669 Aug 13 06:26:43 PM PDT 24 Aug 13 06:26:48 PM PDT 24 540863429 ps
T90 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1348566825 Aug 13 06:26:24 PM PDT 24 Aug 13 06:26:52 PM PDT 24 542294750 ps
T117 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.153963713 Aug 13 06:26:38 PM PDT 24 Aug 13 06:26:42 PM PDT 24 279034742 ps
T326 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1910257915 Aug 13 06:26:24 PM PDT 24 Aug 13 06:26:28 PM PDT 24 217097974 ps
T60 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.18041845 Aug 13 06:26:36 PM PDT 24 Aug 13 06:26:43 PM PDT 24 334421145 ps
T118 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2433107161 Aug 13 06:26:33 PM PDT 24 Aug 13 06:26:38 PM PDT 24 958553429 ps
T73 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1418443763 Aug 13 06:26:23 PM PDT 24 Aug 13 06:27:32 PM PDT 24 1184084970 ps
T76 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2857661902 Aug 13 06:26:32 PM PDT 24 Aug 13 06:26:40 PM PDT 24 133509864 ps
T77 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.11465396 Aug 13 06:26:39 PM PDT 24 Aug 13 06:26:48 PM PDT 24 262707629 ps
T327 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2730877040 Aug 13 06:26:24 PM PDT 24 Aug 13 06:26:28 PM PDT 24 176753301 ps
T328 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1016354151 Aug 13 06:26:38 PM PDT 24 Aug 13 06:26:42 PM PDT 24 85635300 ps
T119 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1408818203 Aug 13 06:26:35 PM PDT 24 Aug 13 06:26:40 PM PDT 24 126521075 ps
T329 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1550151486 Aug 13 06:26:31 PM PDT 24 Aug 13 06:26:36 PM PDT 24 94848238 ps
T78 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1470643276 Aug 13 06:26:46 PM PDT 24 Aug 13 06:26:51 PM PDT 24 95086817 ps
T91 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2750585665 Aug 13 06:26:43 PM PDT 24 Aug 13 06:26:47 PM PDT 24 222140421 ps
T330 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3618195543 Aug 13 06:26:49 PM PDT 24 Aug 13 06:26:56 PM PDT 24 142608456 ps
T122 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3298586709 Aug 13 06:26:42 PM PDT 24 Aug 13 06:27:05 PM PDT 24 548801627 ps
T331 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2340940411 Aug 13 06:26:33 PM PDT 24 Aug 13 06:26:37 PM PDT 24 312335610 ps
T332 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.965908294 Aug 13 06:26:48 PM PDT 24 Aug 13 06:26:55 PM PDT 24 249170251 ps
T333 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2431881261 Aug 13 06:26:31 PM PDT 24 Aug 13 06:26:36 PM PDT 24 499878670 ps
T334 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.831151167 Aug 13 06:26:35 PM PDT 24 Aug 13 06:26:40 PM PDT 24 390726087 ps
T92 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2576643638 Aug 13 06:26:23 PM PDT 24 Aug 13 06:26:28 PM PDT 24 128349151 ps
T335 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3953464843 Aug 13 06:26:43 PM PDT 24 Aug 13 06:26:48 PM PDT 24 693145871 ps
T336 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2176162887 Aug 13 06:26:32 PM PDT 24 Aug 13 06:26:38 PM PDT 24 127006143 ps
T337 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2980673354 Aug 13 06:26:33 PM PDT 24 Aug 13 06:26:38 PM PDT 24 132687524 ps
T338 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.518543743 Aug 13 06:26:31 PM PDT 24 Aug 13 06:26:37 PM PDT 24 390617632 ps
T339 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1755772224 Aug 13 06:26:30 PM PDT 24 Aug 13 06:26:52 PM PDT 24 1072468796 ps
T124 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2218509299 Aug 13 06:26:47 PM PDT 24 Aug 13 06:27:55 PM PDT 24 224804017 ps
T340 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1254801664 Aug 13 06:26:31 PM PDT 24 Aug 13 06:26:40 PM PDT 24 227853812 ps
T341 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3493335586 Aug 13 06:26:41 PM PDT 24 Aug 13 06:26:46 PM PDT 24 334260000 ps
T129 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.780810425 Aug 13 06:26:42 PM PDT 24 Aug 13 06:27:20 PM PDT 24 420284066 ps
T342 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1844682270 Aug 13 06:26:32 PM PDT 24 Aug 13 06:26:40 PM PDT 24 299459677 ps
T343 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3000763656 Aug 13 06:26:41 PM PDT 24 Aug 13 06:26:50 PM PDT 24 500735677 ps
T344 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3093065304 Aug 13 06:26:36 PM PDT 24 Aug 13 06:26:43 PM PDT 24 697048535 ps
T345 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.791510554 Aug 13 06:26:30 PM PDT 24 Aug 13 06:26:35 PM PDT 24 783734769 ps
T346 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.234926097 Aug 13 06:26:45 PM PDT 24 Aug 13 06:26:55 PM PDT 24 668158105 ps
T347 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2128512709 Aug 13 06:26:43 PM PDT 24 Aug 13 06:26:49 PM PDT 24 655868067 ps
T348 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1868239644 Aug 13 06:26:43 PM PDT 24 Aug 13 06:26:51 PM PDT 24 1128724357 ps
T349 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3293128899 Aug 13 06:26:45 PM PDT 24 Aug 13 06:26:54 PM PDT 24 491015846 ps
T350 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1432469660 Aug 13 06:26:50 PM PDT 24 Aug 13 06:26:55 PM PDT 24 365807525 ps
T351 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3973291077 Aug 13 06:26:37 PM PDT 24 Aug 13 06:26:42 PM PDT 24 349310140 ps
T130 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2797093044 Aug 13 06:26:43 PM PDT 24 Aug 13 06:27:57 PM PDT 24 395553128 ps
T93 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2555558540 Aug 13 06:26:49 PM PDT 24 Aug 13 06:27:11 PM PDT 24 741934356 ps
T352 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.575001139 Aug 13 06:26:48 PM PDT 24 Aug 13 06:26:53 PM PDT 24 127973961 ps
T353 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.433710791 Aug 13 06:26:33 PM PDT 24 Aug 13 06:26:39 PM PDT 24 141571503 ps
T123 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2001288171 Aug 13 06:26:34 PM PDT 24 Aug 13 06:27:08 PM PDT 24 3277074421 ps
T354 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2755287242 Aug 13 06:26:34 PM PDT 24 Aug 13 06:26:38 PM PDT 24 361212056 ps
T355 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1969186091 Aug 13 06:26:43 PM PDT 24 Aug 13 06:26:49 PM PDT 24 1387563562 ps
T94 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2272931975 Aug 13 06:26:37 PM PDT 24 Aug 13 06:26:45 PM PDT 24 1009036474 ps
T356 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2618418309 Aug 13 06:26:52 PM PDT 24 Aug 13 06:26:56 PM PDT 24 298950726 ps
T357 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1230113169 Aug 13 06:26:24 PM PDT 24 Aug 13 06:26:28 PM PDT 24 88403804 ps
T95 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1611014119 Aug 13 06:26:31 PM PDT 24 Aug 13 06:26:53 PM PDT 24 550797642 ps
T358 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2167362313 Aug 13 06:26:38 PM PDT 24 Aug 13 06:26:44 PM PDT 24 597745627 ps
T126 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1559978390 Aug 13 06:26:47 PM PDT 24 Aug 13 06:27:58 PM PDT 24 232036581 ps
T359 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.843011356 Aug 13 06:26:41 PM PDT 24 Aug 13 06:27:04 PM PDT 24 2095228134 ps
T96 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1430876933 Aug 13 06:26:49 PM PDT 24 Aug 13 06:27:22 PM PDT 24 784406901 ps
T360 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2780614929 Aug 13 06:26:32 PM PDT 24 Aug 13 06:27:43 PM PDT 24 498857612 ps
T97 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.99772156 Aug 13 06:26:38 PM PDT 24 Aug 13 06:26:45 PM PDT 24 971076894 ps
T98 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3733387926 Aug 13 06:26:32 PM PDT 24 Aug 13 06:26:39 PM PDT 24 93662349 ps
T125 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.460689156 Aug 13 06:26:49 PM PDT 24 Aug 13 06:28:11 PM PDT 24 673934476 ps
T361 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3998554573 Aug 13 06:26:51 PM PDT 24 Aug 13 06:26:57 PM PDT 24 515701714 ps
T362 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.294549457 Aug 13 06:26:41 PM PDT 24 Aug 13 06:27:53 PM PDT 24 316722084 ps
T363 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1704594778 Aug 13 06:26:41 PM PDT 24 Aug 13 06:27:00 PM PDT 24 370450278 ps
T364 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.59181166 Aug 13 06:26:31 PM PDT 24 Aug 13 06:27:08 PM PDT 24 163450612 ps
T99 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3451181954 Aug 13 06:26:32 PM PDT 24 Aug 13 06:26:36 PM PDT 24 95919216 ps
T100 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1523221955 Aug 13 06:26:34 PM PDT 24 Aug 13 06:27:01 PM PDT 24 1589059867 ps
T365 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2972123778 Aug 13 06:26:34 PM PDT 24 Aug 13 06:26:39 PM PDT 24 256298329 ps
T366 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3260143703 Aug 13 06:26:32 PM PDT 24 Aug 13 06:26:37 PM PDT 24 639348383 ps
T367 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3250862597 Aug 13 06:26:51 PM PDT 24 Aug 13 06:26:59 PM PDT 24 143138177 ps
T368 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2089762400 Aug 13 06:26:38 PM PDT 24 Aug 13 06:26:43 PM PDT 24 130479125 ps
T133 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3168949863 Aug 13 06:26:36 PM PDT 24 Aug 13 06:27:16 PM PDT 24 247622935 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3250300058 Aug 13 06:26:23 PM PDT 24 Aug 13 06:26:28 PM PDT 24 166489177 ps
T132 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1077490318 Aug 13 06:26:49 PM PDT 24 Aug 13 06:27:28 PM PDT 24 259617914 ps
T131 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1115060952 Aug 13 06:26:36 PM PDT 24 Aug 13 06:27:48 PM PDT 24 519211100 ps
T370 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4122760963 Aug 13 06:26:40 PM PDT 24 Aug 13 06:26:45 PM PDT 24 520130712 ps
T371 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.554833069 Aug 13 06:26:48 PM PDT 24 Aug 13 06:26:52 PM PDT 24 378230596 ps
T372 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3699268545 Aug 13 06:26:37 PM PDT 24 Aug 13 06:26:59 PM PDT 24 2365731747 ps
T373 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.870667406 Aug 13 06:26:40 PM PDT 24 Aug 13 06:26:45 PM PDT 24 103871132 ps
T374 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.913392261 Aug 13 06:26:49 PM PDT 24 Aug 13 06:26:58 PM PDT 24 2954765333 ps
T375 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.87457749 Aug 13 06:26:35 PM PDT 24 Aug 13 06:26:40 PM PDT 24 2286501951 ps
T376 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.58023180 Aug 13 06:26:31 PM PDT 24 Aug 13 06:26:36 PM PDT 24 694412159 ps
T377 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2889215580 Aug 13 06:26:42 PM PDT 24 Aug 13 06:26:47 PM PDT 24 373788207 ps
T378 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3519965931 Aug 13 06:26:31 PM PDT 24 Aug 13 06:26:40 PM PDT 24 122187567 ps
T379 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3319819931 Aug 13 06:26:45 PM PDT 24 Aug 13 06:26:56 PM PDT 24 152454679 ps
T380 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1529047065 Aug 13 06:26:31 PM PDT 24 Aug 13 06:27:46 PM PDT 24 424090889 ps
T381 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.319851358 Aug 13 06:26:48 PM PDT 24 Aug 13 06:26:54 PM PDT 24 100467063 ps
T101 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1857563862 Aug 13 06:26:31 PM PDT 24 Aug 13 06:26:36 PM PDT 24 85823952 ps
T102 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4285060509 Aug 13 06:26:39 PM PDT 24 Aug 13 06:26:58 PM PDT 24 1490363254 ps
T127 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1542610050 Aug 13 06:26:46 PM PDT 24 Aug 13 06:27:59 PM PDT 24 2556228406 ps
T382 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3905136569 Aug 13 06:26:42 PM PDT 24 Aug 13 06:26:47 PM PDT 24 202337510 ps
T383 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1746120862 Aug 13 06:26:48 PM PDT 24 Aug 13 06:27:17 PM PDT 24 627964551 ps
T384 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1287085521 Aug 13 06:26:50 PM PDT 24 Aug 13 06:26:55 PM PDT 24 100292188 ps
T103 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.956883148 Aug 13 06:26:46 PM PDT 24 Aug 13 06:27:15 PM PDT 24 1507629939 ps
T385 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3073629364 Aug 13 06:26:33 PM PDT 24 Aug 13 06:26:37 PM PDT 24 522498104 ps
T386 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.321506118 Aug 13 06:26:47 PM PDT 24 Aug 13 06:26:52 PM PDT 24 567135312 ps
T387 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.653579646 Aug 13 06:26:30 PM PDT 24 Aug 13 06:26:34 PM PDT 24 833009137 ps
T388 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3828512673 Aug 13 06:26:35 PM PDT 24 Aug 13 06:26:41 PM PDT 24 127286317 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2575501600 Aug 13 06:26:24 PM PDT 24 Aug 13 06:26:29 PM PDT 24 133470686 ps
T390 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3087345695 Aug 13 06:26:35 PM PDT 24 Aug 13 06:26:43 PM PDT 24 127279890 ps
T391 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2352847442 Aug 13 06:26:26 PM PDT 24 Aug 13 06:26:35 PM PDT 24 133905939 ps
T392 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1606188714 Aug 13 06:26:32 PM PDT 24 Aug 13 06:26:42 PM PDT 24 1028051488 ps
T393 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1192263271 Aug 13 06:26:46 PM PDT 24 Aug 13 06:26:50 PM PDT 24 168500021 ps
T394 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2046124834 Aug 13 06:26:42 PM PDT 24 Aug 13 06:26:46 PM PDT 24 85761910 ps
T395 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1886671621 Aug 13 06:26:47 PM PDT 24 Aug 13 06:26:54 PM PDT 24 572166309 ps
T396 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1612861306 Aug 13 06:26:36 PM PDT 24 Aug 13 06:26:40 PM PDT 24 89305477 ps
T397 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2628138177 Aug 13 06:26:46 PM PDT 24 Aug 13 06:26:51 PM PDT 24 1141590653 ps
T398 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.73984215 Aug 13 06:26:40 PM PDT 24 Aug 13 06:26:47 PM PDT 24 187106747 ps
T399 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2589524365 Aug 13 06:26:30 PM PDT 24 Aug 13 06:26:34 PM PDT 24 87794416 ps
T400 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.409222082 Aug 13 06:26:51 PM PDT 24 Aug 13 06:26:57 PM PDT 24 495827028 ps
T104 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.208636120 Aug 13 06:26:31 PM PDT 24 Aug 13 06:26:39 PM PDT 24 3537304743 ps
T401 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1111912723 Aug 13 06:26:48 PM PDT 24 Aug 13 06:26:54 PM PDT 24 277428183 ps
T402 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3862730138 Aug 13 06:26:38 PM PDT 24 Aug 13 06:27:17 PM PDT 24 392478768 ps
T105 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3375641404 Aug 13 06:26:46 PM PDT 24 Aug 13 06:27:20 PM PDT 24 9686474040 ps
T403 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3120448936 Aug 13 06:26:32 PM PDT 24 Aug 13 06:26:38 PM PDT 24 513691407 ps
T404 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2270343620 Aug 13 06:26:46 PM PDT 24 Aug 13 06:26:52 PM PDT 24 132619658 ps
T405 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2132191078 Aug 13 06:26:32 PM PDT 24 Aug 13 06:26:37 PM PDT 24 171391542 ps
T406 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1221418842 Aug 13 06:26:35 PM PDT 24 Aug 13 06:26:44 PM PDT 24 127033880 ps
T407 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.504204183 Aug 13 06:26:41 PM PDT 24 Aug 13 06:26:48 PM PDT 24 590712805 ps
T408 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1815366610 Aug 13 06:26:40 PM PDT 24 Aug 13 06:27:08 PM PDT 24 559976454 ps
T409 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3164776894 Aug 13 06:26:49 PM PDT 24 Aug 13 06:27:22 PM PDT 24 3994449456 ps
T410 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2654004825 Aug 13 06:26:41 PM PDT 24 Aug 13 06:26:47 PM PDT 24 325453996 ps
T411 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3196139749 Aug 13 06:26:31 PM PDT 24 Aug 13 06:26:38 PM PDT 24 260628337 ps
T128 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3050059729 Aug 13 06:26:48 PM PDT 24 Aug 13 06:27:26 PM PDT 24 880637190 ps
T412 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1449179420 Aug 13 06:26:43 PM PDT 24 Aug 13 06:26:49 PM PDT 24 280556427 ps

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3019672334
Short name T2
Test name
Test status
Simulation time 8247032940 ps
CPU time 146.88 seconds
Started Aug 13 06:44:33 PM PDT 24
Finished Aug 13 06:47:06 PM PDT 24
Peak memory 213696 kb
Host smart-46606f4b-c368-4cf1-a69b-240cad1efdad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019672334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3019672334
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2640812607
Short name T18
Test name
Test status
Simulation time 12825484267 ps
CPU time 169.8 seconds
Started Aug 13 06:44:30 PM PDT 24
Finished Aug 13 06:47:20 PM PDT 24
Peak memory 223116 kb
Host smart-e33f0033-3c60-4f57-8b76-0d4c1194f01d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640812607 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2640812607
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2998244451
Short name T13
Test name
Test status
Simulation time 259059692 ps
CPU time 12.08 seconds
Started Aug 13 06:44:15 PM PDT 24
Finished Aug 13 06:44:28 PM PDT 24
Peak memory 214232 kb
Host smart-c54aab54-bbc3-48e5-b93a-1258c0205b3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998244451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2998244451
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1821213867
Short name T19
Test name
Test status
Simulation time 2722433448 ps
CPU time 125.06 seconds
Started Aug 13 06:44:35 PM PDT 24
Finished Aug 13 06:46:41 PM PDT 24
Peak memory 212740 kb
Host smart-ac50a6e4-9aca-4401-950b-46a9b3ca7b8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821213867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1821213867
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1022110191
Short name T135
Test name
Test status
Simulation time 98963308 ps
CPU time 5.82 seconds
Started Aug 13 06:44:07 PM PDT 24
Finished Aug 13 06:44:13 PM PDT 24
Peak memory 211460 kb
Host smart-335c90db-0a65-43f1-a3b2-7b1417c001be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1022110191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1022110191
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1108963491
Short name T52
Test name
Test status
Simulation time 9813652639 ps
CPU time 141.21 seconds
Started Aug 13 06:44:07 PM PDT 24
Finished Aug 13 06:46:28 PM PDT 24
Peak memory 226124 kb
Host smart-5d8ebeb1-acb0-499c-8f2a-f33acb82be70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108963491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1108963491
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4138784313
Short name T56
Test name
Test status
Simulation time 504360523 ps
CPU time 77 seconds
Started Aug 13 06:26:43 PM PDT 24
Finished Aug 13 06:28:00 PM PDT 24
Peak memory 213932 kb
Host smart-be0b175e-bfb6-4e3b-a840-fe0e22a33c64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138784313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.4138784313
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4202182755
Short name T69
Test name
Test status
Simulation time 1378462872 ps
CPU time 4.36 seconds
Started Aug 13 06:44:20 PM PDT 24
Finished Aug 13 06:44:25 PM PDT 24
Peak memory 211408 kb
Host smart-c6a7bc2d-b744-4438-b0c1-84367b12de0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202182755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4202182755
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1245627893
Short name T138
Test name
Test status
Simulation time 160274111 ps
CPU time 5.88 seconds
Started Aug 13 06:44:32 PM PDT 24
Finished Aug 13 06:44:38 PM PDT 24
Peak memory 211412 kb
Host smart-e9a72f44-d5cf-4ace-b0d9-3787e88cfd7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1245627893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1245627893
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1374365375
Short name T1
Test name
Test status
Simulation time 817911843 ps
CPU time 19.29 seconds
Started Aug 13 06:44:50 PM PDT 24
Finished Aug 13 06:45:09 PM PDT 24
Peak memory 214464 kb
Host smart-48d7d2a7-219c-44ce-954b-ec7e85f7a7a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374365375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1374365375
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.4248062215
Short name T23
Test name
Test status
Simulation time 2732578443 ps
CPU time 168.46 seconds
Started Aug 13 06:44:12 PM PDT 24
Finished Aug 13 06:47:00 PM PDT 24
Peak memory 246048 kb
Host smart-dac0b45e-ed3d-4f96-958b-a8afb6372bec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248062215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.4248062215
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2951753033
Short name T72
Test name
Test status
Simulation time 1919207387 ps
CPU time 21.77 seconds
Started Aug 13 06:26:30 PM PDT 24
Finished Aug 13 06:26:52 PM PDT 24
Peak memory 210996 kb
Host smart-49c06b77-bc93-462d-9669-f1e53e6cba0b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951753033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2951753033
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.460689156
Short name T125
Test name
Test status
Simulation time 673934476 ps
CPU time 81.43 seconds
Started Aug 13 06:26:49 PM PDT 24
Finished Aug 13 06:28:11 PM PDT 24
Peak memory 213824 kb
Host smart-01e00ea6-a15e-4056-ae0b-12c9b780c835
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460689156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.460689156
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.323636770
Short name T36
Test name
Test status
Simulation time 535371094 ps
CPU time 6.37 seconds
Started Aug 13 06:44:16 PM PDT 24
Finished Aug 13 06:44:22 PM PDT 24
Peak memory 211424 kb
Host smart-e91436c0-4da7-463f-b120-13add948d6be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=323636770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.323636770
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.738172684
Short name T17
Test name
Test status
Simulation time 1436593376 ps
CPU time 63.79 seconds
Started Aug 13 06:44:26 PM PDT 24
Finished Aug 13 06:45:30 PM PDT 24
Peak memory 231028 kb
Host smart-0e0bb704-0e72-4935-a353-0f26d513ef0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738172684 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.738172684
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1564844931
Short name T121
Test name
Test status
Simulation time 141018097 ps
CPU time 6.57 seconds
Started Aug 13 06:44:20 PM PDT 24
Finished Aug 13 06:44:26 PM PDT 24
Peak memory 211320 kb
Host smart-f1ae41d5-d77e-4b17-b21e-9e6f54bba947
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1564844931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1564844931
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2230621352
Short name T31
Test name
Test status
Simulation time 671598031 ps
CPU time 9.54 seconds
Started Aug 13 06:44:29 PM PDT 24
Finished Aug 13 06:44:39 PM PDT 24
Peak memory 212340 kb
Host smart-40609767-5595-4609-8832-dcc73843eabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230621352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2230621352
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.797790027
Short name T162
Test name
Test status
Simulation time 666939311 ps
CPU time 9.56 seconds
Started Aug 13 06:44:32 PM PDT 24
Finished Aug 13 06:44:42 PM PDT 24
Peak memory 212532 kb
Host smart-910b8a06-32c1-4552-bf79-5598a9d75613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797790027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.797790027
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1115060952
Short name T131
Test name
Test status
Simulation time 519211100 ps
CPU time 71.92 seconds
Started Aug 13 06:26:36 PM PDT 24
Finished Aug 13 06:27:48 PM PDT 24
Peak memory 212772 kb
Host smart-c6cc6b08-ff50-4607-8ecc-01cbef2d30a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115060952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1115060952
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.214143608
Short name T42
Test name
Test status
Simulation time 1998533651 ps
CPU time 110.02 seconds
Started Aug 13 06:44:07 PM PDT 24
Finished Aug 13 06:45:57 PM PDT 24
Peak memory 234812 kb
Host smart-5d4258b0-f6fd-48df-af91-796e0e3d3c7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214143608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.214143608
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.586001752
Short name T88
Test name
Test status
Simulation time 1486433627 ps
CPU time 17.13 seconds
Started Aug 13 06:44:23 PM PDT 24
Finished Aug 13 06:44:40 PM PDT 24
Peak memory 215320 kb
Host smart-cb78ce72-7b25-4708-bdea-761f08e010f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586001752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.586001752
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1704594778
Short name T363
Test name
Test status
Simulation time 370450278 ps
CPU time 18.53 seconds
Started Aug 13 06:26:41 PM PDT 24
Finished Aug 13 06:27:00 PM PDT 24
Peak memory 211020 kb
Host smart-4b53d279-2d07-4b7d-80bc-4142ed80f1c0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704594778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1704594778
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3168949863
Short name T133
Test name
Test status
Simulation time 247622935 ps
CPU time 39.85 seconds
Started Aug 13 06:26:36 PM PDT 24
Finished Aug 13 06:27:16 PM PDT 24
Peak memory 212888 kb
Host smart-3f34e03a-cad9-4327-9cbf-64db9ad4736d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168949863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3168949863
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3926790737
Short name T75
Test name
Test status
Simulation time 433396136 ps
CPU time 5.33 seconds
Started Aug 13 06:44:11 PM PDT 24
Finished Aug 13 06:44:17 PM PDT 24
Peak memory 211392 kb
Host smart-48ca7a12-2b08-41b5-ae83-952d3718ec9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926790737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3926790737
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1062472801
Short name T106
Test name
Test status
Simulation time 192345036 ps
CPU time 5.77 seconds
Started Aug 13 06:44:12 PM PDT 24
Finished Aug 13 06:44:17 PM PDT 24
Peak memory 211380 kb
Host smart-ccc1d315-8154-463f-a166-232f038fe492
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1062472801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1062472801
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2730877040
Short name T327
Test name
Test status
Simulation time 176753301 ps
CPU time 4.33 seconds
Started Aug 13 06:26:24 PM PDT 24
Finished Aug 13 06:26:28 PM PDT 24
Peak memory 210996 kb
Host smart-559b7353-17e0-4654-ad07-79ce7c5010a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730877040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2730877040
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2575501600
Short name T389
Test name
Test status
Simulation time 133470686 ps
CPU time 5.33 seconds
Started Aug 13 06:26:24 PM PDT 24
Finished Aug 13 06:26:29 PM PDT 24
Peak memory 211040 kb
Host smart-2fd4fbac-2be8-4e35-866e-1308fc126173
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575501600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2575501600
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2352847442
Short name T391
Test name
Test status
Simulation time 133905939 ps
CPU time 8.63 seconds
Started Aug 13 06:26:26 PM PDT 24
Finished Aug 13 06:26:35 PM PDT 24
Peak memory 219068 kb
Host smart-0edd44e4-90aa-4719-a5d6-46ea7ac8ca3c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352847442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2352847442
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.58023180
Short name T376
Test name
Test status
Simulation time 694412159 ps
CPU time 5.79 seconds
Started Aug 13 06:26:31 PM PDT 24
Finished Aug 13 06:26:36 PM PDT 24
Peak memory 215916 kb
Host smart-54a21d2a-03a7-4cd6-965f-f871271e34d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58023180 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.58023180
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1230113169
Short name T357
Test name
Test status
Simulation time 88403804 ps
CPU time 4.38 seconds
Started Aug 13 06:26:24 PM PDT 24
Finished Aug 13 06:26:28 PM PDT 24
Peak memory 211056 kb
Host smart-15dd8846-2df6-4478-8ffa-3155a4adb1c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230113169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1230113169
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3250300058
Short name T369
Test name
Test status
Simulation time 166489177 ps
CPU time 4.19 seconds
Started Aug 13 06:26:23 PM PDT 24
Finished Aug 13 06:26:28 PM PDT 24
Peak memory 210868 kb
Host smart-f41d6f13-2d27-4c67-bc04-f87ea6c313f7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250300058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3250300058
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1910257915
Short name T326
Test name
Test status
Simulation time 217097974 ps
CPU time 4.33 seconds
Started Aug 13 06:26:24 PM PDT 24
Finished Aug 13 06:26:28 PM PDT 24
Peak memory 210856 kb
Host smart-c25861d2-56d3-43b1-8d16-6b4d6fbe9fcd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910257915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1910257915
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1348566825
Short name T90
Test name
Test status
Simulation time 542294750 ps
CPU time 27.75 seconds
Started Aug 13 06:26:24 PM PDT 24
Finished Aug 13 06:26:52 PM PDT 24
Peak memory 211092 kb
Host smart-3e6fdf59-c920-4ebc-8811-7f2ea12f5280
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348566825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1348566825
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1550151486
Short name T329
Test name
Test status
Simulation time 94848238 ps
CPU time 4.35 seconds
Started Aug 13 06:26:31 PM PDT 24
Finished Aug 13 06:26:36 PM PDT 24
Peak memory 219192 kb
Host smart-c1e5c075-8f6a-4162-8039-eaf52d61989c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550151486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1550151486
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3519965931
Short name T378
Test name
Test status
Simulation time 122187567 ps
CPU time 8.49 seconds
Started Aug 13 06:26:31 PM PDT 24
Finished Aug 13 06:26:40 PM PDT 24
Peak memory 215912 kb
Host smart-7008c783-6f8c-4abf-9146-bb9c2c151143
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519965931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3519965931
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3150244053
Short name T27
Test name
Test status
Simulation time 1597459849 ps
CPU time 36.35 seconds
Started Aug 13 06:26:24 PM PDT 24
Finished Aug 13 06:27:00 PM PDT 24
Peak memory 211320 kb
Host smart-c4ac463c-dcfd-4486-993b-908a895ff7fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150244053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3150244053
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2589524365
Short name T399
Test name
Test status
Simulation time 87794416 ps
CPU time 4.33 seconds
Started Aug 13 06:26:30 PM PDT 24
Finished Aug 13 06:26:34 PM PDT 24
Peak memory 211152 kb
Host smart-d91fd40f-3b46-4a31-828c-2b2530158002
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589524365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2589524365
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2132191078
Short name T405
Test name
Test status
Simulation time 171391542 ps
CPU time 4.64 seconds
Started Aug 13 06:26:32 PM PDT 24
Finished Aug 13 06:26:37 PM PDT 24
Peak memory 211076 kb
Host smart-e4bdd5ab-d4e4-47bc-b0b5-15ac6e390616
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132191078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2132191078
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3196139749
Short name T411
Test name
Test status
Simulation time 260628337 ps
CPU time 6.64 seconds
Started Aug 13 06:26:31 PM PDT 24
Finished Aug 13 06:26:38 PM PDT 24
Peak memory 211012 kb
Host smart-deea4679-f6e1-44dd-88f8-c7c693546fa7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196139749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3196139749
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.671604785
Short name T57
Test name
Test status
Simulation time 431177928 ps
CPU time 5.03 seconds
Started Aug 13 06:26:33 PM PDT 24
Finished Aug 13 06:26:38 PM PDT 24
Peak memory 219236 kb
Host smart-8e379d58-ce8b-4697-8d37-ba68183b79d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671604785 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.671604785
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2576643638
Short name T92
Test name
Test status
Simulation time 128349151 ps
CPU time 5.17 seconds
Started Aug 13 06:26:23 PM PDT 24
Finished Aug 13 06:26:28 PM PDT 24
Peak memory 211080 kb
Host smart-a7e55527-a113-4693-b297-b84f1b869ed5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576643638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2576643638
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.338660340
Short name T323
Test name
Test status
Simulation time 688591629 ps
CPU time 5.07 seconds
Started Aug 13 06:26:25 PM PDT 24
Finished Aug 13 06:26:31 PM PDT 24
Peak memory 210796 kb
Host smart-99d2ec27-ad23-42b1-8072-61682f9b2579
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338660340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.338660340
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.653579646
Short name T387
Test name
Test status
Simulation time 833009137 ps
CPU time 4.09 seconds
Started Aug 13 06:26:30 PM PDT 24
Finished Aug 13 06:26:34 PM PDT 24
Peak memory 210896 kb
Host smart-7664092b-76e5-460b-8df8-7eebd4a711b1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653579646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
653579646
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3909022427
Short name T83
Test name
Test status
Simulation time 12521745239 ps
CPU time 31.01 seconds
Started Aug 13 06:26:20 PM PDT 24
Finished Aug 13 06:26:51 PM PDT 24
Peak memory 211144 kb
Host smart-83bb3a43-e40a-45a1-8989-585607dea968
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909022427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3909022427
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.791510554
Short name T345
Test name
Test status
Simulation time 783734769 ps
CPU time 5.25 seconds
Started Aug 13 06:26:30 PM PDT 24
Finished Aug 13 06:26:35 PM PDT 24
Peak memory 219184 kb
Host smart-9dd51e1c-ba61-4467-b130-ed8769421b36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791510554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.791510554
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1254801664
Short name T340
Test name
Test status
Simulation time 227853812 ps
CPU time 8.78 seconds
Started Aug 13 06:26:31 PM PDT 24
Finished Aug 13 06:26:40 PM PDT 24
Peak memory 219268 kb
Host smart-d469b21d-ab5c-43b5-baf8-ed3977af6d0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254801664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1254801664
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1418443763
Short name T73
Test name
Test status
Simulation time 1184084970 ps
CPU time 68.94 seconds
Started Aug 13 06:26:23 PM PDT 24
Finished Aug 13 06:27:32 PM PDT 24
Peak memory 212744 kb
Host smart-928b9f36-3071-417a-9e11-cd184250c8b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418443763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1418443763
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2654004825
Short name T410
Test name
Test status
Simulation time 325453996 ps
CPU time 5.96 seconds
Started Aug 13 06:26:41 PM PDT 24
Finished Aug 13 06:26:47 PM PDT 24
Peak memory 219212 kb
Host smart-ae8b152f-b973-4533-9283-3fb036e498ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654004825 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2654004825
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.99772156
Short name T97
Test name
Test status
Simulation time 971076894 ps
CPU time 7.28 seconds
Started Aug 13 06:26:38 PM PDT 24
Finished Aug 13 06:26:45 PM PDT 24
Peak memory 210960 kb
Host smart-12c4c98b-de38-4ff7-9547-6cdff8e06ab7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99772156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.99772156
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4285060509
Short name T102
Test name
Test status
Simulation time 1490363254 ps
CPU time 19.03 seconds
Started Aug 13 06:26:39 PM PDT 24
Finished Aug 13 06:26:58 PM PDT 24
Peak memory 211060 kb
Host smart-304afc75-8c43-4153-bf78-6fdc16cf2df0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285060509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.4285060509
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3953464843
Short name T335
Test name
Test status
Simulation time 693145871 ps
CPU time 4.27 seconds
Started Aug 13 06:26:43 PM PDT 24
Finished Aug 13 06:26:48 PM PDT 24
Peak memory 211048 kb
Host smart-cad2d759-5779-4e1e-abd7-3165447da02f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953464843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3953464843
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1868239644
Short name T348
Test name
Test status
Simulation time 1128724357 ps
CPU time 8.37 seconds
Started Aug 13 06:26:43 PM PDT 24
Finished Aug 13 06:26:51 PM PDT 24
Peak memory 219232 kb
Host smart-7c68d81d-357c-48af-888e-28e9a3124e1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868239644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1868239644
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.294549457
Short name T362
Test name
Test status
Simulation time 316722084 ps
CPU time 71.31 seconds
Started Aug 13 06:26:41 PM PDT 24
Finished Aug 13 06:27:53 PM PDT 24
Peak memory 219148 kb
Host smart-ad6c2f99-dec1-47a1-9ffd-4711bc9a5bb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294549457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.294549457
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2889215580
Short name T377
Test name
Test status
Simulation time 373788207 ps
CPU time 4.66 seconds
Started Aug 13 06:26:42 PM PDT 24
Finished Aug 13 06:26:47 PM PDT 24
Peak memory 213280 kb
Host smart-c45f159a-405c-47b1-b0b1-5fdaf4386b36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889215580 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2889215580
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3222194823
Short name T71
Test name
Test status
Simulation time 272775621 ps
CPU time 5.06 seconds
Started Aug 13 06:26:35 PM PDT 24
Finished Aug 13 06:26:40 PM PDT 24
Peak memory 209712 kb
Host smart-3b457e7e-9586-455c-a105-61a88bf5e5ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222194823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3222194823
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1815366610
Short name T408
Test name
Test status
Simulation time 559976454 ps
CPU time 28.14 seconds
Started Aug 13 06:26:40 PM PDT 24
Finished Aug 13 06:27:08 PM PDT 24
Peak memory 211048 kb
Host smart-34a2df3f-5eec-4fca-9d5f-430cf6275edd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815366610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1815366610
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.801992509
Short name T81
Test name
Test status
Simulation time 136086583 ps
CPU time 5.05 seconds
Started Aug 13 06:26:38 PM PDT 24
Finished Aug 13 06:26:43 PM PDT 24
Peak memory 211080 kb
Host smart-08a7c691-0236-49e0-9c59-b090fb0a4379
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801992509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.801992509
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.18041845
Short name T60
Test name
Test status
Simulation time 334421145 ps
CPU time 6.44 seconds
Started Aug 13 06:26:36 PM PDT 24
Finished Aug 13 06:26:43 PM PDT 24
Peak memory 214876 kb
Host smart-9f04113b-787b-489e-9403-8620c04e2717
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18041845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.18041845
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.780810425
Short name T129
Test name
Test status
Simulation time 420284066 ps
CPU time 38.06 seconds
Started Aug 13 06:26:42 PM PDT 24
Finished Aug 13 06:27:20 PM PDT 24
Peak memory 213672 kb
Host smart-0b9528af-bd90-4d9a-a004-20dcaf2a89f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780810425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.780810425
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.870667406
Short name T373
Test name
Test status
Simulation time 103871132 ps
CPU time 5.02 seconds
Started Aug 13 06:26:40 PM PDT 24
Finished Aug 13 06:26:45 PM PDT 24
Peak memory 219228 kb
Host smart-543e9055-cf8c-439f-a77e-bd2b2e965866
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870667406 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.870667406
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3493335586
Short name T341
Test name
Test status
Simulation time 334260000 ps
CPU time 4.2 seconds
Started Aug 13 06:26:41 PM PDT 24
Finished Aug 13 06:26:46 PM PDT 24
Peak memory 211064 kb
Host smart-c7ce874c-9181-4be7-9590-5185d6981a23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493335586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3493335586
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.504204183
Short name T407
Test name
Test status
Simulation time 590712805 ps
CPU time 6.72 seconds
Started Aug 13 06:26:41 PM PDT 24
Finished Aug 13 06:26:48 PM PDT 24
Peak memory 210996 kb
Host smart-3b4360b8-eb33-48d4-8ffa-9fe1a0905f2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504204183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.504204183
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3000763656
Short name T343
Test name
Test status
Simulation time 500735677 ps
CPU time 9.16 seconds
Started Aug 13 06:26:41 PM PDT 24
Finished Aug 13 06:26:50 PM PDT 24
Peak memory 216368 kb
Host smart-f5ff38d7-cabd-4aea-8ee8-93843e622e82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000763656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3000763656
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2797093044
Short name T130
Test name
Test status
Simulation time 395553128 ps
CPU time 73.22 seconds
Started Aug 13 06:26:43 PM PDT 24
Finished Aug 13 06:27:57 PM PDT 24
Peak memory 212892 kb
Host smart-72d631a5-1fb0-4d4b-9dae-6b32c18b0c98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797093044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2797093044
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2628138177
Short name T397
Test name
Test status
Simulation time 1141590653 ps
CPU time 4.88 seconds
Started Aug 13 06:26:46 PM PDT 24
Finished Aug 13 06:26:51 PM PDT 24
Peak memory 216084 kb
Host smart-a222cf8d-5810-4bc5-a6af-e44d12dd1b9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628138177 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2628138177
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2089762400
Short name T368
Test name
Test status
Simulation time 130479125 ps
CPU time 5.01 seconds
Started Aug 13 06:26:38 PM PDT 24
Finished Aug 13 06:26:43 PM PDT 24
Peak memory 211000 kb
Host smart-13fea8e5-b1b6-4dd8-a005-83024d426b7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089762400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2089762400
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.843011356
Short name T359
Test name
Test status
Simulation time 2095228134 ps
CPU time 22.54 seconds
Started Aug 13 06:26:41 PM PDT 24
Finished Aug 13 06:27:04 PM PDT 24
Peak memory 211096 kb
Host smart-d6bab9aa-1e7f-4f22-b7e7-80d7eb66ea43
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843011356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.843011356
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2046124834
Short name T394
Test name
Test status
Simulation time 85761910 ps
CPU time 4.6 seconds
Started Aug 13 06:26:42 PM PDT 24
Finished Aug 13 06:26:46 PM PDT 24
Peak memory 218324 kb
Host smart-b169b996-ebf9-41a4-addc-d5ff1711cefc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046124834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2046124834
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.11465396
Short name T77
Test name
Test status
Simulation time 262707629 ps
CPU time 8.93 seconds
Started Aug 13 06:26:39 PM PDT 24
Finished Aug 13 06:26:48 PM PDT 24
Peak memory 216228 kb
Host smart-007fe57a-76a4-444b-a3e3-2066cc621218
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11465396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.11465396
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3862730138
Short name T402
Test name
Test status
Simulation time 392478768 ps
CPU time 38.67 seconds
Started Aug 13 06:26:38 PM PDT 24
Finished Aug 13 06:27:17 PM PDT 24
Peak memory 219172 kb
Host smart-150e84d5-1435-493a-b5c5-6f70ace4c491
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862730138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3862730138
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1470643276
Short name T78
Test name
Test status
Simulation time 95086817 ps
CPU time 4.74 seconds
Started Aug 13 06:26:46 PM PDT 24
Finished Aug 13 06:26:51 PM PDT 24
Peak memory 213876 kb
Host smart-b71c3513-0cc9-4c6f-bc8f-b8648c0a09dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470643276 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1470643276
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.575001139
Short name T352
Test name
Test status
Simulation time 127973961 ps
CPU time 4.99 seconds
Started Aug 13 06:26:48 PM PDT 24
Finished Aug 13 06:26:53 PM PDT 24
Peak memory 211008 kb
Host smart-975b0db7-6fca-4f0b-8382-d285a35a88dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575001139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.575001139
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1430876933
Short name T96
Test name
Test status
Simulation time 784406901 ps
CPU time 32.99 seconds
Started Aug 13 06:26:49 PM PDT 24
Finished Aug 13 06:27:22 PM PDT 24
Peak memory 211048 kb
Host smart-eda023e8-df14-46c7-8217-73d445d026a8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430876933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1430876933
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1192263271
Short name T393
Test name
Test status
Simulation time 168500021 ps
CPU time 4.39 seconds
Started Aug 13 06:26:46 PM PDT 24
Finished Aug 13 06:26:50 PM PDT 24
Peak memory 218352 kb
Host smart-1c948634-488b-4d47-a070-330ddb516ecf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192263271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1192263271
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3319819931
Short name T379
Test name
Test status
Simulation time 152454679 ps
CPU time 10.62 seconds
Started Aug 13 06:26:45 PM PDT 24
Finished Aug 13 06:26:56 PM PDT 24
Peak memory 219232 kb
Host smart-3448d56c-6dee-4f48-99ec-4f55040ece81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319819931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3319819931
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1542610050
Short name T127
Test name
Test status
Simulation time 2556228406 ps
CPU time 73.33 seconds
Started Aug 13 06:26:46 PM PDT 24
Finished Aug 13 06:27:59 PM PDT 24
Peak memory 212788 kb
Host smart-4ff2f3be-deb2-408d-9eaa-ea79806caa3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542610050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1542610050
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1432469660
Short name T350
Test name
Test status
Simulation time 365807525 ps
CPU time 4.94 seconds
Started Aug 13 06:26:50 PM PDT 24
Finished Aug 13 06:26:55 PM PDT 24
Peak memory 213436 kb
Host smart-8c4e6a02-901e-417c-a021-aaae7c115110
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432469660 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1432469660
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3690975994
Short name T80
Test name
Test status
Simulation time 490535630 ps
CPU time 7.58 seconds
Started Aug 13 06:26:50 PM PDT 24
Finished Aug 13 06:26:57 PM PDT 24
Peak memory 211000 kb
Host smart-f8c00f39-b1d3-49fc-9136-ebcb1c9c1408
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690975994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3690975994
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3375641404
Short name T105
Test name
Test status
Simulation time 9686474040 ps
CPU time 32.96 seconds
Started Aug 13 06:26:46 PM PDT 24
Finished Aug 13 06:27:20 PM PDT 24
Peak memory 211156 kb
Host smart-6c525b0d-ce37-4052-8af6-c79a7f087999
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375641404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3375641404
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3618195543
Short name T330
Test name
Test status
Simulation time 142608456 ps
CPU time 7.07 seconds
Started Aug 13 06:26:49 PM PDT 24
Finished Aug 13 06:26:56 PM PDT 24
Peak memory 219160 kb
Host smart-fd37c6ae-33c2-4f20-bc60-ef03ba3482a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618195543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3618195543
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.234926097
Short name T346
Test name
Test status
Simulation time 668158105 ps
CPU time 9.11 seconds
Started Aug 13 06:26:45 PM PDT 24
Finished Aug 13 06:26:55 PM PDT 24
Peak memory 216356 kb
Host smart-dddd82e1-6498-410b-ab23-405c747cd686
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234926097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.234926097
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3050059729
Short name T128
Test name
Test status
Simulation time 880637190 ps
CPU time 37.65 seconds
Started Aug 13 06:26:48 PM PDT 24
Finished Aug 13 06:27:26 PM PDT 24
Peak memory 212676 kb
Host smart-65036970-e59b-4744-ad07-707319953fdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050059729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3050059729
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.913392261
Short name T374
Test name
Test status
Simulation time 2954765333 ps
CPU time 8.38 seconds
Started Aug 13 06:26:49 PM PDT 24
Finished Aug 13 06:26:58 PM PDT 24
Peak memory 214728 kb
Host smart-d3a654bb-3816-4560-9f2a-ba6c4e950917
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913392261 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.913392261
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3998554573
Short name T361
Test name
Test status
Simulation time 515701714 ps
CPU time 4.95 seconds
Started Aug 13 06:26:51 PM PDT 24
Finished Aug 13 06:26:57 PM PDT 24
Peak memory 219100 kb
Host smart-aa740a9e-d71e-46e7-a046-c5fbc244c845
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998554573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3998554573
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1746120862
Short name T383
Test name
Test status
Simulation time 627964551 ps
CPU time 28.65 seconds
Started Aug 13 06:26:48 PM PDT 24
Finished Aug 13 06:27:17 PM PDT 24
Peak memory 211100 kb
Host smart-4de1a2e1-3498-42e4-b3d6-ca858a585c3a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746120862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1746120862
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2270343620
Short name T404
Test name
Test status
Simulation time 132619658 ps
CPU time 5.22 seconds
Started Aug 13 06:26:46 PM PDT 24
Finished Aug 13 06:26:52 PM PDT 24
Peak memory 219152 kb
Host smart-d998ec8c-2b9b-4220-9a01-ce9280b02872
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270343620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2270343620
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3293128899
Short name T349
Test name
Test status
Simulation time 491015846 ps
CPU time 8.91 seconds
Started Aug 13 06:26:45 PM PDT 24
Finished Aug 13 06:26:54 PM PDT 24
Peak memory 219248 kb
Host smart-e6262562-2e41-49f1-8ebe-5ca1e9d44ba2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293128899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3293128899
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.319851358
Short name T381
Test name
Test status
Simulation time 100467063 ps
CPU time 6 seconds
Started Aug 13 06:26:48 PM PDT 24
Finished Aug 13 06:26:54 PM PDT 24
Peak memory 219268 kb
Host smart-b2fbd110-6d5c-47e4-af7b-20728e7e5f79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319851358 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.319851358
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1287085521
Short name T384
Test name
Test status
Simulation time 100292188 ps
CPU time 4.34 seconds
Started Aug 13 06:26:50 PM PDT 24
Finished Aug 13 06:26:55 PM PDT 24
Peak memory 218068 kb
Host smart-26f50e0a-fd62-4fff-b085-2de68a37c751
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287085521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1287085521
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3164776894
Short name T409
Test name
Test status
Simulation time 3994449456 ps
CPU time 32.83 seconds
Started Aug 13 06:26:49 PM PDT 24
Finished Aug 13 06:27:22 PM PDT 24
Peak memory 212168 kb
Host smart-f6f1a2de-7560-4afa-a8d0-8af9c73dd404
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164776894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3164776894
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3240298067
Short name T116
Test name
Test status
Simulation time 86437760 ps
CPU time 4.28 seconds
Started Aug 13 06:26:46 PM PDT 24
Finished Aug 13 06:26:50 PM PDT 24
Peak memory 211060 kb
Host smart-80cd698e-6ff6-480f-bff3-082d17595ba2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240298067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3240298067
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.965908294
Short name T332
Test name
Test status
Simulation time 249170251 ps
CPU time 6.7 seconds
Started Aug 13 06:26:48 PM PDT 24
Finished Aug 13 06:26:55 PM PDT 24
Peak memory 219292 kb
Host smart-68dff898-9878-45d6-a47e-8acf3181abed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965908294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.965908294
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2218509299
Short name T124
Test name
Test status
Simulation time 224804017 ps
CPU time 68.68 seconds
Started Aug 13 06:26:47 PM PDT 24
Finished Aug 13 06:27:55 PM PDT 24
Peak memory 212852 kb
Host smart-baedf34d-9c82-420e-9b65-b7b589f08503
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218509299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2218509299
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2077415503
Short name T54
Test name
Test status
Simulation time 149383416 ps
CPU time 5.99 seconds
Started Aug 13 06:26:46 PM PDT 24
Finished Aug 13 06:26:52 PM PDT 24
Peak memory 215600 kb
Host smart-2a7cf9ed-a8ee-4253-9e22-ff0acbc34256
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077415503 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2077415503
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2618418309
Short name T356
Test name
Test status
Simulation time 298950726 ps
CPU time 4.25 seconds
Started Aug 13 06:26:52 PM PDT 24
Finished Aug 13 06:26:56 PM PDT 24
Peak memory 211064 kb
Host smart-a912390b-843d-4a1b-b024-5a7d9d654ceb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618418309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2618418309
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.956883148
Short name T103
Test name
Test status
Simulation time 1507629939 ps
CPU time 28.57 seconds
Started Aug 13 06:26:46 PM PDT 24
Finished Aug 13 06:27:15 PM PDT 24
Peak memory 211092 kb
Host smart-f612e7af-684c-4b5d-bbe3-f17aaf6a4299
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956883148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.956883148
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.554833069
Short name T371
Test name
Test status
Simulation time 378230596 ps
CPU time 4.2 seconds
Started Aug 13 06:26:48 PM PDT 24
Finished Aug 13 06:26:52 PM PDT 24
Peak memory 211056 kb
Host smart-aea635f1-af0a-41ea-a86a-c3c32159cfb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554833069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.554833069
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1886671621
Short name T395
Test name
Test status
Simulation time 572166309 ps
CPU time 6.82 seconds
Started Aug 13 06:26:47 PM PDT 24
Finished Aug 13 06:26:54 PM PDT 24
Peak memory 219292 kb
Host smart-fb734534-eae4-482b-83df-149b3b82ff12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886671621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1886671621
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1559978390
Short name T126
Test name
Test status
Simulation time 232036581 ps
CPU time 70.36 seconds
Started Aug 13 06:26:47 PM PDT 24
Finished Aug 13 06:27:58 PM PDT 24
Peak memory 213784 kb
Host smart-11b67ee6-4145-4312-9254-d4510626bc11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559978390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1559978390
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1111912723
Short name T401
Test name
Test status
Simulation time 277428183 ps
CPU time 5.79 seconds
Started Aug 13 06:26:48 PM PDT 24
Finished Aug 13 06:26:54 PM PDT 24
Peak memory 214892 kb
Host smart-ffcf690f-a551-4840-ae6b-956bb8ecca4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111912723 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1111912723
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.321506118
Short name T386
Test name
Test status
Simulation time 567135312 ps
CPU time 5.13 seconds
Started Aug 13 06:26:47 PM PDT 24
Finished Aug 13 06:26:52 PM PDT 24
Peak memory 219152 kb
Host smart-07c5e111-8f8c-437b-adb9-25a26df05de1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321506118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.321506118
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2555558540
Short name T93
Test name
Test status
Simulation time 741934356 ps
CPU time 22.22 seconds
Started Aug 13 06:26:49 PM PDT 24
Finished Aug 13 06:27:11 PM PDT 24
Peak memory 211016 kb
Host smart-e7bd1e9b-a371-4a48-8132-faba731ffe8f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555558540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2555558540
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.409222082
Short name T400
Test name
Test status
Simulation time 495827028 ps
CPU time 5.47 seconds
Started Aug 13 06:26:51 PM PDT 24
Finished Aug 13 06:26:57 PM PDT 24
Peak memory 211048 kb
Host smart-e8304870-8b1f-475b-9025-6b3c61e29d3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409222082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.409222082
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3250862597
Short name T367
Test name
Test status
Simulation time 143138177 ps
CPU time 7.77 seconds
Started Aug 13 06:26:51 PM PDT 24
Finished Aug 13 06:26:59 PM PDT 24
Peak memory 215048 kb
Host smart-26feea21-8a4a-4790-a5a8-59c6e8936d93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250862597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3250862597
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1077490318
Short name T132
Test name
Test status
Simulation time 259617914 ps
CPU time 39.08 seconds
Started Aug 13 06:26:49 PM PDT 24
Finished Aug 13 06:27:28 PM PDT 24
Peak memory 211580 kb
Host smart-2fe1638f-688a-4255-b733-709c9bdfac8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077490318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1077490318
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.208636120
Short name T104
Test name
Test status
Simulation time 3537304743 ps
CPU time 7.6 seconds
Started Aug 13 06:26:31 PM PDT 24
Finished Aug 13 06:26:39 PM PDT 24
Peak memory 211116 kb
Host smart-e2bc0115-688c-4870-b7d6-8c79c9edb6b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208636120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.208636120
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2431881261
Short name T333
Test name
Test status
Simulation time 499878670 ps
CPU time 5.23 seconds
Started Aug 13 06:26:31 PM PDT 24
Finished Aug 13 06:26:36 PM PDT 24
Peak memory 211076 kb
Host smart-2378742e-9f5f-456f-9c1b-c9a759ff8dcf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431881261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2431881261
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3453706169
Short name T70
Test name
Test status
Simulation time 571327305 ps
CPU time 8.31 seconds
Started Aug 13 06:26:31 PM PDT 24
Finished Aug 13 06:26:40 PM PDT 24
Peak memory 211004 kb
Host smart-e15b0303-02d9-410e-8809-0128237238ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453706169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3453706169
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.433710791
Short name T353
Test name
Test status
Simulation time 141571503 ps
CPU time 6.15 seconds
Started Aug 13 06:26:33 PM PDT 24
Finished Aug 13 06:26:39 PM PDT 24
Peak memory 219228 kb
Host smart-0ca556ee-11e1-45b4-9df6-bc266b67138f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433710791 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.433710791
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3451181954
Short name T99
Test name
Test status
Simulation time 95919216 ps
CPU time 4.26 seconds
Started Aug 13 06:26:32 PM PDT 24
Finished Aug 13 06:26:36 PM PDT 24
Peak memory 211080 kb
Host smart-61e7aff8-6f62-4d59-8a63-8163b5f0c456
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451181954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3451181954
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3973291077
Short name T351
Test name
Test status
Simulation time 349310140 ps
CPU time 4.09 seconds
Started Aug 13 06:26:37 PM PDT 24
Finished Aug 13 06:26:42 PM PDT 24
Peak memory 210880 kb
Host smart-da4f9b8e-ab4b-43b9-8563-f118c1760e63
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973291077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3973291077
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2755287242
Short name T354
Test name
Test status
Simulation time 361212056 ps
CPU time 4.2 seconds
Started Aug 13 06:26:34 PM PDT 24
Finished Aug 13 06:26:38 PM PDT 24
Peak memory 210892 kb
Host smart-c868ea35-8cd8-484c-9963-0770acb120c3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755287242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2755287242
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3120448936
Short name T403
Test name
Test status
Simulation time 513691407 ps
CPU time 5.23 seconds
Started Aug 13 06:26:32 PM PDT 24
Finished Aug 13 06:26:38 PM PDT 24
Peak memory 218184 kb
Host smart-ff6603d9-1d75-4d23-9811-2a2ba76be408
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120448936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3120448936
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1844682270
Short name T342
Test name
Test status
Simulation time 299459677 ps
CPU time 7.56 seconds
Started Aug 13 06:26:32 PM PDT 24
Finished Aug 13 06:26:40 PM PDT 24
Peak memory 215720 kb
Host smart-bf914296-2dd3-4bbb-a4d5-6ca404b2728c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844682270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1844682270
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2780614929
Short name T360
Test name
Test status
Simulation time 498857612 ps
CPU time 70.18 seconds
Started Aug 13 06:26:32 PM PDT 24
Finished Aug 13 06:27:43 PM PDT 24
Peak memory 212748 kb
Host smart-bfc4c7f3-8856-4a37-a1cf-53de4ddd86b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780614929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2780614929
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1857563862
Short name T101
Test name
Test status
Simulation time 85823952 ps
CPU time 4.32 seconds
Started Aug 13 06:26:31 PM PDT 24
Finished Aug 13 06:26:36 PM PDT 24
Peak memory 210932 kb
Host smart-8a9c172f-4701-489c-8290-b9819d290d31
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857563862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1857563862
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2980673354
Short name T337
Test name
Test status
Simulation time 132687524 ps
CPU time 5.07 seconds
Started Aug 13 06:26:33 PM PDT 24
Finished Aug 13 06:26:38 PM PDT 24
Peak memory 219216 kb
Host smart-4030455e-f68f-4f46-b7b1-84cd3f7a04e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980673354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2980673354
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.518543743
Short name T338
Test name
Test status
Simulation time 390617632 ps
CPU time 5.91 seconds
Started Aug 13 06:26:31 PM PDT 24
Finished Aug 13 06:26:37 PM PDT 24
Peak memory 217956 kb
Host smart-a945a34f-2a12-4701-a2c8-9748ffe873ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518543743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.518543743
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2167362313
Short name T358
Test name
Test status
Simulation time 597745627 ps
CPU time 5.97 seconds
Started Aug 13 06:26:38 PM PDT 24
Finished Aug 13 06:26:44 PM PDT 24
Peak memory 219384 kb
Host smart-52dd9209-9459-41a9-996e-8a7fc067b363
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167362313 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2167362313
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2176162887
Short name T336
Test name
Test status
Simulation time 127006143 ps
CPU time 5.24 seconds
Started Aug 13 06:26:32 PM PDT 24
Finished Aug 13 06:26:38 PM PDT 24
Peak memory 210984 kb
Host smart-dc4ae0f8-0a49-4037-a928-3163c9bae5db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176162887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2176162887
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3905136569
Short name T382
Test name
Test status
Simulation time 202337510 ps
CPU time 5.09 seconds
Started Aug 13 06:26:42 PM PDT 24
Finished Aug 13 06:26:47 PM PDT 24
Peak memory 210828 kb
Host smart-3f1e167d-a927-4b5a-a091-888924ba816d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905136569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3905136569
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1844603415
Short name T322
Test name
Test status
Simulation time 86495955 ps
CPU time 4.32 seconds
Started Aug 13 06:26:31 PM PDT 24
Finished Aug 13 06:26:35 PM PDT 24
Peak memory 210944 kb
Host smart-d3365ba0-4fb4-4300-9978-88772d4e27e0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844603415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1844603415
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1755772224
Short name T339
Test name
Test status
Simulation time 1072468796 ps
CPU time 21.85 seconds
Started Aug 13 06:26:30 PM PDT 24
Finished Aug 13 06:26:52 PM PDT 24
Peak memory 211096 kb
Host smart-eabec24a-5425-44e0-a0c6-789963adba0a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755772224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1755772224
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2433107161
Short name T118
Test name
Test status
Simulation time 958553429 ps
CPU time 5.39 seconds
Started Aug 13 06:26:33 PM PDT 24
Finished Aug 13 06:26:38 PM PDT 24
Peak memory 219156 kb
Host smart-a9955b5b-b70b-405e-9d53-18a307e00c25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433107161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2433107161
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1969186091
Short name T355
Test name
Test status
Simulation time 1387563562 ps
CPU time 6.65 seconds
Started Aug 13 06:26:43 PM PDT 24
Finished Aug 13 06:26:49 PM PDT 24
Peak memory 216156 kb
Host smart-27d27480-c6a3-4c8f-a729-30c1ab5e6123
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969186091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1969186091
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2788159139
Short name T82
Test name
Test status
Simulation time 403542484 ps
CPU time 5.09 seconds
Started Aug 13 06:26:35 PM PDT 24
Finished Aug 13 06:26:40 PM PDT 24
Peak memory 219192 kb
Host smart-50a601a1-f9ce-4dc7-8376-efdfb3a022f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788159139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2788159139
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3830653669
Short name T325
Test name
Test status
Simulation time 540863429 ps
CPU time 5.25 seconds
Started Aug 13 06:26:43 PM PDT 24
Finished Aug 13 06:26:48 PM PDT 24
Peak memory 219180 kb
Host smart-b543eb1d-0d23-4dee-8757-e14ba1c60e21
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830653669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3830653669
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3733387926
Short name T98
Test name
Test status
Simulation time 93662349 ps
CPU time 7.51 seconds
Started Aug 13 06:26:32 PM PDT 24
Finished Aug 13 06:26:39 PM PDT 24
Peak memory 211040 kb
Host smart-633ecbb2-8aaa-4695-b971-ae88758d068d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733387926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3733387926
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.87457749
Short name T375
Test name
Test status
Simulation time 2286501951 ps
CPU time 5.57 seconds
Started Aug 13 06:26:35 PM PDT 24
Finished Aug 13 06:26:40 PM PDT 24
Peak memory 214424 kb
Host smart-86ba6729-3012-42cc-8fb6-23b5dc43f05d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87457749 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.87457749
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3828512673
Short name T388
Test name
Test status
Simulation time 127286317 ps
CPU time 5.27 seconds
Started Aug 13 06:26:35 PM PDT 24
Finished Aug 13 06:26:41 PM PDT 24
Peak memory 219176 kb
Host smart-edbdd150-b89d-4383-90b7-72779027c2d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828512673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3828512673
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1016354151
Short name T328
Test name
Test status
Simulation time 85635300 ps
CPU time 4.09 seconds
Started Aug 13 06:26:38 PM PDT 24
Finished Aug 13 06:26:42 PM PDT 24
Peak memory 210880 kb
Host smart-4c2462c3-e703-4a41-848a-b27fe968ff05
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016354151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1016354151
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3260143703
Short name T366
Test name
Test status
Simulation time 639348383 ps
CPU time 4.27 seconds
Started Aug 13 06:26:32 PM PDT 24
Finished Aug 13 06:26:37 PM PDT 24
Peak memory 210876 kb
Host smart-d1134430-df30-48c9-bc74-06223f403d8c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260143703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3260143703
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1523221955
Short name T100
Test name
Test status
Simulation time 1589059867 ps
CPU time 27.4 seconds
Started Aug 13 06:26:34 PM PDT 24
Finished Aug 13 06:27:01 PM PDT 24
Peak memory 211028 kb
Host smart-f55308cf-88a5-4be4-bb6c-1772cd5e5b1c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523221955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1523221955
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2156306718
Short name T85
Test name
Test status
Simulation time 172226852 ps
CPU time 4.3 seconds
Started Aug 13 06:26:35 PM PDT 24
Finished Aug 13 06:26:39 PM PDT 24
Peak memory 218384 kb
Host smart-c3c919f5-2241-4265-9539-5d89ab0c219d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156306718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2156306718
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1606188714
Short name T392
Test name
Test status
Simulation time 1028051488 ps
CPU time 9.29 seconds
Started Aug 13 06:26:32 PM PDT 24
Finished Aug 13 06:26:42 PM PDT 24
Peak memory 219292 kb
Host smart-5c679958-22fa-48af-8c00-d4a7d9e6b0b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606188714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1606188714
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.59181166
Short name T364
Test name
Test status
Simulation time 163450612 ps
CPU time 36.7 seconds
Started Aug 13 06:26:31 PM PDT 24
Finished Aug 13 06:27:08 PM PDT 24
Peak memory 211696 kb
Host smart-d2c6b5eb-8523-423b-a4d1-6d55d169f6ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59181166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg
_err.59181166
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2340940411
Short name T331
Test name
Test status
Simulation time 312335610 ps
CPU time 4.74 seconds
Started Aug 13 06:26:33 PM PDT 24
Finished Aug 13 06:26:37 PM PDT 24
Peak memory 219240 kb
Host smart-18795434-7f21-492b-bda6-1acd749b88d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340940411 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2340940411
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2972123778
Short name T365
Test name
Test status
Simulation time 256298329 ps
CPU time 4.83 seconds
Started Aug 13 06:26:34 PM PDT 24
Finished Aug 13 06:26:39 PM PDT 24
Peak memory 219148 kb
Host smart-96637749-6bde-40f4-a0db-81dc363a8f8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972123778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2972123778
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1611014119
Short name T95
Test name
Test status
Simulation time 550797642 ps
CPU time 21.86 seconds
Started Aug 13 06:26:31 PM PDT 24
Finished Aug 13 06:26:53 PM PDT 24
Peak memory 211016 kb
Host smart-7de38a4d-033d-450e-bdcd-0d0bf04cac70
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611014119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1611014119
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1612861306
Short name T396
Test name
Test status
Simulation time 89305477 ps
CPU time 4.25 seconds
Started Aug 13 06:26:36 PM PDT 24
Finished Aug 13 06:26:40 PM PDT 24
Peak memory 211108 kb
Host smart-e2e1ebf3-d938-4649-81d9-db53a7a4b3f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612861306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1612861306
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3087345695
Short name T390
Test name
Test status
Simulation time 127279890 ps
CPU time 7.86 seconds
Started Aug 13 06:26:35 PM PDT 24
Finished Aug 13 06:26:43 PM PDT 24
Peak memory 219224 kb
Host smart-16d4931d-10a7-490d-90c3-3944ae823cfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087345695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3087345695
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.831151167
Short name T334
Test name
Test status
Simulation time 390726087 ps
CPU time 4.86 seconds
Started Aug 13 06:26:35 PM PDT 24
Finished Aug 13 06:26:40 PM PDT 24
Peak memory 214876 kb
Host smart-22772884-3ab0-440a-925c-219d3a3f4bd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831151167 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.831151167
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2644499817
Short name T324
Test name
Test status
Simulation time 1343411909 ps
CPU time 7.33 seconds
Started Aug 13 06:26:32 PM PDT 24
Finished Aug 13 06:26:39 PM PDT 24
Peak memory 211060 kb
Host smart-c0c98e18-6bee-4e1d-9c70-eb62d7d021fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644499817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2644499817
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.4178636612
Short name T84
Test name
Test status
Simulation time 551986365 ps
CPU time 21.8 seconds
Started Aug 13 06:26:34 PM PDT 24
Finished Aug 13 06:26:56 PM PDT 24
Peak memory 211044 kb
Host smart-2aaf5a0f-d02f-463e-b640-46ef77c26219
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178636612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.4178636612
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1408818203
Short name T119
Test name
Test status
Simulation time 126521075 ps
CPU time 5.04 seconds
Started Aug 13 06:26:35 PM PDT 24
Finished Aug 13 06:26:40 PM PDT 24
Peak memory 211060 kb
Host smart-e2227702-5337-4fa5-85ae-17e9e2ae06a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408818203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1408818203
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3093065304
Short name T344
Test name
Test status
Simulation time 697048535 ps
CPU time 6.74 seconds
Started Aug 13 06:26:36 PM PDT 24
Finished Aug 13 06:26:43 PM PDT 24
Peak memory 216028 kb
Host smart-10e97098-dba4-431c-a118-170680eee2dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093065304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3093065304
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1529047065
Short name T380
Test name
Test status
Simulation time 424090889 ps
CPU time 74.02 seconds
Started Aug 13 06:26:31 PM PDT 24
Finished Aug 13 06:27:46 PM PDT 24
Peak memory 212896 kb
Host smart-24cf0311-d48d-4a3f-8c45-b2a254999425
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529047065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1529047065
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1449179420
Short name T412
Test name
Test status
Simulation time 280556427 ps
CPU time 5.85 seconds
Started Aug 13 06:26:43 PM PDT 24
Finished Aug 13 06:26:49 PM PDT 24
Peak memory 215952 kb
Host smart-802a2c62-c33b-4a99-afb4-2332a99569b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449179420 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1449179420
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2750585665
Short name T91
Test name
Test status
Simulation time 222140421 ps
CPU time 4.15 seconds
Started Aug 13 06:26:43 PM PDT 24
Finished Aug 13 06:26:47 PM PDT 24
Peak memory 217920 kb
Host smart-d442d4ce-6844-41a0-90ed-61254b2b4736
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750585665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2750585665
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2001288171
Short name T123
Test name
Test status
Simulation time 3277074421 ps
CPU time 34 seconds
Started Aug 13 06:26:34 PM PDT 24
Finished Aug 13 06:27:08 PM PDT 24
Peak memory 211156 kb
Host smart-0232b266-3707-464a-8879-969ab6f9561c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001288171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2001288171
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3073629364
Short name T385
Test name
Test status
Simulation time 522498104 ps
CPU time 4.38 seconds
Started Aug 13 06:26:33 PM PDT 24
Finished Aug 13 06:26:37 PM PDT 24
Peak memory 218740 kb
Host smart-3df5c7e1-f45f-404b-8b26-ba4829c0ed68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073629364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3073629364
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1221418842
Short name T406
Test name
Test status
Simulation time 127033880 ps
CPU time 8.26 seconds
Started Aug 13 06:26:35 PM PDT 24
Finished Aug 13 06:26:44 PM PDT 24
Peak memory 216184 kb
Host smart-05657f0e-696b-45ae-9903-a9a8fefc1094
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221418842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1221418842
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3009247679
Short name T55
Test name
Test status
Simulation time 165725815 ps
CPU time 37.48 seconds
Started Aug 13 06:26:31 PM PDT 24
Finished Aug 13 06:27:09 PM PDT 24
Peak memory 219216 kb
Host smart-8ef8bb15-9543-424f-85fb-32f94687d1bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009247679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3009247679
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2128512709
Short name T347
Test name
Test status
Simulation time 655868067 ps
CPU time 5.28 seconds
Started Aug 13 06:26:43 PM PDT 24
Finished Aug 13 06:26:49 PM PDT 24
Peak memory 216144 kb
Host smart-e9865d35-9fef-45b7-b123-4aba76374d15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128512709 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2128512709
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2272931975
Short name T94
Test name
Test status
Simulation time 1009036474 ps
CPU time 7.53 seconds
Started Aug 13 06:26:37 PM PDT 24
Finished Aug 13 06:26:45 PM PDT 24
Peak memory 211016 kb
Host smart-a5d40b95-7e71-453b-a5c1-e9068c506516
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272931975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2272931975
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3298586709
Short name T122
Test name
Test status
Simulation time 548801627 ps
CPU time 22.47 seconds
Started Aug 13 06:26:42 PM PDT 24
Finished Aug 13 06:27:05 PM PDT 24
Peak memory 211080 kb
Host smart-650da802-a769-4ad9-93e6-1a0b773e4d93
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298586709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3298586709
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.153963713
Short name T117
Test name
Test status
Simulation time 279034742 ps
CPU time 4.22 seconds
Started Aug 13 06:26:38 PM PDT 24
Finished Aug 13 06:26:42 PM PDT 24
Peak memory 218624 kb
Host smart-ce980e64-a813-4684-bb29-ec70f58a831c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153963713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.153963713
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2857661902
Short name T76
Test name
Test status
Simulation time 133509864 ps
CPU time 7.33 seconds
Started Aug 13 06:26:32 PM PDT 24
Finished Aug 13 06:26:40 PM PDT 24
Peak memory 215888 kb
Host smart-33452dd4-47f9-47e3-a90c-08deeb842a56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857661902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2857661902
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2709736659
Short name T59
Test name
Test status
Simulation time 93324476 ps
CPU time 4.62 seconds
Started Aug 13 06:26:41 PM PDT 24
Finished Aug 13 06:26:46 PM PDT 24
Peak memory 212444 kb
Host smart-13d22594-6570-4533-ae0d-9dfeb981324a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709736659 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2709736659
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4122760963
Short name T370
Test name
Test status
Simulation time 520130712 ps
CPU time 5 seconds
Started Aug 13 06:26:40 PM PDT 24
Finished Aug 13 06:26:45 PM PDT 24
Peak memory 219152 kb
Host smart-c9cc3305-c666-43e3-a120-34c267d6bae3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122760963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.4122760963
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3699268545
Short name T372
Test name
Test status
Simulation time 2365731747 ps
CPU time 21.68 seconds
Started Aug 13 06:26:37 PM PDT 24
Finished Aug 13 06:26:59 PM PDT 24
Peak memory 211176 kb
Host smart-f5bdabe3-12df-4d21-ae85-efe0812e0857
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699268545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3699268545
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.494459264
Short name T79
Test name
Test status
Simulation time 127061547 ps
CPU time 5.35 seconds
Started Aug 13 06:26:42 PM PDT 24
Finished Aug 13 06:26:47 PM PDT 24
Peak memory 219208 kb
Host smart-cef637c3-5a96-4e96-b4bd-730703674fce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494459264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.494459264
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.73984215
Short name T398
Test name
Test status
Simulation time 187106747 ps
CPU time 6.8 seconds
Started Aug 13 06:26:40 PM PDT 24
Finished Aug 13 06:26:47 PM PDT 24
Peak memory 215896 kb
Host smart-96745ad8-c712-4c3e-ab1e-3ca4a4e42a29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73984215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.73984215
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.652416859
Short name T58
Test name
Test status
Simulation time 914932199 ps
CPU time 70.67 seconds
Started Aug 13 06:26:40 PM PDT 24
Finished Aug 13 06:27:51 PM PDT 24
Peak memory 213836 kb
Host smart-d178fb88-2f6d-4e44-a230-81fa31afa3fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652416859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.652416859
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3666221500
Short name T107
Test name
Test status
Simulation time 514160862 ps
CPU time 7.69 seconds
Started Aug 13 06:43:50 PM PDT 24
Finished Aug 13 06:43:58 PM PDT 24
Peak memory 211416 kb
Host smart-e40760a0-c9dc-4e90-bbad-8c5a8f007ce9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666221500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3666221500
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2958392481
Short name T67
Test name
Test status
Simulation time 1854272789 ps
CPU time 102.26 seconds
Started Aug 13 06:44:32 PM PDT 24
Finished Aug 13 06:46:15 PM PDT 24
Peak memory 212640 kb
Host smart-47da4b9e-f2af-4584-a9eb-01de9c9f0b96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958392481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2958392481
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1090089425
Short name T155
Test name
Test status
Simulation time 1016976609 ps
CPU time 16.19 seconds
Started Aug 13 06:43:52 PM PDT 24
Finished Aug 13 06:44:08 PM PDT 24
Peak memory 212668 kb
Host smart-53fce848-0daf-471a-b6a0-b44ca32b871f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090089425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1090089425
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2411011699
Short name T235
Test name
Test status
Simulation time 1610810223 ps
CPU time 6.46 seconds
Started Aug 13 06:44:14 PM PDT 24
Finished Aug 13 06:44:20 PM PDT 24
Peak memory 211476 kb
Host smart-c155fa92-ccfa-4218-a6ac-d500af8f0ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411011699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2411011699
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2960968338
Short name T156
Test name
Test status
Simulation time 842156382 ps
CPU time 12.74 seconds
Started Aug 13 06:44:11 PM PDT 24
Finished Aug 13 06:44:27 PM PDT 24
Peak memory 215212 kb
Host smart-ebb47762-c4bb-4749-9049-62dcc92ff5d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960968338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2960968338
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.22674607
Short name T113
Test name
Test status
Simulation time 1843676199 ps
CPU time 66.57 seconds
Started Aug 13 06:44:26 PM PDT 24
Finished Aug 13 06:45:43 PM PDT 24
Peak memory 227052 kb
Host smart-46f01bfb-4380-4904-8df3-877c94b26212
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22674607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_cor
rupt_sig_fatal_chk.22674607
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.937400807
Short name T190
Test name
Test status
Simulation time 354035337 ps
CPU time 11.38 seconds
Started Aug 13 06:43:55 PM PDT 24
Finished Aug 13 06:44:06 PM PDT 24
Peak memory 212236 kb
Host smart-a547033a-b78e-45e2-98b1-bba483a11e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937400807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.937400807
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3183619616
Short name T22
Test name
Test status
Simulation time 184251676 ps
CPU time 53.46 seconds
Started Aug 13 06:43:48 PM PDT 24
Finished Aug 13 06:44:41 PM PDT 24
Peak memory 236660 kb
Host smart-f95af87b-37d9-49ca-95c3-f161a5f0a59c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183619616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3183619616
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.67576337
Short name T258
Test name
Test status
Simulation time 136923934 ps
CPU time 6.29 seconds
Started Aug 13 06:43:53 PM PDT 24
Finished Aug 13 06:44:00 PM PDT 24
Peak memory 211440 kb
Host smart-19870b2d-d7c1-49a3-bfc6-fbe70c76977f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67576337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.67576337
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2571777497
Short name T300
Test name
Test status
Simulation time 2014474045 ps
CPU time 10.4 seconds
Started Aug 13 06:44:03 PM PDT 24
Finished Aug 13 06:44:14 PM PDT 24
Peak memory 212588 kb
Host smart-731c3e7f-72ee-4f24-9eee-d5a7808dcedb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571777497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2571777497
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.472893250
Short name T212
Test name
Test status
Simulation time 1970717378 ps
CPU time 7.62 seconds
Started Aug 13 06:44:09 PM PDT 24
Finished Aug 13 06:44:17 PM PDT 24
Peak memory 211392 kb
Host smart-12b9eb6d-1e83-4e98-87c6-c4a2f039fd3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472893250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.472893250
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1266844637
Short name T321
Test name
Test status
Simulation time 2259916535 ps
CPU time 131.48 seconds
Started Aug 13 06:44:35 PM PDT 24
Finished Aug 13 06:46:47 PM PDT 24
Peak memory 213804 kb
Host smart-2df74119-7c46-4753-afe6-e61662f7080d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266844637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1266844637
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3146923686
Short name T234
Test name
Test status
Simulation time 1187890356 ps
CPU time 9.77 seconds
Started Aug 13 06:44:13 PM PDT 24
Finished Aug 13 06:44:23 PM PDT 24
Peak memory 212368 kb
Host smart-7c5ded4c-d1c7-47ed-9ee8-1bfb7dc8283c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146923686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3146923686
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1931334505
Short name T307
Test name
Test status
Simulation time 382489515 ps
CPU time 5.51 seconds
Started Aug 13 06:43:53 PM PDT 24
Finished Aug 13 06:43:58 PM PDT 24
Peak memory 211444 kb
Host smart-5a179cbe-f9ee-49fe-ba61-b0ca18fc8c73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1931334505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1931334505
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2809404047
Short name T33
Test name
Test status
Simulation time 554958893 ps
CPU time 11.41 seconds
Started Aug 13 06:44:08 PM PDT 24
Finished Aug 13 06:44:19 PM PDT 24
Peak memory 212424 kb
Host smart-63c3950b-e511-4e3b-a515-098d197c2803
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809404047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2809404047
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2252591651
Short name T182
Test name
Test status
Simulation time 1622377623 ps
CPU time 87.59 seconds
Started Aug 13 06:43:55 PM PDT 24
Finished Aug 13 06:45:22 PM PDT 24
Peak memory 224680 kb
Host smart-0a02e246-57cc-4eff-8e3b-c47876c14a29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252591651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2252591651
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3709844781
Short name T206
Test name
Test status
Simulation time 251409843 ps
CPU time 11.66 seconds
Started Aug 13 06:44:06 PM PDT 24
Finished Aug 13 06:44:18 PM PDT 24
Peak memory 212140 kb
Host smart-624a93fb-3277-46d7-81ac-9d5a2349500c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709844781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3709844781
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.833447509
Short name T68
Test name
Test status
Simulation time 535298505 ps
CPU time 6.66 seconds
Started Aug 13 06:44:11 PM PDT 24
Finished Aug 13 06:44:18 PM PDT 24
Peak memory 211440 kb
Host smart-ff5debb7-c37a-47f7-864a-53ed4acef5c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=833447509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.833447509
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2695003046
Short name T146
Test name
Test status
Simulation time 294376736 ps
CPU time 14.28 seconds
Started Aug 13 06:44:12 PM PDT 24
Finished Aug 13 06:44:26 PM PDT 24
Peak memory 212288 kb
Host smart-eb755bff-153f-44a1-afb8-4a69807fc8a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695003046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2695003046
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.626830098
Short name T149
Test name
Test status
Simulation time 252798212 ps
CPU time 5.17 seconds
Started Aug 13 06:44:14 PM PDT 24
Finished Aug 13 06:44:20 PM PDT 24
Peak memory 211420 kb
Host smart-31684305-4c2f-4b46-ba41-ff83cf9abc6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626830098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.626830098
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.411765541
Short name T223
Test name
Test status
Simulation time 168735246 ps
CPU time 9.36 seconds
Started Aug 13 06:44:10 PM PDT 24
Finished Aug 13 06:44:20 PM PDT 24
Peak memory 212692 kb
Host smart-36b2b4b4-6c7b-47f3-8537-37f3ba4c440a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411765541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.411765541
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2637008352
Short name T220
Test name
Test status
Simulation time 681637074 ps
CPU time 6.79 seconds
Started Aug 13 06:44:39 PM PDT 24
Finished Aug 13 06:44:46 PM PDT 24
Peak memory 211380 kb
Host smart-81f6d0ba-26b1-4e00-85c7-f42ab7e43ef6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2637008352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2637008352
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.4093587678
Short name T145
Test name
Test status
Simulation time 1554265213 ps
CPU time 21.61 seconds
Started Aug 13 06:44:18 PM PDT 24
Finished Aug 13 06:44:39 PM PDT 24
Peak memory 216464 kb
Host smart-32a91633-8ef0-43b1-bf97-5cb41e1d9625
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093587678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.4093587678
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1393728444
Short name T272
Test name
Test status
Simulation time 519204803 ps
CPU time 7.78 seconds
Started Aug 13 06:44:28 PM PDT 24
Finished Aug 13 06:44:36 PM PDT 24
Peak memory 211404 kb
Host smart-84551632-f79c-437a-8cdb-5099d0b5c66f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393728444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1393728444
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2139317632
Short name T263
Test name
Test status
Simulation time 1911993842 ps
CPU time 106 seconds
Started Aug 13 06:44:03 PM PDT 24
Finished Aug 13 06:45:49 PM PDT 24
Peak memory 237852 kb
Host smart-efd1f1a4-80db-4c1e-832f-456eba696d80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139317632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2139317632
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.729434947
Short name T188
Test name
Test status
Simulation time 1660246652 ps
CPU time 11.29 seconds
Started Aug 13 06:44:10 PM PDT 24
Finished Aug 13 06:44:21 PM PDT 24
Peak memory 212272 kb
Host smart-94beb45c-c827-4417-b44d-2968f837fd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729434947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.729434947
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1148795545
Short name T10
Test name
Test status
Simulation time 377270310 ps
CPU time 5.31 seconds
Started Aug 13 06:44:23 PM PDT 24
Finished Aug 13 06:44:29 PM PDT 24
Peak memory 211436 kb
Host smart-251d1ab4-6152-4dd5-8dda-8de965e0bab5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1148795545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1148795545
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3438371748
Short name T315
Test name
Test status
Simulation time 214827620 ps
CPU time 12.09 seconds
Started Aug 13 06:44:29 PM PDT 24
Finished Aug 13 06:44:41 PM PDT 24
Peak memory 211452 kb
Host smart-be1d8ad5-e49c-4612-838e-c85bcbe699fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438371748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3438371748
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3172161217
Short name T154
Test name
Test status
Simulation time 498595027 ps
CPU time 5.19 seconds
Started Aug 13 06:44:16 PM PDT 24
Finished Aug 13 06:44:22 PM PDT 24
Peak memory 211360 kb
Host smart-020c0433-529f-49c7-97eb-e0bf05b2e9bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172161217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3172161217
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2793605178
Short name T297
Test name
Test status
Simulation time 1024553243 ps
CPU time 61.41 seconds
Started Aug 13 06:44:19 PM PDT 24
Finished Aug 13 06:45:20 PM PDT 24
Peak memory 236688 kb
Host smart-4e542ba4-65a1-41b2-afc4-b2557150610f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793605178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2793605178
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2223884881
Short name T9
Test name
Test status
Simulation time 557625167 ps
CPU time 6.71 seconds
Started Aug 13 06:44:30 PM PDT 24
Finished Aug 13 06:44:37 PM PDT 24
Peak memory 211396 kb
Host smart-67b6c1c1-cbce-4160-be4b-f8ebe09266ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223884881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2223884881
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3155510978
Short name T271
Test name
Test status
Simulation time 162332230 ps
CPU time 5.16 seconds
Started Aug 13 06:44:02 PM PDT 24
Finished Aug 13 06:44:08 PM PDT 24
Peak memory 211356 kb
Host smart-577a84fd-99a9-4a1f-8d14-53e671b846be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155510978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3155510978
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3188935225
Short name T303
Test name
Test status
Simulation time 1763010417 ps
CPU time 83.09 seconds
Started Aug 13 06:44:08 PM PDT 24
Finished Aug 13 06:45:32 PM PDT 24
Peak memory 212836 kb
Host smart-464ed326-730a-41b6-8ff1-9f250fb86636
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188935225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3188935225
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1930378455
Short name T239
Test name
Test status
Simulation time 500253454 ps
CPU time 11.43 seconds
Started Aug 13 06:44:36 PM PDT 24
Finished Aug 13 06:44:48 PM PDT 24
Peak memory 212316 kb
Host smart-1c75332b-1c19-447a-8f69-e35b890882f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930378455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1930378455
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.153895689
Short name T273
Test name
Test status
Simulation time 99736031 ps
CPU time 5.82 seconds
Started Aug 13 06:44:07 PM PDT 24
Finished Aug 13 06:44:13 PM PDT 24
Peak memory 211460 kb
Host smart-3fb44c90-01bc-4682-b796-a98c69087834
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=153895689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.153895689
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3900102537
Short name T168
Test name
Test status
Simulation time 1526717136 ps
CPU time 27.58 seconds
Started Aug 13 06:44:14 PM PDT 24
Finished Aug 13 06:44:42 PM PDT 24
Peak memory 215600 kb
Host smart-5d28a32c-c2af-442c-8899-2f3d15cf66a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900102537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3900102537
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.4056264429
Short name T174
Test name
Test status
Simulation time 126253808 ps
CPU time 5.03 seconds
Started Aug 13 06:44:20 PM PDT 24
Finished Aug 13 06:44:25 PM PDT 24
Peak memory 211400 kb
Host smart-51d77e8f-63eb-4fd2-abd1-67bc340fec7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056264429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.4056264429
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1881228091
Short name T305
Test name
Test status
Simulation time 1097295764 ps
CPU time 67.21 seconds
Started Aug 13 06:44:12 PM PDT 24
Finished Aug 13 06:45:20 PM PDT 24
Peak memory 212596 kb
Host smart-7817bfbf-6ca3-47b8-b156-8d9acb63060b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881228091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1881228091
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.339593496
Short name T218
Test name
Test status
Simulation time 349463703 ps
CPU time 9.48 seconds
Started Aug 13 06:44:04 PM PDT 24
Finished Aug 13 06:44:14 PM PDT 24
Peak memory 212212 kb
Host smart-de6cb617-b08c-4032-ab35-2ff81610082a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339593496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.339593496
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2141945615
Short name T204
Test name
Test status
Simulation time 389551344 ps
CPU time 5.73 seconds
Started Aug 13 06:44:29 PM PDT 24
Finished Aug 13 06:44:35 PM PDT 24
Peak memory 211420 kb
Host smart-05c18a34-3cbf-4e27-bfe5-baadc874df42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2141945615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2141945615
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3092800244
Short name T142
Test name
Test status
Simulation time 1759041840 ps
CPU time 18.72 seconds
Started Aug 13 06:44:05 PM PDT 24
Finished Aug 13 06:44:23 PM PDT 24
Peak memory 214920 kb
Host smart-4aa2185c-a66f-477e-bbb3-6631b83803c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092800244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3092800244
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.66505832
Short name T276
Test name
Test status
Simulation time 397376173 ps
CPU time 4.2 seconds
Started Aug 13 06:44:22 PM PDT 24
Finished Aug 13 06:44:26 PM PDT 24
Peak memory 211412 kb
Host smart-83d1c78a-0e24-465d-945d-50cd637c3bb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66505832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.66505832
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4016004152
Short name T232
Test name
Test status
Simulation time 259448125 ps
CPU time 11.45 seconds
Started Aug 13 06:44:12 PM PDT 24
Finished Aug 13 06:44:24 PM PDT 24
Peak memory 212316 kb
Host smart-8cec9962-8443-4c66-a7fb-e907e88bc1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016004152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.4016004152
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3793805041
Short name T285
Test name
Test status
Simulation time 98474987 ps
CPU time 5.76 seconds
Started Aug 13 06:44:11 PM PDT 24
Finished Aug 13 06:44:17 PM PDT 24
Peak memory 211392 kb
Host smart-6247a297-ef3c-440e-9adf-4c991451ac4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3793805041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3793805041
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.4218331392
Short name T269
Test name
Test status
Simulation time 589739269 ps
CPU time 15.52 seconds
Started Aug 13 06:44:37 PM PDT 24
Finished Aug 13 06:44:52 PM PDT 24
Peak memory 214288 kb
Host smart-8cf749a8-206f-4b8f-ae4a-7ff94a3bf7ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218331392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.4218331392
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1456208338
Short name T186
Test name
Test status
Simulation time 256027193 ps
CPU time 5.01 seconds
Started Aug 13 06:44:15 PM PDT 24
Finished Aug 13 06:44:20 PM PDT 24
Peak memory 211428 kb
Host smart-a3441253-c232-4f36-84fe-8d4334e03861
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456208338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1456208338
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2469197548
Short name T178
Test name
Test status
Simulation time 4238532794 ps
CPU time 103.3 seconds
Started Aug 13 06:44:31 PM PDT 24
Finished Aug 13 06:46:14 PM PDT 24
Peak memory 238492 kb
Host smart-0b883ea5-75aa-445c-b48c-aa28d7fdf22e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469197548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2469197548
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1388572670
Short name T111
Test name
Test status
Simulation time 621982317 ps
CPU time 9.65 seconds
Started Aug 13 06:44:11 PM PDT 24
Finished Aug 13 06:44:20 PM PDT 24
Peak memory 212460 kb
Host smart-7eb487bb-b58c-4a22-8419-45e2eaf1a774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388572670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1388572670
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.390164956
Short name T260
Test name
Test status
Simulation time 473173543 ps
CPU time 6.37 seconds
Started Aug 13 06:44:34 PM PDT 24
Finished Aug 13 06:44:40 PM PDT 24
Peak memory 211408 kb
Host smart-4ac10c81-b32f-40fb-9c61-50247d60caac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=390164956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.390164956
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2187123732
Short name T148
Test name
Test status
Simulation time 875165000 ps
CPU time 14.12 seconds
Started Aug 13 06:44:12 PM PDT 24
Finished Aug 13 06:44:27 PM PDT 24
Peak memory 213620 kb
Host smart-8431f06d-6340-49d0-be08-4f644c43c0d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187123732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2187123732
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1465598785
Short name T158
Test name
Test status
Simulation time 87471843 ps
CPU time 4.27 seconds
Started Aug 13 06:44:26 PM PDT 24
Finished Aug 13 06:44:30 PM PDT 24
Peak memory 211392 kb
Host smart-b83c990b-8c4e-4d9c-b459-001c1b192cb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465598785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1465598785
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3442116818
Short name T41
Test name
Test status
Simulation time 2371662809 ps
CPU time 85.25 seconds
Started Aug 13 06:44:08 PM PDT 24
Finished Aug 13 06:45:38 PM PDT 24
Peak memory 239824 kb
Host smart-de76fbc1-e998-43e6-aca4-8b0129ae9dc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442116818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3442116818
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2390794440
Short name T6
Test name
Test status
Simulation time 499141346 ps
CPU time 11.39 seconds
Started Aug 13 06:44:29 PM PDT 24
Finished Aug 13 06:44:40 PM PDT 24
Peak memory 212264 kb
Host smart-b6fd9233-e13e-4dfa-ba00-b2834a9e925c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390794440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2390794440
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.275375585
Short name T191
Test name
Test status
Simulation time 1180913228 ps
CPU time 5.91 seconds
Started Aug 13 06:44:15 PM PDT 24
Finished Aug 13 06:44:21 PM PDT 24
Peak memory 211424 kb
Host smart-6e3d9950-1a0e-4085-8358-e9a84e9c6c93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=275375585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.275375585
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.84836250
Short name T295
Test name
Test status
Simulation time 823549561 ps
CPU time 7.25 seconds
Started Aug 13 06:44:23 PM PDT 24
Finished Aug 13 06:44:31 PM PDT 24
Peak memory 211200 kb
Host smart-8272a230-f575-44c0-a5e5-fb90c9ac98f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84836250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 19.rom_ctrl_stress_all.84836250
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3338317828
Short name T230
Test name
Test status
Simulation time 542349381 ps
CPU time 5.15 seconds
Started Aug 13 06:43:58 PM PDT 24
Finished Aug 13 06:44:03 PM PDT 24
Peak memory 211404 kb
Host smart-9424dfab-becc-4e3b-82fb-23d646a28c11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338317828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3338317828
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3118151610
Short name T270
Test name
Test status
Simulation time 3747116796 ps
CPU time 185.78 seconds
Started Aug 13 06:43:56 PM PDT 24
Finished Aug 13 06:47:01 PM PDT 24
Peak memory 212700 kb
Host smart-9c1777cb-902f-4dc0-a142-e103e9564f84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118151610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3118151610
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1013549082
Short name T262
Test name
Test status
Simulation time 4115555723 ps
CPU time 16.01 seconds
Started Aug 13 06:44:14 PM PDT 24
Finished Aug 13 06:44:31 PM PDT 24
Peak memory 213368 kb
Host smart-96be3ca5-983e-4a01-a5d6-c2717ceb8f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013549082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1013549082
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4080424072
Short name T207
Test name
Test status
Simulation time 97469839 ps
CPU time 5.55 seconds
Started Aug 13 06:44:15 PM PDT 24
Finished Aug 13 06:44:20 PM PDT 24
Peak memory 211360 kb
Host smart-e1e25dfd-d27c-407d-aced-9d25efbb702a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4080424072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.4080424072
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1906199791
Short name T28
Test name
Test status
Simulation time 271406822 ps
CPU time 51.81 seconds
Started Aug 13 06:43:57 PM PDT 24
Finished Aug 13 06:44:49 PM PDT 24
Peak memory 236672 kb
Host smart-b4f46909-bbbd-4ec7-8c11-6ff26ee978d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906199791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1906199791
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3630464367
Short name T147
Test name
Test status
Simulation time 152890883 ps
CPU time 5.61 seconds
Started Aug 13 06:44:13 PM PDT 24
Finished Aug 13 06:44:20 PM PDT 24
Peak memory 211488 kb
Host smart-13976135-1319-4d2e-a6c5-9f6a6f4151f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630464367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3630464367
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3212150395
Short name T317
Test name
Test status
Simulation time 2266569969 ps
CPU time 14.38 seconds
Started Aug 13 06:44:15 PM PDT 24
Finished Aug 13 06:44:29 PM PDT 24
Peak memory 215004 kb
Host smart-48939b4a-811a-41a7-b6b1-f8436138ad4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212150395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3212150395
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1032641718
Short name T61
Test name
Test status
Simulation time 92019646 ps
CPU time 4.35 seconds
Started Aug 13 06:44:07 PM PDT 24
Finished Aug 13 06:44:16 PM PDT 24
Peak memory 211420 kb
Host smart-3c715ec6-8777-441c-b03d-1f76234e457c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032641718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1032641718
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3897083358
Short name T282
Test name
Test status
Simulation time 1398776801 ps
CPU time 74.76 seconds
Started Aug 13 06:44:30 PM PDT 24
Finished Aug 13 06:45:44 PM PDT 24
Peak memory 228256 kb
Host smart-f609b433-241c-4694-ba76-37672ca9c491
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897083358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3897083358
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.588354083
Short name T193
Test name
Test status
Simulation time 169728199 ps
CPU time 9.75 seconds
Started Aug 13 06:44:09 PM PDT 24
Finished Aug 13 06:44:19 PM PDT 24
Peak memory 212552 kb
Host smart-a45ebdb3-30be-492f-b8d5-0d014d54b446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588354083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.588354083
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3546129599
Short name T120
Test name
Test status
Simulation time 2212913827 ps
CPU time 7 seconds
Started Aug 13 06:44:19 PM PDT 24
Finished Aug 13 06:44:26 PM PDT 24
Peak memory 211488 kb
Host smart-4aa9a21d-9640-4335-a3d3-4ad63b326dfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3546129599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3546129599
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1653200178
Short name T301
Test name
Test status
Simulation time 105122844 ps
CPU time 4.14 seconds
Started Aug 13 06:44:27 PM PDT 24
Finished Aug 13 06:44:31 PM PDT 24
Peak memory 211400 kb
Host smart-a5ef411a-ea26-4dfe-984a-c77f7bebb151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653200178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1653200178
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3571756678
Short name T40
Test name
Test status
Simulation time 7808482899 ps
CPU time 90.35 seconds
Started Aug 13 06:44:07 PM PDT 24
Finished Aug 13 06:45:37 PM PDT 24
Peak memory 238844 kb
Host smart-7ccbd3bd-a115-402d-8309-2151694227a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571756678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3571756678
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.919955668
Short name T181
Test name
Test status
Simulation time 3539208219 ps
CPU time 11.41 seconds
Started Aug 13 06:44:19 PM PDT 24
Finished Aug 13 06:44:31 PM PDT 24
Peak memory 212320 kb
Host smart-201c2054-9985-43a5-9d31-a605c2471776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919955668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.919955668
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2176993536
Short name T252
Test name
Test status
Simulation time 145156509 ps
CPU time 6.47 seconds
Started Aug 13 06:44:31 PM PDT 24
Finished Aug 13 06:44:38 PM PDT 24
Peak memory 211364 kb
Host smart-d5743bd5-384e-4b1b-a103-f54ded700f2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2176993536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2176993536
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1692583906
Short name T189
Test name
Test status
Simulation time 206741421 ps
CPU time 10.3 seconds
Started Aug 13 06:44:03 PM PDT 24
Finished Aug 13 06:44:13 PM PDT 24
Peak memory 211316 kb
Host smart-38adbdeb-b839-4814-ad2e-f81d1be77c7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692583906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1692583906
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2572842586
Short name T286
Test name
Test status
Simulation time 129006634 ps
CPU time 5.13 seconds
Started Aug 13 06:44:32 PM PDT 24
Finished Aug 13 06:44:38 PM PDT 24
Peak memory 211344 kb
Host smart-e2b0175c-d773-40b5-a4dd-d16242ad0d58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572842586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2572842586
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.219439625
Short name T110
Test name
Test status
Simulation time 3049260171 ps
CPU time 72.69 seconds
Started Aug 13 06:44:27 PM PDT 24
Finished Aug 13 06:45:40 PM PDT 24
Peak memory 216120 kb
Host smart-4e92344d-2157-4e43-803b-d10d79e4a47e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219439625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.219439625
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2327643483
Short name T213
Test name
Test status
Simulation time 253781580 ps
CPU time 11.56 seconds
Started Aug 13 06:44:09 PM PDT 24
Finished Aug 13 06:44:20 PM PDT 24
Peak memory 212296 kb
Host smart-6026c881-11a9-4ec6-b154-bcf90c2be7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327643483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2327643483
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1794668644
Short name T217
Test name
Test status
Simulation time 537581022 ps
CPU time 6.54 seconds
Started Aug 13 06:44:16 PM PDT 24
Finished Aug 13 06:44:23 PM PDT 24
Peak memory 211460 kb
Host smart-6e01139a-5ed4-4e30-9d5b-52cb54fda9fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1794668644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1794668644
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3467563123
Short name T185
Test name
Test status
Simulation time 117004143 ps
CPU time 7.66 seconds
Started Aug 13 06:44:22 PM PDT 24
Finished Aug 13 06:44:30 PM PDT 24
Peak memory 211612 kb
Host smart-fb0ab4a4-f950-4863-b2f7-7a08b8ba3e26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467563123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3467563123
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2885374973
Short name T294
Test name
Test status
Simulation time 518313536 ps
CPU time 5.18 seconds
Started Aug 13 06:44:38 PM PDT 24
Finished Aug 13 06:44:43 PM PDT 24
Peak memory 211372 kb
Host smart-4929ed33-c689-43e6-8980-99cd4590d851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885374973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2885374973
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3622677330
Short name T53
Test name
Test status
Simulation time 6189961163 ps
CPU time 105.77 seconds
Started Aug 13 06:44:12 PM PDT 24
Finished Aug 13 06:45:58 PM PDT 24
Peak memory 237016 kb
Host smart-165bb3e2-9af9-427b-9d6a-78cba76dbe83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622677330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3622677330
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.4286657795
Short name T293
Test name
Test status
Simulation time 251409791 ps
CPU time 11.44 seconds
Started Aug 13 06:44:23 PM PDT 24
Finished Aug 13 06:44:34 PM PDT 24
Peak memory 212284 kb
Host smart-4e4f7035-4139-412d-b3a2-f3001235080f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286657795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.4286657795
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.5619542
Short name T64
Test name
Test status
Simulation time 94430514 ps
CPU time 5.49 seconds
Started Aug 13 06:44:16 PM PDT 24
Finished Aug 13 06:44:22 PM PDT 24
Peak memory 211364 kb
Host smart-e369cd73-f73b-4137-878c-1907ea9ac237
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5619542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.5619542
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3866000737
Short name T164
Test name
Test status
Simulation time 728833308 ps
CPU time 8.73 seconds
Started Aug 13 06:44:27 PM PDT 24
Finished Aug 13 06:44:36 PM PDT 24
Peak memory 211540 kb
Host smart-ffad359e-0db8-4e49-ac2c-86af259de749
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866000737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3866000737
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3704347419
Short name T227
Test name
Test status
Simulation time 126838047 ps
CPU time 5.18 seconds
Started Aug 13 06:44:25 PM PDT 24
Finished Aug 13 06:44:30 PM PDT 24
Peak memory 211384 kb
Host smart-89c1dfe9-4683-499a-bac2-be59f8147665
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704347419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3704347419
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2577706178
Short name T243
Test name
Test status
Simulation time 984521242 ps
CPU time 16.34 seconds
Started Aug 13 06:44:38 PM PDT 24
Finished Aug 13 06:44:55 PM PDT 24
Peak memory 212236 kb
Host smart-1f45c882-cd47-4ae5-8b8d-06c19b66ef6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577706178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2577706178
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.353899097
Short name T197
Test name
Test status
Simulation time 988393495 ps
CPU time 5.26 seconds
Started Aug 13 06:44:42 PM PDT 24
Finished Aug 13 06:44:55 PM PDT 24
Peak memory 211416 kb
Host smart-a08ab4fa-0c85-4a80-b5f0-0ed8edb6c0fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=353899097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.353899097
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1129410486
Short name T14
Test name
Test status
Simulation time 376125537 ps
CPU time 21.57 seconds
Started Aug 13 06:44:45 PM PDT 24
Finished Aug 13 06:45:07 PM PDT 24
Peak memory 215408 kb
Host smart-e02e7376-9e8b-438d-960a-164eef5ebd2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129410486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1129410486
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.4038934435
Short name T229
Test name
Test status
Simulation time 87388277 ps
CPU time 4.32 seconds
Started Aug 13 06:44:17 PM PDT 24
Finished Aug 13 06:44:22 PM PDT 24
Peak memory 211404 kb
Host smart-d20b0af1-ffb3-42cf-9d0f-7e6aa79f9012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038934435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.4038934435
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1661599412
Short name T304
Test name
Test status
Simulation time 1436639023 ps
CPU time 93.08 seconds
Started Aug 13 06:44:29 PM PDT 24
Finished Aug 13 06:46:02 PM PDT 24
Peak memory 236684 kb
Host smart-5b4fbd50-aa9b-443d-bfe4-d3e6832ee7a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661599412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1661599412
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3144480802
Short name T320
Test name
Test status
Simulation time 1089350437 ps
CPU time 11.54 seconds
Started Aug 13 06:45:02 PM PDT 24
Finished Aug 13 06:45:14 PM PDT 24
Peak memory 212928 kb
Host smart-e64476ea-9509-4bc4-9325-9d31dd2ebec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144480802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3144480802
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3276695484
Short name T216
Test name
Test status
Simulation time 260665030 ps
CPU time 6.15 seconds
Started Aug 13 06:44:41 PM PDT 24
Finished Aug 13 06:44:51 PM PDT 24
Peak memory 211436 kb
Host smart-c873a3c1-c217-4ce9-b0c1-ac4018bb1164
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3276695484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3276695484
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3678113978
Short name T46
Test name
Test status
Simulation time 1155676179 ps
CPU time 14.37 seconds
Started Aug 13 06:44:25 PM PDT 24
Finished Aug 13 06:44:39 PM PDT 24
Peak memory 214104 kb
Host smart-4b778b24-65a8-4ea1-b28b-37c0cdea81fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678113978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3678113978
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2816296064
Short name T240
Test name
Test status
Simulation time 347740177 ps
CPU time 4.36 seconds
Started Aug 13 06:44:49 PM PDT 24
Finished Aug 13 06:44:54 PM PDT 24
Peak memory 211320 kb
Host smart-33806d5b-8d79-494c-87e8-26e618629517
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816296064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2816296064
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.254921748
Short name T144
Test name
Test status
Simulation time 3351566741 ps
CPU time 183.13 seconds
Started Aug 13 06:44:29 PM PDT 24
Finished Aug 13 06:47:33 PM PDT 24
Peak memory 234328 kb
Host smart-5cdb34d8-ed0b-4f83-8ab7-80c6ed24f08a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254921748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.254921748
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.856182202
Short name T30
Test name
Test status
Simulation time 170567511 ps
CPU time 9.82 seconds
Started Aug 13 06:44:37 PM PDT 24
Finished Aug 13 06:44:47 PM PDT 24
Peak memory 212320 kb
Host smart-13bb4354-f99c-4c55-aba0-2343b60f32ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856182202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.856182202
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1387325095
Short name T47
Test name
Test status
Simulation time 1158425258 ps
CPU time 5.67 seconds
Started Aug 13 06:44:31 PM PDT 24
Finished Aug 13 06:44:42 PM PDT 24
Peak memory 211372 kb
Host smart-abe99e5a-0fe6-4b9a-b75b-e051e548ae93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1387325095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1387325095
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2005974397
Short name T256
Test name
Test status
Simulation time 567883973 ps
CPU time 12.5 seconds
Started Aug 13 06:44:28 PM PDT 24
Finished Aug 13 06:44:41 PM PDT 24
Peak memory 214712 kb
Host smart-9c7456d2-d586-4154-a4ba-e5bc10fa23f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005974397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2005974397
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1396213064
Short name T38
Test name
Test status
Simulation time 87165926 ps
CPU time 4.33 seconds
Started Aug 13 06:44:39 PM PDT 24
Finished Aug 13 06:44:44 PM PDT 24
Peak memory 211404 kb
Host smart-4dda2614-658b-469a-9cf1-14f81c8897a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396213064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1396213064
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3865423272
Short name T302
Test name
Test status
Simulation time 9182208521 ps
CPU time 120.79 seconds
Started Aug 13 06:44:22 PM PDT 24
Finished Aug 13 06:46:23 PM PDT 24
Peak memory 228376 kb
Host smart-9bc5e79b-e92f-47bd-8db9-f2f5265269aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865423272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3865423272
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3069713151
Short name T49
Test name
Test status
Simulation time 170138896 ps
CPU time 9.53 seconds
Started Aug 13 06:44:22 PM PDT 24
Finished Aug 13 06:44:31 PM PDT 24
Peak memory 212200 kb
Host smart-e4063400-6926-4455-93b3-2c60dfdd2324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069713151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3069713151
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3508688530
Short name T209
Test name
Test status
Simulation time 95696606 ps
CPU time 5.4 seconds
Started Aug 13 06:44:31 PM PDT 24
Finished Aug 13 06:44:37 PM PDT 24
Peak memory 211380 kb
Host smart-e24025c4-1140-41b2-89bc-9714dfe17084
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3508688530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3508688530
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2846144876
Short name T183
Test name
Test status
Simulation time 659558632 ps
CPU time 28.21 seconds
Started Aug 13 06:44:20 PM PDT 24
Finished Aug 13 06:44:48 PM PDT 24
Peak memory 215672 kb
Host smart-f797e372-3244-47f3-8556-65367623cfab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846144876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2846144876
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2761515359
Short name T62
Test name
Test status
Simulation time 249859621 ps
CPU time 5.13 seconds
Started Aug 13 06:44:25 PM PDT 24
Finished Aug 13 06:44:30 PM PDT 24
Peak memory 211404 kb
Host smart-490dd756-b658-4e23-9e58-4f1631b209b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761515359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2761515359
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1908068555
Short name T298
Test name
Test status
Simulation time 2145299227 ps
CPU time 136.41 seconds
Started Aug 13 06:44:25 PM PDT 24
Finished Aug 13 06:46:47 PM PDT 24
Peak memory 233756 kb
Host smart-65a07fb2-b7b0-4ac6-936e-3835c17ab5a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908068555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1908068555
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1612401268
Short name T3
Test name
Test status
Simulation time 176933060 ps
CPU time 9.56 seconds
Started Aug 13 06:44:29 PM PDT 24
Finished Aug 13 06:44:38 PM PDT 24
Peak memory 212776 kb
Host smart-162f604c-6f4f-4913-b541-095c4ce669e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612401268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1612401268
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.157943180
Short name T306
Test name
Test status
Simulation time 145811292 ps
CPU time 6.57 seconds
Started Aug 13 06:44:25 PM PDT 24
Finished Aug 13 06:44:31 PM PDT 24
Peak memory 211416 kb
Host smart-89ed16e6-49c6-45d8-bd11-187b9d383e1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=157943180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.157943180
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3533858750
Short name T170
Test name
Test status
Simulation time 405371292 ps
CPU time 21.42 seconds
Started Aug 13 06:44:48 PM PDT 24
Finished Aug 13 06:45:09 PM PDT 24
Peak memory 213488 kb
Host smart-70a2718a-0490-4fd8-a9cc-cdb4f028c1eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533858750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3533858750
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1204052498
Short name T35
Test name
Test status
Simulation time 349691245 ps
CPU time 4.42 seconds
Started Aug 13 06:44:44 PM PDT 24
Finished Aug 13 06:44:49 PM PDT 24
Peak memory 211376 kb
Host smart-184dfa4e-44c1-476f-8e2e-525a4956b388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204052498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1204052498
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1035173419
Short name T161
Test name
Test status
Simulation time 1772400940 ps
CPU time 102.02 seconds
Started Aug 13 06:44:28 PM PDT 24
Finished Aug 13 06:46:10 PM PDT 24
Peak memory 236796 kb
Host smart-5247b043-a29b-4c01-9a70-8a81735ec12e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035173419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1035173419
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1067488615
Short name T236
Test name
Test status
Simulation time 265627540 ps
CPU time 11.52 seconds
Started Aug 13 06:44:28 PM PDT 24
Finished Aug 13 06:44:40 PM PDT 24
Peak memory 212244 kb
Host smart-4d966508-bf4e-4f64-b311-07b602e5a807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067488615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1067488615
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2894235805
Short name T214
Test name
Test status
Simulation time 541018079 ps
CPU time 6.63 seconds
Started Aug 13 06:44:53 PM PDT 24
Finished Aug 13 06:45:00 PM PDT 24
Peak memory 211444 kb
Host smart-9bebbcbe-fe40-4056-9b54-63b177f8f820
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2894235805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2894235805
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.851766444
Short name T114
Test name
Test status
Simulation time 376474869 ps
CPU time 19.82 seconds
Started Aug 13 06:44:36 PM PDT 24
Finished Aug 13 06:44:56 PM PDT 24
Peak memory 215652 kb
Host smart-23cb5470-1466-4117-8c73-90060a4046fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851766444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.851766444
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1841225954
Short name T179
Test name
Test status
Simulation time 146769416 ps
CPU time 5.14 seconds
Started Aug 13 06:44:14 PM PDT 24
Finished Aug 13 06:44:19 PM PDT 24
Peak memory 211272 kb
Host smart-a071a858-0569-498f-acaa-ef5fad2bacbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841225954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1841225954
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.793550278
Short name T50
Test name
Test status
Simulation time 3359569016 ps
CPU time 85.94 seconds
Started Aug 13 06:43:49 PM PDT 24
Finished Aug 13 06:45:15 PM PDT 24
Peak memory 237796 kb
Host smart-320afc72-5e65-425b-86e9-50db155416bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793550278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.793550278
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3980791619
Short name T201
Test name
Test status
Simulation time 665418370 ps
CPU time 9.69 seconds
Started Aug 13 06:43:57 PM PDT 24
Finished Aug 13 06:44:06 PM PDT 24
Peak memory 212164 kb
Host smart-c7a7bf41-7e77-42c0-bf2c-c8351f3d697a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980791619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3980791619
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3683391484
Short name T29
Test name
Test status
Simulation time 637778892 ps
CPU time 56.26 seconds
Started Aug 13 06:44:15 PM PDT 24
Finished Aug 13 06:45:11 PM PDT 24
Peak memory 236672 kb
Host smart-d0460151-b054-46dd-ab1f-03fe7cb2edce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683391484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3683391484
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2131915952
Short name T5
Test name
Test status
Simulation time 264174633 ps
CPU time 6.3 seconds
Started Aug 13 06:43:47 PM PDT 24
Finished Aug 13 06:43:53 PM PDT 24
Peak memory 211488 kb
Host smart-d3062868-3d8a-4873-966b-a0b3a3b5d1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131915952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2131915952
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.99732241
Short name T8
Test name
Test status
Simulation time 1740311565 ps
CPU time 20.26 seconds
Started Aug 13 06:43:58 PM PDT 24
Finished Aug 13 06:44:18 PM PDT 24
Peak memory 214140 kb
Host smart-7bbbf412-cf3f-440f-befb-ebf1185c64eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99732241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.rom_ctrl_stress_all.99732241
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2846599196
Short name T231
Test name
Test status
Simulation time 437017254 ps
CPU time 4.32 seconds
Started Aug 13 06:44:28 PM PDT 24
Finished Aug 13 06:44:32 PM PDT 24
Peak memory 211408 kb
Host smart-91d52f5b-678c-4e48-a627-7403665ba152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846599196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2846599196
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3861671992
Short name T278
Test name
Test status
Simulation time 3131333311 ps
CPU time 93.52 seconds
Started Aug 13 06:44:45 PM PDT 24
Finished Aug 13 06:46:19 PM PDT 24
Peak memory 239924 kb
Host smart-77c4adde-5737-417a-bcaa-c1d3861c5c8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861671992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3861671992
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4105678890
Short name T202
Test name
Test status
Simulation time 177879016 ps
CPU time 9.55 seconds
Started Aug 13 06:44:27 PM PDT 24
Finished Aug 13 06:44:37 PM PDT 24
Peak memory 212276 kb
Host smart-5db0f90d-e693-410d-903d-f9e4087d3076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105678890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4105678890
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3465689238
Short name T224
Test name
Test status
Simulation time 784170520 ps
CPU time 5.63 seconds
Started Aug 13 06:44:45 PM PDT 24
Finished Aug 13 06:44:51 PM PDT 24
Peak memory 211368 kb
Host smart-18583fba-2a44-42b5-8420-953a2d96aedc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3465689238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3465689238
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.19126269
Short name T277
Test name
Test status
Simulation time 3269079182 ps
CPU time 19.4 seconds
Started Aug 13 06:44:19 PM PDT 24
Finished Aug 13 06:44:38 PM PDT 24
Peak memory 214420 kb
Host smart-10e98c89-63cc-44c6-8b3e-5dcf4887ec4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19126269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 30.rom_ctrl_stress_all.19126269
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1042182339
Short name T173
Test name
Test status
Simulation time 227159338 ps
CPU time 4.33 seconds
Started Aug 13 06:44:14 PM PDT 24
Finished Aug 13 06:44:18 PM PDT 24
Peak memory 211384 kb
Host smart-d7eaff9d-336e-48da-9cca-15978188aa31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042182339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1042182339
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4252417962
Short name T21
Test name
Test status
Simulation time 5996994315 ps
CPU time 153.44 seconds
Started Aug 13 06:44:35 PM PDT 24
Finished Aug 13 06:47:09 PM PDT 24
Peak memory 238940 kb
Host smart-aafd3c74-78d4-40e3-95b4-ae05a96719a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252417962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.4252417962
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1288007210
Short name T192
Test name
Test status
Simulation time 400313286 ps
CPU time 5.78 seconds
Started Aug 13 06:44:24 PM PDT 24
Finished Aug 13 06:44:30 PM PDT 24
Peak memory 211428 kb
Host smart-46162720-d4b1-4963-8fb9-488232912bc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1288007210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1288007210
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2472765933
Short name T165
Test name
Test status
Simulation time 1285407783 ps
CPU time 9.28 seconds
Started Aug 13 06:44:37 PM PDT 24
Finished Aug 13 06:44:46 PM PDT 24
Peak memory 211628 kb
Host smart-f5ec0b01-90a2-4769-a3f5-15efb0c12054
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472765933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2472765933
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1610292529
Short name T238
Test name
Test status
Simulation time 132309089 ps
CPU time 5.19 seconds
Started Aug 13 06:44:29 PM PDT 24
Finished Aug 13 06:44:35 PM PDT 24
Peak memory 211348 kb
Host smart-22cd6b76-1ece-4f80-8e3e-e96fe384f485
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610292529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1610292529
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2427380676
Short name T134
Test name
Test status
Simulation time 9170635585 ps
CPU time 173.19 seconds
Started Aug 13 06:44:25 PM PDT 24
Finished Aug 13 06:47:18 PM PDT 24
Peak memory 212688 kb
Host smart-ec81673d-75dd-4781-94dc-3b98451ee1bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427380676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2427380676
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1291277924
Short name T292
Test name
Test status
Simulation time 251584806 ps
CPU time 11.27 seconds
Started Aug 13 06:44:36 PM PDT 24
Finished Aug 13 06:44:48 PM PDT 24
Peak memory 212196 kb
Host smart-79831f85-6c69-4552-a39a-1f1c473b1711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291277924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1291277924
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2999354374
Short name T208
Test name
Test status
Simulation time 399970074 ps
CPU time 5.5 seconds
Started Aug 13 06:44:24 PM PDT 24
Finished Aug 13 06:44:30 PM PDT 24
Peak memory 211428 kb
Host smart-1a75cf47-d76d-4879-bf76-7bc1bbccb4b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2999354374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2999354374
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.377415443
Short name T257
Test name
Test status
Simulation time 114264157 ps
CPU time 8.82 seconds
Started Aug 13 06:44:45 PM PDT 24
Finished Aug 13 06:44:54 PM PDT 24
Peak memory 211236 kb
Host smart-dcf5445a-bc16-4773-8d64-88f239011f1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377415443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.377415443
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1721254700
Short name T12
Test name
Test status
Simulation time 322139342 ps
CPU time 4.3 seconds
Started Aug 13 06:44:30 PM PDT 24
Finished Aug 13 06:44:35 PM PDT 24
Peak memory 211340 kb
Host smart-638dad48-af3f-45bb-a197-775d002a4c70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721254700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1721254700
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4103992431
Short name T267
Test name
Test status
Simulation time 17168629573 ps
CPU time 106.07 seconds
Started Aug 13 06:44:37 PM PDT 24
Finished Aug 13 06:46:23 PM PDT 24
Peak memory 211824 kb
Host smart-ea2286be-1f3f-43ee-a0e7-41c7edd72eef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103992431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.4103992431
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1533984168
Short name T112
Test name
Test status
Simulation time 296911680 ps
CPU time 11.29 seconds
Started Aug 13 06:44:41 PM PDT 24
Finished Aug 13 06:44:52 PM PDT 24
Peak memory 212408 kb
Host smart-ba4f4070-7dc5-46c1-a132-bbf299233623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533984168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1533984168
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.958655306
Short name T200
Test name
Test status
Simulation time 140225498 ps
CPU time 6.4 seconds
Started Aug 13 06:44:34 PM PDT 24
Finished Aug 13 06:44:40 PM PDT 24
Peak memory 211432 kb
Host smart-4bdb7afb-0ef4-4364-a769-d0f785209296
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=958655306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.958655306
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2841096916
Short name T316
Test name
Test status
Simulation time 833613572 ps
CPU time 12.77 seconds
Started Aug 13 06:44:28 PM PDT 24
Finished Aug 13 06:44:41 PM PDT 24
Peak memory 214156 kb
Host smart-d7e775e1-7d1e-4f34-a54a-1ae8730af251
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841096916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2841096916
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2321785113
Short name T311
Test name
Test status
Simulation time 132799744 ps
CPU time 5.3 seconds
Started Aug 13 06:44:33 PM PDT 24
Finished Aug 13 06:44:38 PM PDT 24
Peak memory 211396 kb
Host smart-0f097e49-dbb6-4a70-aa1f-3d186b77cd96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321785113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2321785113
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2776263376
Short name T7
Test name
Test status
Simulation time 925996726 ps
CPU time 11.03 seconds
Started Aug 13 06:44:44 PM PDT 24
Finished Aug 13 06:44:56 PM PDT 24
Peak memory 212496 kb
Host smart-106f144f-5eaa-4828-82e4-4a4a8b043cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776263376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2776263376
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1978553377
Short name T225
Test name
Test status
Simulation time 278060638 ps
CPU time 6.21 seconds
Started Aug 13 06:44:29 PM PDT 24
Finished Aug 13 06:44:36 PM PDT 24
Peak memory 211416 kb
Host smart-75a24a67-2af9-4e64-8f64-3cf6447d1b87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1978553377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1978553377
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2072644870
Short name T109
Test name
Test status
Simulation time 166642332 ps
CPU time 9.02 seconds
Started Aug 13 06:44:45 PM PDT 24
Finished Aug 13 06:44:55 PM PDT 24
Peak memory 211396 kb
Host smart-8350034d-c591-4e76-b1ed-eb942990fb0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072644870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2072644870
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1246316691
Short name T26
Test name
Test status
Simulation time 982621993 ps
CPU time 7.67 seconds
Started Aug 13 06:44:28 PM PDT 24
Finished Aug 13 06:44:35 PM PDT 24
Peak memory 211392 kb
Host smart-86b38210-9e13-4a4b-8cff-7d14b4003fab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246316691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1246316691
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1907883253
Short name T290
Test name
Test status
Simulation time 2608748728 ps
CPU time 112.44 seconds
Started Aug 13 06:44:47 PM PDT 24
Finished Aug 13 06:46:39 PM PDT 24
Peak memory 234936 kb
Host smart-af2e7aa5-a313-4333-881a-1e8c88db496d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907883253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1907883253
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2706814637
Short name T222
Test name
Test status
Simulation time 253427903 ps
CPU time 11.29 seconds
Started Aug 13 06:44:34 PM PDT 24
Finished Aug 13 06:44:46 PM PDT 24
Peak memory 212264 kb
Host smart-87487748-9517-4c5e-9042-0962e27a3f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706814637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2706814637
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1023991942
Short name T4
Test name
Test status
Simulation time 523895471 ps
CPU time 8.69 seconds
Started Aug 13 06:44:56 PM PDT 24
Finished Aug 13 06:45:05 PM PDT 24
Peak memory 211420 kb
Host smart-4c9adb2f-7216-4301-bb56-2c5f488fb15f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1023991942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1023991942
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.121210810
Short name T314
Test name
Test status
Simulation time 4471829489 ps
CPU time 20.46 seconds
Started Aug 13 06:45:04 PM PDT 24
Finished Aug 13 06:45:24 PM PDT 24
Peak memory 217868 kb
Host smart-9bc7eea6-3bcd-45e3-8bfa-26ee31ec4013
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121210810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.121210810
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.52510265
Short name T74
Test name
Test status
Simulation time 464422838 ps
CPU time 5.06 seconds
Started Aug 13 06:44:48 PM PDT 24
Finished Aug 13 06:44:54 PM PDT 24
Peak memory 211392 kb
Host smart-e5e4dbc9-aa1e-4282-b786-8c0d8389b0ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52510265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.52510265
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3076300749
Short name T150
Test name
Test status
Simulation time 3251356550 ps
CPU time 142.18 seconds
Started Aug 13 06:44:47 PM PDT 24
Finished Aug 13 06:47:09 PM PDT 24
Peak memory 236852 kb
Host smart-d82bff58-33b5-46fe-a509-7f1ef05ce518
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076300749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3076300749
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2098251997
Short name T63
Test name
Test status
Simulation time 991998488 ps
CPU time 11.33 seconds
Started Aug 13 06:44:25 PM PDT 24
Finished Aug 13 06:44:36 PM PDT 24
Peak memory 212688 kb
Host smart-0f78e8a0-d771-402b-a2e5-0db6488660d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098251997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2098251997
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.38756134
Short name T89
Test name
Test status
Simulation time 122531463 ps
CPU time 9.25 seconds
Started Aug 13 06:44:25 PM PDT 24
Finished Aug 13 06:44:34 PM PDT 24
Peak memory 211468 kb
Host smart-d4c78462-f7fe-4ef7-8c9b-e7b8dc192916
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38756134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 36.rom_ctrl_stress_all.38756134
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1540330725
Short name T184
Test name
Test status
Simulation time 333471065 ps
CPU time 4.26 seconds
Started Aug 13 06:44:21 PM PDT 24
Finished Aug 13 06:44:25 PM PDT 24
Peak memory 211316 kb
Host smart-a567e44f-227d-41dc-844f-f3db229fe730
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540330725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1540330725
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1533393973
Short name T44
Test name
Test status
Simulation time 1654157566 ps
CPU time 105.9 seconds
Started Aug 13 06:44:44 PM PDT 24
Finished Aug 13 06:46:30 PM PDT 24
Peak memory 228448 kb
Host smart-0bbf52db-c17c-4e8b-afe0-cbadfcbcfb70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533393973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1533393973
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.198205601
Short name T11
Test name
Test status
Simulation time 181226413 ps
CPU time 9.59 seconds
Started Aug 13 06:44:42 PM PDT 24
Finished Aug 13 06:44:52 PM PDT 24
Peak memory 212324 kb
Host smart-19be5cfc-155c-4910-8182-8ed50fbc44e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198205601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.198205601
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1184546353
Short name T15
Test name
Test status
Simulation time 100359206 ps
CPU time 5.53 seconds
Started Aug 13 06:44:24 PM PDT 24
Finished Aug 13 06:44:30 PM PDT 24
Peak memory 211464 kb
Host smart-5ee75ad7-a14e-4c60-9899-afba8628e698
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1184546353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1184546353
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3553874134
Short name T205
Test name
Test status
Simulation time 4000018593 ps
CPU time 18.13 seconds
Started Aug 13 06:44:41 PM PDT 24
Finished Aug 13 06:44:59 PM PDT 24
Peak memory 215184 kb
Host smart-38d1f909-188a-4aa2-a6a6-f6210680803c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553874134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3553874134
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.207060804
Short name T249
Test name
Test status
Simulation time 773153422 ps
CPU time 5.26 seconds
Started Aug 13 06:44:30 PM PDT 24
Finished Aug 13 06:44:36 PM PDT 24
Peak memory 211420 kb
Host smart-4f2fa105-5544-48f0-bc83-94e594fa28f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207060804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.207060804
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4091503962
Short name T296
Test name
Test status
Simulation time 2117058233 ps
CPU time 113.48 seconds
Started Aug 13 06:44:52 PM PDT 24
Finished Aug 13 06:46:46 PM PDT 24
Peak memory 237764 kb
Host smart-705a10da-fd1a-45c4-9588-c3d0c13c1769
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091503962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4091503962
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1356135009
Short name T169
Test name
Test status
Simulation time 3533835005 ps
CPU time 11.47 seconds
Started Aug 13 06:44:34 PM PDT 24
Finished Aug 13 06:44:45 PM PDT 24
Peak memory 212324 kb
Host smart-07e9481c-b2fc-43cb-8a54-f9bb0c9e11c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356135009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1356135009
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1382278292
Short name T198
Test name
Test status
Simulation time 147288510 ps
CPU time 6.96 seconds
Started Aug 13 06:44:26 PM PDT 24
Finished Aug 13 06:44:34 PM PDT 24
Peak memory 211392 kb
Host smart-9196ec12-ba4d-475b-85bd-930eef6eaca5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1382278292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1382278292
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3913161819
Short name T180
Test name
Test status
Simulation time 561421073 ps
CPU time 16.05 seconds
Started Aug 13 06:44:39 PM PDT 24
Finished Aug 13 06:44:56 PM PDT 24
Peak memory 213832 kb
Host smart-ecbf5cfe-4693-4128-880c-bcf9cf7538d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913161819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3913161819
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2051891067
Short name T211
Test name
Test status
Simulation time 320687900 ps
CPU time 4.4 seconds
Started Aug 13 06:44:30 PM PDT 24
Finished Aug 13 06:44:35 PM PDT 24
Peak memory 211412 kb
Host smart-fe0d35ab-9a64-4689-b52e-7af4fc7dfc7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051891067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2051891067
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.821960084
Short name T288
Test name
Test status
Simulation time 1501995457 ps
CPU time 85.61 seconds
Started Aug 13 06:44:33 PM PDT 24
Finished Aug 13 06:45:59 PM PDT 24
Peak memory 212672 kb
Host smart-9b2c0f8d-a4e8-4a42-92e7-c32231b7ab8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821960084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.821960084
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.473063326
Short name T261
Test name
Test status
Simulation time 499259453 ps
CPU time 11.09 seconds
Started Aug 13 06:44:49 PM PDT 24
Finished Aug 13 06:45:00 PM PDT 24
Peak memory 212300 kb
Host smart-520644ef-565c-45e5-bfe4-a27dc7c73c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473063326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.473063326
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.343484081
Short name T20
Test name
Test status
Simulation time 437304243 ps
CPU time 5.74 seconds
Started Aug 13 06:44:44 PM PDT 24
Finished Aug 13 06:44:50 PM PDT 24
Peak memory 211416 kb
Host smart-a348b779-837f-4c81-9722-fc7279c5b105
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=343484081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.343484081
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2537727508
Short name T176
Test name
Test status
Simulation time 447270419 ps
CPU time 16.62 seconds
Started Aug 13 06:44:55 PM PDT 24
Finished Aug 13 06:45:12 PM PDT 24
Peak memory 214712 kb
Host smart-02be6c93-932a-42c4-af61-97c325e37e3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537727508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2537727508
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2344420048
Short name T160
Test name
Test status
Simulation time 86203848 ps
CPU time 4.32 seconds
Started Aug 13 06:44:28 PM PDT 24
Finished Aug 13 06:44:33 PM PDT 24
Peak memory 211408 kb
Host smart-1705344d-956d-40a5-9e3e-57df72ea2670
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344420048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2344420048
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3678317895
Short name T242
Test name
Test status
Simulation time 3850370698 ps
CPU time 92.15 seconds
Started Aug 13 06:44:11 PM PDT 24
Finished Aug 13 06:45:44 PM PDT 24
Peak memory 237760 kb
Host smart-c099311d-2c39-4d2c-b0eb-bfae3d64fa20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678317895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3678317895
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.662512854
Short name T245
Test name
Test status
Simulation time 338442670 ps
CPU time 10.03 seconds
Started Aug 13 06:43:58 PM PDT 24
Finished Aug 13 06:44:08 PM PDT 24
Peak memory 212592 kb
Host smart-9d5db4a6-4982-4813-97bb-6e465196693f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662512854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.662512854
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3726753536
Short name T233
Test name
Test status
Simulation time 145715591 ps
CPU time 6.85 seconds
Started Aug 13 06:44:00 PM PDT 24
Finished Aug 13 06:44:07 PM PDT 24
Peak memory 211448 kb
Host smart-fdef7ffa-788d-4506-9c0a-c77f7a3e4bf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3726753536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3726753536
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2897821430
Short name T24
Test name
Test status
Simulation time 359553563 ps
CPU time 102.94 seconds
Started Aug 13 06:44:16 PM PDT 24
Finished Aug 13 06:46:00 PM PDT 24
Peak memory 236688 kb
Host smart-027694e0-4d99-400c-870d-95c55bb30b34
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897821430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2897821430
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1678233559
Short name T266
Test name
Test status
Simulation time 135623432 ps
CPU time 6.69 seconds
Started Aug 13 06:44:04 PM PDT 24
Finished Aug 13 06:44:11 PM PDT 24
Peak memory 211400 kb
Host smart-c2242166-355d-4c26-85a2-a5d2420ebeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678233559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1678233559
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2950781383
Short name T86
Test name
Test status
Simulation time 831890020 ps
CPU time 10.79 seconds
Started Aug 13 06:43:59 PM PDT 24
Finished Aug 13 06:44:10 PM PDT 24
Peak memory 214564 kb
Host smart-fe959a1d-5ab5-403c-bf1d-26c890f5d38a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950781383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2950781383
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3325556932
Short name T291
Test name
Test status
Simulation time 168975976 ps
CPU time 4.27 seconds
Started Aug 13 06:44:51 PM PDT 24
Finished Aug 13 06:44:56 PM PDT 24
Peak memory 211352 kb
Host smart-677d0dd1-1c2d-44a7-b32e-a0981d74ad4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325556932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3325556932
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4242541471
Short name T153
Test name
Test status
Simulation time 5016402113 ps
CPU time 130.36 seconds
Started Aug 13 06:44:37 PM PDT 24
Finished Aug 13 06:46:47 PM PDT 24
Peak memory 237856 kb
Host smart-e087f252-5253-4cb7-a2d5-238ebb541890
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242541471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4242541471
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.713000258
Short name T244
Test name
Test status
Simulation time 598231393 ps
CPU time 9.39 seconds
Started Aug 13 06:44:50 PM PDT 24
Finished Aug 13 06:45:00 PM PDT 24
Peak memory 212352 kb
Host smart-b5c8ff48-6c01-455b-bce1-45ee7a8e8d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713000258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.713000258
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2888972178
Short name T65
Test name
Test status
Simulation time 140387180 ps
CPU time 6.46 seconds
Started Aug 13 06:44:33 PM PDT 24
Finished Aug 13 06:44:40 PM PDT 24
Peak memory 211428 kb
Host smart-90e717d1-1f01-4d80-85b0-83b14462ca62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2888972178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2888972178
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3750582794
Short name T172
Test name
Test status
Simulation time 836629523 ps
CPU time 20.79 seconds
Started Aug 13 06:44:50 PM PDT 24
Finished Aug 13 06:45:11 PM PDT 24
Peak memory 214336 kb
Host smart-19f077b2-23a6-4845-afbf-cf45d034884b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750582794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3750582794
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3204386352
Short name T115
Test name
Test status
Simulation time 186249212 ps
CPU time 5.09 seconds
Started Aug 13 06:45:00 PM PDT 24
Finished Aug 13 06:45:06 PM PDT 24
Peak memory 211392 kb
Host smart-35907c61-7abb-48d4-8982-a86cf82125e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204386352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3204386352
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2662000505
Short name T310
Test name
Test status
Simulation time 13828582809 ps
CPU time 169.91 seconds
Started Aug 13 06:44:46 PM PDT 24
Finished Aug 13 06:47:36 PM PDT 24
Peak memory 234504 kb
Host smart-d8ea31be-96e8-486f-945c-8202644c42ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662000505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2662000505
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2718391264
Short name T187
Test name
Test status
Simulation time 700230336 ps
CPU time 9.47 seconds
Started Aug 13 06:44:32 PM PDT 24
Finished Aug 13 06:44:42 PM PDT 24
Peak memory 212368 kb
Host smart-25c226f3-38be-4acf-aa7c-62f417b37c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718391264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2718391264
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2485558004
Short name T247
Test name
Test status
Simulation time 1311486316 ps
CPU time 6.08 seconds
Started Aug 13 06:44:30 PM PDT 24
Finished Aug 13 06:44:37 PM PDT 24
Peak memory 211400 kb
Host smart-1f422ba1-67a0-4c9f-a5bc-696fa7e6f186
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2485558004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2485558004
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2953965010
Short name T34
Test name
Test status
Simulation time 2425926238 ps
CPU time 26.01 seconds
Started Aug 13 06:44:40 PM PDT 24
Finished Aug 13 06:45:06 PM PDT 24
Peak memory 213060 kb
Host smart-06c1e9af-8a33-4f9a-b178-3c59f79fe62b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953965010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2953965010
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.629777313
Short name T299
Test name
Test status
Simulation time 175599544 ps
CPU time 4.22 seconds
Started Aug 13 06:44:31 PM PDT 24
Finished Aug 13 06:44:35 PM PDT 24
Peak memory 211364 kb
Host smart-fd5fbe3d-018d-47ca-99a1-1feb8d5675ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629777313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.629777313
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2853052179
Short name T274
Test name
Test status
Simulation time 7994143106 ps
CPU time 120.97 seconds
Started Aug 13 06:44:46 PM PDT 24
Finished Aug 13 06:46:47 PM PDT 24
Peak memory 237824 kb
Host smart-da2355af-9f7a-4511-8595-bb921b46d5e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853052179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2853052179
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3004224926
Short name T226
Test name
Test status
Simulation time 261418491 ps
CPU time 11.09 seconds
Started Aug 13 06:44:30 PM PDT 24
Finished Aug 13 06:44:41 PM PDT 24
Peak memory 212596 kb
Host smart-287bc7c9-7b0e-4388-b659-4c750d1dceeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004224926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3004224926
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1171067424
Short name T48
Test name
Test status
Simulation time 98180642 ps
CPU time 5.42 seconds
Started Aug 13 06:44:38 PM PDT 24
Finished Aug 13 06:44:44 PM PDT 24
Peak memory 211280 kb
Host smart-3a249986-6206-4de0-bcd4-23e8a5c0701b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1171067424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1171067424
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.453145174
Short name T166
Test name
Test status
Simulation time 510048826 ps
CPU time 15.4 seconds
Started Aug 13 06:44:31 PM PDT 24
Finished Aug 13 06:44:47 PM PDT 24
Peak memory 213120 kb
Host smart-32c8beed-2f85-446a-9077-dcd0cf480c0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453145174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.453145174
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1858429179
Short name T16
Test name
Test status
Simulation time 134520845 ps
CPU time 5.06 seconds
Started Aug 13 06:44:36 PM PDT 24
Finished Aug 13 06:44:41 PM PDT 24
Peak memory 211408 kb
Host smart-f7357b4a-3529-4816-930a-1769116a2da4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858429179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1858429179
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2818446814
Short name T268
Test name
Test status
Simulation time 4629259597 ps
CPU time 106.82 seconds
Started Aug 13 06:44:47 PM PDT 24
Finished Aug 13 06:46:34 PM PDT 24
Peak memory 224820 kb
Host smart-88814e02-24b2-45ca-9fb0-d09d55fc5b1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818446814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2818446814
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3730361601
Short name T199
Test name
Test status
Simulation time 1244457231 ps
CPU time 11.39 seconds
Started Aug 13 06:44:35 PM PDT 24
Finished Aug 13 06:44:47 PM PDT 24
Peak memory 212352 kb
Host smart-df72d006-d8b0-4112-8756-4b104f241964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730361601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3730361601
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1525407208
Short name T195
Test name
Test status
Simulation time 134929817 ps
CPU time 6.4 seconds
Started Aug 13 06:45:12 PM PDT 24
Finished Aug 13 06:45:19 PM PDT 24
Peak memory 211448 kb
Host smart-b62e8448-141c-4995-9bf1-cafbf9f32e87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1525407208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1525407208
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1744010418
Short name T157
Test name
Test status
Simulation time 711951206 ps
CPU time 12 seconds
Started Aug 13 06:44:31 PM PDT 24
Finished Aug 13 06:44:43 PM PDT 24
Peak memory 214192 kb
Host smart-59724a8a-7bbc-41b9-a490-da19b3c337ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744010418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1744010418
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1743533768
Short name T308
Test name
Test status
Simulation time 87302336 ps
CPU time 4.41 seconds
Started Aug 13 06:44:33 PM PDT 24
Finished Aug 13 06:44:38 PM PDT 24
Peak memory 211352 kb
Host smart-7977ed14-636d-4533-8b9a-ff9ed2bdfbe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743533768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1743533768
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3648309368
Short name T39
Test name
Test status
Simulation time 2074878410 ps
CPU time 126.93 seconds
Started Aug 13 06:44:44 PM PDT 24
Finished Aug 13 06:46:51 PM PDT 24
Peak memory 234912 kb
Host smart-9bce67ad-284b-4102-884c-8ea70adccd1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648309368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3648309368
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.246424776
Short name T196
Test name
Test status
Simulation time 254288570 ps
CPU time 11.22 seconds
Started Aug 13 06:44:31 PM PDT 24
Finished Aug 13 06:44:43 PM PDT 24
Peak memory 212416 kb
Host smart-1997b67a-df96-4afe-84a1-afa29702c4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246424776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.246424776
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2381389336
Short name T108
Test name
Test status
Simulation time 142789930 ps
CPU time 6.47 seconds
Started Aug 13 06:45:03 PM PDT 24
Finished Aug 13 06:45:09 PM PDT 24
Peak memory 211368 kb
Host smart-37a5b11a-c835-423f-ae6e-3444b451efe2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2381389336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2381389336
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2288628138
Short name T309
Test name
Test status
Simulation time 276257583 ps
CPU time 15.29 seconds
Started Aug 13 06:44:29 PM PDT 24
Finished Aug 13 06:44:45 PM PDT 24
Peak memory 213840 kb
Host smart-1e191631-a493-4492-8bd9-311ce8fecf3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288628138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2288628138
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.104541461
Short name T37
Test name
Test status
Simulation time 86158226 ps
CPU time 4.32 seconds
Started Aug 13 06:45:05 PM PDT 24
Finished Aug 13 06:45:20 PM PDT 24
Peak memory 211396 kb
Host smart-e88de89d-4e20-4590-bcd6-92e39bc35480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104541461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.104541461
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1771842062
Short name T143
Test name
Test status
Simulation time 7164719411 ps
CPU time 109.14 seconds
Started Aug 13 06:44:53 PM PDT 24
Finished Aug 13 06:46:42 PM PDT 24
Peak memory 236692 kb
Host smart-7b326d06-bf1a-4a33-b870-d695cd0c5494
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771842062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1771842062
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2033004381
Short name T32
Test name
Test status
Simulation time 994963331 ps
CPU time 11.27 seconds
Started Aug 13 06:44:34 PM PDT 24
Finished Aug 13 06:44:45 PM PDT 24
Peak memory 212276 kb
Host smart-5177b98f-c032-4899-8c3a-621a8460c005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033004381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2033004381
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2401920200
Short name T221
Test name
Test status
Simulation time 349358675 ps
CPU time 5.75 seconds
Started Aug 13 06:44:45 PM PDT 24
Finished Aug 13 06:44:50 PM PDT 24
Peak memory 211424 kb
Host smart-299131af-afa4-4e3b-9061-c463789343aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2401920200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2401920200
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1910012830
Short name T87
Test name
Test status
Simulation time 388505849 ps
CPU time 10.63 seconds
Started Aug 13 06:44:32 PM PDT 24
Finished Aug 13 06:44:43 PM PDT 24
Peak memory 213484 kb
Host smart-8e4f8cd7-15a0-4418-ae2d-e5bb1260c89a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910012830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1910012830
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.4093464805
Short name T250
Test name
Test status
Simulation time 129213652 ps
CPU time 5.48 seconds
Started Aug 13 06:44:56 PM PDT 24
Finished Aug 13 06:45:01 PM PDT 24
Peak memory 211396 kb
Host smart-d7d7b882-bced-4e6b-9d1c-949e40a0536c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093464805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.4093464805
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.286635017
Short name T312
Test name
Test status
Simulation time 3126839140 ps
CPU time 108.88 seconds
Started Aug 13 06:44:32 PM PDT 24
Finished Aug 13 06:46:20 PM PDT 24
Peak memory 228648 kb
Host smart-bf8fb1a7-7855-43b0-95b0-1e5893101215
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286635017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.286635017
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2621860733
Short name T289
Test name
Test status
Simulation time 173938245 ps
CPU time 9.12 seconds
Started Aug 13 06:44:50 PM PDT 24
Finished Aug 13 06:45:00 PM PDT 24
Peak memory 212208 kb
Host smart-69392a6e-d9d8-4108-a12b-51db3c72fff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621860733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2621860733
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3017385805
Short name T228
Test name
Test status
Simulation time 1043614530 ps
CPU time 5.68 seconds
Started Aug 13 06:44:50 PM PDT 24
Finished Aug 13 06:44:56 PM PDT 24
Peak memory 211364 kb
Host smart-cd93e2a9-8ea3-4539-a897-73968cf2940b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3017385805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3017385805
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.520947513
Short name T136
Test name
Test status
Simulation time 644498967 ps
CPU time 8.02 seconds
Started Aug 13 06:44:47 PM PDT 24
Finished Aug 13 06:44:55 PM PDT 24
Peak memory 212356 kb
Host smart-e5bb0dac-9ccc-4f3b-8931-57fc574efea9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520947513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.520947513
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3747872729
Short name T248
Test name
Test status
Simulation time 87788061 ps
CPU time 4.29 seconds
Started Aug 13 06:44:36 PM PDT 24
Finished Aug 13 06:44:41 PM PDT 24
Peak memory 211328 kb
Host smart-e85acb73-3fc6-45f3-bb0b-d8f9ed5b0042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747872729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3747872729
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2404915021
Short name T175
Test name
Test status
Simulation time 639147240 ps
CPU time 58.92 seconds
Started Aug 13 06:44:34 PM PDT 24
Finished Aug 13 06:45:33 PM PDT 24
Peak memory 227084 kb
Host smart-33cad3b1-cab2-456d-8b5d-1cb19db6d73a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404915021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2404915021
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2464232425
Short name T219
Test name
Test status
Simulation time 334921503 ps
CPU time 9.13 seconds
Started Aug 13 06:44:52 PM PDT 24
Finished Aug 13 06:45:02 PM PDT 24
Peak memory 212280 kb
Host smart-b68fd240-a4f0-48bb-9ad7-85f639ec3eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464232425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2464232425
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3275568868
Short name T141
Test name
Test status
Simulation time 139356320 ps
CPU time 6.73 seconds
Started Aug 13 06:44:51 PM PDT 24
Finished Aug 13 06:44:58 PM PDT 24
Peak memory 211464 kb
Host smart-268b3d8c-6ac3-44f2-9108-3193095874ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3275568868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3275568868
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2683221999
Short name T66
Test name
Test status
Simulation time 309186658 ps
CPU time 14.77 seconds
Started Aug 13 06:44:48 PM PDT 24
Finished Aug 13 06:45:03 PM PDT 24
Peak memory 214472 kb
Host smart-4e5e78f8-138b-42e6-bcd7-366c24b3ad7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683221999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2683221999
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3809114813
Short name T163
Test name
Test status
Simulation time 346262880 ps
CPU time 4.02 seconds
Started Aug 13 06:44:55 PM PDT 24
Finished Aug 13 06:44:59 PM PDT 24
Peak memory 211260 kb
Host smart-43156975-1fe7-43b3-9510-b2a4e8ccc006
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809114813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3809114813
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2786914261
Short name T284
Test name
Test status
Simulation time 6903689887 ps
CPU time 99.26 seconds
Started Aug 13 06:44:27 PM PDT 24
Finished Aug 13 06:46:07 PM PDT 24
Peak memory 213044 kb
Host smart-f777be06-4649-427c-b847-13570012a83c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786914261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2786914261
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.434902454
Short name T318
Test name
Test status
Simulation time 861586210 ps
CPU time 11.07 seconds
Started Aug 13 06:44:39 PM PDT 24
Finished Aug 13 06:44:50 PM PDT 24
Peak memory 211448 kb
Host smart-8a0607ef-6bd4-4281-93b9-6c2563f64f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434902454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.434902454
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1846926265
Short name T275
Test name
Test status
Simulation time 145041520 ps
CPU time 6.41 seconds
Started Aug 13 06:44:33 PM PDT 24
Finished Aug 13 06:44:39 PM PDT 24
Peak memory 211272 kb
Host smart-3c19278b-034c-486e-bd4a-228db697190a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1846926265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1846926265
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.715881078
Short name T253
Test name
Test status
Simulation time 631082313 ps
CPU time 16.17 seconds
Started Aug 13 06:44:34 PM PDT 24
Finished Aug 13 06:44:50 PM PDT 24
Peak memory 213940 kb
Host smart-409cd0e2-9c01-4aca-b090-15a0b40ecad0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715881078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.715881078
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1837957776
Short name T177
Test name
Test status
Simulation time 495881516 ps
CPU time 5.01 seconds
Started Aug 13 06:44:35 PM PDT 24
Finished Aug 13 06:44:40 PM PDT 24
Peak memory 211408 kb
Host smart-7182dc53-433b-4271-b7da-507738037316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837957776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1837957776
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1740030793
Short name T313
Test name
Test status
Simulation time 3938852724 ps
CPU time 77.09 seconds
Started Aug 13 06:45:01 PM PDT 24
Finished Aug 13 06:46:18 PM PDT 24
Peak memory 240580 kb
Host smart-fe5dae8b-b54d-4964-a0b5-e4ed0e702135
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740030793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1740030793
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3307843641
Short name T159
Test name
Test status
Simulation time 517939596 ps
CPU time 11.31 seconds
Started Aug 13 06:44:36 PM PDT 24
Finished Aug 13 06:44:47 PM PDT 24
Peak memory 212252 kb
Host smart-0858add8-7210-4e84-a43c-b7fd7818a4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307843641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3307843641
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.431046416
Short name T215
Test name
Test status
Simulation time 98131030 ps
CPU time 5.7 seconds
Started Aug 13 06:44:38 PM PDT 24
Finished Aug 13 06:44:44 PM PDT 24
Peak memory 211408 kb
Host smart-148cf662-53b5-4cea-821f-93ab69dedc2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=431046416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.431046416
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.4177650033
Short name T255
Test name
Test status
Simulation time 251290050 ps
CPU time 5.45 seconds
Started Aug 13 06:44:04 PM PDT 24
Finished Aug 13 06:44:10 PM PDT 24
Peak memory 211388 kb
Host smart-43543292-4ca6-47af-94e1-94ad6c291cba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177650033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.4177650033
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1341995525
Short name T287
Test name
Test status
Simulation time 3402129993 ps
CPU time 148.57 seconds
Started Aug 13 06:44:11 PM PDT 24
Finished Aug 13 06:46:39 PM PDT 24
Peak memory 214864 kb
Host smart-68c1d5ad-9e84-46d5-9acc-b2008c6abd75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341995525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1341995525
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1798449499
Short name T237
Test name
Test status
Simulation time 889869769 ps
CPU time 11 seconds
Started Aug 13 06:44:14 PM PDT 24
Finished Aug 13 06:44:25 PM PDT 24
Peak memory 212256 kb
Host smart-844962d3-11ee-4539-942c-98c3ddad06c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798449499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1798449499
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3814375232
Short name T140
Test name
Test status
Simulation time 140442203 ps
CPU time 6.7 seconds
Started Aug 13 06:43:59 PM PDT 24
Finished Aug 13 06:44:06 PM PDT 24
Peak memory 211556 kb
Host smart-acc213e1-2673-4145-8b84-e7a17e8bd34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814375232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3814375232
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1964242858
Short name T152
Test name
Test status
Simulation time 696475460 ps
CPU time 11.48 seconds
Started Aug 13 06:44:06 PM PDT 24
Finished Aug 13 06:44:17 PM PDT 24
Peak memory 211628 kb
Host smart-98e64b06-dac2-4c21-8207-b3e320110e6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964242858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1964242858
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3010147005
Short name T246
Test name
Test status
Simulation time 249271208 ps
CPU time 5.14 seconds
Started Aug 13 06:44:22 PM PDT 24
Finished Aug 13 06:44:27 PM PDT 24
Peak memory 211360 kb
Host smart-056894ee-1b78-4450-96ca-5c36157094ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010147005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3010147005
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4245631780
Short name T51
Test name
Test status
Simulation time 8703406826 ps
CPU time 131.61 seconds
Started Aug 13 06:44:12 PM PDT 24
Finished Aug 13 06:46:26 PM PDT 24
Peak memory 236800 kb
Host smart-697da2d9-fc21-43c8-ad54-c1dd21118b09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245631780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.4245631780
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1656354206
Short name T281
Test name
Test status
Simulation time 264143978 ps
CPU time 11.36 seconds
Started Aug 13 06:44:08 PM PDT 24
Finished Aug 13 06:44:20 PM PDT 24
Peak memory 212252 kb
Host smart-9345df13-aeb3-40ef-8204-bc2455af294c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656354206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1656354206
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3656603443
Short name T139
Test name
Test status
Simulation time 3847600807 ps
CPU time 9.01 seconds
Started Aug 13 06:44:20 PM PDT 24
Finished Aug 13 06:44:29 PM PDT 24
Peak memory 211456 kb
Host smart-7052d01b-76a8-4600-8a6b-058a7a72503d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3656603443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3656603443
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3387743155
Short name T241
Test name
Test status
Simulation time 97403499 ps
CPU time 5.72 seconds
Started Aug 13 06:44:14 PM PDT 24
Finished Aug 13 06:44:20 PM PDT 24
Peak memory 211428 kb
Host smart-e2a00d57-d5f9-4b66-8c04-95ec4575d9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387743155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3387743155
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3691846460
Short name T280
Test name
Test status
Simulation time 734026015 ps
CPU time 11.64 seconds
Started Aug 13 06:43:55 PM PDT 24
Finished Aug 13 06:44:06 PM PDT 24
Peak memory 213632 kb
Host smart-717567ac-3b01-4eb6-94d5-d88e14e971fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691846460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3691846460
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1653868065
Short name T283
Test name
Test status
Simulation time 132683217 ps
CPU time 5.44 seconds
Started Aug 13 06:44:04 PM PDT 24
Finished Aug 13 06:44:09 PM PDT 24
Peak memory 211388 kb
Host smart-4cf8a4ed-a932-4f3c-8fbf-1453c9634353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653868065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1653868065
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3101735478
Short name T43
Test name
Test status
Simulation time 1583077726 ps
CPU time 85.98 seconds
Started Aug 13 06:44:09 PM PDT 24
Finished Aug 13 06:45:35 PM PDT 24
Peak memory 236756 kb
Host smart-570d8d8d-a38e-4d97-98c5-73b1afedfe17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101735478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3101735478
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3133881775
Short name T265
Test name
Test status
Simulation time 1040728059 ps
CPU time 11.16 seconds
Started Aug 13 06:44:18 PM PDT 24
Finished Aug 13 06:44:30 PM PDT 24
Peak memory 212292 kb
Host smart-8edc8860-5635-47ad-a3f0-f94c79a6ed93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133881775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3133881775
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2449356499
Short name T194
Test name
Test status
Simulation time 279711800 ps
CPU time 6.3 seconds
Started Aug 13 06:44:23 PM PDT 24
Finished Aug 13 06:44:30 PM PDT 24
Peak memory 211392 kb
Host smart-a758ac01-c02f-4163-9dde-e98bb18043e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2449356499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2449356499
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1112341022
Short name T167
Test name
Test status
Simulation time 900332107 ps
CPU time 6.3 seconds
Started Aug 13 06:44:15 PM PDT 24
Finished Aug 13 06:44:21 PM PDT 24
Peak memory 210616 kb
Host smart-b2a70c94-5103-444f-9bb9-22e3bc8d6ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112341022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1112341022
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3708346070
Short name T279
Test name
Test status
Simulation time 309631044 ps
CPU time 14.82 seconds
Started Aug 13 06:44:02 PM PDT 24
Finished Aug 13 06:44:17 PM PDT 24
Peak memory 214168 kb
Host smart-a7d288a5-3dca-437b-870a-23306d562344
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708346070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3708346070
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2815839756
Short name T25
Test name
Test status
Simulation time 132358902 ps
CPU time 5.41 seconds
Started Aug 13 06:44:04 PM PDT 24
Finished Aug 13 06:44:09 PM PDT 24
Peak memory 211388 kb
Host smart-7816804a-1b3f-4a8b-a13e-7bd1f7a6a560
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815839756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2815839756
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2283042242
Short name T45
Test name
Test status
Simulation time 2583576966 ps
CPU time 122.95 seconds
Started Aug 13 06:44:16 PM PDT 24
Finished Aug 13 06:46:19 PM PDT 24
Peak memory 225056 kb
Host smart-6b6f19de-a5bd-4cbd-89f5-88ac5b681ad3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283042242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2283042242
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1692775928
Short name T210
Test name
Test status
Simulation time 345126614 ps
CPU time 9.7 seconds
Started Aug 13 06:44:08 PM PDT 24
Finished Aug 13 06:44:18 PM PDT 24
Peak memory 212220 kb
Host smart-b81ee254-0d14-4a28-aec9-e1ef60b3e746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692775928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1692775928
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.4252167722
Short name T203
Test name
Test status
Simulation time 491160466 ps
CPU time 6.5 seconds
Started Aug 13 06:44:16 PM PDT 24
Finished Aug 13 06:44:23 PM PDT 24
Peak memory 211404 kb
Host smart-7248e442-bd5e-48eb-8963-84dd46eae2b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4252167722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.4252167722
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2579543577
Short name T259
Test name
Test status
Simulation time 277990948 ps
CPU time 6.65 seconds
Started Aug 13 06:44:09 PM PDT 24
Finished Aug 13 06:44:16 PM PDT 24
Peak memory 211496 kb
Host smart-8bf86af0-715c-4ffb-8f81-dc51cc88c3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579543577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2579543577
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3067520435
Short name T151
Test name
Test status
Simulation time 351337245 ps
CPU time 17.68 seconds
Started Aug 13 06:44:04 PM PDT 24
Finished Aug 13 06:44:22 PM PDT 24
Peak memory 216188 kb
Host smart-049fcbc5-3499-429a-84d6-5fd8bcc02186
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067520435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3067520435
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1940062981
Short name T264
Test name
Test status
Simulation time 135540986 ps
CPU time 5.24 seconds
Started Aug 13 06:44:04 PM PDT 24
Finished Aug 13 06:44:09 PM PDT 24
Peak memory 211408 kb
Host smart-b2ba9779-923e-4a79-9101-3dfa0959eb25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940062981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1940062981
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.742537098
Short name T319
Test name
Test status
Simulation time 8918702023 ps
CPU time 137.8 seconds
Started Aug 13 06:44:07 PM PDT 24
Finished Aug 13 06:46:25 PM PDT 24
Peak memory 236700 kb
Host smart-b6f32c6a-b432-44f6-a6a0-81eee12f7926
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742537098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.742537098
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.596879496
Short name T171
Test name
Test status
Simulation time 259366748 ps
CPU time 11.43 seconds
Started Aug 13 06:44:14 PM PDT 24
Finished Aug 13 06:44:25 PM PDT 24
Peak memory 212472 kb
Host smart-3a1af91e-4e19-4528-a734-c4b0e7245c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596879496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.596879496
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.66977624
Short name T137
Test name
Test status
Simulation time 1287838754 ps
CPU time 5.5 seconds
Started Aug 13 06:44:03 PM PDT 24
Finished Aug 13 06:44:09 PM PDT 24
Peak memory 211428 kb
Host smart-1f035e0d-e608-49ab-beec-d17de7068642
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66977624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.66977624
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1686840378
Short name T254
Test name
Test status
Simulation time 536708508 ps
CPU time 6.74 seconds
Started Aug 13 06:44:09 PM PDT 24
Finished Aug 13 06:44:16 PM PDT 24
Peak memory 211748 kb
Host smart-4b8b69f7-120f-4bcd-9f6c-54f73887efc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686840378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1686840378
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1450411023
Short name T251
Test name
Test status
Simulation time 493967024 ps
CPU time 7.89 seconds
Started Aug 13 06:44:22 PM PDT 24
Finished Aug 13 06:44:30 PM PDT 24
Peak memory 211456 kb
Host smart-1fed2a43-de54-4080-8395-9b4418a3b1a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450411023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1450411023
Directory /workspace/9.rom_ctrl_stress_all/latest
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