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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.29 96.89 91.99 97.67 100.00 98.62 97.45 98.37


Total test records in report: 411
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T306 /workspace/coverage/default/10.rom_ctrl_alert_test.1783172273 Aug 14 04:34:04 PM PDT 24 Aug 14 04:34:08 PM PDT 24 524455008 ps
T307 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2977609199 Aug 14 04:34:21 PM PDT 24 Aug 14 04:36:11 PM PDT 24 7737170760 ps
T308 /workspace/coverage/default/9.rom_ctrl_alert_test.3672018148 Aug 14 04:33:59 PM PDT 24 Aug 14 04:34:05 PM PDT 24 498309864 ps
T309 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.418496419 Aug 14 04:34:24 PM PDT 24 Aug 14 04:36:02 PM PDT 24 1676946887 ps
T310 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4025965430 Aug 14 04:34:20 PM PDT 24 Aug 14 04:34:31 PM PDT 24 501791962 ps
T311 /workspace/coverage/default/37.rom_ctrl_stress_all.2660953742 Aug 14 04:34:12 PM PDT 24 Aug 14 04:34:25 PM PDT 24 573137494 ps
T312 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.4261158604 Aug 14 04:34:15 PM PDT 24 Aug 14 04:34:27 PM PDT 24 964762920 ps
T313 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1502977878 Aug 14 04:34:14 PM PDT 24 Aug 14 04:36:25 PM PDT 24 5247504946 ps
T119 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3255209182 Aug 14 04:34:45 PM PDT 24 Aug 14 04:34:50 PM PDT 24 357492631 ps
T314 /workspace/coverage/default/7.rom_ctrl_smoke.1084916905 Aug 14 04:34:12 PM PDT 24 Aug 14 04:34:18 PM PDT 24 198643786 ps
T315 /workspace/coverage/default/28.rom_ctrl_alert_test.3477662775 Aug 14 04:34:24 PM PDT 24 Aug 14 04:34:29 PM PDT 24 449487419 ps
T316 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2739211282 Aug 14 04:34:25 PM PDT 24 Aug 14 04:36:22 PM PDT 24 21042681118 ps
T317 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2531795372 Aug 14 04:34:45 PM PDT 24 Aug 14 04:36:05 PM PDT 24 1618155332 ps
T318 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2507588148 Aug 14 04:34:11 PM PDT 24 Aug 14 04:36:33 PM PDT 24 5215941319 ps
T319 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.806154200 Aug 14 04:33:52 PM PDT 24 Aug 14 04:34:07 PM PDT 24 176418499 ps
T320 /workspace/coverage/default/1.rom_ctrl_alert_test.3358278290 Aug 14 04:33:56 PM PDT 24 Aug 14 04:34:03 PM PDT 24 1025317232 ps
T64 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1975716761 Aug 14 04:36:04 PM PDT 24 Aug 14 04:36:37 PM PDT 24 1604894358 ps
T321 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1714954890 Aug 14 04:35:59 PM PDT 24 Aug 14 04:36:04 PM PDT 24 347298875 ps
T65 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1543079466 Aug 14 04:36:43 PM PDT 24 Aug 14 04:36:47 PM PDT 24 308565510 ps
T66 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1526019087 Aug 14 04:36:45 PM PDT 24 Aug 14 04:37:13 PM PDT 24 2454937269 ps
T27 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4078292530 Aug 14 04:36:37 PM PDT 24 Aug 14 04:36:45 PM PDT 24 131160547 ps
T78 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4201884784 Aug 14 04:36:25 PM PDT 24 Aug 14 04:36:31 PM PDT 24 96639346 ps
T79 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.262286319 Aug 14 04:36:29 PM PDT 24 Aug 14 04:36:56 PM PDT 24 4467521215 ps
T116 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2645323974 Aug 14 04:36:07 PM PDT 24 Aug 14 04:36:13 PM PDT 24 496049334 ps
T80 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.422014382 Aug 14 04:36:06 PM PDT 24 Aug 14 04:36:14 PM PDT 24 1009102399 ps
T81 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.949677204 Aug 14 04:36:32 PM PDT 24 Aug 14 04:36:39 PM PDT 24 262072700 ps
T28 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1670191013 Aug 14 04:37:29 PM PDT 24 Aug 14 04:37:34 PM PDT 24 342232954 ps
T120 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3234832511 Aug 14 04:36:24 PM PDT 24 Aug 14 04:36:28 PM PDT 24 125892893 ps
T30 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3421034437 Aug 14 04:36:08 PM PDT 24 Aug 14 04:36:14 PM PDT 24 1165371891 ps
T121 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.205196504 Aug 14 04:36:47 PM PDT 24 Aug 14 04:36:52 PM PDT 24 171666515 ps
T46 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.138586850 Aug 14 04:37:39 PM PDT 24 Aug 14 04:38:48 PM PDT 24 296776185 ps
T48 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.426289934 Aug 14 04:36:04 PM PDT 24 Aug 14 04:36:42 PM PDT 24 215235117 ps
T82 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2509393082 Aug 14 04:36:05 PM PDT 24 Aug 14 04:36:10 PM PDT 24 90267356 ps
T83 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2119503334 Aug 14 04:36:35 PM PDT 24 Aug 14 04:36:40 PM PDT 24 595134600 ps
T117 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.888514097 Aug 14 04:36:02 PM PDT 24 Aug 14 04:36:06 PM PDT 24 168993171 ps
T126 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.616108502 Aug 14 04:36:31 PM PDT 24 Aug 14 04:36:53 PM PDT 24 2385554353 ps
T49 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1870398628 Aug 14 04:36:28 PM PDT 24 Aug 14 04:36:33 PM PDT 24 98346304 ps
T84 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.402221765 Aug 14 04:36:29 PM PDT 24 Aug 14 04:36:37 PM PDT 24 530172739 ps
T118 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1180347153 Aug 14 04:36:42 PM PDT 24 Aug 14 04:36:48 PM PDT 24 955422289 ps
T50 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1801545753 Aug 14 04:37:39 PM PDT 24 Aug 14 04:38:50 PM PDT 24 366997340 ps
T51 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3122131827 Aug 14 04:36:45 PM PDT 24 Aug 14 04:36:51 PM PDT 24 333046256 ps
T47 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4673719 Aug 14 04:36:40 PM PDT 24 Aug 14 04:37:16 PM PDT 24 1123089454 ps
T74 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2664974394 Aug 14 04:36:46 PM PDT 24 Aug 14 04:37:56 PM PDT 24 666838048 ps
T67 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1877183492 Aug 14 04:36:04 PM PDT 24 Aug 14 04:36:12 PM PDT 24 228280130 ps
T85 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4175647517 Aug 14 04:36:18 PM PDT 24 Aug 14 04:36:25 PM PDT 24 149664042 ps
T75 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3163348928 Aug 14 04:36:32 PM PDT 24 Aug 14 04:36:37 PM PDT 24 102333597 ps
T76 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3785002243 Aug 14 04:36:04 PM PDT 24 Aug 14 04:37:14 PM PDT 24 442121634 ps
T77 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3747677208 Aug 14 04:36:43 PM PDT 24 Aug 14 04:36:48 PM PDT 24 1019207626 ps
T322 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1162357320 Aug 14 04:36:45 PM PDT 24 Aug 14 04:36:50 PM PDT 24 86142923 ps
T323 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1677430960 Aug 14 04:36:05 PM PDT 24 Aug 14 04:36:10 PM PDT 24 142545542 ps
T324 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1607935740 Aug 14 04:36:25 PM PDT 24 Aug 14 04:36:29 PM PDT 24 172198845 ps
T130 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2605767979 Aug 14 04:36:11 PM PDT 24 Aug 14 04:37:22 PM PDT 24 1726986602 ps
T92 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.737502542 Aug 14 04:36:24 PM PDT 24 Aug 14 04:36:29 PM PDT 24 428027843 ps
T325 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1083837559 Aug 14 04:36:16 PM PDT 24 Aug 14 04:36:26 PM PDT 24 590543824 ps
T134 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3942723546 Aug 14 04:36:06 PM PDT 24 Aug 14 04:37:17 PM PDT 24 4369401609 ps
T326 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1136251149 Aug 14 04:37:43 PM PDT 24 Aug 14 04:37:52 PM PDT 24 306562008 ps
T327 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3365769886 Aug 14 04:36:22 PM PDT 24 Aug 14 04:36:28 PM PDT 24 256889784 ps
T328 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.272093088 Aug 14 04:36:15 PM PDT 24 Aug 14 04:36:22 PM PDT 24 395379745 ps
T329 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4111725504 Aug 14 04:36:17 PM PDT 24 Aug 14 04:36:22 PM PDT 24 127171918 ps
T330 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4048086563 Aug 14 04:36:38 PM PDT 24 Aug 14 04:36:42 PM PDT 24 98635519 ps
T331 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1641456939 Aug 14 04:36:34 PM PDT 24 Aug 14 04:36:40 PM PDT 24 635015306 ps
T332 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3976304329 Aug 14 04:36:42 PM PDT 24 Aug 14 04:37:01 PM PDT 24 1494635631 ps
T128 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3969849937 Aug 14 04:36:40 PM PDT 24 Aug 14 04:37:50 PM PDT 24 1618862409 ps
T333 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.245525377 Aug 14 04:36:22 PM PDT 24 Aug 14 04:36:27 PM PDT 24 85948458 ps
T334 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.27227341 Aug 14 04:36:46 PM PDT 24 Aug 14 04:36:52 PM PDT 24 796169101 ps
T93 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1032224723 Aug 14 04:36:39 PM PDT 24 Aug 14 04:36:46 PM PDT 24 155942803 ps
T335 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2866766361 Aug 14 04:36:31 PM PDT 24 Aug 14 04:37:10 PM PDT 24 901680175 ps
T336 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.430250149 Aug 14 04:36:43 PM PDT 24 Aug 14 04:36:47 PM PDT 24 175145359 ps
T94 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1026766969 Aug 14 04:36:45 PM PDT 24 Aug 14 04:37:03 PM PDT 24 382669812 ps
T337 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1667429340 Aug 14 04:36:09 PM PDT 24 Aug 14 04:36:14 PM PDT 24 563697944 ps
T338 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1437486168 Aug 14 04:36:31 PM PDT 24 Aug 14 04:36:36 PM PDT 24 246622672 ps
T339 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2205907054 Aug 14 04:36:43 PM PDT 24 Aug 14 04:37:57 PM PDT 24 737158389 ps
T340 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4040691812 Aug 14 04:36:22 PM PDT 24 Aug 14 04:36:26 PM PDT 24 133394193 ps
T96 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.174060512 Aug 14 04:36:25 PM PDT 24 Aug 14 04:36:30 PM PDT 24 126392130 ps
T341 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3617377234 Aug 14 04:36:06 PM PDT 24 Aug 14 04:36:11 PM PDT 24 997015000 ps
T342 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2281960390 Aug 14 04:36:06 PM PDT 24 Aug 14 04:36:10 PM PDT 24 89240236 ps
T343 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2187617321 Aug 14 04:36:41 PM PDT 24 Aug 14 04:36:46 PM PDT 24 541000329 ps
T344 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1030654602 Aug 14 04:36:15 PM PDT 24 Aug 14 04:36:19 PM PDT 24 85533790 ps
T131 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4130870531 Aug 14 04:36:19 PM PDT 24 Aug 14 04:36:57 PM PDT 24 203225398 ps
T345 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3015347672 Aug 14 04:36:43 PM PDT 24 Aug 14 04:36:48 PM PDT 24 352457888 ps
T346 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4166345822 Aug 14 04:36:00 PM PDT 24 Aug 14 04:36:05 PM PDT 24 134541195 ps
T347 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3666763243 Aug 14 04:36:46 PM PDT 24 Aug 14 04:36:50 PM PDT 24 89694421 ps
T135 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.354779898 Aug 14 04:36:46 PM PDT 24 Aug 14 04:37:55 PM PDT 24 812900420 ps
T348 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3569220629 Aug 14 04:36:10 PM PDT 24 Aug 14 04:36:42 PM PDT 24 1635339662 ps
T349 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1973902522 Aug 14 04:36:48 PM PDT 24 Aug 14 04:36:54 PM PDT 24 2017059919 ps
T104 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.503878010 Aug 14 04:36:36 PM PDT 24 Aug 14 04:36:55 PM PDT 24 1459680064 ps
T350 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.520471450 Aug 14 04:36:46 PM PDT 24 Aug 14 04:36:54 PM PDT 24 251352201 ps
T351 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3181262731 Aug 14 04:36:23 PM PDT 24 Aug 14 04:36:30 PM PDT 24 251987522 ps
T352 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4010018564 Aug 14 04:36:09 PM PDT 24 Aug 14 04:36:14 PM PDT 24 248576450 ps
T353 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2019888798 Aug 14 04:36:25 PM PDT 24 Aug 14 04:36:30 PM PDT 24 378395403 ps
T354 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1391000965 Aug 14 04:36:46 PM PDT 24 Aug 14 04:36:52 PM PDT 24 1082560114 ps
T127 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2715779682 Aug 14 04:36:23 PM PDT 24 Aug 14 04:36:46 PM PDT 24 2185667690 ps
T355 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3760807289 Aug 14 04:36:25 PM PDT 24 Aug 14 04:36:29 PM PDT 24 755696356 ps
T105 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3935917218 Aug 14 04:36:20 PM PDT 24 Aug 14 04:36:49 PM PDT 24 2487031046 ps
T356 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3683971696 Aug 14 04:36:28 PM PDT 24 Aug 14 04:36:36 PM PDT 24 255391604 ps
T357 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.914133406 Aug 14 04:37:34 PM PDT 24 Aug 14 04:37:41 PM PDT 24 298458936 ps
T358 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.933661464 Aug 14 04:36:20 PM PDT 24 Aug 14 04:36:25 PM PDT 24 136991933 ps
T95 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.767877845 Aug 14 04:36:36 PM PDT 24 Aug 14 04:36:41 PM PDT 24 500860143 ps
T359 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3761146137 Aug 14 04:36:18 PM PDT 24 Aug 14 04:36:24 PM PDT 24 356862826 ps
T102 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3613187445 Aug 14 04:36:12 PM PDT 24 Aug 14 04:36:17 PM PDT 24 251194099 ps
T103 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2901330305 Aug 14 04:36:47 PM PDT 24 Aug 14 04:37:06 PM PDT 24 1123832462 ps
T360 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3569657275 Aug 14 04:36:05 PM PDT 24 Aug 14 04:36:09 PM PDT 24 176097376 ps
T361 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2703206032 Aug 14 04:36:07 PM PDT 24 Aug 14 04:36:13 PM PDT 24 251616817 ps
T362 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2905236944 Aug 14 04:36:30 PM PDT 24 Aug 14 04:36:40 PM PDT 24 286226828 ps
T363 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3770276654 Aug 14 04:36:42 PM PDT 24 Aug 14 04:36:49 PM PDT 24 112171977 ps
T364 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.725300633 Aug 14 04:36:05 PM PDT 24 Aug 14 04:36:10 PM PDT 24 156050561 ps
T365 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2048136367 Aug 14 04:36:48 PM PDT 24 Aug 14 04:37:07 PM PDT 24 7203168727 ps
T129 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.168383565 Aug 14 04:36:23 PM PDT 24 Aug 14 04:37:03 PM PDT 24 400324994 ps
T366 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.46200341 Aug 14 04:36:05 PM PDT 24 Aug 14 04:36:10 PM PDT 24 322989602 ps
T367 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2441611031 Aug 14 04:36:49 PM PDT 24 Aug 14 04:36:53 PM PDT 24 171341780 ps
T368 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4253726087 Aug 14 04:36:16 PM PDT 24 Aug 14 04:36:21 PM PDT 24 99879078 ps
T369 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1927044903 Aug 14 04:36:25 PM PDT 24 Aug 14 04:36:31 PM PDT 24 870558941 ps
T370 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3627361090 Aug 14 04:37:42 PM PDT 24 Aug 14 04:37:47 PM PDT 24 689540812 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1581255670 Aug 14 04:36:05 PM PDT 24 Aug 14 04:36:10 PM PDT 24 88623868 ps
T372 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4008397937 Aug 14 04:36:29 PM PDT 24 Aug 14 04:36:33 PM PDT 24 171527146 ps
T373 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1873069893 Aug 14 04:36:35 PM PDT 24 Aug 14 04:36:40 PM PDT 24 594224001 ps
T374 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3854608636 Aug 14 04:36:26 PM PDT 24 Aug 14 04:36:31 PM PDT 24 519135262 ps
T375 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1515654727 Aug 14 04:36:14 PM PDT 24 Aug 14 04:36:18 PM PDT 24 348221938 ps
T132 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2892744057 Aug 14 04:36:16 PM PDT 24 Aug 14 04:36:53 PM PDT 24 596028962 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.899324275 Aug 14 04:36:10 PM PDT 24 Aug 14 04:36:24 PM PDT 24 516473705 ps
T97 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.246436080 Aug 14 04:36:38 PM PDT 24 Aug 14 04:37:00 PM PDT 24 2611906990 ps
T98 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3251610485 Aug 14 04:36:37 PM PDT 24 Aug 14 04:37:04 PM PDT 24 1070200660 ps
T377 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2623437673 Aug 14 04:36:23 PM PDT 24 Aug 14 04:37:02 PM PDT 24 254013112 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3499866245 Aug 14 04:36:02 PM PDT 24 Aug 14 04:36:08 PM PDT 24 255175301 ps
T379 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3364482692 Aug 14 04:36:40 PM PDT 24 Aug 14 04:36:49 PM PDT 24 132222680 ps
T380 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4237369357 Aug 14 04:36:36 PM PDT 24 Aug 14 04:36:41 PM PDT 24 333789554 ps
T381 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3419133753 Aug 14 04:36:43 PM PDT 24 Aug 14 04:36:47 PM PDT 24 385983186 ps
T133 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1297381473 Aug 14 04:36:33 PM PDT 24 Aug 14 04:38:01 PM PDT 24 4168640581 ps
T99 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1041488766 Aug 14 04:36:39 PM PDT 24 Aug 14 04:37:13 PM PDT 24 802717503 ps
T382 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1121381179 Aug 14 04:36:32 PM PDT 24 Aug 14 04:36:40 PM PDT 24 337585027 ps
T383 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3773932856 Aug 14 04:36:07 PM PDT 24 Aug 14 04:37:21 PM PDT 24 433860181 ps
T384 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4220223866 Aug 14 04:36:21 PM PDT 24 Aug 14 04:36:27 PM PDT 24 586900396 ps
T385 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3446182258 Aug 14 04:36:28 PM PDT 24 Aug 14 04:36:34 PM PDT 24 1381698758 ps
T386 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1062777271 Aug 14 04:36:39 PM PDT 24 Aug 14 04:36:49 PM PDT 24 128204433 ps
T100 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.388872585 Aug 14 04:36:23 PM PDT 24 Aug 14 04:36:56 PM PDT 24 834692631 ps
T387 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3341196766 Aug 14 04:37:34 PM PDT 24 Aug 14 04:37:53 PM PDT 24 739864617 ps
T388 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1754689207 Aug 14 04:36:31 PM PDT 24 Aug 14 04:36:38 PM PDT 24 86632206 ps
T389 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3100494304 Aug 14 04:36:22 PM PDT 24 Aug 14 04:36:32 PM PDT 24 540998488 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3660642341 Aug 14 04:36:04 PM PDT 24 Aug 14 04:36:23 PM PDT 24 365903324 ps
T391 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3255068066 Aug 14 04:36:09 PM PDT 24 Aug 14 04:36:16 PM PDT 24 158068713 ps
T392 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4025100136 Aug 14 04:36:06 PM PDT 24 Aug 14 04:36:11 PM PDT 24 130129416 ps
T393 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1262032223 Aug 14 04:36:35 PM PDT 24 Aug 14 04:36:39 PM PDT 24 85480336 ps
T394 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.639591409 Aug 14 04:36:07 PM PDT 24 Aug 14 04:36:14 PM PDT 24 254352605 ps
T395 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1731348123 Aug 14 04:37:34 PM PDT 24 Aug 14 04:37:38 PM PDT 24 348963566 ps
T396 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3929384761 Aug 14 04:36:28 PM PDT 24 Aug 14 04:36:37 PM PDT 24 251003093 ps
T397 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3638358020 Aug 14 04:36:20 PM PDT 24 Aug 14 04:36:59 PM PDT 24 458257604 ps
T398 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.842257983 Aug 14 04:36:14 PM PDT 24 Aug 14 04:36:23 PM PDT 24 269669394 ps
T399 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3961886113 Aug 14 04:36:47 PM PDT 24 Aug 14 04:36:54 PM PDT 24 96304131 ps
T400 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1683629084 Aug 14 04:36:26 PM PDT 24 Aug 14 04:36:31 PM PDT 24 88667814 ps
T401 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2956071463 Aug 14 04:36:03 PM PDT 24 Aug 14 04:36:08 PM PDT 24 129650830 ps
T402 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1572369240 Aug 14 04:36:46 PM PDT 24 Aug 14 04:36:51 PM PDT 24 774986511 ps
T403 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1491588364 Aug 14 04:36:16 PM PDT 24 Aug 14 04:36:20 PM PDT 24 350111685 ps
T101 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1084147124 Aug 14 04:36:32 PM PDT 24 Aug 14 04:37:05 PM PDT 24 783029742 ps
T404 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2583212270 Aug 14 04:36:25 PM PDT 24 Aug 14 04:36:30 PM PDT 24 591899237 ps
T405 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3761065831 Aug 14 04:36:13 PM PDT 24 Aug 14 04:36:21 PM PDT 24 86368190 ps
T406 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.66628127 Aug 14 04:36:09 PM PDT 24 Aug 14 04:36:16 PM PDT 24 705357560 ps
T407 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3515474854 Aug 14 04:36:06 PM PDT 24 Aug 14 04:36:28 PM PDT 24 1076262944 ps
T408 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1176881998 Aug 14 04:36:21 PM PDT 24 Aug 14 04:36:28 PM PDT 24 133056500 ps
T409 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2784289141 Aug 14 04:36:25 PM PDT 24 Aug 14 04:36:31 PM PDT 24 295379175 ps
T410 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4028018775 Aug 14 04:36:05 PM PDT 24 Aug 14 04:36:09 PM PDT 24 90042785 ps
T411 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2944202780 Aug 14 04:36:25 PM PDT 24 Aug 14 04:37:34 PM PDT 24 833866891 ps

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.320105161
Short name T2
Test name
Test status
Simulation time 37866547905 ps
CPU time 215.43 seconds
Started Aug 14 04:34:14 PM PDT 24
Finished Aug 14 04:37:50 PM PDT 24
Peak memory 234848 kb
Host smart-4dd1d9e9-9f81-4376-8973-4de3d3b28b82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320105161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.320105161
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.942950483
Short name T16
Test name
Test status
Simulation time 14192146232 ps
CPU time 142.91 seconds
Started Aug 14 04:34:20 PM PDT 24
Finished Aug 14 04:36:43 PM PDT 24
Peak memory 233056 kb
Host smart-e9db7b5e-5328-459b-b35a-dbad756b768e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942950483 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.942950483
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2445314897
Short name T11
Test name
Test status
Simulation time 1958353705 ps
CPU time 120.85 seconds
Started Aug 14 04:34:07 PM PDT 24
Finished Aug 14 04:36:08 PM PDT 24
Peak memory 236544 kb
Host smart-39c839b7-be3b-46c9-8815-92ff5c8be1d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445314897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2445314897
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.4288361998
Short name T123
Test name
Test status
Simulation time 100107841 ps
CPU time 5.91 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:18 PM PDT 24
Peak memory 211036 kb
Host smart-88c74175-bbcd-4ce3-9ace-d6ef7b1d82db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4288361998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.4288361998
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2280651987
Short name T4
Test name
Test status
Simulation time 1134172591 ps
CPU time 21.95 seconds
Started Aug 14 04:34:15 PM PDT 24
Finished Aug 14 04:34:37 PM PDT 24
Peak memory 214056 kb
Host smart-89cfc0b5-8f97-4069-858b-c6dbabb80175
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280651987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2280651987
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4673719
Short name T47
Test name
Test status
Simulation time 1123089454 ps
CPU time 36.29 seconds
Started Aug 14 04:36:40 PM PDT 24
Finished Aug 14 04:37:16 PM PDT 24
Peak memory 212600 kb
Host smart-555f1d53-4650-4cbe-83d0-f6ff149a592e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4673719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg
_err.4673719
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2447619912
Short name T25
Test name
Test status
Simulation time 85715919 ps
CPU time 4.33 seconds
Started Aug 14 04:34:22 PM PDT 24
Finished Aug 14 04:34:27 PM PDT 24
Peak memory 211352 kb
Host smart-c915586c-d1ce-4b0a-b869-542c192bf7e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447619912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2447619912
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.975574980
Short name T140
Test name
Test status
Simulation time 280091710 ps
CPU time 6.55 seconds
Started Aug 14 04:33:50 PM PDT 24
Finished Aug 14 04:33:57 PM PDT 24
Peak memory 211300 kb
Host smart-b60dba0d-4572-4534-ac1a-d32dc88e858a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=975574980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.975574980
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.4114535186
Short name T143
Test name
Test status
Simulation time 568849269 ps
CPU time 6.71 seconds
Started Aug 14 04:34:11 PM PDT 24
Finished Aug 14 04:34:17 PM PDT 24
Peak memory 211388 kb
Host smart-924c2eb9-d31e-4b9f-a0dc-fbf2d6bf44e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4114535186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.4114535186
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2773032115
Short name T22
Test name
Test status
Simulation time 391231566 ps
CPU time 101.23 seconds
Started Aug 14 04:33:50 PM PDT 24
Finished Aug 14 04:35:31 PM PDT 24
Peak memory 237964 kb
Host smart-36146651-f875-4ac9-b8a9-d72e464d395f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773032115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2773032115
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1975716761
Short name T64
Test name
Test status
Simulation time 1604894358 ps
CPU time 33.16 seconds
Started Aug 14 04:36:04 PM PDT 24
Finished Aug 14 04:36:37 PM PDT 24
Peak memory 211000 kb
Host smart-c670da2f-914a-4c18-9e31-63b2016f729c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975716761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1975716761
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2605767979
Short name T130
Test name
Test status
Simulation time 1726986602 ps
CPU time 70.38 seconds
Started Aug 14 04:36:11 PM PDT 24
Finished Aug 14 04:37:22 PM PDT 24
Peak memory 219096 kb
Host smart-450069de-05cc-47bb-a883-bcbd35554561
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605767979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2605767979
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2860689731
Short name T87
Test name
Test status
Simulation time 333032553 ps
CPU time 19.89 seconds
Started Aug 14 04:34:09 PM PDT 24
Finished Aug 14 04:34:29 PM PDT 24
Peak memory 215768 kb
Host smart-2c1b151c-3357-4310-a2fc-911c778f5596
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860689731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2860689731
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2495880037
Short name T204
Test name
Test status
Simulation time 450252297 ps
CPU time 5.57 seconds
Started Aug 14 04:34:06 PM PDT 24
Finished Aug 14 04:34:12 PM PDT 24
Peak memory 211280 kb
Host smart-69fafa16-9d55-4be8-82d6-43f44df6bd6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2495880037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2495880037
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3314417602
Short name T29
Test name
Test status
Simulation time 643870987 ps
CPU time 9.38 seconds
Started Aug 14 04:34:07 PM PDT 24
Finished Aug 14 04:34:17 PM PDT 24
Peak memory 212212 kb
Host smart-98851cc6-69b5-4218-861e-2031fd835d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314417602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3314417602
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.512834953
Short name T210
Test name
Test status
Simulation time 790420078 ps
CPU time 9.57 seconds
Started Aug 14 04:34:14 PM PDT 24
Finished Aug 14 04:34:24 PM PDT 24
Peak memory 212108 kb
Host smart-21fdce4e-4fab-4008-ae38-9192b8f278ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512834953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.512834953
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.4246359655
Short name T45
Test name
Test status
Simulation time 250943795 ps
CPU time 11.06 seconds
Started Aug 14 04:34:17 PM PDT 24
Finished Aug 14 04:34:29 PM PDT 24
Peak memory 211324 kb
Host smart-c23c9a3c-3e0b-43eb-ad92-f14cf8d53042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246359655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.4246359655
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2664974394
Short name T74
Test name
Test status
Simulation time 666838048 ps
CPU time 69.73 seconds
Started Aug 14 04:36:46 PM PDT 24
Finished Aug 14 04:37:56 PM PDT 24
Peak memory 219172 kb
Host smart-a7daebe0-e499-400a-a33a-4b0a12b57751
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664974394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2664974394
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4130870531
Short name T131
Test name
Test status
Simulation time 203225398 ps
CPU time 37.47 seconds
Started Aug 14 04:36:19 PM PDT 24
Finished Aug 14 04:36:57 PM PDT 24
Peak memory 212636 kb
Host smart-9918b19b-6048-4f57-8bb8-366f90816d68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130870531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.4130870531
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1041488766
Short name T99
Test name
Test status
Simulation time 802717503 ps
CPU time 33.38 seconds
Started Aug 14 04:36:39 PM PDT 24
Finished Aug 14 04:37:13 PM PDT 24
Peak memory 210976 kb
Host smart-7cf6aaeb-59a7-4a82-9d38-d260dc01b5cc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041488766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1041488766
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.450004798
Short name T113
Test name
Test status
Simulation time 175806717 ps
CPU time 4.51 seconds
Started Aug 14 04:34:18 PM PDT 24
Finished Aug 14 04:34:23 PM PDT 24
Peak memory 211316 kb
Host smart-4a6724a4-69e1-4249-96d7-595d354ffb77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450004798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.450004798
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3887022
Short name T106
Test name
Test status
Simulation time 346671347 ps
CPU time 5.67 seconds
Started Aug 14 04:33:47 PM PDT 24
Finished Aug 14 04:33:53 PM PDT 24
Peak memory 211240 kb
Host smart-7638ab46-ed6d-47ee-8eb6-95d3ceb32d9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3887022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3887022
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4002277010
Short name T21
Test name
Test status
Simulation time 1866655065 ps
CPU time 113.08 seconds
Started Aug 14 04:33:58 PM PDT 24
Finished Aug 14 04:35:51 PM PDT 24
Peak memory 233976 kb
Host smart-37895a19-e3d9-404b-b3bc-93b257777afd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002277010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.4002277010
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1345210917
Short name T23
Test name
Test status
Simulation time 611096793 ps
CPU time 52.66 seconds
Started Aug 14 04:33:53 PM PDT 24
Finished Aug 14 04:34:46 PM PDT 24
Peak memory 236672 kb
Host smart-df379b1b-e036-476b-8904-751c535668b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345210917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1345210917
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.46200341
Short name T366
Test name
Test status
Simulation time 322989602 ps
CPU time 5.1 seconds
Started Aug 14 04:36:05 PM PDT 24
Finished Aug 14 04:36:10 PM PDT 24
Peak memory 210936 kb
Host smart-5beeb422-5707-4c23-ac44-bd36b5f0946d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46200341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasi
ng.46200341
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4025100136
Short name T392
Test name
Test status
Simulation time 130129416 ps
CPU time 5.44 seconds
Started Aug 14 04:36:06 PM PDT 24
Finished Aug 14 04:36:11 PM PDT 24
Peak memory 217740 kb
Host smart-23bec3d1-cb60-4b0a-8c1b-709b91bdaad5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025100136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.4025100136
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1176881998
Short name T408
Test name
Test status
Simulation time 133056500 ps
CPU time 6.73 seconds
Started Aug 14 04:36:21 PM PDT 24
Finished Aug 14 04:36:28 PM PDT 24
Peak memory 210920 kb
Host smart-982f9575-915d-4bd3-b512-114615af6b2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176881998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1176881998
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2784289141
Short name T409
Test name
Test status
Simulation time 295379175 ps
CPU time 6.39 seconds
Started Aug 14 04:36:25 PM PDT 24
Finished Aug 14 04:36:31 PM PDT 24
Peak memory 215224 kb
Host smart-444717ff-aa90-4705-8fa0-941ab72b6186
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784289141 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2784289141
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2703206032
Short name T361
Test name
Test status
Simulation time 251616817 ps
CPU time 5.02 seconds
Started Aug 14 04:36:07 PM PDT 24
Finished Aug 14 04:36:13 PM PDT 24
Peak memory 211032 kb
Host smart-e1c8d6f4-f583-4219-824c-6d3d95a3b7ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703206032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2703206032
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3666763243
Short name T347
Test name
Test status
Simulation time 89694421 ps
CPU time 4.28 seconds
Started Aug 14 04:36:46 PM PDT 24
Finished Aug 14 04:36:50 PM PDT 24
Peak memory 210720 kb
Host smart-3c6f7478-a0ef-4447-8ac8-822b1320f366
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666763243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3666763243
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1714954890
Short name T321
Test name
Test status
Simulation time 347298875 ps
CPU time 4.38 seconds
Started Aug 14 04:35:59 PM PDT 24
Finished Aug 14 04:36:04 PM PDT 24
Peak memory 210884 kb
Host smart-b3024e63-3e2c-4ecd-81cb-142f079e1722
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714954890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1714954890
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.66628127
Short name T406
Test name
Test status
Simulation time 705357560 ps
CPU time 6.68 seconds
Started Aug 14 04:36:09 PM PDT 24
Finished Aug 14 04:36:16 PM PDT 24
Peak memory 211104 kb
Host smart-a5d32b27-7648-4c73-a2ce-d3cacc859346
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66628127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_same_csr_outstanding.66628127
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1877183492
Short name T67
Test name
Test status
Simulation time 228280130 ps
CPU time 7.93 seconds
Started Aug 14 04:36:04 PM PDT 24
Finished Aug 14 04:36:12 PM PDT 24
Peak memory 219228 kb
Host smart-55a8368e-e0ec-4bf1-bc22-932062be0337
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877183492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1877183492
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1581255670
Short name T371
Test name
Test status
Simulation time 88623868 ps
CPU time 4.25 seconds
Started Aug 14 04:36:05 PM PDT 24
Finished Aug 14 04:36:10 PM PDT 24
Peak memory 210780 kb
Host smart-bebfcb24-767e-4ea8-8993-9c14b7facb1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581255670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1581255670
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1491588364
Short name T403
Test name
Test status
Simulation time 350111685 ps
CPU time 4.66 seconds
Started Aug 14 04:36:16 PM PDT 24
Finished Aug 14 04:36:20 PM PDT 24
Peak memory 217668 kb
Host smart-e093a00a-5daf-40b1-a844-28f743f6f95b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491588364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1491588364
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.899324275
Short name T376
Test name
Test status
Simulation time 516473705 ps
CPU time 8.29 seconds
Started Aug 14 04:36:10 PM PDT 24
Finished Aug 14 04:36:24 PM PDT 24
Peak memory 219064 kb
Host smart-72d085f3-c225-4524-9893-a7a475aaf40b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899324275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.899324275
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4010018564
Short name T352
Test name
Test status
Simulation time 248576450 ps
CPU time 5.13 seconds
Started Aug 14 04:36:09 PM PDT 24
Finished Aug 14 04:36:14 PM PDT 24
Peak memory 219160 kb
Host smart-f0fc6686-1965-4f84-8b44-ec09fa729e75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010018564 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.4010018564
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.888514097
Short name T117
Test name
Test status
Simulation time 168993171 ps
CPU time 4.1 seconds
Started Aug 14 04:36:02 PM PDT 24
Finished Aug 14 04:36:06 PM PDT 24
Peak memory 211000 kb
Host smart-11c7e9e9-648a-47e6-a708-b95076f2d725
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888514097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.888514097
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3854608636
Short name T374
Test name
Test status
Simulation time 519135262 ps
CPU time 5.02 seconds
Started Aug 14 04:36:26 PM PDT 24
Finished Aug 14 04:36:31 PM PDT 24
Peak memory 210804 kb
Host smart-285590a4-bcb9-4e80-ac6e-9d89c03c865a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854608636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3854608636
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3760807289
Short name T355
Test name
Test status
Simulation time 755696356 ps
CPU time 4.35 seconds
Started Aug 14 04:36:25 PM PDT 24
Finished Aug 14 04:36:29 PM PDT 24
Peak memory 210808 kb
Host smart-ab230fe1-45b0-4812-b09b-3c0e6d0f7368
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760807289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3760807289
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.246436080
Short name T97
Test name
Test status
Simulation time 2611906990 ps
CPU time 21.88 seconds
Started Aug 14 04:36:38 PM PDT 24
Finished Aug 14 04:37:00 PM PDT 24
Peak memory 211080 kb
Host smart-afa3eaf2-4ccd-4f1f-a611-26114deb16ed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246436080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.246436080
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1180347153
Short name T118
Test name
Test status
Simulation time 955422289 ps
CPU time 5.22 seconds
Started Aug 14 04:36:42 PM PDT 24
Finished Aug 14 04:36:48 PM PDT 24
Peak memory 210992 kb
Host smart-64ac0afb-da26-4b04-884e-456a5460af73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180347153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1180347153
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.272093088
Short name T328
Test name
Test status
Simulation time 395379745 ps
CPU time 6.97 seconds
Started Aug 14 04:36:15 PM PDT 24
Finished Aug 14 04:36:22 PM PDT 24
Peak memory 215012 kb
Host smart-35fc4022-4344-48dc-8dd8-61802f92b3c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272093088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.272093088
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3942723546
Short name T134
Test name
Test status
Simulation time 4369401609 ps
CPU time 70.71 seconds
Started Aug 14 04:36:06 PM PDT 24
Finished Aug 14 04:37:17 PM PDT 24
Peak memory 219188 kb
Host smart-312d99af-5a82-42d7-a1b3-3e31d8b982db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942723546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3942723546
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1870398628
Short name T49
Test name
Test status
Simulation time 98346304 ps
CPU time 4.92 seconds
Started Aug 14 04:36:28 PM PDT 24
Finished Aug 14 04:36:33 PM PDT 24
Peak memory 215012 kb
Host smart-023f38a7-56a8-4e04-b0c7-590965284d8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870398628 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1870398628
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1873069893
Short name T373
Test name
Test status
Simulation time 594224001 ps
CPU time 4.31 seconds
Started Aug 14 04:36:35 PM PDT 24
Finished Aug 14 04:36:40 PM PDT 24
Peak memory 218232 kb
Host smart-365027a4-ad3d-48dc-9bcf-e320f0ff10da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873069893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1873069893
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4111725504
Short name T329
Test name
Test status
Simulation time 127171918 ps
CPU time 5.14 seconds
Started Aug 14 04:36:17 PM PDT 24
Finished Aug 14 04:36:22 PM PDT 24
Peak memory 210892 kb
Host smart-eb636b1f-7feb-4d15-832c-08ee681e9222
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111725504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.4111725504
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.842257983
Short name T398
Test name
Test status
Simulation time 269669394 ps
CPU time 8.94 seconds
Started Aug 14 04:36:14 PM PDT 24
Finished Aug 14 04:36:23 PM PDT 24
Peak memory 219132 kb
Host smart-00e1d329-90f2-4c46-8c35-c3183713cbb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842257983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.842257983
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.168383565
Short name T129
Test name
Test status
Simulation time 400324994 ps
CPU time 40.4 seconds
Started Aug 14 04:36:23 PM PDT 24
Finished Aug 14 04:37:03 PM PDT 24
Peak memory 213592 kb
Host smart-bbba9a0b-7034-4e77-965f-5eb3027f5a7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168383565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.168383565
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1973902522
Short name T349
Test name
Test status
Simulation time 2017059919 ps
CPU time 6.18 seconds
Started Aug 14 04:36:48 PM PDT 24
Finished Aug 14 04:36:54 PM PDT 24
Peak memory 216436 kb
Host smart-15b9bd28-aa26-4c16-97a9-f01bba617ba4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973902522 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1973902522
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.205196504
Short name T121
Test name
Test status
Simulation time 171666515 ps
CPU time 4.24 seconds
Started Aug 14 04:36:47 PM PDT 24
Finished Aug 14 04:36:52 PM PDT 24
Peak memory 218032 kb
Host smart-b627df45-0351-43fb-8e54-5b07eed28697
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205196504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.205196504
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2715779682
Short name T127
Test name
Test status
Simulation time 2185667690 ps
CPU time 22.52 seconds
Started Aug 14 04:36:23 PM PDT 24
Finished Aug 14 04:36:46 PM PDT 24
Peak memory 211128 kb
Host smart-0880aaef-a91f-4cc7-93ff-b9bce969e7e4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715779682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2715779682
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1262032223
Short name T393
Test name
Test status
Simulation time 85480336 ps
CPU time 4.42 seconds
Started Aug 14 04:36:35 PM PDT 24
Finished Aug 14 04:36:39 PM PDT 24
Peak memory 210928 kb
Host smart-edc59b46-6a5e-44b1-8622-c96470b312a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262032223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1262032223
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3100494304
Short name T389
Test name
Test status
Simulation time 540998488 ps
CPU time 8.91 seconds
Started Aug 14 04:36:22 PM PDT 24
Finished Aug 14 04:36:32 PM PDT 24
Peak memory 214904 kb
Host smart-3727f53e-f62b-4585-a769-8e83fb418382
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100494304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3100494304
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1297381473
Short name T133
Test name
Test status
Simulation time 4168640581 ps
CPU time 87.74 seconds
Started Aug 14 04:36:33 PM PDT 24
Finished Aug 14 04:38:01 PM PDT 24
Peak memory 219284 kb
Host smart-95d924fd-c98c-48f3-9859-a68bc9d19d9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297381473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1297381473
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3419133753
Short name T381
Test name
Test status
Simulation time 385983186 ps
CPU time 4.46 seconds
Started Aug 14 04:36:43 PM PDT 24
Finished Aug 14 04:36:47 PM PDT 24
Peak memory 219192 kb
Host smart-8fe69cfa-8691-45c2-a3b9-2fb70fec886f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419133753 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3419133753
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2119503334
Short name T83
Test name
Test status
Simulation time 595134600 ps
CPU time 4.92 seconds
Started Aug 14 04:36:35 PM PDT 24
Finished Aug 14 04:36:40 PM PDT 24
Peak memory 217632 kb
Host smart-c2ee2358-4522-46b0-bb59-8791916fbbf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119503334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2119503334
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3976304329
Short name T332
Test name
Test status
Simulation time 1494635631 ps
CPU time 18.47 seconds
Started Aug 14 04:36:42 PM PDT 24
Finished Aug 14 04:37:01 PM PDT 24
Peak memory 211052 kb
Host smart-f03e56e8-f614-4325-9fb6-b9cc50c6af82
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976304329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3976304329
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1162357320
Short name T322
Test name
Test status
Simulation time 86142923 ps
CPU time 4.5 seconds
Started Aug 14 04:36:45 PM PDT 24
Finished Aug 14 04:36:50 PM PDT 24
Peak memory 211020 kb
Host smart-d1664937-92db-4785-ba77-4b169f108fc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162357320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1162357320
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3122131827
Short name T51
Test name
Test status
Simulation time 333046256 ps
CPU time 6.3 seconds
Started Aug 14 04:36:45 PM PDT 24
Finished Aug 14 04:36:51 PM PDT 24
Peak memory 219176 kb
Host smart-043214ec-059b-4dcb-8883-970c863a0192
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122131827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3122131827
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2944202780
Short name T411
Test name
Test status
Simulation time 833866891 ps
CPU time 69.03 seconds
Started Aug 14 04:36:25 PM PDT 24
Finished Aug 14 04:37:34 PM PDT 24
Peak memory 212692 kb
Host smart-f2ff0044-c47f-4145-a202-43b3d0eb218d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944202780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2944202780
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1391000965
Short name T354
Test name
Test status
Simulation time 1082560114 ps
CPU time 5.34 seconds
Started Aug 14 04:36:46 PM PDT 24
Finished Aug 14 04:36:52 PM PDT 24
Peak memory 214084 kb
Host smart-a09f8dd3-e819-46ba-87f1-aa2e2e717da4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391000965 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1391000965
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.767877845
Short name T95
Test name
Test status
Simulation time 500860143 ps
CPU time 5.37 seconds
Started Aug 14 04:36:36 PM PDT 24
Finished Aug 14 04:36:41 PM PDT 24
Peak memory 219100 kb
Host smart-f8c2b468-7074-411d-bf31-b87fd47ef05b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767877845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.767877845
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1526019087
Short name T66
Test name
Test status
Simulation time 2454937269 ps
CPU time 27.49 seconds
Started Aug 14 04:36:45 PM PDT 24
Finished Aug 14 04:37:13 PM PDT 24
Peak memory 211056 kb
Host smart-c93c1027-e0cb-416c-8d6a-8c577814661b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526019087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1526019087
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.402221765
Short name T84
Test name
Test status
Simulation time 530172739 ps
CPU time 7.3 seconds
Started Aug 14 04:36:29 PM PDT 24
Finished Aug 14 04:36:37 PM PDT 24
Peak memory 210956 kb
Host smart-31ed3703-6d38-41f7-bee7-535d0c88a451
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402221765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.402221765
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1062777271
Short name T386
Test name
Test status
Simulation time 128204433 ps
CPU time 9.53 seconds
Started Aug 14 04:36:39 PM PDT 24
Finished Aug 14 04:36:49 PM PDT 24
Peak memory 219156 kb
Host smart-5c5ffbcf-99d7-4a06-84b5-2ba79fe0c847
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062777271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1062777271
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1801545753
Short name T50
Test name
Test status
Simulation time 366997340 ps
CPU time 70.04 seconds
Started Aug 14 04:37:39 PM PDT 24
Finished Aug 14 04:38:50 PM PDT 24
Peak memory 219208 kb
Host smart-d66efdcd-860f-4968-aa29-994490a3857b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801545753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1801545753
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1437486168
Short name T338
Test name
Test status
Simulation time 246622672 ps
CPU time 4.37 seconds
Started Aug 14 04:36:31 PM PDT 24
Finished Aug 14 04:36:36 PM PDT 24
Peak memory 219168 kb
Host smart-b06093f1-c923-43dd-9d16-8a96994a3beb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437486168 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1437486168
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4008397937
Short name T372
Test name
Test status
Simulation time 171527146 ps
CPU time 4.11 seconds
Started Aug 14 04:36:29 PM PDT 24
Finished Aug 14 04:36:33 PM PDT 24
Peak memory 210876 kb
Host smart-49dc616f-be3e-4886-933a-8ff664505175
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008397937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.4008397937
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.388872585
Short name T100
Test name
Test status
Simulation time 834692631 ps
CPU time 32.54 seconds
Started Aug 14 04:36:23 PM PDT 24
Finished Aug 14 04:36:56 PM PDT 24
Peak memory 211056 kb
Host smart-b292ac86-d412-409f-8cbc-08559fb8b612
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388872585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.388872585
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2441611031
Short name T367
Test name
Test status
Simulation time 171341780 ps
CPU time 4.3 seconds
Started Aug 14 04:36:49 PM PDT 24
Finished Aug 14 04:36:53 PM PDT 24
Peak memory 210956 kb
Host smart-e202d583-171b-48a4-833d-5c8b5d49a121
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441611031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2441611031
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2905236944
Short name T362
Test name
Test status
Simulation time 286226828 ps
CPU time 9.46 seconds
Started Aug 14 04:36:30 PM PDT 24
Finished Aug 14 04:36:40 PM PDT 24
Peak memory 216236 kb
Host smart-0e05e24a-ca22-4b28-98bc-db5f12c42384
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905236944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2905236944
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2892744057
Short name T132
Test name
Test status
Simulation time 596028962 ps
CPU time 36.75 seconds
Started Aug 14 04:36:16 PM PDT 24
Finished Aug 14 04:36:53 PM PDT 24
Peak memory 212648 kb
Host smart-8cd891d6-7819-4121-a90c-47c1253928af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892744057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2892744057
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3015347672
Short name T345
Test name
Test status
Simulation time 352457888 ps
CPU time 4.59 seconds
Started Aug 14 04:36:43 PM PDT 24
Finished Aug 14 04:36:48 PM PDT 24
Peak memory 219128 kb
Host smart-a5c44621-7945-4bd7-9a21-32ec847874f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015347672 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3015347672
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2187617321
Short name T343
Test name
Test status
Simulation time 541000329 ps
CPU time 5.03 seconds
Started Aug 14 04:36:41 PM PDT 24
Finished Aug 14 04:36:46 PM PDT 24
Peak memory 210920 kb
Host smart-f023023f-d432-4a6f-88ac-397927f533ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187617321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2187617321
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2901330305
Short name T103
Test name
Test status
Simulation time 1123832462 ps
CPU time 19.08 seconds
Started Aug 14 04:36:47 PM PDT 24
Finished Aug 14 04:37:06 PM PDT 24
Peak memory 210932 kb
Host smart-dca3913a-6474-4c41-91dd-90662cfeb5c2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901330305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2901330305
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3446182258
Short name T385
Test name
Test status
Simulation time 1381698758 ps
CPU time 5.31 seconds
Started Aug 14 04:36:28 PM PDT 24
Finished Aug 14 04:36:34 PM PDT 24
Peak memory 219148 kb
Host smart-6ea1b1bb-ed4b-4a91-8db4-f089a41d2e0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446182258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3446182258
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1083837559
Short name T325
Test name
Test status
Simulation time 590543824 ps
CPU time 9.57 seconds
Started Aug 14 04:36:16 PM PDT 24
Finished Aug 14 04:36:26 PM PDT 24
Peak memory 219140 kb
Host smart-268740b5-9529-4b64-bba4-7d38bc439459
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083837559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1083837559
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2623437673
Short name T377
Test name
Test status
Simulation time 254013112 ps
CPU time 38.9 seconds
Started Aug 14 04:36:23 PM PDT 24
Finished Aug 14 04:37:02 PM PDT 24
Peak memory 212628 kb
Host smart-418af981-12c9-450d-ac31-120a4eaf69fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623437673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2623437673
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.27227341
Short name T334
Test name
Test status
Simulation time 796169101 ps
CPU time 5.57 seconds
Started Aug 14 04:36:46 PM PDT 24
Finished Aug 14 04:36:52 PM PDT 24
Peak memory 219164 kb
Host smart-e116d511-0654-4e97-b99e-3d4d3cf9c9e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27227341 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.27227341
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3234832511
Short name T120
Test name
Test status
Simulation time 125892893 ps
CPU time 4.26 seconds
Started Aug 14 04:36:24 PM PDT 24
Finished Aug 14 04:36:28 PM PDT 24
Peak memory 217848 kb
Host smart-e5ddb2a9-8feb-468c-97af-df83cbaccad8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234832511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3234832511
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3341196766
Short name T387
Test name
Test status
Simulation time 739864617 ps
CPU time 18.09 seconds
Started Aug 14 04:37:34 PM PDT 24
Finished Aug 14 04:37:53 PM PDT 24
Peak memory 211044 kb
Host smart-7319a6a4-f789-4206-938e-35c4782c8827
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341196766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3341196766
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4201884784
Short name T78
Test name
Test status
Simulation time 96639346 ps
CPU time 6.07 seconds
Started Aug 14 04:36:25 PM PDT 24
Finished Aug 14 04:36:31 PM PDT 24
Peak memory 210992 kb
Host smart-d4888b3c-e6cd-4c93-8ab3-c90f2e4a4417
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201884784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.4201884784
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.520471450
Short name T350
Test name
Test status
Simulation time 251352201 ps
CPU time 7.81 seconds
Started Aug 14 04:36:46 PM PDT 24
Finished Aug 14 04:36:54 PM PDT 24
Peak memory 216040 kb
Host smart-0d31f25f-14b1-4a83-8566-04b1ef6fd125
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520471450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.520471450
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3747677208
Short name T77
Test name
Test status
Simulation time 1019207626 ps
CPU time 5.06 seconds
Started Aug 14 04:36:43 PM PDT 24
Finished Aug 14 04:36:48 PM PDT 24
Peak memory 216136 kb
Host smart-927a64dd-a795-4ef6-b3f7-8670d260fee7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747677208 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3747677208
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1572369240
Short name T402
Test name
Test status
Simulation time 774986511 ps
CPU time 4.86 seconds
Started Aug 14 04:36:46 PM PDT 24
Finished Aug 14 04:36:51 PM PDT 24
Peak memory 210928 kb
Host smart-c4e5f2a4-1fa7-4358-96b3-c2487e6e9e5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572369240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1572369240
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3251610485
Short name T98
Test name
Test status
Simulation time 1070200660 ps
CPU time 26.78 seconds
Started Aug 14 04:36:37 PM PDT 24
Finished Aug 14 04:37:04 PM PDT 24
Peak memory 210968 kb
Host smart-83fcc9b6-2a32-407d-a68f-eab6c40bcfb6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251610485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3251610485
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3627361090
Short name T370
Test name
Test status
Simulation time 689540812 ps
CPU time 5.01 seconds
Started Aug 14 04:37:42 PM PDT 24
Finished Aug 14 04:37:47 PM PDT 24
Peak memory 219168 kb
Host smart-564ef97b-5caf-4f24-9ae4-b673c8db1389
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627361090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3627361090
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3364482692
Short name T379
Test name
Test status
Simulation time 132222680 ps
CPU time 8.85 seconds
Started Aug 14 04:36:40 PM PDT 24
Finished Aug 14 04:36:49 PM PDT 24
Peak memory 215816 kb
Host smart-9366d3d7-45a4-4791-b35a-9916b55bb01c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364482692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3364482692
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.354779898
Short name T135
Test name
Test status
Simulation time 812900420 ps
CPU time 68.92 seconds
Started Aug 14 04:36:46 PM PDT 24
Finished Aug 14 04:37:55 PM PDT 24
Peak memory 219096 kb
Host smart-d19ff13e-88af-4483-b80e-ea64674a83da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354779898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.354779898
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1927044903
Short name T369
Test name
Test status
Simulation time 870558941 ps
CPU time 5.71 seconds
Started Aug 14 04:36:25 PM PDT 24
Finished Aug 14 04:36:31 PM PDT 24
Peak memory 216008 kb
Host smart-8beb4136-ebf5-4bdc-bb8e-995d17a9bd2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927044903 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1927044903
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1543079466
Short name T65
Test name
Test status
Simulation time 308565510 ps
CPU time 4.19 seconds
Started Aug 14 04:36:43 PM PDT 24
Finished Aug 14 04:36:47 PM PDT 24
Peak memory 210936 kb
Host smart-2c431627-31a1-4672-8470-616022667356
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543079466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1543079466
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2048136367
Short name T365
Test name
Test status
Simulation time 7203168727 ps
CPU time 18.84 seconds
Started Aug 14 04:36:48 PM PDT 24
Finished Aug 14 04:37:07 PM PDT 24
Peak memory 210980 kb
Host smart-4e47b91e-3d46-442c-a75b-9bfa066131a3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048136367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2048136367
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1731348123
Short name T395
Test name
Test status
Simulation time 348963566 ps
CPU time 4.28 seconds
Started Aug 14 04:37:34 PM PDT 24
Finished Aug 14 04:37:38 PM PDT 24
Peak memory 211032 kb
Host smart-15062901-7152-45b3-8bbf-db90a691ccff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731348123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1731348123
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3683971696
Short name T356
Test name
Test status
Simulation time 255391604 ps
CPU time 7.32 seconds
Started Aug 14 04:36:28 PM PDT 24
Finished Aug 14 04:36:36 PM PDT 24
Peak memory 215848 kb
Host smart-f22bff39-22c6-49dd-87e7-123b7d2ceeba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683971696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3683971696
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3969849937
Short name T128
Test name
Test status
Simulation time 1618862409 ps
CPU time 69.16 seconds
Started Aug 14 04:36:40 PM PDT 24
Finished Aug 14 04:37:50 PM PDT 24
Peak memory 219052 kb
Host smart-534a75b9-a6af-4147-b883-ef239e1c2bf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969849937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3969849937
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3163348928
Short name T75
Test name
Test status
Simulation time 102333597 ps
CPU time 4.82 seconds
Started Aug 14 04:36:32 PM PDT 24
Finished Aug 14 04:36:37 PM PDT 24
Peak memory 219180 kb
Host smart-f2e79a04-37c3-4b54-8220-00f1ea1ca396
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163348928 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3163348928
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.174060512
Short name T96
Test name
Test status
Simulation time 126392130 ps
CPU time 5.09 seconds
Started Aug 14 04:36:25 PM PDT 24
Finished Aug 14 04:36:30 PM PDT 24
Peak memory 219136 kb
Host smart-b7f0d32d-ecd0-486b-a65f-c77832ed3f88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174060512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.174060512
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3935917218
Short name T105
Test name
Test status
Simulation time 2487031046 ps
CPU time 28.49 seconds
Started Aug 14 04:36:20 PM PDT 24
Finished Aug 14 04:36:49 PM PDT 24
Peak memory 211100 kb
Host smart-167cd130-5ce1-475a-9d8b-27b69810618d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935917218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3935917218
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3770276654
Short name T363
Test name
Test status
Simulation time 112171977 ps
CPU time 6.6 seconds
Started Aug 14 04:36:42 PM PDT 24
Finished Aug 14 04:36:49 PM PDT 24
Peak memory 211020 kb
Host smart-eb78e683-e92f-4495-9ebd-f4d75d00c032
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770276654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3770276654
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3929384761
Short name T396
Test name
Test status
Simulation time 251003093 ps
CPU time 9.4 seconds
Started Aug 14 04:36:28 PM PDT 24
Finished Aug 14 04:36:37 PM PDT 24
Peak memory 216304 kb
Host smart-2d92926a-9d8f-475d-9c9f-8e8e943e577e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929384761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3929384761
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4028018775
Short name T410
Test name
Test status
Simulation time 90042785 ps
CPU time 4.48 seconds
Started Aug 14 04:36:05 PM PDT 24
Finished Aug 14 04:36:09 PM PDT 24
Peak memory 219056 kb
Host smart-3ffad56e-c364-4800-a60b-92e1f6c1be16
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028018775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.4028018775
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.725300633
Short name T364
Test name
Test status
Simulation time 156050561 ps
CPU time 5.25 seconds
Started Aug 14 04:36:05 PM PDT 24
Finished Aug 14 04:36:10 PM PDT 24
Peak memory 211032 kb
Host smart-f1b479ff-187b-4d6a-a93b-e72f3703af70
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725300633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.725300633
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1032224723
Short name T93
Test name
Test status
Simulation time 155942803 ps
CPU time 6.81 seconds
Started Aug 14 04:36:39 PM PDT 24
Finished Aug 14 04:36:46 PM PDT 24
Peak memory 210892 kb
Host smart-7dadfe37-7c33-490f-828f-baf3ac0b9a99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032224723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1032224723
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3617377234
Short name T341
Test name
Test status
Simulation time 997015000 ps
CPU time 5.26 seconds
Started Aug 14 04:36:06 PM PDT 24
Finished Aug 14 04:36:11 PM PDT 24
Peak memory 213100 kb
Host smart-65dddd34-23dd-492c-8236-764cdf015b10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617377234 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3617377234
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2956071463
Short name T401
Test name
Test status
Simulation time 129650830 ps
CPU time 5.03 seconds
Started Aug 14 04:36:03 PM PDT 24
Finished Aug 14 04:36:08 PM PDT 24
Peak memory 219104 kb
Host smart-5225a1cc-813d-480e-98ed-94c82c9c0ed9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956071463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2956071463
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3569657275
Short name T360
Test name
Test status
Simulation time 176097376 ps
CPU time 4.16 seconds
Started Aug 14 04:36:05 PM PDT 24
Finished Aug 14 04:36:09 PM PDT 24
Peak memory 210832 kb
Host smart-5b6cc2be-ee42-40ae-9f7d-6831a5a7944b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569657275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3569657275
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1677430960
Short name T323
Test name
Test status
Simulation time 142545542 ps
CPU time 5.07 seconds
Started Aug 14 04:36:05 PM PDT 24
Finished Aug 14 04:36:10 PM PDT 24
Peak memory 210776 kb
Host smart-355dee11-16f3-4548-829c-4f14ddd8f1a0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677430960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1677430960
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3569220629
Short name T348
Test name
Test status
Simulation time 1635339662 ps
CPU time 32.12 seconds
Started Aug 14 04:36:10 PM PDT 24
Finished Aug 14 04:36:42 PM PDT 24
Peak memory 211068 kb
Host smart-d92e64d7-257f-4589-9fe0-fe0a7b6fd532
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569220629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3569220629
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2645323974
Short name T116
Test name
Test status
Simulation time 496049334 ps
CPU time 5.15 seconds
Started Aug 14 04:36:07 PM PDT 24
Finished Aug 14 04:36:13 PM PDT 24
Peak memory 219128 kb
Host smart-6795095c-7846-4f1a-856c-e040f146267f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645323974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2645323974
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3181262731
Short name T351
Test name
Test status
Simulation time 251987522 ps
CPU time 7.28 seconds
Started Aug 14 04:36:23 PM PDT 24
Finished Aug 14 04:36:30 PM PDT 24
Peak memory 215884 kb
Host smart-6eec84c4-7ef2-4332-9a4e-191895fdfa1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181262731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3181262731
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.426289934
Short name T48
Test name
Test status
Simulation time 215235117 ps
CPU time 37.96 seconds
Started Aug 14 04:36:04 PM PDT 24
Finished Aug 14 04:36:42 PM PDT 24
Peak memory 219172 kb
Host smart-008f557d-458f-4367-a4b2-8282a428f099
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426289934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.426289934
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.422014382
Short name T80
Test name
Test status
Simulation time 1009102399 ps
CPU time 7.46 seconds
Started Aug 14 04:36:06 PM PDT 24
Finished Aug 14 04:36:14 PM PDT 24
Peak memory 211000 kb
Host smart-e6f425f8-e7e0-476d-95f9-d0ff974b6733
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422014382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.422014382
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4040691812
Short name T340
Test name
Test status
Simulation time 133394193 ps
CPU time 4.31 seconds
Started Aug 14 04:36:22 PM PDT 24
Finished Aug 14 04:36:26 PM PDT 24
Peak memory 211032 kb
Host smart-8ef42816-dc50-4743-a588-616b817f14ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040691812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.4040691812
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3761146137
Short name T359
Test name
Test status
Simulation time 356862826 ps
CPU time 6.01 seconds
Started Aug 14 04:36:18 PM PDT 24
Finished Aug 14 04:36:24 PM PDT 24
Peak memory 219096 kb
Host smart-27573899-ddba-472f-9aa8-7473a4b96ec9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761146137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3761146137
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4253726087
Short name T368
Test name
Test status
Simulation time 99879078 ps
CPU time 5.28 seconds
Started Aug 14 04:36:16 PM PDT 24
Finished Aug 14 04:36:21 PM PDT 24
Peak memory 214692 kb
Host smart-67cc12a6-23e2-4c0f-8d30-90116d4c63f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253726087 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.4253726087
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4237369357
Short name T380
Test name
Test status
Simulation time 333789554 ps
CPU time 4.15 seconds
Started Aug 14 04:36:36 PM PDT 24
Finished Aug 14 04:36:41 PM PDT 24
Peak memory 210888 kb
Host smart-3c3a8801-546f-429c-8880-0780f8089186
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237369357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.4237369357
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1030654602
Short name T344
Test name
Test status
Simulation time 85533790 ps
CPU time 4.27 seconds
Started Aug 14 04:36:15 PM PDT 24
Finished Aug 14 04:36:19 PM PDT 24
Peak memory 210800 kb
Host smart-bffe7a43-5063-4a6d-b2f8-21f1b13e8cb7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030654602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1030654602
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3499866245
Short name T378
Test name
Test status
Simulation time 255175301 ps
CPU time 5.1 seconds
Started Aug 14 04:36:02 PM PDT 24
Finished Aug 14 04:36:08 PM PDT 24
Peak memory 210764 kb
Host smart-ae53f897-83f4-442a-a2fb-d50f9845258e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499866245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3499866245
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.262286319
Short name T79
Test name
Test status
Simulation time 4467521215 ps
CPU time 26.99 seconds
Started Aug 14 04:36:29 PM PDT 24
Finished Aug 14 04:36:56 PM PDT 24
Peak memory 211504 kb
Host smart-8c4d2684-5b22-419d-b84c-6a79a41cc1f8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262286319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.262286319
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2281960390
Short name T342
Test name
Test status
Simulation time 89240236 ps
CPU time 4.18 seconds
Started Aug 14 04:36:06 PM PDT 24
Finished Aug 14 04:36:10 PM PDT 24
Peak memory 211024 kb
Host smart-be0873a0-b6bd-4aee-b5d8-f9e6b834b854
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281960390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2281960390
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4078292530
Short name T27
Test name
Test status
Simulation time 131160547 ps
CPU time 7.92 seconds
Started Aug 14 04:36:37 PM PDT 24
Finished Aug 14 04:36:45 PM PDT 24
Peak memory 219144 kb
Host smart-96e48482-1cf8-4b6b-80fe-e159e66392b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078292530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4078292530
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3638358020
Short name T397
Test name
Test status
Simulation time 458257604 ps
CPU time 38.7 seconds
Started Aug 14 04:36:20 PM PDT 24
Finished Aug 14 04:36:59 PM PDT 24
Peak memory 211500 kb
Host smart-64ad97a5-fb25-4b67-828c-912b4498d1cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638358020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3638358020
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2019888798
Short name T353
Test name
Test status
Simulation time 378395403 ps
CPU time 4.14 seconds
Started Aug 14 04:36:25 PM PDT 24
Finished Aug 14 04:36:30 PM PDT 24
Peak memory 210932 kb
Host smart-58f97854-78db-4419-bad9-9aa2583c39ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019888798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2019888798
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1607935740
Short name T324
Test name
Test status
Simulation time 172198845 ps
CPU time 4.56 seconds
Started Aug 14 04:36:25 PM PDT 24
Finished Aug 14 04:36:29 PM PDT 24
Peak memory 210984 kb
Host smart-0413ed59-b3c5-43be-b1a3-851b5a781f72
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607935740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1607935740
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4175647517
Short name T85
Test name
Test status
Simulation time 149664042 ps
CPU time 7 seconds
Started Aug 14 04:36:18 PM PDT 24
Finished Aug 14 04:36:25 PM PDT 24
Peak memory 210928 kb
Host smart-a88262d7-b214-4cfb-bcf6-8dd0ab43f620
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175647517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4175647517
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.914133406
Short name T357
Test name
Test status
Simulation time 298458936 ps
CPU time 5.86 seconds
Started Aug 14 04:37:34 PM PDT 24
Finished Aug 14 04:37:41 PM PDT 24
Peak memory 215668 kb
Host smart-2c0f5a7d-e546-46f0-8c21-a9a7338524ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914133406 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.914133406
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3613187445
Short name T102
Test name
Test status
Simulation time 251194099 ps
CPU time 5.12 seconds
Started Aug 14 04:36:12 PM PDT 24
Finished Aug 14 04:36:17 PM PDT 24
Peak memory 210868 kb
Host smart-e94303c3-d5ed-42f8-8b21-0c8b1d5fe90a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613187445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3613187445
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4166345822
Short name T346
Test name
Test status
Simulation time 134541195 ps
CPU time 4.99 seconds
Started Aug 14 04:36:00 PM PDT 24
Finished Aug 14 04:36:05 PM PDT 24
Peak memory 210824 kb
Host smart-0f4f5391-b554-489a-99a7-eab345c686bc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166345822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.4166345822
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.245525377
Short name T333
Test name
Test status
Simulation time 85948458 ps
CPU time 4.12 seconds
Started Aug 14 04:36:22 PM PDT 24
Finished Aug 14 04:36:27 PM PDT 24
Peak memory 210792 kb
Host smart-e2720340-92af-4ccc-9571-5bd25d2afc05
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245525377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
245525377
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3660642341
Short name T390
Test name
Test status
Simulation time 365903324 ps
CPU time 18.83 seconds
Started Aug 14 04:36:04 PM PDT 24
Finished Aug 14 04:36:23 PM PDT 24
Peak memory 210992 kb
Host smart-ecc622da-3665-4d89-b1ec-d133cd5aae09
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660642341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3660642341
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1515654727
Short name T375
Test name
Test status
Simulation time 348221938 ps
CPU time 4.33 seconds
Started Aug 14 04:36:14 PM PDT 24
Finished Aug 14 04:36:18 PM PDT 24
Peak memory 210956 kb
Host smart-04ab8c22-d9e1-4cde-a20e-ac00ce570370
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515654727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1515654727
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.639591409
Short name T394
Test name
Test status
Simulation time 254352605 ps
CPU time 7 seconds
Started Aug 14 04:36:07 PM PDT 24
Finished Aug 14 04:36:14 PM PDT 24
Peak memory 219244 kb
Host smart-feb9f33a-0cb7-48b4-b63f-b164b51197f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639591409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.639591409
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.138586850
Short name T46
Test name
Test status
Simulation time 296776185 ps
CPU time 68.95 seconds
Started Aug 14 04:37:39 PM PDT 24
Finished Aug 14 04:38:48 PM PDT 24
Peak memory 212804 kb
Host smart-bdeed7de-8823-46a2-9d6f-1fdffb399f4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138586850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.138586850
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4220223866
Short name T384
Test name
Test status
Simulation time 586900396 ps
CPU time 5.95 seconds
Started Aug 14 04:36:21 PM PDT 24
Finished Aug 14 04:36:27 PM PDT 24
Peak memory 219188 kb
Host smart-e0637513-e9b6-4a98-8204-86a793b87491
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220223866 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.4220223866
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.737502542
Short name T92
Test name
Test status
Simulation time 428027843 ps
CPU time 4.88 seconds
Started Aug 14 04:36:24 PM PDT 24
Finished Aug 14 04:36:29 PM PDT 24
Peak memory 210956 kb
Host smart-1b6b0b77-f5a2-42e0-bacf-6f8b97ffa449
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737502542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.737502542
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.503878010
Short name T104
Test name
Test status
Simulation time 1459680064 ps
CPU time 19.1 seconds
Started Aug 14 04:36:36 PM PDT 24
Finished Aug 14 04:36:55 PM PDT 24
Peak memory 210984 kb
Host smart-45a23474-9598-414b-80fd-e73d2a0961ba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503878010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.503878010
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3365769886
Short name T327
Test name
Test status
Simulation time 256889784 ps
CPU time 5.05 seconds
Started Aug 14 04:36:22 PM PDT 24
Finished Aug 14 04:36:28 PM PDT 24
Peak memory 210940 kb
Host smart-405412aa-b807-447a-bdce-11ceb615e059
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365769886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3365769886
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1121381179
Short name T382
Test name
Test status
Simulation time 337585027 ps
CPU time 7.09 seconds
Started Aug 14 04:36:32 PM PDT 24
Finished Aug 14 04:36:40 PM PDT 24
Peak memory 215916 kb
Host smart-786edc6b-8d34-4e3f-8ade-d583c5fbffe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121381179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1121381179
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1670191013
Short name T28
Test name
Test status
Simulation time 342232954 ps
CPU time 4.74 seconds
Started Aug 14 04:37:29 PM PDT 24
Finished Aug 14 04:37:34 PM PDT 24
Peak memory 219180 kb
Host smart-f0db9f2e-9141-4412-b816-b11e487424d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670191013 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1670191013
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1667429340
Short name T337
Test name
Test status
Simulation time 563697944 ps
CPU time 5.16 seconds
Started Aug 14 04:36:09 PM PDT 24
Finished Aug 14 04:36:14 PM PDT 24
Peak memory 219012 kb
Host smart-dfc6797d-ea94-49a7-b6ff-547b749df41b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667429340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1667429340
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.616108502
Short name T126
Test name
Test status
Simulation time 2385554353 ps
CPU time 22.35 seconds
Started Aug 14 04:36:31 PM PDT 24
Finished Aug 14 04:36:53 PM PDT 24
Peak memory 211076 kb
Host smart-5a28b082-5bfb-49e3-be0b-5e375cd1f018
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616108502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.616108502
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1683629084
Short name T400
Test name
Test status
Simulation time 88667814 ps
CPU time 4.31 seconds
Started Aug 14 04:36:26 PM PDT 24
Finished Aug 14 04:36:31 PM PDT 24
Peak memory 210976 kb
Host smart-86627131-7df5-46c0-a4fe-f0bab7868eef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683629084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1683629084
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3761065831
Short name T405
Test name
Test status
Simulation time 86368190 ps
CPU time 8.25 seconds
Started Aug 14 04:36:13 PM PDT 24
Finished Aug 14 04:36:21 PM PDT 24
Peak memory 216124 kb
Host smart-be78428f-967b-47f2-a851-d09c5e69fa64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761065831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3761065831
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3785002243
Short name T76
Test name
Test status
Simulation time 442121634 ps
CPU time 70.05 seconds
Started Aug 14 04:36:04 PM PDT 24
Finished Aug 14 04:37:14 PM PDT 24
Peak memory 212724 kb
Host smart-7b76058b-0c34-4a24-a6a2-5ab907725658
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785002243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3785002243
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.933661464
Short name T358
Test name
Test status
Simulation time 136991933 ps
CPU time 5.38 seconds
Started Aug 14 04:36:20 PM PDT 24
Finished Aug 14 04:36:25 PM PDT 24
Peak memory 214336 kb
Host smart-f5b61ff6-e548-476c-baa5-03ca466fbe0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933661464 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.933661464
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2509393082
Short name T82
Test name
Test status
Simulation time 90267356 ps
CPU time 4.2 seconds
Started Aug 14 04:36:05 PM PDT 24
Finished Aug 14 04:36:10 PM PDT 24
Peak memory 210960 kb
Host smart-535fe52b-ec08-43fa-9e2d-62a567e3aa7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509393082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2509393082
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3515474854
Short name T407
Test name
Test status
Simulation time 1076262944 ps
CPU time 21.93 seconds
Started Aug 14 04:36:06 PM PDT 24
Finished Aug 14 04:36:28 PM PDT 24
Peak memory 210968 kb
Host smart-5933a44e-1272-4f3f-b031-fe05002e0d2c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515474854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3515474854
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.949677204
Short name T81
Test name
Test status
Simulation time 262072700 ps
CPU time 6.71 seconds
Started Aug 14 04:36:32 PM PDT 24
Finished Aug 14 04:36:39 PM PDT 24
Peak memory 211048 kb
Host smart-65624158-224f-4385-9ea6-f5bc558e4008
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949677204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.949677204
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1754689207
Short name T388
Test name
Test status
Simulation time 86632206 ps
CPU time 6.75 seconds
Started Aug 14 04:36:31 PM PDT 24
Finished Aug 14 04:36:38 PM PDT 24
Peak memory 219244 kb
Host smart-c72eab07-c13d-441c-8182-738099ee83a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754689207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1754689207
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2205907054
Short name T339
Test name
Test status
Simulation time 737158389 ps
CPU time 73.12 seconds
Started Aug 14 04:36:43 PM PDT 24
Finished Aug 14 04:37:57 PM PDT 24
Peak memory 212288 kb
Host smart-5bdbccc2-f48c-4376-80ba-80dccc01f6f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205907054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2205907054
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1641456939
Short name T331
Test name
Test status
Simulation time 635015306 ps
CPU time 5.93 seconds
Started Aug 14 04:36:34 PM PDT 24
Finished Aug 14 04:36:40 PM PDT 24
Peak memory 215300 kb
Host smart-a163e688-32a2-43d1-b250-18f5912a53c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641456939 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1641456939
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4048086563
Short name T330
Test name
Test status
Simulation time 98635519 ps
CPU time 4.34 seconds
Started Aug 14 04:36:38 PM PDT 24
Finished Aug 14 04:36:42 PM PDT 24
Peak memory 210916 kb
Host smart-0b5408a0-dd75-4272-b8e3-5682ca3961c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048086563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4048086563
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1026766969
Short name T94
Test name
Test status
Simulation time 382669812 ps
CPU time 18.72 seconds
Started Aug 14 04:36:45 PM PDT 24
Finished Aug 14 04:37:03 PM PDT 24
Peak memory 211056 kb
Host smart-23fe6ab6-c05b-4c8b-bd6d-05f602ea37e3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026766969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1026766969
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3255068066
Short name T391
Test name
Test status
Simulation time 158068713 ps
CPU time 7.43 seconds
Started Aug 14 04:36:09 PM PDT 24
Finished Aug 14 04:36:16 PM PDT 24
Peak memory 211008 kb
Host smart-cb069900-66e9-4ce1-b663-3da97615a384
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255068066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3255068066
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1136251149
Short name T326
Test name
Test status
Simulation time 306562008 ps
CPU time 9.02 seconds
Started Aug 14 04:37:43 PM PDT 24
Finished Aug 14 04:37:52 PM PDT 24
Peak memory 216064 kb
Host smart-eb7fcd59-5e33-48e9-85e4-bc3e18bfdff5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136251149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1136251149
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2866766361
Short name T335
Test name
Test status
Simulation time 901680175 ps
CPU time 38.63 seconds
Started Aug 14 04:36:31 PM PDT 24
Finished Aug 14 04:37:10 PM PDT 24
Peak memory 219136 kb
Host smart-68f52d9c-5971-475a-b1a3-b6d721b3700b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866766361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2866766361
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3421034437
Short name T30
Test name
Test status
Simulation time 1165371891 ps
CPU time 5.65 seconds
Started Aug 14 04:36:08 PM PDT 24
Finished Aug 14 04:36:14 PM PDT 24
Peak memory 214896 kb
Host smart-5ce3babe-6fa9-41f1-92bb-27775fce65a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421034437 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3421034437
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2583212270
Short name T404
Test name
Test status
Simulation time 591899237 ps
CPU time 4.93 seconds
Started Aug 14 04:36:25 PM PDT 24
Finished Aug 14 04:36:30 PM PDT 24
Peak memory 219064 kb
Host smart-f0033fb2-4311-4019-a0cd-c12a259acfe6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583212270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2583212270
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1084147124
Short name T101
Test name
Test status
Simulation time 783029742 ps
CPU time 32.82 seconds
Started Aug 14 04:36:32 PM PDT 24
Finished Aug 14 04:37:05 PM PDT 24
Peak memory 211040 kb
Host smart-d8e863d4-3e69-4a62-9b0c-b7ce49a7e79b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084147124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1084147124
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.430250149
Short name T336
Test name
Test status
Simulation time 175145359 ps
CPU time 4.4 seconds
Started Aug 14 04:36:43 PM PDT 24
Finished Aug 14 04:36:47 PM PDT 24
Peak memory 210984 kb
Host smart-ba57d010-5d77-4e6d-ad31-c9fb78e429f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430250149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.430250149
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3961886113
Short name T399
Test name
Test status
Simulation time 96304131 ps
CPU time 7.23 seconds
Started Aug 14 04:36:47 PM PDT 24
Finished Aug 14 04:36:54 PM PDT 24
Peak memory 219168 kb
Host smart-d28fe1ad-4536-4e9b-931a-d5bcc93e5640
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961886113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3961886113
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3773932856
Short name T383
Test name
Test status
Simulation time 433860181 ps
CPU time 73.6 seconds
Started Aug 14 04:36:07 PM PDT 24
Finished Aug 14 04:37:21 PM PDT 24
Peak memory 213788 kb
Host smart-8fc4ccfe-fd4a-4dbd-a4f5-c16244cb2685
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773932856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3773932856
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1137747881
Short name T284
Test name
Test status
Simulation time 262482463 ps
CPU time 5.18 seconds
Started Aug 14 04:33:47 PM PDT 24
Finished Aug 14 04:33:52 PM PDT 24
Peak memory 211268 kb
Host smart-64f1c30b-bfaa-48c8-97a2-4e502ad75777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137747881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1137747881
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2281269097
Short name T5
Test name
Test status
Simulation time 1627221703 ps
CPU time 99.62 seconds
Started Aug 14 04:33:59 PM PDT 24
Finished Aug 14 04:35:39 PM PDT 24
Peak memory 237688 kb
Host smart-acc69180-3329-471a-8b3d-250ad3e9ed5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281269097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2281269097
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2068071138
Short name T205
Test name
Test status
Simulation time 696914699 ps
CPU time 9.66 seconds
Started Aug 14 04:33:52 PM PDT 24
Finished Aug 14 04:34:02 PM PDT 24
Peak memory 212236 kb
Host smart-8dbe75df-1d3b-4b5a-ac8b-18546141769e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068071138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2068071138
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3119743321
Short name T220
Test name
Test status
Simulation time 96730960 ps
CPU time 5.42 seconds
Started Aug 14 04:33:52 PM PDT 24
Finished Aug 14 04:33:58 PM PDT 24
Peak memory 211312 kb
Host smart-fffaef93-6c4b-4686-b6e8-bde4ff5a86d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3119743321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3119743321
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1251443593
Short name T89
Test name
Test status
Simulation time 598244176 ps
CPU time 6.59 seconds
Started Aug 14 04:33:57 PM PDT 24
Finished Aug 14 04:34:04 PM PDT 24
Peak memory 211524 kb
Host smart-3b49cf0d-95cf-472b-9f0f-f2f41c65822d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251443593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1251443593
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2983898609
Short name T34
Test name
Test status
Simulation time 454100107 ps
CPU time 13.46 seconds
Started Aug 14 04:33:58 PM PDT 24
Finished Aug 14 04:34:11 PM PDT 24
Peak memory 214280 kb
Host smart-30ac2920-8da5-4535-92dc-8e91f36bae28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983898609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2983898609
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3358278290
Short name T320
Test name
Test status
Simulation time 1025317232 ps
CPU time 7.6 seconds
Started Aug 14 04:33:56 PM PDT 24
Finished Aug 14 04:34:03 PM PDT 24
Peak memory 211284 kb
Host smart-77a3d640-e534-4a0d-b401-1c1bf8dfafc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358278290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3358278290
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1236379392
Short name T183
Test name
Test status
Simulation time 17772602485 ps
CPU time 95.86 seconds
Started Aug 14 04:33:51 PM PDT 24
Finished Aug 14 04:35:27 PM PDT 24
Peak memory 237304 kb
Host smart-050caead-8450-4790-b173-e190edf5a393
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236379392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1236379392
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3673332719
Short name T227
Test name
Test status
Simulation time 997074671 ps
CPU time 11.3 seconds
Started Aug 14 04:33:55 PM PDT 24
Finished Aug 14 04:34:06 PM PDT 24
Peak memory 212288 kb
Host smart-29f4115d-15c6-4fe5-9c06-5927a0cd38a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673332719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3673332719
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1861238810
Short name T9
Test name
Test status
Simulation time 2189489383 ps
CPU time 6.15 seconds
Started Aug 14 04:33:58 PM PDT 24
Finished Aug 14 04:34:05 PM PDT 24
Peak memory 211312 kb
Host smart-79b6e2a6-3762-4a59-a5d0-43a6827e22c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1861238810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1861238810
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.874813277
Short name T24
Test name
Test status
Simulation time 645788834 ps
CPU time 103.66 seconds
Started Aug 14 04:33:41 PM PDT 24
Finished Aug 14 04:35:25 PM PDT 24
Peak memory 239024 kb
Host smart-3f8a017b-0e9c-47f9-bbbb-deb2f37ebe9f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874813277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.874813277
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1348196886
Short name T91
Test name
Test status
Simulation time 110348411 ps
CPU time 5.59 seconds
Started Aug 14 04:34:00 PM PDT 24
Finished Aug 14 04:34:05 PM PDT 24
Peak memory 211352 kb
Host smart-811f2cca-3579-405e-bbf9-ff45994e6977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348196886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1348196886
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3666238186
Short name T274
Test name
Test status
Simulation time 1700768522 ps
CPU time 14.09 seconds
Started Aug 14 04:33:50 PM PDT 24
Finished Aug 14 04:34:04 PM PDT 24
Peak memory 213336 kb
Host smart-fe2f0731-2ff7-4033-98e4-9e55553a4bc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666238186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3666238186
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1783172273
Short name T306
Test name
Test status
Simulation time 524455008 ps
CPU time 4.4 seconds
Started Aug 14 04:34:04 PM PDT 24
Finished Aug 14 04:34:08 PM PDT 24
Peak memory 211296 kb
Host smart-d74a37db-766b-46ea-8eef-d74fac269a70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783172273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1783172273
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3203668973
Short name T151
Test name
Test status
Simulation time 1751332123 ps
CPU time 117.8 seconds
Started Aug 14 04:34:07 PM PDT 24
Finished Aug 14 04:36:05 PM PDT 24
Peak memory 237792 kb
Host smart-193dbd65-27af-4a3c-b10e-352e4c61479a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203668973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3203668973
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.412734274
Short name T219
Test name
Test status
Simulation time 556763970 ps
CPU time 6.6 seconds
Started Aug 14 04:33:58 PM PDT 24
Finished Aug 14 04:34:05 PM PDT 24
Peak memory 211336 kb
Host smart-47195c03-a058-449a-9392-73737f3b5684
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=412734274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.412734274
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.169348521
Short name T218
Test name
Test status
Simulation time 129399605 ps
CPU time 5.02 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:17 PM PDT 24
Peak memory 211332 kb
Host smart-784e649c-e01c-4b21-80b4-5fcf326baac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169348521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.169348521
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2768894817
Short name T55
Test name
Test status
Simulation time 3108659407 ps
CPU time 125.51 seconds
Started Aug 14 04:34:00 PM PDT 24
Finished Aug 14 04:36:06 PM PDT 24
Peak memory 233792 kb
Host smart-31cdd7ae-476d-430b-9ce5-d4da2daa429e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768894817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2768894817
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1755672400
Short name T215
Test name
Test status
Simulation time 7602885270 ps
CPU time 15.92 seconds
Started Aug 14 04:33:56 PM PDT 24
Finished Aug 14 04:34:12 PM PDT 24
Peak memory 212836 kb
Host smart-a43e2270-6caf-4137-b872-31af0337a620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755672400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1755672400
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2887521764
Short name T147
Test name
Test status
Simulation time 140359671 ps
CPU time 6.17 seconds
Started Aug 14 04:34:07 PM PDT 24
Finished Aug 14 04:34:14 PM PDT 24
Peak memory 211308 kb
Host smart-3201a432-b563-4151-82aa-f4a820e75ed7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2887521764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2887521764
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.135713536
Short name T277
Test name
Test status
Simulation time 663005123 ps
CPU time 16.96 seconds
Started Aug 14 04:34:04 PM PDT 24
Finished Aug 14 04:34:21 PM PDT 24
Peak memory 214644 kb
Host smart-4ec9bf7e-8ec6-4a87-8338-67c479554cac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135713536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.135713536
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2468643616
Short name T153
Test name
Test status
Simulation time 697277697 ps
CPU time 4.97 seconds
Started Aug 14 04:34:17 PM PDT 24
Finished Aug 14 04:34:23 PM PDT 24
Peak memory 211372 kb
Host smart-30d7ea03-bd8a-421d-8dfe-b1be3bb2b812
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468643616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2468643616
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1278610087
Short name T244
Test name
Test status
Simulation time 17947973908 ps
CPU time 110.09 seconds
Started Aug 14 04:33:58 PM PDT 24
Finished Aug 14 04:35:49 PM PDT 24
Peak memory 234948 kb
Host smart-82e6b67c-6b87-4fbf-acea-655eec2587fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278610087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1278610087
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1417397591
Short name T36
Test name
Test status
Simulation time 1037367427 ps
CPU time 10.91 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:23 PM PDT 24
Peak memory 212156 kb
Host smart-23ccaa62-b9ea-4ea4-bd9e-6c61cb71629e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417397591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1417397591
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1380211315
Short name T233
Test name
Test status
Simulation time 101316630 ps
CPU time 5.84 seconds
Started Aug 14 04:34:02 PM PDT 24
Finished Aug 14 04:34:08 PM PDT 24
Peak memory 211304 kb
Host smart-1da9d92a-8d8b-4440-987a-301e9f0cbdea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1380211315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1380211315
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.343132880
Short name T86
Test name
Test status
Simulation time 190880633 ps
CPU time 12.13 seconds
Started Aug 14 04:34:10 PM PDT 24
Finished Aug 14 04:34:23 PM PDT 24
Peak memory 211336 kb
Host smart-7bde8f2f-89d7-462f-be44-a293c086e0e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343132880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.343132880
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3511873520
Short name T294
Test name
Test status
Simulation time 131361304 ps
CPU time 5.17 seconds
Started Aug 14 04:34:11 PM PDT 24
Finished Aug 14 04:34:17 PM PDT 24
Peak memory 211240 kb
Host smart-0cc0021c-83e5-43b0-ac6c-23bab4d21556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511873520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3511873520
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3658861962
Short name T54
Test name
Test status
Simulation time 408171292 ps
CPU time 9.53 seconds
Started Aug 14 04:33:57 PM PDT 24
Finished Aug 14 04:34:07 PM PDT 24
Peak memory 211496 kb
Host smart-3f12120f-f2f1-4d5a-b3cb-a39f34606dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658861962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3658861962
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3147860001
Short name T149
Test name
Test status
Simulation time 146179794 ps
CPU time 6.72 seconds
Started Aug 14 04:34:04 PM PDT 24
Finished Aug 14 04:34:11 PM PDT 24
Peak memory 211392 kb
Host smart-1b0e2673-cd84-45a2-8ada-3931fb1d6167
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3147860001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3147860001
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.224494804
Short name T174
Test name
Test status
Simulation time 863429356 ps
CPU time 18.2 seconds
Started Aug 14 04:34:01 PM PDT 24
Finished Aug 14 04:34:19 PM PDT 24
Peak memory 213616 kb
Host smart-02b87920-c25e-49da-9719-c12456907bcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224494804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.224494804
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2495028714
Short name T154
Test name
Test status
Simulation time 16086651213 ps
CPU time 172.5 seconds
Started Aug 14 04:34:02 PM PDT 24
Finished Aug 14 04:36:55 PM PDT 24
Peak memory 213724 kb
Host smart-03c82ac5-d4cb-4456-a8b1-7b8cbcee7169
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495028714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2495028714
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1638877980
Short name T238
Test name
Test status
Simulation time 923863946 ps
CPU time 9.61 seconds
Started Aug 14 04:34:10 PM PDT 24
Finished Aug 14 04:34:20 PM PDT 24
Peak memory 212216 kb
Host smart-5526e8b5-46fb-4f22-baed-5fdf2ef5597c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638877980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1638877980
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3628062231
Short name T148
Test name
Test status
Simulation time 1505226285 ps
CPU time 20.91 seconds
Started Aug 14 04:34:10 PM PDT 24
Finished Aug 14 04:34:31 PM PDT 24
Peak memory 215568 kb
Host smart-e8615324-96b2-438f-9d32-471b7564095d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628062231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3628062231
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.691351752
Short name T37
Test name
Test status
Simulation time 175526632 ps
CPU time 4.1 seconds
Started Aug 14 04:34:10 PM PDT 24
Finished Aug 14 04:34:14 PM PDT 24
Peak memory 211292 kb
Host smart-63ce7679-4970-481c-b049-d3519376114f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691351752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.691351752
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.686206684
Short name T229
Test name
Test status
Simulation time 2777583382 ps
CPU time 151.84 seconds
Started Aug 14 04:34:04 PM PDT 24
Finished Aug 14 04:36:36 PM PDT 24
Peak memory 238544 kb
Host smart-1dfab5e2-f660-4a90-bc56-56581fad66ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686206684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.686206684
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2192979523
Short name T292
Test name
Test status
Simulation time 507844843 ps
CPU time 11.39 seconds
Started Aug 14 04:34:00 PM PDT 24
Finished Aug 14 04:34:11 PM PDT 24
Peak memory 212660 kb
Host smart-eccbc62e-27ed-4047-afcf-5c97c06f5977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192979523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2192979523
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1663587870
Short name T226
Test name
Test status
Simulation time 661828250 ps
CPU time 6.24 seconds
Started Aug 14 04:33:52 PM PDT 24
Finished Aug 14 04:33:58 PM PDT 24
Peak memory 211380 kb
Host smart-66ca1345-6eb8-4d0e-80fe-560825abe1e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1663587870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1663587870
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.4029883823
Short name T221
Test name
Test status
Simulation time 3908762460 ps
CPU time 12.21 seconds
Started Aug 14 04:34:09 PM PDT 24
Finished Aug 14 04:34:21 PM PDT 24
Peak memory 214836 kb
Host smart-6ff70043-fcf1-42a8-bf5c-f757b599774d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029883823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.4029883823
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.4207940677
Short name T185
Test name
Test status
Simulation time 597310549 ps
CPU time 5.07 seconds
Started Aug 14 04:33:55 PM PDT 24
Finished Aug 14 04:34:00 PM PDT 24
Peak memory 211264 kb
Host smart-77a1aef6-e4e7-440d-9b70-b9a334fcaf78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207940677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.4207940677
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.4001108161
Short name T286
Test name
Test status
Simulation time 1795375735 ps
CPU time 104.52 seconds
Started Aug 14 04:33:46 PM PDT 24
Finished Aug 14 04:35:30 PM PDT 24
Peak memory 233676 kb
Host smart-0be31e87-ba3d-4a2a-aef0-5590273215d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001108161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.4001108161
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.576769357
Short name T172
Test name
Test status
Simulation time 1188129541 ps
CPU time 9.41 seconds
Started Aug 14 04:33:53 PM PDT 24
Finished Aug 14 04:34:03 PM PDT 24
Peak memory 212192 kb
Host smart-cc63a224-db97-4a57-b360-4df32b5ffe4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576769357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.576769357
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2757952234
Short name T13
Test name
Test status
Simulation time 295381118 ps
CPU time 14.19 seconds
Started Aug 14 04:33:57 PM PDT 24
Finished Aug 14 04:34:11 PM PDT 24
Peak memory 213104 kb
Host smart-09f92df9-ade9-4623-9bc0-07f775c669d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757952234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2757952234
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2767677575
Short name T72
Test name
Test status
Simulation time 444174883 ps
CPU time 5.11 seconds
Started Aug 14 04:33:56 PM PDT 24
Finished Aug 14 04:34:01 PM PDT 24
Peak memory 211320 kb
Host smart-14e3684c-18e1-4f71-ace6-559472599661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767677575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2767677575
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3951305599
Short name T224
Test name
Test status
Simulation time 693118453 ps
CPU time 9.38 seconds
Started Aug 14 04:34:08 PM PDT 24
Finished Aug 14 04:34:18 PM PDT 24
Peak memory 212100 kb
Host smart-f5f4bbfd-9587-486f-88d8-73e3fa231f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951305599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3951305599
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1688210926
Short name T201
Test name
Test status
Simulation time 536814506 ps
CPU time 6.25 seconds
Started Aug 14 04:34:06 PM PDT 24
Finished Aug 14 04:34:12 PM PDT 24
Peak memory 211292 kb
Host smart-582bf387-a04d-4532-a374-bc838e175ede
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1688210926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1688210926
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3009603230
Short name T63
Test name
Test status
Simulation time 1211753970 ps
CPU time 13.98 seconds
Started Aug 14 04:34:03 PM PDT 24
Finished Aug 14 04:34:17 PM PDT 24
Peak memory 213768 kb
Host smart-f89fe1c0-e4d5-4c95-95e4-98c7aa17b979
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009603230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3009603230
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2085220216
Short name T264
Test name
Test status
Simulation time 233136672 ps
CPU time 4.25 seconds
Started Aug 14 04:33:56 PM PDT 24
Finished Aug 14 04:34:01 PM PDT 24
Peak memory 211304 kb
Host smart-bad2b7fc-374d-40ef-ae58-dd182c1eb42d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085220216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2085220216
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3479374510
Short name T136
Test name
Test status
Simulation time 7382294625 ps
CPU time 117.74 seconds
Started Aug 14 04:33:54 PM PDT 24
Finished Aug 14 04:35:52 PM PDT 24
Peak memory 228348 kb
Host smart-183fdd48-13bb-445c-bed7-d0d9431fb15c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479374510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3479374510
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3156559038
Short name T44
Test name
Test status
Simulation time 175725260 ps
CPU time 9.53 seconds
Started Aug 14 04:34:07 PM PDT 24
Finished Aug 14 04:34:17 PM PDT 24
Peak memory 212148 kb
Host smart-2f320d7a-b7de-4087-94e0-165d8cf4b531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156559038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3156559038
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3757274103
Short name T231
Test name
Test status
Simulation time 276706826 ps
CPU time 6.19 seconds
Started Aug 14 04:34:08 PM PDT 24
Finished Aug 14 04:34:14 PM PDT 24
Peak memory 211332 kb
Host smart-ef3a99ce-3029-4e7f-b858-04000e1d7558
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3757274103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3757274103
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1014768986
Short name T124
Test name
Test status
Simulation time 801169512 ps
CPU time 17.63 seconds
Started Aug 14 04:34:00 PM PDT 24
Finished Aug 14 04:34:18 PM PDT 24
Peak memory 214888 kb
Host smart-78dfb571-029e-447b-b340-46b4ed668254
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014768986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1014768986
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3564610429
Short name T279
Test name
Test status
Simulation time 129698556 ps
CPU time 5.22 seconds
Started Aug 14 04:33:57 PM PDT 24
Finished Aug 14 04:34:03 PM PDT 24
Peak memory 211388 kb
Host smart-b346b921-899b-4b5c-b8d8-7fd0a03a597e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564610429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3564610429
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2731565882
Short name T166
Test name
Test status
Simulation time 2507072180 ps
CPU time 155.35 seconds
Started Aug 14 04:33:53 PM PDT 24
Finished Aug 14 04:36:29 PM PDT 24
Peak memory 238768 kb
Host smart-9ce3faad-c104-480f-aefa-3e3af2ea34b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731565882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2731565882
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2799440038
Short name T243
Test name
Test status
Simulation time 1842887531 ps
CPU time 9.39 seconds
Started Aug 14 04:34:18 PM PDT 24
Finished Aug 14 04:34:28 PM PDT 24
Peak memory 212248 kb
Host smart-8a4d9901-3a66-417a-9616-ea7344289f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799440038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2799440038
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4042243621
Short name T114
Test name
Test status
Simulation time 2909622015 ps
CPU time 8.75 seconds
Started Aug 14 04:34:06 PM PDT 24
Finished Aug 14 04:34:15 PM PDT 24
Peak memory 211484 kb
Host smart-50f17163-83c8-4a10-b87f-383b6714f884
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4042243621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4042243621
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3095817110
Short name T19
Test name
Test status
Simulation time 839621773 ps
CPU time 19.79 seconds
Started Aug 14 04:34:22 PM PDT 24
Finished Aug 14 04:34:47 PM PDT 24
Peak memory 216016 kb
Host smart-15e2cd39-f1c3-43e1-801e-78d14fe7807e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095817110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3095817110
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.976023885
Short name T242
Test name
Test status
Simulation time 461268192 ps
CPU time 5.23 seconds
Started Aug 14 04:34:00 PM PDT 24
Finished Aug 14 04:34:05 PM PDT 24
Peak memory 211340 kb
Host smart-c37d7805-a84f-4d7d-aa32-65ecdb82eced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976023885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.976023885
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1104515525
Short name T173
Test name
Test status
Simulation time 1777794825 ps
CPU time 114.8 seconds
Started Aug 14 04:33:55 PM PDT 24
Finished Aug 14 04:35:50 PM PDT 24
Peak memory 234144 kb
Host smart-538e3007-c83e-402e-af26-13abf0e1b32a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104515525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1104515525
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3211269058
Short name T251
Test name
Test status
Simulation time 697925452 ps
CPU time 9.45 seconds
Started Aug 14 04:34:01 PM PDT 24
Finished Aug 14 04:34:10 PM PDT 24
Peak memory 212256 kb
Host smart-0590f639-100c-46c6-a42e-ec6f6e6815bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211269058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3211269058
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1145991673
Short name T125
Test name
Test status
Simulation time 294682092 ps
CPU time 6.43 seconds
Started Aug 14 04:33:49 PM PDT 24
Finished Aug 14 04:33:56 PM PDT 24
Peak memory 211308 kb
Host smart-f4954e6c-3cbc-4497-ad8d-b05bd6f37c8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1145991673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1145991673
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.57188971
Short name T31
Test name
Test status
Simulation time 2533219347 ps
CPU time 100.44 seconds
Started Aug 14 04:34:06 PM PDT 24
Finished Aug 14 04:35:46 PM PDT 24
Peak memory 236768 kb
Host smart-e133dd5c-ea66-454d-8339-bc41bf169779
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57188971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.57188971
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.4158478170
Short name T281
Test name
Test status
Simulation time 545606011 ps
CPU time 5.96 seconds
Started Aug 14 04:34:00 PM PDT 24
Finished Aug 14 04:34:06 PM PDT 24
Peak memory 211376 kb
Host smart-c6d2b722-8323-4fd7-8028-4acee4f5b635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158478170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.4158478170
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2576289215
Short name T216
Test name
Test status
Simulation time 551074779 ps
CPU time 7.85 seconds
Started Aug 14 04:33:50 PM PDT 24
Finished Aug 14 04:33:58 PM PDT 24
Peak memory 212604 kb
Host smart-9eaa16ea-343c-43d6-97a3-2f61831647b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576289215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2576289215
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.429771000
Short name T273
Test name
Test status
Simulation time 499435451 ps
CPU time 5.12 seconds
Started Aug 14 04:34:29 PM PDT 24
Finished Aug 14 04:34:34 PM PDT 24
Peak memory 211236 kb
Host smart-bd3b259a-fe6f-4873-be95-0d79a1fed567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429771000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.429771000
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.13766577
Short name T255
Test name
Test status
Simulation time 3138095811 ps
CPU time 79.69 seconds
Started Aug 14 04:34:09 PM PDT 24
Finished Aug 14 04:35:29 PM PDT 24
Peak memory 237728 kb
Host smart-6e232471-e3b6-4a02-8bb2-0ef002775a68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13766577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_co
rrupt_sig_fatal_chk.13766577
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3654559371
Short name T222
Test name
Test status
Simulation time 1848910614 ps
CPU time 9.51 seconds
Started Aug 14 04:34:18 PM PDT 24
Finished Aug 14 04:34:28 PM PDT 24
Peak memory 212008 kb
Host smart-d2bd50f9-de11-4ac3-b293-a2764f472953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654559371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3654559371
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2838785656
Short name T38
Test name
Test status
Simulation time 306828632 ps
CPU time 12.62 seconds
Started Aug 14 04:34:25 PM PDT 24
Finished Aug 14 04:34:38 PM PDT 24
Peak memory 214060 kb
Host smart-38d8eead-c606-45ab-908a-f0ea7c501131
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838785656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2838785656
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3078842900
Short name T247
Test name
Test status
Simulation time 323002074 ps
CPU time 4.22 seconds
Started Aug 14 04:34:33 PM PDT 24
Finished Aug 14 04:34:37 PM PDT 24
Peak memory 211372 kb
Host smart-924ef331-4590-4435-bd6a-b26300b5cbcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078842900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3078842900
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2234353455
Short name T303
Test name
Test status
Simulation time 1740831951 ps
CPU time 80.71 seconds
Started Aug 14 04:34:16 PM PDT 24
Finished Aug 14 04:35:37 PM PDT 24
Peak memory 227244 kb
Host smart-a17b3104-19d8-42c4-8821-35b72018cd2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234353455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2234353455
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3075829936
Short name T250
Test name
Test status
Simulation time 666762197 ps
CPU time 9.26 seconds
Started Aug 14 04:34:13 PM PDT 24
Finished Aug 14 04:34:22 PM PDT 24
Peak memory 212232 kb
Host smart-f63f43d2-bd4d-4560-aa98-cad7e340b1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075829936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3075829936
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3769087810
Short name T60
Test name
Test status
Simulation time 2205098417 ps
CPU time 6.52 seconds
Started Aug 14 04:34:20 PM PDT 24
Finished Aug 14 04:34:27 PM PDT 24
Peak memory 211368 kb
Host smart-95584db1-4f39-4f66-870c-0365f8bb776c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3769087810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3769087810
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2269928430
Short name T88
Test name
Test status
Simulation time 301296342 ps
CPU time 15.83 seconds
Started Aug 14 04:34:10 PM PDT 24
Finished Aug 14 04:34:26 PM PDT 24
Peak memory 213992 kb
Host smart-8cd6bccf-fd61-4342-bb24-84446f8ab7ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269928430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2269928430
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3100395127
Short name T26
Test name
Test status
Simulation time 1031237631 ps
CPU time 5.09 seconds
Started Aug 14 04:34:04 PM PDT 24
Finished Aug 14 04:34:09 PM PDT 24
Peak memory 211264 kb
Host smart-a44a0f9c-201e-4eef-a494-3c2caff2f06a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100395127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3100395127
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.218452991
Short name T14
Test name
Test status
Simulation time 15783008773 ps
CPU time 196.38 seconds
Started Aug 14 04:34:16 PM PDT 24
Finished Aug 14 04:37:32 PM PDT 24
Peak memory 234180 kb
Host smart-020e14b4-2b36-40fe-b7a9-d4e9ed9bb68a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218452991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.218452991
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.586078892
Short name T232
Test name
Test status
Simulation time 1001017203 ps
CPU time 11.06 seconds
Started Aug 14 04:34:25 PM PDT 24
Finished Aug 14 04:34:37 PM PDT 24
Peak memory 212368 kb
Host smart-e37fcd0f-27de-4efe-945b-eef0e1b8dc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586078892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.586078892
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2665543600
Short name T211
Test name
Test status
Simulation time 143614845 ps
CPU time 7.81 seconds
Started Aug 14 04:34:10 PM PDT 24
Finished Aug 14 04:34:18 PM PDT 24
Peak memory 211340 kb
Host smart-bca1df7c-6794-4954-b960-08ec41489c46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665543600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2665543600
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1779756674
Short name T112
Test name
Test status
Simulation time 259336590 ps
CPU time 5.11 seconds
Started Aug 14 04:34:00 PM PDT 24
Finished Aug 14 04:34:05 PM PDT 24
Peak memory 211296 kb
Host smart-8245bf99-d4a7-4455-98cd-45c23fd402ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779756674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1779756674
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4150749222
Short name T169
Test name
Test status
Simulation time 3308716196 ps
CPU time 62.06 seconds
Started Aug 14 04:34:09 PM PDT 24
Finished Aug 14 04:35:11 PM PDT 24
Peak memory 236824 kb
Host smart-230ae2c8-5b03-42a5-8302-f6cdc1863130
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150749222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.4150749222
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2687429709
Short name T225
Test name
Test status
Simulation time 274748679 ps
CPU time 6.47 seconds
Started Aug 14 04:34:10 PM PDT 24
Finished Aug 14 04:34:17 PM PDT 24
Peak memory 211284 kb
Host smart-326dd112-70a5-43c4-ba62-ed1248aefa02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2687429709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2687429709
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2597883825
Short name T18
Test name
Test status
Simulation time 1449993923 ps
CPU time 8.38 seconds
Started Aug 14 04:34:13 PM PDT 24
Finished Aug 14 04:34:21 PM PDT 24
Peak memory 212448 kb
Host smart-5179056a-171a-476b-9ad3-6f0d5b81898d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597883825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2597883825
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1669099519
Short name T58
Test name
Test status
Simulation time 333266056 ps
CPU time 4.09 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:17 PM PDT 24
Peak memory 211296 kb
Host smart-f311a682-e38d-496d-8ba8-6031e210c9c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669099519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1669099519
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1502977878
Short name T313
Test name
Test status
Simulation time 5247504946 ps
CPU time 130.9 seconds
Started Aug 14 04:34:14 PM PDT 24
Finished Aug 14 04:36:25 PM PDT 24
Peak memory 240040 kb
Host smart-cb53a620-f141-499b-8c2b-d538f0c1efae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502977878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1502977878
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2519863834
Short name T182
Test name
Test status
Simulation time 171334779 ps
CPU time 9.37 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:22 PM PDT 24
Peak memory 211388 kb
Host smart-caa3a604-2b0e-4111-9f30-073ecfda6f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519863834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2519863834
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1197326952
Short name T300
Test name
Test status
Simulation time 101182091 ps
CPU time 5.69 seconds
Started Aug 14 04:34:31 PM PDT 24
Finished Aug 14 04:34:37 PM PDT 24
Peak memory 211324 kb
Host smart-74d8ef46-6791-4b93-8e5a-6e493644521a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1197326952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1197326952
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.4250285637
Short name T175
Test name
Test status
Simulation time 425821629 ps
CPU time 7.34 seconds
Started Aug 14 04:34:13 PM PDT 24
Finished Aug 14 04:34:21 PM PDT 24
Peak memory 211400 kb
Host smart-9e4d4257-4524-41d6-b0b4-8e10be3a8733
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250285637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.4250285637
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1420298873
Short name T70
Test name
Test status
Simulation time 186869319 ps
CPU time 4.43 seconds
Started Aug 14 04:34:23 PM PDT 24
Finished Aug 14 04:34:27 PM PDT 24
Peak memory 211232 kb
Host smart-2dcdd626-cdf6-4149-95c2-53396aa8420a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420298873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1420298873
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.896630701
Short name T108
Test name
Test status
Simulation time 15392506466 ps
CPU time 183.97 seconds
Started Aug 14 04:34:36 PM PDT 24
Finished Aug 14 04:37:40 PM PDT 24
Peak memory 237916 kb
Host smart-a2ef5dd8-df5c-4ec7-b333-efb29a577c43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896630701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.896630701
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.4199103573
Short name T276
Test name
Test status
Simulation time 172377893 ps
CPU time 9.75 seconds
Started Aug 14 04:34:16 PM PDT 24
Finished Aug 14 04:34:26 PM PDT 24
Peak memory 212248 kb
Host smart-44091e1e-fcc8-454d-8390-04c49ee29bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199103573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.4199103573
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1730340329
Short name T122
Test name
Test status
Simulation time 118542798 ps
CPU time 5.47 seconds
Started Aug 14 04:34:24 PM PDT 24
Finished Aug 14 04:34:30 PM PDT 24
Peak memory 211308 kb
Host smart-3e6a656c-c4fb-407e-ae10-b21bf4f64359
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1730340329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1730340329
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3308176736
Short name T213
Test name
Test status
Simulation time 278783503 ps
CPU time 14.14 seconds
Started Aug 14 04:34:20 PM PDT 24
Finished Aug 14 04:34:34 PM PDT 24
Peak memory 214296 kb
Host smart-11fe71e1-ae46-4796-b1eb-753a25ca417f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308176736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3308176736
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3328830913
Short name T68
Test name
Test status
Simulation time 175461339 ps
CPU time 4.31 seconds
Started Aug 14 04:34:13 PM PDT 24
Finished Aug 14 04:34:18 PM PDT 24
Peak memory 211356 kb
Host smart-cc81f9e0-b1ef-4e34-bac8-0c7d6f4379bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328830913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3328830913
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2746716314
Short name T239
Test name
Test status
Simulation time 24983798471 ps
CPU time 271.91 seconds
Started Aug 14 04:34:03 PM PDT 24
Finished Aug 14 04:38:35 PM PDT 24
Peak memory 237896 kb
Host smart-76e2160a-3978-4000-bf0d-6b896832a5f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746716314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2746716314
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3720051239
Short name T285
Test name
Test status
Simulation time 2091750794 ps
CPU time 11.35 seconds
Started Aug 14 04:34:10 PM PDT 24
Finished Aug 14 04:34:22 PM PDT 24
Peak memory 212136 kb
Host smart-2215e4af-0209-47c2-812e-352f7806adb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720051239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3720051239
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3623984821
Short name T146
Test name
Test status
Simulation time 575451183 ps
CPU time 5.24 seconds
Started Aug 14 04:34:03 PM PDT 24
Finished Aug 14 04:34:08 PM PDT 24
Peak memory 211292 kb
Host smart-fc063f32-dd56-4e63-9bc2-8fbe13616200
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3623984821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3623984821
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2244955656
Short name T268
Test name
Test status
Simulation time 227757597 ps
CPU time 11.49 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:24 PM PDT 24
Peak memory 214028 kb
Host smart-b3633bb8-b705-4a35-b27d-88eaf7d9c296
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244955656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2244955656
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3833227004
Short name T181
Test name
Test status
Simulation time 86667059 ps
CPU time 4.49 seconds
Started Aug 14 04:34:11 PM PDT 24
Finished Aug 14 04:34:17 PM PDT 24
Peak memory 211392 kb
Host smart-72171544-9bf2-4f2e-8c89-ae9fac942a76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833227004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3833227004
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3469779703
Short name T195
Test name
Test status
Simulation time 352340691 ps
CPU time 9.52 seconds
Started Aug 14 04:34:01 PM PDT 24
Finished Aug 14 04:34:11 PM PDT 24
Peak memory 212592 kb
Host smart-8011a21f-7fac-4356-bd6b-a408fbc5861e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469779703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3469779703
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.922668082
Short name T35
Test name
Test status
Simulation time 745203649 ps
CPU time 6.38 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:24 PM PDT 24
Peak memory 211096 kb
Host smart-1eb6cd5f-4400-49f8-8425-984e1f9edbf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=922668082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.922668082
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3477662775
Short name T315
Test name
Test status
Simulation time 449487419 ps
CPU time 5.1 seconds
Started Aug 14 04:34:24 PM PDT 24
Finished Aug 14 04:34:29 PM PDT 24
Peak memory 211288 kb
Host smart-27ed20d1-1451-4d32-bf0c-9453cdaf56c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477662775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3477662775
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1188823792
Short name T178
Test name
Test status
Simulation time 1286531929 ps
CPU time 79.11 seconds
Started Aug 14 04:34:21 PM PDT 24
Finished Aug 14 04:35:40 PM PDT 24
Peak memory 237652 kb
Host smart-ff5d402a-a4a8-46f9-98fd-fe1429bbe71f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188823792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1188823792
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1346498557
Short name T179
Test name
Test status
Simulation time 409272775 ps
CPU time 9.37 seconds
Started Aug 14 04:34:14 PM PDT 24
Finished Aug 14 04:34:23 PM PDT 24
Peak memory 212104 kb
Host smart-1048a96e-955f-4ef4-a7b9-734ce6e1679d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346498557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1346498557
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.754194900
Short name T141
Test name
Test status
Simulation time 1014915383 ps
CPU time 6.07 seconds
Started Aug 14 04:34:15 PM PDT 24
Finished Aug 14 04:34:21 PM PDT 24
Peak memory 211396 kb
Host smart-a9461c5f-3371-414a-9fea-898f2423c67a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=754194900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.754194900
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.897335390
Short name T280
Test name
Test status
Simulation time 784021508 ps
CPU time 6.88 seconds
Started Aug 14 04:34:10 PM PDT 24
Finished Aug 14 04:34:22 PM PDT 24
Peak memory 211728 kb
Host smart-78d8b0cf-7962-4d3a-8874-fb03ffdd0f89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897335390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.897335390
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1492531482
Short name T297
Test name
Test status
Simulation time 508991437 ps
CPU time 7.35 seconds
Started Aug 14 04:34:19 PM PDT 24
Finished Aug 14 04:34:27 PM PDT 24
Peak memory 211352 kb
Host smart-b80bfb65-530b-4738-87c6-977fe4a9bd26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492531482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1492531482
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3473287512
Short name T263
Test name
Test status
Simulation time 13160111548 ps
CPU time 96.12 seconds
Started Aug 14 04:34:19 PM PDT 24
Finished Aug 14 04:35:55 PM PDT 24
Peak memory 237920 kb
Host smart-25ef90a1-8044-4e45-8ad9-5614226ee5b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473287512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3473287512
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.620407721
Short name T249
Test name
Test status
Simulation time 175332731 ps
CPU time 9.35 seconds
Started Aug 14 04:34:14 PM PDT 24
Finished Aug 14 04:34:23 PM PDT 24
Peak memory 212152 kb
Host smart-aa6366c6-aa50-4c52-b345-0e13909696bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620407721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.620407721
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3157032095
Short name T302
Test name
Test status
Simulation time 139371945 ps
CPU time 6.37 seconds
Started Aug 14 04:34:28 PM PDT 24
Finished Aug 14 04:34:38 PM PDT 24
Peak memory 211256 kb
Host smart-cb8aaf5b-179e-403d-b568-4fa0bf830d88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3157032095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3157032095
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3516352516
Short name T305
Test name
Test status
Simulation time 282547711 ps
CPU time 16.9 seconds
Started Aug 14 04:34:16 PM PDT 24
Finished Aug 14 04:34:33 PM PDT 24
Peak memory 214256 kb
Host smart-a0512c16-fbe9-4a54-bbe1-2420e9d9225f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516352516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3516352516
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1498776777
Short name T69
Test name
Test status
Simulation time 337421848 ps
CPU time 4.18 seconds
Started Aug 14 04:33:40 PM PDT 24
Finished Aug 14 04:33:44 PM PDT 24
Peak memory 211228 kb
Host smart-4e7b0c92-d06e-462b-a4e4-8fa6f2e4f064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498776777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1498776777
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3079073246
Short name T299
Test name
Test status
Simulation time 11773539621 ps
CPU time 201.97 seconds
Started Aug 14 04:33:54 PM PDT 24
Finished Aug 14 04:37:16 PM PDT 24
Peak memory 233948 kb
Host smart-b3ff83a0-b868-45e9-9b03-40e8abcb8346
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079073246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3079073246
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4143228968
Short name T180
Test name
Test status
Simulation time 258447245 ps
CPU time 11.27 seconds
Started Aug 14 04:33:48 PM PDT 24
Finished Aug 14 04:33:59 PM PDT 24
Peak memory 212332 kb
Host smart-1df96308-dc5c-4158-8ce9-94b76cc47c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143228968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4143228968
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1395050273
Short name T237
Test name
Test status
Simulation time 562029663 ps
CPU time 6.96 seconds
Started Aug 14 04:33:55 PM PDT 24
Finished Aug 14 04:34:02 PM PDT 24
Peak memory 211392 kb
Host smart-091eb716-0b6a-49d4-88f8-5c73789d78e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1395050273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1395050273
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1053503186
Short name T59
Test name
Test status
Simulation time 319184156 ps
CPU time 6.09 seconds
Started Aug 14 04:33:55 PM PDT 24
Finished Aug 14 04:34:01 PM PDT 24
Peak memory 211456 kb
Host smart-b9d3942c-68ba-4bea-be02-cc570e04a1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053503186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1053503186
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3029210633
Short name T156
Test name
Test status
Simulation time 416247915 ps
CPU time 12.44 seconds
Started Aug 14 04:33:49 PM PDT 24
Finished Aug 14 04:34:01 PM PDT 24
Peak memory 212684 kb
Host smart-dcc50169-9f95-4b1e-ba90-a1ee379a8a95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029210633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3029210633
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2689765344
Short name T295
Test name
Test status
Simulation time 521626380 ps
CPU time 5.12 seconds
Started Aug 14 04:34:16 PM PDT 24
Finished Aug 14 04:34:21 PM PDT 24
Peak memory 211256 kb
Host smart-e85d853e-6940-4572-9106-a4e4a7f82aff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689765344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2689765344
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.660462456
Short name T42
Test name
Test status
Simulation time 14113514944 ps
CPU time 105.04 seconds
Started Aug 14 04:34:19 PM PDT 24
Finished Aug 14 04:36:04 PM PDT 24
Peak memory 237572 kb
Host smart-0a111893-9e59-4add-9790-ffc14357e387
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660462456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.660462456
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.427155145
Short name T259
Test name
Test status
Simulation time 1274474447 ps
CPU time 9.64 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:22 PM PDT 24
Peak memory 212300 kb
Host smart-d53c5883-e773-4b90-8ea0-5efe1f369e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427155145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.427155145
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1207781961
Short name T1
Test name
Test status
Simulation time 2088044428 ps
CPU time 8.38 seconds
Started Aug 14 04:34:28 PM PDT 24
Finished Aug 14 04:34:37 PM PDT 24
Peak memory 211324 kb
Host smart-0397dfb1-38f9-4827-87f6-159d56c866fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1207781961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1207781961
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3986052016
Short name T241
Test name
Test status
Simulation time 1523320370 ps
CPU time 7.29 seconds
Started Aug 14 04:34:11 PM PDT 24
Finished Aug 14 04:34:18 PM PDT 24
Peak memory 211332 kb
Host smart-a736d37c-1563-4164-922f-283f449de905
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986052016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3986052016
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2545844340
Short name T71
Test name
Test status
Simulation time 127495415 ps
CPU time 4.97 seconds
Started Aug 14 04:34:36 PM PDT 24
Finished Aug 14 04:34:41 PM PDT 24
Peak memory 211288 kb
Host smart-6c7cd15c-f8d0-4577-90c0-f6853a87f656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545844340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2545844340
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2507588148
Short name T318
Test name
Test status
Simulation time 5215941319 ps
CPU time 142.55 seconds
Started Aug 14 04:34:11 PM PDT 24
Finished Aug 14 04:36:33 PM PDT 24
Peak memory 236804 kb
Host smart-89897e17-36c5-4a4d-b900-41c43c2eb79a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507588148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2507588148
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.4261158604
Short name T312
Test name
Test status
Simulation time 964762920 ps
CPU time 11.57 seconds
Started Aug 14 04:34:15 PM PDT 24
Finished Aug 14 04:34:27 PM PDT 24
Peak memory 212912 kb
Host smart-95b840e3-85e4-477a-bc98-5eaf4d5f20f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261158604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.4261158604
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.148287450
Short name T256
Test name
Test status
Simulation time 538559730 ps
CPU time 6.58 seconds
Started Aug 14 04:34:10 PM PDT 24
Finished Aug 14 04:34:17 PM PDT 24
Peak memory 211352 kb
Host smart-a9952a7b-172a-4957-b69d-1a61265e4591
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=148287450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.148287450
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.98736637
Short name T293
Test name
Test status
Simulation time 564409724 ps
CPU time 11.54 seconds
Started Aug 14 04:34:10 PM PDT 24
Finished Aug 14 04:34:22 PM PDT 24
Peak memory 212764 kb
Host smart-e1a408b9-e451-4387-8365-033555bf7eb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98736637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 31.rom_ctrl_stress_all.98736637
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.680116615
Short name T230
Test name
Test status
Simulation time 347937450 ps
CPU time 4.24 seconds
Started Aug 14 04:34:15 PM PDT 24
Finished Aug 14 04:34:19 PM PDT 24
Peak memory 211296 kb
Host smart-2c0211b8-9fe8-4dcd-9c9e-683c920414cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680116615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.680116615
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1154085206
Short name T228
Test name
Test status
Simulation time 1431439710 ps
CPU time 88.9 seconds
Started Aug 14 04:34:10 PM PDT 24
Finished Aug 14 04:35:39 PM PDT 24
Peak memory 228528 kb
Host smart-86cef2ea-756f-4856-8033-aac48cf9a669
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154085206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1154085206
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2163790463
Short name T194
Test name
Test status
Simulation time 694776997 ps
CPU time 9.32 seconds
Started Aug 14 04:34:06 PM PDT 24
Finished Aug 14 04:34:15 PM PDT 24
Peak memory 211964 kb
Host smart-a57da076-c1a8-421a-82e5-f090a9af2db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163790463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2163790463
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1620848002
Short name T200
Test name
Test status
Simulation time 484258534 ps
CPU time 5.55 seconds
Started Aug 14 04:34:14 PM PDT 24
Finished Aug 14 04:34:20 PM PDT 24
Peak memory 211308 kb
Host smart-9dfcfbbc-9509-4b6f-ae3e-99674f1139d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1620848002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1620848002
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1746032141
Short name T6
Test name
Test status
Simulation time 303501592 ps
CPU time 12.38 seconds
Started Aug 14 04:34:22 PM PDT 24
Finished Aug 14 04:34:35 PM PDT 24
Peak memory 211416 kb
Host smart-9d6facfa-5733-4c79-8e05-cf4654a1386e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746032141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1746032141
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1844251175
Short name T177
Test name
Test status
Simulation time 417700348 ps
CPU time 5.04 seconds
Started Aug 14 04:34:28 PM PDT 24
Finished Aug 14 04:34:33 PM PDT 24
Peak memory 211304 kb
Host smart-d5ad54aa-618b-41ce-8c3f-2b2d8b1fa20e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844251175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1844251175
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2748684510
Short name T193
Test name
Test status
Simulation time 9902922432 ps
CPU time 117.07 seconds
Started Aug 14 04:34:18 PM PDT 24
Finished Aug 14 04:36:16 PM PDT 24
Peak memory 213652 kb
Host smart-96cc3b3d-4bd2-4e25-ab19-aa8f4c18b7e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748684510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2748684510
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3230894825
Short name T187
Test name
Test status
Simulation time 1654202535 ps
CPU time 11.05 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:24 PM PDT 24
Peak memory 212172 kb
Host smart-1ecc0da2-13c6-49f8-96d9-9a65068ac323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230894825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3230894825
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1208251701
Short name T258
Test name
Test status
Simulation time 186769468 ps
CPU time 5.54 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:18 PM PDT 24
Peak memory 211332 kb
Host smart-5b8fae7b-d0c4-4a77-a1c5-717e328bfe49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1208251701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1208251701
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.4293006462
Short name T192
Test name
Test status
Simulation time 201781240 ps
CPU time 10.7 seconds
Started Aug 14 04:34:16 PM PDT 24
Finished Aug 14 04:34:27 PM PDT 24
Peak memory 213668 kb
Host smart-94cba7aa-ac7e-4038-a481-4aafd7d6d476
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293006462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.4293006462
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.563076994
Short name T184
Test name
Test status
Simulation time 498430773 ps
CPU time 5.01 seconds
Started Aug 14 04:34:37 PM PDT 24
Finished Aug 14 04:34:42 PM PDT 24
Peak memory 211368 kb
Host smart-a2a102b1-e158-4749-b8b4-88c77def6ae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563076994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.563076994
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2739211282
Short name T316
Test name
Test status
Simulation time 21042681118 ps
CPU time 116 seconds
Started Aug 14 04:34:25 PM PDT 24
Finished Aug 14 04:36:22 PM PDT 24
Peak memory 237788 kb
Host smart-cbc0466f-44c3-4a85-885e-c633cfcdf696
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739211282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2739211282
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3232189054
Short name T234
Test name
Test status
Simulation time 519866414 ps
CPU time 11.16 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:24 PM PDT 24
Peak memory 212188 kb
Host smart-a423f9fc-f89d-4d10-853a-5940294d9d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232189054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3232189054
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2094244206
Short name T139
Test name
Test status
Simulation time 182758122 ps
CPU time 5.65 seconds
Started Aug 14 04:34:28 PM PDT 24
Finished Aug 14 04:34:34 PM PDT 24
Peak memory 211380 kb
Host smart-0f4d4d3b-2fbe-44db-837f-fa2ec536e807
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2094244206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2094244206
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.789541373
Short name T62
Test name
Test status
Simulation time 637011523 ps
CPU time 9.92 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:23 PM PDT 24
Peak memory 212544 kb
Host smart-4d160b56-fa29-468c-9850-6ae4cf923c1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789541373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.789541373
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1958149637
Short name T41
Test name
Test status
Simulation time 3076901340 ps
CPU time 90.74 seconds
Started Aug 14 04:34:21 PM PDT 24
Finished Aug 14 04:35:52 PM PDT 24
Peak memory 237544 kb
Host smart-8e9e7a86-a245-4ee0-91b0-837a0d984977
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958149637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1958149637
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3478027761
Short name T253
Test name
Test status
Simulation time 253425848 ps
CPU time 11.01 seconds
Started Aug 14 04:34:14 PM PDT 24
Finished Aug 14 04:34:25 PM PDT 24
Peak memory 212340 kb
Host smart-60816ad0-1845-41e0-bb03-d7840e6f3578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478027761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3478027761
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1186309990
Short name T207
Test name
Test status
Simulation time 399032305 ps
CPU time 5.41 seconds
Started Aug 14 04:34:26 PM PDT 24
Finished Aug 14 04:34:31 PM PDT 24
Peak memory 211408 kb
Host smart-2b8298e5-f8ab-497d-ba92-a9207549be68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1186309990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1186309990
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.684054137
Short name T275
Test name
Test status
Simulation time 308263012 ps
CPU time 18.21 seconds
Started Aug 14 04:34:15 PM PDT 24
Finished Aug 14 04:34:33 PM PDT 24
Peak memory 214176 kb
Host smart-9a3ab4ea-557b-46f4-964c-c7dfacf0fca5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684054137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.684054137
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3379232429
Short name T304
Test name
Test status
Simulation time 128399606 ps
CPU time 5.16 seconds
Started Aug 14 04:34:39 PM PDT 24
Finished Aug 14 04:34:44 PM PDT 24
Peak memory 211316 kb
Host smart-a1af3300-61fc-4d31-b4fa-76bdbb41d472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379232429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3379232429
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1807184408
Short name T186
Test name
Test status
Simulation time 1716411922 ps
CPU time 107.74 seconds
Started Aug 14 04:34:15 PM PDT 24
Finished Aug 14 04:36:02 PM PDT 24
Peak memory 224860 kb
Host smart-805794e5-b2b7-44bf-aadc-3205cd7d55f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807184408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1807184408
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1758280093
Short name T164
Test name
Test status
Simulation time 542184037 ps
CPU time 9.52 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:22 PM PDT 24
Peak memory 212124 kb
Host smart-a40e29c2-2f05-45a3-9434-06a68e47b80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758280093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1758280093
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.4077546891
Short name T217
Test name
Test status
Simulation time 1021624759 ps
CPU time 8.42 seconds
Started Aug 14 04:34:29 PM PDT 24
Finished Aug 14 04:34:41 PM PDT 24
Peak memory 211396 kb
Host smart-49d5025a-6d04-498b-b42f-780282c93849
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4077546891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.4077546891
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2711357496
Short name T160
Test name
Test status
Simulation time 757549110 ps
CPU time 11.93 seconds
Started Aug 14 04:34:29 PM PDT 24
Finished Aug 14 04:34:41 PM PDT 24
Peak memory 214776 kb
Host smart-90b0d79c-0b36-4f93-8c2a-4913989f5e93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711357496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2711357496
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1242528040
Short name T236
Test name
Test status
Simulation time 520094823 ps
CPU time 5.18 seconds
Started Aug 14 04:34:13 PM PDT 24
Finished Aug 14 04:34:18 PM PDT 24
Peak memory 211296 kb
Host smart-13f39dc0-b181-4f77-8e45-cc5770dbcb57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242528040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1242528040
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1755842902
Short name T15
Test name
Test status
Simulation time 12018790064 ps
CPU time 88.69 seconds
Started Aug 14 04:34:10 PM PDT 24
Finished Aug 14 04:35:39 PM PDT 24
Peak memory 212732 kb
Host smart-3d44900b-274f-4dc5-b941-1b7e71dbe23b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755842902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1755842902
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1267023137
Short name T265
Test name
Test status
Simulation time 96456259 ps
CPU time 5.48 seconds
Started Aug 14 04:34:14 PM PDT 24
Finished Aug 14 04:34:20 PM PDT 24
Peak memory 211396 kb
Host smart-0660ebd6-d091-45c7-a961-24b04ca95dd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1267023137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1267023137
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2660953742
Short name T311
Test name
Test status
Simulation time 573137494 ps
CPU time 12.81 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:25 PM PDT 24
Peak memory 214644 kb
Host smart-dee5fbab-247a-4f67-aa6f-fc690b2d4816
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660953742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2660953742
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.675375925
Short name T73
Test name
Test status
Simulation time 1110180121 ps
CPU time 7.58 seconds
Started Aug 14 04:34:11 PM PDT 24
Finished Aug 14 04:34:18 PM PDT 24
Peak memory 211288 kb
Host smart-20685964-c533-48a3-839a-df3803e0bdfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675375925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.675375925
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2568398248
Short name T33
Test name
Test status
Simulation time 1298778607 ps
CPU time 88.97 seconds
Started Aug 14 04:34:19 PM PDT 24
Finished Aug 14 04:35:48 PM PDT 24
Peak memory 237796 kb
Host smart-eef127bf-8c34-4031-8601-b78cc222d11d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568398248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2568398248
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3339746317
Short name T197
Test name
Test status
Simulation time 255494741 ps
CPU time 11.31 seconds
Started Aug 14 04:34:23 PM PDT 24
Finished Aug 14 04:34:34 PM PDT 24
Peak memory 211436 kb
Host smart-6140edd7-527e-42d2-8144-2dc347124434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339746317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3339746317
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2312360600
Short name T257
Test name
Test status
Simulation time 370725884 ps
CPU time 5.64 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:18 PM PDT 24
Peak memory 211332 kb
Host smart-576cb902-19a0-401f-a100-8ba695258b21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2312360600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2312360600
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.358246186
Short name T163
Test name
Test status
Simulation time 452729391 ps
CPU time 7.51 seconds
Started Aug 14 04:34:22 PM PDT 24
Finished Aug 14 04:34:30 PM PDT 24
Peak memory 211488 kb
Host smart-b92850ea-11b9-4eb2-9f2e-f36012c5fea3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358246186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.358246186
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1744597611
Short name T8
Test name
Test status
Simulation time 263015197 ps
CPU time 5.15 seconds
Started Aug 14 04:34:23 PM PDT 24
Finished Aug 14 04:34:28 PM PDT 24
Peak memory 211264 kb
Host smart-8bd50ba9-3680-4b70-a611-652f694b2c8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744597611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1744597611
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3054423193
Short name T240
Test name
Test status
Simulation time 6533698475 ps
CPU time 64.41 seconds
Started Aug 14 04:34:39 PM PDT 24
Finished Aug 14 04:35:43 PM PDT 24
Peak memory 237708 kb
Host smart-ee33d5af-80a9-4f9c-8a44-04672ffd44e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054423193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3054423193
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2935525088
Short name T43
Test name
Test status
Simulation time 251449029 ps
CPU time 11.21 seconds
Started Aug 14 04:34:24 PM PDT 24
Finished Aug 14 04:34:35 PM PDT 24
Peak memory 212216 kb
Host smart-f8fca255-2c10-4223-85ee-6cf43d671751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935525088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2935525088
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.837768414
Short name T208
Test name
Test status
Simulation time 2609382630 ps
CPU time 6.48 seconds
Started Aug 14 04:34:13 PM PDT 24
Finished Aug 14 04:34:19 PM PDT 24
Peak memory 211396 kb
Host smart-0cbf3fc4-521b-429c-a9dd-cee9186f6881
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=837768414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.837768414
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2231511989
Short name T278
Test name
Test status
Simulation time 2851264817 ps
CPU time 18.85 seconds
Started Aug 14 04:34:21 PM PDT 24
Finished Aug 14 04:34:40 PM PDT 24
Peak memory 213376 kb
Host smart-e41e8586-b492-41d3-ba63-15268000b740
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231511989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2231511989
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2003305690
Short name T298
Test name
Test status
Simulation time 163528380 ps
CPU time 4.31 seconds
Started Aug 14 04:33:57 PM PDT 24
Finished Aug 14 04:34:01 PM PDT 24
Peak memory 211268 kb
Host smart-564f600a-adc4-4125-ab93-4f869c3b7e79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003305690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2003305690
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3020189839
Short name T271
Test name
Test status
Simulation time 3079717503 ps
CPU time 81.67 seconds
Started Aug 14 04:34:02 PM PDT 24
Finished Aug 14 04:35:23 PM PDT 24
Peak memory 237768 kb
Host smart-8d8f9ec9-ab2c-48a7-887f-b1550ec96e64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020189839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3020189839
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3167846348
Short name T267
Test name
Test status
Simulation time 619650971 ps
CPU time 9.79 seconds
Started Aug 14 04:33:58 PM PDT 24
Finished Aug 14 04:34:08 PM PDT 24
Peak memory 212312 kb
Host smart-a608cc09-c655-40d3-8d3f-3af6b15d4800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167846348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3167846348
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2319965143
Short name T252
Test name
Test status
Simulation time 527746131 ps
CPU time 6.3 seconds
Started Aug 14 04:33:57 PM PDT 24
Finished Aug 14 04:34:04 PM PDT 24
Peak memory 211252 kb
Host smart-7989411a-922d-4e12-8774-ae8bda879548
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2319965143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2319965143
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1338673813
Short name T32
Test name
Test status
Simulation time 286875357 ps
CPU time 102.1 seconds
Started Aug 14 04:33:58 PM PDT 24
Finished Aug 14 04:35:40 PM PDT 24
Peak memory 236688 kb
Host smart-1394c1c2-882b-4037-acdb-765fbc7f1df2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338673813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1338673813
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1479644870
Short name T272
Test name
Test status
Simulation time 2023396362 ps
CPU time 8.72 seconds
Started Aug 14 04:34:03 PM PDT 24
Finished Aug 14 04:34:11 PM PDT 24
Peak memory 212148 kb
Host smart-c7e894ea-9340-4ad7-943f-e800b5141df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479644870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1479644870
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3004744851
Short name T157
Test name
Test status
Simulation time 318307455 ps
CPU time 13.09 seconds
Started Aug 14 04:33:50 PM PDT 24
Finished Aug 14 04:34:03 PM PDT 24
Peak memory 214404 kb
Host smart-a23bd8b1-2634-467c-aacc-455d1f790bc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004744851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3004744851
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2309022878
Short name T3
Test name
Test status
Simulation time 85771359 ps
CPU time 4.15 seconds
Started Aug 14 04:34:25 PM PDT 24
Finished Aug 14 04:34:29 PM PDT 24
Peak memory 211316 kb
Host smart-223d268a-e912-4688-a6da-93b81a5a0356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309022878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2309022878
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.418496419
Short name T309
Test name
Test status
Simulation time 1676946887 ps
CPU time 97.26 seconds
Started Aug 14 04:34:24 PM PDT 24
Finished Aug 14 04:36:02 PM PDT 24
Peak memory 237120 kb
Host smart-aae59457-a384-4cdf-b655-cb6594dc0dbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418496419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.418496419
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.480682989
Short name T190
Test name
Test status
Simulation time 1671943042 ps
CPU time 9.45 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:22 PM PDT 24
Peak memory 212176 kb
Host smart-13fb8b15-cdb7-47ee-b4a4-0596c38e1ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480682989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.480682989
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2771398582
Short name T289
Test name
Test status
Simulation time 438258794 ps
CPU time 5.38 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:18 PM PDT 24
Peak memory 211268 kb
Host smart-bd93cb6e-8716-46d5-81d9-62d211457f95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2771398582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2771398582
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2201671299
Short name T159
Test name
Test status
Simulation time 135955679 ps
CPU time 8.06 seconds
Started Aug 14 04:34:24 PM PDT 24
Finished Aug 14 04:34:32 PM PDT 24
Peak memory 211308 kb
Host smart-e9f516a8-1265-4114-a381-61823f4d81f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201671299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2201671299
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3099287704
Short name T161
Test name
Test status
Simulation time 196600942 ps
CPU time 4.2 seconds
Started Aug 14 04:34:13 PM PDT 24
Finished Aug 14 04:34:18 PM PDT 24
Peak memory 211296 kb
Host smart-d2eed496-869c-42a2-ae03-e7c0b885e6da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099287704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3099287704
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2271240300
Short name T20
Test name
Test status
Simulation time 1122858862 ps
CPU time 69.45 seconds
Started Aug 14 04:34:19 PM PDT 24
Finished Aug 14 04:35:29 PM PDT 24
Peak memory 212672 kb
Host smart-d7427b50-3a68-47aa-870b-dc0820bc7979
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271240300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2271240300
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1103694215
Short name T10
Test name
Test status
Simulation time 177980060 ps
CPU time 9.65 seconds
Started Aug 14 04:34:11 PM PDT 24
Finished Aug 14 04:34:21 PM PDT 24
Peak memory 212052 kb
Host smart-b437f36c-4e9d-4271-a37c-2dd4589b7adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103694215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1103694215
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3156439236
Short name T144
Test name
Test status
Simulation time 166702269 ps
CPU time 6.59 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:19 PM PDT 24
Peak memory 211308 kb
Host smart-8e2a3f57-b19f-4a1b-a831-fa8ce057a7ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3156439236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3156439236
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1335127318
Short name T158
Test name
Test status
Simulation time 308025831 ps
CPU time 15.23 seconds
Started Aug 14 04:34:20 PM PDT 24
Finished Aug 14 04:34:35 PM PDT 24
Peak memory 214672 kb
Host smart-9fb6522d-aef8-4f1e-91fc-ca6e70e44f28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335127318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1335127318
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.777953324
Short name T109
Test name
Test status
Simulation time 496374513 ps
CPU time 5.22 seconds
Started Aug 14 04:34:17 PM PDT 24
Finished Aug 14 04:34:22 PM PDT 24
Peak memory 211388 kb
Host smart-67c572a1-f55e-4666-931e-a2ca666da1c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777953324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.777953324
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1230057978
Short name T260
Test name
Test status
Simulation time 3859405764 ps
CPU time 92.63 seconds
Started Aug 14 04:34:09 PM PDT 24
Finished Aug 14 04:35:42 PM PDT 24
Peak memory 228580 kb
Host smart-909fcb30-54cc-4de4-b663-52fe5902df84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230057978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1230057978
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.444935201
Short name T254
Test name
Test status
Simulation time 672077369 ps
CPU time 9.13 seconds
Started Aug 14 04:34:34 PM PDT 24
Finished Aug 14 04:34:44 PM PDT 24
Peak memory 212264 kb
Host smart-4e65c7da-cf96-4448-95ef-21c94fee9e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444935201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.444935201
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.746273044
Short name T214
Test name
Test status
Simulation time 99472616 ps
CPU time 5.75 seconds
Started Aug 14 04:34:13 PM PDT 24
Finished Aug 14 04:34:19 PM PDT 24
Peak memory 211312 kb
Host smart-c5ea3c00-638e-488f-b09d-20c1fef3bb57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=746273044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.746273044
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1773183627
Short name T53
Test name
Test status
Simulation time 166706626 ps
CPU time 7.48 seconds
Started Aug 14 04:34:26 PM PDT 24
Finished Aug 14 04:34:38 PM PDT 24
Peak memory 211320 kb
Host smart-1e5375db-73de-4fbd-89b4-f94916aaf8aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773183627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1773183627
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.418839175
Short name T171
Test name
Test status
Simulation time 173657156 ps
CPU time 4.36 seconds
Started Aug 14 04:34:13 PM PDT 24
Finished Aug 14 04:34:18 PM PDT 24
Peak memory 211296 kb
Host smart-1954e316-692f-46dc-baf8-b2410e70c499
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418839175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.418839175
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2531795372
Short name T317
Test name
Test status
Simulation time 1618155332 ps
CPU time 80.1 seconds
Started Aug 14 04:34:45 PM PDT 24
Finished Aug 14 04:36:05 PM PDT 24
Peak memory 237800 kb
Host smart-729cad81-bc72-4bbd-8e96-9c9616fcb8cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531795372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2531795372
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2955424649
Short name T107
Test name
Test status
Simulation time 260179603 ps
CPU time 11.17 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:24 PM PDT 24
Peak memory 212192 kb
Host smart-3262b075-a03c-4a68-ad2f-a66c1cc98092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955424649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2955424649
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.519044781
Short name T61
Test name
Test status
Simulation time 138326454 ps
CPU time 6.59 seconds
Started Aug 14 04:34:22 PM PDT 24
Finished Aug 14 04:34:29 PM PDT 24
Peak memory 211380 kb
Host smart-14cf5691-ed9e-4f56-bd7f-5b8661eb5a09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=519044781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.519044781
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.4066016643
Short name T40
Test name
Test status
Simulation time 1031168842 ps
CPU time 22.05 seconds
Started Aug 14 04:34:26 PM PDT 24
Finished Aug 14 04:34:48 PM PDT 24
Peak memory 213824 kb
Host smart-ce55b375-4e58-4d9a-a113-5a4391e053ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066016643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.4066016643
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1540043390
Short name T270
Test name
Test status
Simulation time 635472027 ps
CPU time 7.38 seconds
Started Aug 14 04:34:16 PM PDT 24
Finished Aug 14 04:34:24 PM PDT 24
Peak memory 211380 kb
Host smart-4238509a-6091-4b06-ae79-c9fee304d31e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540043390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1540043390
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1544979436
Short name T191
Test name
Test status
Simulation time 1727194077 ps
CPU time 101.1 seconds
Started Aug 14 04:34:15 PM PDT 24
Finished Aug 14 04:35:56 PM PDT 24
Peak memory 236556 kb
Host smart-2f89e3dc-9fba-4dcd-8533-b36f55955f30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544979436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1544979436
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2236032728
Short name T7
Test name
Test status
Simulation time 492302616 ps
CPU time 11.08 seconds
Started Aug 14 04:34:16 PM PDT 24
Finished Aug 14 04:34:28 PM PDT 24
Peak memory 212508 kb
Host smart-f2044d9c-43c2-4def-a888-12f06fab3854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236032728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2236032728
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.434113708
Short name T287
Test name
Test status
Simulation time 284727094 ps
CPU time 6.63 seconds
Started Aug 14 04:34:14 PM PDT 24
Finished Aug 14 04:34:21 PM PDT 24
Peak memory 211508 kb
Host smart-9d9e999f-efed-4322-842e-b705a054f2ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=434113708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.434113708
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3965440149
Short name T301
Test name
Test status
Simulation time 3842792441 ps
CPU time 16.65 seconds
Started Aug 14 04:34:11 PM PDT 24
Finished Aug 14 04:34:28 PM PDT 24
Peak memory 215232 kb
Host smart-0012aef6-520b-45f4-8424-f36051adaf4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965440149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3965440149
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2742886823
Short name T223
Test name
Test status
Simulation time 132493566 ps
CPU time 4.99 seconds
Started Aug 14 04:34:30 PM PDT 24
Finished Aug 14 04:34:35 PM PDT 24
Peak memory 211364 kb
Host smart-824e9416-bb69-4240-a616-7d4a0c99b1c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742886823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2742886823
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2414250597
Short name T155
Test name
Test status
Simulation time 15336926623 ps
CPU time 181.82 seconds
Started Aug 14 04:34:18 PM PDT 24
Finished Aug 14 04:37:20 PM PDT 24
Peak memory 237756 kb
Host smart-1ce6616e-d5ff-4381-8012-6730f0c4298e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414250597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2414250597
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2410434483
Short name T188
Test name
Test status
Simulation time 252215942 ps
CPU time 11.3 seconds
Started Aug 14 04:34:23 PM PDT 24
Finished Aug 14 04:34:34 PM PDT 24
Peak memory 212220 kb
Host smart-c8021cac-6638-4217-b70b-fc1f23b66d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410434483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2410434483
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3174524036
Short name T209
Test name
Test status
Simulation time 684757485 ps
CPU time 5.78 seconds
Started Aug 14 04:34:22 PM PDT 24
Finished Aug 14 04:34:28 PM PDT 24
Peak memory 211312 kb
Host smart-d8097a31-cab8-42ae-bbb1-5d343a3f8fb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3174524036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3174524036
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3589869724
Short name T56
Test name
Test status
Simulation time 243695631 ps
CPU time 6.19 seconds
Started Aug 14 04:34:21 PM PDT 24
Finished Aug 14 04:34:28 PM PDT 24
Peak memory 211496 kb
Host smart-aee2247f-4bc3-471b-8622-35c45229a3b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589869724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3589869724
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2739031857
Short name T261
Test name
Test status
Simulation time 517598320 ps
CPU time 5.21 seconds
Started Aug 14 04:34:14 PM PDT 24
Finished Aug 14 04:34:19 PM PDT 24
Peak memory 211296 kb
Host smart-c4fdb6ca-34b8-4004-9ff9-ab7a2f6fde58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739031857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2739031857
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2531542419
Short name T291
Test name
Test status
Simulation time 1525705642 ps
CPU time 92.71 seconds
Started Aug 14 04:34:21 PM PDT 24
Finished Aug 14 04:35:54 PM PDT 24
Peak memory 237776 kb
Host smart-f1c87714-d570-412d-8301-df9af5a4b7c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531542419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2531542419
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1522750395
Short name T245
Test name
Test status
Simulation time 259592450 ps
CPU time 10.95 seconds
Started Aug 14 04:34:26 PM PDT 24
Finished Aug 14 04:34:37 PM PDT 24
Peak memory 212344 kb
Host smart-aefb6499-7782-4e7f-b52b-2d31c85488b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522750395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1522750395
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1992659141
Short name T150
Test name
Test status
Simulation time 269953206 ps
CPU time 6.77 seconds
Started Aug 14 04:34:25 PM PDT 24
Finished Aug 14 04:34:32 PM PDT 24
Peak memory 211224 kb
Host smart-d2bf49f2-d01b-4c84-8a7e-e4f49328412b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1992659141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1992659141
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1711224957
Short name T165
Test name
Test status
Simulation time 854422851 ps
CPU time 21.75 seconds
Started Aug 14 04:34:29 PM PDT 24
Finished Aug 14 04:34:51 PM PDT 24
Peak memory 215376 kb
Host smart-3c15785d-dfb0-4202-8efb-eb9564e95c6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711224957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1711224957
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1076146256
Short name T282
Test name
Test status
Simulation time 697201146 ps
CPU time 4.2 seconds
Started Aug 14 04:34:34 PM PDT 24
Finished Aug 14 04:34:39 PM PDT 24
Peak memory 211276 kb
Host smart-aba9be26-8b82-48a0-8e2f-1263e2412d45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076146256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1076146256
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.295010233
Short name T137
Test name
Test status
Simulation time 7831321580 ps
CPU time 139.1 seconds
Started Aug 14 04:34:17 PM PDT 24
Finished Aug 14 04:36:37 PM PDT 24
Peak memory 224860 kb
Host smart-4b0dd8c5-c32b-4183-bcd2-619733a66bd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295010233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.295010233
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1316330272
Short name T262
Test name
Test status
Simulation time 168409917 ps
CPU time 9.27 seconds
Started Aug 14 04:34:17 PM PDT 24
Finished Aug 14 04:34:27 PM PDT 24
Peak memory 212112 kb
Host smart-9f0e3e05-5256-4f55-b8c0-994ba3aa7c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316330272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1316330272
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.359555931
Short name T145
Test name
Test status
Simulation time 339205906 ps
CPU time 5.52 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:18 PM PDT 24
Peak memory 211352 kb
Host smart-1ed20bb1-e5a5-4a0f-9840-da8e061c34ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=359555931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.359555931
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.393378959
Short name T248
Test name
Test status
Simulation time 1144527473 ps
CPU time 11.4 seconds
Started Aug 14 04:34:16 PM PDT 24
Finished Aug 14 04:34:28 PM PDT 24
Peak memory 211404 kb
Host smart-b5e66a2d-d692-4dcc-aabf-81997d6c9ba1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393378959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.393378959
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.236100006
Short name T196
Test name
Test status
Simulation time 569566052 ps
CPU time 5.21 seconds
Started Aug 14 04:34:30 PM PDT 24
Finished Aug 14 04:34:35 PM PDT 24
Peak memory 211376 kb
Host smart-54c8d03f-7a4c-4e10-95c0-c2e6cf2a1f3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236100006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.236100006
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2977609199
Short name T307
Test name
Test status
Simulation time 7737170760 ps
CPU time 109.51 seconds
Started Aug 14 04:34:21 PM PDT 24
Finished Aug 14 04:36:11 PM PDT 24
Peak memory 237808 kb
Host smart-3572a1ac-58b5-4388-a22e-2e1439686cb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977609199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2977609199
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1233439813
Short name T12
Test name
Test status
Simulation time 1249098359 ps
CPU time 11.47 seconds
Started Aug 14 04:34:45 PM PDT 24
Finished Aug 14 04:34:56 PM PDT 24
Peak memory 212180 kb
Host smart-d442cc26-99f0-45b8-b08c-18d72fb10d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233439813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1233439813
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3255209182
Short name T119
Test name
Test status
Simulation time 357492631 ps
CPU time 5.53 seconds
Started Aug 14 04:34:45 PM PDT 24
Finished Aug 14 04:34:50 PM PDT 24
Peak memory 211308 kb
Host smart-3b3d910b-4e95-4c75-97a3-ed65532710c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3255209182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3255209182
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2054644955
Short name T203
Test name
Test status
Simulation time 113071641 ps
CPU time 10.33 seconds
Started Aug 14 04:34:15 PM PDT 24
Finished Aug 14 04:34:26 PM PDT 24
Peak memory 211220 kb
Host smart-d400270e-8bb1-46f4-aa24-087790fc4b19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054644955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2054644955
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3421707460
Short name T246
Test name
Test status
Simulation time 130504231 ps
CPU time 5.35 seconds
Started Aug 14 04:34:36 PM PDT 24
Finished Aug 14 04:34:42 PM PDT 24
Peak memory 211368 kb
Host smart-911605a5-f8f5-49cc-9a8b-1835800f1170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421707460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3421707460
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1788894630
Short name T17
Test name
Test status
Simulation time 2781298312 ps
CPU time 148.93 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:36:41 PM PDT 24
Peak memory 237100 kb
Host smart-e6736424-6081-48d8-912e-e1bbe76d4900
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788894630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1788894630
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3648519221
Short name T235
Test name
Test status
Simulation time 336488886 ps
CPU time 9.25 seconds
Started Aug 14 04:34:22 PM PDT 24
Finished Aug 14 04:34:31 PM PDT 24
Peak memory 212236 kb
Host smart-6ac4250c-b8ec-4a27-9218-112c1484616c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648519221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3648519221
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.825137031
Short name T296
Test name
Test status
Simulation time 8403444289 ps
CPU time 8.62 seconds
Started Aug 14 04:34:31 PM PDT 24
Finished Aug 14 04:34:40 PM PDT 24
Peak memory 211516 kb
Host smart-11dcce36-3371-4f65-b5ed-8cb213c2fd82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=825137031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.825137031
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3961891337
Short name T170
Test name
Test status
Simulation time 229041755 ps
CPU time 12.7 seconds
Started Aug 14 04:34:16 PM PDT 24
Finished Aug 14 04:34:33 PM PDT 24
Peak memory 214608 kb
Host smart-a4612d8e-f09f-4fff-b434-5682fe54e266
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961891337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3961891337
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2180705777
Short name T266
Test name
Test status
Simulation time 754216505 ps
CPU time 4.22 seconds
Started Aug 14 04:33:53 PM PDT 24
Finished Aug 14 04:33:57 PM PDT 24
Peak memory 211316 kb
Host smart-331e81af-d0a1-490a-a94a-cb7730d431ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180705777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2180705777
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1954618385
Short name T162
Test name
Test status
Simulation time 2029033357 ps
CPU time 74.72 seconds
Started Aug 14 04:34:03 PM PDT 24
Finished Aug 14 04:35:18 PM PDT 24
Peak memory 237824 kb
Host smart-859243d2-a120-4de2-9573-ee4a32a02d72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954618385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1954618385
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4191390247
Short name T189
Test name
Test status
Simulation time 997123342 ps
CPU time 11.43 seconds
Started Aug 14 04:33:56 PM PDT 24
Finished Aug 14 04:34:08 PM PDT 24
Peak memory 212220 kb
Host smart-e468a97b-be37-49ab-a23b-97d31910bef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191390247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.4191390247
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2869230031
Short name T90
Test name
Test status
Simulation time 1292252708 ps
CPU time 5.75 seconds
Started Aug 14 04:33:47 PM PDT 24
Finished Aug 14 04:33:53 PM PDT 24
Peak memory 211376 kb
Host smart-b9d83f47-86e2-438b-af0f-273b41b42a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869230031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2869230031
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3371590530
Short name T152
Test name
Test status
Simulation time 120533620 ps
CPU time 7.89 seconds
Started Aug 14 04:33:59 PM PDT 24
Finished Aug 14 04:34:07 PM PDT 24
Peak memory 211344 kb
Host smart-83b20e37-456a-448b-89e1-b599f118b154
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371590530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3371590530
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.806651833
Short name T168
Test name
Test status
Simulation time 220094071 ps
CPU time 4.23 seconds
Started Aug 14 04:33:54 PM PDT 24
Finished Aug 14 04:33:58 PM PDT 24
Peak memory 211268 kb
Host smart-72566c81-aa83-448c-9a36-2ceb7529a277
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806651833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.806651833
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1260755283
Short name T138
Test name
Test status
Simulation time 2962184763 ps
CPU time 83.74 seconds
Started Aug 14 04:33:49 PM PDT 24
Finished Aug 14 04:35:13 PM PDT 24
Peak memory 228020 kb
Host smart-3be062a0-19b0-4d5e-ab27-c176ba54a056
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260755283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1260755283
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3075792585
Short name T111
Test name
Test status
Simulation time 257203953 ps
CPU time 11.42 seconds
Started Aug 14 04:33:56 PM PDT 24
Finished Aug 14 04:34:07 PM PDT 24
Peak memory 211364 kb
Host smart-8cbbb074-9660-476c-8695-43727d336a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075792585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3075792585
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1444568883
Short name T290
Test name
Test status
Simulation time 140667194 ps
CPU time 6.68 seconds
Started Aug 14 04:33:49 PM PDT 24
Finished Aug 14 04:33:56 PM PDT 24
Peak memory 211284 kb
Host smart-f761f10f-4d23-4238-af4d-bede78ca3a72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1444568883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1444568883
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1294473073
Short name T142
Test name
Test status
Simulation time 265775476 ps
CPU time 6.19 seconds
Started Aug 14 04:33:55 PM PDT 24
Finished Aug 14 04:34:02 PM PDT 24
Peak memory 211444 kb
Host smart-ea8693be-2a86-44f2-b7cc-1236579c12aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294473073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1294473073
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.626526632
Short name T110
Test name
Test status
Simulation time 165621566 ps
CPU time 8.55 seconds
Started Aug 14 04:34:05 PM PDT 24
Finished Aug 14 04:34:13 PM PDT 24
Peak memory 211372 kb
Host smart-6818d15f-1270-4436-bf76-ff92c89d7152
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626526632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.626526632
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3643529643
Short name T57
Test name
Test status
Simulation time 519143717 ps
CPU time 7.52 seconds
Started Aug 14 04:33:56 PM PDT 24
Finished Aug 14 04:34:03 PM PDT 24
Peak memory 211376 kb
Host smart-83a023c7-5faa-4f4a-9680-84fda6b308a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643529643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3643529643
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3831636337
Short name T212
Test name
Test status
Simulation time 3050380465 ps
CPU time 131.2 seconds
Started Aug 14 04:33:49 PM PDT 24
Finished Aug 14 04:36:00 PM PDT 24
Peak memory 228596 kb
Host smart-d22ced9b-31ae-4b3e-b1a0-aa57f926c799
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831636337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3831636337
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.806154200
Short name T319
Test name
Test status
Simulation time 176418499 ps
CPU time 9.7 seconds
Started Aug 14 04:33:52 PM PDT 24
Finished Aug 14 04:34:07 PM PDT 24
Peak memory 212312 kb
Host smart-1e789a10-6ef9-4ac0-a13b-d6177bd6cc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806154200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.806154200
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1423781021
Short name T206
Test name
Test status
Simulation time 555343084 ps
CPU time 6.71 seconds
Started Aug 14 04:33:45 PM PDT 24
Finished Aug 14 04:33:52 PM PDT 24
Peak memory 211304 kb
Host smart-5aa658c7-ca85-4dd4-a0d6-9427c7faabfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1423781021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1423781021
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1084916905
Short name T314
Test name
Test status
Simulation time 198643786 ps
CPU time 5.44 seconds
Started Aug 14 04:34:12 PM PDT 24
Finished Aug 14 04:34:18 PM PDT 24
Peak memory 211372 kb
Host smart-c8e29258-3693-4fd2-b0d0-88a0a3250eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084916905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1084916905
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1855014557
Short name T283
Test name
Test status
Simulation time 741905517 ps
CPU time 10.26 seconds
Started Aug 14 04:33:45 PM PDT 24
Finished Aug 14 04:33:55 PM PDT 24
Peak memory 213956 kb
Host smart-c6f62dae-2f15-4a3f-bbf4-8824191fae38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855014557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1855014557
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1302731724
Short name T167
Test name
Test status
Simulation time 320748673 ps
CPU time 5.17 seconds
Started Aug 14 04:33:56 PM PDT 24
Finished Aug 14 04:34:02 PM PDT 24
Peak memory 211292 kb
Host smart-cfb4bad5-4624-463d-9bd3-4eb33f2babff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302731724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1302731724
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3146648537
Short name T269
Test name
Test status
Simulation time 3171858168 ps
CPU time 197.28 seconds
Started Aug 14 04:34:11 PM PDT 24
Finished Aug 14 04:37:28 PM PDT 24
Peak memory 234932 kb
Host smart-dc5752de-3696-4ea3-bc23-3cc9c155e0d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146648537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3146648537
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3714636184
Short name T39
Test name
Test status
Simulation time 995150418 ps
CPU time 11.11 seconds
Started Aug 14 04:34:04 PM PDT 24
Finished Aug 14 04:34:15 PM PDT 24
Peak memory 212196 kb
Host smart-51f42e9a-9540-49cd-b0f4-cfad83d13b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714636184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3714636184
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1610621058
Short name T202
Test name
Test status
Simulation time 547511082 ps
CPU time 6.13 seconds
Started Aug 14 04:33:51 PM PDT 24
Finished Aug 14 04:33:57 PM PDT 24
Peak memory 211252 kb
Host smart-92f19dca-4493-40da-9a56-aec6f5db5f8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1610621058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1610621058
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.4057238865
Short name T52
Test name
Test status
Simulation time 609211229 ps
CPU time 6.58 seconds
Started Aug 14 04:33:52 PM PDT 24
Finished Aug 14 04:33:59 PM PDT 24
Peak memory 211640 kb
Host smart-cc533700-e7c2-4088-996e-5cd52fc83976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057238865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4057238865
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3223830085
Short name T176
Test name
Test status
Simulation time 694648821 ps
CPU time 9.94 seconds
Started Aug 14 04:34:08 PM PDT 24
Finished Aug 14 04:34:18 PM PDT 24
Peak memory 213500 kb
Host smart-45354310-f8c0-4f5b-bfed-0aee990e6025
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223830085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3223830085
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3672018148
Short name T308
Test name
Test status
Simulation time 498309864 ps
CPU time 5.13 seconds
Started Aug 14 04:33:59 PM PDT 24
Finished Aug 14 04:34:05 PM PDT 24
Peak memory 211224 kb
Host smart-d1285608-8ce8-48fb-b3c7-3cce96eae0a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672018148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3672018148
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.262424184
Short name T115
Test name
Test status
Simulation time 4608821843 ps
CPU time 106.14 seconds
Started Aug 14 04:33:55 PM PDT 24
Finished Aug 14 04:35:41 PM PDT 24
Peak memory 213720 kb
Host smart-d803f7fe-aed7-4aa9-9067-811fd979b030
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262424184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.262424184
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4025965430
Short name T310
Test name
Test status
Simulation time 501791962 ps
CPU time 11.05 seconds
Started Aug 14 04:34:20 PM PDT 24
Finished Aug 14 04:34:31 PM PDT 24
Peak memory 211396 kb
Host smart-edfdd38f-4997-4c5a-9c22-d10ee4c1815e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025965430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4025965430
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4092336125
Short name T199
Test name
Test status
Simulation time 94853472 ps
CPU time 5.35 seconds
Started Aug 14 04:34:13 PM PDT 24
Finished Aug 14 04:34:18 PM PDT 24
Peak memory 211308 kb
Host smart-1e833677-7f47-43eb-845f-41d644008e78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4092336125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4092336125
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3701207487
Short name T288
Test name
Test status
Simulation time 385537506 ps
CPU time 5.57 seconds
Started Aug 14 04:34:10 PM PDT 24
Finished Aug 14 04:34:16 PM PDT 24
Peak memory 211500 kb
Host smart-07e68871-b47e-402c-8878-454755e913e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701207487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3701207487
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1259419894
Short name T198
Test name
Test status
Simulation time 206747348 ps
CPU time 8.49 seconds
Started Aug 14 04:33:57 PM PDT 24
Finished Aug 14 04:34:05 PM PDT 24
Peak memory 211324 kb
Host smart-52b22856-ac19-45e4-a3a6-f60c8a19b0eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259419894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1259419894
Directory /workspace/9.rom_ctrl_stress_all/latest
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