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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.40 96.89 92.13 97.67 100.00 98.28 97.75 99.06


Total test records in report: 457
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T294 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1187832207 Aug 15 06:01:42 PM PDT 24 Aug 15 06:01:53 PM PDT 24 1036837023 ps
T295 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.358053020 Aug 15 06:01:27 PM PDT 24 Aug 15 06:01:33 PM PDT 24 137193036 ps
T296 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3951830035 Aug 15 06:01:26 PM PDT 24 Aug 15 06:01:32 PM PDT 24 141487176 ps
T297 /workspace/coverage/default/35.rom_ctrl_alert_test.2577108536 Aug 15 06:02:04 PM PDT 24 Aug 15 06:02:08 PM PDT 24 249350041 ps
T298 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2653202943 Aug 15 06:01:54 PM PDT 24 Aug 15 06:03:11 PM PDT 24 4004437631 ps
T299 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3006622490 Aug 15 06:01:50 PM PDT 24 Aug 15 06:01:55 PM PDT 24 1818874824 ps
T300 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1892160074 Aug 15 06:01:55 PM PDT 24 Aug 15 06:02:06 PM PDT 24 1041067214 ps
T301 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3042814253 Aug 15 06:01:27 PM PDT 24 Aug 15 06:01:33 PM PDT 24 272389229 ps
T302 /workspace/coverage/default/15.rom_ctrl_alert_test.97807136 Aug 15 06:01:34 PM PDT 24 Aug 15 06:01:39 PM PDT 24 261186771 ps
T303 /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2720328369 Aug 15 06:01:33 PM PDT 24 Aug 15 06:04:33 PM PDT 24 6088925612 ps
T304 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1784522031 Aug 15 06:01:56 PM PDT 24 Aug 15 06:02:01 PM PDT 24 185596969 ps
T305 /workspace/coverage/default/41.rom_ctrl_stress_all.522203947 Aug 15 06:02:11 PM PDT 24 Aug 15 06:02:26 PM PDT 24 286957256 ps
T306 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1707278992 Aug 15 06:01:34 PM PDT 24 Aug 15 06:01:44 PM PDT 24 995595591 ps
T307 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1694911451 Aug 15 06:01:42 PM PDT 24 Aug 15 06:01:51 PM PDT 24 169203865 ps
T308 /workspace/coverage/default/39.rom_ctrl_alert_test.2841376119 Aug 15 06:02:11 PM PDT 24 Aug 15 06:02:16 PM PDT 24 252806127 ps
T309 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3364194770 Aug 15 06:01:34 PM PDT 24 Aug 15 06:01:40 PM PDT 24 1111786079 ps
T310 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.223827996 Aug 15 06:01:28 PM PDT 24 Aug 15 06:01:35 PM PDT 24 261745373 ps
T311 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2607003329 Aug 15 06:01:12 PM PDT 24 Aug 15 06:03:09 PM PDT 24 13114263525 ps
T312 /workspace/coverage/default/13.rom_ctrl_stress_all.699072019 Aug 15 06:01:27 PM PDT 24 Aug 15 06:01:35 PM PDT 24 629159351 ps
T313 /workspace/coverage/default/40.rom_ctrl_alert_test.4249926692 Aug 15 06:02:14 PM PDT 24 Aug 15 06:02:18 PM PDT 24 333565149 ps
T314 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1248172994 Aug 15 06:01:48 PM PDT 24 Aug 15 06:05:03 PM PDT 24 16346832385 ps
T315 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3774475755 Aug 15 06:01:50 PM PDT 24 Aug 15 06:02:29 PM PDT 24 2426455521 ps
T316 /workspace/coverage/default/42.rom_ctrl_stress_all.3356473550 Aug 15 06:02:12 PM PDT 24 Aug 15 06:02:26 PM PDT 24 583108413 ps
T317 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.999158684 Aug 15 06:02:10 PM PDT 24 Aug 15 06:03:45 PM PDT 24 6604458617 ps
T318 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1961425110 Aug 15 06:01:13 PM PDT 24 Aug 15 06:01:19 PM PDT 24 135458354 ps
T319 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1529948286 Aug 15 06:02:17 PM PDT 24 Aug 15 06:03:50 PM PDT 24 20274336452 ps
T320 /workspace/coverage/default/34.rom_ctrl_alert_test.3003776141 Aug 15 06:02:00 PM PDT 24 Aug 15 06:02:05 PM PDT 24 520765778 ps
T321 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.623627465 Aug 15 06:01:21 PM PDT 24 Aug 15 06:01:27 PM PDT 24 195656568 ps
T322 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.155601885 Aug 15 06:01:49 PM PDT 24 Aug 15 06:01:58 PM PDT 24 192719246 ps
T323 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.413075063 Aug 15 06:02:11 PM PDT 24 Aug 15 06:02:20 PM PDT 24 598413508 ps
T324 /workspace/coverage/default/46.rom_ctrl_alert_test.429899857 Aug 15 06:02:18 PM PDT 24 Aug 15 06:02:23 PM PDT 24 460919490 ps
T325 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1637774112 Aug 15 06:01:55 PM PDT 24 Aug 15 06:03:56 PM PDT 24 8459675917 ps
T326 /workspace/coverage/default/29.rom_ctrl_stress_all.1603431778 Aug 15 06:01:56 PM PDT 24 Aug 15 06:02:11 PM PDT 24 611243094 ps
T327 /workspace/coverage/default/10.rom_ctrl_stress_all.3112233495 Aug 15 06:01:32 PM PDT 24 Aug 15 06:01:40 PM PDT 24 126935064 ps
T328 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2133790854 Aug 15 06:02:17 PM PDT 24 Aug 15 06:02:27 PM PDT 24 235993189 ps
T329 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.270189411 Aug 15 06:02:16 PM PDT 24 Aug 15 06:02:22 PM PDT 24 583428165 ps
T330 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1512512963 Aug 15 06:01:28 PM PDT 24 Aug 15 06:03:18 PM PDT 24 22386737492 ps
T331 /workspace/coverage/default/35.rom_ctrl_stress_all.4252151177 Aug 15 06:01:55 PM PDT 24 Aug 15 06:02:02 PM PDT 24 176387816 ps
T332 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3649980764 Aug 15 06:02:03 PM PDT 24 Aug 15 06:02:10 PM PDT 24 568379336 ps
T333 /workspace/coverage/default/10.rom_ctrl_alert_test.2372373833 Aug 15 06:01:28 PM PDT 24 Aug 15 06:01:33 PM PDT 24 251258594 ps
T334 /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3603490917 Aug 15 06:01:28 PM PDT 24 Aug 15 06:03:07 PM PDT 24 14161828980 ps
T335 /workspace/coverage/default/43.rom_ctrl_alert_test.2975722966 Aug 15 06:02:11 PM PDT 24 Aug 15 06:02:16 PM PDT 24 498030239 ps
T336 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3908878693 Aug 15 06:02:14 PM PDT 24 Aug 15 06:04:34 PM PDT 24 5374885290 ps
T337 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2722547047 Aug 15 06:01:57 PM PDT 24 Aug 15 06:02:04 PM PDT 24 145425521 ps
T338 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2559912472 Aug 15 06:01:49 PM PDT 24 Aug 15 06:02:03 PM PDT 24 993095947 ps
T339 /workspace/coverage/default/49.rom_ctrl_stress_all.2632778059 Aug 15 06:02:21 PM PDT 24 Aug 15 06:02:30 PM PDT 24 1318800816 ps
T340 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.502140552 Aug 15 06:01:14 PM PDT 24 Aug 15 06:02:55 PM PDT 24 8644998626 ps
T341 /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2274728936 Aug 15 06:01:16 PM PDT 24 Aug 15 06:03:56 PM PDT 24 8668864971 ps
T342 /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3813223459 Aug 15 06:01:27 PM PDT 24 Aug 15 06:02:04 PM PDT 24 3678078849 ps
T343 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3029335518 Aug 15 06:02:19 PM PDT 24 Aug 15 06:03:16 PM PDT 24 1179511980 ps
T344 /workspace/coverage/default/0.rom_ctrl_stress_all.3511532689 Aug 15 06:01:04 PM PDT 24 Aug 15 06:01:17 PM PDT 24 617987831 ps
T345 /workspace/coverage/default/31.rom_ctrl_alert_test.2739142645 Aug 15 06:01:55 PM PDT 24 Aug 15 06:02:00 PM PDT 24 291648572 ps
T346 /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.832680464 Aug 15 06:02:17 PM PDT 24 Aug 15 06:03:58 PM PDT 24 3213592260 ps
T347 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3996667551 Aug 15 06:01:22 PM PDT 24 Aug 15 06:01:33 PM PDT 24 521306307 ps
T348 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1908632301 Aug 15 06:01:27 PM PDT 24 Aug 15 06:02:48 PM PDT 24 14129578875 ps
T349 /workspace/coverage/default/29.rom_ctrl_alert_test.2197760438 Aug 15 06:01:55 PM PDT 24 Aug 15 06:02:00 PM PDT 24 130871668 ps
T350 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1624932364 Aug 15 06:02:00 PM PDT 24 Aug 15 06:03:29 PM PDT 24 2083762330 ps
T351 /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2163365033 Aug 15 06:01:23 PM PDT 24 Aug 15 06:07:02 PM PDT 24 19922555204 ps
T352 /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2871359619 Aug 15 06:01:50 PM PDT 24 Aug 15 06:02:06 PM PDT 24 1349513386 ps
T353 /workspace/coverage/default/8.rom_ctrl_alert_test.910189446 Aug 15 06:01:29 PM PDT 24 Aug 15 06:01:34 PM PDT 24 131924802 ps
T354 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2488356488 Aug 15 06:02:05 PM PDT 24 Aug 15 06:02:15 PM PDT 24 173691763 ps
T355 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.661586331 Aug 15 06:02:11 PM PDT 24 Aug 15 06:04:38 PM PDT 24 14519244416 ps
T57 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.35913370 Aug 15 06:02:39 PM PDT 24 Aug 15 06:02:59 PM PDT 24 549979081 ps
T58 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2154217380 Aug 15 06:02:45 PM PDT 24 Aug 15 06:02:49 PM PDT 24 517110658 ps
T356 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.383376917 Aug 15 06:02:45 PM PDT 24 Aug 15 06:02:53 PM PDT 24 250954333 ps
T59 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1985552854 Aug 15 06:02:25 PM PDT 24 Aug 15 06:02:30 PM PDT 24 261668476 ps
T357 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3577678383 Aug 15 06:02:23 PM PDT 24 Aug 15 06:02:28 PM PDT 24 1383922474 ps
T54 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.26974936 Aug 15 06:02:40 PM PDT 24 Aug 15 06:03:49 PM PDT 24 1234811526 ps
T358 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4022091167 Aug 15 06:02:45 PM PDT 24 Aug 15 06:02:50 PM PDT 24 110250738 ps
T359 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3454217085 Aug 15 06:02:48 PM PDT 24 Aug 15 06:02:54 PM PDT 24 140965649 ps
T360 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2483764721 Aug 15 06:02:27 PM PDT 24 Aug 15 06:02:32 PM PDT 24 518563393 ps
T61 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3261940869 Aug 15 06:02:39 PM PDT 24 Aug 15 06:03:05 PM PDT 24 540430767 ps
T361 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4088727714 Aug 15 06:02:38 PM PDT 24 Aug 15 06:02:46 PM PDT 24 90084250 ps
T362 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2288418784 Aug 15 06:02:45 PM PDT 24 Aug 15 06:02:50 PM PDT 24 575166170 ps
T62 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.350812407 Aug 15 06:02:18 PM PDT 24 Aug 15 06:02:36 PM PDT 24 377625768 ps
T63 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3346034996 Aug 15 06:02:46 PM PDT 24 Aug 15 06:02:52 PM PDT 24 131284697 ps
T55 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4167945847 Aug 15 06:02:39 PM PDT 24 Aug 15 06:03:47 PM PDT 24 392459275 ps
T56 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3769108593 Aug 15 06:02:25 PM PDT 24 Aug 15 06:03:02 PM PDT 24 644748160 ps
T90 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4282926585 Aug 15 06:02:50 PM PDT 24 Aug 15 06:03:57 PM PDT 24 561818257 ps
T363 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.282438427 Aug 15 06:02:25 PM PDT 24 Aug 15 06:02:32 PM PDT 24 130171898 ps
T364 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1062754366 Aug 15 06:02:19 PM PDT 24 Aug 15 06:02:28 PM PDT 24 518164208 ps
T365 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3096778617 Aug 15 06:02:39 PM PDT 24 Aug 15 06:02:46 PM PDT 24 126558446 ps
T64 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4236672509 Aug 15 06:02:24 PM PDT 24 Aug 15 06:02:29 PM PDT 24 833318476 ps
T366 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.812569670 Aug 15 06:02:42 PM PDT 24 Aug 15 06:02:48 PM PDT 24 512472785 ps
T65 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1992928601 Aug 15 06:02:39 PM PDT 24 Aug 15 06:02:44 PM PDT 24 244768582 ps
T367 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1679613590 Aug 15 06:02:29 PM PDT 24 Aug 15 06:02:34 PM PDT 24 130957083 ps
T368 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.514849162 Aug 15 06:02:32 PM PDT 24 Aug 15 06:02:36 PM PDT 24 87355140 ps
T66 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2512892671 Aug 15 06:02:46 PM PDT 24 Aug 15 06:02:51 PM PDT 24 131462408 ps
T84 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2420385292 Aug 15 06:02:39 PM PDT 24 Aug 15 06:02:45 PM PDT 24 180054013 ps
T67 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3860671089 Aug 15 06:02:53 PM PDT 24 Aug 15 06:02:59 PM PDT 24 93703263 ps
T85 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3968960514 Aug 15 06:02:50 PM PDT 24 Aug 15 06:02:54 PM PDT 24 308454255 ps
T369 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3346095702 Aug 15 06:02:55 PM PDT 24 Aug 15 06:03:04 PM PDT 24 175719701 ps
T370 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1622903591 Aug 15 06:02:40 PM PDT 24 Aug 15 06:02:44 PM PDT 24 334432307 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2149764938 Aug 15 06:02:29 PM PDT 24 Aug 15 06:02:48 PM PDT 24 813098083 ps
T372 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1270298127 Aug 15 06:02:40 PM PDT 24 Aug 15 06:02:58 PM PDT 24 368198634 ps
T91 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3569729137 Aug 15 06:02:38 PM PDT 24 Aug 15 06:03:15 PM PDT 24 380640547 ps
T373 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.294844969 Aug 15 06:02:25 PM PDT 24 Aug 15 06:02:30 PM PDT 24 372741752 ps
T374 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3253787659 Aug 15 06:02:39 PM PDT 24 Aug 15 06:02:44 PM PDT 24 199769123 ps
T375 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1211508758 Aug 15 06:02:41 PM PDT 24 Aug 15 06:02:46 PM PDT 24 392507790 ps
T376 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.448633148 Aug 15 06:02:34 PM PDT 24 Aug 15 06:02:45 PM PDT 24 656018211 ps
T377 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.204551242 Aug 15 06:02:50 PM PDT 24 Aug 15 06:03:12 PM PDT 24 2643790684 ps
T93 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3340020138 Aug 15 06:02:37 PM PDT 24 Aug 15 06:03:47 PM PDT 24 1349445024 ps
T68 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1836236902 Aug 15 06:02:33 PM PDT 24 Aug 15 06:03:04 PM PDT 24 1634014857 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.166740747 Aug 15 06:02:36 PM PDT 24 Aug 15 06:02:40 PM PDT 24 552449568 ps
T94 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.306272178 Aug 15 06:02:45 PM PDT 24 Aug 15 06:03:22 PM PDT 24 521892160 ps
T69 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3034962129 Aug 15 06:02:27 PM PDT 24 Aug 15 06:02:58 PM PDT 24 1520749233 ps
T72 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1268956326 Aug 15 06:02:33 PM PDT 24 Aug 15 06:02:37 PM PDT 24 88337897 ps
T379 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1681316255 Aug 15 06:02:38 PM PDT 24 Aug 15 06:02:46 PM PDT 24 131954191 ps
T73 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3663048432 Aug 15 06:02:48 PM PDT 24 Aug 15 06:03:06 PM PDT 24 1559272960 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3608255789 Aug 15 06:02:20 PM PDT 24 Aug 15 06:02:24 PM PDT 24 261260607 ps
T381 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.675500336 Aug 15 06:02:37 PM PDT 24 Aug 15 06:02:44 PM PDT 24 334706854 ps
T382 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2231573278 Aug 15 06:02:46 PM PDT 24 Aug 15 06:02:53 PM PDT 24 90130727 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.440369796 Aug 15 06:02:27 PM PDT 24 Aug 15 06:02:31 PM PDT 24 164891292 ps
T384 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2826291653 Aug 15 06:02:25 PM PDT 24 Aug 15 06:02:36 PM PDT 24 998753492 ps
T385 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2752399532 Aug 15 06:02:54 PM PDT 24 Aug 15 06:03:26 PM PDT 24 1643282228 ps
T86 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.379482700 Aug 15 06:02:22 PM PDT 24 Aug 15 06:02:27 PM PDT 24 778902729 ps
T74 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3029037929 Aug 15 06:02:32 PM PDT 24 Aug 15 06:02:37 PM PDT 24 129869854 ps
T92 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2400857886 Aug 15 06:02:23 PM PDT 24 Aug 15 06:03:00 PM PDT 24 538112921 ps
T386 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2112956599 Aug 15 06:02:21 PM PDT 24 Aug 15 06:02:27 PM PDT 24 387332683 ps
T387 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3312876782 Aug 15 06:02:40 PM PDT 24 Aug 15 06:02:46 PM PDT 24 1093463995 ps
T388 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.920658691 Aug 15 06:02:39 PM PDT 24 Aug 15 06:02:45 PM PDT 24 469032510 ps
T389 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.458883812 Aug 15 06:02:37 PM PDT 24 Aug 15 06:02:41 PM PDT 24 350017165 ps
T390 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3030874512 Aug 15 06:02:53 PM PDT 24 Aug 15 06:03:20 PM PDT 24 553925617 ps
T391 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.489156173 Aug 15 06:02:48 PM PDT 24 Aug 15 06:02:54 PM PDT 24 416555801 ps
T392 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1921509076 Aug 15 06:02:26 PM PDT 24 Aug 15 06:02:32 PM PDT 24 144224975 ps
T393 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3133387154 Aug 15 06:02:27 PM PDT 24 Aug 15 06:02:33 PM PDT 24 535962448 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.67464770 Aug 15 06:02:26 PM PDT 24 Aug 15 06:02:30 PM PDT 24 309562071 ps
T395 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1363796386 Aug 15 06:02:27 PM PDT 24 Aug 15 06:02:33 PM PDT 24 130030382 ps
T396 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3514992861 Aug 15 06:02:41 PM PDT 24 Aug 15 06:02:53 PM PDT 24 518349643 ps
T397 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2010556598 Aug 15 06:02:41 PM PDT 24 Aug 15 06:02:47 PM PDT 24 648697906 ps
T398 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1601759192 Aug 15 06:02:33 PM PDT 24 Aug 15 06:02:38 PM PDT 24 251710040 ps
T75 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2202210060 Aug 15 06:02:25 PM PDT 24 Aug 15 06:02:30 PM PDT 24 127644869 ps
T81 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3881470683 Aug 15 06:02:35 PM PDT 24 Aug 15 06:03:06 PM PDT 24 3263365074 ps
T399 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3718843376 Aug 15 06:02:26 PM PDT 24 Aug 15 06:02:31 PM PDT 24 138822925 ps
T95 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1047157293 Aug 15 06:02:48 PM PDT 24 Aug 15 06:03:25 PM PDT 24 330067792 ps
T100 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3097306527 Aug 15 06:02:46 PM PDT 24 Aug 15 06:03:55 PM PDT 24 251404573 ps
T400 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3032534167 Aug 15 06:02:47 PM PDT 24 Aug 15 06:02:52 PM PDT 24 543698047 ps
T401 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3158231686 Aug 15 06:02:24 PM PDT 24 Aug 15 06:02:29 PM PDT 24 270258345 ps
T402 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4185116685 Aug 15 06:02:35 PM PDT 24 Aug 15 06:02:41 PM PDT 24 355560239 ps
T403 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.375832705 Aug 15 06:02:42 PM PDT 24 Aug 15 06:02:51 PM PDT 24 520736293 ps
T404 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3279260369 Aug 15 06:02:55 PM PDT 24 Aug 15 06:03:00 PM PDT 24 85856455 ps
T405 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1744211393 Aug 15 06:02:43 PM PDT 24 Aug 15 06:03:19 PM PDT 24 1090817582 ps
T406 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1815544523 Aug 15 06:02:25 PM PDT 24 Aug 15 06:02:30 PM PDT 24 94785974 ps
T83 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3662775238 Aug 15 06:02:46 PM PDT 24 Aug 15 06:03:13 PM PDT 24 554230114 ps
T407 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1579201948 Aug 15 06:02:50 PM PDT 24 Aug 15 06:02:57 PM PDT 24 1721684732 ps
T408 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.984042573 Aug 15 06:02:46 PM PDT 24 Aug 15 06:02:55 PM PDT 24 509935958 ps
T409 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4156109998 Aug 15 06:02:54 PM PDT 24 Aug 15 06:02:59 PM PDT 24 182486380 ps
T410 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1578219692 Aug 15 06:02:34 PM PDT 24 Aug 15 06:02:39 PM PDT 24 132371171 ps
T411 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3062677802 Aug 15 06:02:39 PM PDT 24 Aug 15 06:03:48 PM PDT 24 3041848016 ps
T412 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1840116216 Aug 15 06:02:40 PM PDT 24 Aug 15 06:03:51 PM PDT 24 354541076 ps
T413 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1542945707 Aug 15 06:02:33 PM PDT 24 Aug 15 06:02:38 PM PDT 24 256221043 ps
T414 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3248638409 Aug 15 06:02:24 PM PDT 24 Aug 15 06:02:29 PM PDT 24 497283024 ps
T97 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3603126734 Aug 15 06:02:54 PM PDT 24 Aug 15 06:04:04 PM PDT 24 289390108 ps
T415 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2516138681 Aug 15 06:02:42 PM PDT 24 Aug 15 06:02:49 PM PDT 24 131809984 ps
T416 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3786694191 Aug 15 06:02:39 PM PDT 24 Aug 15 06:02:44 PM PDT 24 496406368 ps
T96 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2670420140 Aug 15 06:02:32 PM PDT 24 Aug 15 06:03:44 PM PDT 24 409660555 ps
T417 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3507444465 Aug 15 06:02:26 PM PDT 24 Aug 15 06:02:30 PM PDT 24 346509482 ps
T418 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3427973834 Aug 15 06:02:27 PM PDT 24 Aug 15 06:02:31 PM PDT 24 85453207 ps
T76 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1891279430 Aug 15 06:02:55 PM PDT 24 Aug 15 06:03:22 PM PDT 24 543926325 ps
T82 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2239715182 Aug 15 06:02:26 PM PDT 24 Aug 15 06:02:52 PM PDT 24 567776423 ps
T419 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2974911896 Aug 15 06:02:35 PM PDT 24 Aug 15 06:02:39 PM PDT 24 442159977 ps
T420 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.679182850 Aug 15 06:02:42 PM PDT 24 Aug 15 06:03:13 PM PDT 24 1798420817 ps
T77 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2179394500 Aug 15 06:02:41 PM PDT 24 Aug 15 06:02:45 PM PDT 24 348294026 ps
T98 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3890263982 Aug 15 06:02:55 PM PDT 24 Aug 15 06:04:05 PM PDT 24 1017096927 ps
T101 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.426862314 Aug 15 06:02:53 PM PDT 24 Aug 15 06:04:01 PM PDT 24 920495561 ps
T421 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.196794408 Aug 15 06:02:25 PM PDT 24 Aug 15 06:02:32 PM PDT 24 333212767 ps
T422 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1947523880 Aug 15 06:02:46 PM PDT 24 Aug 15 06:02:53 PM PDT 24 1034705063 ps
T423 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3171391797 Aug 15 06:02:55 PM PDT 24 Aug 15 06:03:02 PM PDT 24 332938536 ps
T424 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3366512786 Aug 15 06:02:26 PM PDT 24 Aug 15 06:02:34 PM PDT 24 181110076 ps
T425 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3999210544 Aug 15 06:02:39 PM PDT 24 Aug 15 06:02:43 PM PDT 24 89108029 ps
T426 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2828418390 Aug 15 06:02:56 PM PDT 24 Aug 15 06:03:04 PM PDT 24 1545890810 ps
T427 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3777390700 Aug 15 06:02:49 PM PDT 24 Aug 15 06:02:57 PM PDT 24 280783869 ps
T78 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2064946375 Aug 15 06:02:40 PM PDT 24 Aug 15 06:02:44 PM PDT 24 172284930 ps
T428 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2911190630 Aug 15 06:02:21 PM PDT 24 Aug 15 06:02:26 PM PDT 24 131942055 ps
T429 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.617700271 Aug 15 06:02:40 PM PDT 24 Aug 15 06:02:47 PM PDT 24 150365801 ps
T430 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3269511381 Aug 15 06:02:47 PM PDT 24 Aug 15 06:02:53 PM PDT 24 127041892 ps
T431 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3888897926 Aug 15 06:02:47 PM PDT 24 Aug 15 06:03:14 PM PDT 24 1159834503 ps
T432 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3809448120 Aug 15 06:02:33 PM PDT 24 Aug 15 06:02:38 PM PDT 24 515273182 ps
T433 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4033871824 Aug 15 06:02:39 PM PDT 24 Aug 15 06:02:43 PM PDT 24 332859191 ps
T434 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.522194354 Aug 15 06:02:45 PM PDT 24 Aug 15 06:02:49 PM PDT 24 350373629 ps
T435 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4257215234 Aug 15 06:02:46 PM PDT 24 Aug 15 06:02:57 PM PDT 24 9923042901 ps
T436 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.869028200 Aug 15 06:02:34 PM PDT 24 Aug 15 06:02:39 PM PDT 24 254422539 ps
T437 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.435370405 Aug 15 06:02:55 PM PDT 24 Aug 15 06:03:00 PM PDT 24 126879091 ps
T438 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.491980040 Aug 15 06:02:35 PM PDT 24 Aug 15 06:02:39 PM PDT 24 363005864 ps
T439 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1264201807 Aug 15 06:02:54 PM PDT 24 Aug 15 06:03:00 PM PDT 24 159216064 ps
T79 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1254988475 Aug 15 06:02:48 PM PDT 24 Aug 15 06:03:09 PM PDT 24 528392231 ps
T440 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.333743646 Aug 15 06:02:26 PM PDT 24 Aug 15 06:02:30 PM PDT 24 89626525 ps
T441 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2501735691 Aug 15 06:02:53 PM PDT 24 Aug 15 06:02:58 PM PDT 24 127188550 ps
T442 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2616737597 Aug 15 06:02:49 PM PDT 24 Aug 15 06:02:54 PM PDT 24 498963593 ps
T102 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1366160334 Aug 15 06:02:26 PM PDT 24 Aug 15 06:03:34 PM PDT 24 1709862925 ps
T443 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.151042167 Aug 15 06:02:23 PM PDT 24 Aug 15 06:02:28 PM PDT 24 245587438 ps
T99 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3924668917 Aug 15 06:02:47 PM PDT 24 Aug 15 06:03:58 PM PDT 24 622412347 ps
T444 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3311988567 Aug 15 06:02:26 PM PDT 24 Aug 15 06:02:31 PM PDT 24 539865172 ps
T445 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2160277577 Aug 15 06:02:38 PM PDT 24 Aug 15 06:02:59 PM PDT 24 2385802807 ps
T446 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3759175473 Aug 15 06:02:56 PM PDT 24 Aug 15 06:03:01 PM PDT 24 260994547 ps
T447 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2568766198 Aug 15 06:02:54 PM PDT 24 Aug 15 06:03:00 PM PDT 24 514128567 ps
T448 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2048543314 Aug 15 06:02:43 PM PDT 24 Aug 15 06:02:48 PM PDT 24 128363438 ps
T449 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1204316548 Aug 15 06:02:40 PM PDT 24 Aug 15 06:02:45 PM PDT 24 596719113 ps
T80 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.508780758 Aug 15 06:02:29 PM PDT 24 Aug 15 06:02:33 PM PDT 24 110326767 ps
T450 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2172191518 Aug 15 06:02:41 PM PDT 24 Aug 15 06:02:46 PM PDT 24 350876082 ps
T451 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4174889191 Aug 15 06:02:26 PM PDT 24 Aug 15 06:03:05 PM PDT 24 2382609516 ps
T452 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2017644695 Aug 15 06:02:47 PM PDT 24 Aug 15 06:02:51 PM PDT 24 85898012 ps
T453 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2401183239 Aug 15 06:02:40 PM PDT 24 Aug 15 06:02:45 PM PDT 24 1401836776 ps
T454 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1880031756 Aug 15 06:02:39 PM PDT 24 Aug 15 06:03:05 PM PDT 24 541886330 ps
T455 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3221185931 Aug 15 06:02:23 PM PDT 24 Aug 15 06:02:27 PM PDT 24 174704869 ps
T456 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2014528874 Aug 15 06:02:47 PM PDT 24 Aug 15 06:02:53 PM PDT 24 348236970 ps
T457 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3909451034 Aug 15 06:02:56 PM PDT 24 Aug 15 06:03:01 PM PDT 24 702694319 ps

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1875104805
Short name T2
Test name
Test status
Simulation time 4048839901 ps
CPU time 131.22 seconds
Started Aug 15 06:02:06 PM PDT 24
Finished Aug 15 06:04:17 PM PDT 24
Peak memory 222164 kb
Host smart-168ee192-b3d8-4ff6-8681-832aa909ad2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875104805 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1875104805
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4034060097
Short name T17
Test name
Test status
Simulation time 4624911330 ps
CPU time 116.91 seconds
Started Aug 15 06:01:26 PM PDT 24
Finished Aug 15 06:03:23 PM PDT 24
Peak memory 228420 kb
Host smart-cb3af184-4486-4295-9471-5dd85568e94a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034060097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.4034060097
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2621892094
Short name T8
Test name
Test status
Simulation time 1956951742 ps
CPU time 25.72 seconds
Started Aug 15 06:02:20 PM PDT 24
Finished Aug 15 06:02:46 PM PDT 24
Peak memory 219484 kb
Host smart-18de3175-d0e9-4211-843f-d93bad09d5f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621892094 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.2621892094
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4282926585
Short name T90
Test name
Test status
Simulation time 561818257 ps
CPU time 66.34 seconds
Started Aug 15 06:02:50 PM PDT 24
Finished Aug 15 06:03:57 PM PDT 24
Peak memory 219400 kb
Host smart-3ee90f37-7b75-42ac-8dcf-13d1db418e0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282926585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.4282926585
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.323959766
Short name T13
Test name
Test status
Simulation time 3331463479 ps
CPU time 126.61 seconds
Started Aug 15 06:01:12 PM PDT 24
Finished Aug 15 06:03:19 PM PDT 24
Peak memory 230444 kb
Host smart-414c6946-38be-4e98-bce7-3edce172a06a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323959766 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.323959766
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.834913262
Short name T30
Test name
Test status
Simulation time 720733798 ps
CPU time 53.31 seconds
Started Aug 15 06:01:14 PM PDT 24
Finished Aug 15 06:02:08 PM PDT 24
Peak memory 235988 kb
Host smart-2c1598d7-3637-42e8-9b0b-2405e6c7f32d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834913262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.834913262
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.350812407
Short name T62
Test name
Test status
Simulation time 377625768 ps
CPU time 17.9 seconds
Started Aug 15 06:02:18 PM PDT 24
Finished Aug 15 06:02:36 PM PDT 24
Peak memory 211388 kb
Host smart-40114140-139e-4f58-9276-f1313d70757c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350812407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.350812407
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.4164319350
Short name T53
Test name
Test status
Simulation time 3701542548 ps
CPU time 153.19 seconds
Started Aug 15 06:02:18 PM PDT 24
Finished Aug 15 06:04:51 PM PDT 24
Peak memory 229992 kb
Host smart-9041b832-5d4e-4df7-bd6b-4c7239b1717e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164319350 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.4164319350
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4167945847
Short name T55
Test name
Test status
Simulation time 392459275 ps
CPU time 68.65 seconds
Started Aug 15 06:02:39 PM PDT 24
Finished Aug 15 06:03:47 PM PDT 24
Peak memory 212968 kb
Host smart-a3ffb6fa-c4f8-410a-9cd2-07813c2e90ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167945847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.4167945847
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3396014921
Short name T50
Test name
Test status
Simulation time 9576644465 ps
CPU time 97.58 seconds
Started Aug 15 06:01:48 PM PDT 24
Finished Aug 15 06:03:26 PM PDT 24
Peak memory 212528 kb
Host smart-fb3de211-633b-41cc-a77f-d78ddb792c76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396014921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3396014921
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1171928324
Short name T35
Test name
Test status
Simulation time 333510995 ps
CPU time 4.35 seconds
Started Aug 15 06:01:10 PM PDT 24
Finished Aug 15 06:01:14 PM PDT 24
Peak memory 211136 kb
Host smart-46ad1363-17b1-4285-afa5-eab829b18ef7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171928324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1171928324
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3340020138
Short name T93
Test name
Test status
Simulation time 1349445024 ps
CPU time 69.45 seconds
Started Aug 15 06:02:37 PM PDT 24
Finished Aug 15 06:03:47 PM PDT 24
Peak memory 213084 kb
Host smart-1680061f-6e39-4e0b-af1b-2c9fdf89fca4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340020138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3340020138
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2093002491
Short name T22
Test name
Test status
Simulation time 875605774 ps
CPU time 9.11 seconds
Started Aug 15 06:01:34 PM PDT 24
Finished Aug 15 06:01:43 PM PDT 24
Peak memory 211524 kb
Host smart-324a3455-b5c6-4d3e-93e6-68e5482ffd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093002491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2093002491
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2593824197
Short name T117
Test name
Test status
Simulation time 335565461 ps
CPU time 9.08 seconds
Started Aug 15 06:01:12 PM PDT 24
Finished Aug 15 06:01:22 PM PDT 24
Peak memory 211516 kb
Host smart-723b7061-1c01-48b1-86ea-9df823722f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593824197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2593824197
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2772222262
Short name T15
Test name
Test status
Simulation time 320138470 ps
CPU time 10.46 seconds
Started Aug 15 06:01:35 PM PDT 24
Finished Aug 15 06:01:46 PM PDT 24
Peak memory 214032 kb
Host smart-947d5a16-25bd-49a1-afb7-3bd0fe6f736d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772222262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2772222262
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1062754366
Short name T364
Test name
Test status
Simulation time 518164208 ps
CPU time 9.17 seconds
Started Aug 15 06:02:19 PM PDT 24
Finished Aug 15 06:02:28 PM PDT 24
Peak memory 219628 kb
Host smart-8ce1a02d-17a9-4350-9df2-4f53125ce41b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062754366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1062754366
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4236672509
Short name T64
Test name
Test status
Simulation time 833318476 ps
CPU time 4.71 seconds
Started Aug 15 06:02:24 PM PDT 24
Finished Aug 15 06:02:29 PM PDT 24
Peak memory 218512 kb
Host smart-d213a740-7e98-4e0f-9e03-d5aa236b7ad7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236672509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.4236672509
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3221185931
Short name T455
Test name
Test status
Simulation time 174704869 ps
CPU time 4.31 seconds
Started Aug 15 06:02:23 PM PDT 24
Finished Aug 15 06:02:27 PM PDT 24
Peak memory 211436 kb
Host smart-1e209482-4a83-4d87-be71-c97f78094373
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221185931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3221185931
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2112956599
Short name T386
Test name
Test status
Simulation time 387332683 ps
CPU time 5.47 seconds
Started Aug 15 06:02:21 PM PDT 24
Finished Aug 15 06:02:27 PM PDT 24
Peak memory 219484 kb
Host smart-78cb147d-844d-4f50-b8f7-cbb9d0c41039
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112956599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2112956599
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.294844969
Short name T373
Test name
Test status
Simulation time 372741752 ps
CPU time 4.58 seconds
Started Aug 15 06:02:25 PM PDT 24
Finished Aug 15 06:02:30 PM PDT 24
Peak memory 215680 kb
Host smart-ac6f6715-3668-4b75-968b-6d803e6a4d99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294844969 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.294844969
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.151042167
Short name T443
Test name
Test status
Simulation time 245587438 ps
CPU time 4.78 seconds
Started Aug 15 06:02:23 PM PDT 24
Finished Aug 15 06:02:28 PM PDT 24
Peak memory 211428 kb
Host smart-ab39f479-4f29-45ea-9d4f-f38f2ce4e902
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151042167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.151042167
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2911190630
Short name T428
Test name
Test status
Simulation time 131942055 ps
CPU time 4.72 seconds
Started Aug 15 06:02:21 PM PDT 24
Finished Aug 15 06:02:26 PM PDT 24
Peak memory 211252 kb
Host smart-3955e6c5-674e-4e62-a45a-eb550a5603e1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911190630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2911190630
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3608255789
Short name T380
Test name
Test status
Simulation time 261260607 ps
CPU time 4.83 seconds
Started Aug 15 06:02:20 PM PDT 24
Finished Aug 15 06:02:24 PM PDT 24
Peak memory 211356 kb
Host smart-abb625ec-2d5e-4718-97d7-649c9a5b68b6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608255789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3608255789
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.379482700
Short name T86
Test name
Test status
Simulation time 778902729 ps
CPU time 4.77 seconds
Started Aug 15 06:02:22 PM PDT 24
Finished Aug 15 06:02:27 PM PDT 24
Peak memory 211396 kb
Host smart-ee8a246c-9fbf-464b-834e-f3c29ea62789
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379482700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.379482700
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2400857886
Short name T92
Test name
Test status
Simulation time 538112921 ps
CPU time 36.81 seconds
Started Aug 15 06:02:23 PM PDT 24
Finished Aug 15 06:03:00 PM PDT 24
Peak memory 211988 kb
Host smart-d5be8b32-29d6-4458-a7fa-3693442a51db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400857886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2400857886
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.333743646
Short name T440
Test name
Test status
Simulation time 89626525 ps
CPU time 4.02 seconds
Started Aug 15 06:02:26 PM PDT 24
Finished Aug 15 06:02:30 PM PDT 24
Peak memory 211372 kb
Host smart-c844f9ca-0c47-41ac-b771-4343ea2e9478
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333743646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.333743646
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3158231686
Short name T401
Test name
Test status
Simulation time 270258345 ps
CPU time 4.44 seconds
Started Aug 15 06:02:24 PM PDT 24
Finished Aug 15 06:02:29 PM PDT 24
Peak memory 218552 kb
Host smart-395b9949-ff2f-4942-83b3-f97381371c89
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158231686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3158231686
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3133387154
Short name T393
Test name
Test status
Simulation time 535962448 ps
CPU time 6.34 seconds
Started Aug 15 06:02:27 PM PDT 24
Finished Aug 15 06:02:33 PM PDT 24
Peak memory 219500 kb
Host smart-5eaef258-d7f7-4bcf-8342-3dcb88109d06
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133387154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3133387154
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1985552854
Short name T59
Test name
Test status
Simulation time 261668476 ps
CPU time 5.16 seconds
Started Aug 15 06:02:25 PM PDT 24
Finished Aug 15 06:02:30 PM PDT 24
Peak memory 219624 kb
Host smart-5d92a8ef-d595-4d05-b36f-0dadb9615f0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985552854 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1985552854
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2202210060
Short name T75
Test name
Test status
Simulation time 127644869 ps
CPU time 4.77 seconds
Started Aug 15 06:02:25 PM PDT 24
Finished Aug 15 06:02:30 PM PDT 24
Peak memory 218152 kb
Host smart-06317751-4522-4cde-815c-596aa4879fc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202210060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2202210060
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.67464770
Short name T394
Test name
Test status
Simulation time 309562071 ps
CPU time 3.87 seconds
Started Aug 15 06:02:26 PM PDT 24
Finished Aug 15 06:02:30 PM PDT 24
Peak memory 211332 kb
Host smart-2454f9f3-3709-41c4-a1fa-375a7ffe4f49
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67464770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_
mem_partial_access.67464770
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.440369796
Short name T383
Test name
Test status
Simulation time 164891292 ps
CPU time 4 seconds
Started Aug 15 06:02:27 PM PDT 24
Finished Aug 15 06:02:31 PM PDT 24
Peak memory 211312 kb
Host smart-90a068f1-f900-40aa-ab33-e261810bd6ba
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440369796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
440369796
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2149764938
Short name T371
Test name
Test status
Simulation time 813098083 ps
CPU time 17.9 seconds
Started Aug 15 06:02:29 PM PDT 24
Finished Aug 15 06:02:48 PM PDT 24
Peak memory 211432 kb
Host smart-225feea0-6908-4f04-927d-88a624aae918
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149764938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2149764938
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1815544523
Short name T406
Test name
Test status
Simulation time 94785974 ps
CPU time 4.14 seconds
Started Aug 15 06:02:25 PM PDT 24
Finished Aug 15 06:02:30 PM PDT 24
Peak memory 211432 kb
Host smart-0120d06d-9c8a-4625-a139-685de2fc6b35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815544523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1815544523
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.196794408
Short name T421
Test name
Test status
Simulation time 333212767 ps
CPU time 6.55 seconds
Started Aug 15 06:02:25 PM PDT 24
Finished Aug 15 06:02:32 PM PDT 24
Peak memory 216592 kb
Host smart-dd5de9b2-d3d9-4dca-8221-47404c016bb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196794408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.196794408
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4174889191
Short name T451
Test name
Test status
Simulation time 2382609516 ps
CPU time 38.88 seconds
Started Aug 15 06:02:26 PM PDT 24
Finished Aug 15 06:03:05 PM PDT 24
Peak memory 219856 kb
Host smart-a7d2b584-0adb-441b-bf89-f7cc9187f103
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174889191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.4174889191
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3312876782
Short name T387
Test name
Test status
Simulation time 1093463995 ps
CPU time 5.96 seconds
Started Aug 15 06:02:40 PM PDT 24
Finished Aug 15 06:02:46 PM PDT 24
Peak memory 216580 kb
Host smart-760b6889-317c-4d7d-804e-5a9d6003fbec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312876782 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3312876782
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2064946375
Short name T78
Test name
Test status
Simulation time 172284930 ps
CPU time 4.04 seconds
Started Aug 15 06:02:40 PM PDT 24
Finished Aug 15 06:02:44 PM PDT 24
Peak memory 219516 kb
Host smart-2fb77f65-e3a4-49a5-bd9d-d9989e8984c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064946375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2064946375
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.35913370
Short name T57
Test name
Test status
Simulation time 549979081 ps
CPU time 20.49 seconds
Started Aug 15 06:02:39 PM PDT 24
Finished Aug 15 06:02:59 PM PDT 24
Peak memory 211296 kb
Host smart-69a961ea-7689-4758-add4-ad2621001c5a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35913370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pas
sthru_mem_tl_intg_err.35913370
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2172191518
Short name T450
Test name
Test status
Simulation time 350876082 ps
CPU time 4.18 seconds
Started Aug 15 06:02:41 PM PDT 24
Finished Aug 15 06:02:46 PM PDT 24
Peak memory 219560 kb
Host smart-6f99a6b1-fcd3-4329-9a4c-11631b139747
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172191518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2172191518
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3514992861
Short name T396
Test name
Test status
Simulation time 518349643 ps
CPU time 11.07 seconds
Started Aug 15 06:02:41 PM PDT 24
Finished Aug 15 06:02:53 PM PDT 24
Peak memory 217728 kb
Host smart-052065dc-36cb-4255-bc81-2c6030df1278
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514992861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3514992861
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.26974936
Short name T54
Test name
Test status
Simulation time 1234811526 ps
CPU time 69.25 seconds
Started Aug 15 06:02:40 PM PDT 24
Finished Aug 15 06:03:49 PM PDT 24
Peak memory 213136 kb
Host smart-37f2f2cb-e6b1-433d-8069-c9b7465a1275
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26974936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_int
g_err.26974936
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.920658691
Short name T388
Test name
Test status
Simulation time 469032510 ps
CPU time 5.31 seconds
Started Aug 15 06:02:39 PM PDT 24
Finished Aug 15 06:02:45 PM PDT 24
Peak memory 216504 kb
Host smart-4aefacfb-43c2-493d-abf1-5dd5736184a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920658691 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.920658691
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1622903591
Short name T370
Test name
Test status
Simulation time 334432307 ps
CPU time 4.03 seconds
Started Aug 15 06:02:40 PM PDT 24
Finished Aug 15 06:02:44 PM PDT 24
Peak memory 211384 kb
Host smart-ac4d6380-1063-4f1e-97e2-3c9c0086df4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622903591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1622903591
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.679182850
Short name T420
Test name
Test status
Simulation time 1798420817 ps
CPU time 30.86 seconds
Started Aug 15 06:02:42 PM PDT 24
Finished Aug 15 06:03:13 PM PDT 24
Peak memory 211420 kb
Host smart-890eb966-7508-401d-888e-da7fff18b1ad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679182850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.679182850
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2420385292
Short name T84
Test name
Test status
Simulation time 180054013 ps
CPU time 4.86 seconds
Started Aug 15 06:02:39 PM PDT 24
Finished Aug 15 06:02:45 PM PDT 24
Peak memory 218572 kb
Host smart-fa9bb99a-ecfa-4140-a8fe-d6109b109b4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420385292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2420385292
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.375832705
Short name T403
Test name
Test status
Simulation time 520736293 ps
CPU time 8.76 seconds
Started Aug 15 06:02:42 PM PDT 24
Finished Aug 15 06:02:51 PM PDT 24
Peak memory 219660 kb
Host smart-5ad6efaa-35ac-424a-8249-ec7e3733883b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375832705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.375832705
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2288418784
Short name T362
Test name
Test status
Simulation time 575166170 ps
CPU time 4.97 seconds
Started Aug 15 06:02:45 PM PDT 24
Finished Aug 15 06:02:50 PM PDT 24
Peak memory 219652 kb
Host smart-3bf2b63f-729b-47db-84c1-a019c31027e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288418784 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2288418784
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2616737597
Short name T442
Test name
Test status
Simulation time 498963593 ps
CPU time 4.81 seconds
Started Aug 15 06:02:49 PM PDT 24
Finished Aug 15 06:02:54 PM PDT 24
Peak memory 211424 kb
Host smart-63ff82a4-c241-405d-b46d-ea232a8b1177
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616737597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2616737597
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3888897926
Short name T431
Test name
Test status
Simulation time 1159834503 ps
CPU time 26.85 seconds
Started Aug 15 06:02:47 PM PDT 24
Finished Aug 15 06:03:14 PM PDT 24
Peak memory 211456 kb
Host smart-1ee3baf2-6e5e-4eb4-bea0-3177b10df352
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888897926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3888897926
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1947523880
Short name T422
Test name
Test status
Simulation time 1034705063 ps
CPU time 6.71 seconds
Started Aug 15 06:02:46 PM PDT 24
Finished Aug 15 06:02:53 PM PDT 24
Peak memory 211424 kb
Host smart-c90330c7-f90a-4579-acb1-d23092ab3fcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947523880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1947523880
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4257215234
Short name T435
Test name
Test status
Simulation time 9923042901 ps
CPU time 11.76 seconds
Started Aug 15 06:02:46 PM PDT 24
Finished Aug 15 06:02:57 PM PDT 24
Peak memory 219764 kb
Host smart-c7b66335-4382-47d7-83e5-8c3d9b484b26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257215234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.4257215234
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3924668917
Short name T99
Test name
Test status
Simulation time 622412347 ps
CPU time 71.04 seconds
Started Aug 15 06:02:47 PM PDT 24
Finished Aug 15 06:03:58 PM PDT 24
Peak memory 219548 kb
Host smart-24e005b9-0597-4666-a8ca-3741b2c664c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924668917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3924668917
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4022091167
Short name T358
Test name
Test status
Simulation time 110250738 ps
CPU time 5.3 seconds
Started Aug 15 06:02:45 PM PDT 24
Finished Aug 15 06:02:50 PM PDT 24
Peak memory 216092 kb
Host smart-4a87a50f-6a52-49d5-ba36-26664158d7c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022091167 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.4022091167
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3968960514
Short name T85
Test name
Test status
Simulation time 308454255 ps
CPU time 3.96 seconds
Started Aug 15 06:02:50 PM PDT 24
Finished Aug 15 06:02:54 PM PDT 24
Peak memory 219492 kb
Host smart-3cfbbbf7-1567-4e26-ba1a-16c3cb015473
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968960514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3968960514
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3663048432
Short name T73
Test name
Test status
Simulation time 1559272960 ps
CPU time 17.37 seconds
Started Aug 15 06:02:48 PM PDT 24
Finished Aug 15 06:03:06 PM PDT 24
Peak memory 211436 kb
Host smart-a99312c8-a561-40ad-b0f9-9b0c81debc46
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663048432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3663048432
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1579201948
Short name T407
Test name
Test status
Simulation time 1721684732 ps
CPU time 5.85 seconds
Started Aug 15 06:02:50 PM PDT 24
Finished Aug 15 06:02:57 PM PDT 24
Peak memory 219520 kb
Host smart-3843f044-8858-4da3-8a5c-f072fb037dac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579201948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1579201948
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.489156173
Short name T391
Test name
Test status
Simulation time 416555801 ps
CPU time 6.47 seconds
Started Aug 15 06:02:48 PM PDT 24
Finished Aug 15 06:02:54 PM PDT 24
Peak memory 216508 kb
Host smart-13e4784e-4c5b-49e0-9dd2-a5c4fe3b9202
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489156173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.489156173
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3454217085
Short name T359
Test name
Test status
Simulation time 140965649 ps
CPU time 5.46 seconds
Started Aug 15 06:02:48 PM PDT 24
Finished Aug 15 06:02:54 PM PDT 24
Peak memory 219672 kb
Host smart-171326a9-a719-407b-887f-aeec6b83a473
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454217085 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3454217085
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3346034996
Short name T63
Test name
Test status
Simulation time 131284697 ps
CPU time 4.85 seconds
Started Aug 15 06:02:46 PM PDT 24
Finished Aug 15 06:02:52 PM PDT 24
Peak memory 211392 kb
Host smart-b34a73b5-9d34-4f73-b9bb-1cfd1b3f94d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346034996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3346034996
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.204551242
Short name T377
Test name
Test status
Simulation time 2643790684 ps
CPU time 21.16 seconds
Started Aug 15 06:02:50 PM PDT 24
Finished Aug 15 06:03:12 PM PDT 24
Peak memory 211284 kb
Host smart-7a4964b8-dcbc-47e6-9d71-5e570a1d8d2a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204551242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.204551242
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3032534167
Short name T400
Test name
Test status
Simulation time 543698047 ps
CPU time 4.84 seconds
Started Aug 15 06:02:47 PM PDT 24
Finished Aug 15 06:02:52 PM PDT 24
Peak memory 211392 kb
Host smart-09995bc1-3bb2-4f95-8096-e715abbea80d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032534167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3032534167
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2231573278
Short name T382
Test name
Test status
Simulation time 90130727 ps
CPU time 6.72 seconds
Started Aug 15 06:02:46 PM PDT 24
Finished Aug 15 06:02:53 PM PDT 24
Peak memory 219588 kb
Host smart-22003c35-283d-46af-af0a-53df39757edc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231573278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2231573278
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3097306527
Short name T100
Test name
Test status
Simulation time 251404573 ps
CPU time 68.85 seconds
Started Aug 15 06:02:46 PM PDT 24
Finished Aug 15 06:03:55 PM PDT 24
Peak memory 219560 kb
Host smart-bc59dddf-00fe-4a55-a89e-811c1baa67fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097306527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3097306527
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.984042573
Short name T408
Test name
Test status
Simulation time 509935958 ps
CPU time 8.23 seconds
Started Aug 15 06:02:46 PM PDT 24
Finished Aug 15 06:02:55 PM PDT 24
Peak memory 217596 kb
Host smart-24dbbceb-85e1-4330-8d1e-37533eadeaab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984042573 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.984042573
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.522194354
Short name T434
Test name
Test status
Simulation time 350373629 ps
CPU time 4.01 seconds
Started Aug 15 06:02:45 PM PDT 24
Finished Aug 15 06:02:49 PM PDT 24
Peak memory 219580 kb
Host smart-ff7f0684-996f-48e9-ba9b-774b766f5187
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522194354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.522194354
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3662775238
Short name T83
Test name
Test status
Simulation time 554230114 ps
CPU time 26.59 seconds
Started Aug 15 06:02:46 PM PDT 24
Finished Aug 15 06:03:13 PM PDT 24
Peak memory 211408 kb
Host smart-7800730b-e97c-4d6b-a0ca-5b965a3a3fc0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662775238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3662775238
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2512892671
Short name T66
Test name
Test status
Simulation time 131462408 ps
CPU time 4.89 seconds
Started Aug 15 06:02:46 PM PDT 24
Finished Aug 15 06:02:51 PM PDT 24
Peak memory 218644 kb
Host smart-7cbf927b-0cb3-4a3b-b3e9-d1502ccd2ff7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512892671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2512892671
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.383376917
Short name T356
Test name
Test status
Simulation time 250954333 ps
CPU time 7.74 seconds
Started Aug 15 06:02:45 PM PDT 24
Finished Aug 15 06:02:53 PM PDT 24
Peak memory 216564 kb
Host smart-dadd3b40-f1ba-494c-9b5c-f09a2d71a50f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383376917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.383376917
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1047157293
Short name T95
Test name
Test status
Simulation time 330067792 ps
CPU time 36.84 seconds
Started Aug 15 06:02:48 PM PDT 24
Finished Aug 15 06:03:25 PM PDT 24
Peak memory 212004 kb
Host smart-d7528c1e-4e34-4d48-91d5-20b4d6177d21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047157293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1047157293
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3269511381
Short name T430
Test name
Test status
Simulation time 127041892 ps
CPU time 5.23 seconds
Started Aug 15 06:02:47 PM PDT 24
Finished Aug 15 06:02:53 PM PDT 24
Peak memory 219640 kb
Host smart-4aaebe39-5477-47b2-a27b-e85baacacfa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269511381 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3269511381
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2017644695
Short name T452
Test name
Test status
Simulation time 85898012 ps
CPU time 4.28 seconds
Started Aug 15 06:02:47 PM PDT 24
Finished Aug 15 06:02:51 PM PDT 24
Peak memory 211416 kb
Host smart-14ddd384-0422-487c-8e3a-e46231216330
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017644695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2017644695
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1254988475
Short name T79
Test name
Test status
Simulation time 528392231 ps
CPU time 20.25 seconds
Started Aug 15 06:02:48 PM PDT 24
Finished Aug 15 06:03:09 PM PDT 24
Peak memory 211396 kb
Host smart-4e8c4c63-c108-416f-be36-502e23c0e4bc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254988475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1254988475
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2014528874
Short name T456
Test name
Test status
Simulation time 348236970 ps
CPU time 5.02 seconds
Started Aug 15 06:02:47 PM PDT 24
Finished Aug 15 06:02:53 PM PDT 24
Peak memory 218972 kb
Host smart-3ddf9e4a-d0a7-4c2e-acb0-545cf9a193c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014528874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2014528874
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3777390700
Short name T427
Test name
Test status
Simulation time 280783869 ps
CPU time 8.65 seconds
Started Aug 15 06:02:49 PM PDT 24
Finished Aug 15 06:02:57 PM PDT 24
Peak memory 216496 kb
Host smart-5a71d5bf-0782-4ee7-9213-8f3e11190ead
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777390700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3777390700
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.306272178
Short name T94
Test name
Test status
Simulation time 521892160 ps
CPU time 37.28 seconds
Started Aug 15 06:02:45 PM PDT 24
Finished Aug 15 06:03:22 PM PDT 24
Peak memory 211996 kb
Host smart-65ba6bfb-68f9-4ade-9c4f-4c8ead0d0ef6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306272178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.306272178
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4156109998
Short name T409
Test name
Test status
Simulation time 182486380 ps
CPU time 4.86 seconds
Started Aug 15 06:02:54 PM PDT 24
Finished Aug 15 06:02:59 PM PDT 24
Peak memory 216096 kb
Host smart-3bb05e7c-08f5-476d-adf5-f5aa74454986
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156109998 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.4156109998
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2568766198
Short name T447
Test name
Test status
Simulation time 514128567 ps
CPU time 4.9 seconds
Started Aug 15 06:02:54 PM PDT 24
Finished Aug 15 06:03:00 PM PDT 24
Peak memory 211424 kb
Host smart-19cd6312-7e09-4b3c-b5e7-dae19ca3ed8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568766198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2568766198
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1891279430
Short name T76
Test name
Test status
Simulation time 543926325 ps
CPU time 26.64 seconds
Started Aug 15 06:02:55 PM PDT 24
Finished Aug 15 06:03:22 PM PDT 24
Peak memory 211400 kb
Host smart-7d8c8f07-a05d-4dba-a2c3-101e986629c7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891279430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1891279430
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3279260369
Short name T404
Test name
Test status
Simulation time 85856455 ps
CPU time 4.13 seconds
Started Aug 15 06:02:55 PM PDT 24
Finished Aug 15 06:03:00 PM PDT 24
Peak memory 218516 kb
Host smart-05d667b3-8bfd-4c64-a41c-b43dc2dfe693
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279260369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3279260369
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2828418390
Short name T426
Test name
Test status
Simulation time 1545890810 ps
CPU time 8.05 seconds
Started Aug 15 06:02:56 PM PDT 24
Finished Aug 15 06:03:04 PM PDT 24
Peak memory 219676 kb
Host smart-40227f3d-4374-4613-b5d3-e653626df26a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828418390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2828418390
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3603126734
Short name T97
Test name
Test status
Simulation time 289390108 ps
CPU time 70.09 seconds
Started Aug 15 06:02:54 PM PDT 24
Finished Aug 15 06:04:04 PM PDT 24
Peak memory 213152 kb
Host smart-a4926276-c65d-40d4-8f2f-55ec7b7f9257
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603126734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3603126734
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1264201807
Short name T439
Test name
Test status
Simulation time 159216064 ps
CPU time 5.83 seconds
Started Aug 15 06:02:54 PM PDT 24
Finished Aug 15 06:03:00 PM PDT 24
Peak memory 214960 kb
Host smart-3ff7eb25-269a-4f4d-b7bb-ee6760419b43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264201807 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1264201807
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2501735691
Short name T441
Test name
Test status
Simulation time 127188550 ps
CPU time 4.92 seconds
Started Aug 15 06:02:53 PM PDT 24
Finished Aug 15 06:02:58 PM PDT 24
Peak memory 218708 kb
Host smart-26dd21df-7075-41dd-afc5-288ec5ef160d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501735691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2501735691
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2752399532
Short name T385
Test name
Test status
Simulation time 1643282228 ps
CPU time 31.6 seconds
Started Aug 15 06:02:54 PM PDT 24
Finished Aug 15 06:03:26 PM PDT 24
Peak memory 211356 kb
Host smart-b139144f-ff39-4059-be99-1bcb3417f036
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752399532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2752399532
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3860671089
Short name T67
Test name
Test status
Simulation time 93703263 ps
CPU time 5.72 seconds
Started Aug 15 06:02:53 PM PDT 24
Finished Aug 15 06:02:59 PM PDT 24
Peak memory 211792 kb
Host smart-86d17fa8-d129-4835-81c7-42df37888de2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860671089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3860671089
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3171391797
Short name T423
Test name
Test status
Simulation time 332938536 ps
CPU time 6.58 seconds
Started Aug 15 06:02:55 PM PDT 24
Finished Aug 15 06:03:02 PM PDT 24
Peak memory 216392 kb
Host smart-16fe4323-c03c-4c38-98ad-136b1ea0d2e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171391797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3171391797
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3890263982
Short name T98
Test name
Test status
Simulation time 1017096927 ps
CPU time 69.9 seconds
Started Aug 15 06:02:55 PM PDT 24
Finished Aug 15 06:04:05 PM PDT 24
Peak memory 213208 kb
Host smart-9432976c-4e57-4636-9ce9-7fe37c19d2f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890263982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3890263982
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3909451034
Short name T457
Test name
Test status
Simulation time 702694319 ps
CPU time 5.56 seconds
Started Aug 15 06:02:56 PM PDT 24
Finished Aug 15 06:03:01 PM PDT 24
Peak memory 219656 kb
Host smart-d11f8b82-3067-489e-8a74-e42c478f2efe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909451034 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3909451034
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.435370405
Short name T437
Test name
Test status
Simulation time 126879091 ps
CPU time 4.88 seconds
Started Aug 15 06:02:55 PM PDT 24
Finished Aug 15 06:03:00 PM PDT 24
Peak memory 219496 kb
Host smart-8e99eaec-7add-45fb-a992-821e6518b48d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435370405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.435370405
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3030874512
Short name T390
Test name
Test status
Simulation time 553925617 ps
CPU time 26.13 seconds
Started Aug 15 06:02:53 PM PDT 24
Finished Aug 15 06:03:20 PM PDT 24
Peak memory 219532 kb
Host smart-7e02b322-851d-4bcd-b7e6-360f6c5a46ed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030874512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3030874512
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3759175473
Short name T446
Test name
Test status
Simulation time 260994547 ps
CPU time 5 seconds
Started Aug 15 06:02:56 PM PDT 24
Finished Aug 15 06:03:01 PM PDT 24
Peak memory 218940 kb
Host smart-6eace03b-ad2a-492d-bcd4-b97042e1502f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759175473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3759175473
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3346095702
Short name T369
Test name
Test status
Simulation time 175719701 ps
CPU time 8.19 seconds
Started Aug 15 06:02:55 PM PDT 24
Finished Aug 15 06:03:04 PM PDT 24
Peak memory 216772 kb
Host smart-32200f82-ba8f-48e9-a5ba-dda5628fba80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346095702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3346095702
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.426862314
Short name T101
Test name
Test status
Simulation time 920495561 ps
CPU time 67.93 seconds
Started Aug 15 06:02:53 PM PDT 24
Finished Aug 15 06:04:01 PM PDT 24
Peak memory 219568 kb
Host smart-ac541b2c-8b84-4ef8-9e03-5be4a990e875
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426862314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.426862314
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.508780758
Short name T80
Test name
Test status
Simulation time 110326767 ps
CPU time 4.19 seconds
Started Aug 15 06:02:29 PM PDT 24
Finished Aug 15 06:02:33 PM PDT 24
Peak memory 211396 kb
Host smart-00ed4702-4839-4ada-b35b-507306174ff5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508780758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.508780758
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3507444465
Short name T417
Test name
Test status
Simulation time 346509482 ps
CPU time 4.25 seconds
Started Aug 15 06:02:26 PM PDT 24
Finished Aug 15 06:02:30 PM PDT 24
Peak memory 211424 kb
Host smart-2fb0e78d-e1c6-4e98-8ea4-979ea27e96c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507444465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3507444465
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3366512786
Short name T424
Test name
Test status
Simulation time 181110076 ps
CPU time 7.93 seconds
Started Aug 15 06:02:26 PM PDT 24
Finished Aug 15 06:02:34 PM PDT 24
Peak memory 219272 kb
Host smart-b4e01e1f-c4d3-4581-9735-f30a560008e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366512786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3366512786
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1921509076
Short name T392
Test name
Test status
Simulation time 144224975 ps
CPU time 5.42 seconds
Started Aug 15 06:02:26 PM PDT 24
Finished Aug 15 06:02:32 PM PDT 24
Peak memory 214160 kb
Host smart-2dbeb257-e4e7-4793-9aa0-47ed9808dfd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921509076 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1921509076
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3718843376
Short name T399
Test name
Test status
Simulation time 138822925 ps
CPU time 4.71 seconds
Started Aug 15 06:02:26 PM PDT 24
Finished Aug 15 06:02:31 PM PDT 24
Peak memory 217996 kb
Host smart-7d5014df-f4ae-48eb-87d3-a95a72ee57bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718843376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3718843376
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3427973834
Short name T418
Test name
Test status
Simulation time 85453207 ps
CPU time 3.91 seconds
Started Aug 15 06:02:27 PM PDT 24
Finished Aug 15 06:02:31 PM PDT 24
Peak memory 211292 kb
Host smart-2565dffd-0c54-44cf-857e-8b48c1ce5e4c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427973834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3427973834
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2483764721
Short name T360
Test name
Test status
Simulation time 518563393 ps
CPU time 4.87 seconds
Started Aug 15 06:02:27 PM PDT 24
Finished Aug 15 06:02:32 PM PDT 24
Peak memory 211328 kb
Host smart-133d3440-be73-4e0b-9cde-39687addc804
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483764721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2483764721
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3034962129
Short name T69
Test name
Test status
Simulation time 1520749233 ps
CPU time 31.41 seconds
Started Aug 15 06:02:27 PM PDT 24
Finished Aug 15 06:02:58 PM PDT 24
Peak memory 211388 kb
Host smart-099bb95c-619b-4415-9420-f9ac0e894bf3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034962129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3034962129
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3248638409
Short name T414
Test name
Test status
Simulation time 497283024 ps
CPU time 4.94 seconds
Started Aug 15 06:02:24 PM PDT 24
Finished Aug 15 06:02:29 PM PDT 24
Peak memory 219012 kb
Host smart-4c990120-9ac5-4ca1-9181-99d6225f101c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248638409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3248638409
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.282438427
Short name T363
Test name
Test status
Simulation time 130171898 ps
CPU time 7.18 seconds
Started Aug 15 06:02:25 PM PDT 24
Finished Aug 15 06:02:32 PM PDT 24
Peak memory 215372 kb
Host smart-b689406b-d78b-40f7-a73f-79b160abf372
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282438427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.282438427
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3769108593
Short name T56
Test name
Test status
Simulation time 644748160 ps
CPU time 37.03 seconds
Started Aug 15 06:02:25 PM PDT 24
Finished Aug 15 06:03:02 PM PDT 24
Peak memory 219584 kb
Host smart-5a253e97-c407-46f4-b2d5-1669375d8561
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769108593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3769108593
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.166740747
Short name T378
Test name
Test status
Simulation time 552449568 ps
CPU time 4.06 seconds
Started Aug 15 06:02:36 PM PDT 24
Finished Aug 15 06:02:40 PM PDT 24
Peak memory 211428 kb
Host smart-9eeb0225-85ad-4cf1-8c3e-2858602943f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166740747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.166740747
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1578219692
Short name T410
Test name
Test status
Simulation time 132371171 ps
CPU time 5.18 seconds
Started Aug 15 06:02:34 PM PDT 24
Finished Aug 15 06:02:39 PM PDT 24
Peak memory 211396 kb
Host smart-12c7471a-ae92-4145-a8be-6c453af1f746
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578219692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1578219692
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1363796386
Short name T395
Test name
Test status
Simulation time 130030382 ps
CPU time 6.32 seconds
Started Aug 15 06:02:27 PM PDT 24
Finished Aug 15 06:02:33 PM PDT 24
Peak memory 219092 kb
Host smart-fba00e5a-7502-4671-89f3-82c6a46b108b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363796386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1363796386
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3253787659
Short name T374
Test name
Test status
Simulation time 199769123 ps
CPU time 5.39 seconds
Started Aug 15 06:02:39 PM PDT 24
Finished Aug 15 06:02:44 PM PDT 24
Peak memory 219584 kb
Host smart-ed82d1f1-bb2b-46a6-b2ee-e4896483f616
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253787659 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3253787659
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3311988567
Short name T444
Test name
Test status
Simulation time 539865172 ps
CPU time 4.77 seconds
Started Aug 15 06:02:26 PM PDT 24
Finished Aug 15 06:02:31 PM PDT 24
Peak memory 211348 kb
Host smart-2ec9ef4a-1b85-42f3-a526-00a26bf17d4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311988567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3311988567
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1679613590
Short name T367
Test name
Test status
Simulation time 130957083 ps
CPU time 4.79 seconds
Started Aug 15 06:02:29 PM PDT 24
Finished Aug 15 06:02:34 PM PDT 24
Peak memory 211356 kb
Host smart-4b6921c0-1967-4619-b455-8bdf3c211803
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679613590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1679613590
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3577678383
Short name T357
Test name
Test status
Simulation time 1383922474 ps
CPU time 4.83 seconds
Started Aug 15 06:02:23 PM PDT 24
Finished Aug 15 06:02:28 PM PDT 24
Peak memory 211308 kb
Host smart-585bb3a0-428e-4223-96d5-2024f61f9904
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577678383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3577678383
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2239715182
Short name T82
Test name
Test status
Simulation time 567776423 ps
CPU time 25.8 seconds
Started Aug 15 06:02:26 PM PDT 24
Finished Aug 15 06:02:52 PM PDT 24
Peak memory 211376 kb
Host smart-767e5e7c-022a-43ef-b625-39fdff029263
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239715182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2239715182
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.869028200
Short name T436
Test name
Test status
Simulation time 254422539 ps
CPU time 4.8 seconds
Started Aug 15 06:02:34 PM PDT 24
Finished Aug 15 06:02:39 PM PDT 24
Peak memory 218600 kb
Host smart-787a57ec-1928-4886-85c8-57f16093683f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869028200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.869028200
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2826291653
Short name T384
Test name
Test status
Simulation time 998753492 ps
CPU time 10.41 seconds
Started Aug 15 06:02:25 PM PDT 24
Finished Aug 15 06:02:36 PM PDT 24
Peak memory 216692 kb
Host smart-d3fe40c1-476e-48fc-b782-b6b6ce40cca2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826291653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2826291653
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1366160334
Short name T102
Test name
Test status
Simulation time 1709862925 ps
CPU time 67.52 seconds
Started Aug 15 06:02:26 PM PDT 24
Finished Aug 15 06:03:34 PM PDT 24
Peak memory 219580 kb
Host smart-56b3ec0a-e359-427b-822f-bd7ff045aabd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366160334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1366160334
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1268956326
Short name T72
Test name
Test status
Simulation time 88337897 ps
CPU time 4.01 seconds
Started Aug 15 06:02:33 PM PDT 24
Finished Aug 15 06:02:37 PM PDT 24
Peak memory 211336 kb
Host smart-fd54b480-be2e-4b24-b60b-79a5a28f5820
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268956326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1268956326
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.491980040
Short name T438
Test name
Test status
Simulation time 363005864 ps
CPU time 4.35 seconds
Started Aug 15 06:02:35 PM PDT 24
Finished Aug 15 06:02:39 PM PDT 24
Peak memory 219736 kb
Host smart-ed681793-871e-4e94-ae6e-ea767be5ec31
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491980040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.491980040
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4185116685
Short name T402
Test name
Test status
Simulation time 355560239 ps
CPU time 5.48 seconds
Started Aug 15 06:02:35 PM PDT 24
Finished Aug 15 06:02:41 PM PDT 24
Peak memory 211444 kb
Host smart-6574234d-1625-49b3-b342-8881e90bc8a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185116685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4185116685
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2974911896
Short name T419
Test name
Test status
Simulation time 442159977 ps
CPU time 4.59 seconds
Started Aug 15 06:02:35 PM PDT 24
Finished Aug 15 06:02:39 PM PDT 24
Peak memory 219660 kb
Host smart-be93e78e-58da-4379-b408-fa5f8bafd654
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974911896 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2974911896
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3029037929
Short name T74
Test name
Test status
Simulation time 129869854 ps
CPU time 4.87 seconds
Started Aug 15 06:02:32 PM PDT 24
Finished Aug 15 06:02:37 PM PDT 24
Peak memory 211432 kb
Host smart-7ba8b314-516a-46b3-a3fd-726246e5cbe4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029037929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3029037929
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1542945707
Short name T413
Test name
Test status
Simulation time 256221043 ps
CPU time 4.86 seconds
Started Aug 15 06:02:33 PM PDT 24
Finished Aug 15 06:02:38 PM PDT 24
Peak memory 211324 kb
Host smart-d2843b66-74b9-4107-8c65-d857454b1603
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542945707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1542945707
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.514849162
Short name T368
Test name
Test status
Simulation time 87355140 ps
CPU time 3.93 seconds
Started Aug 15 06:02:32 PM PDT 24
Finished Aug 15 06:02:36 PM PDT 24
Peak memory 211184 kb
Host smart-ded44fea-c6ea-4047-ba08-9d0ef298a98f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514849162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
514849162
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3881470683
Short name T81
Test name
Test status
Simulation time 3263365074 ps
CPU time 31.27 seconds
Started Aug 15 06:02:35 PM PDT 24
Finished Aug 15 06:03:06 PM PDT 24
Peak memory 211548 kb
Host smart-7bad619f-506f-4f6c-8570-41746178b198
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881470683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3881470683
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3809448120
Short name T432
Test name
Test status
Simulation time 515273182 ps
CPU time 4.77 seconds
Started Aug 15 06:02:33 PM PDT 24
Finished Aug 15 06:02:38 PM PDT 24
Peak memory 211404 kb
Host smart-4567a393-e1f7-4e3a-b98d-a0ce2bd5623a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809448120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3809448120
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.675500336
Short name T381
Test name
Test status
Simulation time 334706854 ps
CPU time 6.99 seconds
Started Aug 15 06:02:37 PM PDT 24
Finished Aug 15 06:02:44 PM PDT 24
Peak memory 216324 kb
Host smart-ffdd111e-dfbb-462b-9dce-5795bba99ad5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675500336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.675500336
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2010556598
Short name T397
Test name
Test status
Simulation time 648697906 ps
CPU time 5.03 seconds
Started Aug 15 06:02:41 PM PDT 24
Finished Aug 15 06:02:47 PM PDT 24
Peak memory 219648 kb
Host smart-f54ac4f0-d133-4ba1-97a3-f76114654852
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010556598 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2010556598
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.458883812
Short name T389
Test name
Test status
Simulation time 350017165 ps
CPU time 3.94 seconds
Started Aug 15 06:02:37 PM PDT 24
Finished Aug 15 06:02:41 PM PDT 24
Peak memory 211348 kb
Host smart-f5b2d053-44a9-4f23-817e-0b0c0bf1c9b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458883812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.458883812
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1836236902
Short name T68
Test name
Test status
Simulation time 1634014857 ps
CPU time 31.41 seconds
Started Aug 15 06:02:33 PM PDT 24
Finished Aug 15 06:03:04 PM PDT 24
Peak memory 211372 kb
Host smart-09928b86-2b8e-4f11-bd73-8de14f4919a1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836236902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1836236902
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1601759192
Short name T398
Test name
Test status
Simulation time 251710040 ps
CPU time 4.95 seconds
Started Aug 15 06:02:33 PM PDT 24
Finished Aug 15 06:02:38 PM PDT 24
Peak memory 219104 kb
Host smart-0651a28d-87ea-4b8a-ba9c-8377436b8995
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601759192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1601759192
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.448633148
Short name T376
Test name
Test status
Simulation time 656018211 ps
CPU time 10.36 seconds
Started Aug 15 06:02:34 PM PDT 24
Finished Aug 15 06:02:45 PM PDT 24
Peak memory 219680 kb
Host smart-1e83380d-3d93-4eec-8a7d-249e6781bc03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448633148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.448633148
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2670420140
Short name T96
Test name
Test status
Simulation time 409660555 ps
CPU time 72.14 seconds
Started Aug 15 06:02:32 PM PDT 24
Finished Aug 15 06:03:44 PM PDT 24
Peak memory 213112 kb
Host smart-5c3cb5b0-b734-4317-9a53-024a170ade47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670420140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2670420140
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2401183239
Short name T453
Test name
Test status
Simulation time 1401836776 ps
CPU time 4.86 seconds
Started Aug 15 06:02:40 PM PDT 24
Finished Aug 15 06:02:45 PM PDT 24
Peak memory 219540 kb
Host smart-e8b48a60-70fb-4ee3-a65c-f65153c0a00a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401183239 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2401183239
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1992928601
Short name T65
Test name
Test status
Simulation time 244768582 ps
CPU time 4.72 seconds
Started Aug 15 06:02:39 PM PDT 24
Finished Aug 15 06:02:44 PM PDT 24
Peak memory 218312 kb
Host smart-027354fa-59c7-49f9-a6eb-c841c92234d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992928601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1992928601
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2160277577
Short name T445
Test name
Test status
Simulation time 2385802807 ps
CPU time 20.73 seconds
Started Aug 15 06:02:38 PM PDT 24
Finished Aug 15 06:02:59 PM PDT 24
Peak memory 211484 kb
Host smart-4c833b82-a00d-4869-b3e2-5dc47ea4f6a2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160277577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2160277577
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3786694191
Short name T416
Test name
Test status
Simulation time 496406368 ps
CPU time 4.9 seconds
Started Aug 15 06:02:39 PM PDT 24
Finished Aug 15 06:02:44 PM PDT 24
Peak memory 211408 kb
Host smart-c46c9e44-a656-4d35-820b-0f33ec1e1864
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786694191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3786694191
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1681316255
Short name T379
Test name
Test status
Simulation time 131954191 ps
CPU time 7.11 seconds
Started Aug 15 06:02:38 PM PDT 24
Finished Aug 15 06:02:46 PM PDT 24
Peak memory 216176 kb
Host smart-7fa630c9-e36d-44ff-9246-2f56820101be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681316255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1681316255
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1840116216
Short name T412
Test name
Test status
Simulation time 354541076 ps
CPU time 71.06 seconds
Started Aug 15 06:02:40 PM PDT 24
Finished Aug 15 06:03:51 PM PDT 24
Peak memory 213036 kb
Host smart-26fcc08a-3c91-4977-b575-07a7abbc1138
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840116216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1840116216
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.812569670
Short name T366
Test name
Test status
Simulation time 512472785 ps
CPU time 5.83 seconds
Started Aug 15 06:02:42 PM PDT 24
Finished Aug 15 06:02:48 PM PDT 24
Peak memory 219644 kb
Host smart-dd9349d4-4e4d-40d6-876a-87828353fadb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812569670 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.812569670
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2179394500
Short name T77
Test name
Test status
Simulation time 348294026 ps
CPU time 4.04 seconds
Started Aug 15 06:02:41 PM PDT 24
Finished Aug 15 06:02:45 PM PDT 24
Peak memory 211428 kb
Host smart-0a805941-3716-4df3-839b-ae538bb69e70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179394500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2179394500
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1880031756
Short name T454
Test name
Test status
Simulation time 541886330 ps
CPU time 25.94 seconds
Started Aug 15 06:02:39 PM PDT 24
Finished Aug 15 06:03:05 PM PDT 24
Peak memory 211408 kb
Host smart-34083ed3-fa06-45df-aa12-17a01cf33678
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880031756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1880031756
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3999210544
Short name T425
Test name
Test status
Simulation time 89108029 ps
CPU time 4.38 seconds
Started Aug 15 06:02:39 PM PDT 24
Finished Aug 15 06:02:43 PM PDT 24
Peak memory 211424 kb
Host smart-2ac17a7c-8327-4ead-8779-8855895cd097
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999210544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3999210544
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3096778617
Short name T365
Test name
Test status
Simulation time 126558446 ps
CPU time 7.06 seconds
Started Aug 15 06:02:39 PM PDT 24
Finished Aug 15 06:02:46 PM PDT 24
Peak memory 215232 kb
Host smart-260c50ee-0334-4dcb-a82e-6aaecab3501d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096778617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3096778617
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1744211393
Short name T405
Test name
Test status
Simulation time 1090817582 ps
CPU time 36.16 seconds
Started Aug 15 06:02:43 PM PDT 24
Finished Aug 15 06:03:19 PM PDT 24
Peak memory 219544 kb
Host smart-78d347c5-de62-49b3-8f6b-b519b95f98c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744211393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1744211393
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1204316548
Short name T449
Test name
Test status
Simulation time 596719113 ps
CPU time 5.62 seconds
Started Aug 15 06:02:40 PM PDT 24
Finished Aug 15 06:02:45 PM PDT 24
Peak memory 219692 kb
Host smart-c260c822-352a-4c95-ab7d-fb21dd91bce5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204316548 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1204316548
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2048543314
Short name T448
Test name
Test status
Simulation time 128363438 ps
CPU time 4.84 seconds
Started Aug 15 06:02:43 PM PDT 24
Finished Aug 15 06:02:48 PM PDT 24
Peak memory 211400 kb
Host smart-a4b57b58-3c0e-410f-801e-f574b118ded7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048543314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2048543314
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3261940869
Short name T61
Test name
Test status
Simulation time 540430767 ps
CPU time 25.96 seconds
Started Aug 15 06:02:39 PM PDT 24
Finished Aug 15 06:03:05 PM PDT 24
Peak memory 211424 kb
Host smart-1fc282d7-8da7-48a1-8514-8e3623b8cc15
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261940869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3261940869
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.617700271
Short name T429
Test name
Test status
Simulation time 150365801 ps
CPU time 6.53 seconds
Started Aug 15 06:02:40 PM PDT 24
Finished Aug 15 06:02:47 PM PDT 24
Peak memory 211488 kb
Host smart-a880aed9-fcf2-4523-821a-56a44f49c80b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617700271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.617700271
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2516138681
Short name T415
Test name
Test status
Simulation time 131809984 ps
CPU time 6.93 seconds
Started Aug 15 06:02:42 PM PDT 24
Finished Aug 15 06:02:49 PM PDT 24
Peak memory 216108 kb
Host smart-55db6ce6-5efb-4714-8ab3-9bc8bba447fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516138681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2516138681
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3062677802
Short name T411
Test name
Test status
Simulation time 3041848016 ps
CPU time 68.63 seconds
Started Aug 15 06:02:39 PM PDT 24
Finished Aug 15 06:03:48 PM PDT 24
Peak memory 219672 kb
Host smart-71005489-350f-40a4-bd5e-f1146b8337ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062677802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3062677802
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1211508758
Short name T375
Test name
Test status
Simulation time 392507790 ps
CPU time 4.69 seconds
Started Aug 15 06:02:41 PM PDT 24
Finished Aug 15 06:02:46 PM PDT 24
Peak memory 219664 kb
Host smart-99c16ef8-74f4-41ed-bd90-202c11328c7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211508758 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1211508758
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2154217380
Short name T58
Test name
Test status
Simulation time 517110658 ps
CPU time 4.76 seconds
Started Aug 15 06:02:45 PM PDT 24
Finished Aug 15 06:02:49 PM PDT 24
Peak memory 211400 kb
Host smart-0929a8e7-deef-4e0b-96c4-c2c8711ae861
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154217380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2154217380
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1270298127
Short name T372
Test name
Test status
Simulation time 368198634 ps
CPU time 17.93 seconds
Started Aug 15 06:02:40 PM PDT 24
Finished Aug 15 06:02:58 PM PDT 24
Peak memory 211432 kb
Host smart-d8954d68-fbd5-4f82-9127-5864de6678ae
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270298127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1270298127
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4033871824
Short name T433
Test name
Test status
Simulation time 332859191 ps
CPU time 3.97 seconds
Started Aug 15 06:02:39 PM PDT 24
Finished Aug 15 06:02:43 PM PDT 24
Peak memory 211436 kb
Host smart-aef9f148-5c36-44a9-8849-52e2be18070c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033871824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.4033871824
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4088727714
Short name T361
Test name
Test status
Simulation time 90084250 ps
CPU time 7.73 seconds
Started Aug 15 06:02:38 PM PDT 24
Finished Aug 15 06:02:46 PM PDT 24
Peak memory 216668 kb
Host smart-8b7ba35a-af0c-41af-a38f-e7d29e89eeb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088727714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.4088727714
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3569729137
Short name T91
Test name
Test status
Simulation time 380640547 ps
CPU time 36.89 seconds
Started Aug 15 06:02:38 PM PDT 24
Finished Aug 15 06:03:15 PM PDT 24
Peak memory 213768 kb
Host smart-c8910ed7-1a81-478d-9030-4a9c1674bcd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569729137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3569729137
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3129291896
Short name T290
Test name
Test status
Simulation time 4625914101 ps
CPU time 103.54 seconds
Started Aug 15 06:01:04 PM PDT 24
Finished Aug 15 06:02:48 PM PDT 24
Peak memory 212508 kb
Host smart-7fafa408-54de-4501-9756-74a5e0b36bf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129291896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3129291896
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.946006955
Short name T254
Test name
Test status
Simulation time 952007113 ps
CPU time 5.89 seconds
Started Aug 15 06:01:13 PM PDT 24
Finished Aug 15 06:01:19 PM PDT 24
Peak memory 211160 kb
Host smart-462b9771-45d5-4235-acf0-00e274bcfcd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=946006955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.946006955
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.274274860
Short name T221
Test name
Test status
Simulation time 143827478 ps
CPU time 6.39 seconds
Started Aug 15 06:01:04 PM PDT 24
Finished Aug 15 06:01:11 PM PDT 24
Peak memory 211544 kb
Host smart-c7a0384f-1944-462f-8f53-2b8b40d53db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274274860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.274274860
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3511532689
Short name T344
Test name
Test status
Simulation time 617987831 ps
CPU time 13.61 seconds
Started Aug 15 06:01:04 PM PDT 24
Finished Aug 15 06:01:17 PM PDT 24
Peak memory 213636 kb
Host smart-2c26517a-14c9-4bb0-9ece-50062f443a34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511532689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3511532689
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.368300046
Short name T250
Test name
Test status
Simulation time 132147349 ps
CPU time 4.78 seconds
Started Aug 15 06:01:14 PM PDT 24
Finished Aug 15 06:01:19 PM PDT 24
Peak memory 211104 kb
Host smart-0aa92c56-ad7c-4fe4-93fa-74248e265d3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368300046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.368300046
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.240405583
Short name T150
Test name
Test status
Simulation time 3281533346 ps
CPU time 135.42 seconds
Started Aug 15 06:01:13 PM PDT 24
Finished Aug 15 06:03:29 PM PDT 24
Peak memory 232992 kb
Host smart-cc014dd0-2ae3-4508-af19-99a27bf210bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240405583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.240405583
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1671071984
Short name T265
Test name
Test status
Simulation time 726465546 ps
CPU time 9.06 seconds
Started Aug 15 06:01:13 PM PDT 24
Finished Aug 15 06:01:22 PM PDT 24
Peak memory 211492 kb
Host smart-909305a8-5884-465d-946e-1e6674d0894a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671071984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1671071984
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2787349503
Short name T138
Test name
Test status
Simulation time 393282322 ps
CPU time 5.47 seconds
Started Aug 15 06:01:12 PM PDT 24
Finished Aug 15 06:01:18 PM PDT 24
Peak memory 211088 kb
Host smart-b217561e-5414-423a-827e-095f03ef2da6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2787349503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2787349503
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2943491645
Short name T32
Test name
Test status
Simulation time 850861048 ps
CPU time 104.83 seconds
Started Aug 15 06:01:15 PM PDT 24
Finished Aug 15 06:03:00 PM PDT 24
Peak memory 236696 kb
Host smart-f636b8c9-e70a-42c7-ae76-82a8c472133c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943491645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2943491645
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1231507381
Short name T202
Test name
Test status
Simulation time 1920151705 ps
CPU time 7.81 seconds
Started Aug 15 06:01:14 PM PDT 24
Finished Aug 15 06:01:22 PM PDT 24
Peak memory 211940 kb
Host smart-68d14e9e-58b9-4dea-a8bc-6d2b76468863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231507381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1231507381
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3616437166
Short name T183
Test name
Test status
Simulation time 203710046 ps
CPU time 6.64 seconds
Started Aug 15 06:01:12 PM PDT 24
Finished Aug 15 06:01:19 PM PDT 24
Peak memory 210996 kb
Host smart-d4508c46-fcf4-473f-b7d7-e5a5f21678d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616437166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3616437166
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.817688668
Short name T127
Test name
Test status
Simulation time 4799526665 ps
CPU time 146.2 seconds
Started Aug 15 06:01:14 PM PDT 24
Finished Aug 15 06:03:40 PM PDT 24
Peak memory 220828 kb
Host smart-024600b3-1e92-44b7-965a-f5b9e34df38a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817688668 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.817688668
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2372373833
Short name T333
Test name
Test status
Simulation time 251258594 ps
CPU time 4.95 seconds
Started Aug 15 06:01:28 PM PDT 24
Finished Aug 15 06:01:33 PM PDT 24
Peak memory 211136 kb
Host smart-49bd0557-60cc-4c2a-9fbd-b1e7cdc6aada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372373833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2372373833
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.288830772
Short name T161
Test name
Test status
Simulation time 1930879602 ps
CPU time 103.21 seconds
Started Aug 15 06:01:34 PM PDT 24
Finished Aug 15 06:03:17 PM PDT 24
Peak memory 237100 kb
Host smart-0020e39e-bf04-41a8-b5bf-b71f399c1e65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288830772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.288830772
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1743860592
Short name T252
Test name
Test status
Simulation time 995817947 ps
CPU time 10.62 seconds
Started Aug 15 06:01:26 PM PDT 24
Finished Aug 15 06:01:37 PM PDT 24
Peak memory 211096 kb
Host smart-13533207-b7bb-4a54-a2e8-3083d3998024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743860592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1743860592
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.358053020
Short name T295
Test name
Test status
Simulation time 137193036 ps
CPU time 5.98 seconds
Started Aug 15 06:01:27 PM PDT 24
Finished Aug 15 06:01:33 PM PDT 24
Peak memory 211112 kb
Host smart-85dddb06-90f6-4afc-bd54-d0b6f02f3eeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=358053020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.358053020
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3112233495
Short name T327
Test name
Test status
Simulation time 126935064 ps
CPU time 7.43 seconds
Started Aug 15 06:01:32 PM PDT 24
Finished Aug 15 06:01:40 PM PDT 24
Peak memory 211076 kb
Host smart-fb817db5-aa7f-4598-9fe7-6fe14d9e5f21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112233495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3112233495
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.748102894
Short name T109
Test name
Test status
Simulation time 4041052789 ps
CPU time 227.32 seconds
Started Aug 15 06:01:26 PM PDT 24
Finished Aug 15 06:05:13 PM PDT 24
Peak memory 224136 kb
Host smart-68cd37f9-4fd3-4c83-bb52-335037d4418c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748102894 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.748102894
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.4137877101
Short name T227
Test name
Test status
Simulation time 257262166 ps
CPU time 4.75 seconds
Started Aug 15 06:01:27 PM PDT 24
Finished Aug 15 06:01:32 PM PDT 24
Peak memory 211068 kb
Host smart-831118e6-0e4f-45bd-9ff4-bb1b81e05b8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137877101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.4137877101
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2621636941
Short name T196
Test name
Test status
Simulation time 13588011693 ps
CPU time 107.96 seconds
Started Aug 15 06:01:26 PM PDT 24
Finished Aug 15 06:03:14 PM PDT 24
Peak memory 228400 kb
Host smart-36e4da03-9e68-4f69-a9e2-7d74fa95fd8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621636941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2621636941
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2770375478
Short name T194
Test name
Test status
Simulation time 267803764 ps
CPU time 10.73 seconds
Started Aug 15 06:01:32 PM PDT 24
Finished Aug 15 06:01:43 PM PDT 24
Peak memory 211064 kb
Host smart-f748ff37-ed25-4769-924c-77e36f60da5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770375478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2770375478
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1150363767
Short name T130
Test name
Test status
Simulation time 1112207061 ps
CPU time 6.28 seconds
Started Aug 15 06:01:25 PM PDT 24
Finished Aug 15 06:01:32 PM PDT 24
Peak memory 211120 kb
Host smart-f5a031b2-49ac-4dd6-a8d7-cd2e71d3ffb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1150363767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1150363767
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2644249350
Short name T287
Test name
Test status
Simulation time 1372765591 ps
CPU time 14.21 seconds
Started Aug 15 06:01:27 PM PDT 24
Finished Aug 15 06:01:41 PM PDT 24
Peak memory 212396 kb
Host smart-54b48033-9e76-45ab-aa2b-09e0691d58cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644249350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2644249350
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2720328369
Short name T303
Test name
Test status
Simulation time 6088925612 ps
CPU time 180.48 seconds
Started Aug 15 06:01:33 PM PDT 24
Finished Aug 15 06:04:33 PM PDT 24
Peak memory 223220 kb
Host smart-cf9832b7-be6c-4003-8d95-ff5ac1473b6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720328369 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2720328369
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1235747467
Short name T262
Test name
Test status
Simulation time 85548059 ps
CPU time 4.21 seconds
Started Aug 15 06:01:29 PM PDT 24
Finished Aug 15 06:01:33 PM PDT 24
Peak memory 211116 kb
Host smart-60206723-b0b8-46f0-a417-9c5c68be3553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235747467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1235747467
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.415340084
Short name T23
Test name
Test status
Simulation time 29838864504 ps
CPU time 127.34 seconds
Started Aug 15 06:01:28 PM PDT 24
Finished Aug 15 06:03:36 PM PDT 24
Peak memory 237656 kb
Host smart-4d33b42d-afb9-4bc1-9756-5c5500a8c3cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415340084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.415340084
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.223827996
Short name T310
Test name
Test status
Simulation time 261745373 ps
CPU time 6.12 seconds
Started Aug 15 06:01:28 PM PDT 24
Finished Aug 15 06:01:35 PM PDT 24
Peak memory 211160 kb
Host smart-7be89bd4-c4fa-43fd-bf8a-c6472c750e01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=223827996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.223827996
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2446892274
Short name T259
Test name
Test status
Simulation time 191214584 ps
CPU time 11.63 seconds
Started Aug 15 06:01:26 PM PDT 24
Finished Aug 15 06:01:37 PM PDT 24
Peak memory 214660 kb
Host smart-76f92226-375f-4025-81ce-7d7b718b9bb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446892274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2446892274
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.690938783
Short name T131
Test name
Test status
Simulation time 4234457071 ps
CPU time 100.14 seconds
Started Aug 15 06:01:28 PM PDT 24
Finished Aug 15 06:03:08 PM PDT 24
Peak memory 221888 kb
Host smart-3e793658-3179-4c2c-aa8c-8a522f761509
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690938783 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.690938783
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3693543460
Short name T190
Test name
Test status
Simulation time 131353572 ps
CPU time 4.94 seconds
Started Aug 15 06:01:28 PM PDT 24
Finished Aug 15 06:01:33 PM PDT 24
Peak memory 211092 kb
Host smart-7c0b1f74-fb39-4884-8ad9-f809a420652c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693543460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3693543460
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1908632301
Short name T348
Test name
Test status
Simulation time 14129578875 ps
CPU time 81.64 seconds
Started Aug 15 06:01:27 PM PDT 24
Finished Aug 15 06:02:48 PM PDT 24
Peak memory 233532 kb
Host smart-eab674a7-68f9-42de-ad30-e6fd0e7e1073
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908632301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1908632301
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1630624190
Short name T9
Test name
Test status
Simulation time 512057729 ps
CPU time 10.59 seconds
Started Aug 15 06:01:28 PM PDT 24
Finished Aug 15 06:01:39 PM PDT 24
Peak memory 211108 kb
Host smart-94b29800-448b-4230-8492-7578217a6c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630624190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1630624190
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2770414314
Short name T105
Test name
Test status
Simulation time 1259945034 ps
CPU time 7.6 seconds
Started Aug 15 06:01:27 PM PDT 24
Finished Aug 15 06:01:34 PM PDT 24
Peak memory 211044 kb
Host smart-51c61ad3-9286-40b9-9058-8b6fba058886
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2770414314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2770414314
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.699072019
Short name T312
Test name
Test status
Simulation time 629159351 ps
CPU time 7.67 seconds
Started Aug 15 06:01:27 PM PDT 24
Finished Aug 15 06:01:35 PM PDT 24
Peak memory 211096 kb
Host smart-dc7e13b1-3f5a-4f79-b247-0d7134e12d75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699072019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.699072019
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2245930239
Short name T288
Test name
Test status
Simulation time 3948627780 ps
CPU time 52.6 seconds
Started Aug 15 06:01:26 PM PDT 24
Finished Aug 15 06:02:19 PM PDT 24
Peak memory 220648 kb
Host smart-5dd1af7c-8662-471a-ab1b-d0adacf2be49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245930239 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.2245930239
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.926512817
Short name T239
Test name
Test status
Simulation time 179281272 ps
CPU time 4.85 seconds
Started Aug 15 06:01:27 PM PDT 24
Finished Aug 15 06:01:31 PM PDT 24
Peak memory 211100 kb
Host smart-82ffda87-e4cc-4e00-bf97-eb14588c4112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926512817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.926512817
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1512512963
Short name T330
Test name
Test status
Simulation time 22386737492 ps
CPU time 110.33 seconds
Started Aug 15 06:01:28 PM PDT 24
Finished Aug 15 06:03:18 PM PDT 24
Peak memory 224872 kb
Host smart-216c2d8b-d9ed-435a-887d-155134175340
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512512963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1512512963
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1414840936
Short name T245
Test name
Test status
Simulation time 257049195 ps
CPU time 10.6 seconds
Started Aug 15 06:01:29 PM PDT 24
Finished Aug 15 06:01:40 PM PDT 24
Peak memory 211088 kb
Host smart-a0cdc98a-75b6-4fc4-9c81-d4710151a238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414840936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1414840936
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3527698412
Short name T152
Test name
Test status
Simulation time 832670749 ps
CPU time 6.11 seconds
Started Aug 15 06:01:30 PM PDT 24
Finished Aug 15 06:01:36 PM PDT 24
Peak memory 211168 kb
Host smart-c59877c3-8b54-4c65-bcd9-9210b2f2f277
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3527698412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3527698412
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3790555431
Short name T153
Test name
Test status
Simulation time 1396564265 ps
CPU time 12.85 seconds
Started Aug 15 06:01:28 PM PDT 24
Finished Aug 15 06:01:41 PM PDT 24
Peak memory 213956 kb
Host smart-5daac4e3-29cc-461a-adc0-46b6e99444bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790555431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3790555431
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.599636979
Short name T181
Test name
Test status
Simulation time 10640846099 ps
CPU time 185.09 seconds
Started Aug 15 06:01:27 PM PDT 24
Finished Aug 15 06:04:32 PM PDT 24
Peak memory 230180 kb
Host smart-bc236c4f-9619-41db-94a7-0cd6e36ae205
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599636979 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.599636979
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.97807136
Short name T302
Test name
Test status
Simulation time 261186771 ps
CPU time 4.87 seconds
Started Aug 15 06:01:34 PM PDT 24
Finished Aug 15 06:01:39 PM PDT 24
Peak memory 211092 kb
Host smart-924da83d-bd9e-4208-8288-17abc4d3e6ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97807136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.97807136
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1707278992
Short name T306
Test name
Test status
Simulation time 995595591 ps
CPU time 10.65 seconds
Started Aug 15 06:01:34 PM PDT 24
Finished Aug 15 06:01:44 PM PDT 24
Peak memory 211160 kb
Host smart-3de052a1-6dce-4d2b-ba96-25684ccfb5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707278992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1707278992
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1435076439
Short name T89
Test name
Test status
Simulation time 123572499 ps
CPU time 5.48 seconds
Started Aug 15 06:01:32 PM PDT 24
Finished Aug 15 06:01:38 PM PDT 24
Peak memory 211072 kb
Host smart-150816a8-0bb6-42c2-97f4-baed6cd03a5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1435076439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1435076439
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1026878816
Short name T159
Test name
Test status
Simulation time 112698608 ps
CPU time 7.1 seconds
Started Aug 15 06:01:28 PM PDT 24
Finished Aug 15 06:01:36 PM PDT 24
Peak memory 211104 kb
Host smart-932ff598-1808-4d60-b5c7-0ae173b8a0ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026878816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1026878816
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.628607444
Short name T112
Test name
Test status
Simulation time 2641421930 ps
CPU time 109.66 seconds
Started Aug 15 06:01:37 PM PDT 24
Finished Aug 15 06:03:27 PM PDT 24
Peak memory 221368 kb
Host smart-4c2487eb-46e7-48e0-bc8b-732fca8382ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628607444 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.628607444
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3710323655
Short name T34
Test name
Test status
Simulation time 254695183 ps
CPU time 4.77 seconds
Started Aug 15 06:01:38 PM PDT 24
Finished Aug 15 06:01:42 PM PDT 24
Peak memory 211088 kb
Host smart-92f044ea-2433-4916-9c48-196e45afe830
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710323655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3710323655
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3389177452
Short name T215
Test name
Test status
Simulation time 10046486157 ps
CPU time 160.03 seconds
Started Aug 15 06:01:33 PM PDT 24
Finished Aug 15 06:04:14 PM PDT 24
Peak memory 236844 kb
Host smart-3abc024f-b29a-4a93-8d1f-5a79d76ab1cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389177452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3389177452
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2474522097
Short name T7
Test name
Test status
Simulation time 262634460 ps
CPU time 10.99 seconds
Started Aug 15 06:01:33 PM PDT 24
Finished Aug 15 06:01:44 PM PDT 24
Peak memory 211604 kb
Host smart-49ee8344-9b45-48c4-a0db-f8466ee5dd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474522097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2474522097
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2041302954
Short name T139
Test name
Test status
Simulation time 276763928 ps
CPU time 6.06 seconds
Started Aug 15 06:01:35 PM PDT 24
Finished Aug 15 06:01:41 PM PDT 24
Peak memory 211116 kb
Host smart-edbfdce1-1661-4d08-b4f9-818d31a7b9be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2041302954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2041302954
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3566779484
Short name T167
Test name
Test status
Simulation time 530884808 ps
CPU time 14.58 seconds
Started Aug 15 06:01:34 PM PDT 24
Finished Aug 15 06:01:48 PM PDT 24
Peak memory 213596 kb
Host smart-152b69af-ea21-40f7-94a3-e85651bc5396
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566779484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3566779484
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2932400924
Short name T11
Test name
Test status
Simulation time 17269089971 ps
CPU time 277.83 seconds
Started Aug 15 06:01:33 PM PDT 24
Finished Aug 15 06:06:11 PM PDT 24
Peak memory 235236 kb
Host smart-2b84d20b-d428-4d8d-9ac5-008bb6a20d65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932400924 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2932400924
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2347244833
Short name T60
Test name
Test status
Simulation time 256750111 ps
CPU time 4.91 seconds
Started Aug 15 06:01:35 PM PDT 24
Finished Aug 15 06:01:40 PM PDT 24
Peak memory 211084 kb
Host smart-9ec6ff94-e88f-4063-b7ab-647219669fb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347244833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2347244833
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4272242208
Short name T6
Test name
Test status
Simulation time 5671295059 ps
CPU time 139.86 seconds
Started Aug 15 06:01:34 PM PDT 24
Finished Aug 15 06:03:54 PM PDT 24
Peak memory 212548 kb
Host smart-0ca2a787-e04e-4efc-8d1b-abf25cf900c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272242208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.4272242208
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1487842918
Short name T124
Test name
Test status
Simulation time 254812774 ps
CPU time 10.58 seconds
Started Aug 15 06:01:34 PM PDT 24
Finished Aug 15 06:01:45 PM PDT 24
Peak memory 211152 kb
Host smart-b7915bb4-496e-498a-a8a3-69e3b55cdb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487842918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1487842918
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2128435735
Short name T162
Test name
Test status
Simulation time 97166156 ps
CPU time 5.28 seconds
Started Aug 15 06:01:34 PM PDT 24
Finished Aug 15 06:01:40 PM PDT 24
Peak memory 211148 kb
Host smart-ecb22305-01a9-41f6-a196-8f030cced5ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2128435735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2128435735
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.413872065
Short name T200
Test name
Test status
Simulation time 232221606 ps
CPU time 8.74 seconds
Started Aug 15 06:01:35 PM PDT 24
Finished Aug 15 06:01:44 PM PDT 24
Peak memory 211320 kb
Host smart-b3274e3f-b1be-44d8-aa4e-2c532e6f0b06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413872065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.413872065
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.4201331668
Short name T176
Test name
Test status
Simulation time 2125958422 ps
CPU time 134.78 seconds
Started Aug 15 06:01:34 PM PDT 24
Finished Aug 15 06:03:49 PM PDT 24
Peak memory 220752 kb
Host smart-afdada6a-9994-4889-9e2b-574386409327
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201331668 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.4201331668
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3086988120
Short name T169
Test name
Test status
Simulation time 337842214 ps
CPU time 4.01 seconds
Started Aug 15 06:01:35 PM PDT 24
Finished Aug 15 06:01:39 PM PDT 24
Peak memory 211116 kb
Host smart-5c93c699-0793-4953-9fb6-9990a513ee5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086988120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3086988120
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1834453070
Short name T174
Test name
Test status
Simulation time 2912908236 ps
CPU time 137.29 seconds
Started Aug 15 06:01:37 PM PDT 24
Finished Aug 15 06:03:54 PM PDT 24
Peak memory 228436 kb
Host smart-c50e3b22-f229-4fc8-addf-cfcb21aee6cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834453070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1834453070
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2459360330
Short name T269
Test name
Test status
Simulation time 996588973 ps
CPU time 10.62 seconds
Started Aug 15 06:01:37 PM PDT 24
Finished Aug 15 06:01:47 PM PDT 24
Peak memory 211476 kb
Host smart-fd76b2f7-cf88-4b4e-acde-0c6be8a616b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459360330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2459360330
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3364194770
Short name T309
Test name
Test status
Simulation time 1111786079 ps
CPU time 6.03 seconds
Started Aug 15 06:01:34 PM PDT 24
Finished Aug 15 06:01:40 PM PDT 24
Peak memory 211136 kb
Host smart-3debdf7d-ba8c-4679-9816-f79f380f5940
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3364194770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3364194770
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1333260688
Short name T205
Test name
Test status
Simulation time 101300938 ps
CPU time 6.95 seconds
Started Aug 15 06:01:33 PM PDT 24
Finished Aug 15 06:01:40 PM PDT 24
Peak memory 211176 kb
Host smart-22297dbd-3164-424d-853f-5b25c4566b12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333260688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1333260688
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.4103902804
Short name T42
Test name
Test status
Simulation time 3316491058 ps
CPU time 197.19 seconds
Started Aug 15 06:01:33 PM PDT 24
Finished Aug 15 06:04:50 PM PDT 24
Peak memory 232656 kb
Host smart-c49af3a0-3c84-4a83-b07b-b951302034e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103902804 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.4103902804
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2156223466
Short name T272
Test name
Test status
Simulation time 128036161 ps
CPU time 4.82 seconds
Started Aug 15 06:01:33 PM PDT 24
Finished Aug 15 06:01:38 PM PDT 24
Peak memory 211152 kb
Host smart-e88a462e-b7b7-4900-99fa-57ae5e83215b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156223466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2156223466
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.173225156
Short name T283
Test name
Test status
Simulation time 1872308212 ps
CPU time 75.1 seconds
Started Aug 15 06:01:33 PM PDT 24
Finished Aug 15 06:02:48 PM PDT 24
Peak memory 232612 kb
Host smart-1d5aaf61-a0b9-4949-bc0a-1e52698b3265
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173225156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.173225156
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2788273727
Short name T48
Test name
Test status
Simulation time 777948569 ps
CPU time 10.61 seconds
Started Aug 15 06:01:33 PM PDT 24
Finished Aug 15 06:01:44 PM PDT 24
Peak memory 211568 kb
Host smart-65a2fcab-6b78-4f51-a83e-8062857462e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788273727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2788273727
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1916016051
Short name T223
Test name
Test status
Simulation time 510675732 ps
CPU time 7.56 seconds
Started Aug 15 06:01:35 PM PDT 24
Finished Aug 15 06:01:42 PM PDT 24
Peak memory 211124 kb
Host smart-cefa0dff-d37a-4906-9e7c-2b0c32c4df33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1916016051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1916016051
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3097911219
Short name T230
Test name
Test status
Simulation time 892898987 ps
CPU time 14.33 seconds
Started Aug 15 06:01:37 PM PDT 24
Finished Aug 15 06:01:51 PM PDT 24
Peak memory 219216 kb
Host smart-4879a481-8fb5-4b91-958c-44de80bbee5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097911219 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.3097911219
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1809130894
Short name T160
Test name
Test status
Simulation time 86166299 ps
CPU time 4.1 seconds
Started Aug 15 06:01:15 PM PDT 24
Finished Aug 15 06:01:19 PM PDT 24
Peak memory 211104 kb
Host smart-7a83af72-1f7e-4ce7-9443-7af0c8de8655
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809130894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1809130894
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2607003329
Short name T311
Test name
Test status
Simulation time 13114263525 ps
CPU time 117.43 seconds
Started Aug 15 06:01:12 PM PDT 24
Finished Aug 15 06:03:09 PM PDT 24
Peak memory 240212 kb
Host smart-7de31060-32c8-4e1f-8e67-d0644c716c97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607003329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2607003329
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1840408408
Short name T44
Test name
Test status
Simulation time 551417415 ps
CPU time 10.2 seconds
Started Aug 15 06:01:15 PM PDT 24
Finished Aug 15 06:01:25 PM PDT 24
Peak memory 211124 kb
Host smart-52ae3cb7-c9c0-4d7b-b452-0c08eb97482c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840408408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1840408408
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1961425110
Short name T318
Test name
Test status
Simulation time 135458354 ps
CPU time 5.91 seconds
Started Aug 15 06:01:13 PM PDT 24
Finished Aug 15 06:01:19 PM PDT 24
Peak memory 211144 kb
Host smart-bd6a243b-365a-4a8a-a53d-3d2a7b16c12c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1961425110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1961425110
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.702273577
Short name T36
Test name
Test status
Simulation time 1164848996 ps
CPU time 54.01 seconds
Started Aug 15 06:01:12 PM PDT 24
Finished Aug 15 06:02:07 PM PDT 24
Peak memory 235748 kb
Host smart-1f15c270-e32c-41d9-aa68-35fb9588f1d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702273577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.702273577
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2705685834
Short name T51
Test name
Test status
Simulation time 278096896 ps
CPU time 6.15 seconds
Started Aug 15 06:01:11 PM PDT 24
Finished Aug 15 06:01:17 PM PDT 24
Peak memory 211460 kb
Host smart-64beb980-494b-46e5-8a51-f44c253bfe20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705685834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2705685834
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3661942470
Short name T149
Test name
Test status
Simulation time 223366695 ps
CPU time 9.29 seconds
Started Aug 15 06:01:11 PM PDT 24
Finished Aug 15 06:01:20 PM PDT 24
Peak memory 212096 kb
Host smart-1ff999a1-5244-47d6-8fcd-7333c6dc956d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661942470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3661942470
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1736343824
Short name T16
Test name
Test status
Simulation time 8061196672 ps
CPU time 77.18 seconds
Started Aug 15 06:01:12 PM PDT 24
Finished Aug 15 06:02:30 PM PDT 24
Peak memory 222220 kb
Host smart-6d1ec03d-e5e6-4b40-b6e3-56bbc888003c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736343824 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1736343824
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.978385951
Short name T204
Test name
Test status
Simulation time 1181759309 ps
CPU time 4.07 seconds
Started Aug 15 06:01:37 PM PDT 24
Finished Aug 15 06:01:41 PM PDT 24
Peak memory 211140 kb
Host smart-b976dd15-24c0-4082-acf7-f879053fd807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978385951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.978385951
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1886884864
Short name T253
Test name
Test status
Simulation time 990889307 ps
CPU time 14.72 seconds
Started Aug 15 06:01:34 PM PDT 24
Finished Aug 15 06:01:49 PM PDT 24
Peak memory 211528 kb
Host smart-87dd46df-9a9f-4f71-af3d-c5f174b23777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886884864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1886884864
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2410094047
Short name T125
Test name
Test status
Simulation time 275219750 ps
CPU time 6.47 seconds
Started Aug 15 06:01:34 PM PDT 24
Finished Aug 15 06:01:41 PM PDT 24
Peak memory 211124 kb
Host smart-9d60d154-573e-4b34-946d-49deeb2a0823
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2410094047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2410094047
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1103921907
Short name T10
Test name
Test status
Simulation time 1513976199 ps
CPU time 19.59 seconds
Started Aug 15 06:01:36 PM PDT 24
Finished Aug 15 06:01:56 PM PDT 24
Peak memory 214244 kb
Host smart-98a65684-add4-49f1-929d-d4ba83acbbe5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103921907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1103921907
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3772070977
Short name T292
Test name
Test status
Simulation time 3422069965 ps
CPU time 99.36 seconds
Started Aug 15 06:01:37 PM PDT 24
Finished Aug 15 06:03:16 PM PDT 24
Peak memory 220436 kb
Host smart-de38c8a9-12f2-4010-863a-d8c716b30db3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772070977 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3772070977
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3160242521
Short name T208
Test name
Test status
Simulation time 329259229 ps
CPU time 4.89 seconds
Started Aug 15 06:01:40 PM PDT 24
Finished Aug 15 06:01:45 PM PDT 24
Peak memory 211128 kb
Host smart-7b7a69a7-305a-424e-b0fc-e431d6bed127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160242521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3160242521
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4075683037
Short name T43
Test name
Test status
Simulation time 520110231 ps
CPU time 10.74 seconds
Started Aug 15 06:01:42 PM PDT 24
Finished Aug 15 06:01:52 PM PDT 24
Peak memory 211472 kb
Host smart-a744ec5e-b3ce-4f0c-8b50-3e0605466032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075683037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4075683037
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1666341000
Short name T145
Test name
Test status
Simulation time 672314383 ps
CPU time 5.62 seconds
Started Aug 15 06:01:40 PM PDT 24
Finished Aug 15 06:01:46 PM PDT 24
Peak memory 211132 kb
Host smart-b9eb75a8-0993-4a54-8473-85702a0cee0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1666341000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1666341000
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3088682316
Short name T209
Test name
Test status
Simulation time 1679330179 ps
CPU time 9.31 seconds
Started Aug 15 06:01:32 PM PDT 24
Finished Aug 15 06:01:41 PM PDT 24
Peak memory 211896 kb
Host smart-506f437d-7074-4d98-85cc-5aaf8ad67a97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088682316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3088682316
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3621140326
Short name T12
Test name
Test status
Simulation time 4358013779 ps
CPU time 92.51 seconds
Started Aug 15 06:01:48 PM PDT 24
Finished Aug 15 06:03:21 PM PDT 24
Peak memory 223416 kb
Host smart-3eccf9f0-a9b2-4543-8769-b9edef19038c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621140326 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.3621140326
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1038204563
Short name T270
Test name
Test status
Simulation time 348356399 ps
CPU time 4.05 seconds
Started Aug 15 06:01:43 PM PDT 24
Finished Aug 15 06:01:47 PM PDT 24
Peak memory 211124 kb
Host smart-b0ef2ad6-dbf8-4325-a27a-90472447feee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038204563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1038204563
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2169437713
Short name T207
Test name
Test status
Simulation time 13231235879 ps
CPU time 143.84 seconds
Started Aug 15 06:01:40 PM PDT 24
Finished Aug 15 06:04:04 PM PDT 24
Peak memory 237672 kb
Host smart-4e1e61c3-4713-4331-ae57-35abf207ef16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169437713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2169437713
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2685653983
Short name T237
Test name
Test status
Simulation time 261434180 ps
CPU time 10.41 seconds
Started Aug 15 06:01:48 PM PDT 24
Finished Aug 15 06:01:58 PM PDT 24
Peak memory 211636 kb
Host smart-6b544adf-6278-4b2e-89ba-6e28229e75b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685653983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2685653983
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2170414270
Short name T165
Test name
Test status
Simulation time 547991576 ps
CPU time 6.02 seconds
Started Aug 15 06:01:41 PM PDT 24
Finished Aug 15 06:01:47 PM PDT 24
Peak memory 211044 kb
Host smart-193bd475-ae7b-49c2-832e-d530cffca981
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2170414270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2170414270
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.343437854
Short name T158
Test name
Test status
Simulation time 884139258 ps
CPU time 18.31 seconds
Started Aug 15 06:01:49 PM PDT 24
Finished Aug 15 06:02:08 PM PDT 24
Peak memory 215244 kb
Host smart-4684767e-891e-4959-8732-54cab91f1304
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343437854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.343437854
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.4102540290
Short name T40
Test name
Test status
Simulation time 2352838214 ps
CPU time 139.92 seconds
Started Aug 15 06:01:43 PM PDT 24
Finished Aug 15 06:04:03 PM PDT 24
Peak memory 220916 kb
Host smart-70110139-d31b-46c5-b0cb-dc8fda5ce4c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102540290 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.4102540290
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.35926613
Short name T133
Test name
Test status
Simulation time 480582874 ps
CPU time 4.79 seconds
Started Aug 15 06:01:38 PM PDT 24
Finished Aug 15 06:01:43 PM PDT 24
Peak memory 211088 kb
Host smart-54ef0a77-68d2-4983-b676-1288f242b2fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35926613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.35926613
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2869290582
Short name T47
Test name
Test status
Simulation time 10113782162 ps
CPU time 104.92 seconds
Started Aug 15 06:01:40 PM PDT 24
Finished Aug 15 06:03:26 PM PDT 24
Peak memory 212920 kb
Host smart-269cfde9-03e1-4a71-b75e-6d5f08876514
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869290582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2869290582
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1187832207
Short name T294
Test name
Test status
Simulation time 1036837023 ps
CPU time 10.62 seconds
Started Aug 15 06:01:42 PM PDT 24
Finished Aug 15 06:01:53 PM PDT 24
Peak memory 211536 kb
Host smart-f0c7a2fc-4d07-4c0c-8950-aff2c53525f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187832207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1187832207
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.4195886197
Short name T137
Test name
Test status
Simulation time 274291542 ps
CPU time 6.17 seconds
Started Aug 15 06:01:42 PM PDT 24
Finished Aug 15 06:01:48 PM PDT 24
Peak memory 211104 kb
Host smart-f9e6d657-e391-4ce9-9644-9a34b19251f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4195886197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.4195886197
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1556189013
Short name T280
Test name
Test status
Simulation time 573786843 ps
CPU time 12.21 seconds
Started Aug 15 06:01:45 PM PDT 24
Finished Aug 15 06:01:57 PM PDT 24
Peak memory 214388 kb
Host smart-ee42b7b3-e19e-4443-87fd-33ceb3d14f6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556189013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1556189013
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.853014833
Short name T186
Test name
Test status
Simulation time 1567659694 ps
CPU time 64.64 seconds
Started Aug 15 06:01:41 PM PDT 24
Finished Aug 15 06:02:45 PM PDT 24
Peak memory 219600 kb
Host smart-481f9dba-064b-40af-9ca9-afaca75aa5b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853014833 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.853014833
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2768840988
Short name T212
Test name
Test status
Simulation time 538941099 ps
CPU time 4.76 seconds
Started Aug 15 06:01:42 PM PDT 24
Finished Aug 15 06:01:47 PM PDT 24
Peak memory 211072 kb
Host smart-44174cbd-ff10-4b62-be8e-fcb878411d14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768840988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2768840988
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2742055455
Short name T257
Test name
Test status
Simulation time 2827884503 ps
CPU time 100.92 seconds
Started Aug 15 06:01:44 PM PDT 24
Finished Aug 15 06:03:25 PM PDT 24
Peak memory 228020 kb
Host smart-5903262a-a01a-4d1a-b028-c03f49465f84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742055455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2742055455
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.728317724
Short name T170
Test name
Test status
Simulation time 1036823531 ps
CPU time 10.35 seconds
Started Aug 15 06:01:38 PM PDT 24
Finished Aug 15 06:01:48 PM PDT 24
Peak memory 211120 kb
Host smart-830efe4e-94fd-4369-966c-b3a2762ab4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728317724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.728317724
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3364268630
Short name T218
Test name
Test status
Simulation time 138624860 ps
CPU time 5.96 seconds
Started Aug 15 06:01:39 PM PDT 24
Finished Aug 15 06:01:45 PM PDT 24
Peak memory 211096 kb
Host smart-943c294e-ff32-4dc9-8823-bfa7a6b28710
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3364268630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3364268630
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.4079999492
Short name T231
Test name
Test status
Simulation time 400047268 ps
CPU time 18.01 seconds
Started Aug 15 06:01:42 PM PDT 24
Finished Aug 15 06:02:00 PM PDT 24
Peak memory 215356 kb
Host smart-450cfaf4-0310-4b54-95c1-27652e1389d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079999492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.4079999492
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3449260771
Short name T24
Test name
Test status
Simulation time 8194593270 ps
CPU time 83.79 seconds
Started Aug 15 06:01:48 PM PDT 24
Finished Aug 15 06:03:12 PM PDT 24
Peak memory 221764 kb
Host smart-bae7fff9-61b7-4059-86e5-84351ec647b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449260771 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.3449260771
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3441587046
Short name T155
Test name
Test status
Simulation time 497223037 ps
CPU time 5.08 seconds
Started Aug 15 06:01:40 PM PDT 24
Finished Aug 15 06:01:45 PM PDT 24
Peak memory 211120 kb
Host smart-b5b6a37a-d36a-444e-8edc-18ad2373f817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441587046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3441587046
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.54428481
Short name T168
Test name
Test status
Simulation time 3796283471 ps
CPU time 50.83 seconds
Started Aug 15 06:01:43 PM PDT 24
Finished Aug 15 06:02:34 PM PDT 24
Peak memory 211452 kb
Host smart-d442f427-e22f-4718-97f6-4151a14457bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54428481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_co
rrupt_sig_fatal_chk.54428481
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1694911451
Short name T307
Test name
Test status
Simulation time 169203865 ps
CPU time 9.32 seconds
Started Aug 15 06:01:42 PM PDT 24
Finished Aug 15 06:01:51 PM PDT 24
Peak memory 211132 kb
Host smart-9ac71f6b-1a4e-4419-89d4-7a3898252362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694911451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1694911451
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.4198913197
Short name T228
Test name
Test status
Simulation time 111874196 ps
CPU time 5.41 seconds
Started Aug 15 06:01:41 PM PDT 24
Finished Aug 15 06:01:46 PM PDT 24
Peak memory 211116 kb
Host smart-272131f8-8378-4cd5-9a22-548e41a948bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4198913197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.4198913197
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3420296900
Short name T46
Test name
Test status
Simulation time 581102229 ps
CPU time 18.78 seconds
Started Aug 15 06:01:43 PM PDT 24
Finished Aug 15 06:02:02 PM PDT 24
Peak memory 215160 kb
Host smart-2d1b895c-f3ac-4d6e-9746-9125031dff37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420296900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3420296900
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3429983285
Short name T242
Test name
Test status
Simulation time 12466547917 ps
CPU time 121.29 seconds
Started Aug 15 06:01:41 PM PDT 24
Finished Aug 15 06:03:42 PM PDT 24
Peak memory 231084 kb
Host smart-ee43cfef-7d55-4d52-950d-c92cf3c7f42b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429983285 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3429983285
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2793138918
Short name T211
Test name
Test status
Simulation time 251139388 ps
CPU time 4.87 seconds
Started Aug 15 06:01:49 PM PDT 24
Finished Aug 15 06:01:54 PM PDT 24
Peak memory 211060 kb
Host smart-bff511fd-0f95-432f-910f-00c4d9f02a3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793138918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2793138918
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4046086521
Short name T166
Test name
Test status
Simulation time 18252896531 ps
CPU time 213.51 seconds
Started Aug 15 06:01:42 PM PDT 24
Finished Aug 15 06:05:15 PM PDT 24
Peak memory 233604 kb
Host smart-6b590391-2177-445d-819e-ebd269731a3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046086521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.4046086521
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3563358365
Short name T49
Test name
Test status
Simulation time 697009301 ps
CPU time 9 seconds
Started Aug 15 06:01:49 PM PDT 24
Finished Aug 15 06:01:58 PM PDT 24
Peak memory 211540 kb
Host smart-683cb16a-3f5d-48b4-afa4-0c34192daf44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563358365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3563358365
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.6651157
Short name T157
Test name
Test status
Simulation time 136181279 ps
CPU time 5.98 seconds
Started Aug 15 06:01:41 PM PDT 24
Finished Aug 15 06:01:47 PM PDT 24
Peak memory 211172 kb
Host smart-a5139e98-b62e-42df-a2e8-6d8e31b6d1b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=6651157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.6651157
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3188697927
Short name T251
Test name
Test status
Simulation time 900793625 ps
CPU time 19.06 seconds
Started Aug 15 06:01:40 PM PDT 24
Finished Aug 15 06:01:59 PM PDT 24
Peak memory 214744 kb
Host smart-02284b38-364c-47a5-ace1-2e2fa80dc502
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188697927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3188697927
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2284817903
Short name T177
Test name
Test status
Simulation time 332649074 ps
CPU time 4.18 seconds
Started Aug 15 06:01:49 PM PDT 24
Finished Aug 15 06:01:53 PM PDT 24
Peak memory 211132 kb
Host smart-066cbc78-df1b-4a90-bb61-40d6b9ae4153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284817903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2284817903
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1596470058
Short name T192
Test name
Test status
Simulation time 1975010981 ps
CPU time 98.33 seconds
Started Aug 15 06:01:53 PM PDT 24
Finished Aug 15 06:03:31 PM PDT 24
Peak memory 232536 kb
Host smart-0a73ab3b-698f-47e3-bf22-3dd2d7952277
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596470058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1596470058
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1740459725
Short name T291
Test name
Test status
Simulation time 641210667 ps
CPU time 9.03 seconds
Started Aug 15 06:01:50 PM PDT 24
Finished Aug 15 06:01:59 PM PDT 24
Peak memory 211664 kb
Host smart-f95ee63b-29ab-48b5-a1ba-388dbf4fca65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740459725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1740459725
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3006622490
Short name T299
Test name
Test status
Simulation time 1818874824 ps
CPU time 5.49 seconds
Started Aug 15 06:01:50 PM PDT 24
Finished Aug 15 06:01:55 PM PDT 24
Peak memory 211124 kb
Host smart-12b71dec-e40c-4cdc-894b-b9fc67a53ac3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3006622490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3006622490
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3794234246
Short name T122
Test name
Test status
Simulation time 2379132769 ps
CPU time 14.51 seconds
Started Aug 15 06:01:54 PM PDT 24
Finished Aug 15 06:02:09 PM PDT 24
Peak memory 213944 kb
Host smart-621a83d6-5ab1-4595-9697-cc112ffb6b98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794234246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3794234246
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2871359619
Short name T352
Test name
Test status
Simulation time 1349513386 ps
CPU time 16.14 seconds
Started Aug 15 06:01:50 PM PDT 24
Finished Aug 15 06:02:06 PM PDT 24
Peak memory 219216 kb
Host smart-ece1f4e6-4682-4548-805d-59f441402979
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871359619 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.2871359619
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3773822920
Short name T224
Test name
Test status
Simulation time 518653092 ps
CPU time 5.01 seconds
Started Aug 15 06:01:48 PM PDT 24
Finished Aug 15 06:01:53 PM PDT 24
Peak memory 211144 kb
Host smart-3e844d2a-b30a-4e68-a86e-4fefa8dfb972
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773822920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3773822920
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1637774112
Short name T325
Test name
Test status
Simulation time 8459675917 ps
CPU time 120.44 seconds
Started Aug 15 06:01:55 PM PDT 24
Finished Aug 15 06:03:56 PM PDT 24
Peak memory 236592 kb
Host smart-7bb92ff5-ddb9-499c-b916-fea25489fe13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637774112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1637774112
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.155601885
Short name T322
Test name
Test status
Simulation time 192719246 ps
CPU time 9.11 seconds
Started Aug 15 06:01:49 PM PDT 24
Finished Aug 15 06:01:58 PM PDT 24
Peak memory 211564 kb
Host smart-a96ceb5f-dfa2-4f17-aa86-27c203839ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155601885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.155601885
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1589898003
Short name T1
Test name
Test status
Simulation time 1473285749 ps
CPU time 6.26 seconds
Started Aug 15 06:01:49 PM PDT 24
Finished Aug 15 06:01:55 PM PDT 24
Peak memory 211132 kb
Host smart-85e54be7-4e77-4c9c-b1c0-62f6989b4001
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1589898003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1589898003
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2728254100
Short name T201
Test name
Test status
Simulation time 607067470 ps
CPU time 16.22 seconds
Started Aug 15 06:01:48 PM PDT 24
Finished Aug 15 06:02:04 PM PDT 24
Peak memory 215800 kb
Host smart-49b3a6b5-102f-444c-8fb7-e91f8a8beda0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728254100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2728254100
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3085597380
Short name T220
Test name
Test status
Simulation time 6021888181 ps
CPU time 103.08 seconds
Started Aug 15 06:01:49 PM PDT 24
Finished Aug 15 06:03:33 PM PDT 24
Peak memory 227520 kb
Host smart-dbcdd6c7-884d-4fab-9b32-7655a23a00b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085597380 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3085597380
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2197760438
Short name T349
Test name
Test status
Simulation time 130871668 ps
CPU time 4.73 seconds
Started Aug 15 06:01:55 PM PDT 24
Finished Aug 15 06:02:00 PM PDT 24
Peak memory 211020 kb
Host smart-49921166-a64f-4307-8de5-cef0fc3b844e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197760438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2197760438
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1248172994
Short name T314
Test name
Test status
Simulation time 16346832385 ps
CPU time 194.56 seconds
Started Aug 15 06:01:48 PM PDT 24
Finished Aug 15 06:05:03 PM PDT 24
Peak memory 224968 kb
Host smart-6736d5dd-d8ca-4f8a-ab60-18dac719c99c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248172994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1248172994
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2559912472
Short name T338
Test name
Test status
Simulation time 993095947 ps
CPU time 14.67 seconds
Started Aug 15 06:01:49 PM PDT 24
Finished Aug 15 06:02:03 PM PDT 24
Peak memory 211576 kb
Host smart-2189ee64-3668-4347-9d68-8f690b995374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559912472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2559912472
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2191033518
Short name T178
Test name
Test status
Simulation time 139667177 ps
CPU time 5.96 seconds
Started Aug 15 06:01:51 PM PDT 24
Finished Aug 15 06:01:57 PM PDT 24
Peak memory 211068 kb
Host smart-a3068e64-ebe0-4660-879a-203cd60ac551
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2191033518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2191033518
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1603431778
Short name T326
Test name
Test status
Simulation time 611243094 ps
CPU time 15.27 seconds
Started Aug 15 06:01:56 PM PDT 24
Finished Aug 15 06:02:11 PM PDT 24
Peak memory 214216 kb
Host smart-722a37d8-0b82-439c-9f3e-44970a3d9c6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603431778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1603431778
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3774475755
Short name T315
Test name
Test status
Simulation time 2426455521 ps
CPU time 37.93 seconds
Started Aug 15 06:01:50 PM PDT 24
Finished Aug 15 06:02:29 PM PDT 24
Peak memory 219308 kb
Host smart-80022405-f476-4c01-a84b-14c237676056
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774475755 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3774475755
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2134597180
Short name T244
Test name
Test status
Simulation time 495042049 ps
CPU time 5.04 seconds
Started Aug 15 06:01:13 PM PDT 24
Finished Aug 15 06:01:18 PM PDT 24
Peak memory 211112 kb
Host smart-cfb4b3d8-4852-48ad-9043-68e11783dc62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134597180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2134597180
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4032881936
Short name T123
Test name
Test status
Simulation time 960907063 ps
CPU time 47.87 seconds
Started Aug 15 06:01:13 PM PDT 24
Finished Aug 15 06:02:01 PM PDT 24
Peak memory 227972 kb
Host smart-13f4c183-42f8-45c0-8bf7-3a55ad73746c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032881936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.4032881936
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2701174701
Short name T279
Test name
Test status
Simulation time 1136762084 ps
CPU time 10.88 seconds
Started Aug 15 06:01:14 PM PDT 24
Finished Aug 15 06:01:25 PM PDT 24
Peak memory 211140 kb
Host smart-566be137-c109-41a4-9e92-c7e42c6f8bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701174701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2701174701
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1537141442
Short name T276
Test name
Test status
Simulation time 97278888 ps
CPU time 5.29 seconds
Started Aug 15 06:01:12 PM PDT 24
Finished Aug 15 06:01:17 PM PDT 24
Peak memory 211092 kb
Host smart-4f98b9ac-4a83-46ab-b093-bb39052308bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1537141442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1537141442
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.4232070924
Short name T31
Test name
Test status
Simulation time 265932198 ps
CPU time 99.72 seconds
Started Aug 15 06:01:13 PM PDT 24
Finished Aug 15 06:02:53 PM PDT 24
Peak memory 235404 kb
Host smart-6e85ed85-2c53-435b-be52-fe81152256cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232070924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4232070924
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.4000529271
Short name T3
Test name
Test status
Simulation time 195417984 ps
CPU time 5.3 seconds
Started Aug 15 06:01:13 PM PDT 24
Finished Aug 15 06:01:18 PM PDT 24
Peak memory 212384 kb
Host smart-ba62a11b-0ae4-4738-8bed-05a35a0a933b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000529271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.4000529271
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2105804099
Short name T70
Test name
Test status
Simulation time 164517002 ps
CPU time 8.29 seconds
Started Aug 15 06:01:14 PM PDT 24
Finished Aug 15 06:01:23 PM PDT 24
Peak memory 211472 kb
Host smart-9d4c3cdc-eb8a-41bf-94a9-579c28501b55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105804099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2105804099
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3669553498
Short name T180
Test name
Test status
Simulation time 1219107134 ps
CPU time 48.39 seconds
Started Aug 15 06:01:14 PM PDT 24
Finished Aug 15 06:02:02 PM PDT 24
Peak memory 220624 kb
Host smart-53b7e2e4-10f6-425f-827e-c413041524f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669553498 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.3669553498
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.699725461
Short name T33
Test name
Test status
Simulation time 249382571 ps
CPU time 4.81 seconds
Started Aug 15 06:01:55 PM PDT 24
Finished Aug 15 06:02:00 PM PDT 24
Peak memory 211072 kb
Host smart-13b0cdba-a836-4b8a-9737-10501fb9dc70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699725461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.699725461
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.639118935
Short name T243
Test name
Test status
Simulation time 5108448287 ps
CPU time 83.5 seconds
Started Aug 15 06:01:48 PM PDT 24
Finished Aug 15 06:03:11 PM PDT 24
Peak memory 236436 kb
Host smart-4f88c2f7-7a97-41fe-86b0-1742b1097170
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639118935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.639118935
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1095778907
Short name T225
Test name
Test status
Simulation time 4963434773 ps
CPU time 10.9 seconds
Started Aug 15 06:01:54 PM PDT 24
Finished Aug 15 06:02:05 PM PDT 24
Peak memory 211184 kb
Host smart-f22eeb07-16df-4053-9959-d7649f64aa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095778907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1095778907
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1784522031
Short name T304
Test name
Test status
Simulation time 185596969 ps
CPU time 4.96 seconds
Started Aug 15 06:01:56 PM PDT 24
Finished Aug 15 06:02:01 PM PDT 24
Peak memory 211036 kb
Host smart-aabf7a02-8cac-40ef-8b2d-5fc21c2bbc98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1784522031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1784522031
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.453745252
Short name T213
Test name
Test status
Simulation time 735442920 ps
CPU time 8.89 seconds
Started Aug 15 06:01:55 PM PDT 24
Finished Aug 15 06:02:04 PM PDT 24
Peak memory 210876 kb
Host smart-a6408ab9-0e3f-430c-abba-6841f3138523
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453745252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.453745252
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.869488642
Short name T268
Test name
Test status
Simulation time 4614246703 ps
CPU time 82.94 seconds
Started Aug 15 06:01:55 PM PDT 24
Finished Aug 15 06:03:18 PM PDT 24
Peak memory 222568 kb
Host smart-f70b9e06-dac5-46a7-8397-e6af87a4f882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869488642 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.869488642
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2739142645
Short name T345
Test name
Test status
Simulation time 291648572 ps
CPU time 4.98 seconds
Started Aug 15 06:01:55 PM PDT 24
Finished Aug 15 06:02:00 PM PDT 24
Peak memory 211104 kb
Host smart-450230df-298b-41f8-a78c-f8a7c4516027
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739142645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2739142645
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.636628990
Short name T184
Test name
Test status
Simulation time 63596376235 ps
CPU time 271.7 seconds
Started Aug 15 06:01:54 PM PDT 24
Finished Aug 15 06:06:26 PM PDT 24
Peak memory 234760 kb
Host smart-9dfda5df-eff6-4019-a326-79f095a47135
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636628990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.636628990
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.146632698
Short name T5
Test name
Test status
Simulation time 262710572 ps
CPU time 10.73 seconds
Started Aug 15 06:02:01 PM PDT 24
Finished Aug 15 06:02:11 PM PDT 24
Peak memory 210972 kb
Host smart-f29f547a-0f5e-4c08-ab20-e84e0bd6c732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146632698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.146632698
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3414958493
Short name T19
Test name
Test status
Simulation time 397184613 ps
CPU time 5.54 seconds
Started Aug 15 06:01:58 PM PDT 24
Finished Aug 15 06:02:04 PM PDT 24
Peak memory 211104 kb
Host smart-286c9e3b-d6e9-46b4-b1b4-28fdae3d8bf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3414958493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3414958493
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3765648698
Short name T121
Test name
Test status
Simulation time 712410610 ps
CPU time 8.23 seconds
Started Aug 15 06:01:57 PM PDT 24
Finished Aug 15 06:02:05 PM PDT 24
Peak memory 211428 kb
Host smart-0d79c79b-de47-4375-a163-abbe59102f9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765648698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3765648698
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3975060647
Short name T52
Test name
Test status
Simulation time 9954014279 ps
CPU time 160.32 seconds
Started Aug 15 06:02:01 PM PDT 24
Finished Aug 15 06:04:41 PM PDT 24
Peak memory 222584 kb
Host smart-fb8bc4e4-6c21-41db-9b98-9ffad94f9463
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975060647 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.3975060647
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1235573208
Short name T115
Test name
Test status
Simulation time 250585048 ps
CPU time 4.89 seconds
Started Aug 15 06:01:58 PM PDT 24
Finished Aug 15 06:02:03 PM PDT 24
Peak memory 211112 kb
Host smart-59865b49-00cb-4d92-8ead-419fb0b5b53e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235573208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1235573208
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3559431072
Short name T28
Test name
Test status
Simulation time 5388269690 ps
CPU time 164.13 seconds
Started Aug 15 06:01:58 PM PDT 24
Finished Aug 15 06:04:42 PM PDT 24
Peak memory 237692 kb
Host smart-60e88f31-e025-4804-89eb-ebcf41c4d9ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559431072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3559431072
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1005571416
Short name T284
Test name
Test status
Simulation time 1187304029 ps
CPU time 8.93 seconds
Started Aug 15 06:01:54 PM PDT 24
Finished Aug 15 06:02:03 PM PDT 24
Peak memory 211424 kb
Host smart-c797dddb-2f82-4010-82ce-737bfb57399b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005571416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1005571416
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2577662989
Short name T249
Test name
Test status
Simulation time 529158510 ps
CPU time 5.7 seconds
Started Aug 15 06:01:55 PM PDT 24
Finished Aug 15 06:02:01 PM PDT 24
Peak memory 211072 kb
Host smart-3b647c06-cf92-405f-8231-cfdf05dc5c1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2577662989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2577662989
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3713015418
Short name T129
Test name
Test status
Simulation time 305263577 ps
CPU time 14.65 seconds
Started Aug 15 06:01:55 PM PDT 24
Finished Aug 15 06:02:09 PM PDT 24
Peak memory 216284 kb
Host smart-e453884b-3702-45be-92b5-b9842c849ffc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713015418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3713015418
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2484791003
Short name T179
Test name
Test status
Simulation time 3576427300 ps
CPU time 76.86 seconds
Started Aug 15 06:01:56 PM PDT 24
Finished Aug 15 06:03:13 PM PDT 24
Peak memory 222468 kb
Host smart-bf176e9e-40be-4eef-a3d1-5b698973d5c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484791003 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.2484791003
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.4257947996
Short name T256
Test name
Test status
Simulation time 1181606712 ps
CPU time 4.04 seconds
Started Aug 15 06:02:00 PM PDT 24
Finished Aug 15 06:02:05 PM PDT 24
Peak memory 211124 kb
Host smart-03d077a0-0e2d-436a-931a-a6c0b6c54ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257947996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.4257947996
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1624932364
Short name T350
Test name
Test status
Simulation time 2083762330 ps
CPU time 88.27 seconds
Started Aug 15 06:02:00 PM PDT 24
Finished Aug 15 06:03:29 PM PDT 24
Peak memory 236236 kb
Host smart-1c02bcf6-131d-4ecf-a8b4-1e92c1611a41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624932364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1624932364
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1892160074
Short name T300
Test name
Test status
Simulation time 1041067214 ps
CPU time 10.71 seconds
Started Aug 15 06:01:55 PM PDT 24
Finished Aug 15 06:02:06 PM PDT 24
Peak memory 211480 kb
Host smart-3208ede2-028e-437f-a93f-16c43b18f467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892160074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1892160074
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3792853091
Short name T206
Test name
Test status
Simulation time 580338725 ps
CPU time 6.15 seconds
Started Aug 15 06:01:55 PM PDT 24
Finished Aug 15 06:02:01 PM PDT 24
Peak memory 211104 kb
Host smart-3a49d076-37a5-45c9-ba70-2431995230f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3792853091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3792853091
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.749206620
Short name T41
Test name
Test status
Simulation time 2801285772 ps
CPU time 14.98 seconds
Started Aug 15 06:01:56 PM PDT 24
Finished Aug 15 06:02:11 PM PDT 24
Peak memory 214880 kb
Host smart-6657a81b-b922-4e64-a011-ab14035c62c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749206620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.749206620
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1047275807
Short name T175
Test name
Test status
Simulation time 4103397621 ps
CPU time 117.2 seconds
Started Aug 15 06:01:58 PM PDT 24
Finished Aug 15 06:03:55 PM PDT 24
Peak memory 227736 kb
Host smart-6f261cdc-50e9-44f1-a441-d0ea50fef249
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047275807 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.1047275807
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3003776141
Short name T320
Test name
Test status
Simulation time 520765778 ps
CPU time 4.96 seconds
Started Aug 15 06:02:00 PM PDT 24
Finished Aug 15 06:02:05 PM PDT 24
Peak memory 211096 kb
Host smart-7384b731-28b9-4522-903f-24d0991a35da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003776141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3003776141
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.462861437
Short name T191
Test name
Test status
Simulation time 4844782628 ps
CPU time 65.58 seconds
Started Aug 15 06:01:55 PM PDT 24
Finished Aug 15 06:03:01 PM PDT 24
Peak memory 232596 kb
Host smart-6c21a21c-bbce-4704-a3b2-7a50f6437bd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462861437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.462861437
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.262323946
Short name T222
Test name
Test status
Simulation time 262537199 ps
CPU time 10.5 seconds
Started Aug 15 06:01:55 PM PDT 24
Finished Aug 15 06:02:06 PM PDT 24
Peak memory 211124 kb
Host smart-fa3fc5c1-05b7-44e8-9525-1f01b5e9c62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262323946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.262323946
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2722547047
Short name T337
Test name
Test status
Simulation time 145425521 ps
CPU time 6.54 seconds
Started Aug 15 06:01:57 PM PDT 24
Finished Aug 15 06:02:04 PM PDT 24
Peak memory 211120 kb
Host smart-b2c4ff4b-b2e7-48fd-9935-0d253e874419
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2722547047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2722547047
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.137063818
Short name T71
Test name
Test status
Simulation time 226275972 ps
CPU time 15.17 seconds
Started Aug 15 06:01:55 PM PDT 24
Finished Aug 15 06:02:10 PM PDT 24
Peak memory 213168 kb
Host smart-93201428-3035-4a21-9dff-794d54056a0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137063818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.137063818
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2653202943
Short name T298
Test name
Test status
Simulation time 4004437631 ps
CPU time 76.33 seconds
Started Aug 15 06:01:54 PM PDT 24
Finished Aug 15 06:03:11 PM PDT 24
Peak memory 223108 kb
Host smart-509d12d1-564f-4c89-a1e0-bc0270db0b19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653202943 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2653202943
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2577108536
Short name T297
Test name
Test status
Simulation time 249350041 ps
CPU time 3.98 seconds
Started Aug 15 06:02:04 PM PDT 24
Finished Aug 15 06:02:08 PM PDT 24
Peak memory 211144 kb
Host smart-277cb379-a877-487f-baec-1ea412817038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577108536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2577108536
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4101163509
Short name T25
Test name
Test status
Simulation time 13703006683 ps
CPU time 167.52 seconds
Started Aug 15 06:02:04 PM PDT 24
Finished Aug 15 06:04:51 PM PDT 24
Peak memory 234744 kb
Host smart-f6a6284e-ef1f-4752-8e37-dd7a49cfd999
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101163509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.4101163509
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2173566924
Short name T189
Test name
Test status
Simulation time 834627419 ps
CPU time 10.41 seconds
Started Aug 15 06:02:06 PM PDT 24
Finished Aug 15 06:02:16 PM PDT 24
Peak memory 211108 kb
Host smart-cb91cf51-b871-4948-bf94-f150740a83d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173566924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2173566924
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2936069559
Short name T154
Test name
Test status
Simulation time 141198928 ps
CPU time 6.14 seconds
Started Aug 15 06:01:54 PM PDT 24
Finished Aug 15 06:02:00 PM PDT 24
Peak memory 211084 kb
Host smart-fc8bcf6d-e18f-48d6-8390-48224d127327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2936069559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2936069559
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.4252151177
Short name T331
Test name
Test status
Simulation time 176387816 ps
CPU time 7.35 seconds
Started Aug 15 06:01:55 PM PDT 24
Finished Aug 15 06:02:02 PM PDT 24
Peak memory 211020 kb
Host smart-016d3f51-5a3b-446c-b9ad-64926e8f629e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252151177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.4252151177
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2409101596
Short name T266
Test name
Test status
Simulation time 350144616 ps
CPU time 4.11 seconds
Started Aug 15 06:02:07 PM PDT 24
Finished Aug 15 06:02:11 PM PDT 24
Peak memory 211108 kb
Host smart-4837aaa1-e4e4-4f18-8466-7c7ce9182643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409101596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2409101596
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.405261166
Short name T238
Test name
Test status
Simulation time 3397077645 ps
CPU time 143.89 seconds
Started Aug 15 06:02:06 PM PDT 24
Finished Aug 15 06:04:30 PM PDT 24
Peak memory 237128 kb
Host smart-1760f159-7f54-4755-afe1-73e5d23f8b90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405261166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.405261166
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3424619251
Short name T21
Test name
Test status
Simulation time 172024468 ps
CPU time 8.86 seconds
Started Aug 15 06:02:04 PM PDT 24
Finished Aug 15 06:02:13 PM PDT 24
Peak memory 211608 kb
Host smart-e2e3572b-a5bc-42a6-8e4e-325959ec0eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424619251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3424619251
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.935864698
Short name T39
Test name
Test status
Simulation time 388712693 ps
CPU time 5.41 seconds
Started Aug 15 06:02:05 PM PDT 24
Finished Aug 15 06:02:10 PM PDT 24
Peak memory 211144 kb
Host smart-153e1d59-59a7-4d5e-949b-59a0f4b22a21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=935864698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.935864698
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1082745212
Short name T119
Test name
Test status
Simulation time 620614234 ps
CPU time 7.4 seconds
Started Aug 15 06:02:03 PM PDT 24
Finished Aug 15 06:02:10 PM PDT 24
Peak memory 211652 kb
Host smart-e52192e6-f8ad-4a5c-9088-3588a8c8b230
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082745212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1082745212
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3416165735
Short name T148
Test name
Test status
Simulation time 347296011 ps
CPU time 4.13 seconds
Started Aug 15 06:02:04 PM PDT 24
Finished Aug 15 06:02:09 PM PDT 24
Peak memory 211152 kb
Host smart-85d5aa2c-e390-42e4-91dd-aa750b22c2d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416165735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3416165735
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2969604679
Short name T103
Test name
Test status
Simulation time 14293848148 ps
CPU time 65.71 seconds
Started Aug 15 06:02:04 PM PDT 24
Finished Aug 15 06:03:10 PM PDT 24
Peak memory 227660 kb
Host smart-bdf84d53-e42e-43a3-acc9-1f3e7864439a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969604679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2969604679
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2488356488
Short name T354
Test name
Test status
Simulation time 173691763 ps
CPU time 9.58 seconds
Started Aug 15 06:02:05 PM PDT 24
Finished Aug 15 06:02:15 PM PDT 24
Peak memory 211656 kb
Host smart-da8c5ef9-32d2-4bd7-b2f9-ed3ea89398a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488356488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2488356488
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2864917509
Short name T233
Test name
Test status
Simulation time 526580874 ps
CPU time 6 seconds
Started Aug 15 06:02:04 PM PDT 24
Finished Aug 15 06:02:11 PM PDT 24
Peak memory 211132 kb
Host smart-1a18eba2-4b6d-4304-9533-c1726771c251
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2864917509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2864917509
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.593865057
Short name T187
Test name
Test status
Simulation time 1245114685 ps
CPU time 19.3 seconds
Started Aug 15 06:02:04 PM PDT 24
Finished Aug 15 06:02:24 PM PDT 24
Peak memory 216180 kb
Host smart-33ebdea8-6a33-4a69-a105-9f7484b089d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593865057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.593865057
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3400635101
Short name T271
Test name
Test status
Simulation time 7416634025 ps
CPU time 260.96 seconds
Started Aug 15 06:02:02 PM PDT 24
Finished Aug 15 06:06:23 PM PDT 24
Peak memory 221816 kb
Host smart-48076261-5959-4c38-9ab2-ecca121ea515
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400635101 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3400635101
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2897465954
Short name T260
Test name
Test status
Simulation time 1184961297 ps
CPU time 4.08 seconds
Started Aug 15 06:02:10 PM PDT 24
Finished Aug 15 06:02:14 PM PDT 24
Peak memory 211064 kb
Host smart-aaaba848-6ac3-4bd6-bd59-5e73fe74c2d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897465954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2897465954
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1126383817
Short name T164
Test name
Test status
Simulation time 3237396604 ps
CPU time 155.29 seconds
Started Aug 15 06:02:05 PM PDT 24
Finished Aug 15 06:04:40 PM PDT 24
Peak memory 237724 kb
Host smart-d7bcc541-b43c-4cef-a403-dfea95a6d2b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126383817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1126383817
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.319746133
Short name T289
Test name
Test status
Simulation time 544957925 ps
CPU time 10.65 seconds
Started Aug 15 06:02:03 PM PDT 24
Finished Aug 15 06:02:14 PM PDT 24
Peak memory 211600 kb
Host smart-1b7f20aa-1696-4860-a3c3-1efb2b66f9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319746133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.319746133
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3649980764
Short name T332
Test name
Test status
Simulation time 568379336 ps
CPU time 6.28 seconds
Started Aug 15 06:02:03 PM PDT 24
Finished Aug 15 06:02:10 PM PDT 24
Peak memory 211124 kb
Host smart-5fcd5aa2-7f36-40d4-a381-42831a8cf56e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3649980764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3649980764
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.745068905
Short name T142
Test name
Test status
Simulation time 1722817549 ps
CPU time 18.79 seconds
Started Aug 15 06:02:03 PM PDT 24
Finished Aug 15 06:02:22 PM PDT 24
Peak memory 214624 kb
Host smart-694fe370-ea47-44ff-9f89-5e18b817c9a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745068905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.745068905
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2350557362
Short name T234
Test name
Test status
Simulation time 2840865686 ps
CPU time 190.19 seconds
Started Aug 15 06:02:06 PM PDT 24
Finished Aug 15 06:05:16 PM PDT 24
Peak memory 222400 kb
Host smart-00f488d7-83a1-4839-b8ba-da272e76f8f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350557362 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.2350557362
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2841376119
Short name T308
Test name
Test status
Simulation time 252806127 ps
CPU time 4.93 seconds
Started Aug 15 06:02:11 PM PDT 24
Finished Aug 15 06:02:16 PM PDT 24
Peak memory 211144 kb
Host smart-652b67c8-0113-4653-bc39-8f6ade6c8e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841376119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2841376119
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2476446076
Short name T229
Test name
Test status
Simulation time 3657116446 ps
CPU time 61.93 seconds
Started Aug 15 06:02:11 PM PDT 24
Finished Aug 15 06:03:13 PM PDT 24
Peak memory 228452 kb
Host smart-abe86390-2f90-49fe-8af0-60e4e1b01dff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476446076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2476446076
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.413075063
Short name T323
Test name
Test status
Simulation time 598413508 ps
CPU time 8.94 seconds
Started Aug 15 06:02:11 PM PDT 24
Finished Aug 15 06:02:20 PM PDT 24
Peak memory 211536 kb
Host smart-399e18d9-49a6-4f3c-8e9f-a0afe75fe9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413075063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.413075063
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.871528916
Short name T18
Test name
Test status
Simulation time 569206142 ps
CPU time 6.44 seconds
Started Aug 15 06:02:14 PM PDT 24
Finished Aug 15 06:02:20 PM PDT 24
Peak memory 211140 kb
Host smart-d3569fb2-7173-4798-878d-89a3690c172d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=871528916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.871528916
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.894348314
Short name T116
Test name
Test status
Simulation time 214781916 ps
CPU time 7.17 seconds
Started Aug 15 06:02:11 PM PDT 24
Finished Aug 15 06:02:19 PM PDT 24
Peak memory 211892 kb
Host smart-4b86d761-6987-4b1d-94f6-1bb1622b4a1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894348314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.894348314
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3719425019
Short name T107
Test name
Test status
Simulation time 8550846063 ps
CPU time 264.04 seconds
Started Aug 15 06:02:11 PM PDT 24
Finished Aug 15 06:06:35 PM PDT 24
Peak memory 227936 kb
Host smart-dbbbf262-11e7-45b4-8b98-fe9dc92a7dcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719425019 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.3719425019
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3318421703
Short name T248
Test name
Test status
Simulation time 735230293 ps
CPU time 4.9 seconds
Started Aug 15 06:01:18 PM PDT 24
Finished Aug 15 06:01:23 PM PDT 24
Peak memory 211124 kb
Host smart-9fba1c67-2bef-41f9-8b4d-bc351fc9acfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318421703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3318421703
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.502140552
Short name T340
Test name
Test status
Simulation time 8644998626 ps
CPU time 100.33 seconds
Started Aug 15 06:01:14 PM PDT 24
Finished Aug 15 06:02:55 PM PDT 24
Peak memory 233568 kb
Host smart-95895dfe-07bc-490e-95c7-692348371da0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502140552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.502140552
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1096762237
Short name T118
Test name
Test status
Simulation time 725792989 ps
CPU time 9.35 seconds
Started Aug 15 06:01:13 PM PDT 24
Finished Aug 15 06:01:23 PM PDT 24
Peak memory 211508 kb
Host smart-7fa1d5e7-b49c-46fb-8c1c-68413d11d1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096762237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1096762237
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2404412628
Short name T286
Test name
Test status
Simulation time 532477702 ps
CPU time 6.12 seconds
Started Aug 15 06:01:13 PM PDT 24
Finished Aug 15 06:01:19 PM PDT 24
Peak memory 211136 kb
Host smart-86f8c078-089a-4d95-b697-3e86ba92ff7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2404412628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2404412628
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.930854904
Short name T37
Test name
Test status
Simulation time 828045665 ps
CPU time 101.19 seconds
Started Aug 15 06:01:19 PM PDT 24
Finished Aug 15 06:03:00 PM PDT 24
Peak memory 236628 kb
Host smart-eba582a3-4dff-4473-91cf-03b668749576
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930854904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.930854904
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1535664215
Short name T217
Test name
Test status
Simulation time 390836172 ps
CPU time 5.47 seconds
Started Aug 15 06:01:14 PM PDT 24
Finished Aug 15 06:01:19 PM PDT 24
Peak memory 212624 kb
Host smart-1ae6a434-1f3a-40db-86eb-48a33822abb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535664215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1535664215
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2096916987
Short name T235
Test name
Test status
Simulation time 1080880528 ps
CPU time 11.82 seconds
Started Aug 15 06:01:15 PM PDT 24
Finished Aug 15 06:01:27 PM PDT 24
Peak memory 213368 kb
Host smart-5fdb3ebb-cd70-4153-966d-3d9cd4183358
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096916987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2096916987
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2274728936
Short name T341
Test name
Test status
Simulation time 8668864971 ps
CPU time 160.1 seconds
Started Aug 15 06:01:16 PM PDT 24
Finished Aug 15 06:03:56 PM PDT 24
Peak memory 233128 kb
Host smart-264e0314-d568-4469-a779-bf0402b10b89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274728936 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2274728936
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.4249926692
Short name T313
Test name
Test status
Simulation time 333565149 ps
CPU time 4.02 seconds
Started Aug 15 06:02:14 PM PDT 24
Finished Aug 15 06:02:18 PM PDT 24
Peak memory 211152 kb
Host smart-fa3e7a85-6e95-4adc-8b70-b53a94f63e68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249926692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.4249926692
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.883553571
Short name T106
Test name
Test status
Simulation time 36771588321 ps
CPU time 190.19 seconds
Started Aug 15 06:02:11 PM PDT 24
Finished Aug 15 06:05:21 PM PDT 24
Peak memory 232464 kb
Host smart-76029d9e-6557-41f3-a4ad-6184350667b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883553571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.883553571
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3675169147
Short name T156
Test name
Test status
Simulation time 2071734602 ps
CPU time 9.02 seconds
Started Aug 15 06:02:11 PM PDT 24
Finished Aug 15 06:02:20 PM PDT 24
Peak memory 211640 kb
Host smart-9f831c03-39e4-46d8-991d-90efb6abd7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675169147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3675169147
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.4002776750
Short name T293
Test name
Test status
Simulation time 101121601 ps
CPU time 5.52 seconds
Started Aug 15 06:02:12 PM PDT 24
Finished Aug 15 06:02:18 PM PDT 24
Peak memory 211144 kb
Host smart-5ad729ea-75a9-4831-b3ca-1eafe0af4dc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4002776750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.4002776750
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3711576661
Short name T114
Test name
Test status
Simulation time 1609970795 ps
CPU time 19.44 seconds
Started Aug 15 06:02:09 PM PDT 24
Finished Aug 15 06:02:29 PM PDT 24
Peak memory 214700 kb
Host smart-2c774181-5d74-4131-bcdd-9aac48458804
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711576661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3711576661
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.462498789
Short name T275
Test name
Test status
Simulation time 7827229470 ps
CPU time 77.14 seconds
Started Aug 15 06:02:13 PM PDT 24
Finished Aug 15 06:03:31 PM PDT 24
Peak memory 230364 kb
Host smart-38b6ea8f-1b84-458b-81f9-53576ee78b56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462498789 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.462498789
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1502106023
Short name T255
Test name
Test status
Simulation time 416712329 ps
CPU time 4.16 seconds
Started Aug 15 06:02:12 PM PDT 24
Finished Aug 15 06:02:16 PM PDT 24
Peak memory 211104 kb
Host smart-f9ddecc1-a8f2-4163-9620-5bf070e749e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502106023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1502106023
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.999158684
Short name T317
Test name
Test status
Simulation time 6604458617 ps
CPU time 94.66 seconds
Started Aug 15 06:02:10 PM PDT 24
Finished Aug 15 06:03:45 PM PDT 24
Peak memory 224476 kb
Host smart-bef49e34-c2c0-40f3-8013-ecd2aa171dba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999158684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.999158684
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1084647538
Short name T263
Test name
Test status
Simulation time 260882444 ps
CPU time 10.7 seconds
Started Aug 15 06:02:12 PM PDT 24
Finished Aug 15 06:02:23 PM PDT 24
Peak memory 211108 kb
Host smart-08811d40-f576-4013-90ea-be598d6aad11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084647538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1084647538
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1510660623
Short name T273
Test name
Test status
Simulation time 467283797 ps
CPU time 5.46 seconds
Started Aug 15 06:02:09 PM PDT 24
Finished Aug 15 06:02:15 PM PDT 24
Peak memory 211108 kb
Host smart-b2ff621d-adfc-46fa-8588-6fb63a0ca638
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1510660623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1510660623
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.522203947
Short name T305
Test name
Test status
Simulation time 286957256 ps
CPU time 14.59 seconds
Started Aug 15 06:02:11 PM PDT 24
Finished Aug 15 06:02:26 PM PDT 24
Peak memory 216552 kb
Host smart-37738632-68f0-4929-aec2-bc36642cc538
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522203947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.522203947
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1396627010
Short name T241
Test name
Test status
Simulation time 2381153084 ps
CPU time 160.52 seconds
Started Aug 15 06:02:12 PM PDT 24
Finished Aug 15 06:04:53 PM PDT 24
Peak memory 222116 kb
Host smart-23b7eccb-5191-4ed4-b761-45c23622ecc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396627010 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.1396627010
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1007644568
Short name T264
Test name
Test status
Simulation time 89283109 ps
CPU time 4.06 seconds
Started Aug 15 06:02:11 PM PDT 24
Finished Aug 15 06:02:15 PM PDT 24
Peak memory 211052 kb
Host smart-fd3e7938-ecac-40af-ae84-a8ccfa25766c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007644568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1007644568
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3908878693
Short name T336
Test name
Test status
Simulation time 5374885290 ps
CPU time 140.71 seconds
Started Aug 15 06:02:14 PM PDT 24
Finished Aug 15 06:04:34 PM PDT 24
Peak memory 232720 kb
Host smart-a31f016e-6211-4510-a9f6-8a9298f88d7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908878693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3908878693
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2222275062
Short name T285
Test name
Test status
Simulation time 274783333 ps
CPU time 10.36 seconds
Started Aug 15 06:02:12 PM PDT 24
Finished Aug 15 06:02:23 PM PDT 24
Peak memory 211108 kb
Host smart-cfd54712-baa3-4f82-938c-5e27a5d007ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222275062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2222275062
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.789713707
Short name T147
Test name
Test status
Simulation time 529550209 ps
CPU time 5.94 seconds
Started Aug 15 06:02:11 PM PDT 24
Finished Aug 15 06:02:17 PM PDT 24
Peak memory 211168 kb
Host smart-74c2dd84-703e-44b3-8fb7-c993fb5c6495
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=789713707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.789713707
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3356473550
Short name T316
Test name
Test status
Simulation time 583108413 ps
CPU time 13.31 seconds
Started Aug 15 06:02:12 PM PDT 24
Finished Aug 15 06:02:26 PM PDT 24
Peak memory 213228 kb
Host smart-36b27697-13a7-4b07-897b-2ec0a56f67ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356473550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3356473550
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2379188837
Short name T108
Test name
Test status
Simulation time 2148045427 ps
CPU time 119.28 seconds
Started Aug 15 06:02:14 PM PDT 24
Finished Aug 15 06:04:14 PM PDT 24
Peak memory 220636 kb
Host smart-c9ee9510-d8c9-444c-a2e6-5e00e59c2435
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379188837 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2379188837
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2975722966
Short name T335
Test name
Test status
Simulation time 498030239 ps
CPU time 5.06 seconds
Started Aug 15 06:02:11 PM PDT 24
Finished Aug 15 06:02:16 PM PDT 24
Peak memory 211152 kb
Host smart-9ff2ec66-3e30-4731-a55e-16c89e3aa2c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975722966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2975722966
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.661586331
Short name T355
Test name
Test status
Simulation time 14519244416 ps
CPU time 147.35 seconds
Started Aug 15 06:02:11 PM PDT 24
Finished Aug 15 06:04:38 PM PDT 24
Peak memory 237032 kb
Host smart-019e5f55-bf6b-4b07-87b8-4639e1ea99d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661586331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.661586331
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4110186693
Short name T143
Test name
Test status
Simulation time 169997784 ps
CPU time 8.93 seconds
Started Aug 15 06:02:13 PM PDT 24
Finished Aug 15 06:02:22 PM PDT 24
Peak memory 211540 kb
Host smart-5ae2d22b-610f-44ff-970e-76912123c98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110186693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4110186693
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3015215621
Short name T126
Test name
Test status
Simulation time 282466779 ps
CPU time 6.11 seconds
Started Aug 15 06:02:13 PM PDT 24
Finished Aug 15 06:02:19 PM PDT 24
Peak memory 211360 kb
Host smart-4877ae73-504b-4cf5-b6a3-d868cb665a98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3015215621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3015215621
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.4082934058
Short name T45
Test name
Test status
Simulation time 1066633569 ps
CPU time 25.22 seconds
Started Aug 15 06:02:10 PM PDT 24
Finished Aug 15 06:02:35 PM PDT 24
Peak memory 215888 kb
Host smart-8036710a-7238-41f2-a963-09088746007a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082934058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.4082934058
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2403585172
Short name T182
Test name
Test status
Simulation time 3351272202 ps
CPU time 57.7 seconds
Started Aug 15 06:02:12 PM PDT 24
Finished Aug 15 06:03:10 PM PDT 24
Peak memory 221280 kb
Host smart-8e138979-b157-43df-b474-28e4b3d03357
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403585172 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.2403585172
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3241003313
Short name T210
Test name
Test status
Simulation time 126669658 ps
CPU time 5.03 seconds
Started Aug 15 06:02:18 PM PDT 24
Finished Aug 15 06:02:23 PM PDT 24
Peak memory 211088 kb
Host smart-695d710e-030a-450f-9eae-f7640cf486ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241003313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3241003313
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1376000768
Short name T144
Test name
Test status
Simulation time 2050959507 ps
CPU time 61.8 seconds
Started Aug 15 06:02:11 PM PDT 24
Finished Aug 15 06:03:13 PM PDT 24
Peak memory 236628 kb
Host smart-39d7f091-078b-496d-b63d-f9fc7b2f24b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376000768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1376000768
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1725830819
Short name T188
Test name
Test status
Simulation time 170465161 ps
CPU time 9.16 seconds
Started Aug 15 06:02:10 PM PDT 24
Finished Aug 15 06:02:19 PM PDT 24
Peak memory 211652 kb
Host smart-f742fde2-5768-42ef-b14b-bd338ed8fb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725830819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1725830819
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.596156386
Short name T282
Test name
Test status
Simulation time 141184482 ps
CPU time 5.98 seconds
Started Aug 15 06:02:10 PM PDT 24
Finished Aug 15 06:02:16 PM PDT 24
Peak memory 211152 kb
Host smart-763894af-396a-40df-a92e-646febad9327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=596156386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.596156386
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1992809468
Short name T120
Test name
Test status
Simulation time 1280677552 ps
CPU time 11.73 seconds
Started Aug 15 06:02:11 PM PDT 24
Finished Aug 15 06:02:23 PM PDT 24
Peak memory 211560 kb
Host smart-a21ed62e-51f9-458b-83ae-0e3ef4698cfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992809468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1992809468
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3086666249
Short name T281
Test name
Test status
Simulation time 3944563046 ps
CPU time 256.89 seconds
Started Aug 15 06:02:18 PM PDT 24
Finished Aug 15 06:06:35 PM PDT 24
Peak memory 223012 kb
Host smart-d045c8aa-afbf-4aee-a1d4-383a68f122a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086666249 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3086666249
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.194876332
Short name T199
Test name
Test status
Simulation time 90753077 ps
CPU time 4.07 seconds
Started Aug 15 06:02:18 PM PDT 24
Finished Aug 15 06:02:22 PM PDT 24
Peak memory 211112 kb
Host smart-36d3c8f7-c337-4988-bf4c-b2b295e3c1d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194876332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.194876332
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1290983274
Short name T27
Test name
Test status
Simulation time 5087532883 ps
CPU time 103.3 seconds
Started Aug 15 06:02:16 PM PDT 24
Finished Aug 15 06:03:59 PM PDT 24
Peak memory 232612 kb
Host smart-8e38c4b5-42f1-4311-aea6-3beb7e603538
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290983274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1290983274
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2573970223
Short name T197
Test name
Test status
Simulation time 250679724 ps
CPU time 10.42 seconds
Started Aug 15 06:02:18 PM PDT 24
Finished Aug 15 06:02:28 PM PDT 24
Peak memory 211156 kb
Host smart-b5d9fd76-0812-4ad2-beb0-bd990d05f9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573970223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2573970223
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3470424468
Short name T132
Test name
Test status
Simulation time 2180641654 ps
CPU time 6.23 seconds
Started Aug 15 06:02:17 PM PDT 24
Finished Aug 15 06:02:24 PM PDT 24
Peak memory 211200 kb
Host smart-48be88c0-d0ee-4830-850a-9dcbcae4ab1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3470424468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3470424468
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3218000830
Short name T226
Test name
Test status
Simulation time 158289765 ps
CPU time 7.77 seconds
Started Aug 15 06:02:18 PM PDT 24
Finished Aug 15 06:02:26 PM PDT 24
Peak memory 211132 kb
Host smart-3d5144e8-131c-4a69-99db-90e0f4db3b86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218000830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3218000830
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3186278579
Short name T172
Test name
Test status
Simulation time 17930665779 ps
CPU time 187.11 seconds
Started Aug 15 06:02:16 PM PDT 24
Finished Aug 15 06:05:23 PM PDT 24
Peak memory 235660 kb
Host smart-e48722ba-1ebf-45c1-88e1-6d6bdc276031
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186278579 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.3186278579
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.429899857
Short name T324
Test name
Test status
Simulation time 460919490 ps
CPU time 4.84 seconds
Started Aug 15 06:02:18 PM PDT 24
Finished Aug 15 06:02:23 PM PDT 24
Peak memory 211080 kb
Host smart-b4e474f7-d30a-4895-9815-b31a4be4f818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429899857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.429899857
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3692021914
Short name T267
Test name
Test status
Simulation time 3643729455 ps
CPU time 83.96 seconds
Started Aug 15 06:02:16 PM PDT 24
Finished Aug 15 06:03:41 PM PDT 24
Peak memory 236984 kb
Host smart-66841a92-2352-416f-b4e3-edef904b9fdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692021914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3692021914
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2133790854
Short name T328
Test name
Test status
Simulation time 235993189 ps
CPU time 9.11 seconds
Started Aug 15 06:02:17 PM PDT 24
Finished Aug 15 06:02:27 PM PDT 24
Peak memory 211508 kb
Host smart-d1dbb4fe-880b-4c5f-bb70-9371579be8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133790854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2133790854
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1491251098
Short name T146
Test name
Test status
Simulation time 192119123 ps
CPU time 5.35 seconds
Started Aug 15 06:02:17 PM PDT 24
Finished Aug 15 06:02:23 PM PDT 24
Peak memory 211164 kb
Host smart-7743c7ac-3802-401a-9a13-799f91e5bae7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1491251098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1491251098
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1243933399
Short name T185
Test name
Test status
Simulation time 1315669318 ps
CPU time 11.14 seconds
Started Aug 15 06:02:25 PM PDT 24
Finished Aug 15 06:02:36 PM PDT 24
Peak memory 213960 kb
Host smart-efbf19c0-f1d2-4b57-99f5-1ec79dfe048c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243933399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1243933399
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1441031827
Short name T236
Test name
Test status
Simulation time 1390518438 ps
CPU time 4.76 seconds
Started Aug 15 06:02:16 PM PDT 24
Finished Aug 15 06:02:21 PM PDT 24
Peak memory 211140 kb
Host smart-79220cc2-0625-48cd-baf3-7abba90bb984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441031827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1441031827
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3029335518
Short name T343
Test name
Test status
Simulation time 1179511980 ps
CPU time 55.98 seconds
Started Aug 15 06:02:19 PM PDT 24
Finished Aug 15 06:03:16 PM PDT 24
Peak memory 211308 kb
Host smart-4e01bd9b-3407-44d6-8ab9-10dc35c1a00c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029335518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3029335518
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1222003906
Short name T136
Test name
Test status
Simulation time 1106696476 ps
CPU time 9.15 seconds
Started Aug 15 06:02:17 PM PDT 24
Finished Aug 15 06:02:26 PM PDT 24
Peak memory 211508 kb
Host smart-e52699f1-97cd-49c2-9579-8d55d022fb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222003906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1222003906
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.387054107
Short name T198
Test name
Test status
Simulation time 267568430 ps
CPU time 6.13 seconds
Started Aug 15 06:02:18 PM PDT 24
Finished Aug 15 06:02:24 PM PDT 24
Peak memory 211148 kb
Host smart-17ad5fa6-9e21-4150-8124-4bd7dc13d06f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=387054107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.387054107
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3303347047
Short name T135
Test name
Test status
Simulation time 565641500 ps
CPU time 6.5 seconds
Started Aug 15 06:02:17 PM PDT 24
Finished Aug 15 06:02:23 PM PDT 24
Peak memory 211352 kb
Host smart-9d12e2c4-7e48-4cd3-b898-133c60bbb7a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303347047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3303347047
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.832680464
Short name T346
Test name
Test status
Simulation time 3213592260 ps
CPU time 100.84 seconds
Started Aug 15 06:02:17 PM PDT 24
Finished Aug 15 06:03:58 PM PDT 24
Peak memory 221208 kb
Host smart-6018a66f-43b1-40ca-8d31-2ed4a41e8a61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832680464 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.832680464
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.855065510
Short name T214
Test name
Test status
Simulation time 168720522 ps
CPU time 4 seconds
Started Aug 15 06:02:16 PM PDT 24
Finished Aug 15 06:02:21 PM PDT 24
Peak memory 211128 kb
Host smart-6cb1c8ed-2b62-4342-9026-85067e31ab8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855065510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.855065510
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1529948286
Short name T319
Test name
Test status
Simulation time 20274336452 ps
CPU time 92.21 seconds
Started Aug 15 06:02:17 PM PDT 24
Finished Aug 15 06:03:50 PM PDT 24
Peak memory 228392 kb
Host smart-b3f2fbb0-581a-4afc-a210-1d3540cf9a7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529948286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1529948286
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3968673306
Short name T128
Test name
Test status
Simulation time 168613134 ps
CPU time 8.98 seconds
Started Aug 15 06:02:20 PM PDT 24
Finished Aug 15 06:02:29 PM PDT 24
Peak memory 211440 kb
Host smart-e8446916-25c9-4796-9dcc-619cdfba2975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968673306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3968673306
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.270189411
Short name T329
Test name
Test status
Simulation time 583428165 ps
CPU time 5.32 seconds
Started Aug 15 06:02:16 PM PDT 24
Finished Aug 15 06:02:22 PM PDT 24
Peak memory 211172 kb
Host smart-9005fba4-d291-40b1-ab2d-127395593547
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=270189411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.270189411
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3153667665
Short name T88
Test name
Test status
Simulation time 7850229049 ps
CPU time 17.35 seconds
Started Aug 15 06:02:17 PM PDT 24
Finished Aug 15 06:02:34 PM PDT 24
Peak memory 214344 kb
Host smart-9ec1d944-4b69-40a2-827a-dd9240cb4022
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153667665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3153667665
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1657652930
Short name T203
Test name
Test status
Simulation time 19095326777 ps
CPU time 93.86 seconds
Started Aug 15 06:02:18 PM PDT 24
Finished Aug 15 06:03:52 PM PDT 24
Peak memory 232952 kb
Host smart-41b9737e-db00-4ec5-b8c2-ce7df458d712
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657652930 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.1657652930
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2722335726
Short name T274
Test name
Test status
Simulation time 626911340 ps
CPU time 4.77 seconds
Started Aug 15 06:02:17 PM PDT 24
Finished Aug 15 06:02:22 PM PDT 24
Peak memory 211136 kb
Host smart-5a2d9b8d-04bc-499d-8b0c-541ef9a60ded
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722335726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2722335726
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3326412139
Short name T278
Test name
Test status
Simulation time 10965270606 ps
CPU time 135.7 seconds
Started Aug 15 06:02:17 PM PDT 24
Finished Aug 15 06:04:33 PM PDT 24
Peak memory 237652 kb
Host smart-4ea3f41f-eb73-4b9f-a00a-c74b75d626aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326412139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3326412139
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2026942972
Short name T193
Test name
Test status
Simulation time 2789871250 ps
CPU time 8.74 seconds
Started Aug 15 06:02:16 PM PDT 24
Finished Aug 15 06:02:25 PM PDT 24
Peak memory 211560 kb
Host smart-ea677b6e-bbe7-482d-9b5f-d89935da67e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026942972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2026942972
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1225714607
Short name T258
Test name
Test status
Simulation time 93425404 ps
CPU time 5.15 seconds
Started Aug 15 06:02:17 PM PDT 24
Finished Aug 15 06:02:22 PM PDT 24
Peak memory 211148 kb
Host smart-74cf4a0b-4257-4319-ab0d-ee5fd3044aea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1225714607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1225714607
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2632778059
Short name T339
Test name
Test status
Simulation time 1318800816 ps
CPU time 9.21 seconds
Started Aug 15 06:02:21 PM PDT 24
Finished Aug 15 06:02:30 PM PDT 24
Peak memory 211804 kb
Host smart-37599ea5-fa05-4491-9e54-0bfefc9d4d05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632778059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2632778059
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2145563114
Short name T151
Test name
Test status
Simulation time 131843548 ps
CPU time 4.85 seconds
Started Aug 15 06:01:28 PM PDT 24
Finished Aug 15 06:01:33 PM PDT 24
Peak memory 211124 kb
Host smart-7f312aa3-c099-4528-a80b-c57b12968851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145563114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2145563114
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1577366446
Short name T240
Test name
Test status
Simulation time 6440179918 ps
CPU time 87.81 seconds
Started Aug 15 06:01:22 PM PDT 24
Finished Aug 15 06:02:50 PM PDT 24
Peak memory 237144 kb
Host smart-4a69ad88-13fc-48ca-8af6-376a686a41da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577366446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1577366446
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2693482292
Short name T20
Test name
Test status
Simulation time 341157332 ps
CPU time 8.87 seconds
Started Aug 15 06:01:23 PM PDT 24
Finished Aug 15 06:01:32 PM PDT 24
Peak memory 211516 kb
Host smart-663fc527-4948-4867-8955-970d0b25fa33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693482292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2693482292
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1877557515
Short name T87
Test name
Test status
Simulation time 275669573 ps
CPU time 6.02 seconds
Started Aug 15 06:01:16 PM PDT 24
Finished Aug 15 06:01:22 PM PDT 24
Peak memory 211152 kb
Host smart-7aefe872-b471-444d-b4fb-91581967b593
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1877557515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1877557515
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.947919472
Short name T113
Test name
Test status
Simulation time 562194748 ps
CPU time 6.04 seconds
Started Aug 15 06:01:20 PM PDT 24
Finished Aug 15 06:01:26 PM PDT 24
Peak memory 211180 kb
Host smart-9f2464d3-33d5-4b0c-a36d-7b906283964a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947919472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.947919472
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2313789377
Short name T111
Test name
Test status
Simulation time 581322501 ps
CPU time 16.36 seconds
Started Aug 15 06:01:21 PM PDT 24
Finished Aug 15 06:01:37 PM PDT 24
Peak memory 215192 kb
Host smart-b1c0d80c-aae1-4eb4-94e6-b8854c5e4433
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313789377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2313789377
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3603490917
Short name T334
Test name
Test status
Simulation time 14161828980 ps
CPU time 99.53 seconds
Started Aug 15 06:01:28 PM PDT 24
Finished Aug 15 06:03:07 PM PDT 24
Peak memory 232312 kb
Host smart-e850addd-b706-4a8a-8d0b-d17e3afc781c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603490917 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.3603490917
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.926659587
Short name T163
Test name
Test status
Simulation time 461575597 ps
CPU time 4.83 seconds
Started Aug 15 06:01:21 PM PDT 24
Finished Aug 15 06:01:26 PM PDT 24
Peak memory 211056 kb
Host smart-34a50503-67fa-4829-bd1f-2e55a658e5e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926659587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.926659587
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.106321820
Short name T29
Test name
Test status
Simulation time 3881446484 ps
CPU time 90.01 seconds
Started Aug 15 06:01:23 PM PDT 24
Finished Aug 15 06:02:53 PM PDT 24
Peak memory 211472 kb
Host smart-1cf6b6e0-e69f-4ab0-a3e4-0330669f8f1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106321820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.106321820
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3996667551
Short name T347
Test name
Test status
Simulation time 521306307 ps
CPU time 10.41 seconds
Started Aug 15 06:01:22 PM PDT 24
Finished Aug 15 06:01:33 PM PDT 24
Peak memory 211132 kb
Host smart-14bd0850-6ad6-4a0c-abc0-9e47643f8f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996667551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3996667551
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.623627465
Short name T321
Test name
Test status
Simulation time 195656568 ps
CPU time 5.39 seconds
Started Aug 15 06:01:21 PM PDT 24
Finished Aug 15 06:01:27 PM PDT 24
Peak memory 211172 kb
Host smart-c07cdf4c-695b-44b7-b5ae-0faea5be7c15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=623627465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.623627465
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.4023710697
Short name T140
Test name
Test status
Simulation time 96651359 ps
CPU time 5.66 seconds
Started Aug 15 06:01:19 PM PDT 24
Finished Aug 15 06:01:25 PM PDT 24
Peak memory 212376 kb
Host smart-4909f529-7891-4bb1-95d0-8a22d04224e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023710697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.4023710697
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1877068599
Short name T4
Test name
Test status
Simulation time 201290638 ps
CPU time 12.96 seconds
Started Aug 15 06:01:20 PM PDT 24
Finished Aug 15 06:01:33 PM PDT 24
Peak memory 211596 kb
Host smart-956018a8-e4ff-41e4-90c0-f220520c5c4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877068599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1877068599
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.24172013
Short name T247
Test name
Test status
Simulation time 1018145074 ps
CPU time 49.82 seconds
Started Aug 15 06:01:29 PM PDT 24
Finished Aug 15 06:02:19 PM PDT 24
Peak memory 220060 kb
Host smart-edf1d10a-0f4a-44bb-88f7-1bd165a5fd5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24172013 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.24172013
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3501780322
Short name T246
Test name
Test status
Simulation time 88914894 ps
CPU time 3.96 seconds
Started Aug 15 06:01:19 PM PDT 24
Finished Aug 15 06:01:23 PM PDT 24
Peak memory 211120 kb
Host smart-ca804c83-dc38-49b4-afe2-f652ca9e4392
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501780322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3501780322
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1006389305
Short name T195
Test name
Test status
Simulation time 8141878106 ps
CPU time 112.01 seconds
Started Aug 15 06:01:20 PM PDT 24
Finished Aug 15 06:03:13 PM PDT 24
Peak memory 237688 kb
Host smart-bcf4811a-4d7e-43cd-bd6a-012f946730f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006389305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1006389305
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2302737485
Short name T173
Test name
Test status
Simulation time 976669429 ps
CPU time 9.15 seconds
Started Aug 15 06:01:21 PM PDT 24
Finished Aug 15 06:01:31 PM PDT 24
Peak memory 211544 kb
Host smart-146c98d7-f45f-43a9-8b42-e5dce0868c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302737485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2302737485
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.942292789
Short name T134
Test name
Test status
Simulation time 139310092 ps
CPU time 5.97 seconds
Started Aug 15 06:01:19 PM PDT 24
Finished Aug 15 06:01:25 PM PDT 24
Peak memory 211160 kb
Host smart-2258f063-f1fc-4273-8d54-8febe097d2aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=942292789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.942292789
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3982255991
Short name T171
Test name
Test status
Simulation time 741679670 ps
CPU time 5.96 seconds
Started Aug 15 06:01:18 PM PDT 24
Finished Aug 15 06:01:24 PM PDT 24
Peak memory 211116 kb
Host smart-eb3aeb21-b4e5-4cee-9a11-dce9167381e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982255991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3982255991
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1816660216
Short name T104
Test name
Test status
Simulation time 1314138151 ps
CPU time 15.98 seconds
Started Aug 15 06:01:23 PM PDT 24
Finished Aug 15 06:01:39 PM PDT 24
Peak memory 214276 kb
Host smart-f6611a86-da4b-4517-b48a-593cf750dd07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816660216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1816660216
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2163365033
Short name T351
Test name
Test status
Simulation time 19922555204 ps
CPU time 339.12 seconds
Started Aug 15 06:01:23 PM PDT 24
Finished Aug 15 06:07:02 PM PDT 24
Peak memory 235704 kb
Host smart-7fd54cb7-12ec-49fc-a7f6-82f182e38e18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163365033 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.2163365033
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.910189446
Short name T353
Test name
Test status
Simulation time 131924802 ps
CPU time 4.91 seconds
Started Aug 15 06:01:29 PM PDT 24
Finished Aug 15 06:01:34 PM PDT 24
Peak memory 211128 kb
Host smart-72c8f1e1-d5bc-4502-a8c0-523373e2c79c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910189446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.910189446
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1651905553
Short name T219
Test name
Test status
Simulation time 11631853191 ps
CPU time 119.47 seconds
Started Aug 15 06:01:33 PM PDT 24
Finished Aug 15 06:03:32 PM PDT 24
Peak memory 212376 kb
Host smart-8adc6e5e-f1d4-4416-9bf9-670a66bfd2a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651905553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1651905553
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1020912853
Short name T216
Test name
Test status
Simulation time 1657977979 ps
CPU time 10.68 seconds
Started Aug 15 06:01:27 PM PDT 24
Finished Aug 15 06:01:38 PM PDT 24
Peak memory 211356 kb
Host smart-e6d25092-86d0-48e6-bd2b-4105b7f47f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020912853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1020912853
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3042814253
Short name T301
Test name
Test status
Simulation time 272389229 ps
CPU time 6.13 seconds
Started Aug 15 06:01:27 PM PDT 24
Finished Aug 15 06:01:33 PM PDT 24
Peak memory 211132 kb
Host smart-26a2ce9c-283e-43c9-8c37-fd108e0a4510
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3042814253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3042814253
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.550318209
Short name T277
Test name
Test status
Simulation time 768224083 ps
CPU time 6.3 seconds
Started Aug 15 06:01:28 PM PDT 24
Finished Aug 15 06:01:34 PM PDT 24
Peak memory 211300 kb
Host smart-78b4f983-e6f2-45c7-a256-182995ca8af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550318209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.550318209
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2984647213
Short name T232
Test name
Test status
Simulation time 532851822 ps
CPU time 8.98 seconds
Started Aug 15 06:01:30 PM PDT 24
Finished Aug 15 06:01:39 PM PDT 24
Peak memory 210992 kb
Host smart-21fb1e8e-13f8-4d57-b765-2f6671261f71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984647213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2984647213
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.542331091
Short name T14
Test name
Test status
Simulation time 681096161 ps
CPU time 28.86 seconds
Started Aug 15 06:01:29 PM PDT 24
Finished Aug 15 06:01:58 PM PDT 24
Peak memory 219356 kb
Host smart-18fbc454-cd5c-4faf-bcea-362254b595a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542331091 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.542331091
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2380517969
Short name T261
Test name
Test status
Simulation time 127433797 ps
CPU time 4.86 seconds
Started Aug 15 06:01:28 PM PDT 24
Finished Aug 15 06:01:33 PM PDT 24
Peak memory 211152 kb
Host smart-634e1bbc-69ff-4110-a308-d267bfbc94a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380517969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2380517969
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.803743387
Short name T26
Test name
Test status
Simulation time 1602435204 ps
CPU time 64.87 seconds
Started Aug 15 06:01:27 PM PDT 24
Finished Aug 15 06:02:32 PM PDT 24
Peak memory 236572 kb
Host smart-e6aebed9-7414-47b2-bf09-1635e7de165d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803743387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.803743387
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1155760909
Short name T141
Test name
Test status
Simulation time 169941283 ps
CPU time 9.21 seconds
Started Aug 15 06:01:28 PM PDT 24
Finished Aug 15 06:01:37 PM PDT 24
Peak memory 211548 kb
Host smart-9f3bb3ba-c20d-4843-a02d-7a412eb50ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155760909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1155760909
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3951830035
Short name T296
Test name
Test status
Simulation time 141487176 ps
CPU time 6.22 seconds
Started Aug 15 06:01:26 PM PDT 24
Finished Aug 15 06:01:32 PM PDT 24
Peak memory 211168 kb
Host smart-2344e0cb-0788-4989-9d3e-a1511c082c23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3951830035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3951830035
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2235802683
Short name T110
Test name
Test status
Simulation time 522335087 ps
CPU time 5.87 seconds
Started Aug 15 06:01:30 PM PDT 24
Finished Aug 15 06:01:35 PM PDT 24
Peak memory 211132 kb
Host smart-0a441712-95d5-4b75-8c4d-3f4bb71a64ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235802683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2235802683
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1298635093
Short name T38
Test name
Test status
Simulation time 156288938 ps
CPU time 10.54 seconds
Started Aug 15 06:01:29 PM PDT 24
Finished Aug 15 06:01:39 PM PDT 24
Peak memory 211120 kb
Host smart-60e27c3a-b49e-4c65-8504-2ec7233e4c75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298635093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1298635093
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3813223459
Short name T342
Test name
Test status
Simulation time 3678078849 ps
CPU time 36.92 seconds
Started Aug 15 06:01:27 PM PDT 24
Finished Aug 15 06:02:04 PM PDT 24
Peak memory 227520 kb
Host smart-389abff0-86f4-42f2-865c-a3c91d678f9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813223459 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3813223459
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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