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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.41 96.89 92.13 97.67 100.00 98.28 98.05 98.83


Total test records in report: 453
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T306 /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2828019685 Aug 17 06:38:45 PM PDT 24 Aug 17 06:42:52 PM PDT 24 13149885631 ps
T307 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1960597010 Aug 17 06:39:13 PM PDT 24 Aug 17 06:39:18 PM PDT 24 141225118 ps
T308 /workspace/coverage/default/25.rom_ctrl_stress_all.429091581 Aug 17 06:38:57 PM PDT 24 Aug 17 06:39:19 PM PDT 24 1639532293 ps
T309 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1117814883 Aug 17 06:38:45 PM PDT 24 Aug 17 06:38:51 PM PDT 24 141753500 ps
T310 /workspace/coverage/default/48.rom_ctrl_stress_all.2208332244 Aug 17 06:39:28 PM PDT 24 Aug 17 06:39:37 PM PDT 24 610840534 ps
T311 /workspace/coverage/default/19.rom_ctrl_stress_all.2778710763 Aug 17 06:39:09 PM PDT 24 Aug 17 06:39:22 PM PDT 24 200395816 ps
T312 /workspace/coverage/default/30.rom_ctrl_stress_all.3192682061 Aug 17 06:39:30 PM PDT 24 Aug 17 06:39:42 PM PDT 24 178381974 ps
T313 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2020114042 Aug 17 06:38:57 PM PDT 24 Aug 17 06:39:04 PM PDT 24 145062560 ps
T314 /workspace/coverage/default/12.rom_ctrl_alert_test.2463508773 Aug 17 06:38:53 PM PDT 24 Aug 17 06:38:59 PM PDT 24 737571184 ps
T315 /workspace/coverage/default/37.rom_ctrl_alert_test.3021021088 Aug 17 06:39:13 PM PDT 24 Aug 17 06:39:17 PM PDT 24 168345215 ps
T316 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3709424447 Aug 17 06:38:47 PM PDT 24 Aug 17 06:38:53 PM PDT 24 141528343 ps
T317 /workspace/coverage/default/9.rom_ctrl_alert_test.1050467435 Aug 17 06:38:45 PM PDT 24 Aug 17 06:38:50 PM PDT 24 428919601 ps
T318 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3526551054 Aug 17 06:38:57 PM PDT 24 Aug 17 06:40:41 PM PDT 24 1875515847 ps
T319 /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2841023850 Aug 17 06:39:31 PM PDT 24 Aug 17 06:41:34 PM PDT 24 8789102489 ps
T320 /workspace/coverage/default/7.rom_ctrl_alert_test.4189178051 Aug 17 06:38:42 PM PDT 24 Aug 17 06:38:46 PM PDT 24 88018507 ps
T321 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2770310842 Aug 17 06:39:13 PM PDT 24 Aug 17 06:39:23 PM PDT 24 1042770300 ps
T322 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3228246087 Aug 17 06:39:22 PM PDT 24 Aug 17 06:43:16 PM PDT 24 23083131801 ps
T323 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.605532800 Aug 17 06:38:57 PM PDT 24 Aug 17 06:40:53 PM PDT 24 1699005849 ps
T324 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3802110662 Aug 17 06:38:42 PM PDT 24 Aug 17 06:40:31 PM PDT 24 8313767272 ps
T325 /workspace/coverage/default/3.rom_ctrl_stress_all.1337837825 Aug 17 06:38:41 PM PDT 24 Aug 17 06:38:50 PM PDT 24 459025455 ps
T326 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3972446483 Aug 17 06:38:59 PM PDT 24 Aug 17 06:39:14 PM PDT 24 1037406381 ps
T327 /workspace/coverage/default/11.rom_ctrl_alert_test.3064212639 Aug 17 06:38:56 PM PDT 24 Aug 17 06:39:01 PM PDT 24 498558664 ps
T328 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3881178612 Aug 17 06:38:51 PM PDT 24 Aug 17 06:39:01 PM PDT 24 1038996712 ps
T329 /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3988150592 Aug 17 06:38:42 PM PDT 24 Aug 17 06:41:52 PM PDT 24 11627152330 ps
T330 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3089022525 Aug 17 06:39:18 PM PDT 24 Aug 17 06:40:14 PM PDT 24 3232680997 ps
T331 /workspace/coverage/default/40.rom_ctrl_alert_test.2416706143 Aug 17 06:39:05 PM PDT 24 Aug 17 06:39:10 PM PDT 24 127823273 ps
T332 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3844882186 Aug 17 06:39:00 PM PDT 24 Aug 17 06:40:11 PM PDT 24 6743636464 ps
T333 /workspace/coverage/default/2.rom_ctrl_stress_all.4247929797 Aug 17 06:38:33 PM PDT 24 Aug 17 06:38:40 PM PDT 24 127353565 ps
T334 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3113648706 Aug 17 06:38:59 PM PDT 24 Aug 17 06:39:11 PM PDT 24 410387050 ps
T335 /workspace/coverage/default/23.rom_ctrl_stress_all.4209406774 Aug 17 06:38:58 PM PDT 24 Aug 17 06:39:16 PM PDT 24 421498114 ps
T336 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1906057914 Aug 17 06:38:54 PM PDT 24 Aug 17 06:39:00 PM PDT 24 277718242 ps
T337 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3498352513 Aug 17 06:39:23 PM PDT 24 Aug 17 06:41:11 PM PDT 24 7746413669 ps
T338 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.249993963 Aug 17 06:38:58 PM PDT 24 Aug 17 06:40:43 PM PDT 24 1845049222 ps
T339 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.786483355 Aug 17 06:39:04 PM PDT 24 Aug 17 06:39:15 PM PDT 24 98057860 ps
T340 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1240946603 Aug 17 06:38:58 PM PDT 24 Aug 17 06:39:04 PM PDT 24 136780178 ps
T341 /workspace/coverage/default/32.rom_ctrl_stress_all.1859887677 Aug 17 06:39:09 PM PDT 24 Aug 17 06:39:22 PM PDT 24 293216571 ps
T342 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2449829057 Aug 17 06:38:54 PM PDT 24 Aug 17 06:40:42 PM PDT 24 2339813643 ps
T343 /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3954124981 Aug 17 06:39:20 PM PDT 24 Aug 17 06:43:35 PM PDT 24 3966315127 ps
T344 /workspace/coverage/default/16.rom_ctrl_alert_test.850938725 Aug 17 06:39:01 PM PDT 24 Aug 17 06:39:06 PM PDT 24 566653584 ps
T345 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2815761279 Aug 17 06:39:14 PM PDT 24 Aug 17 06:41:00 PM PDT 24 11121189914 ps
T346 /workspace/coverage/default/49.rom_ctrl_stress_all.3229584041 Aug 17 06:39:26 PM PDT 24 Aug 17 06:39:36 PM PDT 24 153598504 ps
T347 /workspace/coverage/default/34.rom_ctrl_alert_test.4227179150 Aug 17 06:39:27 PM PDT 24 Aug 17 06:39:31 PM PDT 24 332561192 ps
T348 /workspace/coverage/default/4.rom_ctrl_stress_all.317543337 Aug 17 06:39:08 PM PDT 24 Aug 17 06:39:20 PM PDT 24 469939081 ps
T349 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4083395277 Aug 17 06:39:06 PM PDT 24 Aug 17 06:39:12 PM PDT 24 961839151 ps
T350 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3963882957 Aug 17 06:39:00 PM PDT 24 Aug 17 06:39:09 PM PDT 24 320958154 ps
T351 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.927833669 Aug 17 06:38:45 PM PDT 24 Aug 17 06:39:32 PM PDT 24 1116363051 ps
T352 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3109173230 Aug 17 06:38:57 PM PDT 24 Aug 17 06:39:07 PM PDT 24 219019264 ps
T353 /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.4150819522 Aug 17 06:38:52 PM PDT 24 Aug 17 06:40:30 PM PDT 24 24498188853 ps
T354 /workspace/coverage/default/38.rom_ctrl_alert_test.2383601254 Aug 17 06:39:28 PM PDT 24 Aug 17 06:39:33 PM PDT 24 963988662 ps
T355 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2277130699 Aug 17 06:38:49 PM PDT 24 Aug 17 06:38:55 PM PDT 24 281201107 ps
T356 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.521630048 Aug 17 06:39:09 PM PDT 24 Aug 17 06:39:15 PM PDT 24 271065550 ps
T357 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2132714105 Aug 17 06:39:10 PM PDT 24 Aug 17 06:41:28 PM PDT 24 5844407596 ps
T358 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.4760885 Aug 17 06:39:04 PM PDT 24 Aug 17 06:39:13 PM PDT 24 695095827 ps
T359 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1496443628 Aug 17 06:39:15 PM PDT 24 Aug 17 06:39:24 PM PDT 24 173751287 ps
T360 /workspace/coverage/default/10.rom_ctrl_stress_all.3532614700 Aug 17 06:38:45 PM PDT 24 Aug 17 06:39:04 PM PDT 24 867552436 ps
T361 /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.365955342 Aug 17 06:39:16 PM PDT 24 Aug 17 06:40:52 PM PDT 24 1593340126 ps
T362 /workspace/coverage/default/43.rom_ctrl_stress_all.2934828407 Aug 17 06:39:10 PM PDT 24 Aug 17 06:39:25 PM PDT 24 996116072 ps
T363 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1741512374 Aug 17 06:39:30 PM PDT 24 Aug 17 06:39:40 PM PDT 24 390975196 ps
T59 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3278556662 Aug 17 06:29:23 PM PDT 24 Aug 17 06:29:32 PM PDT 24 1045818785 ps
T60 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.696353854 Aug 17 06:29:10 PM PDT 24 Aug 17 06:29:14 PM PDT 24 350852169 ps
T56 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3727818401 Aug 17 06:29:23 PM PDT 24 Aug 17 06:30:03 PM PDT 24 353100981 ps
T364 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4293350905 Aug 17 06:29:20 PM PDT 24 Aug 17 06:29:25 PM PDT 24 127226423 ps
T65 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2973763224 Aug 17 06:29:28 PM PDT 24 Aug 17 06:29:33 PM PDT 24 499207239 ps
T365 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4224588562 Aug 17 06:28:48 PM PDT 24 Aug 17 06:28:53 PM PDT 24 519229740 ps
T366 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.238555700 Aug 17 06:28:48 PM PDT 24 Aug 17 06:28:55 PM PDT 24 515149897 ps
T367 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2088610018 Aug 17 06:29:18 PM PDT 24 Aug 17 06:29:23 PM PDT 24 654071313 ps
T368 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2064844511 Aug 17 06:29:25 PM PDT 24 Aug 17 06:29:30 PM PDT 24 355166068 ps
T369 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1766117854 Aug 17 06:29:20 PM PDT 24 Aug 17 06:29:30 PM PDT 24 157677365 ps
T113 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1732098313 Aug 17 06:28:51 PM PDT 24 Aug 17 06:28:56 PM PDT 24 520942421 ps
T114 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3319808632 Aug 17 06:28:49 PM PDT 24 Aug 17 06:29:18 PM PDT 24 7384293144 ps
T370 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1019608606 Aug 17 06:28:43 PM PDT 24 Aug 17 06:28:52 PM PDT 24 132659716 ps
T66 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2595988436 Aug 17 06:29:11 PM PDT 24 Aug 17 06:29:16 PM PDT 24 500041785 ps
T57 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1788570962 Aug 17 06:29:07 PM PDT 24 Aug 17 06:29:45 PM PDT 24 795815893 ps
T67 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2437794088 Aug 17 06:29:08 PM PDT 24 Aug 17 06:29:29 PM PDT 24 530666634 ps
T115 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.125217486 Aug 17 06:28:56 PM PDT 24 Aug 17 06:29:00 PM PDT 24 333084427 ps
T107 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.840125148 Aug 17 06:29:10 PM PDT 24 Aug 17 06:29:15 PM PDT 24 135835869 ps
T68 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2929775737 Aug 17 06:29:18 PM PDT 24 Aug 17 06:29:22 PM PDT 24 290801533 ps
T69 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3637996839 Aug 17 06:28:52 PM PDT 24 Aug 17 06:28:58 PM PDT 24 128698729 ps
T371 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2141950586 Aug 17 06:29:24 PM PDT 24 Aug 17 06:29:35 PM PDT 24 2042197986 ps
T108 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1501568602 Aug 17 06:28:55 PM PDT 24 Aug 17 06:28:59 PM PDT 24 299649175 ps
T58 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.616186156 Aug 17 06:29:11 PM PDT 24 Aug 17 06:30:22 PM PDT 24 710558929 ps
T70 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3799837298 Aug 17 06:29:15 PM PDT 24 Aug 17 06:29:22 PM PDT 24 260340652 ps
T372 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2975804942 Aug 17 06:29:03 PM PDT 24 Aug 17 06:29:11 PM PDT 24 480935169 ps
T373 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.274599489 Aug 17 06:29:17 PM PDT 24 Aug 17 06:29:21 PM PDT 24 348561046 ps
T374 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2093879842 Aug 17 06:29:12 PM PDT 24 Aug 17 06:29:30 PM PDT 24 375574941 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4111444875 Aug 17 06:28:55 PM PDT 24 Aug 17 06:29:00 PM PDT 24 1036687588 ps
T71 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1682574609 Aug 17 06:29:24 PM PDT 24 Aug 17 06:29:56 PM PDT 24 826076232 ps
T72 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1290817432 Aug 17 06:29:11 PM PDT 24 Aug 17 06:29:16 PM PDT 24 256830018 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1457104256 Aug 17 06:29:12 PM PDT 24 Aug 17 06:29:19 PM PDT 24 408641236 ps
T73 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3027012266 Aug 17 06:29:05 PM PDT 24 Aug 17 06:29:10 PM PDT 24 256933102 ps
T74 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1669685798 Aug 17 06:29:12 PM PDT 24 Aug 17 06:29:30 PM PDT 24 380735806 ps
T109 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3384602464 Aug 17 06:29:23 PM PDT 24 Aug 17 06:29:27 PM PDT 24 321394590 ps
T377 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1668141767 Aug 17 06:28:48 PM PDT 24 Aug 17 06:28:58 PM PDT 24 263061653 ps
T378 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2806667772 Aug 17 06:29:30 PM PDT 24 Aug 17 06:29:35 PM PDT 24 506192283 ps
T110 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2517959219 Aug 17 06:29:17 PM PDT 24 Aug 17 06:29:22 PM PDT 24 127910089 ps
T379 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2861807035 Aug 17 06:28:59 PM PDT 24 Aug 17 06:29:05 PM PDT 24 280036088 ps
T121 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.547656909 Aug 17 06:29:29 PM PDT 24 Aug 17 06:30:37 PM PDT 24 1479622493 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2211503498 Aug 17 06:29:14 PM PDT 24 Aug 17 06:29:18 PM PDT 24 419421565 ps
T111 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2310906622 Aug 17 06:29:17 PM PDT 24 Aug 17 06:29:22 PM PDT 24 518278681 ps
T381 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3000891185 Aug 17 06:29:19 PM PDT 24 Aug 17 06:29:26 PM PDT 24 126994610 ps
T382 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2851884778 Aug 17 06:29:19 PM PDT 24 Aug 17 06:29:23 PM PDT 24 210428070 ps
T125 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1236387956 Aug 17 06:29:31 PM PDT 24 Aug 17 06:30:08 PM PDT 24 890871443 ps
T112 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2588307986 Aug 17 06:28:50 PM PDT 24 Aug 17 06:28:55 PM PDT 24 516846300 ps
T81 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.964466369 Aug 17 06:29:18 PM PDT 24 Aug 17 06:29:23 PM PDT 24 127041885 ps
T82 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2867987806 Aug 17 06:29:00 PM PDT 24 Aug 17 06:29:28 PM PDT 24 561435143 ps
T383 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3635681370 Aug 17 06:29:05 PM PDT 24 Aug 17 06:29:10 PM PDT 24 521441246 ps
T83 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2845901720 Aug 17 06:29:07 PM PDT 24 Aug 17 06:29:11 PM PDT 24 89664442 ps
T384 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.573073271 Aug 17 06:28:43 PM PDT 24 Aug 17 06:28:51 PM PDT 24 96310469 ps
T385 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2807763256 Aug 17 06:29:29 PM PDT 24 Aug 17 06:29:39 PM PDT 24 92913241 ps
T386 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1471549080 Aug 17 06:29:04 PM PDT 24 Aug 17 06:29:08 PM PDT 24 171154464 ps
T131 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.596819788 Aug 17 06:29:24 PM PDT 24 Aug 17 06:30:04 PM PDT 24 602786023 ps
T387 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.860403518 Aug 17 06:28:51 PM PDT 24 Aug 17 06:29:00 PM PDT 24 321802086 ps
T133 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.640784646 Aug 17 06:29:31 PM PDT 24 Aug 17 06:30:08 PM PDT 24 196961816 ps
T132 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.925659210 Aug 17 06:28:58 PM PDT 24 Aug 17 06:30:08 PM PDT 24 276040883 ps
T388 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1070696827 Aug 17 06:28:59 PM PDT 24 Aug 17 06:29:04 PM PDT 24 132890743 ps
T84 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2552887628 Aug 17 06:29:05 PM PDT 24 Aug 17 06:29:36 PM PDT 24 808361895 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3131471333 Aug 17 06:28:43 PM PDT 24 Aug 17 06:28:48 PM PDT 24 249242443 ps
T390 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3221056538 Aug 17 06:29:03 PM PDT 24 Aug 17 06:29:08 PM PDT 24 522860572 ps
T124 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2452451354 Aug 17 06:28:51 PM PDT 24 Aug 17 06:30:01 PM PDT 24 7325910407 ps
T391 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3269278107 Aug 17 06:29:31 PM PDT 24 Aug 17 06:29:36 PM PDT 24 97098545 ps
T392 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3635300247 Aug 17 06:29:08 PM PDT 24 Aug 17 06:29:15 PM PDT 24 334880490 ps
T122 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3246545953 Aug 17 06:28:51 PM PDT 24 Aug 17 06:30:00 PM PDT 24 1056534764 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2442194578 Aug 17 06:28:51 PM PDT 24 Aug 17 06:28:55 PM PDT 24 334143686 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1326406405 Aug 17 06:28:52 PM PDT 24 Aug 17 06:28:57 PM PDT 24 895723968 ps
T395 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4147580585 Aug 17 06:28:42 PM PDT 24 Aug 17 06:28:49 PM PDT 24 96802010 ps
T123 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2116641249 Aug 17 06:29:16 PM PDT 24 Aug 17 06:30:24 PM PDT 24 927614046 ps
T396 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2709204877 Aug 17 06:29:20 PM PDT 24 Aug 17 06:29:26 PM PDT 24 340137132 ps
T397 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2658336924 Aug 17 06:29:29 PM PDT 24 Aug 17 06:29:35 PM PDT 24 288754634 ps
T398 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3166594792 Aug 17 06:29:18 PM PDT 24 Aug 17 06:29:23 PM PDT 24 210619414 ps
T399 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.988021629 Aug 17 06:29:12 PM PDT 24 Aug 17 06:29:18 PM PDT 24 480756881 ps
T400 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2096636754 Aug 17 06:29:10 PM PDT 24 Aug 17 06:29:15 PM PDT 24 334146954 ps
T134 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.866480110 Aug 17 06:29:17 PM PDT 24 Aug 17 06:29:48 PM PDT 24 3135203683 ps
T401 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2838530204 Aug 17 06:29:18 PM PDT 24 Aug 17 06:29:23 PM PDT 24 360654787 ps
T402 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1016927124 Aug 17 06:28:50 PM PDT 24 Aug 17 06:28:55 PM PDT 24 380940649 ps
T403 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3016127386 Aug 17 06:29:31 PM PDT 24 Aug 17 06:29:35 PM PDT 24 1035086248 ps
T85 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4212544206 Aug 17 06:29:01 PM PDT 24 Aug 17 06:29:28 PM PDT 24 1785720283 ps
T86 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.880333039 Aug 17 06:28:41 PM PDT 24 Aug 17 06:28:49 PM PDT 24 190418591 ps
T404 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3158372185 Aug 17 06:29:02 PM PDT 24 Aug 17 06:29:07 PM PDT 24 880988561 ps
T405 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4147998198 Aug 17 06:29:14 PM PDT 24 Aug 17 06:29:20 PM PDT 24 350688271 ps
T406 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.167579970 Aug 17 06:28:55 PM PDT 24 Aug 17 06:29:01 PM PDT 24 479059394 ps
T407 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2131758887 Aug 17 06:29:08 PM PDT 24 Aug 17 06:30:19 PM PDT 24 3778121061 ps
T408 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.277520037 Aug 17 06:29:14 PM PDT 24 Aug 17 06:29:21 PM PDT 24 517794694 ps
T409 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.279861986 Aug 17 06:28:56 PM PDT 24 Aug 17 06:29:01 PM PDT 24 655746453 ps
T410 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2066991580 Aug 17 06:29:00 PM PDT 24 Aug 17 06:29:04 PM PDT 24 1186289269 ps
T411 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.978540148 Aug 17 06:29:16 PM PDT 24 Aug 17 06:29:21 PM PDT 24 128422731 ps
T412 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1144977228 Aug 17 06:28:51 PM PDT 24 Aug 17 06:28:56 PM PDT 24 1112608886 ps
T92 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3299940136 Aug 17 06:29:21 PM PDT 24 Aug 17 06:29:39 PM PDT 24 2588772981 ps
T413 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2970939278 Aug 17 06:28:43 PM PDT 24 Aug 17 06:28:52 PM PDT 24 2589206858 ps
T128 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.637389402 Aug 17 06:29:13 PM PDT 24 Aug 17 06:30:26 PM PDT 24 411348265 ps
T135 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1231176913 Aug 17 06:29:27 PM PDT 24 Aug 17 06:29:58 PM PDT 24 4382182041 ps
T126 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.440006709 Aug 17 06:29:16 PM PDT 24 Aug 17 06:29:52 PM PDT 24 420170124 ps
T414 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1452747746 Aug 17 06:28:51 PM PDT 24 Aug 17 06:29:08 PM PDT 24 1505600416 ps
T415 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.431262942 Aug 17 06:29:04 PM PDT 24 Aug 17 06:29:10 PM PDT 24 347520953 ps
T416 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.619711968 Aug 17 06:29:18 PM PDT 24 Aug 17 06:29:23 PM PDT 24 320875517 ps
T130 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2984624785 Aug 17 06:28:58 PM PDT 24 Aug 17 06:30:17 PM PDT 24 765522007 ps
T417 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3471609889 Aug 17 06:28:54 PM PDT 24 Aug 17 06:29:02 PM PDT 24 255734666 ps
T418 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.50072725 Aug 17 06:29:30 PM PDT 24 Aug 17 06:29:36 PM PDT 24 347966815 ps
T419 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4065762911 Aug 17 06:29:21 PM PDT 24 Aug 17 06:29:29 PM PDT 24 348154226 ps
T129 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2297984274 Aug 17 06:28:59 PM PDT 24 Aug 17 06:30:07 PM PDT 24 500572081 ps
T420 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1110131237 Aug 17 06:29:30 PM PDT 24 Aug 17 06:29:34 PM PDT 24 107519668 ps
T93 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4076938659 Aug 17 06:29:07 PM PDT 24 Aug 17 06:29:25 PM PDT 24 370590207 ps
T421 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3270342603 Aug 17 06:29:16 PM PDT 24 Aug 17 06:29:53 PM PDT 24 235882576 ps
T422 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2706138990 Aug 17 06:29:12 PM PDT 24 Aug 17 06:29:18 PM PDT 24 280077180 ps
T423 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4132840916 Aug 17 06:29:18 PM PDT 24 Aug 17 06:29:25 PM PDT 24 100699964 ps
T424 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3755977570 Aug 17 06:29:00 PM PDT 24 Aug 17 06:29:04 PM PDT 24 172727320 ps
T425 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.876676805 Aug 17 06:28:51 PM PDT 24 Aug 17 06:28:56 PM PDT 24 558171992 ps
T94 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2753159710 Aug 17 06:29:16 PM PDT 24 Aug 17 06:29:20 PM PDT 24 333629803 ps
T95 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1046925964 Aug 17 06:29:04 PM PDT 24 Aug 17 06:29:32 PM PDT 24 1990338801 ps
T127 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1765243241 Aug 17 06:29:21 PM PDT 24 Aug 17 06:29:57 PM PDT 24 537846721 ps
T426 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3326860411 Aug 17 06:28:44 PM PDT 24 Aug 17 06:28:49 PM PDT 24 126741242 ps
T427 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2111462163 Aug 17 06:29:15 PM PDT 24 Aug 17 06:29:20 PM PDT 24 210305016 ps
T428 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3183498350 Aug 17 06:29:22 PM PDT 24 Aug 17 06:29:29 PM PDT 24 85594566 ps
T429 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2574114234 Aug 17 06:28:51 PM PDT 24 Aug 17 06:28:55 PM PDT 24 183539665 ps
T430 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3723768250 Aug 17 06:29:12 PM PDT 24 Aug 17 06:29:18 PM PDT 24 91068307 ps
T431 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1988280785 Aug 17 06:29:31 PM PDT 24 Aug 17 06:29:36 PM PDT 24 199554203 ps
T432 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3801746791 Aug 17 06:29:07 PM PDT 24 Aug 17 06:29:12 PM PDT 24 186321536 ps
T433 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.917140282 Aug 17 06:29:17 PM PDT 24 Aug 17 06:29:24 PM PDT 24 186934779 ps
T434 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2820486774 Aug 17 06:29:09 PM PDT 24 Aug 17 06:29:13 PM PDT 24 89208474 ps
T435 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1490225836 Aug 17 06:29:19 PM PDT 24 Aug 17 06:29:23 PM PDT 24 416103530 ps
T96 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.387439751 Aug 17 06:28:45 PM PDT 24 Aug 17 06:29:17 PM PDT 24 3145590017 ps
T436 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2084369330 Aug 17 06:29:24 PM PDT 24 Aug 17 06:29:29 PM PDT 24 190202805 ps
T437 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2759465026 Aug 17 06:29:26 PM PDT 24 Aug 17 06:29:31 PM PDT 24 130866738 ps
T438 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3493197120 Aug 17 06:29:01 PM PDT 24 Aug 17 06:29:28 PM PDT 24 1088309314 ps
T439 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.605378162 Aug 17 06:29:12 PM PDT 24 Aug 17 06:29:19 PM PDT 24 97593100 ps
T440 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1341149208 Aug 17 06:28:52 PM PDT 24 Aug 17 06:28:56 PM PDT 24 832774285 ps
T441 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1432268953 Aug 17 06:29:20 PM PDT 24 Aug 17 06:29:24 PM PDT 24 90224406 ps
T442 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.73825725 Aug 17 06:28:49 PM PDT 24 Aug 17 06:28:56 PM PDT 24 272948057 ps
T443 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1321568957 Aug 17 06:29:05 PM PDT 24 Aug 17 06:29:10 PM PDT 24 248585279 ps
T444 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3105245145 Aug 17 06:28:48 PM PDT 24 Aug 17 06:29:25 PM PDT 24 784858592 ps
T445 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4220660717 Aug 17 06:29:14 PM PDT 24 Aug 17 06:29:19 PM PDT 24 161768286 ps
T446 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3407559253 Aug 17 06:28:49 PM PDT 24 Aug 17 06:28:58 PM PDT 24 162725684 ps
T447 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.20260010 Aug 17 06:28:49 PM PDT 24 Aug 17 06:29:00 PM PDT 24 1215378827 ps
T448 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2509741942 Aug 17 06:29:13 PM PDT 24 Aug 17 06:29:20 PM PDT 24 140869530 ps
T449 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2568285656 Aug 17 06:29:03 PM PDT 24 Aug 17 06:29:12 PM PDT 24 255354855 ps
T450 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1899490278 Aug 17 06:28:49 PM PDT 24 Aug 17 06:29:07 PM PDT 24 2088583244 ps
T87 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3841578114 Aug 17 06:28:51 PM PDT 24 Aug 17 06:28:55 PM PDT 24 88038354 ps
T451 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2272874096 Aug 17 06:29:02 PM PDT 24 Aug 17 06:29:07 PM PDT 24 1554293161 ps
T88 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1415636101 Aug 17 06:29:14 PM PDT 24 Aug 17 06:29:46 PM PDT 24 1646932915 ps
T452 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1514114606 Aug 17 06:29:17 PM PDT 24 Aug 17 06:29:54 PM PDT 24 600612523 ps
T89 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2556422748 Aug 17 06:29:22 PM PDT 24 Aug 17 06:29:53 PM PDT 24 3270307801 ps
T90 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2558718323 Aug 17 06:29:16 PM PDT 24 Aug 17 06:29:35 PM PDT 24 725568775 ps
T91 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3362047487 Aug 17 06:28:51 PM PDT 24 Aug 17 06:28:56 PM PDT 24 89646139 ps
T453 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2224560961 Aug 17 06:29:27 PM PDT 24 Aug 17 06:29:36 PM PDT 24 127785670 ps

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1066487220
Short name T8
Test name
Test status
Simulation time 10598228089 ps
CPU time 88.35 seconds
Started Aug 17 06:39:03 PM PDT 24
Finished Aug 17 06:40:31 PM PDT 24
Peak memory 213552 kb
Host smart-989bcf27-09e9-43c5-b6de-df0016965dd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066487220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1066487220
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.436577890
Short name T14
Test name
Test status
Simulation time 16776136714 ps
CPU time 88.84 seconds
Started Aug 17 06:38:59 PM PDT 24
Finished Aug 17 06:40:28 PM PDT 24
Peak memory 223024 kb
Host smart-1174fd4c-9a00-469f-aae4-263ee9a4cffb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436577890 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.436577890
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3126212491
Short name T21
Test name
Test status
Simulation time 428618799 ps
CPU time 7.53 seconds
Started Aug 17 06:39:22 PM PDT 24
Finished Aug 17 06:39:30 PM PDT 24
Peak memory 211552 kb
Host smart-e97ddcab-04b2-45c6-b130-0996dafb4032
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126212491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3126212491
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2586665747
Short name T4
Test name
Test status
Simulation time 9250847457 ps
CPU time 99.54 seconds
Started Aug 17 06:39:01 PM PDT 24
Finished Aug 17 06:40:41 PM PDT 24
Peak memory 228056 kb
Host smart-43960461-518e-453f-98fc-8c41e17f1f45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586665747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2586665747
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.616186156
Short name T58
Test name
Test status
Simulation time 710558929 ps
CPU time 70.49 seconds
Started Aug 17 06:29:11 PM PDT 24
Finished Aug 17 06:30:22 PM PDT 24
Peak memory 213064 kb
Host smart-8dbcc749-317d-497f-b8b1-8b4ef5ebb716
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616186156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.616186156
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1290295668
Short name T29
Test name
Test status
Simulation time 271347252 ps
CPU time 100.16 seconds
Started Aug 17 06:38:57 PM PDT 24
Finished Aug 17 06:40:37 PM PDT 24
Peak memory 236732 kb
Host smart-1fd0d52e-9a18-438b-980b-c7b6878204d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290295668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1290295668
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3383074588
Short name T10
Test name
Test status
Simulation time 172343133 ps
CPU time 4.28 seconds
Started Aug 17 06:39:06 PM PDT 24
Finished Aug 17 06:39:10 PM PDT 24
Peak memory 211164 kb
Host smart-e4407e8c-92f3-41d0-8c20-932104902959
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383074588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3383074588
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2437794088
Short name T67
Test name
Test status
Simulation time 530666634 ps
CPU time 20.73 seconds
Started Aug 17 06:29:08 PM PDT 24
Finished Aug 17 06:29:29 PM PDT 24
Peak memory 211408 kb
Host smart-485e76ef-34a5-411d-a820-2e098228aae0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437794088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2437794088
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2891405033
Short name T33
Test name
Test status
Simulation time 1065495593 ps
CPU time 14.55 seconds
Started Aug 17 06:38:44 PM PDT 24
Finished Aug 17 06:38:59 PM PDT 24
Peak memory 211624 kb
Host smart-c0c37fd7-4b12-46d3-a62b-870a8e2ef4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891405033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2891405033
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.440006709
Short name T126
Test name
Test status
Simulation time 420170124 ps
CPU time 35.93 seconds
Started Aug 17 06:29:16 PM PDT 24
Finished Aug 17 06:29:52 PM PDT 24
Peak memory 211680 kb
Host smart-3cad3450-2bff-4313-952e-6e80a0996eaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440006709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.440006709
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.749494740
Short name T180
Test name
Test status
Simulation time 2187053948 ps
CPU time 93.41 seconds
Started Aug 17 06:39:05 PM PDT 24
Finished Aug 17 06:40:39 PM PDT 24
Peak memory 227884 kb
Host smart-db2739e7-500c-483f-b765-7d0db8857c7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749494740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.749494740
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3320269896
Short name T42
Test name
Test status
Simulation time 172411452 ps
CPU time 9.18 seconds
Started Aug 17 06:38:45 PM PDT 24
Finished Aug 17 06:38:59 PM PDT 24
Peak memory 211476 kb
Host smart-6d562423-9bf9-4230-8683-75743d58e7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320269896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3320269896
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2116641249
Short name T123
Test name
Test status
Simulation time 927614046 ps
CPU time 68.53 seconds
Started Aug 17 06:29:16 PM PDT 24
Finished Aug 17 06:30:24 PM PDT 24
Peak memory 213160 kb
Host smart-381bce8d-cf7e-4c4a-9302-0376f2b26553
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116641249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2116641249
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.880333039
Short name T86
Test name
Test status
Simulation time 190418591 ps
CPU time 7.3 seconds
Started Aug 17 06:28:41 PM PDT 24
Finished Aug 17 06:28:49 PM PDT 24
Peak memory 211344 kb
Host smart-c1ddaa93-69da-468f-9dff-657dfb653bde
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880333039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.880333039
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2973763224
Short name T65
Test name
Test status
Simulation time 499207239 ps
CPU time 4.94 seconds
Started Aug 17 06:29:28 PM PDT 24
Finished Aug 17 06:29:33 PM PDT 24
Peak memory 211408 kb
Host smart-e5d3064c-e9e8-473d-b9d9-3c3295294820
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973763224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2973763224
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3270342603
Short name T421
Test name
Test status
Simulation time 235882576 ps
CPU time 37.52 seconds
Started Aug 17 06:29:16 PM PDT 24
Finished Aug 17 06:29:53 PM PDT 24
Peak memory 212720 kb
Host smart-af6d86a9-781f-4ac7-a1f1-a510144b8d5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270342603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3270342603
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2867987806
Short name T82
Test name
Test status
Simulation time 561435143 ps
CPU time 27.45 seconds
Started Aug 17 06:29:00 PM PDT 24
Finished Aug 17 06:29:28 PM PDT 24
Peak memory 211356 kb
Host smart-989f979a-c857-46b3-85a7-93f19521802d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867987806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2867987806
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.925659210
Short name T132
Test name
Test status
Simulation time 276040883 ps
CPU time 69.77 seconds
Started Aug 17 06:28:58 PM PDT 24
Finished Aug 17 06:30:08 PM PDT 24
Peak memory 219520 kb
Host smart-d58fb9e2-4d87-4b4a-9017-43c446391ba8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925659210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.925659210
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.770413795
Short name T117
Test name
Test status
Simulation time 141348610 ps
CPU time 6.19 seconds
Started Aug 17 06:38:54 PM PDT 24
Finished Aug 17 06:39:01 PM PDT 24
Peak memory 211080 kb
Host smart-1efde615-36da-4bb2-8bb3-3d1f67ecbaf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=770413795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.770413795
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1829020854
Short name T76
Test name
Test status
Simulation time 1545034920 ps
CPU time 17.78 seconds
Started Aug 17 06:38:47 PM PDT 24
Finished Aug 17 06:39:05 PM PDT 24
Peak memory 215156 kb
Host smart-1bdf22a0-93a5-4d60-b0c1-8ef285b44eb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829020854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1829020854
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1719959827
Short name T97
Test name
Test status
Simulation time 1179276850 ps
CPU time 5.77 seconds
Started Aug 17 06:39:05 PM PDT 24
Finished Aug 17 06:39:11 PM PDT 24
Peak memory 211152 kb
Host smart-badbee2b-65ac-4c93-b53f-6f7da817daa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1719959827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1719959827
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3114984324
Short name T16
Test name
Test status
Simulation time 2495289444 ps
CPU time 90.95 seconds
Started Aug 17 06:39:12 PM PDT 24
Finished Aug 17 06:40:43 PM PDT 24
Peak memory 219924 kb
Host smart-b9826e86-887e-4c9e-b9a8-568eeb7ebcbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114984324 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3114984324
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2211503498
Short name T380
Test name
Test status
Simulation time 419421565 ps
CPU time 4.06 seconds
Started Aug 17 06:29:14 PM PDT 24
Finished Aug 17 06:29:18 PM PDT 24
Peak memory 211428 kb
Host smart-241a8f58-8397-4158-9a65-df72cc637542
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211503498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2211503498
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2759465026
Short name T437
Test name
Test status
Simulation time 130866738 ps
CPU time 5.17 seconds
Started Aug 17 06:29:26 PM PDT 24
Finished Aug 17 06:29:31 PM PDT 24
Peak memory 217856 kb
Host smart-3fa5faa6-091c-42d9-9d72-f6badd3b71d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759465026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2759465026
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1144977228
Short name T412
Test name
Test status
Simulation time 1112608886 ps
CPU time 5.37 seconds
Started Aug 17 06:28:51 PM PDT 24
Finished Aug 17 06:28:56 PM PDT 24
Peak memory 215464 kb
Host smart-d72bb489-cbec-4888-a937-7250490e536b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144977228 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1144977228
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.696353854
Short name T60
Test name
Test status
Simulation time 350852169 ps
CPU time 4.11 seconds
Started Aug 17 06:29:10 PM PDT 24
Finished Aug 17 06:29:14 PM PDT 24
Peak memory 211424 kb
Host smart-a40f8390-bbd3-4a6d-9ab2-7b20205b0b26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696353854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.696353854
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1321568957
Short name T443
Test name
Test status
Simulation time 248585279 ps
CPU time 4.58 seconds
Started Aug 17 06:29:05 PM PDT 24
Finished Aug 17 06:29:10 PM PDT 24
Peak memory 211312 kb
Host smart-a4384bf2-6e9f-4449-afc0-928f2cb334cf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321568957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1321568957
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2442194578
Short name T393
Test name
Test status
Simulation time 334143686 ps
CPU time 4 seconds
Started Aug 17 06:28:51 PM PDT 24
Finished Aug 17 06:28:55 PM PDT 24
Peak memory 211264 kb
Host smart-b7ff2037-d2e7-47fc-b0f0-3597e40f1748
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442194578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2442194578
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3493197120
Short name T438
Test name
Test status
Simulation time 1088309314 ps
CPU time 27.48 seconds
Started Aug 17 06:29:01 PM PDT 24
Finished Aug 17 06:29:28 PM PDT 24
Peak memory 211356 kb
Host smart-d901d675-c3f4-4f44-96ce-56b7c1cf7d51
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493197120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3493197120
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4147580585
Short name T395
Test name
Test status
Simulation time 96802010 ps
CPU time 6.11 seconds
Started Aug 17 06:28:42 PM PDT 24
Finished Aug 17 06:28:49 PM PDT 24
Peak memory 211428 kb
Host smart-470cdedc-c493-4191-afe0-7f2ab6f091f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147580585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.4147580585
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2970939278
Short name T413
Test name
Test status
Simulation time 2589206858 ps
CPU time 8.91 seconds
Started Aug 17 06:28:43 PM PDT 24
Finished Aug 17 06:28:52 PM PDT 24
Peak memory 219700 kb
Host smart-f4f6408e-b25b-4142-9105-c3944ba683a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970939278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2970939278
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2131758887
Short name T407
Test name
Test status
Simulation time 3778121061 ps
CPU time 70.44 seconds
Started Aug 17 06:29:08 PM PDT 24
Finished Aug 17 06:30:19 PM PDT 24
Peak memory 219712 kb
Host smart-9a998c10-4cb6-4201-bf6d-3160ed470459
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131758887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2131758887
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3326860411
Short name T426
Test name
Test status
Simulation time 126741242 ps
CPU time 4.9 seconds
Started Aug 17 06:28:44 PM PDT 24
Finished Aug 17 06:28:49 PM PDT 24
Peak memory 211388 kb
Host smart-ae7de7ee-3446-4c14-90d0-e15c6e335879
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326860411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3326860411
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1732098313
Short name T113
Test name
Test status
Simulation time 520942421 ps
CPU time 5.02 seconds
Started Aug 17 06:28:51 PM PDT 24
Finished Aug 17 06:28:56 PM PDT 24
Peak memory 219508 kb
Host smart-182b72f0-73f0-4d3c-9735-50e1ec77208c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732098313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1732098313
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3637996839
Short name T69
Test name
Test status
Simulation time 128698729 ps
CPU time 6.5 seconds
Started Aug 17 06:28:52 PM PDT 24
Finished Aug 17 06:28:58 PM PDT 24
Peak memory 211376 kb
Host smart-ae7636ad-4582-4dbb-b1bf-06a59e349969
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637996839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3637996839
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2861807035
Short name T379
Test name
Test status
Simulation time 280036088 ps
CPU time 6.5 seconds
Started Aug 17 06:28:59 PM PDT 24
Finished Aug 17 06:29:05 PM PDT 24
Peak memory 219636 kb
Host smart-97056fad-ceb8-4a5d-afe0-9a4388a893ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861807035 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2861807035
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1110131237
Short name T420
Test name
Test status
Simulation time 107519668 ps
CPU time 4.05 seconds
Started Aug 17 06:29:30 PM PDT 24
Finished Aug 17 06:29:34 PM PDT 24
Peak memory 211408 kb
Host smart-a6f43213-ccbe-425c-a186-1ddcc6822b31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110131237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1110131237
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4111444875
Short name T375
Test name
Test status
Simulation time 1036687588 ps
CPU time 3.94 seconds
Started Aug 17 06:28:55 PM PDT 24
Finished Aug 17 06:29:00 PM PDT 24
Peak memory 211320 kb
Host smart-5d7d3edc-2f62-449b-afcb-925b418fdd63
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111444875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4111444875
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1490225836
Short name T435
Test name
Test status
Simulation time 416103530 ps
CPU time 4.08 seconds
Started Aug 17 06:29:19 PM PDT 24
Finished Aug 17 06:29:23 PM PDT 24
Peak memory 211368 kb
Host smart-debd7e1c-3fdc-4e1c-a6f3-8fe77fa5d824
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490225836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1490225836
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1899490278
Short name T450
Test name
Test status
Simulation time 2088583244 ps
CPU time 17.45 seconds
Started Aug 17 06:28:49 PM PDT 24
Finished Aug 17 06:29:07 PM PDT 24
Peak memory 211316 kb
Host smart-ff25b838-7bb0-4088-9b50-031d6eb150f3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899490278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1899490278
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1326406405
Short name T394
Test name
Test status
Simulation time 895723968 ps
CPU time 4.78 seconds
Started Aug 17 06:28:52 PM PDT 24
Finished Aug 17 06:28:57 PM PDT 24
Peak memory 218692 kb
Host smart-8776845c-36d0-4e75-bcf4-47eb8feab20f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326406405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1326406405
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1457104256
Short name T376
Test name
Test status
Simulation time 408641236 ps
CPU time 7.17 seconds
Started Aug 17 06:29:12 PM PDT 24
Finished Aug 17 06:29:19 PM PDT 24
Peak memory 219584 kb
Host smart-f6c75fce-b331-48b3-be44-9e767618e312
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457104256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1457104256
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2806667772
Short name T378
Test name
Test status
Simulation time 506192283 ps
CPU time 4.87 seconds
Started Aug 17 06:29:30 PM PDT 24
Finished Aug 17 06:29:35 PM PDT 24
Peak memory 219600 kb
Host smart-0118c013-6072-4d8b-98ce-02333f264d27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806667772 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2806667772
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.274599489
Short name T373
Test name
Test status
Simulation time 348561046 ps
CPU time 4.24 seconds
Started Aug 17 06:29:17 PM PDT 24
Finished Aug 17 06:29:21 PM PDT 24
Peak memory 219524 kb
Host smart-cf9bbecf-e617-465b-b6fb-ae9f1bdb84b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274599489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.274599489
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4147998198
Short name T405
Test name
Test status
Simulation time 350688271 ps
CPU time 5.82 seconds
Started Aug 17 06:29:14 PM PDT 24
Finished Aug 17 06:29:20 PM PDT 24
Peak memory 219528 kb
Host smart-dbb7d9d4-8a63-470a-b835-64905b4d9df5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147998198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.4147998198
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.917140282
Short name T433
Test name
Test status
Simulation time 186934779 ps
CPU time 6.98 seconds
Started Aug 17 06:29:17 PM PDT 24
Finished Aug 17 06:29:24 PM PDT 24
Peak memory 215392 kb
Host smart-09aa4bf3-4a13-4c5f-b34e-cce2e5312fff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917140282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.917140282
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2064844511
Short name T368
Test name
Test status
Simulation time 355166068 ps
CPU time 4.68 seconds
Started Aug 17 06:29:25 PM PDT 24
Finished Aug 17 06:29:30 PM PDT 24
Peak memory 215268 kb
Host smart-f6353104-db77-47f3-875d-b9d757f8f7b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064844511 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2064844511
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2588307986
Short name T112
Test name
Test status
Simulation time 516846300 ps
CPU time 4.79 seconds
Started Aug 17 06:28:50 PM PDT 24
Finished Aug 17 06:28:55 PM PDT 24
Peak memory 211396 kb
Host smart-102c8e7a-93a3-45e3-a8e2-a643fd592260
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588307986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2588307986
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2558718323
Short name T90
Test name
Test status
Simulation time 725568775 ps
CPU time 18.25 seconds
Started Aug 17 06:29:16 PM PDT 24
Finished Aug 17 06:29:35 PM PDT 24
Peak memory 211444 kb
Host smart-fea75dcf-6f13-447b-9385-2aff3e931ba6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558718323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2558718323
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.167579970
Short name T406
Test name
Test status
Simulation time 479059394 ps
CPU time 4.87 seconds
Started Aug 17 06:28:55 PM PDT 24
Finished Aug 17 06:29:01 PM PDT 24
Peak memory 218808 kb
Host smart-60832619-4d94-4648-bbd0-a2e7111d95d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167579970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.167579970
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4132840916
Short name T423
Test name
Test status
Simulation time 100699964 ps
CPU time 7.25 seconds
Started Aug 17 06:29:18 PM PDT 24
Finished Aug 17 06:29:25 PM PDT 24
Peak memory 219600 kb
Host smart-b7da8e9d-b79f-4ada-bec3-a4c140830fc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132840916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.4132840916
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2838530204
Short name T401
Test name
Test status
Simulation time 360654787 ps
CPU time 4.57 seconds
Started Aug 17 06:29:18 PM PDT 24
Finished Aug 17 06:29:23 PM PDT 24
Peak memory 219572 kb
Host smart-f1b19d39-c261-4c23-bc7b-964eed627179
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838530204 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2838530204
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3801746791
Short name T432
Test name
Test status
Simulation time 186321536 ps
CPU time 4.82 seconds
Started Aug 17 06:29:07 PM PDT 24
Finished Aug 17 06:29:12 PM PDT 24
Peak memory 211268 kb
Host smart-23cf03b9-bd19-4ad0-9f20-7001e9f0d1a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801746791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3801746791
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4076938659
Short name T93
Test name
Test status
Simulation time 370590207 ps
CPU time 17.97 seconds
Started Aug 17 06:29:07 PM PDT 24
Finished Aug 17 06:29:25 PM PDT 24
Peak memory 211440 kb
Host smart-bbb3ae78-6e4c-4e13-b0a6-8bed65fb66b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076938659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.4076938659
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.840125148
Short name T107
Test name
Test status
Simulation time 135835869 ps
CPU time 4.94 seconds
Started Aug 17 06:29:10 PM PDT 24
Finished Aug 17 06:29:15 PM PDT 24
Peak memory 218884 kb
Host smart-64af9403-6835-4d08-8550-ac384d4fd611
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840125148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.840125148
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3471609889
Short name T417
Test name
Test status
Simulation time 255734666 ps
CPU time 7.41 seconds
Started Aug 17 06:28:54 PM PDT 24
Finished Aug 17 06:29:02 PM PDT 24
Peak memory 219608 kb
Host smart-4599f7fe-d749-4d23-a296-108014b64b0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471609889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3471609889
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2088610018
Short name T367
Test name
Test status
Simulation time 654071313 ps
CPU time 5.58 seconds
Started Aug 17 06:29:18 PM PDT 24
Finished Aug 17 06:29:23 PM PDT 24
Peak memory 219564 kb
Host smart-545abc15-a514-4bd5-94d5-87e89cca9e14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088610018 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2088610018
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.964466369
Short name T81
Test name
Test status
Simulation time 127041885 ps
CPU time 4.86 seconds
Started Aug 17 06:29:18 PM PDT 24
Finished Aug 17 06:29:23 PM PDT 24
Peak memory 211404 kb
Host smart-62d7734e-232b-4823-9bd8-d7ffcb6bb6d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964466369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.964466369
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3319808632
Short name T114
Test name
Test status
Simulation time 7384293144 ps
CPU time 28.7 seconds
Started Aug 17 06:28:49 PM PDT 24
Finished Aug 17 06:29:18 PM PDT 24
Peak memory 211504 kb
Host smart-31033f8a-8f0d-47b1-8d4f-525442519b01
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319808632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3319808632
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.431262942
Short name T415
Test name
Test status
Simulation time 347520953 ps
CPU time 5.86 seconds
Started Aug 17 06:29:04 PM PDT 24
Finished Aug 17 06:29:10 PM PDT 24
Peak memory 219548 kb
Host smart-4857a65f-f41e-44c9-b3e8-270aaaf4f7e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431262942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.431262942
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3183498350
Short name T428
Test name
Test status
Simulation time 85594566 ps
CPU time 6.61 seconds
Started Aug 17 06:29:22 PM PDT 24
Finished Aug 17 06:29:29 PM PDT 24
Peak memory 216348 kb
Host smart-9c863283-7cdc-49eb-8738-b929b7fa4039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183498350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3183498350
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1514114606
Short name T452
Test name
Test status
Simulation time 600612523 ps
CPU time 36.36 seconds
Started Aug 17 06:29:17 PM PDT 24
Finished Aug 17 06:29:54 PM PDT 24
Peak memory 211680 kb
Host smart-350c5ebb-2ed4-4b8c-a740-73e51b06b63e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514114606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1514114606
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2706138990
Short name T422
Test name
Test status
Simulation time 280077180 ps
CPU time 5.3 seconds
Started Aug 17 06:29:12 PM PDT 24
Finished Aug 17 06:29:18 PM PDT 24
Peak memory 219580 kb
Host smart-1e363bee-3c3b-4c09-8813-4152955611b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706138990 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2706138990
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2753159710
Short name T94
Test name
Test status
Simulation time 333629803 ps
CPU time 4.07 seconds
Started Aug 17 06:29:16 PM PDT 24
Finished Aug 17 06:29:20 PM PDT 24
Peak memory 218556 kb
Host smart-aeb78bce-7cb8-4c58-9d85-6d96de74afca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753159710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2753159710
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.866480110
Short name T134
Test name
Test status
Simulation time 3135203683 ps
CPU time 30.51 seconds
Started Aug 17 06:29:17 PM PDT 24
Finished Aug 17 06:29:48 PM PDT 24
Peak memory 211628 kb
Host smart-b674b686-9197-4b2b-b52e-058595d8fe60
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866480110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.866480110
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1501568602
Short name T108
Test name
Test status
Simulation time 299649175 ps
CPU time 4.06 seconds
Started Aug 17 06:28:55 PM PDT 24
Finished Aug 17 06:28:59 PM PDT 24
Peak memory 219548 kb
Host smart-62729ada-0285-40ee-9ca8-9396e37a776c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501568602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1501568602
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.50072725
Short name T418
Test name
Test status
Simulation time 347966815 ps
CPU time 6.08 seconds
Started Aug 17 06:29:30 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 219680 kb
Host smart-87abb5fb-e838-489f-869e-ecb9a4419d5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50072725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.50072725
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3246545953
Short name T122
Test name
Test status
Simulation time 1056534764 ps
CPU time 68.74 seconds
Started Aug 17 06:28:51 PM PDT 24
Finished Aug 17 06:30:00 PM PDT 24
Peak memory 219572 kb
Host smart-fa651b85-8532-420d-9329-fb669f3844c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246545953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3246545953
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.277520037
Short name T408
Test name
Test status
Simulation time 517794694 ps
CPU time 6.9 seconds
Started Aug 17 06:29:14 PM PDT 24
Finished Aug 17 06:29:21 PM PDT 24
Peak memory 219588 kb
Host smart-39f0ff2c-a99c-48f7-a6f0-2da64153188e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277520037 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.277520037
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2595988436
Short name T66
Test name
Test status
Simulation time 500041785 ps
CPU time 4.84 seconds
Started Aug 17 06:29:11 PM PDT 24
Finished Aug 17 06:29:16 PM PDT 24
Peak memory 218204 kb
Host smart-9dcc24d7-8768-497b-b752-ca0017a5e83d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595988436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2595988436
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1231176913
Short name T135
Test name
Test status
Simulation time 4382182041 ps
CPU time 30.99 seconds
Started Aug 17 06:29:27 PM PDT 24
Finished Aug 17 06:29:58 PM PDT 24
Peak memory 211932 kb
Host smart-2f913098-a8e0-4126-b7c6-5b24a4d92c98
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231176913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1231176913
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3221056538
Short name T390
Test name
Test status
Simulation time 522860572 ps
CPU time 4.83 seconds
Started Aug 17 06:29:03 PM PDT 24
Finished Aug 17 06:29:08 PM PDT 24
Peak memory 211276 kb
Host smart-1a036cda-890b-46be-93f3-5357605c9dd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221056538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3221056538
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1766117854
Short name T369
Test name
Test status
Simulation time 157677365 ps
CPU time 9.8 seconds
Started Aug 17 06:29:20 PM PDT 24
Finished Aug 17 06:29:30 PM PDT 24
Peak memory 215364 kb
Host smart-f756d021-f996-4dbb-9fb2-322c66010915
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766117854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1766117854
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2807763256
Short name T385
Test name
Test status
Simulation time 92913241 ps
CPU time 4.52 seconds
Started Aug 17 06:29:29 PM PDT 24
Finished Aug 17 06:29:39 PM PDT 24
Peak memory 219572 kb
Host smart-9961de6c-f060-47a8-83a7-fdf38ae86122
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807763256 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2807763256
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2310906622
Short name T111
Test name
Test status
Simulation time 518278681 ps
CPU time 4.9 seconds
Started Aug 17 06:29:17 PM PDT 24
Finished Aug 17 06:29:22 PM PDT 24
Peak memory 218356 kb
Host smart-175f9362-6661-49a6-b7db-ecdd95ca945f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310906622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2310906622
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1682574609
Short name T71
Test name
Test status
Simulation time 826076232 ps
CPU time 31.72 seconds
Started Aug 17 06:29:24 PM PDT 24
Finished Aug 17 06:29:56 PM PDT 24
Peak memory 211416 kb
Host smart-bf06ac85-38b7-4c1c-a2e7-b4302890ead4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682574609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1682574609
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1290817432
Short name T72
Test name
Test status
Simulation time 256830018 ps
CPU time 4.93 seconds
Started Aug 17 06:29:11 PM PDT 24
Finished Aug 17 06:29:16 PM PDT 24
Peak memory 211328 kb
Host smart-18f8fcbb-18ee-40d7-8b48-52fc67c1988a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290817432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1290817432
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2141950586
Short name T371
Test name
Test status
Simulation time 2042197986 ps
CPU time 10.89 seconds
Started Aug 17 06:29:24 PM PDT 24
Finished Aug 17 06:29:35 PM PDT 24
Peak memory 219680 kb
Host smart-a250c851-1390-4377-aaf4-d56453f88241
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141950586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2141950586
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.640784646
Short name T133
Test name
Test status
Simulation time 196961816 ps
CPU time 36.51 seconds
Started Aug 17 06:29:31 PM PDT 24
Finished Aug 17 06:30:08 PM PDT 24
Peak memory 212048 kb
Host smart-2c562a09-e93a-4a74-8a6b-ab29f3356516
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640784646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.640784646
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2084369330
Short name T436
Test name
Test status
Simulation time 190202805 ps
CPU time 4.73 seconds
Started Aug 17 06:29:24 PM PDT 24
Finished Aug 17 06:29:29 PM PDT 24
Peak memory 219608 kb
Host smart-e81385c8-3d9a-411b-b343-f92d9e114dbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084369330 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2084369330
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.978540148
Short name T411
Test name
Test status
Simulation time 128422731 ps
CPU time 4.81 seconds
Started Aug 17 06:29:16 PM PDT 24
Finished Aug 17 06:29:21 PM PDT 24
Peak memory 211412 kb
Host smart-93162987-ec8b-496b-a623-71c2b55af212
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978540148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.978540148
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3299940136
Short name T92
Test name
Test status
Simulation time 2588772981 ps
CPU time 17.99 seconds
Started Aug 17 06:29:21 PM PDT 24
Finished Aug 17 06:29:39 PM PDT 24
Peak memory 211588 kb
Host smart-8dc791d0-aad4-423e-9c35-7f4ed4d3750b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299940136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3299940136
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3755977570
Short name T424
Test name
Test status
Simulation time 172727320 ps
CPU time 4.21 seconds
Started Aug 17 06:29:00 PM PDT 24
Finished Aug 17 06:29:04 PM PDT 24
Peak memory 219568 kb
Host smart-b8de1f51-3afe-4cd1-81c5-4ffb3a53eabe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755977570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3755977570
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2568285656
Short name T449
Test name
Test status
Simulation time 255354855 ps
CPU time 8.88 seconds
Started Aug 17 06:29:03 PM PDT 24
Finished Aug 17 06:29:12 PM PDT 24
Peak memory 216564 kb
Host smart-34d0b85e-8d6f-406f-b392-3e8e0e7ae8ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568285656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2568285656
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1765243241
Short name T127
Test name
Test status
Simulation time 537846721 ps
CPU time 35.79 seconds
Started Aug 17 06:29:21 PM PDT 24
Finished Aug 17 06:29:57 PM PDT 24
Peak memory 219556 kb
Host smart-1a477b3c-15f0-4409-9fd0-a02337cb888b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765243241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1765243241
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3278556662
Short name T59
Test name
Test status
Simulation time 1045818785 ps
CPU time 8.41 seconds
Started Aug 17 06:29:23 PM PDT 24
Finished Aug 17 06:29:32 PM PDT 24
Peak memory 216800 kb
Host smart-e6bf3568-ba10-4110-b38a-a7eb76cf80aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278556662 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3278556662
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2851884778
Short name T382
Test name
Test status
Simulation time 210428070 ps
CPU time 4.14 seconds
Started Aug 17 06:29:19 PM PDT 24
Finished Aug 17 06:29:23 PM PDT 24
Peak memory 219544 kb
Host smart-b876244e-9745-4e38-b7d8-8b63bd6f1ee0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851884778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2851884778
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2093879842
Short name T374
Test name
Test status
Simulation time 375574941 ps
CPU time 17.98 seconds
Started Aug 17 06:29:12 PM PDT 24
Finished Aug 17 06:29:30 PM PDT 24
Peak memory 211404 kb
Host smart-d2114012-3fcd-4427-86f1-2875ea5c3154
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093879842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2093879842
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3799837298
Short name T70
Test name
Test status
Simulation time 260340652 ps
CPU time 6.65 seconds
Started Aug 17 06:29:15 PM PDT 24
Finished Aug 17 06:29:22 PM PDT 24
Peak memory 218852 kb
Host smart-065c0152-4673-43b7-9863-c52284ced35b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799837298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3799837298
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4065762911
Short name T419
Test name
Test status
Simulation time 348154226 ps
CPU time 8.44 seconds
Started Aug 17 06:29:21 PM PDT 24
Finished Aug 17 06:29:29 PM PDT 24
Peak memory 219632 kb
Host smart-bb137668-b7e3-4a38-a639-54242c600926
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065762911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4065762911
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.596819788
Short name T131
Test name
Test status
Simulation time 602786023 ps
CPU time 39.52 seconds
Started Aug 17 06:29:24 PM PDT 24
Finished Aug 17 06:30:04 PM PDT 24
Peak memory 214036 kb
Host smart-25fc33aa-3bea-4138-b51a-c397df9b4984
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596819788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.596819788
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3269278107
Short name T391
Test name
Test status
Simulation time 97098545 ps
CPU time 4.51 seconds
Started Aug 17 06:29:31 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 215048 kb
Host smart-14fa16c0-3c33-4c8e-b07f-eea5ca28771b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269278107 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3269278107
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2929775737
Short name T68
Test name
Test status
Simulation time 290801533 ps
CPU time 4.03 seconds
Started Aug 17 06:29:18 PM PDT 24
Finished Aug 17 06:29:22 PM PDT 24
Peak memory 211388 kb
Host smart-6b947ba9-88e6-4ea2-98f1-702769182c32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929775737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2929775737
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1415636101
Short name T88
Test name
Test status
Simulation time 1646932915 ps
CPU time 31.78 seconds
Started Aug 17 06:29:14 PM PDT 24
Finished Aug 17 06:29:46 PM PDT 24
Peak memory 211460 kb
Host smart-f00ad916-e687-4d9b-9615-e5e97abd74ff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415636101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1415636101
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3384602464
Short name T109
Test name
Test status
Simulation time 321394590 ps
CPU time 4.24 seconds
Started Aug 17 06:29:23 PM PDT 24
Finished Aug 17 06:29:27 PM PDT 24
Peak memory 211400 kb
Host smart-24c0e391-f515-44d3-815a-b0d924042ddf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384602464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3384602464
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3000891185
Short name T381
Test name
Test status
Simulation time 126994610 ps
CPU time 7.27 seconds
Started Aug 17 06:29:19 PM PDT 24
Finished Aug 17 06:29:26 PM PDT 24
Peak memory 219636 kb
Host smart-8e563b2c-9ae9-4ac5-a071-bcba6aa5d078
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000891185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3000891185
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1236387956
Short name T125
Test name
Test status
Simulation time 890871443 ps
CPU time 37.52 seconds
Started Aug 17 06:29:31 PM PDT 24
Finished Aug 17 06:30:08 PM PDT 24
Peak memory 213056 kb
Host smart-e6c38c2c-d2fb-46df-b73a-4ae3c16e23d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236387956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1236387956
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.279861986
Short name T409
Test name
Test status
Simulation time 655746453 ps
CPU time 4.77 seconds
Started Aug 17 06:28:56 PM PDT 24
Finished Aug 17 06:29:01 PM PDT 24
Peak memory 211436 kb
Host smart-a680ecf9-b63b-4971-b386-8a0710a035d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279861986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.279861986
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4220660717
Short name T445
Test name
Test status
Simulation time 161768286 ps
CPU time 4.91 seconds
Started Aug 17 06:29:14 PM PDT 24
Finished Aug 17 06:29:19 PM PDT 24
Peak memory 211416 kb
Host smart-84f9be12-cf55-4267-b2aa-5a5b674ea0b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220660717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.4220660717
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.73825725
Short name T442
Test name
Test status
Simulation time 272948057 ps
CPU time 6.48 seconds
Started Aug 17 06:28:49 PM PDT 24
Finished Aug 17 06:28:56 PM PDT 24
Peak memory 218608 kb
Host smart-d2660772-5f1f-41e1-be8f-7f78d6745732
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73825725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_res
et.73825725
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3158372185
Short name T404
Test name
Test status
Simulation time 880988561 ps
CPU time 5.41 seconds
Started Aug 17 06:29:02 PM PDT 24
Finished Aug 17 06:29:07 PM PDT 24
Peak memory 215808 kb
Host smart-8b74799a-6419-4dde-a19a-7f0d1ccec08d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158372185 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3158372185
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.125217486
Short name T115
Test name
Test status
Simulation time 333084427 ps
CPU time 4.05 seconds
Started Aug 17 06:28:56 PM PDT 24
Finished Aug 17 06:29:00 PM PDT 24
Peak memory 211412 kb
Host smart-6e53a745-4bf4-437e-9d06-a6cdcfcd01f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125217486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.125217486
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.238555700
Short name T366
Test name
Test status
Simulation time 515149897 ps
CPU time 6.58 seconds
Started Aug 17 06:28:48 PM PDT 24
Finished Aug 17 06:28:55 PM PDT 24
Peak memory 211344 kb
Host smart-e2228eee-47ae-48e3-ab31-163ec27d7c34
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238555700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.238555700
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4224588562
Short name T365
Test name
Test status
Simulation time 519229740 ps
CPU time 4.68 seconds
Started Aug 17 06:28:48 PM PDT 24
Finished Aug 17 06:28:53 PM PDT 24
Peak memory 211328 kb
Host smart-a3a73dbf-79b2-44e6-a099-65b37efff69b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224588562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.4224588562
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.387439751
Short name T96
Test name
Test status
Simulation time 3145590017 ps
CPU time 31.4 seconds
Started Aug 17 06:28:45 PM PDT 24
Finished Aug 17 06:29:17 PM PDT 24
Peak memory 211548 kb
Host smart-3a90f495-a35a-4287-bce7-0c9ffbca68ea
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387439751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.387439751
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2820486774
Short name T434
Test name
Test status
Simulation time 89208474 ps
CPU time 4.09 seconds
Started Aug 17 06:29:09 PM PDT 24
Finished Aug 17 06:29:13 PM PDT 24
Peak memory 211368 kb
Host smart-dd7eaf59-254c-41c6-bb85-4ef4eaa0b683
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820486774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2820486774
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3635300247
Short name T392
Test name
Test status
Simulation time 334880490 ps
CPU time 7.61 seconds
Started Aug 17 06:29:08 PM PDT 24
Finished Aug 17 06:29:15 PM PDT 24
Peak memory 217756 kb
Host smart-7d4e09b9-6fe1-4c55-82de-06256728cf8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635300247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3635300247
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2452451354
Short name T124
Test name
Test status
Simulation time 7325910407 ps
CPU time 69.96 seconds
Started Aug 17 06:28:51 PM PDT 24
Finished Aug 17 06:30:01 PM PDT 24
Peak memory 214268 kb
Host smart-34ece0e5-abe1-4518-8a4b-a7b334690c52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452451354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2452451354
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3362047487
Short name T91
Test name
Test status
Simulation time 89646139 ps
CPU time 4.02 seconds
Started Aug 17 06:28:51 PM PDT 24
Finished Aug 17 06:28:56 PM PDT 24
Peak memory 211364 kb
Host smart-9f8be1c4-bb91-427f-8115-2324dcc7e57f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362047487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3362047487
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4293350905
Short name T364
Test name
Test status
Simulation time 127226423 ps
CPU time 5.08 seconds
Started Aug 17 06:29:20 PM PDT 24
Finished Aug 17 06:29:25 PM PDT 24
Peak memory 211404 kb
Host smart-b2f42d69-ff99-4da9-9185-245fc0f5c82e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293350905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.4293350905
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.573073271
Short name T384
Test name
Test status
Simulation time 96310469 ps
CPU time 7.43 seconds
Started Aug 17 06:28:43 PM PDT 24
Finished Aug 17 06:28:51 PM PDT 24
Peak memory 211404 kb
Host smart-be7d86a5-96a5-411f-a27a-da01bb9b7b1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573073271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.573073271
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1016927124
Short name T402
Test name
Test status
Simulation time 380940649 ps
CPU time 4.5 seconds
Started Aug 17 06:28:50 PM PDT 24
Finished Aug 17 06:28:55 PM PDT 24
Peak memory 214748 kb
Host smart-02b07bbe-8ba8-4318-9792-a5086184f65f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016927124 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1016927124
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3131471333
Short name T389
Test name
Test status
Simulation time 249242443 ps
CPU time 4.81 seconds
Started Aug 17 06:28:43 PM PDT 24
Finished Aug 17 06:28:48 PM PDT 24
Peak memory 211376 kb
Host smart-f7faa148-deac-408d-a317-d93a676b0043
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131471333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3131471333
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1070696827
Short name T388
Test name
Test status
Simulation time 132890743 ps
CPU time 4.64 seconds
Started Aug 17 06:28:59 PM PDT 24
Finished Aug 17 06:29:04 PM PDT 24
Peak memory 211352 kb
Host smart-3ed7c776-c999-43e4-98ff-17ff5ca450ae
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070696827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1070696827
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3635681370
Short name T383
Test name
Test status
Simulation time 521441246 ps
CPU time 4.81 seconds
Started Aug 17 06:29:05 PM PDT 24
Finished Aug 17 06:29:10 PM PDT 24
Peak memory 211260 kb
Host smart-b57c7366-0f5c-41d2-bca6-14ec845704b4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635681370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3635681370
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.605378162
Short name T439
Test name
Test status
Simulation time 97593100 ps
CPU time 7.02 seconds
Started Aug 17 06:29:12 PM PDT 24
Finished Aug 17 06:29:19 PM PDT 24
Peak memory 216492 kb
Host smart-74cfc64b-8829-416d-a1db-fc0817a4ead9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605378162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.605378162
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3727818401
Short name T56
Test name
Test status
Simulation time 353100981 ps
CPU time 40.17 seconds
Started Aug 17 06:29:23 PM PDT 24
Finished Aug 17 06:30:03 PM PDT 24
Peak memory 213076 kb
Host smart-9226af3c-b3d1-4d83-bf63-4e8dd1363f43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727818401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3727818401
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2272874096
Short name T451
Test name
Test status
Simulation time 1554293161 ps
CPU time 5.12 seconds
Started Aug 17 06:29:02 PM PDT 24
Finished Aug 17 06:29:07 PM PDT 24
Peak memory 218352 kb
Host smart-31d70d50-5487-488b-a3e9-202c12cec521
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272874096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2272874096
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2709204877
Short name T396
Test name
Test status
Simulation time 340137132 ps
CPU time 5.35 seconds
Started Aug 17 06:29:20 PM PDT 24
Finished Aug 17 06:29:26 PM PDT 24
Peak memory 211412 kb
Host smart-0f2fa329-6a67-4afe-a4e9-786b7912e442
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709204877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2709204877
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.988021629
Short name T399
Test name
Test status
Simulation time 480756881 ps
CPU time 5.63 seconds
Started Aug 17 06:29:12 PM PDT 24
Finished Aug 17 06:29:18 PM PDT 24
Peak memory 219556 kb
Host smart-aa8a7d5e-2f33-4da3-88b5-0444723d358f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988021629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.988021629
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.876676805
Short name T425
Test name
Test status
Simulation time 558171992 ps
CPU time 5.33 seconds
Started Aug 17 06:28:51 PM PDT 24
Finished Aug 17 06:28:56 PM PDT 24
Peak memory 215204 kb
Host smart-864d906b-c84a-4c3a-8102-9b455658eeaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876676805 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.876676805
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3841578114
Short name T87
Test name
Test status
Simulation time 88038354 ps
CPU time 4.11 seconds
Started Aug 17 06:28:51 PM PDT 24
Finished Aug 17 06:28:55 PM PDT 24
Peak memory 219520 kb
Host smart-66a221fb-8f5d-4005-a389-5f73f50cf1ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841578114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3841578114
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1341149208
Short name T440
Test name
Test status
Simulation time 832774285 ps
CPU time 4.71 seconds
Started Aug 17 06:28:52 PM PDT 24
Finished Aug 17 06:28:56 PM PDT 24
Peak memory 211308 kb
Host smart-8a6ec33a-0e09-454e-a08f-f8be962fa503
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341149208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1341149208
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2066991580
Short name T410
Test name
Test status
Simulation time 1186289269 ps
CPU time 4.09 seconds
Started Aug 17 06:29:00 PM PDT 24
Finished Aug 17 06:29:04 PM PDT 24
Peak memory 211324 kb
Host smart-3bb5874d-fff0-4ead-9d2e-f5d890549d54
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066991580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2066991580
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1669685798
Short name T74
Test name
Test status
Simulation time 380735806 ps
CPU time 17.95 seconds
Started Aug 17 06:29:12 PM PDT 24
Finished Aug 17 06:29:30 PM PDT 24
Peak memory 211420 kb
Host smart-1385fbb2-aedd-4b6a-914e-4e00eb05d00e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669685798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1669685798
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2509741942
Short name T448
Test name
Test status
Simulation time 140869530 ps
CPU time 6.74 seconds
Started Aug 17 06:29:13 PM PDT 24
Finished Aug 17 06:29:20 PM PDT 24
Peak memory 219552 kb
Host smart-1ac4eae8-5450-4344-ba7e-213607a64d1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509741942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2509741942
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2975804942
Short name T372
Test name
Test status
Simulation time 480935169 ps
CPU time 8.25 seconds
Started Aug 17 06:29:03 PM PDT 24
Finished Aug 17 06:29:11 PM PDT 24
Peak memory 216588 kb
Host smart-45a9e7e5-2d40-4d54-a3d1-9bf71faf4f78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975804942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2975804942
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1788570962
Short name T57
Test name
Test status
Simulation time 795815893 ps
CPU time 37.24 seconds
Started Aug 17 06:29:07 PM PDT 24
Finished Aug 17 06:29:45 PM PDT 24
Peak memory 211992 kb
Host smart-3ed9d434-6175-4b45-8d3f-015e79fcfd8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788570962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1788570962
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.20260010
Short name T447
Test name
Test status
Simulation time 1215378827 ps
CPU time 5.78 seconds
Started Aug 17 06:28:49 PM PDT 24
Finished Aug 17 06:29:00 PM PDT 24
Peak memory 216396 kb
Host smart-e796da73-df8a-43bd-9ee0-555bd221b00f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20260010 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.20260010
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1432268953
Short name T441
Test name
Test status
Simulation time 90224406 ps
CPU time 4.14 seconds
Started Aug 17 06:29:20 PM PDT 24
Finished Aug 17 06:29:24 PM PDT 24
Peak memory 211412 kb
Host smart-7dc6e66c-1c86-4982-986a-f701e936a7c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432268953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1432268953
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4212544206
Short name T85
Test name
Test status
Simulation time 1785720283 ps
CPU time 26.64 seconds
Started Aug 17 06:29:01 PM PDT 24
Finished Aug 17 06:29:28 PM PDT 24
Peak memory 211416 kb
Host smart-e4ede017-7c58-4287-a8dc-d57451a82912
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212544206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4212544206
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2517959219
Short name T110
Test name
Test status
Simulation time 127910089 ps
CPU time 5.06 seconds
Started Aug 17 06:29:17 PM PDT 24
Finished Aug 17 06:29:22 PM PDT 24
Peak memory 211400 kb
Host smart-b1a14fe1-4148-4f57-bf0b-057fed2cfcb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517959219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2517959219
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1668141767
Short name T377
Test name
Test status
Simulation time 263061653 ps
CPU time 8.76 seconds
Started Aug 17 06:28:48 PM PDT 24
Finished Aug 17 06:28:58 PM PDT 24
Peak memory 215496 kb
Host smart-7330f212-4d36-4163-83e2-1847cf88fd9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668141767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1668141767
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.637389402
Short name T128
Test name
Test status
Simulation time 411348265 ps
CPU time 72.97 seconds
Started Aug 17 06:29:13 PM PDT 24
Finished Aug 17 06:30:26 PM PDT 24
Peak memory 219504 kb
Host smart-ba96d632-7971-4383-8fa8-a56d2e91a42e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637389402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.637389402
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.619711968
Short name T416
Test name
Test status
Simulation time 320875517 ps
CPU time 4.59 seconds
Started Aug 17 06:29:18 PM PDT 24
Finished Aug 17 06:29:23 PM PDT 24
Peak memory 219632 kb
Host smart-96396a69-863c-492f-815c-fe5178df0796
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619711968 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.619711968
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3016127386
Short name T403
Test name
Test status
Simulation time 1035086248 ps
CPU time 4.7 seconds
Started Aug 17 06:29:31 PM PDT 24
Finished Aug 17 06:29:35 PM PDT 24
Peak memory 211440 kb
Host smart-f059a39b-f88c-4079-82f8-1c097893d905
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016127386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3016127386
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2552887628
Short name T84
Test name
Test status
Simulation time 808361895 ps
CPU time 31.16 seconds
Started Aug 17 06:29:05 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 212404 kb
Host smart-a5b5db60-feee-4f9f-8ce4-d466c088139f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552887628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2552887628
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3723768250
Short name T430
Test name
Test status
Simulation time 91068307 ps
CPU time 5.64 seconds
Started Aug 17 06:29:12 PM PDT 24
Finished Aug 17 06:29:18 PM PDT 24
Peak memory 219556 kb
Host smart-dddef422-7d27-4410-8cb2-41737d51a988
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723768250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3723768250
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3407559253
Short name T446
Test name
Test status
Simulation time 162725684 ps
CPU time 9.42 seconds
Started Aug 17 06:28:49 PM PDT 24
Finished Aug 17 06:28:58 PM PDT 24
Peak memory 216448 kb
Host smart-396ef516-21ce-4fb3-99d2-715fda3dfc7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407559253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3407559253
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2297984274
Short name T129
Test name
Test status
Simulation time 500572081 ps
CPU time 67.7 seconds
Started Aug 17 06:28:59 PM PDT 24
Finished Aug 17 06:30:07 PM PDT 24
Peak memory 219576 kb
Host smart-bb1eaf0a-dfa6-45cb-8760-6d9a041aa2ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297984274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2297984274
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1988280785
Short name T431
Test name
Test status
Simulation time 199554203 ps
CPU time 5.31 seconds
Started Aug 17 06:29:31 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 215300 kb
Host smart-14db27b1-f394-41b8-b599-678fc7bbf114
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988280785 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1988280785
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1471549080
Short name T386
Test name
Test status
Simulation time 171154464 ps
CPU time 4.03 seconds
Started Aug 17 06:29:04 PM PDT 24
Finished Aug 17 06:29:08 PM PDT 24
Peak memory 211272 kb
Host smart-0f6626a4-477a-4c68-a389-3efc040c30ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471549080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1471549080
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1046925964
Short name T95
Test name
Test status
Simulation time 1990338801 ps
CPU time 27.21 seconds
Started Aug 17 06:29:04 PM PDT 24
Finished Aug 17 06:29:32 PM PDT 24
Peak memory 211416 kb
Host smart-6d1e5060-14e8-4ae5-a5f5-4b5d898788b6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046925964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1046925964
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2096636754
Short name T400
Test name
Test status
Simulation time 334146954 ps
CPU time 4.1 seconds
Started Aug 17 06:29:10 PM PDT 24
Finished Aug 17 06:29:15 PM PDT 24
Peak memory 218748 kb
Host smart-0c323968-ff0a-4266-ab31-9ad5e711c310
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096636754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2096636754
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1019608606
Short name T370
Test name
Test status
Simulation time 132659716 ps
CPU time 9.04 seconds
Started Aug 17 06:28:43 PM PDT 24
Finished Aug 17 06:28:52 PM PDT 24
Peak memory 215464 kb
Host smart-0b65d3aa-dba5-4f07-869d-86636f310338
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019608606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1019608606
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2984624785
Short name T130
Test name
Test status
Simulation time 765522007 ps
CPU time 78.9 seconds
Started Aug 17 06:28:58 PM PDT 24
Finished Aug 17 06:30:17 PM PDT 24
Peak memory 214200 kb
Host smart-91b874db-b577-4936-9f98-7e6dd0720fbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984624785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2984624785
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2111462163
Short name T427
Test name
Test status
Simulation time 210305016 ps
CPU time 5.18 seconds
Started Aug 17 06:29:15 PM PDT 24
Finished Aug 17 06:29:20 PM PDT 24
Peak memory 219628 kb
Host smart-c5c6bfbf-d1dc-46d2-83f0-8bc798f25d83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111462163 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2111462163
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3166594792
Short name T398
Test name
Test status
Simulation time 210619414 ps
CPU time 4.9 seconds
Started Aug 17 06:29:18 PM PDT 24
Finished Aug 17 06:29:23 PM PDT 24
Peak memory 211416 kb
Host smart-070c0bf4-ff0c-4b9e-9848-10d62edac415
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166594792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3166594792
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1452747746
Short name T414
Test name
Test status
Simulation time 1505600416 ps
CPU time 17.73 seconds
Started Aug 17 06:28:51 PM PDT 24
Finished Aug 17 06:29:08 PM PDT 24
Peak memory 211400 kb
Host smart-53582be5-f00e-4a64-a1fd-a1ca980f7a11
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452747746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1452747746
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2574114234
Short name T429
Test name
Test status
Simulation time 183539665 ps
CPU time 4.04 seconds
Started Aug 17 06:28:51 PM PDT 24
Finished Aug 17 06:28:55 PM PDT 24
Peak memory 211408 kb
Host smart-64b8b78c-5e18-472a-bde1-d21ea08ddb37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574114234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2574114234
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.860403518
Short name T387
Test name
Test status
Simulation time 321802086 ps
CPU time 8.74 seconds
Started Aug 17 06:28:51 PM PDT 24
Finished Aug 17 06:29:00 PM PDT 24
Peak memory 219604 kb
Host smart-4684599c-979f-4cf5-aaf7-541dab71de47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860403518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.860403518
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3105245145
Short name T444
Test name
Test status
Simulation time 784858592 ps
CPU time 36.78 seconds
Started Aug 17 06:28:48 PM PDT 24
Finished Aug 17 06:29:25 PM PDT 24
Peak memory 219496 kb
Host smart-b325c9e3-fe0f-4eb7-9151-6f00f639ee1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105245145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3105245145
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2658336924
Short name T397
Test name
Test status
Simulation time 288754634 ps
CPU time 5.26 seconds
Started Aug 17 06:29:29 PM PDT 24
Finished Aug 17 06:29:35 PM PDT 24
Peak memory 219660 kb
Host smart-1b26e125-919f-4075-b144-26aabcb685b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658336924 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2658336924
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2845901720
Short name T83
Test name
Test status
Simulation time 89664442 ps
CPU time 4.18 seconds
Started Aug 17 06:29:07 PM PDT 24
Finished Aug 17 06:29:11 PM PDT 24
Peak memory 211408 kb
Host smart-295ec268-2d8c-47ca-b21c-cad2840cd2da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845901720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2845901720
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2556422748
Short name T89
Test name
Test status
Simulation time 3270307801 ps
CPU time 30.32 seconds
Started Aug 17 06:29:22 PM PDT 24
Finished Aug 17 06:29:53 PM PDT 24
Peak memory 211496 kb
Host smart-6363623e-256b-4ad8-84d5-e60e4dc7248b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556422748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2556422748
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3027012266
Short name T73
Test name
Test status
Simulation time 256933102 ps
CPU time 4.78 seconds
Started Aug 17 06:29:05 PM PDT 24
Finished Aug 17 06:29:10 PM PDT 24
Peak memory 211400 kb
Host smart-4937da6d-1239-4c0b-8879-7873ae74e5ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027012266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3027012266
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2224560961
Short name T453
Test name
Test status
Simulation time 127785670 ps
CPU time 8.81 seconds
Started Aug 17 06:29:27 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 218032 kb
Host smart-6c8ca675-9af8-4b9b-9851-e33a56bba5db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224560961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2224560961
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.547656909
Short name T121
Test name
Test status
Simulation time 1479622493 ps
CPU time 68.83 seconds
Started Aug 17 06:29:29 PM PDT 24
Finished Aug 17 06:30:37 PM PDT 24
Peak memory 213176 kb
Host smart-2193f015-76ec-483f-bd72-6b17c726d022
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547656909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.547656909
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.344309463
Short name T55
Test name
Test status
Simulation time 87009701 ps
CPU time 3.99 seconds
Started Aug 17 06:38:41 PM PDT 24
Finished Aug 17 06:38:45 PM PDT 24
Peak memory 211112 kb
Host smart-dbc0e202-da7c-4ece-a58d-a672c2e1552d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344309463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.344309463
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1759407108
Short name T144
Test name
Test status
Simulation time 176803948 ps
CPU time 8.89 seconds
Started Aug 17 06:38:39 PM PDT 24
Finished Aug 17 06:38:48 PM PDT 24
Peak memory 211680 kb
Host smart-d2d8a5a0-11d1-4429-9030-5ea94949c854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759407108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1759407108
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2277130699
Short name T355
Test name
Test status
Simulation time 281201107 ps
CPU time 5.96 seconds
Started Aug 17 06:38:49 PM PDT 24
Finished Aug 17 06:38:55 PM PDT 24
Peak memory 211088 kb
Host smart-8f41fc47-d0ae-4a46-9c1a-f45c35b08616
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2277130699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2277130699
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1098803556
Short name T106
Test name
Test status
Simulation time 1895092506 ps
CPU time 6.04 seconds
Started Aug 17 06:38:57 PM PDT 24
Finished Aug 17 06:39:03 PM PDT 24
Peak memory 211320 kb
Host smart-ace8bb33-d845-472a-94f5-51d33f3d481d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098803556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1098803556
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2095859277
Short name T120
Test name
Test status
Simulation time 2367390468 ps
CPU time 12.59 seconds
Started Aug 17 06:38:50 PM PDT 24
Finished Aug 17 06:39:02 PM PDT 24
Peak memory 212480 kb
Host smart-4ce6f966-688e-4ad9-bdd6-9b19cd63680e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095859277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2095859277
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3336021816
Short name T12
Test name
Test status
Simulation time 3445978638 ps
CPU time 66.77 seconds
Started Aug 17 06:38:41 PM PDT 24
Finished Aug 17 06:39:48 PM PDT 24
Peak memory 221704 kb
Host smart-351e062a-17c8-487a-8b34-44c2e7b0ff0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336021816 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.3336021816
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1901408691
Short name T182
Test name
Test status
Simulation time 127326054 ps
CPU time 4.99 seconds
Started Aug 17 06:38:42 PM PDT 24
Finished Aug 17 06:38:47 PM PDT 24
Peak memory 211136 kb
Host smart-b00a8bef-2c9a-4713-a9ec-b6b5531f210a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901408691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1901408691
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2260443463
Short name T243
Test name
Test status
Simulation time 25729874515 ps
CPU time 173.63 seconds
Started Aug 17 06:38:40 PM PDT 24
Finished Aug 17 06:41:34 PM PDT 24
Peak memory 234952 kb
Host smart-a648b9cc-c42a-416a-925a-db60ca5caf9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260443463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2260443463
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2101809417
Short name T220
Test name
Test status
Simulation time 619999900 ps
CPU time 9.17 seconds
Started Aug 17 06:38:42 PM PDT 24
Finished Aug 17 06:38:51 PM PDT 24
Peak memory 211644 kb
Host smart-13211069-df4d-49ac-bb6c-93a498be096a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101809417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2101809417
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2792350889
Short name T25
Test name
Test status
Simulation time 192817926 ps
CPU time 52.39 seconds
Started Aug 17 06:38:39 PM PDT 24
Finished Aug 17 06:39:32 PM PDT 24
Peak memory 234980 kb
Host smart-739f6157-402f-4d0d-8acf-1f5294601aa1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792350889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2792350889
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.757174367
Short name T172
Test name
Test status
Simulation time 139255601 ps
CPU time 6.51 seconds
Started Aug 17 06:38:43 PM PDT 24
Finished Aug 17 06:38:49 PM PDT 24
Peak memory 211252 kb
Host smart-5e7a445f-00f0-4d4a-a711-333155caab9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757174367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.757174367
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2720993841
Short name T270
Test name
Test status
Simulation time 278788060 ps
CPU time 14.58 seconds
Started Aug 17 06:38:51 PM PDT 24
Finished Aug 17 06:39:06 PM PDT 24
Peak memory 213632 kb
Host smart-45a32f42-5ce3-445c-b775-36b7a9f45fda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720993841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2720993841
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3988150592
Short name T329
Test name
Test status
Simulation time 11627152330 ps
CPU time 189.53 seconds
Started Aug 17 06:38:42 PM PDT 24
Finished Aug 17 06:41:52 PM PDT 24
Peak memory 222692 kb
Host smart-013f3be8-4a47-4ba5-82d7-41e3b524a250
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988150592 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.3988150592
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1277967131
Short name T224
Test name
Test status
Simulation time 85640778 ps
CPU time 4.1 seconds
Started Aug 17 06:38:55 PM PDT 24
Finished Aug 17 06:39:00 PM PDT 24
Peak memory 211100 kb
Host smart-ca54936b-7c1e-47f5-b449-f8a7afb9de09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277967131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1277967131
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3911634998
Short name T238
Test name
Test status
Simulation time 7096066210 ps
CPU time 164.35 seconds
Started Aug 17 06:38:49 PM PDT 24
Finished Aug 17 06:41:33 PM PDT 24
Peak memory 237712 kb
Host smart-8ad26b38-aef4-44a7-87ff-18864a5c8ca0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911634998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3911634998
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2598723532
Short name T262
Test name
Test status
Simulation time 303598332 ps
CPU time 6.22 seconds
Started Aug 17 06:38:54 PM PDT 24
Finished Aug 17 06:39:00 PM PDT 24
Peak memory 211152 kb
Host smart-609b72a2-90f7-4d7e-abcc-c42d9454ce91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2598723532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2598723532
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3532614700
Short name T360
Test name
Test status
Simulation time 867552436 ps
CPU time 19.11 seconds
Started Aug 17 06:38:45 PM PDT 24
Finished Aug 17 06:39:04 PM PDT 24
Peak memory 215464 kb
Host smart-bee88bcd-8c6e-4ea6-9fbf-596e9decd306
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532614700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3532614700
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1361057354
Short name T137
Test name
Test status
Simulation time 4049196390 ps
CPU time 270.5 seconds
Started Aug 17 06:38:56 PM PDT 24
Finished Aug 17 06:43:27 PM PDT 24
Peak memory 230972 kb
Host smart-d4d38b18-6093-43ed-abcd-c48cad187ee7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361057354 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1361057354
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3064212639
Short name T327
Test name
Test status
Simulation time 498558664 ps
CPU time 4.84 seconds
Started Aug 17 06:38:56 PM PDT 24
Finished Aug 17 06:39:01 PM PDT 24
Peak memory 211128 kb
Host smart-b8056ef9-30e6-4b14-a758-70c775af24ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064212639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3064212639
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2221471696
Short name T23
Test name
Test status
Simulation time 13772846832 ps
CPU time 129.66 seconds
Started Aug 17 06:38:55 PM PDT 24
Finished Aug 17 06:41:05 PM PDT 24
Peak memory 236696 kb
Host smart-4c7f660e-c709-468d-9d5b-623032da152f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221471696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2221471696
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.197607495
Short name T286
Test name
Test status
Simulation time 830535280 ps
CPU time 8.99 seconds
Started Aug 17 06:39:01 PM PDT 24
Finished Aug 17 06:39:10 PM PDT 24
Peak memory 211512 kb
Host smart-d289449f-38e8-412b-9b72-cd8fc1a6b690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197607495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.197607495
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.4034782660
Short name T280
Test name
Test status
Simulation time 140773469 ps
CPU time 6.05 seconds
Started Aug 17 06:39:02 PM PDT 24
Finished Aug 17 06:39:08 PM PDT 24
Peak memory 211124 kb
Host smart-d948d6b5-63fe-490c-ac3a-2c2bb7d589f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4034782660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.4034782660
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.638664843
Short name T102
Test name
Test status
Simulation time 595328790 ps
CPU time 15.18 seconds
Started Aug 17 06:39:12 PM PDT 24
Finished Aug 17 06:39:28 PM PDT 24
Peak memory 213800 kb
Host smart-a333bddd-a8b2-4077-a7d2-34fd8023f68c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638664843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.638664843
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2463508773
Short name T314
Test name
Test status
Simulation time 737571184 ps
CPU time 4.99 seconds
Started Aug 17 06:38:53 PM PDT 24
Finished Aug 17 06:38:59 PM PDT 24
Peak memory 211148 kb
Host smart-1c869828-866c-4a60-94fe-755bf09ad130
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463508773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2463508773
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1313895084
Short name T241
Test name
Test status
Simulation time 10635480956 ps
CPU time 81.15 seconds
Started Aug 17 06:38:48 PM PDT 24
Finished Aug 17 06:40:09 PM PDT 24
Peak memory 227112 kb
Host smart-0b7eed40-bfd8-4d62-9121-cf6e857ac924
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313895084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1313895084
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3963882957
Short name T350
Test name
Test status
Simulation time 320958154 ps
CPU time 9.15 seconds
Started Aug 17 06:39:00 PM PDT 24
Finished Aug 17 06:39:09 PM PDT 24
Peak memory 211528 kb
Host smart-c88f5e69-e734-459d-af37-a6e545543ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963882957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3963882957
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1117814883
Short name T309
Test name
Test status
Simulation time 141753500 ps
CPU time 5.98 seconds
Started Aug 17 06:38:45 PM PDT 24
Finished Aug 17 06:38:51 PM PDT 24
Peak memory 211088 kb
Host smart-17e74098-0ad9-4f59-86c5-d34007369c03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1117814883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1117814883
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2828019685
Short name T306
Test name
Test status
Simulation time 13149885631 ps
CPU time 246.24 seconds
Started Aug 17 06:38:45 PM PDT 24
Finished Aug 17 06:42:52 PM PDT 24
Peak memory 224592 kb
Host smart-d6cb4449-3eb1-43e6-ba3a-2c3900ded1da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828019685 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.2828019685
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1095999233
Short name T299
Test name
Test status
Simulation time 520542860 ps
CPU time 6.89 seconds
Started Aug 17 06:38:46 PM PDT 24
Finished Aug 17 06:38:53 PM PDT 24
Peak memory 211064 kb
Host smart-ac0fdb86-6578-4bb2-aef4-ad6a79f1fb32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095999233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1095999233
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2353372296
Short name T303
Test name
Test status
Simulation time 2587977316 ps
CPU time 76.34 seconds
Started Aug 17 06:38:46 PM PDT 24
Finished Aug 17 06:40:03 PM PDT 24
Peak memory 237736 kb
Host smart-42ed12ca-4aa2-4d43-84eb-bdf0769a690b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353372296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2353372296
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3881178612
Short name T328
Test name
Test status
Simulation time 1038996712 ps
CPU time 10.37 seconds
Started Aug 17 06:38:51 PM PDT 24
Finished Aug 17 06:39:01 PM PDT 24
Peak memory 211520 kb
Host smart-7018cd92-1be1-4958-a686-1460f010b2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881178612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3881178612
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.742992661
Short name T279
Test name
Test status
Simulation time 741089837 ps
CPU time 5.88 seconds
Started Aug 17 06:38:45 PM PDT 24
Finished Aug 17 06:38:51 PM PDT 24
Peak memory 211140 kb
Host smart-133d4b20-a1e6-4d29-9397-5e204255d40c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=742992661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.742992661
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.382559546
Short name T22
Test name
Test status
Simulation time 211698187 ps
CPU time 15 seconds
Started Aug 17 06:39:00 PM PDT 24
Finished Aug 17 06:39:15 PM PDT 24
Peak memory 213744 kb
Host smart-ecc9cc71-61ba-4aa9-a1e8-009c297c827a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382559546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.382559546
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2858098194
Short name T169
Test name
Test status
Simulation time 3190002233 ps
CPU time 71.6 seconds
Started Aug 17 06:38:44 PM PDT 24
Finished Aug 17 06:39:56 PM PDT 24
Peak memory 228552 kb
Host smart-e9feb49b-932f-4e52-b138-30034bccec98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858098194 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.2858098194
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1387792435
Short name T2
Test name
Test status
Simulation time 1210506779 ps
CPU time 75.34 seconds
Started Aug 17 06:39:12 PM PDT 24
Finished Aug 17 06:40:27 PM PDT 24
Peak memory 235868 kb
Host smart-08979170-d750-4596-98e6-16c9172f1c5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387792435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1387792435
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.351744387
Short name T175
Test name
Test status
Simulation time 398610620 ps
CPU time 8.99 seconds
Started Aug 17 06:38:58 PM PDT 24
Finished Aug 17 06:39:07 PM PDT 24
Peak memory 211536 kb
Host smart-fb0cdf85-786f-430c-9591-deabd3e63dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351744387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.351744387
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2427907865
Short name T116
Test name
Test status
Simulation time 273673738 ps
CPU time 5.75 seconds
Started Aug 17 06:38:57 PM PDT 24
Finished Aug 17 06:39:03 PM PDT 24
Peak memory 211124 kb
Host smart-184b6699-4e56-4659-8251-9d14513df860
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2427907865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2427907865
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3320355889
Short name T78
Test name
Test status
Simulation time 423475535 ps
CPU time 19.25 seconds
Started Aug 17 06:38:42 PM PDT 24
Finished Aug 17 06:39:02 PM PDT 24
Peak memory 215368 kb
Host smart-23739154-2acc-41eb-b55c-cf469bc34295
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320355889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3320355889
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1867002672
Short name T260
Test name
Test status
Simulation time 127205858 ps
CPU time 4.83 seconds
Started Aug 17 06:39:10 PM PDT 24
Finished Aug 17 06:39:15 PM PDT 24
Peak memory 211124 kb
Host smart-322cf8b9-ac5c-4da3-8435-891faa75ef03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867002672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1867002672
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.249993963
Short name T338
Test name
Test status
Simulation time 1845049222 ps
CPU time 104.58 seconds
Started Aug 17 06:38:58 PM PDT 24
Finished Aug 17 06:40:43 PM PDT 24
Peak memory 212428 kb
Host smart-b0958ca9-0eb0-4c07-b72b-ddf19a9cbc47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249993963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.249993963
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1334759762
Short name T3
Test name
Test status
Simulation time 1515454259 ps
CPU time 9.32 seconds
Started Aug 17 06:38:45 PM PDT 24
Finished Aug 17 06:38:54 PM PDT 24
Peak memory 211112 kb
Host smart-a724618f-c5c9-4ada-903f-419eecb6ebbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334759762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1334759762
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.4024278227
Short name T146
Test name
Test status
Simulation time 139618786 ps
CPU time 6.18 seconds
Started Aug 17 06:38:58 PM PDT 24
Finished Aug 17 06:39:04 PM PDT 24
Peak memory 211152 kb
Host smart-95df8668-1489-468e-8429-ed27ca9b14d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4024278227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.4024278227
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2890994238
Short name T288
Test name
Test status
Simulation time 289473011 ps
CPU time 12.52 seconds
Started Aug 17 06:39:05 PM PDT 24
Finished Aug 17 06:39:18 PM PDT 24
Peak memory 213128 kb
Host smart-0ae98d26-b9de-499e-a7a0-cad075e77087
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890994238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2890994238
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.927833669
Short name T351
Test name
Test status
Simulation time 1116363051 ps
CPU time 46.73 seconds
Started Aug 17 06:38:45 PM PDT 24
Finished Aug 17 06:39:32 PM PDT 24
Peak memory 220580 kb
Host smart-ae4f27ec-4f98-4b20-bf89-622ec53e98d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927833669 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.927833669
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.850938725
Short name T344
Test name
Test status
Simulation time 566653584 ps
CPU time 4.84 seconds
Started Aug 17 06:39:01 PM PDT 24
Finished Aug 17 06:39:06 PM PDT 24
Peak memory 210108 kb
Host smart-902e4f99-dbd9-4ad6-a7e6-ce763c914b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850938725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.850938725
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2817336398
Short name T163
Test name
Test status
Simulation time 1479606970 ps
CPU time 90.97 seconds
Started Aug 17 06:38:58 PM PDT 24
Finished Aug 17 06:40:29 PM PDT 24
Peak memory 236520 kb
Host smart-a1f44e9f-8ef0-4c1a-b3e7-304660b3f310
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817336398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2817336398
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.575291654
Short name T31
Test name
Test status
Simulation time 4961999278 ps
CPU time 10.79 seconds
Started Aug 17 06:38:56 PM PDT 24
Finished Aug 17 06:39:07 PM PDT 24
Peak memory 211876 kb
Host smart-f2b5bca1-f4bf-422a-b283-e55e4622c953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575291654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.575291654
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.35928752
Short name T104
Test name
Test status
Simulation time 409399018 ps
CPU time 5.29 seconds
Started Aug 17 06:38:49 PM PDT 24
Finished Aug 17 06:38:54 PM PDT 24
Peak memory 211148 kb
Host smart-4dfe46ab-cf3e-4fa1-982f-e15a7b4685f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=35928752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.35928752
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1943998022
Short name T278
Test name
Test status
Simulation time 581811598 ps
CPU time 14.74 seconds
Started Aug 17 06:38:51 PM PDT 24
Finished Aug 17 06:39:06 PM PDT 24
Peak memory 214672 kb
Host smart-cd4bd628-2405-4348-b6c7-30137727ebb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943998022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1943998022
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1685507257
Short name T213
Test name
Test status
Simulation time 3212780318 ps
CPU time 42.27 seconds
Started Aug 17 06:38:45 PM PDT 24
Finished Aug 17 06:39:27 PM PDT 24
Peak memory 222616 kb
Host smart-58edbc3b-3114-4d65-9f45-ba44ced6f07f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685507257 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1685507257
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2376630000
Short name T250
Test name
Test status
Simulation time 89198163 ps
CPU time 4.21 seconds
Started Aug 17 06:38:55 PM PDT 24
Finished Aug 17 06:39:00 PM PDT 24
Peak memory 211124 kb
Host smart-c3e62af3-5af1-4e22-9123-c82a01fea4cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376630000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2376630000
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1450237408
Short name T248
Test name
Test status
Simulation time 13536724401 ps
CPU time 224.97 seconds
Started Aug 17 06:39:03 PM PDT 24
Finished Aug 17 06:42:48 PM PDT 24
Peak memory 234680 kb
Host smart-601b03ab-2f39-4bf1-9b70-53e33c900f79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450237408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1450237408
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1949103407
Short name T39
Test name
Test status
Simulation time 499506023 ps
CPU time 10.57 seconds
Started Aug 17 06:38:52 PM PDT 24
Finished Aug 17 06:39:03 PM PDT 24
Peak memory 211520 kb
Host smart-bb51bdc6-703a-41e4-9ed6-ea964124330a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949103407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1949103407
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.379242045
Short name T232
Test name
Test status
Simulation time 532711111 ps
CPU time 5.81 seconds
Started Aug 17 06:38:58 PM PDT 24
Finished Aug 17 06:39:04 PM PDT 24
Peak memory 211156 kb
Host smart-210f7fc6-b399-4cc4-85c1-3911e1038366
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=379242045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.379242045
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2578304366
Short name T44
Test name
Test status
Simulation time 386362216 ps
CPU time 8.24 seconds
Started Aug 17 06:39:09 PM PDT 24
Finished Aug 17 06:39:18 PM PDT 24
Peak memory 212256 kb
Host smart-30169d11-0c4b-4d25-b81c-c6ab095fcf1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578304366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2578304366
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2842885419
Short name T13
Test name
Test status
Simulation time 3484887851 ps
CPU time 188.08 seconds
Started Aug 17 06:38:58 PM PDT 24
Finished Aug 17 06:42:06 PM PDT 24
Peak memory 222900 kb
Host smart-d9846cee-f3bb-496e-b6dd-27f2c6c74cab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842885419 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2842885419
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1546523274
Short name T240
Test name
Test status
Simulation time 87954187 ps
CPU time 4.11 seconds
Started Aug 17 06:39:19 PM PDT 24
Finished Aug 17 06:39:24 PM PDT 24
Peak memory 211108 kb
Host smart-c0ddf25d-c2ac-4ff7-bf26-a6b536e4de1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546523274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1546523274
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3708573715
Short name T296
Test name
Test status
Simulation time 2350037794 ps
CPU time 129.59 seconds
Started Aug 17 06:38:48 PM PDT 24
Finished Aug 17 06:40:57 PM PDT 24
Peak memory 236184 kb
Host smart-c3a8dc37-38f4-410c-9569-9f01704f566b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708573715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3708573715
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.72638534
Short name T187
Test name
Test status
Simulation time 258742903 ps
CPU time 10.48 seconds
Started Aug 17 06:38:48 PM PDT 24
Finished Aug 17 06:38:58 PM PDT 24
Peak memory 211536 kb
Host smart-ca8f907d-3a98-432e-8b2c-ce0ef752e35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72638534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.72638534
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1918286647
Short name T217
Test name
Test status
Simulation time 138931500 ps
CPU time 6.19 seconds
Started Aug 17 06:38:58 PM PDT 24
Finished Aug 17 06:39:09 PM PDT 24
Peak memory 211152 kb
Host smart-77c57ae6-0c80-4022-84c4-6e5607a483b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1918286647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1918286647
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2479075841
Short name T15
Test name
Test status
Simulation time 198936144 ps
CPU time 7.19 seconds
Started Aug 17 06:38:55 PM PDT 24
Finished Aug 17 06:39:03 PM PDT 24
Peak memory 211836 kb
Host smart-10a7433a-fc9e-4b8e-a184-f78d54b359bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479075841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2479075841
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1401346308
Short name T43
Test name
Test status
Simulation time 2025695171 ps
CPU time 111.23 seconds
Started Aug 17 06:38:43 PM PDT 24
Finished Aug 17 06:40:34 PM PDT 24
Peak memory 220940 kb
Host smart-e0c39a0a-9ee3-44c9-87fc-e74bbe1a3819
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401346308 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.1401346308
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.4099233429
Short name T194
Test name
Test status
Simulation time 166974041 ps
CPU time 4.01 seconds
Started Aug 17 06:38:58 PM PDT 24
Finished Aug 17 06:39:02 PM PDT 24
Peak memory 211136 kb
Host smart-c575ef71-84a7-4f52-a599-5cf64b8f413b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099233429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.4099233429
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2449829057
Short name T342
Test name
Test status
Simulation time 2339813643 ps
CPU time 107.84 seconds
Started Aug 17 06:38:54 PM PDT 24
Finished Aug 17 06:40:42 PM PDT 24
Peak memory 236284 kb
Host smart-820d8096-0fcf-4caf-9cfc-c23b22313bdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449829057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2449829057
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1761686397
Short name T161
Test name
Test status
Simulation time 250828218 ps
CPU time 10.61 seconds
Started Aug 17 06:38:55 PM PDT 24
Finished Aug 17 06:39:06 PM PDT 24
Peak memory 211516 kb
Host smart-3fc06470-92f6-49ff-8ccf-445798f466c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761686397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1761686397
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3504853079
Short name T20
Test name
Test status
Simulation time 137427370 ps
CPU time 5.98 seconds
Started Aug 17 06:39:06 PM PDT 24
Finished Aug 17 06:39:12 PM PDT 24
Peak memory 211036 kb
Host smart-0e61e1a0-1bd3-4fd1-aecd-02ad46977a79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3504853079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3504853079
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2778710763
Short name T311
Test name
Test status
Simulation time 200395816 ps
CPU time 13.22 seconds
Started Aug 17 06:39:09 PM PDT 24
Finished Aug 17 06:39:22 PM PDT 24
Peak memory 214272 kb
Host smart-644a3544-63c3-48c0-93a4-073ad2d19a1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778710763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2778710763
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1458554047
Short name T49
Test name
Test status
Simulation time 2337884903 ps
CPU time 46.99 seconds
Started Aug 17 06:38:54 PM PDT 24
Finished Aug 17 06:39:41 PM PDT 24
Peak memory 220852 kb
Host smart-93825dc5-c061-4af5-beda-8c82df0b0a2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458554047 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1458554047
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3002366925
Short name T212
Test name
Test status
Simulation time 1339086039 ps
CPU time 6.38 seconds
Started Aug 17 06:38:43 PM PDT 24
Finished Aug 17 06:38:49 PM PDT 24
Peak memory 211080 kb
Host smart-4dce0d72-c10b-4475-b6a8-411d776498ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002366925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3002366925
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3072411384
Short name T274
Test name
Test status
Simulation time 3081446969 ps
CPU time 154.39 seconds
Started Aug 17 06:38:51 PM PDT 24
Finished Aug 17 06:41:25 PM PDT 24
Peak memory 237668 kb
Host smart-265bbf0f-43ad-4eb1-b55d-ce0b1f5add66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072411384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3072411384
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1817210624
Short name T149
Test name
Test status
Simulation time 96738766 ps
CPU time 5.46 seconds
Started Aug 17 06:38:42 PM PDT 24
Finished Aug 17 06:38:48 PM PDT 24
Peak memory 211080 kb
Host smart-14e89bb0-5852-4d71-a973-962ebdb36b3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1817210624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1817210624
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1163826872
Short name T30
Test name
Test status
Simulation time 144931306 ps
CPU time 51.73 seconds
Started Aug 17 06:38:43 PM PDT 24
Finished Aug 17 06:39:35 PM PDT 24
Peak memory 236744 kb
Host smart-906e50ef-23e4-4238-85db-6fb8e2e2fbf2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163826872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1163826872
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.489383353
Short name T257
Test name
Test status
Simulation time 551608678 ps
CPU time 5.28 seconds
Started Aug 17 06:38:42 PM PDT 24
Finished Aug 17 06:38:47 PM PDT 24
Peak memory 211132 kb
Host smart-b0df9ed6-f2df-49eb-9fd5-e2699d5f56c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489383353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.489383353
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.4247929797
Short name T333
Test name
Test status
Simulation time 127353565 ps
CPU time 7.23 seconds
Started Aug 17 06:38:33 PM PDT 24
Finished Aug 17 06:38:40 PM PDT 24
Peak memory 211460 kb
Host smart-16c05d1d-4f0d-41ce-8f67-b20b287c4588
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247929797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.4247929797
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.829298038
Short name T52
Test name
Test status
Simulation time 4738338663 ps
CPU time 60.32 seconds
Started Aug 17 06:38:42 PM PDT 24
Finished Aug 17 06:39:42 PM PDT 24
Peak memory 221672 kb
Host smart-0aba26fc-396f-4c25-bee3-64b5a2af291c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829298038 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.829298038
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1540541956
Short name T142
Test name
Test status
Simulation time 259584119 ps
CPU time 4.83 seconds
Started Aug 17 06:38:59 PM PDT 24
Finished Aug 17 06:39:04 PM PDT 24
Peak memory 211132 kb
Host smart-529c56f5-f0a9-4c67-9320-61cfedf73870
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540541956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1540541956
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2576701289
Short name T209
Test name
Test status
Simulation time 6270116230 ps
CPU time 102.51 seconds
Started Aug 17 06:38:43 PM PDT 24
Finished Aug 17 06:40:26 PM PDT 24
Peak memory 232544 kb
Host smart-4685fe85-05d9-4f2b-b4a3-7cb740ab537d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576701289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2576701289
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2887448971
Short name T282
Test name
Test status
Simulation time 347273785 ps
CPU time 9.01 seconds
Started Aug 17 06:39:22 PM PDT 24
Finished Aug 17 06:39:31 PM PDT 24
Peak memory 211500 kb
Host smart-3f0a4bb3-9cc2-49e5-882f-73253c843c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887448971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2887448971
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.521630048
Short name T356
Test name
Test status
Simulation time 271065550 ps
CPU time 6.01 seconds
Started Aug 17 06:39:09 PM PDT 24
Finished Aug 17 06:39:15 PM PDT 24
Peak memory 211140 kb
Host smart-97499c54-89ea-4aab-b6b8-2e83dfda883c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=521630048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.521630048
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.4164016656
Short name T226
Test name
Test status
Simulation time 373394204 ps
CPU time 6.41 seconds
Started Aug 17 06:38:52 PM PDT 24
Finished Aug 17 06:38:59 PM PDT 24
Peak memory 211016 kb
Host smart-3a36b1bf-d4a9-4844-a08b-c86cc4479e16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164016656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.4164016656
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1535267575
Short name T177
Test name
Test status
Simulation time 1229364948 ps
CPU time 78.33 seconds
Started Aug 17 06:38:55 PM PDT 24
Finished Aug 17 06:40:14 PM PDT 24
Peak memory 227524 kb
Host smart-91be7aad-0036-42ea-bc72-a336b1fc734b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535267575 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1535267575
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2318271183
Short name T301
Test name
Test status
Simulation time 502209897 ps
CPU time 4.85 seconds
Started Aug 17 06:38:50 PM PDT 24
Finished Aug 17 06:38:55 PM PDT 24
Peak memory 211112 kb
Host smart-b6d0dc90-a1c5-41f6-b9b4-8396be44bd6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318271183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2318271183
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3999651545
Short name T159
Test name
Test status
Simulation time 6343407161 ps
CPU time 148.32 seconds
Started Aug 17 06:38:44 PM PDT 24
Finished Aug 17 06:41:12 PM PDT 24
Peak memory 228340 kb
Host smart-c8b7ec68-05e8-4766-83a9-4ecae2be76a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999651545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3999651545
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3129355141
Short name T167
Test name
Test status
Simulation time 170969149 ps
CPU time 9.16 seconds
Started Aug 17 06:39:04 PM PDT 24
Finished Aug 17 06:39:13 PM PDT 24
Peak memory 210516 kb
Host smart-6c25cb2e-481a-462a-95e2-aac44743b6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129355141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3129355141
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2138759365
Short name T100
Test name
Test status
Simulation time 136578072 ps
CPU time 6.12 seconds
Started Aug 17 06:39:02 PM PDT 24
Finished Aug 17 06:39:08 PM PDT 24
Peak memory 211036 kb
Host smart-8ff9cbfb-596d-4f18-84bb-b5c039553dba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138759365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2138759365
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3763849758
Short name T233
Test name
Test status
Simulation time 1959770808 ps
CPU time 5.54 seconds
Started Aug 17 06:39:02 PM PDT 24
Finished Aug 17 06:39:08 PM PDT 24
Peak memory 212404 kb
Host smart-cda94c63-2a94-4869-aad2-5177b12e226c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763849758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3763849758
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3983287328
Short name T51
Test name
Test status
Simulation time 9533264961 ps
CPU time 102.53 seconds
Started Aug 17 06:38:55 PM PDT 24
Finished Aug 17 06:40:38 PM PDT 24
Peak memory 224072 kb
Host smart-65a2c3fa-5751-431f-b5c0-d94568430df0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983287328 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.3983287328
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2809753131
Short name T103
Test name
Test status
Simulation time 171873444 ps
CPU time 4.03 seconds
Started Aug 17 06:38:48 PM PDT 24
Finished Aug 17 06:38:52 PM PDT 24
Peak memory 211096 kb
Host smart-c086f4e7-b3b9-492b-a8d2-3c15109c42ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809753131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2809753131
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3526551054
Short name T318
Test name
Test status
Simulation time 1875515847 ps
CPU time 104.29 seconds
Started Aug 17 06:38:57 PM PDT 24
Finished Aug 17 06:40:41 PM PDT 24
Peak memory 227480 kb
Host smart-f5afa121-beec-42c8-9b4d-52a7607806ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526551054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3526551054
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.111328252
Short name T173
Test name
Test status
Simulation time 790646486 ps
CPU time 9.29 seconds
Started Aug 17 06:38:51 PM PDT 24
Finished Aug 17 06:39:01 PM PDT 24
Peak memory 211116 kb
Host smart-998987d9-453a-4680-b214-63e67be04570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111328252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.111328252
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1960597010
Short name T307
Test name
Test status
Simulation time 141225118 ps
CPU time 5.05 seconds
Started Aug 17 06:39:13 PM PDT 24
Finished Aug 17 06:39:18 PM PDT 24
Peak memory 211036 kb
Host smart-ee71617e-6267-486f-b279-ed693451218f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1960597010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1960597010
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.4009729125
Short name T231
Test name
Test status
Simulation time 537969702 ps
CPU time 15.99 seconds
Started Aug 17 06:38:51 PM PDT 24
Finished Aug 17 06:39:07 PM PDT 24
Peak memory 215560 kb
Host smart-f4038bb6-518e-4798-b23b-8f2525d29427
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009729125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.4009729125
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.265918559
Short name T141
Test name
Test status
Simulation time 336779067 ps
CPU time 4.03 seconds
Started Aug 17 06:38:58 PM PDT 24
Finished Aug 17 06:39:02 PM PDT 24
Peak memory 211136 kb
Host smart-433b26f7-b21a-4b9a-8670-bc36f47b644a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265918559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.265918559
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3089022525
Short name T330
Test name
Test status
Simulation time 3232680997 ps
CPU time 55.89 seconds
Started Aug 17 06:39:18 PM PDT 24
Finished Aug 17 06:40:14 PM PDT 24
Peak memory 237680 kb
Host smart-7ca45fe6-b342-4342-9797-eb5398d4a5a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089022525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3089022525
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.481237673
Short name T228
Test name
Test status
Simulation time 695628936 ps
CPU time 9.13 seconds
Started Aug 17 06:38:57 PM PDT 24
Finished Aug 17 06:39:06 PM PDT 24
Peak memory 211496 kb
Host smart-7f8593c6-0393-4718-baf0-e29454bbad79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481237673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.481237673
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3709424447
Short name T316
Test name
Test status
Simulation time 141528343 ps
CPU time 6.31 seconds
Started Aug 17 06:38:47 PM PDT 24
Finished Aug 17 06:38:53 PM PDT 24
Peak memory 211028 kb
Host smart-4698bd18-caf6-4d30-a5cd-0002542e7d2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3709424447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3709424447
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.4209406774
Short name T335
Test name
Test status
Simulation time 421498114 ps
CPU time 18.61 seconds
Started Aug 17 06:38:58 PM PDT 24
Finished Aug 17 06:39:16 PM PDT 24
Peak memory 213396 kb
Host smart-445e76af-3a4c-4be6-8f82-5fc73f12c3f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209406774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.4209406774
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2515102922
Short name T239
Test name
Test status
Simulation time 1236314682 ps
CPU time 65.07 seconds
Started Aug 17 06:39:16 PM PDT 24
Finished Aug 17 06:40:21 PM PDT 24
Peak memory 219972 kb
Host smart-a64cb5fc-2198-4525-bf38-7d5b85f22ea4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515102922 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2515102922
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2897662377
Short name T206
Test name
Test status
Simulation time 1240833466 ps
CPU time 4.88 seconds
Started Aug 17 06:39:02 PM PDT 24
Finished Aug 17 06:39:07 PM PDT 24
Peak memory 211028 kb
Host smart-5e24a9da-956c-426e-b322-8863bd742ef6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897662377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2897662377
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2815761279
Short name T345
Test name
Test status
Simulation time 11121189914 ps
CPU time 105.99 seconds
Started Aug 17 06:39:14 PM PDT 24
Finished Aug 17 06:41:00 PM PDT 24
Peak memory 233520 kb
Host smart-f3985ee0-711d-4921-b0ed-19594e740962
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815761279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2815761279
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2575184794
Short name T222
Test name
Test status
Simulation time 252504182 ps
CPU time 10.58 seconds
Started Aug 17 06:38:55 PM PDT 24
Finished Aug 17 06:39:05 PM PDT 24
Peak memory 210620 kb
Host smart-01e4152c-ea02-44d2-aa74-6ba88d74b293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575184794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2575184794
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3656771249
Short name T54
Test name
Test status
Simulation time 138330696 ps
CPU time 6.1 seconds
Started Aug 17 06:38:48 PM PDT 24
Finished Aug 17 06:38:54 PM PDT 24
Peak memory 211164 kb
Host smart-8a1df8a0-b2d0-42d6-807f-6a4b6810ad21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3656771249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3656771249
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2691479816
Short name T267
Test name
Test status
Simulation time 252487506 ps
CPU time 13.38 seconds
Started Aug 17 06:38:51 PM PDT 24
Finished Aug 17 06:39:04 PM PDT 24
Peak memory 214160 kb
Host smart-8283b427-3a54-40e3-bbff-fed76b400fa2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691479816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2691479816
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1784330166
Short name T152
Test name
Test status
Simulation time 2397751924 ps
CPU time 142.28 seconds
Started Aug 17 06:38:56 PM PDT 24
Finished Aug 17 06:41:18 PM PDT 24
Peak memory 220508 kb
Host smart-3e48e107-1e89-4b71-a314-beb588d277fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784330166 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1784330166
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3524786882
Short name T269
Test name
Test status
Simulation time 252317154 ps
CPU time 4.79 seconds
Started Aug 17 06:39:07 PM PDT 24
Finished Aug 17 06:39:12 PM PDT 24
Peak memory 211048 kb
Host smart-d52c617f-df67-466a-a24d-661a67dbc742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524786882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3524786882
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.363256402
Short name T205
Test name
Test status
Simulation time 1256242489 ps
CPU time 56.35 seconds
Started Aug 17 06:38:55 PM PDT 24
Finished Aug 17 06:39:52 PM PDT 24
Peak memory 235680 kb
Host smart-133d0f8c-efe9-43ec-bfc1-324dec576fc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363256402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.363256402
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1153103011
Short name T191
Test name
Test status
Simulation time 4152667535 ps
CPU time 10.85 seconds
Started Aug 17 06:38:58 PM PDT 24
Finished Aug 17 06:39:09 PM PDT 24
Peak memory 211544 kb
Host smart-4b6bf16f-c120-4e60-8228-5270557ef6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153103011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1153103011
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2020114042
Short name T313
Test name
Test status
Simulation time 145062560 ps
CPU time 6.3 seconds
Started Aug 17 06:38:57 PM PDT 24
Finished Aug 17 06:39:04 PM PDT 24
Peak memory 211124 kb
Host smart-93c17001-a38f-453f-82b4-39fcd2f5c457
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2020114042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2020114042
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.429091581
Short name T308
Test name
Test status
Simulation time 1639532293 ps
CPU time 22.3 seconds
Started Aug 17 06:38:57 PM PDT 24
Finished Aug 17 06:39:19 PM PDT 24
Peak memory 215892 kb
Host smart-c0067496-6929-4a1c-859b-71ba2c29e057
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429091581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.429091581
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.605532800
Short name T323
Test name
Test status
Simulation time 1699005849 ps
CPU time 115.78 seconds
Started Aug 17 06:38:57 PM PDT 24
Finished Aug 17 06:40:53 PM PDT 24
Peak memory 220676 kb
Host smart-90213903-8426-4528-ba6f-119ae024aa95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605532800 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.605532800
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3776877687
Short name T145
Test name
Test status
Simulation time 128253308 ps
CPU time 4.73 seconds
Started Aug 17 06:38:57 PM PDT 24
Finished Aug 17 06:39:01 PM PDT 24
Peak memory 210956 kb
Host smart-b526f22f-dc8b-460c-8930-981f751d2cb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776877687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3776877687
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.836509136
Short name T259
Test name
Test status
Simulation time 7757715200 ps
CPU time 86.6 seconds
Started Aug 17 06:39:22 PM PDT 24
Finished Aug 17 06:40:48 PM PDT 24
Peak memory 227600 kb
Host smart-1e685781-b09d-4e56-8f19-c86ddfc18887
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836509136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.836509136
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2019120099
Short name T105
Test name
Test status
Simulation time 255404046 ps
CPU time 10.64 seconds
Started Aug 17 06:38:58 PM PDT 24
Finished Aug 17 06:39:08 PM PDT 24
Peak memory 211128 kb
Host smart-9244d37e-cb1a-4adb-b295-c0c9544938f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019120099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2019120099
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.848728057
Short name T154
Test name
Test status
Simulation time 519033099 ps
CPU time 7.65 seconds
Started Aug 17 06:39:24 PM PDT 24
Finished Aug 17 06:39:32 PM PDT 24
Peak memory 211148 kb
Host smart-401a5eb8-db22-4a0c-9b32-4052c8423b59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=848728057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.848728057
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3702165662
Short name T1
Test name
Test status
Simulation time 797966915 ps
CPU time 18.75 seconds
Started Aug 17 06:39:09 PM PDT 24
Finished Aug 17 06:39:28 PM PDT 24
Peak memory 216864 kb
Host smart-8330939c-22c3-4781-8066-9affc0690d80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702165662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3702165662
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3228246087
Short name T322
Test name
Test status
Simulation time 23083131801 ps
CPU time 234.41 seconds
Started Aug 17 06:39:22 PM PDT 24
Finished Aug 17 06:43:16 PM PDT 24
Peak memory 233568 kb
Host smart-9dfb476a-f665-4206-9c3b-fc34ddaaba3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228246087 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3228246087
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3232869549
Short name T242
Test name
Test status
Simulation time 191253076 ps
CPU time 4.07 seconds
Started Aug 17 06:39:12 PM PDT 24
Finished Aug 17 06:39:16 PM PDT 24
Peak memory 211136 kb
Host smart-a0ff05c1-2dc7-4488-9050-79626623e5a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232869549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3232869549
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3542502974
Short name T294
Test name
Test status
Simulation time 1780280937 ps
CPU time 101.25 seconds
Started Aug 17 06:39:13 PM PDT 24
Finished Aug 17 06:40:55 PM PDT 24
Peak memory 236412 kb
Host smart-fe47e5e8-ccbd-471d-8f8c-f886a22b4da2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542502974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3542502974
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4039876079
Short name T28
Test name
Test status
Simulation time 669564992 ps
CPU time 9.01 seconds
Started Aug 17 06:38:58 PM PDT 24
Finished Aug 17 06:39:07 PM PDT 24
Peak memory 211512 kb
Host smart-4184659c-438c-449d-8c24-9fcacb55bb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039876079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.4039876079
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1864297371
Short name T298
Test name
Test status
Simulation time 355902993 ps
CPU time 5.26 seconds
Started Aug 17 06:39:14 PM PDT 24
Finished Aug 17 06:39:20 PM PDT 24
Peak memory 211040 kb
Host smart-18c6ec6a-2c65-443b-acef-517c926ea436
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1864297371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1864297371
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2990305497
Short name T80
Test name
Test status
Simulation time 2718629360 ps
CPU time 11.45 seconds
Started Aug 17 06:38:57 PM PDT 24
Finished Aug 17 06:39:08 PM PDT 24
Peak memory 211068 kb
Host smart-2f3b5d10-8f58-419a-9ee6-3d1b3644cfa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990305497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2990305497
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3378592419
Short name T47
Test name
Test status
Simulation time 4686150235 ps
CPU time 40.55 seconds
Started Aug 17 06:38:56 PM PDT 24
Finished Aug 17 06:39:36 PM PDT 24
Peak memory 220260 kb
Host smart-b665f462-f400-44be-bc69-6be20b2a4cdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378592419 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.3378592419
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.44497350
Short name T214
Test name
Test status
Simulation time 272622749 ps
CPU time 4.93 seconds
Started Aug 17 06:39:07 PM PDT 24
Finished Aug 17 06:39:12 PM PDT 24
Peak memory 211068 kb
Host smart-cfca98b1-0092-46ab-b6a8-b293c11a6566
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44497350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.44497350
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2385081744
Short name T285
Test name
Test status
Simulation time 5027387329 ps
CPU time 71.77 seconds
Started Aug 17 06:38:57 PM PDT 24
Finished Aug 17 06:40:09 PM PDT 24
Peak memory 212516 kb
Host smart-2769e97d-2cc5-4fbf-b765-6b849bb81bf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385081744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2385081744
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3226112290
Short name T98
Test name
Test status
Simulation time 541229504 ps
CPU time 9.19 seconds
Started Aug 17 06:38:56 PM PDT 24
Finished Aug 17 06:39:05 PM PDT 24
Peak memory 211524 kb
Host smart-c31168a3-b932-477a-8eaf-1a745dbb974f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226112290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3226112290
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.686563326
Short name T158
Test name
Test status
Simulation time 198472256 ps
CPU time 5.34 seconds
Started Aug 17 06:39:22 PM PDT 24
Finished Aug 17 06:39:28 PM PDT 24
Peak memory 211152 kb
Host smart-f84be8af-7fef-40bf-add2-aac13c3fff02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=686563326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.686563326
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2759636710
Short name T195
Test name
Test status
Simulation time 457647039 ps
CPU time 8.9 seconds
Started Aug 17 06:38:55 PM PDT 24
Finished Aug 17 06:39:04 PM PDT 24
Peak memory 211408 kb
Host smart-c9091824-21ca-4d56-802c-57fd287fb123
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759636710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2759636710
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3814408691
Short name T198
Test name
Test status
Simulation time 1036199796 ps
CPU time 41.26 seconds
Started Aug 17 06:39:14 PM PDT 24
Finished Aug 17 06:39:55 PM PDT 24
Peak memory 220400 kb
Host smart-6b7dfe34-51f7-48bf-9229-d4a2d8f65cf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814408691 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3814408691
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.208837562
Short name T210
Test name
Test status
Simulation time 333165964 ps
CPU time 4.19 seconds
Started Aug 17 06:39:11 PM PDT 24
Finished Aug 17 06:39:15 PM PDT 24
Peak memory 211120 kb
Host smart-17ef204c-c8d5-45bc-beae-9647300829f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208837562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.208837562
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.326877387
Short name T32
Test name
Test status
Simulation time 4105691659 ps
CPU time 115.65 seconds
Started Aug 17 06:39:06 PM PDT 24
Finished Aug 17 06:41:02 PM PDT 24
Peak memory 224936 kb
Host smart-fc3165c2-2508-4109-bae3-1d487dcc9dec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326877387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.326877387
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2379897993
Short name T245
Test name
Test status
Simulation time 722622540 ps
CPU time 9.14 seconds
Started Aug 17 06:39:15 PM PDT 24
Finished Aug 17 06:39:24 PM PDT 24
Peak memory 211580 kb
Host smart-cf354e02-6e30-4f8b-baed-c1fadc888c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379897993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2379897993
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3622171488
Short name T255
Test name
Test status
Simulation time 94630398 ps
CPU time 5.18 seconds
Started Aug 17 06:39:18 PM PDT 24
Finished Aug 17 06:39:23 PM PDT 24
Peak memory 211116 kb
Host smart-9215fb79-b60b-43aa-a23f-d8d0b5a49b81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3622171488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3622171488
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.656849332
Short name T203
Test name
Test status
Simulation time 1441354040 ps
CPU time 11.73 seconds
Started Aug 17 06:39:14 PM PDT 24
Finished Aug 17 06:39:26 PM PDT 24
Peak memory 215440 kb
Host smart-d9c30602-2d1a-4605-8570-36c488e9e35f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656849332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.656849332
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.472355662
Short name T211
Test name
Test status
Simulation time 10480491098 ps
CPU time 116.17 seconds
Started Aug 17 06:38:58 PM PDT 24
Finished Aug 17 06:40:54 PM PDT 24
Peak memory 222024 kb
Host smart-945893b6-a154-4ffa-a2bd-f34be2f374d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472355662 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.472355662
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3165284644
Short name T276
Test name
Test status
Simulation time 348995257 ps
CPU time 4.09 seconds
Started Aug 17 06:38:57 PM PDT 24
Finished Aug 17 06:39:01 PM PDT 24
Peak memory 211136 kb
Host smart-3fc32596-8b02-4397-b77b-4facf8fa921a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165284644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3165284644
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.986136333
Short name T223
Test name
Test status
Simulation time 12754925998 ps
CPU time 169.63 seconds
Started Aug 17 06:38:42 PM PDT 24
Finished Aug 17 06:41:32 PM PDT 24
Peak memory 237620 kb
Host smart-210ff2c1-d465-4caf-8801-83b656414d69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986136333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.986136333
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3972446483
Short name T326
Test name
Test status
Simulation time 1037406381 ps
CPU time 15.22 seconds
Started Aug 17 06:38:59 PM PDT 24
Finished Aug 17 06:39:14 PM PDT 24
Peak memory 211144 kb
Host smart-964a080c-8bd1-47e1-b11e-bf9643607982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972446483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3972446483
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2768051713
Short name T184
Test name
Test status
Simulation time 101127810 ps
CPU time 5.55 seconds
Started Aug 17 06:38:46 PM PDT 24
Finished Aug 17 06:38:52 PM PDT 24
Peak memory 211348 kb
Host smart-f07e758c-740f-43b2-839a-27e515f07cd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2768051713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2768051713
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2019403349
Short name T26
Test name
Test status
Simulation time 163222162 ps
CPU time 52.73 seconds
Started Aug 17 06:38:57 PM PDT 24
Finished Aug 17 06:39:50 PM PDT 24
Peak memory 236724 kb
Host smart-19e26a83-f595-4b8f-9eb2-a8f9f16ea858
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019403349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2019403349
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2160349509
Short name T218
Test name
Test status
Simulation time 191034386 ps
CPU time 5.24 seconds
Started Aug 17 06:38:46 PM PDT 24
Finished Aug 17 06:38:51 PM PDT 24
Peak memory 212632 kb
Host smart-c918d1be-6066-43f6-9fb3-3ac82ee2e030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160349509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2160349509
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1337837825
Short name T325
Test name
Test status
Simulation time 459025455 ps
CPU time 8.56 seconds
Started Aug 17 06:38:41 PM PDT 24
Finished Aug 17 06:38:50 PM PDT 24
Peak memory 211404 kb
Host smart-08f9dc85-2b40-49e2-8228-7e3c629bf337
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337837825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1337837825
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3415423480
Short name T188
Test name
Test status
Simulation time 7617490818 ps
CPU time 47.54 seconds
Started Aug 17 06:38:50 PM PDT 24
Finished Aug 17 06:39:38 PM PDT 24
Peak memory 221120 kb
Host smart-ffc95f6c-fbd6-4412-b72d-5a768e1ad142
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415423480 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.3415423480
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3175148067
Short name T160
Test name
Test status
Simulation time 86799843 ps
CPU time 4.13 seconds
Started Aug 17 06:39:13 PM PDT 24
Finished Aug 17 06:39:17 PM PDT 24
Peak memory 211152 kb
Host smart-309dfa09-0f9d-466a-ab52-b290b9c84a8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175148067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3175148067
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1782325717
Short name T147
Test name
Test status
Simulation time 841224047 ps
CPU time 58.5 seconds
Started Aug 17 06:38:56 PM PDT 24
Finished Aug 17 06:39:55 PM PDT 24
Peak memory 226308 kb
Host smart-bbc5d700-65cd-4a4d-9dab-8d36e1851691
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782325717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1782325717
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1948983728
Short name T277
Test name
Test status
Simulation time 673097688 ps
CPU time 9.16 seconds
Started Aug 17 06:39:06 PM PDT 24
Finished Aug 17 06:39:16 PM PDT 24
Peak memory 211540 kb
Host smart-76cdf3fa-53b4-4cc1-a353-5838004326b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948983728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1948983728
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.664341691
Short name T183
Test name
Test status
Simulation time 436958695 ps
CPU time 5.28 seconds
Started Aug 17 06:39:09 PM PDT 24
Finished Aug 17 06:39:14 PM PDT 24
Peak memory 211088 kb
Host smart-91da273b-ca06-4222-a3af-8638d9802d0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=664341691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.664341691
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3192682061
Short name T312
Test name
Test status
Simulation time 178381974 ps
CPU time 11.23 seconds
Started Aug 17 06:39:30 PM PDT 24
Finished Aug 17 06:39:42 PM PDT 24
Peak memory 213580 kb
Host smart-c848539f-2d4d-4775-8ad0-d9781b605feb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192682061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3192682061
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3733207624
Short name T156
Test name
Test status
Simulation time 13165631079 ps
CPU time 59.19 seconds
Started Aug 17 06:38:57 PM PDT 24
Finished Aug 17 06:39:56 PM PDT 24
Peak memory 227412 kb
Host smart-dddd08db-a0dc-4e1b-9b15-2441d4d7c102
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733207624 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.3733207624
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2682808317
Short name T38
Test name
Test status
Simulation time 261161998 ps
CPU time 4.99 seconds
Started Aug 17 06:39:08 PM PDT 24
Finished Aug 17 06:39:13 PM PDT 24
Peak memory 211072 kb
Host smart-0a8bd5c7-71b6-4aca-9f1d-c40f41b89332
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682808317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2682808317
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1673403278
Short name T192
Test name
Test status
Simulation time 4630558747 ps
CPU time 106.81 seconds
Started Aug 17 06:38:56 PM PDT 24
Finished Aug 17 06:40:43 PM PDT 24
Peak memory 233644 kb
Host smart-1c6e40a2-830b-4cda-8270-ee81f9698235
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673403278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1673403278
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.88106663
Short name T227
Test name
Test status
Simulation time 252159742 ps
CPU time 10.58 seconds
Started Aug 17 06:38:56 PM PDT 24
Finished Aug 17 06:39:07 PM PDT 24
Peak memory 211536 kb
Host smart-5a0fb535-65ce-4bb3-a316-19f3ad2be521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88106663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.88106663
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3109173230
Short name T352
Test name
Test status
Simulation time 219019264 ps
CPU time 5.39 seconds
Started Aug 17 06:38:57 PM PDT 24
Finished Aug 17 06:39:07 PM PDT 24
Peak memory 211136 kb
Host smart-d2c156f1-1a70-475d-9cf3-317be9df6230
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3109173230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3109173230
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1832263392
Short name T189
Test name
Test status
Simulation time 2095264078 ps
CPU time 17.28 seconds
Started Aug 17 06:39:13 PM PDT 24
Finished Aug 17 06:39:31 PM PDT 24
Peak memory 213104 kb
Host smart-969120ef-4753-4a14-8bad-964d023ec8ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832263392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1832263392
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.380613571
Short name T136
Test name
Test status
Simulation time 8748184322 ps
CPU time 106.01 seconds
Started Aug 17 06:39:14 PM PDT 24
Finished Aug 17 06:41:00 PM PDT 24
Peak memory 223068 kb
Host smart-30955a5d-9c6d-4585-8327-97c0df6e8027
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380613571 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.380613571
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2030568740
Short name T237
Test name
Test status
Simulation time 832017730 ps
CPU time 4.92 seconds
Started Aug 17 06:38:59 PM PDT 24
Finished Aug 17 06:39:04 PM PDT 24
Peak memory 211096 kb
Host smart-3c623204-d1e3-4411-b836-3c34370f1ac4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030568740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2030568740
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2975851174
Short name T254
Test name
Test status
Simulation time 32266799377 ps
CPU time 146.46 seconds
Started Aug 17 06:39:21 PM PDT 24
Finished Aug 17 06:41:48 PM PDT 24
Peak memory 237736 kb
Host smart-fa70842b-a0af-411d-bc0d-3fa79bcc1d4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975851174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2975851174
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3045390903
Short name T283
Test name
Test status
Simulation time 168718518 ps
CPU time 9.12 seconds
Started Aug 17 06:38:55 PM PDT 24
Finished Aug 17 06:39:04 PM PDT 24
Peak memory 211640 kb
Host smart-48bed713-3acd-4a04-ab86-002b92a16bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045390903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3045390903
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1906057914
Short name T336
Test name
Test status
Simulation time 277718242 ps
CPU time 6.18 seconds
Started Aug 17 06:38:54 PM PDT 24
Finished Aug 17 06:39:00 PM PDT 24
Peak memory 211136 kb
Host smart-3b09dae0-a078-446f-8d13-9ea89f2b36e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1906057914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1906057914
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1859887677
Short name T341
Test name
Test status
Simulation time 293216571 ps
CPU time 13.2 seconds
Started Aug 17 06:39:09 PM PDT 24
Finished Aug 17 06:39:22 PM PDT 24
Peak memory 214816 kb
Host smart-689c2b3b-f636-4339-be04-40b985ac0385
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859887677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1859887677
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3699951947
Short name T258
Test name
Test status
Simulation time 50682391624 ps
CPU time 321.19 seconds
Started Aug 17 06:39:06 PM PDT 24
Finished Aug 17 06:44:28 PM PDT 24
Peak memory 234504 kb
Host smart-2bdeab0e-fe17-4580-ada6-961476c2661d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699951947 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.3699951947
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.284866054
Short name T181
Test name
Test status
Simulation time 85963200 ps
CPU time 4.12 seconds
Started Aug 17 06:38:59 PM PDT 24
Finished Aug 17 06:39:03 PM PDT 24
Peak memory 211144 kb
Host smart-a4fbb92f-ddf6-4e66-bb56-3c5a940c96c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284866054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.284866054
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3453819135
Short name T19
Test name
Test status
Simulation time 1239102295 ps
CPU time 82.35 seconds
Started Aug 17 06:39:06 PM PDT 24
Finished Aug 17 06:40:29 PM PDT 24
Peak memory 237336 kb
Host smart-5c281378-338f-4317-a1d3-ca7fed723e7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453819135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3453819135
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3567917621
Short name T219
Test name
Test status
Simulation time 177243176 ps
CPU time 9.04 seconds
Started Aug 17 06:38:58 PM PDT 24
Finished Aug 17 06:39:07 PM PDT 24
Peak memory 211560 kb
Host smart-2f978d51-0780-4e99-8560-9d08d56daab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567917621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3567917621
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2194231194
Short name T291
Test name
Test status
Simulation time 946782359 ps
CPU time 5.9 seconds
Started Aug 17 06:38:56 PM PDT 24
Finished Aug 17 06:39:02 PM PDT 24
Peak memory 211140 kb
Host smart-16580cbf-5069-4898-833b-fe1859a6eeb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2194231194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2194231194
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3135828954
Short name T79
Test name
Test status
Simulation time 210395464 ps
CPU time 11.97 seconds
Started Aug 17 06:39:09 PM PDT 24
Finished Aug 17 06:39:21 PM PDT 24
Peak memory 214780 kb
Host smart-4c422d12-1f83-4782-8798-b0ee467b6941
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135828954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3135828954
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4227179150
Short name T347
Test name
Test status
Simulation time 332561192 ps
CPU time 4.01 seconds
Started Aug 17 06:39:27 PM PDT 24
Finished Aug 17 06:39:31 PM PDT 24
Peak memory 211148 kb
Host smart-614bd026-179b-4b67-9441-b3f639673ec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227179150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4227179150
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3498352513
Short name T337
Test name
Test status
Simulation time 7746413669 ps
CPU time 107.43 seconds
Started Aug 17 06:39:23 PM PDT 24
Finished Aug 17 06:41:11 PM PDT 24
Peak memory 224472 kb
Host smart-3b48116d-b362-4859-a4b6-aa527b6a0d91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498352513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3498352513
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3692608647
Short name T27
Test name
Test status
Simulation time 168829224 ps
CPU time 9.23 seconds
Started Aug 17 06:39:16 PM PDT 24
Finished Aug 17 06:39:25 PM PDT 24
Peak memory 211508 kb
Host smart-faf0d21b-d43e-4bcd-b31a-460b0839a404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692608647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3692608647
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3241805
Short name T157
Test name
Test status
Simulation time 309502587 ps
CPU time 5.04 seconds
Started Aug 17 06:39:14 PM PDT 24
Finished Aug 17 06:39:19 PM PDT 24
Peak memory 211140 kb
Host smart-94b26123-40cc-4ed0-8cf3-ea0b558c0b20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3241805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3241805
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2193915789
Short name T101
Test name
Test status
Simulation time 185911550 ps
CPU time 12.81 seconds
Started Aug 17 06:39:09 PM PDT 24
Finished Aug 17 06:39:22 PM PDT 24
Peak memory 213076 kb
Host smart-bc5506d7-5cbc-4764-859b-c027bf748efa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193915789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2193915789
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1916978893
Short name T221
Test name
Test status
Simulation time 260637875 ps
CPU time 5.02 seconds
Started Aug 17 06:39:18 PM PDT 24
Finished Aug 17 06:39:23 PM PDT 24
Peak memory 211152 kb
Host smart-32a6c69f-f8c1-42dc-9a9d-4b73748c5c2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916978893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1916978893
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2763444147
Short name T287
Test name
Test status
Simulation time 750392668 ps
CPU time 41.03 seconds
Started Aug 17 06:38:59 PM PDT 24
Finished Aug 17 06:39:40 PM PDT 24
Peak memory 236628 kb
Host smart-b964fe70-7467-4fd4-a3f6-71e563b5938b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763444147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2763444147
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3071221561
Short name T201
Test name
Test status
Simulation time 365291632 ps
CPU time 9.06 seconds
Started Aug 17 06:39:09 PM PDT 24
Finished Aug 17 06:39:18 PM PDT 24
Peak memory 211532 kb
Host smart-6e56d964-2cea-441a-8374-a20ed5d2e2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071221561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3071221561
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.850612775
Short name T193
Test name
Test status
Simulation time 619131836 ps
CPU time 6.22 seconds
Started Aug 17 06:38:58 PM PDT 24
Finished Aug 17 06:39:05 PM PDT 24
Peak memory 211156 kb
Host smart-c858f077-e8d5-45ef-9bb5-16a6483245e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=850612775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.850612775
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.793068478
Short name T36
Test name
Test status
Simulation time 2069539467 ps
CPU time 10.3 seconds
Started Aug 17 06:39:08 PM PDT 24
Finished Aug 17 06:39:18 PM PDT 24
Peak memory 211164 kb
Host smart-b4f6758e-0c26-4c74-a147-91ff00e942a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793068478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.793068478
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2003098468
Short name T196
Test name
Test status
Simulation time 6553552326 ps
CPU time 115.61 seconds
Started Aug 17 06:38:59 PM PDT 24
Finished Aug 17 06:40:55 PM PDT 24
Peak memory 232168 kb
Host smart-ff75e304-8a17-4850-b588-253ea092e16a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003098468 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2003098468
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4254850578
Short name T61
Test name
Test status
Simulation time 731127540 ps
CPU time 4.66 seconds
Started Aug 17 06:39:00 PM PDT 24
Finished Aug 17 06:39:05 PM PDT 24
Peak memory 211092 kb
Host smart-30cdee15-a083-454a-9902-eae6721771ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254850578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4254850578
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3844882186
Short name T332
Test name
Test status
Simulation time 6743636464 ps
CPU time 70.7 seconds
Started Aug 17 06:39:00 PM PDT 24
Finished Aug 17 06:40:11 PM PDT 24
Peak memory 228432 kb
Host smart-1da52d57-72b7-4a1a-8056-cccc12499811
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844882186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3844882186
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.921545870
Short name T165
Test name
Test status
Simulation time 888944665 ps
CPU time 10.73 seconds
Started Aug 17 06:38:58 PM PDT 24
Finished Aug 17 06:39:09 PM PDT 24
Peak memory 211160 kb
Host smart-3a8dc955-a437-440b-b25e-4a28476ce050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921545870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.921545870
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.4033765350
Short name T225
Test name
Test status
Simulation time 374069440 ps
CPU time 5.19 seconds
Started Aug 17 06:38:59 PM PDT 24
Finished Aug 17 06:39:04 PM PDT 24
Peak memory 211156 kb
Host smart-0876325b-e73f-40e2-8cae-4f7c63ff351a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4033765350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.4033765350
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1580581439
Short name T265
Test name
Test status
Simulation time 295234038 ps
CPU time 7.76 seconds
Started Aug 17 06:39:16 PM PDT 24
Finished Aug 17 06:39:24 PM PDT 24
Peak memory 211224 kb
Host smart-5da758db-f3d4-4e7c-a502-94b8d48b0c91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580581439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1580581439
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.597733732
Short name T251
Test name
Test status
Simulation time 6404037934 ps
CPU time 120.44 seconds
Started Aug 17 06:39:09 PM PDT 24
Finished Aug 17 06:41:10 PM PDT 24
Peak memory 230324 kb
Host smart-e8d58995-5fa3-40c3-8071-b00000e0d0ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597733732 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.597733732
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3021021088
Short name T315
Test name
Test status
Simulation time 168345215 ps
CPU time 4.05 seconds
Started Aug 17 06:39:13 PM PDT 24
Finished Aug 17 06:39:17 PM PDT 24
Peak memory 211124 kb
Host smart-81ab35c9-0eea-4797-9f16-7f9a67fb42f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021021088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3021021088
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.744214438
Short name T153
Test name
Test status
Simulation time 2582640737 ps
CPU time 115.82 seconds
Started Aug 17 06:39:16 PM PDT 24
Finished Aug 17 06:41:12 PM PDT 24
Peak memory 232604 kb
Host smart-270e6a6b-537f-4256-aa71-ef2713ef7798
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744214438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.744214438
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1496443628
Short name T359
Test name
Test status
Simulation time 173751287 ps
CPU time 9.3 seconds
Started Aug 17 06:39:15 PM PDT 24
Finished Aug 17 06:39:24 PM PDT 24
Peak memory 211528 kb
Host smart-a0ab8889-c6de-40bf-8b49-82129e3dd527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496443628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1496443628
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2676587416
Short name T273
Test name
Test status
Simulation time 136885748 ps
CPU time 6.13 seconds
Started Aug 17 06:39:15 PM PDT 24
Finished Aug 17 06:39:21 PM PDT 24
Peak memory 211168 kb
Host smart-34f923fa-9532-488a-9426-1b4fc4e19845
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2676587416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2676587416
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2705727793
Short name T305
Test name
Test status
Simulation time 849324109 ps
CPU time 19.23 seconds
Started Aug 17 06:39:11 PM PDT 24
Finished Aug 17 06:39:30 PM PDT 24
Peak memory 214940 kb
Host smart-47deebc4-3d50-4641-a547-57ed328e7e09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705727793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2705727793
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3707138529
Short name T162
Test name
Test status
Simulation time 12551983027 ps
CPU time 226.26 seconds
Started Aug 17 06:38:56 PM PDT 24
Finished Aug 17 06:42:42 PM PDT 24
Peak memory 232968 kb
Host smart-9a5b0fda-92c6-4aa7-9d46-12e619139cf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707138529 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3707138529
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2383601254
Short name T354
Test name
Test status
Simulation time 963988662 ps
CPU time 4.81 seconds
Started Aug 17 06:39:28 PM PDT 24
Finished Aug 17 06:39:33 PM PDT 24
Peak memory 211152 kb
Host smart-a3f5bb3a-877e-4fa3-975d-90324515671e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383601254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2383601254
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.980079253
Short name T275
Test name
Test status
Simulation time 2711796733 ps
CPU time 134.81 seconds
Started Aug 17 06:39:11 PM PDT 24
Finished Aug 17 06:41:26 PM PDT 24
Peak memory 237728 kb
Host smart-fcb0728d-c75f-4c51-892f-4115716444f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980079253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.980079253
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3598537690
Short name T263
Test name
Test status
Simulation time 256353001 ps
CPU time 10.52 seconds
Started Aug 17 06:39:13 PM PDT 24
Finished Aug 17 06:39:24 PM PDT 24
Peak memory 211524 kb
Host smart-90e2d3bd-454c-4030-a979-a7ff43cc65ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598537690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3598537690
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3531383728
Short name T34
Test name
Test status
Simulation time 279507296 ps
CPU time 6.23 seconds
Started Aug 17 06:39:21 PM PDT 24
Finished Aug 17 06:39:28 PM PDT 24
Peak memory 211116 kb
Host smart-d9e776e2-899c-4ae4-896e-142d47fb89fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3531383728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3531383728
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.596723889
Short name T247
Test name
Test status
Simulation time 535243418 ps
CPU time 14.07 seconds
Started Aug 17 06:38:57 PM PDT 24
Finished Aug 17 06:39:12 PM PDT 24
Peak memory 213960 kb
Host smart-9d21a80e-2bec-4f70-b15a-d87832bf98d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596723889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.596723889
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2957594234
Short name T256
Test name
Test status
Simulation time 7915844466 ps
CPU time 47 seconds
Started Aug 17 06:38:58 PM PDT 24
Finished Aug 17 06:39:45 PM PDT 24
Peak memory 228808 kb
Host smart-a013cb7a-ed50-40e1-923a-ed096cb6e590
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957594234 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.2957594234
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2580595268
Short name T264
Test name
Test status
Simulation time 347904868 ps
CPU time 3.91 seconds
Started Aug 17 06:39:30 PM PDT 24
Finished Aug 17 06:39:35 PM PDT 24
Peak memory 211048 kb
Host smart-902711f0-59d8-4ddc-98f7-e853fbb09062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580595268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2580595268
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1142228780
Short name T174
Test name
Test status
Simulation time 7328842986 ps
CPU time 83.39 seconds
Started Aug 17 06:39:05 PM PDT 24
Finished Aug 17 06:40:28 PM PDT 24
Peak memory 232624 kb
Host smart-cbb430d9-6d95-4e6f-be6c-2b21d2c9947a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142228780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1142228780
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2372730805
Short name T170
Test name
Test status
Simulation time 261744582 ps
CPU time 10.59 seconds
Started Aug 17 06:39:18 PM PDT 24
Finished Aug 17 06:39:29 PM PDT 24
Peak memory 211552 kb
Host smart-111a45a7-a3d9-4ebd-9d59-6ecb2d2a3ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372730805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2372730805
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4083395277
Short name T349
Test name
Test status
Simulation time 961839151 ps
CPU time 6.23 seconds
Started Aug 17 06:39:06 PM PDT 24
Finished Aug 17 06:39:12 PM PDT 24
Peak memory 211164 kb
Host smart-4ae74dda-3bc2-44a8-ae12-10a7f9490a61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4083395277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4083395277
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3749076872
Short name T207
Test name
Test status
Simulation time 829603580 ps
CPU time 11.66 seconds
Started Aug 17 06:38:57 PM PDT 24
Finished Aug 17 06:39:09 PM PDT 24
Peak memory 213864 kb
Host smart-ce9dd8df-5a45-4a7c-9fbf-93387543bf70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749076872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3749076872
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.904085651
Short name T168
Test name
Test status
Simulation time 2488199870 ps
CPU time 43.06 seconds
Started Aug 17 06:39:19 PM PDT 24
Finished Aug 17 06:40:02 PM PDT 24
Peak memory 219552 kb
Host smart-9bcc5f8a-11cc-48af-b0c9-9ca28e5c7849
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904085651 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.904085651
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3115393358
Short name T215
Test name
Test status
Simulation time 87131314 ps
CPU time 4.12 seconds
Started Aug 17 06:38:45 PM PDT 24
Finished Aug 17 06:38:49 PM PDT 24
Peak memory 211148 kb
Host smart-8a6e56ce-30b7-4256-9d86-46e523b2cfa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115393358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3115393358
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.820696191
Short name T35
Test name
Test status
Simulation time 6598532693 ps
CPU time 104.89 seconds
Started Aug 17 06:39:13 PM PDT 24
Finished Aug 17 06:40:58 PM PDT 24
Peak memory 228140 kb
Host smart-46f10b2c-4316-417d-83a0-03e1e5a6c240
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820696191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.820696191
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2770310842
Short name T321
Test name
Test status
Simulation time 1042770300 ps
CPU time 10.35 seconds
Started Aug 17 06:39:13 PM PDT 24
Finished Aug 17 06:39:23 PM PDT 24
Peak memory 211136 kb
Host smart-fe4a1cf2-fb7b-4cb6-a6d2-fdff72efe5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770310842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2770310842
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2437776338
Short name T179
Test name
Test status
Simulation time 142210473 ps
CPU time 6.27 seconds
Started Aug 17 06:38:43 PM PDT 24
Finished Aug 17 06:38:49 PM PDT 24
Peak memory 211132 kb
Host smart-c972daea-c35e-4595-ab6a-bc0f3fc66f2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2437776338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2437776338
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1115861944
Short name T24
Test name
Test status
Simulation time 278506068 ps
CPU time 53.09 seconds
Started Aug 17 06:38:45 PM PDT 24
Finished Aug 17 06:39:38 PM PDT 24
Peak memory 236740 kb
Host smart-920fd25f-182f-47c7-ab25-76fc3ff6b7ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115861944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1115861944
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.514648809
Short name T202
Test name
Test status
Simulation time 464500302 ps
CPU time 5.42 seconds
Started Aug 17 06:38:43 PM PDT 24
Finished Aug 17 06:38:49 PM PDT 24
Peak memory 211692 kb
Host smart-7278db43-0f2c-4350-bb83-91bce98ccb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514648809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.514648809
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.317543337
Short name T348
Test name
Test status
Simulation time 469939081 ps
CPU time 12.14 seconds
Started Aug 17 06:39:08 PM PDT 24
Finished Aug 17 06:39:20 PM PDT 24
Peak memory 214460 kb
Host smart-220a20e6-c77c-4ef2-9ec2-96b8ec5b822b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317543337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.317543337
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.4150819522
Short name T353
Test name
Test status
Simulation time 24498188853 ps
CPU time 97.85 seconds
Started Aug 17 06:38:52 PM PDT 24
Finished Aug 17 06:40:30 PM PDT 24
Peak memory 232144 kb
Host smart-34b5b13b-9c5c-4a69-8436-9c6ec81cb65e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150819522 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.4150819522
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2416706143
Short name T331
Test name
Test status
Simulation time 127823273 ps
CPU time 4.83 seconds
Started Aug 17 06:39:05 PM PDT 24
Finished Aug 17 06:39:10 PM PDT 24
Peak memory 211092 kb
Host smart-24550dce-752b-4b4f-9962-7a9c1a2302ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416706143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2416706143
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3728407258
Short name T197
Test name
Test status
Simulation time 4531731676 ps
CPU time 75.05 seconds
Started Aug 17 06:39:24 PM PDT 24
Finished Aug 17 06:40:39 PM PDT 24
Peak memory 232496 kb
Host smart-64df8759-28f6-4147-b0c9-9e60f193d2af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728407258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3728407258
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.4760885
Short name T358
Test name
Test status
Simulation time 695095827 ps
CPU time 9.16 seconds
Started Aug 17 06:39:04 PM PDT 24
Finished Aug 17 06:39:13 PM PDT 24
Peak memory 211672 kb
Host smart-56087f12-eb3e-43d8-96a0-f6bf345b2a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4760885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.4760885
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2477666608
Short name T293
Test name
Test status
Simulation time 293621969 ps
CPU time 13.31 seconds
Started Aug 17 06:39:28 PM PDT 24
Finished Aug 17 06:39:42 PM PDT 24
Peak memory 213812 kb
Host smart-a925f5ac-1688-4952-9601-60f51caabb7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477666608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2477666608
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3457447842
Short name T48
Test name
Test status
Simulation time 2959991636 ps
CPU time 170.36 seconds
Started Aug 17 06:39:04 PM PDT 24
Finished Aug 17 06:41:55 PM PDT 24
Peak memory 221336 kb
Host smart-946e9f31-1714-454d-8f2e-ccb871a43cee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457447842 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.3457447842
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2026008860
Short name T62
Test name
Test status
Simulation time 89216920 ps
CPU time 4.11 seconds
Started Aug 17 06:39:28 PM PDT 24
Finished Aug 17 06:39:32 PM PDT 24
Peak memory 211152 kb
Host smart-89ed742c-a633-4f16-a9b3-d68f31c1d946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026008860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2026008860
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.893623668
Short name T246
Test name
Test status
Simulation time 1330549731 ps
CPU time 60.76 seconds
Started Aug 17 06:39:04 PM PDT 24
Finished Aug 17 06:40:05 PM PDT 24
Peak memory 239824 kb
Host smart-ea337117-1036-473b-b09e-d2dba48867ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893623668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.893623668
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3323791909
Short name T272
Test name
Test status
Simulation time 169470071 ps
CPU time 9.09 seconds
Started Aug 17 06:39:04 PM PDT 24
Finished Aug 17 06:39:13 PM PDT 24
Peak memory 211580 kb
Host smart-1d616aa5-6055-4223-9ed4-646c7a9245d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323791909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3323791909
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.786483355
Short name T339
Test name
Test status
Simulation time 98057860 ps
CPU time 5.56 seconds
Started Aug 17 06:39:04 PM PDT 24
Finished Aug 17 06:39:15 PM PDT 24
Peak memory 211144 kb
Host smart-0a82be1a-1b46-4da1-b1fc-69575df5ca83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786483355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.786483355
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3985159995
Short name T138
Test name
Test status
Simulation time 670421499 ps
CPU time 7.98 seconds
Started Aug 17 06:39:24 PM PDT 24
Finished Aug 17 06:39:32 PM PDT 24
Peak memory 211016 kb
Host smart-e99d96ae-260d-4f76-b96f-fb4061406b68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985159995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3985159995
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.361865074
Short name T17
Test name
Test status
Simulation time 4235947345 ps
CPU time 77.76 seconds
Started Aug 17 06:39:19 PM PDT 24
Finished Aug 17 06:40:36 PM PDT 24
Peak memory 220680 kb
Host smart-35fe8c78-e3c4-494a-bd00-f4b60ae75ae9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361865074 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.361865074
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4050015752
Short name T11
Test name
Test status
Simulation time 260214996 ps
CPU time 4.85 seconds
Started Aug 17 06:39:22 PM PDT 24
Finished Aug 17 06:39:27 PM PDT 24
Peak memory 211136 kb
Host smart-88bb9330-38e9-4f72-bc9e-63fc4c922718
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050015752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4050015752
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1741512374
Short name T363
Test name
Test status
Simulation time 390975196 ps
CPU time 10.49 seconds
Started Aug 17 06:39:30 PM PDT 24
Finished Aug 17 06:39:40 PM PDT 24
Peak memory 211500 kb
Host smart-924519ad-c0d4-46aa-814d-9efbbe0b49a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741512374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1741512374
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3053324033
Short name T176
Test name
Test status
Simulation time 140300519 ps
CPU time 6.21 seconds
Started Aug 17 06:39:27 PM PDT 24
Finished Aug 17 06:39:33 PM PDT 24
Peak memory 211108 kb
Host smart-e3cac8e0-8bc5-4457-8505-f550ac189c36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3053324033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3053324033
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2829505821
Short name T230
Test name
Test status
Simulation time 325926049 ps
CPU time 14.02 seconds
Started Aug 17 06:39:05 PM PDT 24
Finished Aug 17 06:39:19 PM PDT 24
Peak memory 214344 kb
Host smart-a7c5a8bf-5df9-49f1-8161-7df73ca76d90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829505821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2829505821
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3292932466
Short name T290
Test name
Test status
Simulation time 521843350 ps
CPU time 4.04 seconds
Started Aug 17 06:39:26 PM PDT 24
Finished Aug 17 06:39:30 PM PDT 24
Peak memory 211116 kb
Host smart-61e0f2fb-2161-4fd8-bf47-de295cfb31c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292932466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3292932466
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2132714105
Short name T357
Test name
Test status
Simulation time 5844407596 ps
CPU time 138.29 seconds
Started Aug 17 06:39:10 PM PDT 24
Finished Aug 17 06:41:28 PM PDT 24
Peak memory 212492 kb
Host smart-90e1ab76-1b8a-4816-9fa0-b1a81302aa40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132714105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2132714105
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.130075846
Short name T289
Test name
Test status
Simulation time 977603064 ps
CPU time 9.31 seconds
Started Aug 17 06:39:17 PM PDT 24
Finished Aug 17 06:39:26 PM PDT 24
Peak memory 211660 kb
Host smart-e3205145-9826-4d28-a63c-85700ff6c235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130075846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.130075846
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3650107526
Short name T190
Test name
Test status
Simulation time 526026805 ps
CPU time 5.9 seconds
Started Aug 17 06:39:25 PM PDT 24
Finished Aug 17 06:39:31 PM PDT 24
Peak memory 211064 kb
Host smart-7950babe-af12-4e6f-9283-65e74eddd509
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3650107526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3650107526
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2934828407
Short name T362
Test name
Test status
Simulation time 996116072 ps
CPU time 14.17 seconds
Started Aug 17 06:39:10 PM PDT 24
Finished Aug 17 06:39:25 PM PDT 24
Peak memory 213908 kb
Host smart-080c3f5b-3900-4aad-8690-b5b1ccf4ed1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934828407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2934828407
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.983430934
Short name T252
Test name
Test status
Simulation time 2812388598 ps
CPU time 182.51 seconds
Started Aug 17 06:39:22 PM PDT 24
Finished Aug 17 06:42:25 PM PDT 24
Peak memory 231352 kb
Host smart-e31ee84e-322e-4dd9-9b7b-6298fe541b17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983430934 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.983430934
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1274149587
Short name T171
Test name
Test status
Simulation time 130066583 ps
CPU time 4.77 seconds
Started Aug 17 06:39:23 PM PDT 24
Finished Aug 17 06:39:28 PM PDT 24
Peak memory 211148 kb
Host smart-fd8bd1b3-280a-4beb-8b8e-b4b514903829
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274149587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1274149587
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.115988077
Short name T164
Test name
Test status
Simulation time 3481072026 ps
CPU time 65.62 seconds
Started Aug 17 06:39:23 PM PDT 24
Finished Aug 17 06:40:28 PM PDT 24
Peak memory 212464 kb
Host smart-840a0a54-82ba-4fa0-85bd-5a79827d0844
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115988077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.115988077
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.890636922
Short name T99
Test name
Test status
Simulation time 349058569 ps
CPU time 8.98 seconds
Started Aug 17 06:39:28 PM PDT 24
Finished Aug 17 06:39:38 PM PDT 24
Peak memory 211660 kb
Host smart-506a3465-928f-4772-aea3-caebeac1e41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890636922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.890636922
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3327884693
Short name T151
Test name
Test status
Simulation time 140726734 ps
CPU time 6.3 seconds
Started Aug 17 06:39:31 PM PDT 24
Finished Aug 17 06:39:37 PM PDT 24
Peak memory 211180 kb
Host smart-0e86d343-3c3d-4541-8647-55bdc3fc7261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3327884693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3327884693
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4125329274
Short name T200
Test name
Test status
Simulation time 4247301830 ps
CPU time 18.95 seconds
Started Aug 17 06:39:21 PM PDT 24
Finished Aug 17 06:39:40 PM PDT 24
Peak memory 213816 kb
Host smart-d76fa26b-332a-4510-bbce-a324244e927c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125329274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4125329274
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.365955342
Short name T361
Test name
Test status
Simulation time 1593340126 ps
CPU time 96.1 seconds
Started Aug 17 06:39:16 PM PDT 24
Finished Aug 17 06:40:52 PM PDT 24
Peak memory 220440 kb
Host smart-22782202-8aad-4842-ad15-cff6793dcc29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365955342 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.365955342
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2858913413
Short name T5
Test name
Test status
Simulation time 86515440 ps
CPU time 4.1 seconds
Started Aug 17 06:39:29 PM PDT 24
Finished Aug 17 06:39:33 PM PDT 24
Peak memory 211100 kb
Host smart-7d9ba10d-35b4-44f8-ac90-320442b74606
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858913413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2858913413
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3223284259
Short name T45
Test name
Test status
Simulation time 4436616612 ps
CPU time 117.94 seconds
Started Aug 17 06:39:15 PM PDT 24
Finished Aug 17 06:41:13 PM PDT 24
Peak memory 232956 kb
Host smart-fd0f0c2c-82ae-436d-a96c-87f5625a1a35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223284259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3223284259
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3602135634
Short name T199
Test name
Test status
Simulation time 665266606 ps
CPU time 8.86 seconds
Started Aug 17 06:39:17 PM PDT 24
Finished Aug 17 06:39:26 PM PDT 24
Peak memory 211596 kb
Host smart-ad71dc44-0a94-496b-91d7-936d1b36b604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602135634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3602135634
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1345712282
Short name T155
Test name
Test status
Simulation time 265879457 ps
CPU time 6.04 seconds
Started Aug 17 06:39:30 PM PDT 24
Finished Aug 17 06:39:36 PM PDT 24
Peak memory 211116 kb
Host smart-9ef85b6d-b2b0-4cd0-bed4-a5d991a13ce5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1345712282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1345712282
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.711905811
Short name T75
Test name
Test status
Simulation time 472598547 ps
CPU time 21.14 seconds
Started Aug 17 06:39:16 PM PDT 24
Finished Aug 17 06:39:37 PM PDT 24
Peak memory 214840 kb
Host smart-ef766487-5cc1-4a44-99f5-e1059912d499
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711905811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.711905811
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3129365255
Short name T229
Test name
Test status
Simulation time 87987649 ps
CPU time 4.14 seconds
Started Aug 17 06:39:21 PM PDT 24
Finished Aug 17 06:39:25 PM PDT 24
Peak memory 211128 kb
Host smart-25866e55-e8c9-4a57-ad54-50ead18f76b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129365255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3129365255
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1136085788
Short name T292
Test name
Test status
Simulation time 4798975627 ps
CPU time 65.48 seconds
Started Aug 17 06:39:35 PM PDT 24
Finished Aug 17 06:40:41 PM PDT 24
Peak memory 224480 kb
Host smart-8dc40e29-1ecc-4ebd-9955-354b3f4ef3d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136085788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1136085788
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.532086142
Short name T140
Test name
Test status
Simulation time 995622055 ps
CPU time 10.86 seconds
Started Aug 17 06:39:16 PM PDT 24
Finished Aug 17 06:39:27 PM PDT 24
Peak memory 211540 kb
Host smart-726b59a4-fefc-4707-9027-563cf4f4c02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532086142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.532086142
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2664739256
Short name T118
Test name
Test status
Simulation time 1797613970 ps
CPU time 8.07 seconds
Started Aug 17 06:39:23 PM PDT 24
Finished Aug 17 06:39:31 PM PDT 24
Peak memory 211164 kb
Host smart-ad43b76a-27bf-4498-a3ac-165bd2973fd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2664739256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2664739256
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.100350224
Short name T216
Test name
Test status
Simulation time 500816964 ps
CPU time 4.85 seconds
Started Aug 17 06:39:37 PM PDT 24
Finished Aug 17 06:39:42 PM PDT 24
Peak memory 211044 kb
Host smart-7c0c77bc-c0e9-45fa-adab-82f664064e70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100350224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.100350224
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2061019296
Short name T37
Test name
Test status
Simulation time 16235863038 ps
CPU time 147.37 seconds
Started Aug 17 06:39:32 PM PDT 24
Finished Aug 17 06:42:00 PM PDT 24
Peak memory 228216 kb
Host smart-4661594b-024a-4902-affe-457db4e60fea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061019296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2061019296
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3526954764
Short name T41
Test name
Test status
Simulation time 664714655 ps
CPU time 9.16 seconds
Started Aug 17 06:39:22 PM PDT 24
Finished Aug 17 06:39:32 PM PDT 24
Peak memory 211512 kb
Host smart-7f88c6e6-3d9e-4f1c-aa76-e615b6f176b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526954764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3526954764
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3003074035
Short name T284
Test name
Test status
Simulation time 144383751 ps
CPU time 6.46 seconds
Started Aug 17 06:39:17 PM PDT 24
Finished Aug 17 06:39:24 PM PDT 24
Peak memory 211164 kb
Host smart-8a6a7ed4-d30d-4667-8b3a-19ddc59e7a42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3003074035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3003074035
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.671105984
Short name T119
Test name
Test status
Simulation time 299741037 ps
CPU time 12.43 seconds
Started Aug 17 06:39:31 PM PDT 24
Finished Aug 17 06:39:43 PM PDT 24
Peak memory 214536 kb
Host smart-d5d2b86e-884b-487e-a705-fee8e3c3620c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671105984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.671105984
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2841023850
Short name T319
Test name
Test status
Simulation time 8789102489 ps
CPU time 122.89 seconds
Started Aug 17 06:39:31 PM PDT 24
Finished Aug 17 06:41:34 PM PDT 24
Peak memory 222352 kb
Host smart-84caca96-8c2f-49ef-975f-e93a04af7c90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841023850 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2841023850
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.661658067
Short name T235
Test name
Test status
Simulation time 130477567 ps
CPU time 4.98 seconds
Started Aug 17 06:39:31 PM PDT 24
Finished Aug 17 06:39:36 PM PDT 24
Peak memory 211064 kb
Host smart-0136148e-4509-42a6-8412-2979abee811f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661658067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.661658067
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1296920708
Short name T186
Test name
Test status
Simulation time 2471157307 ps
CPU time 134.88 seconds
Started Aug 17 06:39:19 PM PDT 24
Finished Aug 17 06:41:34 PM PDT 24
Peak memory 236888 kb
Host smart-690ec4c8-d2e0-4370-8b58-683700171d18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296920708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1296920708
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1191642807
Short name T178
Test name
Test status
Simulation time 1023471753 ps
CPU time 14.66 seconds
Started Aug 17 06:39:35 PM PDT 24
Finished Aug 17 06:39:50 PM PDT 24
Peak memory 211592 kb
Host smart-784250e6-93ef-4a33-a7a0-ec70d4a862b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191642807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1191642807
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2287986810
Short name T302
Test name
Test status
Simulation time 95091487 ps
CPU time 5.38 seconds
Started Aug 17 06:39:31 PM PDT 24
Finished Aug 17 06:39:36 PM PDT 24
Peak memory 211152 kb
Host smart-56334109-0644-46df-9fd9-29f55da2a73d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2287986810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2287986810
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2208332244
Short name T310
Test name
Test status
Simulation time 610840534 ps
CPU time 9.08 seconds
Started Aug 17 06:39:28 PM PDT 24
Finished Aug 17 06:39:37 PM PDT 24
Peak memory 210956 kb
Host smart-6d907a0f-4e82-4e95-890e-f37afccba5c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208332244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2208332244
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3954124981
Short name T343
Test name
Test status
Simulation time 3966315127 ps
CPU time 254.35 seconds
Started Aug 17 06:39:20 PM PDT 24
Finished Aug 17 06:43:35 PM PDT 24
Peak memory 222536 kb
Host smart-0df642f9-ca9e-4953-8402-6a1dfa878756
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954124981 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.3954124981
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1274809175
Short name T63
Test name
Test status
Simulation time 518527176 ps
CPU time 4.14 seconds
Started Aug 17 06:39:35 PM PDT 24
Finished Aug 17 06:39:39 PM PDT 24
Peak memory 211132 kb
Host smart-29925065-27e1-4838-9156-ec55057af416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274809175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1274809175
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1998488230
Short name T208
Test name
Test status
Simulation time 6025384693 ps
CPU time 61.8 seconds
Started Aug 17 06:39:45 PM PDT 24
Finished Aug 17 06:40:47 PM PDT 24
Peak memory 211392 kb
Host smart-7700a376-13f0-4170-b971-61a1f282f249
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998488230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1998488230
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1511168475
Short name T64
Test name
Test status
Simulation time 251491611 ps
CPU time 10.74 seconds
Started Aug 17 06:39:29 PM PDT 24
Finished Aug 17 06:39:40 PM PDT 24
Peak memory 211112 kb
Host smart-5ae6a305-b73b-498e-8a34-09cd2363f9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511168475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1511168475
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3781576592
Short name T143
Test name
Test status
Simulation time 103182683 ps
CPU time 5.84 seconds
Started Aug 17 06:39:29 PM PDT 24
Finished Aug 17 06:39:34 PM PDT 24
Peak memory 211148 kb
Host smart-0b820c59-4db1-4ba9-9937-cd6bc95c71fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3781576592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3781576592
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3229584041
Short name T346
Test name
Test status
Simulation time 153598504 ps
CPU time 9.39 seconds
Started Aug 17 06:39:26 PM PDT 24
Finished Aug 17 06:39:36 PM PDT 24
Peak memory 211164 kb
Host smart-036d3e13-c256-4000-9f58-908af46ef930
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229584041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3229584041
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3681465265
Short name T300
Test name
Test status
Simulation time 22031453792 ps
CPU time 366.33 seconds
Started Aug 17 06:39:30 PM PDT 24
Finished Aug 17 06:45:37 PM PDT 24
Peak memory 227708 kb
Host smart-82a4a406-b497-4e42-8c52-b9fd91eb8414
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681465265 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3681465265
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2840483039
Short name T271
Test name
Test status
Simulation time 928003126 ps
CPU time 3.92 seconds
Started Aug 17 06:38:44 PM PDT 24
Finished Aug 17 06:38:48 PM PDT 24
Peak memory 211136 kb
Host smart-787b3f99-485b-479a-848a-daf6123d5b5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840483039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2840483039
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3066946732
Short name T234
Test name
Test status
Simulation time 2726442768 ps
CPU time 120.12 seconds
Started Aug 17 06:38:51 PM PDT 24
Finished Aug 17 06:40:51 PM PDT 24
Peak memory 212900 kb
Host smart-ec32c1b0-c5e3-4a6f-8115-136aee096b89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066946732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3066946732
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4011326954
Short name T40
Test name
Test status
Simulation time 1137155639 ps
CPU time 10.66 seconds
Started Aug 17 06:39:03 PM PDT 24
Finished Aug 17 06:39:14 PM PDT 24
Peak memory 211468 kb
Host smart-d57be0e4-9580-4fc4-acf3-17a1fb579946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011326954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.4011326954
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1240946603
Short name T340
Test name
Test status
Simulation time 136780178 ps
CPU time 6.27 seconds
Started Aug 17 06:38:58 PM PDT 24
Finished Aug 17 06:39:04 PM PDT 24
Peak memory 211132 kb
Host smart-e2ab7aea-de83-43da-bb85-9ebebe3741ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1240946603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1240946603
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.7502944
Short name T244
Test name
Test status
Simulation time 514984975 ps
CPU time 6.1 seconds
Started Aug 17 06:38:57 PM PDT 24
Finished Aug 17 06:39:03 PM PDT 24
Peak memory 211536 kb
Host smart-b2e9d2f8-4afd-4bef-acf2-7cce05b4763b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7502944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.7502944
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3251383529
Short name T148
Test name
Test status
Simulation time 247451603 ps
CPU time 13.29 seconds
Started Aug 17 06:38:46 PM PDT 24
Finished Aug 17 06:38:59 PM PDT 24
Peak memory 213212 kb
Host smart-ea65baab-aafa-4edc-bc4f-51e2c7cfb790
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251383529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3251383529
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1680508368
Short name T304
Test name
Test status
Simulation time 4030162379 ps
CPU time 44.84 seconds
Started Aug 17 06:38:54 PM PDT 24
Finished Aug 17 06:39:39 PM PDT 24
Peak memory 222968 kb
Host smart-57d579b3-2d60-4a94-a6cf-49d5711eadcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680508368 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.1680508368
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2943786297
Short name T7
Test name
Test status
Simulation time 86803205 ps
CPU time 4.27 seconds
Started Aug 17 06:38:46 PM PDT 24
Finished Aug 17 06:38:50 PM PDT 24
Peak memory 211136 kb
Host smart-f9e0aa3b-7893-4282-81ac-a0a0086383fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943786297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2943786297
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3802110662
Short name T324
Test name
Test status
Simulation time 8313767272 ps
CPU time 108.63 seconds
Started Aug 17 06:38:42 PM PDT 24
Finished Aug 17 06:40:31 PM PDT 24
Peak memory 237092 kb
Host smart-e7a78d23-9fd3-4a5c-acbb-be1b9adcb712
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802110662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3802110662
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1005232294
Short name T166
Test name
Test status
Simulation time 285245142 ps
CPU time 10.52 seconds
Started Aug 17 06:38:43 PM PDT 24
Finished Aug 17 06:38:53 PM PDT 24
Peak memory 211592 kb
Host smart-c29e23bb-4018-415e-b65f-1de5aa308d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005232294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1005232294
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.344774376
Short name T150
Test name
Test status
Simulation time 139322299 ps
CPU time 6.39 seconds
Started Aug 17 06:38:44 PM PDT 24
Finished Aug 17 06:38:50 PM PDT 24
Peak memory 211156 kb
Host smart-8b06a4a8-57df-42c8-aa29-460cb0bd5770
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=344774376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.344774376
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2056135149
Short name T18
Test name
Test status
Simulation time 1020644787 ps
CPU time 8.34 seconds
Started Aug 17 06:38:43 PM PDT 24
Finished Aug 17 06:38:52 PM PDT 24
Peak memory 211140 kb
Host smart-2600f6dc-20f3-43c5-8dc0-9c1c5bf1249e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056135149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2056135149
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.350595323
Short name T204
Test name
Test status
Simulation time 824109159 ps
CPU time 16.53 seconds
Started Aug 17 06:38:54 PM PDT 24
Finished Aug 17 06:39:11 PM PDT 24
Peak memory 214396 kb
Host smart-b89d1a7d-84b9-4e61-b5ab-9bc42ee42d9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350595323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.350595323
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1574992829
Short name T297
Test name
Test status
Simulation time 2478947978 ps
CPU time 104.23 seconds
Started Aug 17 06:38:54 PM PDT 24
Finished Aug 17 06:40:39 PM PDT 24
Peak memory 221448 kb
Host smart-8d1c9503-aff6-4b15-b9a8-efce660d11dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574992829 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.1574992829
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.4189178051
Short name T320
Test name
Test status
Simulation time 88018507 ps
CPU time 4.1 seconds
Started Aug 17 06:38:42 PM PDT 24
Finished Aug 17 06:38:46 PM PDT 24
Peak memory 211132 kb
Host smart-c277d8ec-64c0-4a7a-b662-997b43d80ea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189178051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.4189178051
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3698072611
Short name T295
Test name
Test status
Simulation time 2139535535 ps
CPU time 62.9 seconds
Started Aug 17 06:38:51 PM PDT 24
Finished Aug 17 06:39:55 PM PDT 24
Peak memory 228460 kb
Host smart-2276487f-23f1-4d74-bf7b-3cdae3ce1d13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698072611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3698072611
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1991080678
Short name T249
Test name
Test status
Simulation time 221475496 ps
CPU time 6.34 seconds
Started Aug 17 06:38:59 PM PDT 24
Finished Aug 17 06:39:06 PM PDT 24
Peak memory 211152 kb
Host smart-f5a3f623-d7d1-41bc-84f8-a955698db014
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1991080678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1991080678
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1312848799
Short name T53
Test name
Test status
Simulation time 415644434 ps
CPU time 5.23 seconds
Started Aug 17 06:38:50 PM PDT 24
Finished Aug 17 06:38:55 PM PDT 24
Peak memory 212344 kb
Host smart-73016710-bc1b-4e83-88da-1e0d6ad07ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312848799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1312848799
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.4113910019
Short name T236
Test name
Test status
Simulation time 227123088 ps
CPU time 10.3 seconds
Started Aug 17 06:38:46 PM PDT 24
Finished Aug 17 06:38:56 PM PDT 24
Peak memory 214324 kb
Host smart-b863c8dd-2a62-4ff7-8226-e0b5314b4cee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113910019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.4113910019
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2082042182
Short name T50
Test name
Test status
Simulation time 19944614566 ps
CPU time 170.82 seconds
Started Aug 17 06:38:50 PM PDT 24
Finished Aug 17 06:41:41 PM PDT 24
Peak memory 224008 kb
Host smart-c7a063e7-c655-45e7-91e6-214a96b8f709
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082042182 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.2082042182
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3358541775
Short name T253
Test name
Test status
Simulation time 262094019 ps
CPU time 4.78 seconds
Started Aug 17 06:39:06 PM PDT 24
Finished Aug 17 06:39:11 PM PDT 24
Peak memory 211084 kb
Host smart-a0cf34a8-ce53-4c9f-a188-fa33ecd4f173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358541775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3358541775
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2759638500
Short name T185
Test name
Test status
Simulation time 697335633 ps
CPU time 9.06 seconds
Started Aug 17 06:38:51 PM PDT 24
Finished Aug 17 06:39:00 PM PDT 24
Peak memory 211564 kb
Host smart-881d7022-b99f-4e71-a6c4-fc674e55577d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759638500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2759638500
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2084012142
Short name T9
Test name
Test status
Simulation time 268077594 ps
CPU time 5.9 seconds
Started Aug 17 06:38:55 PM PDT 24
Finished Aug 17 06:39:01 PM PDT 24
Peak memory 211136 kb
Host smart-f3f18058-f06f-4005-9a82-f4612fd6ccff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2084012142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2084012142
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3480883396
Short name T266
Test name
Test status
Simulation time 95222379 ps
CPU time 5.2 seconds
Started Aug 17 06:38:43 PM PDT 24
Finished Aug 17 06:38:48 PM PDT 24
Peak memory 212148 kb
Host smart-102049c1-af47-4435-9e3c-8a0e3519ac5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480883396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3480883396
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.635532490
Short name T6
Test name
Test status
Simulation time 742588561 ps
CPU time 10.13 seconds
Started Aug 17 06:38:52 PM PDT 24
Finished Aug 17 06:39:03 PM PDT 24
Peak memory 214304 kb
Host smart-d2c3150a-b31b-478b-b55b-c58019ac52b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635532490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.635532490
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.312796932
Short name T268
Test name
Test status
Simulation time 7104040562 ps
CPU time 72.2 seconds
Started Aug 17 06:38:47 PM PDT 24
Finished Aug 17 06:39:59 PM PDT 24
Peak memory 221796 kb
Host smart-cbd9c9fb-0f3c-4b55-a78d-fd5d5b539421
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312796932 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.312796932
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1050467435
Short name T317
Test name
Test status
Simulation time 428919601 ps
CPU time 4.75 seconds
Started Aug 17 06:38:45 PM PDT 24
Finished Aug 17 06:38:50 PM PDT 24
Peak memory 211128 kb
Host smart-a3cdf1f4-e40a-4208-bd3e-23b0be0ea8b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050467435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1050467435
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2899378594
Short name T281
Test name
Test status
Simulation time 11419540928 ps
CPU time 84.34 seconds
Started Aug 17 06:38:46 PM PDT 24
Finished Aug 17 06:40:10 PM PDT 24
Peak memory 236648 kb
Host smart-8f4b7148-b4ab-4248-9850-4b386709f709
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899378594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2899378594
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.790654005
Short name T139
Test name
Test status
Simulation time 512093777 ps
CPU time 10.26 seconds
Started Aug 17 06:38:47 PM PDT 24
Finished Aug 17 06:38:58 PM PDT 24
Peak memory 211652 kb
Host smart-2cf200fb-ebe5-444f-9da6-ffbf9e43ec00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790654005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.790654005
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3113648706
Short name T334
Test name
Test status
Simulation time 410387050 ps
CPU time 6.11 seconds
Started Aug 17 06:38:59 PM PDT 24
Finished Aug 17 06:39:11 PM PDT 24
Peak memory 211140 kb
Host smart-6ea50162-eab1-4424-bd90-6956e0557aa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3113648706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3113648706
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.939968248
Short name T77
Test name
Test status
Simulation time 106174090 ps
CPU time 5.32 seconds
Started Aug 17 06:39:03 PM PDT 24
Finished Aug 17 06:39:08 PM PDT 24
Peak memory 212092 kb
Host smart-9fb383fc-e245-447c-ae57-fcd0d4537ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939968248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.939968248
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2445295041
Short name T261
Test name
Test status
Simulation time 543020985 ps
CPU time 8.62 seconds
Started Aug 17 06:38:43 PM PDT 24
Finished Aug 17 06:38:52 PM PDT 24
Peak memory 211516 kb
Host smart-82a6ba45-fc7e-4ef2-9ffe-339476e7716b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445295041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2445295041
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.735344112
Short name T46
Test name
Test status
Simulation time 114178736 ps
CPU time 7.06 seconds
Started Aug 17 06:39:01 PM PDT 24
Finished Aug 17 06:39:08 PM PDT 24
Peak memory 218268 kb
Host smart-615f612e-6d88-4114-b60b-aa3bab82c593
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735344112 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.735344112
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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