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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.63 96.89 92.56 97.67 100.00 98.62 97.90 99.77


Total test records in report: 454
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T300 /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1531339183 Aug 19 04:26:51 PM PDT 24 Aug 19 04:28:36 PM PDT 24 11320121885 ps
T301 /workspace/coverage/default/7.rom_ctrl_smoke.901807631 Aug 19 04:26:23 PM PDT 24 Aug 19 04:26:29 PM PDT 24 99445485 ps
T302 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.928870154 Aug 19 04:26:36 PM PDT 24 Aug 19 04:26:45 PM PDT 24 169252737 ps
T303 /workspace/coverage/default/34.rom_ctrl_alert_test.727242499 Aug 19 04:27:05 PM PDT 24 Aug 19 04:27:10 PM PDT 24 320347982 ps
T304 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2457567905 Aug 19 04:26:48 PM PDT 24 Aug 19 04:26:58 PM PDT 24 346330828 ps
T305 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1700236231 Aug 19 04:26:48 PM PDT 24 Aug 19 04:26:57 PM PDT 24 175564034 ps
T306 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1693811678 Aug 19 04:26:46 PM PDT 24 Aug 19 04:26:51 PM PDT 24 96944935 ps
T307 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2637184252 Aug 19 04:27:15 PM PDT 24 Aug 19 04:27:21 PM PDT 24 1864188042 ps
T308 /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.112838190 Aug 19 04:26:30 PM PDT 24 Aug 19 04:30:41 PM PDT 24 3602958147 ps
T309 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.342108299 Aug 19 04:27:11 PM PDT 24 Aug 19 04:27:22 PM PDT 24 251777346 ps
T310 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2493121627 Aug 19 04:26:53 PM PDT 24 Aug 19 04:27:01 PM PDT 24 510600160 ps
T311 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3096577163 Aug 19 04:26:47 PM PDT 24 Aug 19 04:27:51 PM PDT 24 1233674370 ps
T312 /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1010892083 Aug 19 04:26:55 PM PDT 24 Aug 19 04:30:03 PM PDT 24 11357266288 ps
T313 /workspace/coverage/default/39.rom_ctrl_stress_all.3840035252 Aug 19 04:26:49 PM PDT 24 Aug 19 04:27:01 PM PDT 24 198418408 ps
T314 /workspace/coverage/default/29.rom_ctrl_alert_test.2990924990 Aug 19 04:26:58 PM PDT 24 Aug 19 04:27:03 PM PDT 24 168439751 ps
T315 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3054902841 Aug 19 04:26:50 PM PDT 24 Aug 19 04:28:02 PM PDT 24 9685353681 ps
T316 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2825340206 Aug 19 04:26:50 PM PDT 24 Aug 19 04:28:12 PM PDT 24 6706729004 ps
T317 /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1277027631 Aug 19 04:27:49 PM PDT 24 Aug 19 04:29:38 PM PDT 24 1890233536 ps
T318 /workspace/coverage/default/49.rom_ctrl_alert_test.9797739 Aug 19 04:27:53 PM PDT 24 Aug 19 04:27:58 PM PDT 24 500250995 ps
T319 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.494445954 Aug 19 04:26:21 PM PDT 24 Aug 19 04:27:53 PM PDT 24 1471596427 ps
T320 /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.4115844878 Aug 19 04:26:54 PM PDT 24 Aug 19 04:27:19 PM PDT 24 2860440069 ps
T321 /workspace/coverage/default/14.rom_ctrl_stress_all.3871085140 Aug 19 04:26:43 PM PDT 24 Aug 19 04:26:51 PM PDT 24 387937611 ps
T322 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1846901936 Aug 19 04:27:14 PM PDT 24 Aug 19 04:27:23 PM PDT 24 173147138 ps
T323 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.4088907339 Aug 19 04:26:49 PM PDT 24 Aug 19 04:26:58 PM PDT 24 693254970 ps
T324 /workspace/coverage/default/23.rom_ctrl_stress_all.2991560135 Aug 19 04:26:58 PM PDT 24 Aug 19 04:27:07 PM PDT 24 837428289 ps
T325 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2463093265 Aug 19 04:26:55 PM PDT 24 Aug 19 04:27:01 PM PDT 24 338612254 ps
T326 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3931385142 Aug 19 04:26:59 PM PDT 24 Aug 19 04:31:12 PM PDT 24 17451427369 ps
T327 /workspace/coverage/default/16.rom_ctrl_alert_test.2810385540 Aug 19 04:26:48 PM PDT 24 Aug 19 04:26:52 PM PDT 24 1127360511 ps
T328 /workspace/coverage/default/27.rom_ctrl_alert_test.651861167 Aug 19 04:26:54 PM PDT 24 Aug 19 04:26:59 PM PDT 24 131727807 ps
T329 /workspace/coverage/default/5.rom_ctrl_stress_all.2778807141 Aug 19 04:26:20 PM PDT 24 Aug 19 04:26:31 PM PDT 24 210418733 ps
T330 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.116494083 Aug 19 04:27:05 PM PDT 24 Aug 19 04:27:16 PM PDT 24 2079466254 ps
T331 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.520625711 Aug 19 04:26:39 PM PDT 24 Aug 19 04:28:40 PM PDT 24 2592535947 ps
T332 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.317281618 Aug 19 04:26:46 PM PDT 24 Aug 19 04:26:55 PM PDT 24 280870397 ps
T333 /workspace/coverage/default/34.rom_ctrl_stress_all.3866689977 Aug 19 04:27:10 PM PDT 24 Aug 19 04:27:23 PM PDT 24 764791172 ps
T18 /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2183838171 Aug 19 04:26:54 PM PDT 24 Aug 19 04:28:46 PM PDT 24 6277325975 ps
T334 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3518573972 Aug 19 04:26:15 PM PDT 24 Aug 19 04:26:26 PM PDT 24 253126484 ps
T335 /workspace/coverage/default/18.rom_ctrl_alert_test.33414402 Aug 19 04:26:50 PM PDT 24 Aug 19 04:26:55 PM PDT 24 782831466 ps
T336 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2339608233 Aug 19 04:26:52 PM PDT 24 Aug 19 04:28:11 PM PDT 24 12681395043 ps
T337 /workspace/coverage/default/6.rom_ctrl_stress_all.3826901385 Aug 19 04:26:25 PM PDT 24 Aug 19 04:26:37 PM PDT 24 224669439 ps
T338 /workspace/coverage/default/1.rom_ctrl_alert_test.1966883111 Aug 19 04:26:50 PM PDT 24 Aug 19 04:26:55 PM PDT 24 255594742 ps
T339 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3907263944 Aug 19 04:27:08 PM PDT 24 Aug 19 04:29:36 PM PDT 24 4645152054 ps
T340 /workspace/coverage/default/49.rom_ctrl_stress_all.2854089588 Aug 19 04:26:53 PM PDT 24 Aug 19 04:27:11 PM PDT 24 6253292317 ps
T341 /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.773558559 Aug 19 04:26:33 PM PDT 24 Aug 19 04:30:57 PM PDT 24 87274527729 ps
T342 /workspace/coverage/default/42.rom_ctrl_alert_test.125705409 Aug 19 04:26:51 PM PDT 24 Aug 19 04:26:55 PM PDT 24 88268560 ps
T343 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2183751445 Aug 19 04:26:59 PM PDT 24 Aug 19 04:27:08 PM PDT 24 2083679551 ps
T344 /workspace/coverage/default/11.rom_ctrl_stress_all.1833412784 Aug 19 04:26:30 PM PDT 24 Aug 19 04:26:48 PM PDT 24 397764266 ps
T345 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2574471248 Aug 19 04:26:50 PM PDT 24 Aug 19 04:26:55 PM PDT 24 267586514 ps
T346 /workspace/coverage/default/22.rom_ctrl_stress_all.2114838919 Aug 19 04:26:42 PM PDT 24 Aug 19 04:27:02 PM PDT 24 4583343373 ps
T347 /workspace/coverage/default/33.rom_ctrl_alert_test.821443860 Aug 19 04:26:56 PM PDT 24 Aug 19 04:27:01 PM PDT 24 543818281 ps
T348 /workspace/coverage/default/45.rom_ctrl_alert_test.1530413997 Aug 19 04:27:10 PM PDT 24 Aug 19 04:27:15 PM PDT 24 1769733649 ps
T349 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.200153802 Aug 19 04:26:49 PM PDT 24 Aug 19 04:26:55 PM PDT 24 385657503 ps
T350 /workspace/coverage/default/10.rom_ctrl_stress_all.1634625976 Aug 19 04:26:47 PM PDT 24 Aug 19 04:27:00 PM PDT 24 218581031 ps
T351 /workspace/coverage/default/14.rom_ctrl_alert_test.4007926293 Aug 19 04:26:44 PM PDT 24 Aug 19 04:26:48 PM PDT 24 88336626 ps
T352 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.859793257 Aug 19 04:26:45 PM PDT 24 Aug 19 04:28:21 PM PDT 24 4347150109 ps
T353 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2554239775 Aug 19 04:26:45 PM PDT 24 Aug 19 04:29:07 PM PDT 24 4521254209 ps
T354 /workspace/coverage/default/15.rom_ctrl_stress_all.1252919528 Aug 19 04:26:39 PM PDT 24 Aug 19 04:26:46 PM PDT 24 161168442 ps
T355 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.957902275 Aug 19 04:27:05 PM PDT 24 Aug 19 04:28:50 PM PDT 24 8505022965 ps
T356 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2166484702 Aug 19 04:26:46 PM PDT 24 Aug 19 04:26:56 PM PDT 24 509344364 ps
T357 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2589460107 Aug 19 04:26:59 PM PDT 24 Aug 19 04:27:04 PM PDT 24 180863692 ps
T358 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.991276261 Aug 19 04:27:45 PM PDT 24 Aug 19 04:27:56 PM PDT 24 1134842438 ps
T56 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3928217884 Aug 19 04:25:18 PM PDT 24 Aug 19 04:25:40 PM PDT 24 529883350 ps
T52 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4149372088 Aug 19 04:25:14 PM PDT 24 Aug 19 04:25:52 PM PDT 24 2607273867 ps
T53 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2895645859 Aug 19 04:25:06 PM PDT 24 Aug 19 04:25:43 PM PDT 24 603305974 ps
T359 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2498374313 Aug 19 04:24:56 PM PDT 24 Aug 19 04:25:01 PM PDT 24 2481559324 ps
T94 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.936596945 Aug 19 04:25:10 PM PDT 24 Aug 19 04:25:15 PM PDT 24 132950700 ps
T61 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2404767898 Aug 19 04:25:21 PM PDT 24 Aug 19 04:25:26 PM PDT 24 290439782 ps
T360 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.514840890 Aug 19 04:25:04 PM PDT 24 Aug 19 04:25:09 PM PDT 24 366978804 ps
T62 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.790961665 Aug 19 04:25:03 PM PDT 24 Aug 19 04:25:08 PM PDT 24 99935493 ps
T95 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3324565549 Aug 19 04:24:56 PM PDT 24 Aug 19 04:25:00 PM PDT 24 89062767 ps
T63 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3810391836 Aug 19 04:25:07 PM PDT 24 Aug 19 04:25:11 PM PDT 24 173015934 ps
T361 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1485084874 Aug 19 04:25:04 PM PDT 24 Aug 19 04:25:09 PM PDT 24 398357468 ps
T64 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4006712951 Aug 19 04:25:08 PM PDT 24 Aug 19 04:25:35 PM PDT 24 1018340964 ps
T90 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1283931615 Aug 19 04:25:12 PM PDT 24 Aug 19 04:25:17 PM PDT 24 2075821066 ps
T96 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1540050475 Aug 19 04:25:04 PM PDT 24 Aug 19 04:25:26 PM PDT 24 2402542844 ps
T362 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.104529465 Aug 19 04:25:13 PM PDT 24 Aug 19 04:25:22 PM PDT 24 128358719 ps
T97 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2217741882 Aug 19 04:25:05 PM PDT 24 Aug 19 04:25:10 PM PDT 24 127000823 ps
T363 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2932014575 Aug 19 04:24:56 PM PDT 24 Aug 19 04:25:01 PM PDT 24 538472627 ps
T364 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.752995288 Aug 19 04:24:49 PM PDT 24 Aug 19 04:24:54 PM PDT 24 255236086 ps
T65 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3162180467 Aug 19 04:25:08 PM PDT 24 Aug 19 04:25:15 PM PDT 24 143988911 ps
T66 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.944163443 Aug 19 04:25:06 PM PDT 24 Aug 19 04:25:12 PM PDT 24 498816805 ps
T365 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.287535436 Aug 19 04:25:12 PM PDT 24 Aug 19 04:25:17 PM PDT 24 143001370 ps
T67 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1442625357 Aug 19 04:25:16 PM PDT 24 Aug 19 04:25:41 PM PDT 24 1360472380 ps
T54 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2632279318 Aug 19 04:25:01 PM PDT 24 Aug 19 04:26:09 PM PDT 24 1027529726 ps
T68 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2831009905 Aug 19 04:25:03 PM PDT 24 Aug 19 04:25:21 PM PDT 24 373710351 ps
T69 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.893258080 Aug 19 04:24:53 PM PDT 24 Aug 19 04:25:14 PM PDT 24 4387046082 ps
T366 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3398818618 Aug 19 04:25:08 PM PDT 24 Aug 19 04:25:13 PM PDT 24 510477055 ps
T91 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3726156226 Aug 19 04:25:06 PM PDT 24 Aug 19 04:25:12 PM PDT 24 133238045 ps
T367 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1199592151 Aug 19 04:25:09 PM PDT 24 Aug 19 04:25:14 PM PDT 24 133266852 ps
T368 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3695476352 Aug 19 04:24:55 PM PDT 24 Aug 19 04:24:59 PM PDT 24 111847670 ps
T369 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3572218474 Aug 19 04:25:08 PM PDT 24 Aug 19 04:25:13 PM PDT 24 401247933 ps
T370 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1314720853 Aug 19 04:24:57 PM PDT 24 Aug 19 04:25:01 PM PDT 24 172418916 ps
T371 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3450271588 Aug 19 04:25:00 PM PDT 24 Aug 19 04:25:10 PM PDT 24 170012591 ps
T92 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3798846971 Aug 19 04:25:05 PM PDT 24 Aug 19 04:25:12 PM PDT 24 549917094 ps
T372 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2372564847 Aug 19 04:25:06 PM PDT 24 Aug 19 04:25:11 PM PDT 24 2473894453 ps
T78 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1648078626 Aug 19 04:25:09 PM PDT 24 Aug 19 04:25:39 PM PDT 24 805089945 ps
T93 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2117446869 Aug 19 04:25:07 PM PDT 24 Aug 19 04:25:11 PM PDT 24 175560990 ps
T373 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.208457775 Aug 19 04:24:56 PM PDT 24 Aug 19 04:25:01 PM PDT 24 130319062 ps
T374 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2573700178 Aug 19 04:25:06 PM PDT 24 Aug 19 04:25:13 PM PDT 24 2087509017 ps
T79 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.999678552 Aug 19 04:25:12 PM PDT 24 Aug 19 04:25:42 PM PDT 24 834993488 ps
T375 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4093865485 Aug 19 04:25:03 PM PDT 24 Aug 19 04:25:07 PM PDT 24 93459404 ps
T376 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4092837824 Aug 19 04:25:05 PM PDT 24 Aug 19 04:25:10 PM PDT 24 132600249 ps
T80 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.981192369 Aug 19 04:25:04 PM PDT 24 Aug 19 04:25:35 PM PDT 24 9879716895 ps
T81 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2002290525 Aug 19 04:25:09 PM PDT 24 Aug 19 04:25:35 PM PDT 24 1111807855 ps
T377 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1158595208 Aug 19 04:25:18 PM PDT 24 Aug 19 04:25:24 PM PDT 24 551495324 ps
T378 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1382619396 Aug 19 04:25:00 PM PDT 24 Aug 19 04:25:04 PM PDT 24 129694456 ps
T379 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1747321729 Aug 19 04:25:04 PM PDT 24 Aug 19 04:25:09 PM PDT 24 91436508 ps
T109 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3879603110 Aug 19 04:25:10 PM PDT 24 Aug 19 04:25:46 PM PDT 24 1353561934 ps
T380 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3999363406 Aug 19 04:25:11 PM PDT 24 Aug 19 04:25:17 PM PDT 24 555412576 ps
T381 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.833271687 Aug 19 04:25:09 PM PDT 24 Aug 19 04:25:34 PM PDT 24 537812934 ps
T82 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1162310410 Aug 19 04:25:06 PM PDT 24 Aug 19 04:25:37 PM PDT 24 789493945 ps
T382 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2529434876 Aug 19 04:25:05 PM PDT 24 Aug 19 04:25:14 PM PDT 24 503977791 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1081783284 Aug 19 04:24:55 PM PDT 24 Aug 19 04:24:59 PM PDT 24 1035095752 ps
T384 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1566427364 Aug 19 04:24:53 PM PDT 24 Aug 19 04:24:58 PM PDT 24 104987809 ps
T385 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3756962491 Aug 19 04:24:56 PM PDT 24 Aug 19 04:25:01 PM PDT 24 128423273 ps
T106 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3188570206 Aug 19 04:25:04 PM PDT 24 Aug 19 04:26:13 PM PDT 24 273642107 ps
T386 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3320694427 Aug 19 04:25:09 PM PDT 24 Aug 19 04:25:13 PM PDT 24 172876837 ps
T387 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.501440523 Aug 19 04:24:56 PM PDT 24 Aug 19 04:25:03 PM PDT 24 505172462 ps
T89 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4132255125 Aug 19 04:25:04 PM PDT 24 Aug 19 04:25:35 PM PDT 24 802081493 ps
T102 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2969827360 Aug 19 04:25:10 PM PDT 24 Aug 19 04:26:19 PM PDT 24 355999487 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3474975122 Aug 19 04:25:03 PM PDT 24 Aug 19 04:25:34 PM PDT 24 827524887 ps
T389 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3214852741 Aug 19 04:25:09 PM PDT 24 Aug 19 04:25:17 PM PDT 24 124805824 ps
T390 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2982462525 Aug 19 04:25:07 PM PDT 24 Aug 19 04:25:12 PM PDT 24 161954443 ps
T112 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.414986642 Aug 19 04:24:57 PM PDT 24 Aug 19 04:26:07 PM PDT 24 1500874114 ps
T105 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3126406762 Aug 19 04:24:54 PM PDT 24 Aug 19 04:25:34 PM PDT 24 551935041 ps
T100 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1475451247 Aug 19 04:25:06 PM PDT 24 Aug 19 04:26:16 PM PDT 24 682939016 ps
T391 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2787979875 Aug 19 04:25:09 PM PDT 24 Aug 19 04:25:13 PM PDT 24 362770250 ps
T107 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1270398875 Aug 19 04:25:07 PM PDT 24 Aug 19 04:26:16 PM PDT 24 246695848 ps
T110 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.645784702 Aug 19 04:24:56 PM PDT 24 Aug 19 04:26:05 PM PDT 24 628706959 ps
T392 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3924340267 Aug 19 04:25:10 PM PDT 24 Aug 19 04:25:15 PM PDT 24 501022647 ps
T108 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.559669692 Aug 19 04:25:08 PM PDT 24 Aug 19 04:26:16 PM PDT 24 371472306 ps
T393 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3278569636 Aug 19 04:25:09 PM PDT 24 Aug 19 04:25:46 PM PDT 24 1355581840 ps
T394 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.824192165 Aug 19 04:25:04 PM PDT 24 Aug 19 04:25:11 PM PDT 24 88883394 ps
T395 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1671291958 Aug 19 04:24:56 PM PDT 24 Aug 19 04:25:03 PM PDT 24 1654229300 ps
T396 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1942833305 Aug 19 04:25:06 PM PDT 24 Aug 19 04:25:13 PM PDT 24 500930194 ps
T103 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4119634800 Aug 19 04:24:56 PM PDT 24 Aug 19 04:26:05 PM PDT 24 914247732 ps
T397 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2977442996 Aug 19 04:24:57 PM PDT 24 Aug 19 04:25:02 PM PDT 24 520186608 ps
T114 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3263785328 Aug 19 04:25:03 PM PDT 24 Aug 19 04:25:43 PM PDT 24 357111555 ps
T84 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.828795939 Aug 19 04:25:06 PM PDT 24 Aug 19 04:25:36 PM PDT 24 787066590 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2049483698 Aug 19 04:24:55 PM PDT 24 Aug 19 04:25:00 PM PDT 24 132907671 ps
T399 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4026933206 Aug 19 04:25:03 PM PDT 24 Aug 19 04:25:08 PM PDT 24 560413653 ps
T400 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4182492779 Aug 19 04:25:06 PM PDT 24 Aug 19 04:25:11 PM PDT 24 518104969 ps
T83 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3479953663 Aug 19 04:25:04 PM PDT 24 Aug 19 04:25:08 PM PDT 24 348015880 ps
T401 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2479711264 Aug 19 04:25:10 PM PDT 24 Aug 19 04:25:15 PM PDT 24 146621609 ps
T402 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4283313739 Aug 19 04:25:12 PM PDT 24 Aug 19 04:25:16 PM PDT 24 109234744 ps
T403 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1478527169 Aug 19 04:25:04 PM PDT 24 Aug 19 04:25:11 PM PDT 24 139637026 ps
T404 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1317955204 Aug 19 04:25:19 PM PDT 24 Aug 19 04:25:55 PM PDT 24 150322922 ps
T405 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.463867061 Aug 19 04:25:16 PM PDT 24 Aug 19 04:25:22 PM PDT 24 140619898 ps
T85 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2802613031 Aug 19 04:24:58 PM PDT 24 Aug 19 04:25:03 PM PDT 24 502011154 ps
T406 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1018369855 Aug 19 04:25:18 PM PDT 24 Aug 19 04:25:26 PM PDT 24 250581504 ps
T101 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1714587128 Aug 19 04:25:13 PM PDT 24 Aug 19 04:25:50 PM PDT 24 222880027 ps
T407 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2059094753 Aug 19 04:24:57 PM PDT 24 Aug 19 04:25:04 PM PDT 24 1231340267 ps
T113 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2785390063 Aug 19 04:25:06 PM PDT 24 Aug 19 04:26:14 PM PDT 24 2901320422 ps
T408 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.569480963 Aug 19 04:25:08 PM PDT 24 Aug 19 04:25:16 PM PDT 24 254243738 ps
T409 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3791489752 Aug 19 04:25:05 PM PDT 24 Aug 19 04:25:37 PM PDT 24 1705951786 ps
T410 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4023019194 Aug 19 04:25:10 PM PDT 24 Aug 19 04:25:15 PM PDT 24 260428400 ps
T411 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2176731643 Aug 19 04:25:17 PM PDT 24 Aug 19 04:25:27 PM PDT 24 194409086 ps
T412 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1594198206 Aug 19 04:25:05 PM PDT 24 Aug 19 04:25:12 PM PDT 24 86887366 ps
T413 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.947934577 Aug 19 04:25:10 PM PDT 24 Aug 19 04:25:14 PM PDT 24 361981161 ps
T414 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2188715678 Aug 19 04:24:55 PM PDT 24 Aug 19 04:25:05 PM PDT 24 434418244 ps
T415 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.738373522 Aug 19 04:24:48 PM PDT 24 Aug 19 04:24:55 PM PDT 24 2439412872 ps
T416 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3286406636 Aug 19 04:25:02 PM PDT 24 Aug 19 04:25:09 PM PDT 24 86466430 ps
T417 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3121859017 Aug 19 04:24:56 PM PDT 24 Aug 19 04:25:01 PM PDT 24 94687078 ps
T418 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3459328295 Aug 19 04:25:06 PM PDT 24 Aug 19 04:25:13 PM PDT 24 1184123136 ps
T419 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2948316964 Aug 19 04:25:05 PM PDT 24 Aug 19 04:25:10 PM PDT 24 498256544 ps
T420 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.697038262 Aug 19 04:24:55 PM PDT 24 Aug 19 04:25:03 PM PDT 24 503513217 ps
T421 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1502891849 Aug 19 04:24:58 PM PDT 24 Aug 19 04:25:04 PM PDT 24 351898148 ps
T422 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2292738261 Aug 19 04:24:55 PM PDT 24 Aug 19 04:25:00 PM PDT 24 625371633 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3899816789 Aug 19 04:25:06 PM PDT 24 Aug 19 04:25:10 PM PDT 24 88256284 ps
T111 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4156514825 Aug 19 04:25:08 PM PDT 24 Aug 19 04:26:17 PM PDT 24 974380384 ps
T424 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2246901891 Aug 19 04:25:15 PM PDT 24 Aug 19 04:25:20 PM PDT 24 126929453 ps
T425 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.508961073 Aug 19 04:25:11 PM PDT 24 Aug 19 04:25:16 PM PDT 24 133406354 ps
T426 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1195614326 Aug 19 04:25:04 PM PDT 24 Aug 19 04:25:09 PM PDT 24 521626802 ps
T427 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.552399227 Aug 19 04:25:04 PM PDT 24 Aug 19 04:25:09 PM PDT 24 256383959 ps
T86 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.681732307 Aug 19 04:25:20 PM PDT 24 Aug 19 04:25:24 PM PDT 24 350500671 ps
T428 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.299263291 Aug 19 04:25:06 PM PDT 24 Aug 19 04:25:15 PM PDT 24 256435562 ps
T429 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1206133362 Aug 19 04:24:59 PM PDT 24 Aug 19 04:25:07 PM PDT 24 1249988861 ps
T430 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3158730980 Aug 19 04:25:11 PM PDT 24 Aug 19 04:25:16 PM PDT 24 95649165 ps
T431 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.873979263 Aug 19 04:25:11 PM PDT 24 Aug 19 04:25:16 PM PDT 24 97381143 ps
T432 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.897756536 Aug 19 04:25:09 PM PDT 24 Aug 19 04:25:14 PM PDT 24 184105106 ps
T433 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2148462136 Aug 19 04:24:54 PM PDT 24 Aug 19 04:25:00 PM PDT 24 397659428 ps
T434 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.13963488 Aug 19 04:24:57 PM PDT 24 Aug 19 04:25:01 PM PDT 24 599409031 ps
T435 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3544486066 Aug 19 04:26:00 PM PDT 24 Aug 19 04:26:05 PM PDT 24 262511696 ps
T436 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1573369093 Aug 19 04:24:55 PM PDT 24 Aug 19 04:25:00 PM PDT 24 357654789 ps
T437 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1606975862 Aug 19 04:25:09 PM PDT 24 Aug 19 04:25:14 PM PDT 24 150710745 ps
T438 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2132577980 Aug 19 04:25:08 PM PDT 24 Aug 19 04:25:13 PM PDT 24 250457987 ps
T439 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4230105464 Aug 19 04:25:04 PM PDT 24 Aug 19 04:25:11 PM PDT 24 440453163 ps
T440 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.465065666 Aug 19 04:25:18 PM PDT 24 Aug 19 04:25:22 PM PDT 24 417669604 ps
T104 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1908292123 Aug 19 04:25:07 PM PDT 24 Aug 19 04:26:21 PM PDT 24 2197610087 ps
T441 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2995687003 Aug 19 04:24:47 PM PDT 24 Aug 19 04:24:52 PM PDT 24 520541969 ps
T442 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2014548463 Aug 19 04:24:49 PM PDT 24 Aug 19 04:24:54 PM PDT 24 168685466 ps
T443 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.995050886 Aug 19 04:25:02 PM PDT 24 Aug 19 04:25:06 PM PDT 24 321038450 ps
T87 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2929476248 Aug 19 04:24:49 PM PDT 24 Aug 19 04:24:57 PM PDT 24 280343793 ps
T444 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1900018600 Aug 19 04:25:04 PM PDT 24 Aug 19 04:25:11 PM PDT 24 149816775 ps
T445 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1802065005 Aug 19 04:24:56 PM PDT 24 Aug 19 04:25:26 PM PDT 24 2067748845 ps
T446 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2018027580 Aug 19 04:24:56 PM PDT 24 Aug 19 04:25:00 PM PDT 24 89972986 ps
T447 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.283954201 Aug 19 04:25:01 PM PDT 24 Aug 19 04:25:32 PM PDT 24 816625024 ps
T448 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1788298250 Aug 19 04:25:10 PM PDT 24 Aug 19 04:25:15 PM PDT 24 127347503 ps
T449 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1277280489 Aug 19 04:25:04 PM PDT 24 Aug 19 04:25:34 PM PDT 24 807263481 ps
T450 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2057744531 Aug 19 04:24:58 PM PDT 24 Aug 19 04:25:03 PM PDT 24 89990243 ps
T451 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1160789593 Aug 19 04:25:09 PM PDT 24 Aug 19 04:25:28 PM PDT 24 2194001745 ps
T88 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4108406979 Aug 19 04:24:55 PM PDT 24 Aug 19 04:24:59 PM PDT 24 337023854 ps
T452 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.816557308 Aug 19 04:24:57 PM PDT 24 Aug 19 04:25:02 PM PDT 24 431408379 ps
T453 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.743911216 Aug 19 04:25:16 PM PDT 24 Aug 19 04:25:22 PM PDT 24 95428760 ps
T454 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3315041007 Aug 19 04:25:00 PM PDT 24 Aug 19 04:25:07 PM PDT 24 89337585 ps

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3197024004
Short name T7
Test name
Test status
Simulation time 2368637595 ps
CPU time 148.39 seconds
Started Aug 19 04:27:08 PM PDT 24
Finished Aug 19 04:29:36 PM PDT 24
Peak memory 219444 kb
Host smart-1a642763-57e8-4690-984e-302192ea59d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197024004 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3197024004
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3874236497
Short name T2
Test name
Test status
Simulation time 5153689813 ps
CPU time 120 seconds
Started Aug 19 04:26:57 PM PDT 24
Finished Aug 19 04:28:57 PM PDT 24
Peak memory 234704 kb
Host smart-1d005868-4851-4819-81a8-3d69810eb2b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874236497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3874236497
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4093063641
Short name T1
Test name
Test status
Simulation time 1530670567 ps
CPU time 84.25 seconds
Started Aug 19 04:27:12 PM PDT 24
Finished Aug 19 04:28:37 PM PDT 24
Peak memory 237316 kb
Host smart-4ec19bd8-ba53-4735-af85-92bc2851f1ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093063641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.4093063641
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2632279318
Short name T54
Test name
Test status
Simulation time 1027529726 ps
CPU time 67.09 seconds
Started Aug 19 04:25:01 PM PDT 24
Finished Aug 19 04:26:09 PM PDT 24
Peak memory 212948 kb
Host smart-0601a1a8-fca5-4cc6-b4c9-1ef63fd4e15f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632279318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2632279318
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.242300853
Short name T11
Test name
Test status
Simulation time 5283045125 ps
CPU time 95.47 seconds
Started Aug 19 04:26:44 PM PDT 24
Finished Aug 19 04:28:19 PM PDT 24
Peak memory 222036 kb
Host smart-a545d7b5-6154-4ea0-a88b-5b7c0cdb6af4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242300853 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.242300853
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.912367406
Short name T20
Test name
Test status
Simulation time 285404671 ps
CPU time 99.91 seconds
Started Aug 19 04:26:24 PM PDT 24
Finished Aug 19 04:28:09 PM PDT 24
Peak memory 236564 kb
Host smart-29742762-de6a-403a-83a5-9beb6c453c94
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912367406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.912367406
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2404767898
Short name T61
Test name
Test status
Simulation time 290439782 ps
CPU time 4.88 seconds
Started Aug 19 04:25:21 PM PDT 24
Finished Aug 19 04:25:26 PM PDT 24
Peak memory 218592 kb
Host smart-081f2d21-a4b7-4771-b0ea-91f1cfb204cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404767898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2404767898
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1475451247
Short name T100
Test name
Test status
Simulation time 682939016 ps
CPU time 69.57 seconds
Started Aug 19 04:25:06 PM PDT 24
Finished Aug 19 04:26:16 PM PDT 24
Peak memory 219460 kb
Host smart-ee87b883-1a47-4256-9745-15212966c54b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475451247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1475451247
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.4229265622
Short name T19
Test name
Test status
Simulation time 830807006 ps
CPU time 49.81 seconds
Started Aug 19 04:26:48 PM PDT 24
Finished Aug 19 04:27:38 PM PDT 24
Peak memory 220228 kb
Host smart-e9f8a17f-fe33-4977-b047-772da4e7b3e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229265622 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.4229265622
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3495442097
Short name T10
Test name
Test status
Simulation time 256501619 ps
CPU time 4.79 seconds
Started Aug 19 04:27:05 PM PDT 24
Finished Aug 19 04:27:09 PM PDT 24
Peak memory 210980 kb
Host smart-92969572-5f55-42c7-8c81-1c1e37e53649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495442097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3495442097
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3187538047
Short name T26
Test name
Test status
Simulation time 1029596442 ps
CPU time 14.05 seconds
Started Aug 19 04:27:03 PM PDT 24
Finished Aug 19 04:27:17 PM PDT 24
Peak memory 210996 kb
Host smart-3fa117c3-b475-4180-9467-26ea39122cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187538047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3187538047
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.570174392
Short name T294
Test name
Test status
Simulation time 1106249117 ps
CPU time 9.09 seconds
Started Aug 19 04:26:52 PM PDT 24
Finished Aug 19 04:27:01 PM PDT 24
Peak memory 210996 kb
Host smart-c1ddb269-5352-4c1b-bf98-1f02547b58b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570174392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.570174392
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1442625357
Short name T67
Test name
Test status
Simulation time 1360472380 ps
CPU time 25.56 seconds
Started Aug 19 04:25:16 PM PDT 24
Finished Aug 19 04:25:41 PM PDT 24
Peak memory 211332 kb
Host smart-e0ad6c7c-b582-4b36-8986-9e87864dcd01
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442625357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1442625357
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2969827360
Short name T102
Test name
Test status
Simulation time 355999487 ps
CPU time 68.72 seconds
Started Aug 19 04:25:10 PM PDT 24
Finished Aug 19 04:26:19 PM PDT 24
Peak memory 213024 kb
Host smart-d4f3615d-525c-49f3-ab82-f2f967520815
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969827360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2969827360
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.4014417181
Short name T3
Test name
Test status
Simulation time 549560738 ps
CPU time 5.14 seconds
Started Aug 19 04:26:11 PM PDT 24
Finished Aug 19 04:26:16 PM PDT 24
Peak memory 211000 kb
Host smart-39aa668c-279e-4667-8c28-e7cacd7e93ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4014417181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.4014417181
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.196315771
Short name T139
Test name
Test status
Simulation time 4641248267 ps
CPU time 159.68 seconds
Started Aug 19 04:26:24 PM PDT 24
Finished Aug 19 04:29:04 PM PDT 24
Peak memory 220924 kb
Host smart-e058513c-149d-4cbe-8805-ae6fd815c266
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196315771 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.196315771
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3879603110
Short name T109
Test name
Test status
Simulation time 1353561934 ps
CPU time 36.12 seconds
Started Aug 19 04:25:10 PM PDT 24
Finished Aug 19 04:25:46 PM PDT 24
Peak memory 219444 kb
Host smart-d0d2a5ed-d965-48b2-a5fd-02d33159bd0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879603110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3879603110
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3810391836
Short name T63
Test name
Test status
Simulation time 173015934 ps
CPU time 4.05 seconds
Started Aug 19 04:25:07 PM PDT 24
Finished Aug 19 04:25:11 PM PDT 24
Peak memory 211200 kb
Host smart-c1d5cf5b-d913-4d7c-9fe2-63acfc7893e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810391836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3810391836
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4045872893
Short name T72
Test name
Test status
Simulation time 355132560 ps
CPU time 5.12 seconds
Started Aug 19 04:26:35 PM PDT 24
Finished Aug 19 04:26:46 PM PDT 24
Peak memory 211404 kb
Host smart-f1a19b31-c792-43b3-8980-cc44251c1f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045872893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4045872893
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3418411488
Short name T17
Test name
Test status
Simulation time 3406152284 ps
CPU time 113.25 seconds
Started Aug 19 04:26:39 PM PDT 24
Finished Aug 19 04:28:32 PM PDT 24
Peak memory 222116 kb
Host smart-0868e8af-444e-492f-abb2-30d4161ed884
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418411488 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3418411488
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2014548463
Short name T442
Test name
Test status
Simulation time 168685466 ps
CPU time 4.02 seconds
Started Aug 19 04:24:49 PM PDT 24
Finished Aug 19 04:24:54 PM PDT 24
Peak memory 211636 kb
Host smart-2f6946ed-291b-402f-8eea-502a0f6371b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014548463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2014548463
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.738373522
Short name T415
Test name
Test status
Simulation time 2439412872 ps
CPU time 7 seconds
Started Aug 19 04:24:48 PM PDT 24
Finished Aug 19 04:24:55 PM PDT 24
Peak memory 211416 kb
Host smart-1c4c2a01-7cde-4002-89a8-13fbb2c4ac43
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738373522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.738373522
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2929476248
Short name T87
Test name
Test status
Simulation time 280343793 ps
CPU time 7.26 seconds
Started Aug 19 04:24:49 PM PDT 24
Finished Aug 19 04:24:57 PM PDT 24
Peak memory 219412 kb
Host smart-863f3bf9-b461-4035-942d-d67bbd162126
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929476248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2929476248
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1566427364
Short name T384
Test name
Test status
Simulation time 104987809 ps
CPU time 4.86 seconds
Started Aug 19 04:24:53 PM PDT 24
Finished Aug 19 04:24:58 PM PDT 24
Peak memory 215660 kb
Host smart-3f370bad-478f-42e6-b879-5ce14a97ee27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566427364 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1566427364
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2995687003
Short name T441
Test name
Test status
Simulation time 520541969 ps
CPU time 4.83 seconds
Started Aug 19 04:24:47 PM PDT 24
Finished Aug 19 04:24:52 PM PDT 24
Peak memory 211644 kb
Host smart-62d7e2f4-f8d1-4315-b9f9-7ca92cf1172c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995687003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2995687003
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.752995288
Short name T364
Test name
Test status
Simulation time 255236086 ps
CPU time 4.75 seconds
Started Aug 19 04:24:49 PM PDT 24
Finished Aug 19 04:24:54 PM PDT 24
Peak memory 210836 kb
Host smart-4b3cd0b4-bc22-449f-b9f8-3ba4d7289bd2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752995288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.752995288
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2932014575
Short name T363
Test name
Test status
Simulation time 538472627 ps
CPU time 4.63 seconds
Started Aug 19 04:24:56 PM PDT 24
Finished Aug 19 04:25:01 PM PDT 24
Peak memory 211200 kb
Host smart-8192a2f6-a9f4-486c-8246-0a618c0cf8de
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932014575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2932014575
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1802065005
Short name T445
Test name
Test status
Simulation time 2067748845 ps
CPU time 30.69 seconds
Started Aug 19 04:24:56 PM PDT 24
Finished Aug 19 04:25:26 PM PDT 24
Peak memory 211256 kb
Host smart-5d83b105-da5d-4292-aa21-4ede3f26efda
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802065005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1802065005
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1382619396
Short name T378
Test name
Test status
Simulation time 129694456 ps
CPU time 4.79 seconds
Started Aug 19 04:25:00 PM PDT 24
Finished Aug 19 04:25:04 PM PDT 24
Peak memory 218404 kb
Host smart-245adc68-8f10-4d24-bda7-3365e922ce11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382619396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1382619396
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2148462136
Short name T433
Test name
Test status
Simulation time 397659428 ps
CPU time 6 seconds
Started Aug 19 04:24:54 PM PDT 24
Finished Aug 19 04:25:00 PM PDT 24
Peak memory 219580 kb
Host smart-0ef3e4c7-5059-44fb-8adb-9a8b8c64a678
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148462136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2148462136
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.414986642
Short name T112
Test name
Test status
Simulation time 1500874114 ps
CPU time 69.94 seconds
Started Aug 19 04:24:57 PM PDT 24
Finished Aug 19 04:26:07 PM PDT 24
Peak memory 219428 kb
Host smart-2d6e9d2c-de8f-4704-8ce9-d228f88975a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414986642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.414986642
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3324565549
Short name T95
Test name
Test status
Simulation time 89062767 ps
CPU time 4.06 seconds
Started Aug 19 04:24:56 PM PDT 24
Finished Aug 19 04:25:00 PM PDT 24
Peak memory 211256 kb
Host smart-54271b65-c03a-4a4b-bedb-992524b6fbda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324565549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3324565549
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2977442996
Short name T397
Test name
Test status
Simulation time 520186608 ps
CPU time 5.07 seconds
Started Aug 19 04:24:57 PM PDT 24
Finished Aug 19 04:25:02 PM PDT 24
Peak memory 217980 kb
Host smart-37dd8744-21e7-4f87-8760-83182641b2df
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977442996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2977442996
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1573369093
Short name T436
Test name
Test status
Simulation time 357654789 ps
CPU time 5.62 seconds
Started Aug 19 04:24:55 PM PDT 24
Finished Aug 19 04:25:00 PM PDT 24
Peak memory 211236 kb
Host smart-8c7b1cb2-2461-4ffb-8091-c9f4dd1ee4a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573369093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1573369093
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.897756536
Short name T432
Test name
Test status
Simulation time 184105106 ps
CPU time 4.23 seconds
Started Aug 19 04:25:09 PM PDT 24
Finished Aug 19 04:25:14 PM PDT 24
Peak memory 219548 kb
Host smart-aba43480-ba44-4843-9216-e56ba5866b04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897756536 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.897756536
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1671291958
Short name T395
Test name
Test status
Simulation time 1654229300 ps
CPU time 6.74 seconds
Started Aug 19 04:24:56 PM PDT 24
Finished Aug 19 04:25:03 PM PDT 24
Peak memory 211292 kb
Host smart-adb29d2b-a990-4685-9508-3c32126ff086
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671291958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1671291958
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2049483698
Short name T398
Test name
Test status
Simulation time 132907671 ps
CPU time 4.85 seconds
Started Aug 19 04:24:55 PM PDT 24
Finished Aug 19 04:25:00 PM PDT 24
Peak memory 211104 kb
Host smart-fc672bde-ca2c-454e-b972-b2ff3208a7c9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049483698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2049483698
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1081783284
Short name T383
Test name
Test status
Simulation time 1035095752 ps
CPU time 4.06 seconds
Started Aug 19 04:24:55 PM PDT 24
Finished Aug 19 04:24:59 PM PDT 24
Peak memory 211132 kb
Host smart-498a6dc7-cc8a-4bec-b145-ec15e83c2d3f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081783284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1081783284
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4132255125
Short name T89
Test name
Test status
Simulation time 802081493 ps
CPU time 30.8 seconds
Started Aug 19 04:25:04 PM PDT 24
Finished Aug 19 04:25:35 PM PDT 24
Peak memory 211164 kb
Host smart-85b39584-dd3a-4d3b-afd2-395b863226be
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132255125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.4132255125
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.13963488
Short name T434
Test name
Test status
Simulation time 599409031 ps
CPU time 4.09 seconds
Started Aug 19 04:24:57 PM PDT 24
Finished Aug 19 04:25:01 PM PDT 24
Peak memory 211332 kb
Host smart-55489f42-32ad-496a-8c85-3143a844486a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13963488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_same_csr_outstanding.13963488
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2188715678
Short name T414
Test name
Test status
Simulation time 434418244 ps
CPU time 9.99 seconds
Started Aug 19 04:24:55 PM PDT 24
Finished Aug 19 04:25:05 PM PDT 24
Peak memory 219568 kb
Host smart-044d1174-e11d-41c2-ace1-22d6303d65d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188715678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2188715678
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3126406762
Short name T105
Test name
Test status
Simulation time 551935041 ps
CPU time 39.51 seconds
Started Aug 19 04:24:54 PM PDT 24
Finished Aug 19 04:25:34 PM PDT 24
Peak memory 214028 kb
Host smart-c51ca793-4ac0-4622-9f7b-edf651589eac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126406762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3126406762
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.514840890
Short name T360
Test name
Test status
Simulation time 366978804 ps
CPU time 4.98 seconds
Started Aug 19 04:25:04 PM PDT 24
Finished Aug 19 04:25:09 PM PDT 24
Peak memory 219560 kb
Host smart-8399af78-2304-4157-a123-2166fa77f17b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514840890 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.514840890
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4283313739
Short name T402
Test name
Test status
Simulation time 109234744 ps
CPU time 4.01 seconds
Started Aug 19 04:25:12 PM PDT 24
Finished Aug 19 04:25:16 PM PDT 24
Peak memory 211336 kb
Host smart-73a57637-1d10-42db-b8b7-7fc48946b026
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283313739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4283313739
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3791489752
Short name T409
Test name
Test status
Simulation time 1705951786 ps
CPU time 31.32 seconds
Started Aug 19 04:25:05 PM PDT 24
Finished Aug 19 04:25:37 PM PDT 24
Peak memory 211284 kb
Host smart-baaa4502-8040-497f-b10f-a292ede07c96
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791489752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3791489752
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1478527169
Short name T403
Test name
Test status
Simulation time 139637026 ps
CPU time 6.51 seconds
Started Aug 19 04:25:04 PM PDT 24
Finished Aug 19 04:25:11 PM PDT 24
Peak memory 211280 kb
Host smart-55565ef5-f1da-4a0a-a9b5-ca1b53cf186e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478527169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1478527169
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1594198206
Short name T412
Test name
Test status
Simulation time 86887366 ps
CPU time 6.67 seconds
Started Aug 19 04:25:05 PM PDT 24
Finished Aug 19 04:25:12 PM PDT 24
Peak memory 216292 kb
Host smart-de7ea0cc-52c0-4d9c-857a-17b8237e95ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594198206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1594198206
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2895645859
Short name T53
Test name
Test status
Simulation time 603305974 ps
CPU time 36.55 seconds
Started Aug 19 04:25:06 PM PDT 24
Finished Aug 19 04:25:43 PM PDT 24
Peak memory 211704 kb
Host smart-0ce67f74-2665-41a6-ab0a-a1903825dfa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895645859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2895645859
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3398818618
Short name T366
Test name
Test status
Simulation time 510477055 ps
CPU time 5.13 seconds
Started Aug 19 04:25:08 PM PDT 24
Finished Aug 19 04:25:13 PM PDT 24
Peak memory 219508 kb
Host smart-a234d8a2-c2e0-4c6c-9728-71f9e282812b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398818618 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3398818618
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.552399227
Short name T427
Test name
Test status
Simulation time 256383959 ps
CPU time 4.67 seconds
Started Aug 19 04:25:04 PM PDT 24
Finished Aug 19 04:25:09 PM PDT 24
Peak memory 211316 kb
Host smart-d2316584-2dd7-433c-9c3f-5cd2f6436fd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552399227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.552399227
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.828795939
Short name T84
Test name
Test status
Simulation time 787066590 ps
CPU time 29.82 seconds
Started Aug 19 04:25:06 PM PDT 24
Finished Aug 19 04:25:36 PM PDT 24
Peak memory 211272 kb
Host smart-ba8f5800-dd91-4fcd-9282-69a672a63e28
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828795939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.828795939
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2529434876
Short name T382
Test name
Test status
Simulation time 503977791 ps
CPU time 8.8 seconds
Started Aug 19 04:25:05 PM PDT 24
Finished Aug 19 04:25:14 PM PDT 24
Peak memory 219532 kb
Host smart-9314d367-277e-4607-8b5e-8e885d49ecb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529434876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2529434876
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.559669692
Short name T108
Test name
Test status
Simulation time 371472306 ps
CPU time 68.35 seconds
Started Aug 19 04:25:08 PM PDT 24
Finished Aug 19 04:26:16 PM PDT 24
Peak memory 219408 kb
Host smart-83a9bac4-598d-4b4d-aa28-a941b12c45c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559669692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.559669692
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3572218474
Short name T369
Test name
Test status
Simulation time 401247933 ps
CPU time 4.37 seconds
Started Aug 19 04:25:08 PM PDT 24
Finished Aug 19 04:25:13 PM PDT 24
Peak memory 215476 kb
Host smart-ad991cc7-b27b-45ea-a015-9a2250715526
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572218474 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3572218474
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1195614326
Short name T426
Test name
Test status
Simulation time 521626802 ps
CPU time 4.71 seconds
Started Aug 19 04:25:04 PM PDT 24
Finished Aug 19 04:25:09 PM PDT 24
Peak memory 218136 kb
Host smart-0de19c3d-8005-4254-9ec0-097f1e5aa91d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195614326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1195614326
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1277280489
Short name T449
Test name
Test status
Simulation time 807263481 ps
CPU time 30 seconds
Started Aug 19 04:25:04 PM PDT 24
Finished Aug 19 04:25:34 PM PDT 24
Peak memory 211020 kb
Host smart-27701146-26ea-4bf5-9afe-5716bf11aecb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277280489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1277280489
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4182492779
Short name T400
Test name
Test status
Simulation time 518104969 ps
CPU time 4.8 seconds
Started Aug 19 04:25:06 PM PDT 24
Finished Aug 19 04:25:11 PM PDT 24
Peak memory 218824 kb
Host smart-21bfe80a-5de3-4c84-a4c5-a442b46f7ac2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182492779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.4182492779
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1942833305
Short name T396
Test name
Test status
Simulation time 500930194 ps
CPU time 7.14 seconds
Started Aug 19 04:25:06 PM PDT 24
Finished Aug 19 04:25:13 PM PDT 24
Peak memory 219580 kb
Host smart-41f9bebb-214a-43e8-943e-fe35cc3266dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942833305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1942833305
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2785390063
Short name T113
Test name
Test status
Simulation time 2901320422 ps
CPU time 68.35 seconds
Started Aug 19 04:25:06 PM PDT 24
Finished Aug 19 04:26:14 PM PDT 24
Peak memory 213080 kb
Host smart-58592dc2-9fd9-4b50-a5b0-b8e3aa4f89b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785390063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2785390063
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2573700178
Short name T374
Test name
Test status
Simulation time 2087509017 ps
CPU time 7.29 seconds
Started Aug 19 04:25:06 PM PDT 24
Finished Aug 19 04:25:13 PM PDT 24
Peak memory 215752 kb
Host smart-1ca805a1-0146-4216-8152-88a0b9e97b6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573700178 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2573700178
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2117446869
Short name T93
Test name
Test status
Simulation time 175560990 ps
CPU time 3.99 seconds
Started Aug 19 04:25:07 PM PDT 24
Finished Aug 19 04:25:11 PM PDT 24
Peak memory 211324 kb
Host smart-5c5ece5b-a90f-4e91-95c6-00ad81d2f759
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117446869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2117446869
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4006712951
Short name T64
Test name
Test status
Simulation time 1018340964 ps
CPU time 26.28 seconds
Started Aug 19 04:25:08 PM PDT 24
Finished Aug 19 04:25:35 PM PDT 24
Peak memory 211316 kb
Host smart-ae76831f-d887-49c5-9e2b-6a5cbdee0192
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006712951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.4006712951
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.873979263
Short name T431
Test name
Test status
Simulation time 97381143 ps
CPU time 5.69 seconds
Started Aug 19 04:25:11 PM PDT 24
Finished Aug 19 04:25:16 PM PDT 24
Peak memory 219436 kb
Host smart-2788dcfb-4aa9-48ab-af8f-b6886ae12980
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873979263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.873979263
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4230105464
Short name T439
Test name
Test status
Simulation time 440453163 ps
CPU time 6.91 seconds
Started Aug 19 04:25:04 PM PDT 24
Finished Aug 19 04:25:11 PM PDT 24
Peak memory 219512 kb
Host smart-8128b103-aabd-4d44-a505-0b7a2a074ae1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230105464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.4230105464
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1908292123
Short name T104
Test name
Test status
Simulation time 2197610087 ps
CPU time 74.06 seconds
Started Aug 19 04:25:07 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 214260 kb
Host smart-5569ac93-0208-4bdd-9eba-5e13c44f73a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908292123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1908292123
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3999363406
Short name T380
Test name
Test status
Simulation time 555412576 ps
CPU time 6.27 seconds
Started Aug 19 04:25:11 PM PDT 24
Finished Aug 19 04:25:17 PM PDT 24
Peak memory 219552 kb
Host smart-42b5163d-77a5-4e78-9086-ecd66e94a119
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999363406 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3999363406
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2372564847
Short name T372
Test name
Test status
Simulation time 2473894453 ps
CPU time 4.89 seconds
Started Aug 19 04:25:06 PM PDT 24
Finished Aug 19 04:25:11 PM PDT 24
Peak memory 218720 kb
Host smart-dcfec9b5-a9e2-4d83-8cd2-03b428a8fd7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372564847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2372564847
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.999678552
Short name T79
Test name
Test status
Simulation time 834993488 ps
CPU time 30.35 seconds
Started Aug 19 04:25:12 PM PDT 24
Finished Aug 19 04:25:42 PM PDT 24
Peak memory 211372 kb
Host smart-78137899-7a82-4885-9296-88f78a88a49f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999678552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.999678552
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3798846971
Short name T92
Test name
Test status
Simulation time 549917094 ps
CPU time 6.61 seconds
Started Aug 19 04:25:05 PM PDT 24
Finished Aug 19 04:25:12 PM PDT 24
Peak memory 211392 kb
Host smart-8f30514d-7143-4e14-8952-50ebc583483c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798846971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3798846971
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3459328295
Short name T418
Test name
Test status
Simulation time 1184123136 ps
CPU time 7.49 seconds
Started Aug 19 04:25:06 PM PDT 24
Finished Aug 19 04:25:13 PM PDT 24
Peak memory 219580 kb
Host smart-71219e5e-fd9b-413a-a153-5eb1d0ce265d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459328295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3459328295
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1485084874
Short name T361
Test name
Test status
Simulation time 398357468 ps
CPU time 4.77 seconds
Started Aug 19 04:25:04 PM PDT 24
Finished Aug 19 04:25:09 PM PDT 24
Peak memory 215904 kb
Host smart-2a7607d5-e3fa-433b-a1d7-baeae2445df6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485084874 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1485084874
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2217741882
Short name T97
Test name
Test status
Simulation time 127000823 ps
CPU time 4.68 seconds
Started Aug 19 04:25:05 PM PDT 24
Finished Aug 19 04:25:10 PM PDT 24
Peak memory 211184 kb
Host smart-d02c6eeb-04f5-4dc1-b416-7b1a06716dc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217741882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2217741882
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1540050475
Short name T96
Test name
Test status
Simulation time 2402542844 ps
CPU time 21.17 seconds
Started Aug 19 04:25:04 PM PDT 24
Finished Aug 19 04:25:26 PM PDT 24
Peak memory 211448 kb
Host smart-4230886f-a3ee-41af-9f63-bfb078a84441
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540050475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1540050475
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2982462525
Short name T390
Test name
Test status
Simulation time 161954443 ps
CPU time 4.12 seconds
Started Aug 19 04:25:07 PM PDT 24
Finished Aug 19 04:25:12 PM PDT 24
Peak memory 218592 kb
Host smart-048c2b58-ebb0-4707-a30d-68dab979cbeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982462525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2982462525
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.299263291
Short name T428
Test name
Test status
Simulation time 256435562 ps
CPU time 8.07 seconds
Started Aug 19 04:25:06 PM PDT 24
Finished Aug 19 04:25:15 PM PDT 24
Peak memory 219556 kb
Host smart-d45cbb26-42bd-4f17-bb4d-10e8c22f7857
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299263291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.299263291
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1270398875
Short name T107
Test name
Test status
Simulation time 246695848 ps
CPU time 68.56 seconds
Started Aug 19 04:25:07 PM PDT 24
Finished Aug 19 04:26:16 PM PDT 24
Peak memory 212940 kb
Host smart-fbe5634c-b04a-488c-90be-8abd9deb2285
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270398875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1270398875
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.287535436
Short name T365
Test name
Test status
Simulation time 143001370 ps
CPU time 5.22 seconds
Started Aug 19 04:25:12 PM PDT 24
Finished Aug 19 04:25:17 PM PDT 24
Peak memory 215688 kb
Host smart-bd41bcad-910c-447c-b080-44eb73335720
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287535436 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.287535436
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2132577980
Short name T438
Test name
Test status
Simulation time 250457987 ps
CPU time 4.82 seconds
Started Aug 19 04:25:08 PM PDT 24
Finished Aug 19 04:25:13 PM PDT 24
Peak memory 211312 kb
Host smart-534edc8b-7d9f-40c7-80c1-f8a1a225642f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132577980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2132577980
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2002290525
Short name T81
Test name
Test status
Simulation time 1111807855 ps
CPU time 26.1 seconds
Started Aug 19 04:25:09 PM PDT 24
Finished Aug 19 04:25:35 PM PDT 24
Peak memory 211324 kb
Host smart-f3c5d061-43be-4359-b994-870b57d67abc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002290525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2002290525
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2948316964
Short name T419
Test name
Test status
Simulation time 498256544 ps
CPU time 4.77 seconds
Started Aug 19 04:25:05 PM PDT 24
Finished Aug 19 04:25:10 PM PDT 24
Peak memory 218476 kb
Host smart-40675a9f-c9b9-4bc8-a82a-62152a55887a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948316964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2948316964
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.104529465
Short name T362
Test name
Test status
Simulation time 128358719 ps
CPU time 8.1 seconds
Started Aug 19 04:25:13 PM PDT 24
Finished Aug 19 04:25:22 PM PDT 24
Peak memory 218520 kb
Host smart-01b88947-31dd-4809-b128-985da87e7c94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104529465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.104529465
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1714587128
Short name T101
Test name
Test status
Simulation time 222880027 ps
CPU time 36.9 seconds
Started Aug 19 04:25:13 PM PDT 24
Finished Aug 19 04:25:50 PM PDT 24
Peak memory 218332 kb
Host smart-054881a1-cff5-464a-af07-42202ff1d0fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714587128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1714587128
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.463867061
Short name T405
Test name
Test status
Simulation time 140619898 ps
CPU time 5.68 seconds
Started Aug 19 04:25:16 PM PDT 24
Finished Aug 19 04:25:22 PM PDT 24
Peak memory 219576 kb
Host smart-2e26ed41-ca12-4b45-8fd3-927794ef7376
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463867061 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.463867061
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1283931615
Short name T90
Test name
Test status
Simulation time 2075821066 ps
CPU time 4.66 seconds
Started Aug 19 04:25:12 PM PDT 24
Finished Aug 19 04:25:17 PM PDT 24
Peak memory 218228 kb
Host smart-c9729e90-0886-46ba-a4b6-4d149ce4fb8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283931615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1283931615
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1162310410
Short name T82
Test name
Test status
Simulation time 789493945 ps
CPU time 30.88 seconds
Started Aug 19 04:25:06 PM PDT 24
Finished Aug 19 04:25:37 PM PDT 24
Peak memory 211348 kb
Host smart-f7050784-bfbf-4323-be87-df7110fe8c4c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162310410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1162310410
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3544486066
Short name T435
Test name
Test status
Simulation time 262511696 ps
CPU time 5.05 seconds
Started Aug 19 04:26:00 PM PDT 24
Finished Aug 19 04:26:05 PM PDT 24
Peak memory 211288 kb
Host smart-96282814-352a-4fff-8520-37df647e6445
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544486066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3544486066
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.569480963
Short name T408
Test name
Test status
Simulation time 254243738 ps
CPU time 7.85 seconds
Started Aug 19 04:25:08 PM PDT 24
Finished Aug 19 04:25:16 PM PDT 24
Peak memory 219568 kb
Host smart-d6788d15-b85f-4ea0-86c5-22b803ac1632
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569480963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.569480963
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.465065666
Short name T440
Test name
Test status
Simulation time 417669604 ps
CPU time 4.44 seconds
Started Aug 19 04:25:18 PM PDT 24
Finished Aug 19 04:25:22 PM PDT 24
Peak memory 219552 kb
Host smart-fe14c206-0169-4219-ab94-9cc30e6137bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465065666 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.465065666
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.681732307
Short name T86
Test name
Test status
Simulation time 350500671 ps
CPU time 3.88 seconds
Started Aug 19 04:25:20 PM PDT 24
Finished Aug 19 04:25:24 PM PDT 24
Peak memory 211320 kb
Host smart-0e9ed450-5771-4e29-9aed-271cb7225c4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681732307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.681732307
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.743911216
Short name T453
Test name
Test status
Simulation time 95428760 ps
CPU time 6.02 seconds
Started Aug 19 04:25:16 PM PDT 24
Finished Aug 19 04:25:22 PM PDT 24
Peak memory 211544 kb
Host smart-44e28212-952b-46b6-861b-5a7254a20945
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743911216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.743911216
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1018369855
Short name T406
Test name
Test status
Simulation time 250581504 ps
CPU time 6.79 seconds
Started Aug 19 04:25:18 PM PDT 24
Finished Aug 19 04:25:26 PM PDT 24
Peak memory 219576 kb
Host smart-165f5b79-67a0-4859-bc34-6f66f88cef7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018369855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1018369855
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1317955204
Short name T404
Test name
Test status
Simulation time 150322922 ps
CPU time 35.4 seconds
Started Aug 19 04:25:19 PM PDT 24
Finished Aug 19 04:25:55 PM PDT 24
Peak memory 213824 kb
Host smart-e818021a-9c33-43e7-8c67-c5fb1591f418
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317955204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1317955204
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1158595208
Short name T377
Test name
Test status
Simulation time 551495324 ps
CPU time 5.53 seconds
Started Aug 19 04:25:18 PM PDT 24
Finished Aug 19 04:25:24 PM PDT 24
Peak memory 216580 kb
Host smart-487fa764-aca1-45a8-9a5c-509e212add87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158595208 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1158595208
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3928217884
Short name T56
Test name
Test status
Simulation time 529883350 ps
CPU time 21.25 seconds
Started Aug 19 04:25:18 PM PDT 24
Finished Aug 19 04:25:40 PM PDT 24
Peak memory 211332 kb
Host smart-e7080fc1-791d-450f-bc50-a966d0d3160c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928217884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3928217884
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2246901891
Short name T424
Test name
Test status
Simulation time 126929453 ps
CPU time 4.92 seconds
Started Aug 19 04:25:15 PM PDT 24
Finished Aug 19 04:25:20 PM PDT 24
Peak memory 211272 kb
Host smart-69d88997-e15a-4536-9ba6-8df3391fa632
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246901891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2246901891
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2176731643
Short name T411
Test name
Test status
Simulation time 194409086 ps
CPU time 9.68 seconds
Started Aug 19 04:25:17 PM PDT 24
Finished Aug 19 04:25:27 PM PDT 24
Peak memory 216308 kb
Host smart-0c41a855-64a2-4785-8bdf-13202c36da01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176731643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2176731643
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4149372088
Short name T52
Test name
Test status
Simulation time 2607273867 ps
CPU time 37.42 seconds
Started Aug 19 04:25:14 PM PDT 24
Finished Aug 19 04:25:52 PM PDT 24
Peak memory 219524 kb
Host smart-4bf40a16-4a82-4bfb-8eb3-b1cdbe4a536a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149372088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.4149372088
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2802613031
Short name T85
Test name
Test status
Simulation time 502011154 ps
CPU time 4.81 seconds
Started Aug 19 04:24:58 PM PDT 24
Finished Aug 19 04:25:03 PM PDT 24
Peak memory 217512 kb
Host smart-cd869d7d-2cdd-40be-941f-ba6c65cc58f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802613031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2802613031
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.208457775
Short name T373
Test name
Test status
Simulation time 130319062 ps
CPU time 4.94 seconds
Started Aug 19 04:24:56 PM PDT 24
Finished Aug 19 04:25:01 PM PDT 24
Peak memory 211276 kb
Host smart-6c2e1687-ca6d-4955-b603-0f9fcd8439ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208457775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.208457775
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1206133362
Short name T429
Test name
Test status
Simulation time 1249988861 ps
CPU time 7.27 seconds
Started Aug 19 04:24:59 PM PDT 24
Finished Aug 19 04:25:07 PM PDT 24
Peak memory 211312 kb
Host smart-a66f7165-af39-4a0e-8f19-52ed2fbd767c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206133362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1206133362
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3695476352
Short name T368
Test name
Test status
Simulation time 111847670 ps
CPU time 4.74 seconds
Started Aug 19 04:24:55 PM PDT 24
Finished Aug 19 04:24:59 PM PDT 24
Peak memory 215596 kb
Host smart-8bab6878-9618-4364-963a-a203180b9d07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695476352 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3695476352
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3320694427
Short name T386
Test name
Test status
Simulation time 172876837 ps
CPU time 3.74 seconds
Started Aug 19 04:25:09 PM PDT 24
Finished Aug 19 04:25:13 PM PDT 24
Peak memory 211320 kb
Host smart-a42e6583-756c-4998-a121-6e97faf8b805
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320694427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3320694427
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2479711264
Short name T401
Test name
Test status
Simulation time 146621609 ps
CPU time 4.53 seconds
Started Aug 19 04:25:10 PM PDT 24
Finished Aug 19 04:25:15 PM PDT 24
Peak memory 211200 kb
Host smart-440776a8-24d4-4848-8e13-d3b94c776e80
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479711264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2479711264
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.501440523
Short name T387
Test name
Test status
Simulation time 505172462 ps
CPU time 6.76 seconds
Started Aug 19 04:24:56 PM PDT 24
Finished Aug 19 04:25:03 PM PDT 24
Peak memory 211196 kb
Host smart-8d9501a0-3bb5-4d5e-a4bc-41feea9d58b5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501440523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
501440523
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3474975122
Short name T388
Test name
Test status
Simulation time 827524887 ps
CPU time 31.04 seconds
Started Aug 19 04:25:03 PM PDT 24
Finished Aug 19 04:25:34 PM PDT 24
Peak memory 211328 kb
Host smart-a722a5cc-0d1a-4c8d-b061-7fd26c2f31cc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474975122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3474975122
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2018027580
Short name T446
Test name
Test status
Simulation time 89972986 ps
CPU time 4.22 seconds
Started Aug 19 04:24:56 PM PDT 24
Finished Aug 19 04:25:00 PM PDT 24
Peak memory 211188 kb
Host smart-5422f13d-6113-4afb-8631-757766028d9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018027580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2018027580
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2059094753
Short name T407
Test name
Test status
Simulation time 1231340267 ps
CPU time 6.58 seconds
Started Aug 19 04:24:57 PM PDT 24
Finished Aug 19 04:25:04 PM PDT 24
Peak memory 219588 kb
Host smart-e4c5f101-ea32-4496-8c1e-afc1f4cc045c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059094753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2059094753
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4119634800
Short name T103
Test name
Test status
Simulation time 914247732 ps
CPU time 69.6 seconds
Started Aug 19 04:24:56 PM PDT 24
Finished Aug 19 04:26:05 PM PDT 24
Peak memory 214044 kb
Host smart-cb93de82-6ada-4cee-84c9-93b2ead03d79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119634800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.4119634800
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4108406979
Short name T88
Test name
Test status
Simulation time 337023854 ps
CPU time 3.85 seconds
Started Aug 19 04:24:55 PM PDT 24
Finished Aug 19 04:24:59 PM PDT 24
Peak memory 219328 kb
Host smart-22a8db2c-3611-416c-95e0-c5a88633621a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108406979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.4108406979
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.936596945
Short name T94
Test name
Test status
Simulation time 132950700 ps
CPU time 4.71 seconds
Started Aug 19 04:25:10 PM PDT 24
Finished Aug 19 04:25:15 PM PDT 24
Peak memory 218196 kb
Host smart-dc9a41fd-ba74-4a89-828d-90f972172b10
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936596945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.936596945
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1747321729
Short name T379
Test name
Test status
Simulation time 91436508 ps
CPU time 5.56 seconds
Started Aug 19 04:25:04 PM PDT 24
Finished Aug 19 04:25:09 PM PDT 24
Peak memory 211300 kb
Host smart-15aa3bc9-e5f8-4b5a-a905-894840aa4ce8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747321729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1747321729
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4093865485
Short name T375
Test name
Test status
Simulation time 93459404 ps
CPU time 4.36 seconds
Started Aug 19 04:25:03 PM PDT 24
Finished Aug 19 04:25:07 PM PDT 24
Peak memory 213620 kb
Host smart-ee1b1b66-8c3d-4fd2-a711-a273e9364c4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093865485 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.4093865485
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2057744531
Short name T450
Test name
Test status
Simulation time 89990243 ps
CPU time 4.14 seconds
Started Aug 19 04:24:58 PM PDT 24
Finished Aug 19 04:25:03 PM PDT 24
Peak memory 211288 kb
Host smart-bf7131e7-f73b-4054-a9af-2d7cfe686949
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057744531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2057744531
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3899816789
Short name T423
Test name
Test status
Simulation time 88256284 ps
CPU time 3.83 seconds
Started Aug 19 04:25:06 PM PDT 24
Finished Aug 19 04:25:10 PM PDT 24
Peak memory 211208 kb
Host smart-171f60c1-88a9-400a-ade8-5c47bac72b3a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899816789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3899816789
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3756962491
Short name T385
Test name
Test status
Simulation time 128423273 ps
CPU time 4.76 seconds
Started Aug 19 04:24:56 PM PDT 24
Finished Aug 19 04:25:01 PM PDT 24
Peak memory 211112 kb
Host smart-b6c4d4c4-e1f6-4c08-970f-e2e8651c2488
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756962491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3756962491
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.893258080
Short name T69
Test name
Test status
Simulation time 4387046082 ps
CPU time 21.04 seconds
Started Aug 19 04:24:53 PM PDT 24
Finished Aug 19 04:25:14 PM PDT 24
Peak memory 211400 kb
Host smart-e80d96dc-60b5-4333-9151-e4c66d7c7501
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893258080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.893258080
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2292738261
Short name T422
Test name
Test status
Simulation time 625371633 ps
CPU time 4.88 seconds
Started Aug 19 04:24:55 PM PDT 24
Finished Aug 19 04:25:00 PM PDT 24
Peak memory 211256 kb
Host smart-da9364af-ab75-48c5-8213-9a1cbf58095c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292738261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2292738261
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3286406636
Short name T416
Test name
Test status
Simulation time 86466430 ps
CPU time 6.89 seconds
Started Aug 19 04:25:02 PM PDT 24
Finished Aug 19 04:25:09 PM PDT 24
Peak memory 215296 kb
Host smart-e9b850af-89b8-40da-970d-4e41d05589f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286406636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3286406636
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3188570206
Short name T106
Test name
Test status
Simulation time 273642107 ps
CPU time 68.25 seconds
Started Aug 19 04:25:04 PM PDT 24
Finished Aug 19 04:26:13 PM PDT 24
Peak memory 219452 kb
Host smart-d37d3378-4f49-4d90-a94b-60dc340c750a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188570206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3188570206
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4092837824
Short name T376
Test name
Test status
Simulation time 132600249 ps
CPU time 4.75 seconds
Started Aug 19 04:25:05 PM PDT 24
Finished Aug 19 04:25:10 PM PDT 24
Peak memory 211312 kb
Host smart-c31808dd-45df-43b1-afb2-a02c18b7832e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092837824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.4092837824
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1606975862
Short name T437
Test name
Test status
Simulation time 150710745 ps
CPU time 4.15 seconds
Started Aug 19 04:25:09 PM PDT 24
Finished Aug 19 04:25:14 PM PDT 24
Peak memory 219440 kb
Host smart-bcdabb8c-dcf3-4124-9736-8620b48d9c98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606975862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1606975862
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.697038262
Short name T420
Test name
Test status
Simulation time 503513217 ps
CPU time 7.73 seconds
Started Aug 19 04:24:55 PM PDT 24
Finished Aug 19 04:25:03 PM PDT 24
Peak memory 211284 kb
Host smart-b45be161-22f6-4395-a93b-c5ce3700370b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697038262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.697038262
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3121859017
Short name T417
Test name
Test status
Simulation time 94687078 ps
CPU time 4.87 seconds
Started Aug 19 04:24:56 PM PDT 24
Finished Aug 19 04:25:01 PM PDT 24
Peak memory 219440 kb
Host smart-08573e5e-5db2-48c6-87d9-b52df8c285d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121859017 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3121859017
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.995050886
Short name T443
Test name
Test status
Simulation time 321038450 ps
CPU time 4.04 seconds
Started Aug 19 04:25:02 PM PDT 24
Finished Aug 19 04:25:06 PM PDT 24
Peak memory 219416 kb
Host smart-7db2b701-267d-4bae-922b-3d0d9925ee29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995050886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.995050886
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2498374313
Short name T359
Test name
Test status
Simulation time 2481559324 ps
CPU time 4.79 seconds
Started Aug 19 04:24:56 PM PDT 24
Finished Aug 19 04:25:01 PM PDT 24
Peak memory 211324 kb
Host smart-3625a300-dfaf-4a75-9458-43d0c53bc1af
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498374313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2498374313
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1788298250
Short name T448
Test name
Test status
Simulation time 127347503 ps
CPU time 4.6 seconds
Started Aug 19 04:25:10 PM PDT 24
Finished Aug 19 04:25:15 PM PDT 24
Peak memory 211236 kb
Host smart-9e282bdb-7f48-4758-95f5-6affd09e5712
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788298250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1788298250
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.981192369
Short name T80
Test name
Test status
Simulation time 9879716895 ps
CPU time 30.75 seconds
Started Aug 19 04:25:04 PM PDT 24
Finished Aug 19 04:25:35 PM PDT 24
Peak memory 211252 kb
Host smart-92b67589-7a7f-4d22-b984-2aae431a92a8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981192369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.981192369
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.947934577
Short name T413
Test name
Test status
Simulation time 361981161 ps
CPU time 3.96 seconds
Started Aug 19 04:25:10 PM PDT 24
Finished Aug 19 04:25:14 PM PDT 24
Peak memory 218272 kb
Host smart-6668f667-358f-4524-a870-3c19ec978378
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947934577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.947934577
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3315041007
Short name T454
Test name
Test status
Simulation time 89337585 ps
CPU time 6.52 seconds
Started Aug 19 04:25:00 PM PDT 24
Finished Aug 19 04:25:07 PM PDT 24
Peak memory 217368 kb
Host smart-c22bcc45-318d-46bd-a292-4e53cde15b14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315041007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3315041007
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3278569636
Short name T393
Test name
Test status
Simulation time 1355581840 ps
CPU time 36.19 seconds
Started Aug 19 04:25:09 PM PDT 24
Finished Aug 19 04:25:46 PM PDT 24
Peak memory 219432 kb
Host smart-c4c30706-c047-4a65-b1ee-ce0bf2f6a502
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278569636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3278569636
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3158730980
Short name T430
Test name
Test status
Simulation time 95649165 ps
CPU time 4.44 seconds
Started Aug 19 04:25:11 PM PDT 24
Finished Aug 19 04:25:16 PM PDT 24
Peak memory 219520 kb
Host smart-de398cd8-6faa-480b-8a37-360512a13fa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158730980 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3158730980
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1314720853
Short name T370
Test name
Test status
Simulation time 172418916 ps
CPU time 3.95 seconds
Started Aug 19 04:24:57 PM PDT 24
Finished Aug 19 04:25:01 PM PDT 24
Peak memory 211340 kb
Host smart-1c2b2b02-2d9f-46a4-a7f3-37fa6ee93b0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314720853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1314720853
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1648078626
Short name T78
Test name
Test status
Simulation time 805089945 ps
CPU time 29.72 seconds
Started Aug 19 04:25:09 PM PDT 24
Finished Aug 19 04:25:39 PM PDT 24
Peak memory 211324 kb
Host smart-84240ba0-2c61-49f3-9ffb-9ff3c0db4fac
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648078626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1648078626
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.944163443
Short name T66
Test name
Test status
Simulation time 498816805 ps
CPU time 6.54 seconds
Started Aug 19 04:25:06 PM PDT 24
Finished Aug 19 04:25:12 PM PDT 24
Peak memory 218840 kb
Host smart-fdfba6a4-c4ff-43f2-ab17-1b73b8617ca0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944163443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.944163443
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1502891849
Short name T421
Test name
Test status
Simulation time 351898148 ps
CPU time 6.51 seconds
Started Aug 19 04:24:58 PM PDT 24
Finished Aug 19 04:25:04 PM PDT 24
Peak memory 219304 kb
Host smart-83f2d9fa-ae4b-4c84-b3bc-661153df5c45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502891849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1502891849
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3263785328
Short name T114
Test name
Test status
Simulation time 357111555 ps
CPU time 40.02 seconds
Started Aug 19 04:25:03 PM PDT 24
Finished Aug 19 04:25:43 PM PDT 24
Peak memory 212996 kb
Host smart-aa58b39d-b25b-46f1-9dbf-57bea2f3e881
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263785328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3263785328
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2787979875
Short name T391
Test name
Test status
Simulation time 362770250 ps
CPU time 4.15 seconds
Started Aug 19 04:25:09 PM PDT 24
Finished Aug 19 04:25:13 PM PDT 24
Peak memory 215772 kb
Host smart-2b9a0516-b580-4d54-90de-9b6281096cb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787979875 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2787979875
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.790961665
Short name T62
Test name
Test status
Simulation time 99935493 ps
CPU time 4.12 seconds
Started Aug 19 04:25:03 PM PDT 24
Finished Aug 19 04:25:08 PM PDT 24
Peak memory 211276 kb
Host smart-8f836449-fd33-4c5d-a66d-36a6b02bc74d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790961665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.790961665
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.283954201
Short name T447
Test name
Test status
Simulation time 816625024 ps
CPU time 31.04 seconds
Started Aug 19 04:25:01 PM PDT 24
Finished Aug 19 04:25:32 PM PDT 24
Peak memory 211316 kb
Host smart-ffaacda3-1ddf-4d6b-a40d-401caceb166f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283954201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.283954201
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.508961073
Short name T425
Test name
Test status
Simulation time 133406354 ps
CPU time 4.71 seconds
Started Aug 19 04:25:11 PM PDT 24
Finished Aug 19 04:25:16 PM PDT 24
Peak memory 211336 kb
Host smart-e4af8f6d-685c-4650-bb0e-ba7766e9657a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508961073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.508961073
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3450271588
Short name T371
Test name
Test status
Simulation time 170012591 ps
CPU time 10.1 seconds
Started Aug 19 04:25:00 PM PDT 24
Finished Aug 19 04:25:10 PM PDT 24
Peak memory 215428 kb
Host smart-02e58f59-2d32-4c80-97e8-973cbb87a1ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450271588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3450271588
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.645784702
Short name T110
Test name
Test status
Simulation time 628706959 ps
CPU time 69.51 seconds
Started Aug 19 04:24:56 PM PDT 24
Finished Aug 19 04:26:05 PM PDT 24
Peak memory 219348 kb
Host smart-96018b19-cd42-4abd-8770-1bc505fe6875
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645784702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.645784702
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.816557308
Short name T452
Test name
Test status
Simulation time 431408379 ps
CPU time 5.26 seconds
Started Aug 19 04:24:57 PM PDT 24
Finished Aug 19 04:25:02 PM PDT 24
Peak memory 216828 kb
Host smart-ebe2bd36-12e1-416c-8fb8-3ab7c6616c48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816557308 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.816557308
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1199592151
Short name T367
Test name
Test status
Simulation time 133266852 ps
CPU time 4.63 seconds
Started Aug 19 04:25:09 PM PDT 24
Finished Aug 19 04:25:14 PM PDT 24
Peak memory 211304 kb
Host smart-fde7926d-3a9c-4d88-a3c9-178b681a794a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199592151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1199592151
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.833271687
Short name T381
Test name
Test status
Simulation time 537812934 ps
CPU time 25.09 seconds
Started Aug 19 04:25:09 PM PDT 24
Finished Aug 19 04:25:34 PM PDT 24
Peak memory 211340 kb
Host smart-5b2001f8-2a7e-44b9-8801-ec62529d94a9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833271687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.833271687
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3924340267
Short name T392
Test name
Test status
Simulation time 501022647 ps
CPU time 4.8 seconds
Started Aug 19 04:25:10 PM PDT 24
Finished Aug 19 04:25:15 PM PDT 24
Peak memory 218952 kb
Host smart-bd72a440-66b4-4d49-aa02-4913929a5b05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924340267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3924340267
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3214852741
Short name T389
Test name
Test status
Simulation time 124805824 ps
CPU time 7.9 seconds
Started Aug 19 04:25:09 PM PDT 24
Finished Aug 19 04:25:17 PM PDT 24
Peak memory 215328 kb
Host smart-d5e65369-0b58-4168-8090-72dfc96fcb40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214852741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3214852741
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4026933206
Short name T399
Test name
Test status
Simulation time 560413653 ps
CPU time 5.31 seconds
Started Aug 19 04:25:03 PM PDT 24
Finished Aug 19 04:25:08 PM PDT 24
Peak memory 219480 kb
Host smart-5d4ad23b-d2c6-472d-a67f-531f28a9f7ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026933206 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4026933206
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4023019194
Short name T410
Test name
Test status
Simulation time 260428400 ps
CPU time 4.49 seconds
Started Aug 19 04:25:10 PM PDT 24
Finished Aug 19 04:25:15 PM PDT 24
Peak memory 211320 kb
Host smart-e8551ff0-189a-4d6b-976e-b26b7223adf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023019194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4023019194
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2831009905
Short name T68
Test name
Test status
Simulation time 373710351 ps
CPU time 18.16 seconds
Started Aug 19 04:25:03 PM PDT 24
Finished Aug 19 04:25:21 PM PDT 24
Peak memory 211328 kb
Host smart-4df51eed-dfd7-4184-8946-ac7bc6532b7f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831009905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2831009905
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3162180467
Short name T65
Test name
Test status
Simulation time 143988911 ps
CPU time 6.48 seconds
Started Aug 19 04:25:08 PM PDT 24
Finished Aug 19 04:25:15 PM PDT 24
Peak memory 211368 kb
Host smart-beb55659-9ab5-405d-b620-744650b14b6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162180467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3162180467
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1900018600
Short name T444
Test name
Test status
Simulation time 149816775 ps
CPU time 6.45 seconds
Started Aug 19 04:25:04 PM PDT 24
Finished Aug 19 04:25:11 PM PDT 24
Peak memory 219516 kb
Host smart-04c2926e-b9ac-4270-8b24-1917a445b980
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900018600 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1900018600
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3479953663
Short name T83
Test name
Test status
Simulation time 348015880 ps
CPU time 4.14 seconds
Started Aug 19 04:25:04 PM PDT 24
Finished Aug 19 04:25:08 PM PDT 24
Peak memory 218568 kb
Host smart-c773c14b-7034-435b-b587-a89c579a7de8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479953663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3479953663
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1160789593
Short name T451
Test name
Test status
Simulation time 2194001745 ps
CPU time 19.49 seconds
Started Aug 19 04:25:09 PM PDT 24
Finished Aug 19 04:25:28 PM PDT 24
Peak memory 211408 kb
Host smart-07c174e7-f9e0-46fc-8926-d85f6283f5e5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160789593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1160789593
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3726156226
Short name T91
Test name
Test status
Simulation time 133238045 ps
CPU time 5.1 seconds
Started Aug 19 04:25:06 PM PDT 24
Finished Aug 19 04:25:12 PM PDT 24
Peak memory 211308 kb
Host smart-fcdd422e-ad1b-4f00-887f-d20a1b2303b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726156226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3726156226
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.824192165
Short name T394
Test name
Test status
Simulation time 88883394 ps
CPU time 6.96 seconds
Started Aug 19 04:25:04 PM PDT 24
Finished Aug 19 04:25:11 PM PDT 24
Peak memory 219660 kb
Host smart-3365af0f-ac94-40bb-9448-d5d9b5446b32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824192165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.824192165
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4156514825
Short name T111
Test name
Test status
Simulation time 974380384 ps
CPU time 68.54 seconds
Started Aug 19 04:25:08 PM PDT 24
Finished Aug 19 04:26:17 PM PDT 24
Peak memory 213036 kb
Host smart-37b65f63-67e5-42b0-b43f-00a1bad3e662
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156514825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.4156514825
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3598003665
Short name T177
Test name
Test status
Simulation time 144988375 ps
CPU time 4.01 seconds
Started Aug 19 04:26:29 PM PDT 24
Finished Aug 19 04:26:33 PM PDT 24
Peak memory 210984 kb
Host smart-18b1a37b-3238-4c5e-bd90-188c40493916
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598003665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3598003665
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3503698564
Short name T172
Test name
Test status
Simulation time 17169155729 ps
CPU time 120.28 seconds
Started Aug 19 04:26:22 PM PDT 24
Finished Aug 19 04:28:23 PM PDT 24
Peak memory 232412 kb
Host smart-b4c807d2-6228-48c2-96da-223c40c4a62c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503698564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3503698564
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4115655256
Short name T188
Test name
Test status
Simulation time 277102502 ps
CPU time 10.6 seconds
Started Aug 19 04:26:13 PM PDT 24
Finished Aug 19 04:26:24 PM PDT 24
Peak memory 211016 kb
Host smart-c1dde56d-0048-4d68-8d9e-b3f310bbb5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115655256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.4115655256
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3152325317
Short name T29
Test name
Test status
Simulation time 301857256 ps
CPU time 54.19 seconds
Started Aug 19 04:26:22 PM PDT 24
Finished Aug 19 04:27:17 PM PDT 24
Peak memory 235964 kb
Host smart-dc40ef80-9140-43f2-9416-cb42ba604c44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152325317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3152325317
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.797507151
Short name T209
Test name
Test status
Simulation time 97147008 ps
CPU time 5.34 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:25 PM PDT 24
Peak memory 212216 kb
Host smart-9326aa70-b6cf-4c9e-89cb-5e8dc6a4549b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797507151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.797507151
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.388968941
Short name T264
Test name
Test status
Simulation time 324251181 ps
CPU time 8.41 seconds
Started Aug 19 04:26:23 PM PDT 24
Finished Aug 19 04:26:32 PM PDT 24
Peak memory 212748 kb
Host smart-2b1cc9e1-f0f2-40db-9491-37d319c5f11d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388968941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.388968941
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1966883111
Short name T338
Test name
Test status
Simulation time 255594742 ps
CPU time 4.92 seconds
Started Aug 19 04:26:50 PM PDT 24
Finished Aug 19 04:26:55 PM PDT 24
Peak memory 211076 kb
Host smart-db9d7847-a734-4dac-8172-53d54b91c24f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966883111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1966883111
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1664067107
Short name T30
Test name
Test status
Simulation time 7174929005 ps
CPU time 93.48 seconds
Started Aug 19 04:26:54 PM PDT 24
Finished Aug 19 04:28:27 PM PDT 24
Peak memory 236564 kb
Host smart-bbce1f0d-5a8e-4876-be44-5212eb42b457
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664067107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1664067107
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.4088907339
Short name T323
Test name
Test status
Simulation time 693254970 ps
CPU time 8.95 seconds
Started Aug 19 04:26:49 PM PDT 24
Finished Aug 19 04:26:58 PM PDT 24
Peak memory 211380 kb
Host smart-c05134ad-7604-4ba6-8ddb-10dbf6297c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088907339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.4088907339
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3599718279
Short name T170
Test name
Test status
Simulation time 95360127 ps
CPU time 5.3 seconds
Started Aug 19 04:26:32 PM PDT 24
Finished Aug 19 04:26:37 PM PDT 24
Peak memory 211016 kb
Host smart-b1f63341-9115-4a04-b59f-6aaa01077ec7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3599718279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3599718279
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1960700659
Short name T122
Test name
Test status
Simulation time 279483507 ps
CPU time 12.94 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:33 PM PDT 24
Peak memory 213744 kb
Host smart-21972a65-7eeb-4f91-9189-4ab48cfebeb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960700659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1960700659
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.84296505
Short name T47
Test name
Test status
Simulation time 4156917058 ps
CPU time 160.71 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:29:00 PM PDT 24
Peak memory 221692 kb
Host smart-6eea328a-b901-418f-919e-a402d755e5ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84296505 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.84296505
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1705826017
Short name T99
Test name
Test status
Simulation time 565288575 ps
CPU time 4.78 seconds
Started Aug 19 04:26:47 PM PDT 24
Finished Aug 19 04:26:52 PM PDT 24
Peak memory 210992 kb
Host smart-ec5d4dbb-5547-4f32-b35f-dc6a7484ba96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705826017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1705826017
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3054902841
Short name T315
Test name
Test status
Simulation time 9685353681 ps
CPU time 67.35 seconds
Started Aug 19 04:26:50 PM PDT 24
Finished Aug 19 04:28:02 PM PDT 24
Peak memory 237452 kb
Host smart-42c95fc9-c9d5-444b-aa01-84430695f62f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054902841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3054902841
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2130018870
Short name T218
Test name
Test status
Simulation time 1196917281 ps
CPU time 9 seconds
Started Aug 19 04:26:52 PM PDT 24
Finished Aug 19 04:27:01 PM PDT 24
Peak memory 211348 kb
Host smart-6e634231-3271-4aba-80e2-f310d2da9a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130018870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2130018870
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3835228311
Short name T261
Test name
Test status
Simulation time 141873938 ps
CPU time 5.91 seconds
Started Aug 19 04:26:47 PM PDT 24
Finished Aug 19 04:26:53 PM PDT 24
Peak memory 211088 kb
Host smart-2c6be93b-a400-4abb-b670-e1c7ef4b7b75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3835228311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3835228311
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1634625976
Short name T350
Test name
Test status
Simulation time 218581031 ps
CPU time 12.5 seconds
Started Aug 19 04:26:47 PM PDT 24
Finished Aug 19 04:27:00 PM PDT 24
Peak memory 213328 kb
Host smart-b8bf14d4-1d0b-41e7-b77a-1635c1e4104b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634625976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1634625976
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1621695991
Short name T16
Test name
Test status
Simulation time 5083510971 ps
CPU time 158.86 seconds
Started Aug 19 04:26:46 PM PDT 24
Finished Aug 19 04:29:25 PM PDT 24
Peak memory 227380 kb
Host smart-dee0e4bf-0d68-4218-bdb9-54b33ab59928
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621695991 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1621695991
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2153540264
Short name T98
Test name
Test status
Simulation time 570810071 ps
CPU time 4.88 seconds
Started Aug 19 04:26:44 PM PDT 24
Finished Aug 19 04:26:49 PM PDT 24
Peak memory 210880 kb
Host smart-e153ba36-ccf4-4067-8e1f-b3e517988c0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153540264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2153540264
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4191906501
Short name T148
Test name
Test status
Simulation time 13357090851 ps
CPU time 156.9 seconds
Started Aug 19 04:26:58 PM PDT 24
Finished Aug 19 04:29:35 PM PDT 24
Peak memory 213360 kb
Host smart-19887113-c9ae-494c-af95-cf1362c2eab0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191906501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.4191906501
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2540668674
Short name T239
Test name
Test status
Simulation time 383400161 ps
CPU time 5.11 seconds
Started Aug 19 04:26:45 PM PDT 24
Finished Aug 19 04:26:51 PM PDT 24
Peak memory 211008 kb
Host smart-f9875e90-bb19-4404-81e5-e4dfe2971c81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2540668674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2540668674
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1833412784
Short name T344
Test name
Test status
Simulation time 397764266 ps
CPU time 18.5 seconds
Started Aug 19 04:26:30 PM PDT 24
Finished Aug 19 04:26:48 PM PDT 24
Peak memory 214448 kb
Host smart-9c799c30-9e1d-4b33-b082-365b8abd598b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833412784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1833412784
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1852665361
Short name T49
Test name
Test status
Simulation time 2991268731 ps
CPU time 56.73 seconds
Started Aug 19 04:26:33 PM PDT 24
Finished Aug 19 04:27:29 PM PDT 24
Peak memory 220768 kb
Host smart-83486e54-d9c1-463b-a203-7bb1c296e057
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852665361 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.1852665361
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2399546001
Short name T153
Test name
Test status
Simulation time 85801540 ps
CPU time 4.18 seconds
Started Aug 19 04:26:36 PM PDT 24
Finished Aug 19 04:26:40 PM PDT 24
Peak memory 210980 kb
Host smart-1dc5457e-c08a-4433-9671-262548b82225
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399546001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2399546001
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3926253774
Short name T196
Test name
Test status
Simulation time 5428802476 ps
CPU time 134.87 seconds
Started Aug 19 04:26:42 PM PDT 24
Finished Aug 19 04:28:57 PM PDT 24
Peak memory 236836 kb
Host smart-6c18adfa-ca85-4f27-a0ff-40d51d1181fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926253774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3926253774
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2457567905
Short name T304
Test name
Test status
Simulation time 346330828 ps
CPU time 9.36 seconds
Started Aug 19 04:26:48 PM PDT 24
Finished Aug 19 04:26:58 PM PDT 24
Peak memory 211464 kb
Host smart-7099db3e-c7cd-4cbd-b23b-1614008195a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457567905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2457567905
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.400430214
Short name T235
Test name
Test status
Simulation time 340859293 ps
CPU time 6.22 seconds
Started Aug 19 04:26:49 PM PDT 24
Finished Aug 19 04:26:56 PM PDT 24
Peak memory 211004 kb
Host smart-a2f5b834-6f3b-44f3-9f1c-fa34aeb51358
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=400430214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.400430214
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2042170635
Short name T173
Test name
Test status
Simulation time 412616375 ps
CPU time 16.71 seconds
Started Aug 19 04:26:56 PM PDT 24
Finished Aug 19 04:27:13 PM PDT 24
Peak memory 214544 kb
Host smart-4bbdaece-abbf-4bdc-a474-13d3389aae39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042170635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2042170635
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.773558559
Short name T341
Test name
Test status
Simulation time 87274527729 ps
CPU time 263.67 seconds
Started Aug 19 04:26:33 PM PDT 24
Finished Aug 19 04:30:57 PM PDT 24
Peak memory 235552 kb
Host smart-f3e2f159-a743-4663-8866-052b7f2977bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773558559 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.773558559
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2925725152
Short name T162
Test name
Test status
Simulation time 498981126 ps
CPU time 4.69 seconds
Started Aug 19 04:27:05 PM PDT 24
Finished Aug 19 04:27:10 PM PDT 24
Peak memory 210984 kb
Host smart-824aac1d-fd1f-4bf5-8ef1-f3362405a2d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925725152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2925725152
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.520625711
Short name T331
Test name
Test status
Simulation time 2592535947 ps
CPU time 121.45 seconds
Started Aug 19 04:26:39 PM PDT 24
Finished Aug 19 04:28:40 PM PDT 24
Peak memory 233408 kb
Host smart-33c1fa02-59c8-4f47-a7ad-7a05c4bd6784
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520625711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.520625711
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2378459174
Short name T185
Test name
Test status
Simulation time 181128784 ps
CPU time 9.08 seconds
Started Aug 19 04:26:38 PM PDT 24
Finished Aug 19 04:26:47 PM PDT 24
Peak memory 211504 kb
Host smart-7bd8ada3-6978-4000-9559-25f677f32c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378459174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2378459174
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4257584474
Short name T151
Test name
Test status
Simulation time 619553570 ps
CPU time 6.52 seconds
Started Aug 19 04:26:48 PM PDT 24
Finished Aug 19 04:26:54 PM PDT 24
Peak memory 211000 kb
Host smart-4c333d4a-f1de-49c7-9c5e-f38b364d0e74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4257584474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4257584474
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1129540986
Short name T73
Test name
Test status
Simulation time 1179949744 ps
CPU time 8.56 seconds
Started Aug 19 04:27:00 PM PDT 24
Finished Aug 19 04:27:09 PM PDT 24
Peak memory 211040 kb
Host smart-986ca150-07bb-40b9-9cb8-0945cb6e8c30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129540986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1129540986
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.4007926293
Short name T351
Test name
Test status
Simulation time 88336626 ps
CPU time 4.01 seconds
Started Aug 19 04:26:44 PM PDT 24
Finished Aug 19 04:26:48 PM PDT 24
Peak memory 210980 kb
Host smart-9617dfa3-0fb2-4fb3-bfa2-564d975f49b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007926293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.4007926293
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.641217168
Short name T288
Test name
Test status
Simulation time 1275900211 ps
CPU time 75.69 seconds
Started Aug 19 04:26:37 PM PDT 24
Finished Aug 19 04:27:53 PM PDT 24
Peak memory 236184 kb
Host smart-7d628340-5e1f-479f-9cb3-b02b238239d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641217168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.641217168
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.638847310
Short name T42
Test name
Test status
Simulation time 168586171 ps
CPU time 9.01 seconds
Started Aug 19 04:26:34 PM PDT 24
Finished Aug 19 04:26:44 PM PDT 24
Peak memory 211356 kb
Host smart-b4a8da23-1121-40ef-9b59-a4fb95679cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638847310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.638847310
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.200153802
Short name T349
Test name
Test status
Simulation time 385657503 ps
CPU time 5.52 seconds
Started Aug 19 04:26:49 PM PDT 24
Finished Aug 19 04:26:55 PM PDT 24
Peak memory 211016 kb
Host smart-ceb25856-2b56-4fdc-acf1-4c53f29ecb26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=200153802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.200153802
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3871085140
Short name T321
Test name
Test status
Simulation time 387937611 ps
CPU time 8.29 seconds
Started Aug 19 04:26:43 PM PDT 24
Finished Aug 19 04:26:51 PM PDT 24
Peak memory 210896 kb
Host smart-6459d2aa-b3ba-416c-a98a-d8423413abd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871085140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3871085140
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.843957607
Short name T116
Test name
Test status
Simulation time 7295840496 ps
CPU time 134.56 seconds
Started Aug 19 04:26:48 PM PDT 24
Finished Aug 19 04:29:03 PM PDT 24
Peak memory 221968 kb
Host smart-d0c9f808-9c8f-48ad-a473-8cf5287ebba2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843957607 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.843957607
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1997381471
Short name T219
Test name
Test status
Simulation time 565370461 ps
CPU time 4.76 seconds
Started Aug 19 04:26:53 PM PDT 24
Finished Aug 19 04:26:58 PM PDT 24
Peak memory 210984 kb
Host smart-e023f7fe-519e-45fb-b36b-933938ed720b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997381471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1997381471
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1584037071
Short name T180
Test name
Test status
Simulation time 5954273911 ps
CPU time 69.53 seconds
Started Aug 19 04:26:49 PM PDT 24
Finished Aug 19 04:27:59 PM PDT 24
Peak memory 227852 kb
Host smart-e458373e-098f-4b91-9a59-05c6c8c4fc91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584037071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1584037071
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2705455563
Short name T202
Test name
Test status
Simulation time 1134290328 ps
CPU time 10.69 seconds
Started Aug 19 04:26:47 PM PDT 24
Finished Aug 19 04:26:57 PM PDT 24
Peak memory 211384 kb
Host smart-ab7f762d-07eb-46b3-9538-bfcfdeb55eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705455563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2705455563
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2673983742
Short name T216
Test name
Test status
Simulation time 191120567 ps
CPU time 5.6 seconds
Started Aug 19 04:26:29 PM PDT 24
Finished Aug 19 04:26:35 PM PDT 24
Peak memory 211016 kb
Host smart-4fe56372-a7eb-4d19-a108-4a72ceb22e9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2673983742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2673983742
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1252919528
Short name T354
Test name
Test status
Simulation time 161168442 ps
CPU time 6.61 seconds
Started Aug 19 04:26:39 PM PDT 24
Finished Aug 19 04:26:46 PM PDT 24
Peak memory 211444 kb
Host smart-10d3a707-2a6e-43a6-8710-24795de1d262
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252919528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1252919528
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2810385540
Short name T327
Test name
Test status
Simulation time 1127360511 ps
CPU time 4.7 seconds
Started Aug 19 04:26:48 PM PDT 24
Finished Aug 19 04:26:52 PM PDT 24
Peak memory 210984 kb
Host smart-feee52fd-1e45-4ee4-a355-63a4a43ecc55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810385540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2810385540
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1529943843
Short name T238
Test name
Test status
Simulation time 10429431395 ps
CPU time 179.67 seconds
Started Aug 19 04:26:38 PM PDT 24
Finished Aug 19 04:29:38 PM PDT 24
Peak memory 236480 kb
Host smart-6be43668-0e7e-4adc-b0b0-34a1cbcb9400
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529943843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1529943843
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.4184813603
Short name T41
Test name
Test status
Simulation time 416404011 ps
CPU time 9.26 seconds
Started Aug 19 04:27:01 PM PDT 24
Finished Aug 19 04:27:10 PM PDT 24
Peak memory 211376 kb
Host smart-a037565f-6ac5-42df-afe2-52a02a6f1159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184813603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.4184813603
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.4146599221
Short name T118
Test name
Test status
Simulation time 113746125 ps
CPU time 5.45 seconds
Started Aug 19 04:26:51 PM PDT 24
Finished Aug 19 04:26:57 PM PDT 24
Peak memory 210948 kb
Host smart-505b66b3-82ae-4517-b296-fe3e67735abb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4146599221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.4146599221
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1488551001
Short name T55
Test name
Test status
Simulation time 804873672 ps
CPU time 19.59 seconds
Started Aug 19 04:26:36 PM PDT 24
Finished Aug 19 04:26:56 PM PDT 24
Peak memory 214156 kb
Host smart-78d84630-68c3-45b3-9989-be9edccf58a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488551001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1488551001
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.109076456
Short name T192
Test name
Test status
Simulation time 6098306614 ps
CPU time 82.51 seconds
Started Aug 19 04:26:34 PM PDT 24
Finished Aug 19 04:27:57 PM PDT 24
Peak memory 220456 kb
Host smart-5fbc53d3-8b4b-4c65-a9a9-1e32b7dfaba3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109076456 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.109076456
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3340221674
Short name T157
Test name
Test status
Simulation time 518407207 ps
CPU time 7.03 seconds
Started Aug 19 04:26:35 PM PDT 24
Finished Aug 19 04:26:43 PM PDT 24
Peak memory 210984 kb
Host smart-3b3ba3dd-b784-4f23-9b06-93870a3de986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340221674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3340221674
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1329205690
Short name T6
Test name
Test status
Simulation time 21513738930 ps
CPU time 118.88 seconds
Started Aug 19 04:27:02 PM PDT 24
Finished Aug 19 04:29:01 PM PDT 24
Peak memory 232372 kb
Host smart-b2ecc91d-e885-4e0f-9b60-c5bb16eb460f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329205690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1329205690
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1774461009
Short name T277
Test name
Test status
Simulation time 241437215 ps
CPU time 8.98 seconds
Started Aug 19 04:26:41 PM PDT 24
Finished Aug 19 04:26:50 PM PDT 24
Peak memory 211504 kb
Host smart-a4804134-8c2e-48b7-b73b-5283f1a59f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774461009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1774461009
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3566162236
Short name T231
Test name
Test status
Simulation time 564054770 ps
CPU time 6.27 seconds
Started Aug 19 04:26:48 PM PDT 24
Finished Aug 19 04:26:54 PM PDT 24
Peak memory 211032 kb
Host smart-8d6b4202-20a0-4be9-98f6-0b2502f0d9ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3566162236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3566162236
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1481362679
Short name T191
Test name
Test status
Simulation time 2222946181 ps
CPU time 14.5 seconds
Started Aug 19 04:26:51 PM PDT 24
Finished Aug 19 04:27:05 PM PDT 24
Peak memory 216304 kb
Host smart-aa767f8b-338c-4ff5-b667-faebf5f11f0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481362679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1481362679
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3540514684
Short name T149
Test name
Test status
Simulation time 20617690000 ps
CPU time 119.48 seconds
Started Aug 19 04:26:49 PM PDT 24
Finished Aug 19 04:28:49 PM PDT 24
Peak memory 223276 kb
Host smart-f92ef9ae-44e0-48c4-9cd2-d65401e7d972
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540514684 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.3540514684
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.33414402
Short name T335
Test name
Test status
Simulation time 782831466 ps
CPU time 4.93 seconds
Started Aug 19 04:26:50 PM PDT 24
Finished Aug 19 04:26:55 PM PDT 24
Peak memory 211068 kb
Host smart-ecdd3db6-75f7-4ba9-8db2-949b4a8a0e7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33414402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.33414402
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.4207906792
Short name T14
Test name
Test status
Simulation time 2637868752 ps
CPU time 161.95 seconds
Started Aug 19 04:26:41 PM PDT 24
Finished Aug 19 04:29:23 PM PDT 24
Peak memory 224392 kb
Host smart-aa7e1615-d71a-4652-bd11-1bf40b3c72d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207906792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.4207906792
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.928870154
Short name T302
Test name
Test status
Simulation time 169252737 ps
CPU time 9.1 seconds
Started Aug 19 04:26:36 PM PDT 24
Finished Aug 19 04:26:45 PM PDT 24
Peak memory 211504 kb
Host smart-d53326bf-5ead-40be-be42-8a8db4c68cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928870154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.928870154
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.770207383
Short name T224
Test name
Test status
Simulation time 144271485 ps
CPU time 6.27 seconds
Started Aug 19 04:26:36 PM PDT 24
Finished Aug 19 04:26:42 PM PDT 24
Peak memory 211004 kb
Host smart-fa20541c-463b-4792-a74b-86342573354c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=770207383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.770207383
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.570584804
Short name T189
Test name
Test status
Simulation time 144744803 ps
CPU time 8.87 seconds
Started Aug 19 04:26:35 PM PDT 24
Finished Aug 19 04:26:44 PM PDT 24
Peak memory 210868 kb
Host smart-a9b0716b-9e68-49dc-bdbf-aa05400b23b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570584804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.570584804
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3979450441
Short name T123
Test name
Test status
Simulation time 1043950107 ps
CPU time 3.93 seconds
Started Aug 19 04:26:39 PM PDT 24
Finished Aug 19 04:26:43 PM PDT 24
Peak memory 210948 kb
Host smart-f79dc6a1-aeae-4509-bb75-878f39d18775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979450441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3979450441
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1151720955
Short name T254
Test name
Test status
Simulation time 11333510946 ps
CPU time 111.91 seconds
Started Aug 19 04:26:52 PM PDT 24
Finished Aug 19 04:28:45 PM PDT 24
Peak memory 236676 kb
Host smart-24b657b4-102d-4206-acb3-40d4a4cb8ed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151720955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1151720955
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.315910906
Short name T246
Test name
Test status
Simulation time 919198924 ps
CPU time 10.7 seconds
Started Aug 19 04:26:46 PM PDT 24
Finished Aug 19 04:26:57 PM PDT 24
Peak memory 210996 kb
Host smart-dca52e34-3202-4bfe-b04f-5a657ee7cbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315910906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.315910906
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1354638826
Short name T133
Test name
Test status
Simulation time 603874889 ps
CPU time 6.01 seconds
Started Aug 19 04:27:13 PM PDT 24
Finished Aug 19 04:27:20 PM PDT 24
Peak memory 211028 kb
Host smart-e1a8d03d-031e-421c-9ce3-3431bc6511c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1354638826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1354638826
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.4085903474
Short name T174
Test name
Test status
Simulation time 244367948 ps
CPU time 15.5 seconds
Started Aug 19 04:26:34 PM PDT 24
Finished Aug 19 04:26:55 PM PDT 24
Peak memory 213780 kb
Host smart-47ad0102-dba2-41f8-964f-dda2f435ac79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085903474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.4085903474
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.810385309
Short name T45
Test name
Test status
Simulation time 13707790590 ps
CPU time 120.86 seconds
Started Aug 19 04:26:35 PM PDT 24
Finished Aug 19 04:28:36 PM PDT 24
Peak memory 224376 kb
Host smart-d72b33fd-6161-42b0-b6b0-e41212b71eeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810385309 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.810385309
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1156590232
Short name T293
Test name
Test status
Simulation time 132059046 ps
CPU time 4.79 seconds
Started Aug 19 04:26:24 PM PDT 24
Finished Aug 19 04:26:29 PM PDT 24
Peak memory 210988 kb
Host smart-8a91f121-6c8f-4f21-ad81-4957ba128d27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156590232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1156590232
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.957902275
Short name T355
Test name
Test status
Simulation time 8505022965 ps
CPU time 105.42 seconds
Started Aug 19 04:27:05 PM PDT 24
Finished Aug 19 04:28:50 PM PDT 24
Peak memory 239040 kb
Host smart-690ac367-428a-41a7-81b2-a8066d501332
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957902275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.957902275
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.116494083
Short name T330
Test name
Test status
Simulation time 2079466254 ps
CPU time 10.72 seconds
Started Aug 19 04:27:05 PM PDT 24
Finished Aug 19 04:27:16 PM PDT 24
Peak memory 211484 kb
Host smart-dfd5ea9a-a107-49fc-92cc-c26347d08e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116494083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.116494083
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.672884129
Short name T179
Test name
Test status
Simulation time 101459694 ps
CPU time 5.58 seconds
Started Aug 19 04:26:36 PM PDT 24
Finished Aug 19 04:26:42 PM PDT 24
Peak memory 211004 kb
Host smart-9b436ca0-2c77-494b-a1ee-c034c014018b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=672884129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.672884129
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.4100893358
Short name T28
Test name
Test status
Simulation time 377865861 ps
CPU time 101.6 seconds
Started Aug 19 04:26:42 PM PDT 24
Finished Aug 19 04:28:24 PM PDT 24
Peak memory 235236 kb
Host smart-5772ca33-a742-4986-82a6-78e807af8035
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100893358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.4100893358
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3407514640
Short name T243
Test name
Test status
Simulation time 380805094 ps
CPU time 5.14 seconds
Started Aug 19 04:26:26 PM PDT 24
Finished Aug 19 04:26:32 PM PDT 24
Peak memory 212096 kb
Host smart-acbfffe5-5c32-4792-a8da-9430952691df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407514640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3407514640
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1302389099
Short name T211
Test name
Test status
Simulation time 415438892 ps
CPU time 13.62 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:33 PM PDT 24
Peak memory 213816 kb
Host smart-f4dfd53f-4ca7-420f-b1da-1c3e0aa22ed8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302389099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1302389099
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1871885589
Short name T143
Test name
Test status
Simulation time 336211637 ps
CPU time 4.19 seconds
Started Aug 19 04:26:55 PM PDT 24
Finished Aug 19 04:27:00 PM PDT 24
Peak memory 210980 kb
Host smart-fa79fc62-4a82-4d4d-a094-7a44d91e9337
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871885589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1871885589
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.859793257
Short name T352
Test name
Test status
Simulation time 4347150109 ps
CPU time 95.78 seconds
Started Aug 19 04:26:45 PM PDT 24
Finished Aug 19 04:28:21 PM PDT 24
Peak memory 237520 kb
Host smart-4df94336-a83f-47dc-b1ed-48894423549c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859793257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.859793257
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3820894070
Short name T298
Test name
Test status
Simulation time 1039760597 ps
CPU time 10.52 seconds
Started Aug 19 04:26:35 PM PDT 24
Finished Aug 19 04:26:46 PM PDT 24
Peak memory 210968 kb
Host smart-52c6e726-41f6-49fe-b7c0-7309c3b68875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820894070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3820894070
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1693811678
Short name T306
Test name
Test status
Simulation time 96944935 ps
CPU time 5.05 seconds
Started Aug 19 04:26:46 PM PDT 24
Finished Aug 19 04:26:51 PM PDT 24
Peak memory 211008 kb
Host smart-0c211390-904d-416f-9e95-f5b9301cec23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1693811678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1693811678
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2851396196
Short name T75
Test name
Test status
Simulation time 215319994 ps
CPU time 11.77 seconds
Started Aug 19 04:27:03 PM PDT 24
Finished Aug 19 04:27:15 PM PDT 24
Peak memory 211880 kb
Host smart-f59de582-ee54-4eda-8da5-0f55bc8260ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851396196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2851396196
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.289243900
Short name T115
Test name
Test status
Simulation time 6903071847 ps
CPU time 104.36 seconds
Started Aug 19 04:26:59 PM PDT 24
Finished Aug 19 04:28:44 PM PDT 24
Peak memory 221664 kb
Host smart-9ba33255-d973-4c58-9e9f-496fdf627b4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289243900 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.289243900
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.121129642
Short name T126
Test name
Test status
Simulation time 257438823 ps
CPU time 4.93 seconds
Started Aug 19 04:26:43 PM PDT 24
Finished Aug 19 04:26:48 PM PDT 24
Peak memory 210968 kb
Host smart-6603e9b6-d748-41d3-be7d-8231053dbdf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121129642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.121129642
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3494372185
Short name T279
Test name
Test status
Simulation time 15561453857 ps
CPU time 138.86 seconds
Started Aug 19 04:26:46 PM PDT 24
Finished Aug 19 04:29:05 PM PDT 24
Peak memory 233428 kb
Host smart-f2776e5b-6277-4580-84f0-04a8902f5932
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494372185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3494372185
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1647358212
Short name T245
Test name
Test status
Simulation time 831585580 ps
CPU time 8.95 seconds
Started Aug 19 04:26:33 PM PDT 24
Finished Aug 19 04:26:42 PM PDT 24
Peak memory 211392 kb
Host smart-9470eff6-a828-401e-86dc-b226ab0ffdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647358212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1647358212
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3138643234
Short name T4
Test name
Test status
Simulation time 143046982 ps
CPU time 6.27 seconds
Started Aug 19 04:26:25 PM PDT 24
Finished Aug 19 04:26:36 PM PDT 24
Peak memory 210972 kb
Host smart-68e0a89d-50c4-4c99-8a72-9a7c8ef5652e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3138643234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3138643234
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1158300344
Short name T203
Test name
Test status
Simulation time 118694230 ps
CPU time 7.19 seconds
Started Aug 19 04:26:44 PM PDT 24
Finished Aug 19 04:26:51 PM PDT 24
Peak memory 211700 kb
Host smart-426ca56e-ad55-4c5c-be2e-0933769c11f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158300344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1158300344
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1005044770
Short name T217
Test name
Test status
Simulation time 519918313 ps
CPU time 4.15 seconds
Started Aug 19 04:26:46 PM PDT 24
Finished Aug 19 04:26:50 PM PDT 24
Peak memory 211068 kb
Host smart-d9088df0-46ba-4af4-923e-dd86e7de5593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005044770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1005044770
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1285467426
Short name T214
Test name
Test status
Simulation time 7519350587 ps
CPU time 106.24 seconds
Started Aug 19 04:27:03 PM PDT 24
Finished Aug 19 04:28:49 PM PDT 24
Peak memory 236532 kb
Host smart-7a8837e1-49cd-44ec-8266-a405e7497f3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285467426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1285467426
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.520713835
Short name T181
Test name
Test status
Simulation time 507508607 ps
CPU time 9 seconds
Started Aug 19 04:26:23 PM PDT 24
Finished Aug 19 04:26:32 PM PDT 24
Peak memory 211448 kb
Host smart-ba2ee3c8-c804-4d15-9b4a-46f3d14e15a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520713835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.520713835
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3178039093
Short name T255
Test name
Test status
Simulation time 325264642 ps
CPU time 4.99 seconds
Started Aug 19 04:27:13 PM PDT 24
Finished Aug 19 04:27:18 PM PDT 24
Peak memory 210972 kb
Host smart-621fb4ca-1589-4228-9407-373d3d908f56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3178039093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3178039093
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2114838919
Short name T346
Test name
Test status
Simulation time 4583343373 ps
CPU time 19.8 seconds
Started Aug 19 04:26:42 PM PDT 24
Finished Aug 19 04:27:02 PM PDT 24
Peak memory 216312 kb
Host smart-0d03e812-f8c3-4f85-a94a-0163f7cf6d53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114838919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2114838919
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2183838171
Short name T18
Test name
Test status
Simulation time 6277325975 ps
CPU time 111.99 seconds
Started Aug 19 04:26:54 PM PDT 24
Finished Aug 19 04:28:46 PM PDT 24
Peak memory 227324 kb
Host smart-b342674d-19ba-4d27-987e-99de3e18b124
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183838171 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2183838171
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2097032385
Short name T263
Test name
Test status
Simulation time 521011456 ps
CPU time 4.89 seconds
Started Aug 19 04:26:49 PM PDT 24
Finished Aug 19 04:26:54 PM PDT 24
Peak memory 210980 kb
Host smart-54d4e3ad-d041-4ca1-8de4-52b216ee71ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097032385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2097032385
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1097315041
Short name T39
Test name
Test status
Simulation time 2822023946 ps
CPU time 128.22 seconds
Started Aug 19 04:26:43 PM PDT 24
Finished Aug 19 04:28:51 PM PDT 24
Peak memory 236288 kb
Host smart-3adfc4b7-85dd-4ec5-a451-e5023f40318a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097315041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1097315041
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2353970410
Short name T176
Test name
Test status
Simulation time 695858597 ps
CPU time 9.04 seconds
Started Aug 19 04:26:34 PM PDT 24
Finished Aug 19 04:26:48 PM PDT 24
Peak memory 211000 kb
Host smart-ae37e84c-a472-455d-b8df-b59d80cf4ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353970410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2353970410
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2157159
Short name T249
Test name
Test status
Simulation time 94343519 ps
CPU time 5.29 seconds
Started Aug 19 04:26:47 PM PDT 24
Finished Aug 19 04:26:52 PM PDT 24
Peak memory 210996 kb
Host smart-33dd3914-70e3-4bc8-8e03-964c800724d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2157159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2157159
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2991560135
Short name T324
Test name
Test status
Simulation time 837428289 ps
CPU time 8.62 seconds
Started Aug 19 04:26:58 PM PDT 24
Finished Aug 19 04:27:07 PM PDT 24
Peak memory 211228 kb
Host smart-edc421dc-b5f0-481b-b095-685110791718
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991560135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2991560135
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3596558465
Short name T128
Test name
Test status
Simulation time 176594396 ps
CPU time 4.03 seconds
Started Aug 19 04:27:00 PM PDT 24
Finished Aug 19 04:27:04 PM PDT 24
Peak memory 210980 kb
Host smart-f591cca3-f434-430f-8097-2a3f120d9ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596558465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3596558465
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1655306702
Short name T38
Test name
Test status
Simulation time 2158971285 ps
CPU time 122.4 seconds
Started Aug 19 04:26:41 PM PDT 24
Finished Aug 19 04:28:44 PM PDT 24
Peak memory 211508 kb
Host smart-74dc18ff-ed01-4371-9270-12fa6f5d18b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655306702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1655306702
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2014331130
Short name T280
Test name
Test status
Simulation time 1183325433 ps
CPU time 10.15 seconds
Started Aug 19 04:26:52 PM PDT 24
Finished Aug 19 04:27:04 PM PDT 24
Peak memory 211056 kb
Host smart-ba046cb8-49b6-4040-918e-1beae1a7a377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014331130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2014331130
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1414367010
Short name T234
Test name
Test status
Simulation time 137543692 ps
CPU time 6.4 seconds
Started Aug 19 04:26:43 PM PDT 24
Finished Aug 19 04:26:49 PM PDT 24
Peak memory 210212 kb
Host smart-b7e11f52-e0cb-4955-9146-fd3edc399e44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1414367010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1414367010
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2526003842
Short name T197
Test name
Test status
Simulation time 117123016 ps
CPU time 7 seconds
Started Aug 19 04:26:40 PM PDT 24
Finished Aug 19 04:26:47 PM PDT 24
Peak memory 211012 kb
Host smart-5365af26-015b-4488-98ad-b79219374595
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526003842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2526003842
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.4115844878
Short name T320
Test name
Test status
Simulation time 2860440069 ps
CPU time 24.49 seconds
Started Aug 19 04:26:54 PM PDT 24
Finished Aug 19 04:27:19 PM PDT 24
Peak memory 219288 kb
Host smart-028ef609-f831-48dc-ad3f-9789b3d016d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115844878 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.4115844878
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2912881332
Short name T146
Test name
Test status
Simulation time 230238738 ps
CPU time 4.71 seconds
Started Aug 19 04:26:46 PM PDT 24
Finished Aug 19 04:26:51 PM PDT 24
Peak memory 210992 kb
Host smart-a0816a8a-2f22-47a8-af3f-c7f21c798fc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912881332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2912881332
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1548349670
Short name T262
Test name
Test status
Simulation time 2047101328 ps
CPU time 123.02 seconds
Started Aug 19 04:26:58 PM PDT 24
Finished Aug 19 04:29:01 PM PDT 24
Peak memory 228132 kb
Host smart-db8ce199-9fa9-4cfd-9d97-c4027ba161a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548349670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1548349670
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.121920234
Short name T169
Test name
Test status
Simulation time 1040576591 ps
CPU time 10.44 seconds
Started Aug 19 04:27:08 PM PDT 24
Finished Aug 19 04:27:18 PM PDT 24
Peak memory 211104 kb
Host smart-9c896592-56aa-4d56-93aa-e07f93c7bf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121920234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.121920234
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2095334560
Short name T58
Test name
Test status
Simulation time 191470844 ps
CPU time 5.34 seconds
Started Aug 19 04:26:48 PM PDT 24
Finished Aug 19 04:26:54 PM PDT 24
Peak memory 210996 kb
Host smart-fe382dad-5b59-4e33-8075-cffa801cb020
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2095334560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2095334560
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.493479193
Short name T127
Test name
Test status
Simulation time 509579098 ps
CPU time 18.06 seconds
Started Aug 19 04:26:45 PM PDT 24
Finished Aug 19 04:27:03 PM PDT 24
Peak memory 214764 kb
Host smart-c0842f82-9901-41cf-a83b-8d676ec67655
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493479193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.493479193
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3155311481
Short name T295
Test name
Test status
Simulation time 15590657336 ps
CPU time 138.92 seconds
Started Aug 19 04:26:49 PM PDT 24
Finished Aug 19 04:29:08 PM PDT 24
Peak memory 227352 kb
Host smart-6576ad5d-86be-4404-9f04-3805f194a9bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155311481 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3155311481
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2825340206
Short name T316
Test name
Test status
Simulation time 6706729004 ps
CPU time 81.13 seconds
Started Aug 19 04:26:50 PM PDT 24
Finished Aug 19 04:28:12 PM PDT 24
Peak memory 234748 kb
Host smart-8b556c43-c2cd-458e-8257-a0ee449a1eeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825340206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2825340206
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2629380763
Short name T227
Test name
Test status
Simulation time 669362021 ps
CPU time 8.96 seconds
Started Aug 19 04:26:54 PM PDT 24
Finished Aug 19 04:27:03 PM PDT 24
Peak memory 210992 kb
Host smart-360f2ff4-a5ca-480a-a9b0-1673d0ba4359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629380763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2629380763
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.623986073
Short name T152
Test name
Test status
Simulation time 99212444 ps
CPU time 5.23 seconds
Started Aug 19 04:26:51 PM PDT 24
Finished Aug 19 04:26:59 PM PDT 24
Peak memory 211012 kb
Host smart-ad8e1e37-3acd-480c-bb2d-dfd47d0185f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=623986073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.623986073
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1894091032
Short name T15
Test name
Test status
Simulation time 857528339 ps
CPU time 9.63 seconds
Started Aug 19 04:26:36 PM PDT 24
Finished Aug 19 04:26:46 PM PDT 24
Peak memory 213624 kb
Host smart-f6a4b130-5055-4f3e-97c5-1dd7d42466f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894091032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1894091032
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.4284304945
Short name T131
Test name
Test status
Simulation time 82239180977 ps
CPU time 320.27 seconds
Started Aug 19 04:26:46 PM PDT 24
Finished Aug 19 04:32:06 PM PDT 24
Peak memory 235528 kb
Host smart-6ab186bc-4554-4c30-8bc6-bffa504cb38b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284304945 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.4284304945
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.651861167
Short name T328
Test name
Test status
Simulation time 131727807 ps
CPU time 4.7 seconds
Started Aug 19 04:26:54 PM PDT 24
Finished Aug 19 04:26:59 PM PDT 24
Peak memory 210992 kb
Host smart-869f359a-8460-459f-bafc-b3a9f8f18d3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651861167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.651861167
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3626147210
Short name T278
Test name
Test status
Simulation time 2210631163 ps
CPU time 104.72 seconds
Started Aug 19 04:27:09 PM PDT 24
Finished Aug 19 04:28:54 PM PDT 24
Peak memory 211332 kb
Host smart-3c55e615-6071-4ee3-ac0d-939816779182
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626147210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3626147210
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.740826747
Short name T137
Test name
Test status
Simulation time 1035262891 ps
CPU time 10.48 seconds
Started Aug 19 04:26:51 PM PDT 24
Finished Aug 19 04:27:01 PM PDT 24
Peak memory 211008 kb
Host smart-1f8d642e-c3a7-40f1-9412-3329f6d798d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740826747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.740826747
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2463093265
Short name T325
Test name
Test status
Simulation time 338612254 ps
CPU time 5.12 seconds
Started Aug 19 04:26:55 PM PDT 24
Finished Aug 19 04:27:01 PM PDT 24
Peak memory 211104 kb
Host smart-65649e52-9e5b-40b1-a894-9ca58321d85d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2463093265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2463093265
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3018350337
Short name T156
Test name
Test status
Simulation time 1086368866 ps
CPU time 17.77 seconds
Started Aug 19 04:27:03 PM PDT 24
Finished Aug 19 04:27:21 PM PDT 24
Peak memory 213856 kb
Host smart-c351aead-fbe5-44bf-9fee-218e5ebf69b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018350337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3018350337
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3389710458
Short name T166
Test name
Test status
Simulation time 20429253491 ps
CPU time 242.78 seconds
Started Aug 19 04:26:46 PM PDT 24
Finished Aug 19 04:30:49 PM PDT 24
Peak memory 227332 kb
Host smart-887a95ed-fed9-432e-a179-2bc7036255a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389710458 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.3389710458
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.369072342
Short name T147
Test name
Test status
Simulation time 334587621 ps
CPU time 4.06 seconds
Started Aug 19 04:27:07 PM PDT 24
Finished Aug 19 04:27:11 PM PDT 24
Peak memory 210980 kb
Host smart-d8167f92-64ed-4fab-97dc-d046426b48a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369072342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.369072342
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3096577163
Short name T311
Test name
Test status
Simulation time 1233674370 ps
CPU time 64.43 seconds
Started Aug 19 04:26:47 PM PDT 24
Finished Aug 19 04:27:51 PM PDT 24
Peak memory 232320 kb
Host smart-16f627ea-acf4-48a5-8e5a-a8a4502f0260
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096577163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3096577163
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.939414514
Short name T223
Test name
Test status
Simulation time 692655695 ps
CPU time 8.78 seconds
Started Aug 19 04:27:05 PM PDT 24
Finished Aug 19 04:27:14 PM PDT 24
Peak memory 211468 kb
Host smart-af7f4436-ec44-4f11-8796-16c157f99e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939414514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.939414514
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.4094283823
Short name T155
Test name
Test status
Simulation time 174232502 ps
CPU time 6.39 seconds
Started Aug 19 04:26:44 PM PDT 24
Finished Aug 19 04:26:51 PM PDT 24
Peak memory 210984 kb
Host smart-0bbaca62-cc76-408c-bfa3-8cae02265822
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4094283823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.4094283823
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1585441609
Short name T266
Test name
Test status
Simulation time 629871525 ps
CPU time 13.59 seconds
Started Aug 19 04:27:05 PM PDT 24
Finished Aug 19 04:27:19 PM PDT 24
Peak memory 214256 kb
Host smart-0acb96a6-49c4-44f5-9746-692ff20471c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585441609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1585441609
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2341230991
Short name T178
Test name
Test status
Simulation time 1915921585 ps
CPU time 75.69 seconds
Started Aug 19 04:26:53 PM PDT 24
Finished Aug 19 04:28:09 PM PDT 24
Peak memory 220660 kb
Host smart-816aba99-498f-4708-9646-9f62d821e713
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341230991 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2341230991
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2990924990
Short name T314
Test name
Test status
Simulation time 168439751 ps
CPU time 4.8 seconds
Started Aug 19 04:26:58 PM PDT 24
Finished Aug 19 04:27:03 PM PDT 24
Peak memory 211068 kb
Host smart-047ae574-411a-4962-bfd1-9bb1f9109950
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990924990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2990924990
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1886935082
Short name T205
Test name
Test status
Simulation time 2451932663 ps
CPU time 100.6 seconds
Started Aug 19 04:26:49 PM PDT 24
Finished Aug 19 04:28:30 PM PDT 24
Peak memory 227872 kb
Host smart-28382a52-f8e0-4555-aabd-139b59e5102a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886935082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1886935082
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2144214768
Short name T132
Test name
Test status
Simulation time 694980525 ps
CPU time 10.52 seconds
Started Aug 19 04:27:04 PM PDT 24
Finished Aug 19 04:27:15 PM PDT 24
Peak memory 211376 kb
Host smart-6e6058bb-138c-4529-b43b-23bd6b1f54f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144214768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2144214768
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.634331524
Short name T32
Test name
Test status
Simulation time 98127296 ps
CPU time 5.43 seconds
Started Aug 19 04:27:04 PM PDT 24
Finished Aug 19 04:27:09 PM PDT 24
Peak memory 211100 kb
Host smart-df438a06-f093-4630-8f13-4a6492047f80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=634331524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.634331524
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.870534633
Short name T70
Test name
Test status
Simulation time 545077104 ps
CPU time 12.75 seconds
Started Aug 19 04:27:05 PM PDT 24
Finished Aug 19 04:27:18 PM PDT 24
Peak memory 213780 kb
Host smart-aaca2769-e7a7-44c6-b8b7-2f2981f2ea9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870534633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.870534633
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3849830997
Short name T48
Test name
Test status
Simulation time 1601083222 ps
CPU time 94.09 seconds
Started Aug 19 04:26:49 PM PDT 24
Finished Aug 19 04:28:29 PM PDT 24
Peak memory 220432 kb
Host smart-c2b36ffc-4e2e-4b9c-ae16-baba3254ded8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849830997 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3849830997
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.438328188
Short name T121
Test name
Test status
Simulation time 145016311 ps
CPU time 4.8 seconds
Started Aug 19 04:26:15 PM PDT 24
Finished Aug 19 04:26:20 PM PDT 24
Peak memory 210960 kb
Host smart-046f29ed-3d9d-485f-9963-295add6ef6a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438328188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.438328188
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.494445954
Short name T319
Test name
Test status
Simulation time 1471596427 ps
CPU time 91.49 seconds
Started Aug 19 04:26:21 PM PDT 24
Finished Aug 19 04:27:53 PM PDT 24
Peak memory 228196 kb
Host smart-08bee892-a68f-4fb4-aac0-bb9dd96fc99f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494445954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.494445954
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3518573972
Short name T334
Test name
Test status
Simulation time 253126484 ps
CPU time 10.43 seconds
Started Aug 19 04:26:15 PM PDT 24
Finished Aug 19 04:26:26 PM PDT 24
Peak memory 210996 kb
Host smart-7345d60e-9111-4f9e-a39b-19ca587e586e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518573972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3518573972
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2009115256
Short name T134
Test name
Test status
Simulation time 2081972501 ps
CPU time 8.08 seconds
Started Aug 19 04:26:28 PM PDT 24
Finished Aug 19 04:26:36 PM PDT 24
Peak memory 210972 kb
Host smart-a6052f12-6704-4d5e-b5d1-ad0c04995605
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2009115256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2009115256
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.4216246688
Short name T22
Test name
Test status
Simulation time 981631793 ps
CPU time 97.15 seconds
Started Aug 19 04:27:06 PM PDT 24
Finished Aug 19 04:28:43 PM PDT 24
Peak memory 236688 kb
Host smart-bff4fb30-31ac-486b-9c8a-f830b7d0adfa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216246688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4216246688
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1918478253
Short name T71
Test name
Test status
Simulation time 273227999 ps
CPU time 5.91 seconds
Started Aug 19 04:27:03 PM PDT 24
Finished Aug 19 04:27:09 PM PDT 24
Peak memory 211008 kb
Host smart-c1229b87-f00b-410f-ac74-f25a8027d3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918478253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1918478253
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.639590422
Short name T5
Test name
Test status
Simulation time 277965268 ps
CPU time 12.66 seconds
Started Aug 19 04:27:06 PM PDT 24
Finished Aug 19 04:27:19 PM PDT 24
Peak memory 213064 kb
Host smart-a11ee1f0-502e-4d2d-b7df-28e135a552da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639590422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.639590422
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.112838190
Short name T308
Test name
Test status
Simulation time 3602958147 ps
CPU time 251.3 seconds
Started Aug 19 04:26:30 PM PDT 24
Finished Aug 19 04:30:41 PM PDT 24
Peak memory 230928 kb
Host smart-620c080b-ab0a-44db-a252-5129a2cdaf3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112838190 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.112838190
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2209658151
Short name T125
Test name
Test status
Simulation time 131003864 ps
CPU time 4.86 seconds
Started Aug 19 04:27:08 PM PDT 24
Finished Aug 19 04:27:13 PM PDT 24
Peak memory 210980 kb
Host smart-5687925f-0519-428c-be06-a4a1c28029d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209658151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2209658151
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2102640703
Short name T213
Test name
Test status
Simulation time 23954020659 ps
CPU time 167.86 seconds
Started Aug 19 04:26:52 PM PDT 24
Finished Aug 19 04:29:40 PM PDT 24
Peak memory 237048 kb
Host smart-fd00dc04-da00-43d9-80ee-b578a8992fe5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102640703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2102640703
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4014813696
Short name T281
Test name
Test status
Simulation time 265051073 ps
CPU time 10.35 seconds
Started Aug 19 04:27:13 PM PDT 24
Finished Aug 19 04:27:23 PM PDT 24
Peak memory 211084 kb
Host smart-0d55e602-d62b-4e5a-a7c5-d0c4c64c2226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014813696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4014813696
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.412401869
Short name T60
Test name
Test status
Simulation time 100412516 ps
CPU time 5.51 seconds
Started Aug 19 04:26:50 PM PDT 24
Finished Aug 19 04:26:56 PM PDT 24
Peak memory 210992 kb
Host smart-6ab8e347-d4ae-4b2a-8322-4f71d40010d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=412401869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.412401869
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1275407839
Short name T129
Test name
Test status
Simulation time 1618437716 ps
CPU time 7.42 seconds
Started Aug 19 04:26:53 PM PDT 24
Finished Aug 19 04:27:01 PM PDT 24
Peak memory 210980 kb
Host smart-3418edbc-7c85-432e-a21e-a91bb1350edb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275407839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1275407839
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1531339183
Short name T300
Test name
Test status
Simulation time 11320121885 ps
CPU time 103.91 seconds
Started Aug 19 04:26:51 PM PDT 24
Finished Aug 19 04:28:36 PM PDT 24
Peak memory 232768 kb
Host smart-f008ec13-23a8-4878-8a0c-0c2c5d6b141b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531339183 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1531339183
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.953082606
Short name T251
Test name
Test status
Simulation time 252757536 ps
CPU time 4.24 seconds
Started Aug 19 04:26:53 PM PDT 24
Finished Aug 19 04:26:57 PM PDT 24
Peak memory 210984 kb
Host smart-29df7243-5033-49cb-a649-e3d1c9eb08bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953082606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.953082606
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.947337009
Short name T272
Test name
Test status
Simulation time 2280595315 ps
CPU time 137.91 seconds
Started Aug 19 04:26:51 PM PDT 24
Finished Aug 19 04:29:09 PM PDT 24
Peak memory 228136 kb
Host smart-d7830e13-dd11-4210-a89c-20356ba8eb3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947337009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.947337009
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.317281618
Short name T332
Test name
Test status
Simulation time 280870397 ps
CPU time 8.89 seconds
Started Aug 19 04:26:46 PM PDT 24
Finished Aug 19 04:26:55 PM PDT 24
Peak memory 211384 kb
Host smart-5c2c5bf0-ea19-4dfe-96c0-a2523efa3349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317281618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.317281618
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2493121627
Short name T310
Test name
Test status
Simulation time 510600160 ps
CPU time 7.47 seconds
Started Aug 19 04:26:53 PM PDT 24
Finished Aug 19 04:27:01 PM PDT 24
Peak memory 211008 kb
Host smart-5563435d-31c8-4e22-98ba-5c0f6f6262b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2493121627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2493121627
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1691585445
Short name T210
Test name
Test status
Simulation time 419984109 ps
CPU time 16.15 seconds
Started Aug 19 04:26:49 PM PDT 24
Finished Aug 19 04:27:05 PM PDT 24
Peak memory 213256 kb
Host smart-d646c223-54e3-4204-973e-901d4f7a8286
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691585445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1691585445
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3619061533
Short name T186
Test name
Test status
Simulation time 176932567 ps
CPU time 3.9 seconds
Started Aug 19 04:27:09 PM PDT 24
Finished Aug 19 04:27:13 PM PDT 24
Peak memory 211064 kb
Host smart-5c2d2198-771e-430e-bf0b-5721178ae6b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619061533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3619061533
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2042690528
Short name T286
Test name
Test status
Simulation time 11471567688 ps
CPU time 84.2 seconds
Started Aug 19 04:26:52 PM PDT 24
Finished Aug 19 04:28:18 PM PDT 24
Peak memory 212108 kb
Host smart-f03d20a8-1252-4c70-bbff-38848cd9fbcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042690528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2042690528
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.283259242
Short name T187
Test name
Test status
Simulation time 1035538938 ps
CPU time 10.32 seconds
Started Aug 19 04:26:53 PM PDT 24
Finished Aug 19 04:27:04 PM PDT 24
Peak memory 211096 kb
Host smart-e9ed519d-0f6d-4712-8cda-ed5b5efe0330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283259242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.283259242
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1279302786
Short name T190
Test name
Test status
Simulation time 226718352 ps
CPU time 6.3 seconds
Started Aug 19 04:26:52 PM PDT 24
Finished Aug 19 04:26:58 PM PDT 24
Peak memory 211016 kb
Host smart-af6d445e-4c50-4df4-8cf3-dfe517c4a1a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1279302786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1279302786
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2876018033
Short name T270
Test name
Test status
Simulation time 167711713 ps
CPU time 9.56 seconds
Started Aug 19 04:27:07 PM PDT 24
Finished Aug 19 04:27:17 PM PDT 24
Peak memory 211424 kb
Host smart-db14a89a-44a4-4833-b224-6255832c57cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876018033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2876018033
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1211577861
Short name T260
Test name
Test status
Simulation time 1325067825 ps
CPU time 67.51 seconds
Started Aug 19 04:26:54 PM PDT 24
Finished Aug 19 04:28:02 PM PDT 24
Peak memory 221400 kb
Host smart-49dd01b8-3a26-49a8-bf2c-aa843ea5655d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211577861 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1211577861
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.821443860
Short name T347
Test name
Test status
Simulation time 543818281 ps
CPU time 4.93 seconds
Started Aug 19 04:26:56 PM PDT 24
Finished Aug 19 04:27:01 PM PDT 24
Peak memory 210980 kb
Host smart-d2041baf-dd29-450b-8ecd-8b971077f321
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821443860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.821443860
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1471124191
Short name T8
Test name
Test status
Simulation time 1517912762 ps
CPU time 96.67 seconds
Started Aug 19 04:27:00 PM PDT 24
Finished Aug 19 04:28:36 PM PDT 24
Peak memory 227720 kb
Host smart-64ca30e4-b9f6-4b00-be60-ff2c0993e9df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471124191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1471124191
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2592409025
Short name T258
Test name
Test status
Simulation time 3553511841 ps
CPU time 10.7 seconds
Started Aug 19 04:27:09 PM PDT 24
Finished Aug 19 04:27:25 PM PDT 24
Peak memory 211576 kb
Host smart-abcae552-f020-4dbc-bf9a-00ad0559fb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592409025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2592409025
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3883010933
Short name T35
Test name
Test status
Simulation time 302652333 ps
CPU time 5.81 seconds
Started Aug 19 04:26:54 PM PDT 24
Finished Aug 19 04:27:00 PM PDT 24
Peak memory 211008 kb
Host smart-c61ebe57-af42-4bf1-bb18-65f649a11929
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3883010933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3883010933
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2608802494
Short name T168
Test name
Test status
Simulation time 617199837 ps
CPU time 16.85 seconds
Started Aug 19 04:26:55 PM PDT 24
Finished Aug 19 04:27:13 PM PDT 24
Peak memory 213592 kb
Host smart-f31365ff-4e80-4325-ba9e-d33767b601b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608802494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2608802494
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3931385142
Short name T326
Test name
Test status
Simulation time 17451427369 ps
CPU time 252.1 seconds
Started Aug 19 04:26:59 PM PDT 24
Finished Aug 19 04:31:12 PM PDT 24
Peak memory 233012 kb
Host smart-9f3679f4-4b20-4e35-8110-9bf6b53f638a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931385142 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.3931385142
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.727242499
Short name T303
Test name
Test status
Simulation time 320347982 ps
CPU time 4.78 seconds
Started Aug 19 04:27:05 PM PDT 24
Finished Aug 19 04:27:10 PM PDT 24
Peak memory 211016 kb
Host smart-10829232-ff21-4e1a-a334-2cefafa8ad00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727242499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.727242499
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2615315446
Short name T142
Test name
Test status
Simulation time 3921204147 ps
CPU time 98.66 seconds
Started Aug 19 04:26:50 PM PDT 24
Finished Aug 19 04:28:28 PM PDT 24
Peak memory 237092 kb
Host smart-632adaf7-cf31-4737-9150-784cedc0797e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615315446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2615315446
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3734776701
Short name T233
Test name
Test status
Simulation time 310449602 ps
CPU time 10.39 seconds
Started Aug 19 04:27:07 PM PDT 24
Finished Aug 19 04:27:18 PM PDT 24
Peak memory 211492 kb
Host smart-9cbe3b99-b770-4722-afb0-f867537cfb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734776701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3734776701
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.657631485
Short name T9
Test name
Test status
Simulation time 1504550432 ps
CPU time 7.74 seconds
Started Aug 19 04:27:01 PM PDT 24
Finished Aug 19 04:27:09 PM PDT 24
Peak memory 211016 kb
Host smart-cc9424b0-f7d4-4b24-a560-54d25384e118
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=657631485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.657631485
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3866689977
Short name T333
Test name
Test status
Simulation time 764791172 ps
CPU time 12.94 seconds
Started Aug 19 04:27:10 PM PDT 24
Finished Aug 19 04:27:23 PM PDT 24
Peak memory 212540 kb
Host smart-aec2c7fb-ce0b-4fc8-8e90-2170da275655
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866689977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3866689977
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2781795126
Short name T199
Test name
Test status
Simulation time 4041725835 ps
CPU time 79.76 seconds
Started Aug 19 04:26:47 PM PDT 24
Finished Aug 19 04:28:07 PM PDT 24
Peak memory 231356 kb
Host smart-632da27a-8ae6-443f-8f4b-d1d8ff55bc86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781795126 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2781795126
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1271249870
Short name T36
Test name
Test status
Simulation time 123286880 ps
CPU time 3.87 seconds
Started Aug 19 04:27:04 PM PDT 24
Finished Aug 19 04:27:08 PM PDT 24
Peak memory 210980 kb
Host smart-fbf58ccd-f115-4c9e-a604-abb225ed21af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271249870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1271249870
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.342108299
Short name T309
Test name
Test status
Simulation time 251777346 ps
CPU time 10.42 seconds
Started Aug 19 04:27:11 PM PDT 24
Finished Aug 19 04:27:22 PM PDT 24
Peak memory 210956 kb
Host smart-06d49895-cc49-474e-b20a-5cf78e82f3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342108299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.342108299
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2574471248
Short name T345
Test name
Test status
Simulation time 267586514 ps
CPU time 5.42 seconds
Started Aug 19 04:26:50 PM PDT 24
Finished Aug 19 04:26:55 PM PDT 24
Peak memory 211084 kb
Host smart-6f2541cf-1b92-4354-863c-c4573f5fef22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2574471248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2574471248
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3623386237
Short name T119
Test name
Test status
Simulation time 214607869 ps
CPU time 11.5 seconds
Started Aug 19 04:27:11 PM PDT 24
Finished Aug 19 04:27:22 PM PDT 24
Peak memory 213368 kb
Host smart-e8fc3639-7a44-47af-b7e2-940423253903
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623386237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3623386237
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.81427074
Short name T161
Test name
Test status
Simulation time 2264697264 ps
CPU time 51.31 seconds
Started Aug 19 04:27:05 PM PDT 24
Finished Aug 19 04:27:57 PM PDT 24
Peak memory 220516 kb
Host smart-c3f79fc9-7ba9-4162-802c-32a5eb6044ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81427074 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.81427074
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.182996720
Short name T220
Test name
Test status
Simulation time 333486422 ps
CPU time 4.27 seconds
Started Aug 19 04:26:45 PM PDT 24
Finished Aug 19 04:26:49 PM PDT 24
Peak memory 210988 kb
Host smart-1c33203b-dd82-496a-ad22-ae9319fc76a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182996720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.182996720
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2554239775
Short name T353
Test name
Test status
Simulation time 4521254209 ps
CPU time 142.02 seconds
Started Aug 19 04:26:45 PM PDT 24
Finished Aug 19 04:29:07 PM PDT 24
Peak memory 233484 kb
Host smart-3a924582-5cf3-4d8a-8aa5-8e5de745841a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554239775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2554239775
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1846901936
Short name T322
Test name
Test status
Simulation time 173147138 ps
CPU time 9.22 seconds
Started Aug 19 04:27:14 PM PDT 24
Finished Aug 19 04:27:23 PM PDT 24
Peak memory 211016 kb
Host smart-b9f352f6-0af6-4416-8fe7-532ac0c8928a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846901936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1846901936
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.119426406
Short name T215
Test name
Test status
Simulation time 148671458 ps
CPU time 5.84 seconds
Started Aug 19 04:26:46 PM PDT 24
Finished Aug 19 04:26:52 PM PDT 24
Peak memory 211004 kb
Host smart-30d09839-17f8-49ef-92d7-f7a27e1d2e95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=119426406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.119426406
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3397738011
Short name T265
Test name
Test status
Simulation time 1186593818 ps
CPU time 18.71 seconds
Started Aug 19 04:26:51 PM PDT 24
Finished Aug 19 04:27:09 PM PDT 24
Peak memory 214392 kb
Host smart-3c920185-a3d9-473e-9fa4-307b58e467a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397738011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3397738011
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1578414718
Short name T50
Test name
Test status
Simulation time 18413664611 ps
CPU time 315.99 seconds
Started Aug 19 04:26:48 PM PDT 24
Finished Aug 19 04:32:04 PM PDT 24
Peak memory 233448 kb
Host smart-328629e5-a42c-4422-a79b-ef32e68883e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578414718 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1578414718
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1983746658
Short name T124
Test name
Test status
Simulation time 253846454 ps
CPU time 3.87 seconds
Started Aug 19 04:26:52 PM PDT 24
Finished Aug 19 04:26:57 PM PDT 24
Peak memory 211068 kb
Host smart-a4bd639c-c6b7-4141-8f85-14ca2a0f60a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983746658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1983746658
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1939994481
Short name T167
Test name
Test status
Simulation time 4865730190 ps
CPU time 107.33 seconds
Started Aug 19 04:26:59 PM PDT 24
Finished Aug 19 04:28:47 PM PDT 24
Peak memory 212348 kb
Host smart-958798e6-fc9c-4e6c-bcc4-fc45e389c1f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939994481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1939994481
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2183751445
Short name T343
Test name
Test status
Simulation time 2083679551 ps
CPU time 8.86 seconds
Started Aug 19 04:26:59 PM PDT 24
Finished Aug 19 04:27:08 PM PDT 24
Peak memory 211392 kb
Host smart-c5506a6b-0300-4337-9892-28d172e647c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183751445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2183751445
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2589460107
Short name T357
Test name
Test status
Simulation time 180863692 ps
CPU time 5.06 seconds
Started Aug 19 04:26:59 PM PDT 24
Finished Aug 19 04:27:04 PM PDT 24
Peak memory 211008 kb
Host smart-bc008f48-ffe2-4f8f-9ca1-2d9c93292a83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2589460107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2589460107
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.4258134328
Short name T232
Test name
Test status
Simulation time 569737258 ps
CPU time 23.09 seconds
Started Aug 19 04:27:03 PM PDT 24
Finished Aug 19 04:27:26 PM PDT 24
Peak memory 215316 kb
Host smart-d2747ab5-5b3c-4032-83ca-c4917dadefd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258134328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.4258134328
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3433015317
Short name T144
Test name
Test status
Simulation time 6472837605 ps
CPU time 85.96 seconds
Started Aug 19 04:26:53 PM PDT 24
Finished Aug 19 04:28:19 PM PDT 24
Peak memory 221856 kb
Host smart-ca393074-0f48-4320-aba6-4af139af1b49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433015317 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3433015317
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.426470323
Short name T194
Test name
Test status
Simulation time 89816286 ps
CPU time 4.02 seconds
Started Aug 19 04:27:09 PM PDT 24
Finished Aug 19 04:27:14 PM PDT 24
Peak memory 210980 kb
Host smart-8b74f693-2190-472b-ad38-6d2d3db6aad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426470323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.426470323
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2339608233
Short name T336
Test name
Test status
Simulation time 12681395043 ps
CPU time 77.41 seconds
Started Aug 19 04:26:52 PM PDT 24
Finished Aug 19 04:28:11 PM PDT 24
Peak memory 212460 kb
Host smart-db5b141b-87d0-46ac-9be5-be0feec6f16c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339608233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2339608233
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.4109474194
Short name T163
Test name
Test status
Simulation time 263726311 ps
CPU time 10.52 seconds
Started Aug 19 04:27:11 PM PDT 24
Finished Aug 19 04:27:22 PM PDT 24
Peak memory 211392 kb
Host smart-66ac8a69-6f3d-402c-8bf0-a750d5f176e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109474194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.4109474194
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1604272363
Short name T289
Test name
Test status
Simulation time 100106621 ps
CPU time 5.57 seconds
Started Aug 19 04:27:14 PM PDT 24
Finished Aug 19 04:27:20 PM PDT 24
Peak memory 211120 kb
Host smart-4181b573-118d-4cb3-bf95-6f3e541cd596
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1604272363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1604272363
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.4154526003
Short name T284
Test name
Test status
Simulation time 398568876 ps
CPU time 10 seconds
Started Aug 19 04:27:12 PM PDT 24
Finished Aug 19 04:27:22 PM PDT 24
Peak memory 213956 kb
Host smart-f1ba3f30-9821-4738-bc77-e084214d083c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154526003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.4154526003
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1793086989
Short name T135
Test name
Test status
Simulation time 4433250631 ps
CPU time 258.02 seconds
Started Aug 19 04:26:57 PM PDT 24
Finished Aug 19 04:31:15 PM PDT 24
Peak memory 227660 kb
Host smart-f6d7f3cc-0e39-4400-9df6-aef7fb0cbd34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793086989 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1793086989
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.4285391547
Short name T269
Test name
Test status
Simulation time 333204869 ps
CPU time 3.91 seconds
Started Aug 19 04:26:49 PM PDT 24
Finished Aug 19 04:26:53 PM PDT 24
Peak memory 210980 kb
Host smart-e2cb5b11-adc0-4667-ad50-d1cee0181058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285391547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.4285391547
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2307807011
Short name T283
Test name
Test status
Simulation time 11432804563 ps
CPU time 150.15 seconds
Started Aug 19 04:27:07 PM PDT 24
Finished Aug 19 04:29:37 PM PDT 24
Peak memory 236608 kb
Host smart-e5dffd19-1dc9-41f1-ade1-d1f1fd5f3869
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307807011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2307807011
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3541871537
Short name T204
Test name
Test status
Simulation time 266853323 ps
CPU time 10.66 seconds
Started Aug 19 04:26:45 PM PDT 24
Finished Aug 19 04:26:56 PM PDT 24
Peak memory 211384 kb
Host smart-f4f7c65e-8b6d-45d8-a531-a1c98392ecba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541871537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3541871537
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1194150919
Short name T117
Test name
Test status
Simulation time 820740320 ps
CPU time 5.23 seconds
Started Aug 19 04:26:59 PM PDT 24
Finished Aug 19 04:27:04 PM PDT 24
Peak memory 211008 kb
Host smart-f244ac0d-06f7-445d-a957-d4a7e192f1d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1194150919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1194150919
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3840035252
Short name T313
Test name
Test status
Simulation time 198418408 ps
CPU time 11.82 seconds
Started Aug 19 04:26:49 PM PDT 24
Finished Aug 19 04:27:01 PM PDT 24
Peak memory 213688 kb
Host smart-9dd15d55-a99e-4b50-97d0-50e27e4023b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840035252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3840035252
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3748296759
Short name T201
Test name
Test status
Simulation time 133257005 ps
CPU time 4.73 seconds
Started Aug 19 04:26:15 PM PDT 24
Finished Aug 19 04:26:20 PM PDT 24
Peak memory 210976 kb
Host smart-8315b1eb-b633-4309-b194-a3565589000b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748296759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3748296759
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2674889662
Short name T37
Test name
Test status
Simulation time 52307419930 ps
CPU time 224.98 seconds
Started Aug 19 04:26:24 PM PDT 24
Finished Aug 19 04:30:09 PM PDT 24
Peak memory 228244 kb
Host smart-04dc9994-b309-4a9c-9bce-6ee6ca1a3064
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674889662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2674889662
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.941693917
Short name T271
Test name
Test status
Simulation time 393374409 ps
CPU time 6.23 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:27 PM PDT 24
Peak memory 211004 kb
Host smart-37bb985b-d487-4950-8a75-cf2d577fa3d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=941693917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.941693917
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3086043707
Short name T21
Test name
Test status
Simulation time 581255648 ps
CPU time 50.17 seconds
Started Aug 19 04:26:23 PM PDT 24
Finished Aug 19 04:27:13 PM PDT 24
Peak memory 236060 kb
Host smart-6ed21e6d-20f5-4f2a-81ec-bd72675219dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086043707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3086043707
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.327064274
Short name T206
Test name
Test status
Simulation time 268650292 ps
CPU time 6.11 seconds
Started Aug 19 04:26:25 PM PDT 24
Finished Aug 19 04:26:32 PM PDT 24
Peak memory 210972 kb
Host smart-75053a88-8807-4ab7-928f-b66200c9ec6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327064274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.327064274
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2689273811
Short name T253
Test name
Test status
Simulation time 1733466615 ps
CPU time 19.53 seconds
Started Aug 19 04:26:22 PM PDT 24
Finished Aug 19 04:26:42 PM PDT 24
Peak memory 215420 kb
Host smart-a7e76b6d-986f-405a-92b0-46c311d56a02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689273811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2689273811
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.236455304
Short name T164
Test name
Test status
Simulation time 6568379745 ps
CPU time 106.03 seconds
Started Aug 19 04:26:30 PM PDT 24
Finished Aug 19 04:28:16 PM PDT 24
Peak memory 223008 kb
Host smart-f13d9d8d-c64e-4183-a118-aa36676c04c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236455304 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.236455304
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2886570572
Short name T230
Test name
Test status
Simulation time 1390214284 ps
CPU time 5.07 seconds
Started Aug 19 04:27:03 PM PDT 24
Finished Aug 19 04:27:08 PM PDT 24
Peak memory 211112 kb
Host smart-5318dfc0-2d3a-4fe5-88d2-ade27af5876c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886570572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2886570572
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3907263944
Short name T339
Test name
Test status
Simulation time 4645152054 ps
CPU time 148.31 seconds
Started Aug 19 04:27:08 PM PDT 24
Finished Aug 19 04:29:36 PM PDT 24
Peak memory 233452 kb
Host smart-acb1ac5d-0fb3-4b25-ae32-ca18e98dcfba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907263944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3907263944
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1980748962
Short name T274
Test name
Test status
Simulation time 171552498 ps
CPU time 8.87 seconds
Started Aug 19 04:26:55 PM PDT 24
Finished Aug 19 04:27:04 PM PDT 24
Peak memory 211076 kb
Host smart-c45aa619-d62e-45ab-bb93-c811d22808b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980748962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1980748962
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.4285601660
Short name T184
Test name
Test status
Simulation time 143926057 ps
CPU time 6.08 seconds
Started Aug 19 04:27:12 PM PDT 24
Finished Aug 19 04:27:19 PM PDT 24
Peak memory 211020 kb
Host smart-3011308c-be37-4bfa-9229-9256d2cfc4cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4285601660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.4285601660
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3425754381
Short name T212
Test name
Test status
Simulation time 1563186612 ps
CPU time 15.37 seconds
Started Aug 19 04:26:52 PM PDT 24
Finished Aug 19 04:27:08 PM PDT 24
Peak memory 212948 kb
Host smart-fa7f70fa-c649-4ad9-9d13-70bb401482ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425754381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3425754381
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1429440451
Short name T257
Test name
Test status
Simulation time 258093436 ps
CPU time 4.92 seconds
Started Aug 19 04:26:56 PM PDT 24
Finished Aug 19 04:27:01 PM PDT 24
Peak memory 210992 kb
Host smart-104712d5-5891-475b-a951-fd5db707718b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429440451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1429440451
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1903960815
Short name T282
Test name
Test status
Simulation time 5455820675 ps
CPU time 65.95 seconds
Started Aug 19 04:27:02 PM PDT 24
Finished Aug 19 04:28:08 PM PDT 24
Peak memory 228292 kb
Host smart-e42a1ba4-3031-41ed-8adc-c3a05c351d74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903960815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1903960815
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.137536496
Short name T27
Test name
Test status
Simulation time 2755444269 ps
CPU time 10.52 seconds
Started Aug 19 04:26:53 PM PDT 24
Finished Aug 19 04:27:04 PM PDT 24
Peak memory 211464 kb
Host smart-694d2302-650d-4233-a9f5-0d929f5ca2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137536496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.137536496
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2387299514
Short name T31
Test name
Test status
Simulation time 700829900 ps
CPU time 5.34 seconds
Started Aug 19 04:26:54 PM PDT 24
Finished Aug 19 04:27:00 PM PDT 24
Peak memory 211000 kb
Host smart-204c7b17-3866-4590-aec0-d29f375d44f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2387299514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2387299514
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3718599245
Short name T158
Test name
Test status
Simulation time 737954138 ps
CPU time 7.13 seconds
Started Aug 19 04:26:55 PM PDT 24
Finished Aug 19 04:27:03 PM PDT 24
Peak memory 210872 kb
Host smart-95cc2dc4-c645-4bbf-854e-4e1f28298078
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718599245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3718599245
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2976228175
Short name T291
Test name
Test status
Simulation time 11766096093 ps
CPU time 192.76 seconds
Started Aug 19 04:27:44 PM PDT 24
Finished Aug 19 04:30:57 PM PDT 24
Peak memory 222544 kb
Host smart-bd5c3e45-5096-4073-b273-6d856c81ec44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976228175 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2976228175
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.125705409
Short name T342
Test name
Test status
Simulation time 88268560 ps
CPU time 4.07 seconds
Started Aug 19 04:26:51 PM PDT 24
Finished Aug 19 04:26:55 PM PDT 24
Peak memory 210984 kb
Host smart-90877c88-da22-4a30-9acb-2669db3f7268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125705409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.125705409
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3317925120
Short name T247
Test name
Test status
Simulation time 2277902502 ps
CPU time 104.67 seconds
Started Aug 19 04:27:09 PM PDT 24
Finished Aug 19 04:28:54 PM PDT 24
Peak memory 236132 kb
Host smart-a25f67dd-a96d-4c5f-932f-b1c37ccd5529
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317925120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3317925120
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.266608973
Short name T141
Test name
Test status
Simulation time 252300491 ps
CPU time 10.4 seconds
Started Aug 19 04:27:10 PM PDT 24
Finished Aug 19 04:27:21 PM PDT 24
Peak memory 211084 kb
Host smart-fc1068e6-60ab-497b-b6d2-1b4e0da0e6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266608973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.266608973
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2637184252
Short name T307
Test name
Test status
Simulation time 1864188042 ps
CPU time 5.63 seconds
Started Aug 19 04:27:15 PM PDT 24
Finished Aug 19 04:27:21 PM PDT 24
Peak memory 211028 kb
Host smart-0a625560-70d6-4468-8d8f-946773e46efc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2637184252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2637184252
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3073578107
Short name T145
Test name
Test status
Simulation time 666194378 ps
CPU time 8.27 seconds
Started Aug 19 04:27:08 PM PDT 24
Finished Aug 19 04:27:16 PM PDT 24
Peak memory 211752 kb
Host smart-c3218b08-ea4f-4e7b-81b0-76b31780a67a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073578107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3073578107
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1010892083
Short name T312
Test name
Test status
Simulation time 11357266288 ps
CPU time 187.14 seconds
Started Aug 19 04:26:55 PM PDT 24
Finished Aug 19 04:30:03 PM PDT 24
Peak memory 222720 kb
Host smart-b1031d52-57e4-407a-acbf-687ddb273362
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010892083 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.1010892083
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1749449716
Short name T24
Test name
Test status
Simulation time 258452385 ps
CPU time 4.83 seconds
Started Aug 19 04:27:16 PM PDT 24
Finished Aug 19 04:27:21 PM PDT 24
Peak memory 211084 kb
Host smart-f741e41d-2b9a-4613-abde-a75f5002ee34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749449716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1749449716
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.413903613
Short name T297
Test name
Test status
Simulation time 2015919584 ps
CPU time 97.61 seconds
Started Aug 19 04:27:12 PM PDT 24
Finished Aug 19 04:28:50 PM PDT 24
Peak memory 232372 kb
Host smart-b0054390-97af-4091-b550-a340afebfd42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413903613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.413903613
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1731986255
Short name T268
Test name
Test status
Simulation time 261336498 ps
CPU time 10.78 seconds
Started Aug 19 04:27:01 PM PDT 24
Finished Aug 19 04:27:12 PM PDT 24
Peak memory 211076 kb
Host smart-d4e211d7-2ef3-46b5-97a2-82972869b70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731986255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1731986255
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.934586884
Short name T273
Test name
Test status
Simulation time 346295244 ps
CPU time 5.36 seconds
Started Aug 19 04:27:22 PM PDT 24
Finished Aug 19 04:27:27 PM PDT 24
Peak memory 211104 kb
Host smart-18c5f639-8430-4dde-ba2b-7e54c3ead7ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=934586884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.934586884
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3769233894
Short name T256
Test name
Test status
Simulation time 662204704 ps
CPU time 10.14 seconds
Started Aug 19 04:26:54 PM PDT 24
Finished Aug 19 04:27:05 PM PDT 24
Peak memory 211564 kb
Host smart-cfa2061f-692f-4003-b9f8-9943cbe9be9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769233894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3769233894
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.557118898
Short name T175
Test name
Test status
Simulation time 27740410227 ps
CPU time 197.87 seconds
Started Aug 19 04:26:54 PM PDT 24
Finished Aug 19 04:30:12 PM PDT 24
Peak memory 225108 kb
Host smart-302cc936-d5cc-4446-9cc5-8c198f87ff45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557118898 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.557118898
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.605780812
Short name T138
Test name
Test status
Simulation time 546764759 ps
CPU time 4.79 seconds
Started Aug 19 04:27:07 PM PDT 24
Finished Aug 19 04:27:12 PM PDT 24
Peak memory 210976 kb
Host smart-5d1a892e-4933-465f-ac6f-16d54330c82f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605780812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.605780812
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3707576182
Short name T193
Test name
Test status
Simulation time 6224839332 ps
CPU time 105.68 seconds
Started Aug 19 04:26:52 PM PDT 24
Finished Aug 19 04:28:38 PM PDT 24
Peak memory 228248 kb
Host smart-5517b53b-b7c6-4b49-b8dc-dc99defd8886
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707576182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3707576182
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3451442462
Short name T154
Test name
Test status
Simulation time 253320469 ps
CPU time 10.63 seconds
Started Aug 19 04:26:50 PM PDT 24
Finished Aug 19 04:27:01 PM PDT 24
Peak memory 211076 kb
Host smart-e804cd58-ced4-4119-8b4b-b3f1d2a51ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451442462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3451442462
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1443986540
Short name T140
Test name
Test status
Simulation time 282741568 ps
CPU time 5.46 seconds
Started Aug 19 04:26:50 PM PDT 24
Finished Aug 19 04:26:56 PM PDT 24
Peak memory 210988 kb
Host smart-3886f28c-bff6-4fa6-9191-8373a5ea5929
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1443986540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1443986540
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3630022924
Short name T208
Test name
Test status
Simulation time 121214554 ps
CPU time 7.22 seconds
Started Aug 19 04:27:12 PM PDT 24
Finished Aug 19 04:27:19 PM PDT 24
Peak memory 211076 kb
Host smart-cd7b97c3-d424-4f34-82b6-04de8321bc17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630022924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3630022924
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2263453986
Short name T240
Test name
Test status
Simulation time 11869158809 ps
CPU time 220.06 seconds
Started Aug 19 04:27:07 PM PDT 24
Finished Aug 19 04:30:47 PM PDT 24
Peak memory 233984 kb
Host smart-99edb562-03a2-4d81-a67f-c15b07d2ff37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263453986 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2263453986
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1530413997
Short name T348
Test name
Test status
Simulation time 1769733649 ps
CPU time 4.83 seconds
Started Aug 19 04:27:10 PM PDT 24
Finished Aug 19 04:27:15 PM PDT 24
Peak memory 210980 kb
Host smart-117ffaa2-deca-43ff-80c9-bde6e4c656fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530413997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1530413997
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1917514306
Short name T25
Test name
Test status
Simulation time 170062214 ps
CPU time 9.17 seconds
Started Aug 19 04:26:52 PM PDT 24
Finished Aug 19 04:27:01 PM PDT 24
Peak memory 211332 kb
Host smart-d97be19f-a890-417e-9a5e-c98adffc37f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917514306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1917514306
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.672634056
Short name T241
Test name
Test status
Simulation time 98684128 ps
CPU time 5.5 seconds
Started Aug 19 04:26:54 PM PDT 24
Finished Aug 19 04:27:00 PM PDT 24
Peak memory 211092 kb
Host smart-0c56707c-a09c-47c3-a945-999f54ce1564
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=672634056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.672634056
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3143712205
Short name T296
Test name
Test status
Simulation time 1492044409 ps
CPU time 17.85 seconds
Started Aug 19 04:27:14 PM PDT 24
Finished Aug 19 04:27:32 PM PDT 24
Peak memory 214468 kb
Host smart-bd31d05f-d4d1-4588-903f-dbe732d88397
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143712205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3143712205
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.1039742720
Short name T51
Test name
Test status
Simulation time 3380074363 ps
CPU time 142.2 seconds
Started Aug 19 04:26:54 PM PDT 24
Finished Aug 19 04:29:16 PM PDT 24
Peak memory 223304 kb
Host smart-7f4e64eb-aa63-4f92-bc19-716cdcd59dc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039742720 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.1039742720
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3704211012
Short name T160
Test name
Test status
Simulation time 328536299 ps
CPU time 4.71 seconds
Started Aug 19 04:27:13 PM PDT 24
Finished Aug 19 04:27:18 PM PDT 24
Peak memory 210980 kb
Host smart-2448524d-4199-4bc1-9f4a-5ff863592036
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704211012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3704211012
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1707151788
Short name T40
Test name
Test status
Simulation time 3828907683 ps
CPU time 95.95 seconds
Started Aug 19 04:26:52 PM PDT 24
Finished Aug 19 04:28:29 PM PDT 24
Peak memory 236396 kb
Host smart-62725e83-4ff5-47c0-ae87-c0b30370ae95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707151788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1707151788
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4006170933
Short name T237
Test name
Test status
Simulation time 270567840 ps
CPU time 10.48 seconds
Started Aug 19 04:27:11 PM PDT 24
Finished Aug 19 04:27:22 PM PDT 24
Peak memory 210968 kb
Host smart-4b0d7c8c-e109-4e09-8718-72d0c2d81f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006170933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4006170933
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.4182978081
Short name T120
Test name
Test status
Simulation time 405655778 ps
CPU time 5.3 seconds
Started Aug 19 04:27:13 PM PDT 24
Finished Aug 19 04:27:18 PM PDT 24
Peak memory 210972 kb
Host smart-fd3d1bbf-8b22-4d46-8eeb-523de7cde401
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182978081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.4182978081
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.56439058
Short name T74
Test name
Test status
Simulation time 5605913503 ps
CPU time 13.37 seconds
Started Aug 19 04:26:50 PM PDT 24
Finished Aug 19 04:27:04 PM PDT 24
Peak memory 214844 kb
Host smart-615ead07-f1e9-4147-9294-3705a27ad9c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56439058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 46.rom_ctrl_stress_all.56439058
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3963338016
Short name T44
Test name
Test status
Simulation time 9475665518 ps
CPU time 153.15 seconds
Started Aug 19 04:27:08 PM PDT 24
Finished Aug 19 04:29:41 PM PDT 24
Peak memory 223228 kb
Host smart-05ccae4d-d3d1-4292-9758-00fbe68debc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963338016 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.3963338016
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2288111209
Short name T252
Test name
Test status
Simulation time 127012626 ps
CPU time 4.76 seconds
Started Aug 19 04:27:30 PM PDT 24
Finished Aug 19 04:27:35 PM PDT 24
Peak memory 211072 kb
Host smart-fc433873-4303-427f-8bd0-1e458aa0d905
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288111209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2288111209
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3320148212
Short name T285
Test name
Test status
Simulation time 31011213547 ps
CPU time 113.47 seconds
Started Aug 19 04:26:59 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 236616 kb
Host smart-d03559d6-983f-474c-891f-6928e9df0aed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320148212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3320148212
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.33816686
Short name T250
Test name
Test status
Simulation time 261114289 ps
CPU time 10.24 seconds
Started Aug 19 04:26:53 PM PDT 24
Finished Aug 19 04:27:03 PM PDT 24
Peak memory 211332 kb
Host smart-7c334ea0-f55b-4395-ba38-4b4d7a278730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33816686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.33816686
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1293224492
Short name T225
Test name
Test status
Simulation time 142462087 ps
CPU time 5.86 seconds
Started Aug 19 04:26:59 PM PDT 24
Finished Aug 19 04:27:05 PM PDT 24
Peak memory 210988 kb
Host smart-7af4d240-e90b-4077-8d94-14c38f79c1eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1293224492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1293224492
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2845920539
Short name T12
Test name
Test status
Simulation time 8052030160 ps
CPU time 31.15 seconds
Started Aug 19 04:27:02 PM PDT 24
Finished Aug 19 04:27:33 PM PDT 24
Peak memory 215992 kb
Host smart-8c3a1bc9-4aee-4514-88f7-aff907883813
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845920539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2845920539
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3396257863
Short name T46
Test name
Test status
Simulation time 6489102951 ps
CPU time 77.72 seconds
Started Aug 19 04:26:53 PM PDT 24
Finished Aug 19 04:28:11 PM PDT 24
Peak memory 221748 kb
Host smart-70e96133-5b79-4d0a-ac45-6f570cf1e78d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396257863 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.3396257863
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.399597269
Short name T276
Test name
Test status
Simulation time 521683875 ps
CPU time 4.9 seconds
Started Aug 19 04:27:56 PM PDT 24
Finished Aug 19 04:28:01 PM PDT 24
Peak memory 211072 kb
Host smart-4c7fced6-d049-41c6-a23b-5169cacc226f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399597269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.399597269
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1716792410
Short name T171
Test name
Test status
Simulation time 7238197010 ps
CPU time 97.56 seconds
Started Aug 19 04:26:54 PM PDT 24
Finished Aug 19 04:28:32 PM PDT 24
Peak memory 233480 kb
Host smart-0a6ff60e-cd63-4452-9207-19e0691aaab6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716792410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1716792410
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.991276261
Short name T358
Test name
Test status
Simulation time 1134842438 ps
CPU time 10.38 seconds
Started Aug 19 04:27:45 PM PDT 24
Finished Aug 19 04:27:56 PM PDT 24
Peak memory 211528 kb
Host smart-43756aa7-1a3f-4ae4-8821-032ae105ff03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991276261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.991276261
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3814570835
Short name T200
Test name
Test status
Simulation time 97663376 ps
CPU time 5.02 seconds
Started Aug 19 04:26:53 PM PDT 24
Finished Aug 19 04:26:58 PM PDT 24
Peak memory 210948 kb
Host smart-18c78ddf-7564-4f61-a390-b4f0af891270
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3814570835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3814570835
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2296410985
Short name T222
Test name
Test status
Simulation time 221989017 ps
CPU time 7.17 seconds
Started Aug 19 04:26:53 PM PDT 24
Finished Aug 19 04:27:01 PM PDT 24
Peak memory 210952 kb
Host smart-cd36fc9b-8110-49a1-92ac-4dfbc682b0c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296410985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2296410985
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1277027631
Short name T317
Test name
Test status
Simulation time 1890233536 ps
CPU time 108.64 seconds
Started Aug 19 04:27:49 PM PDT 24
Finished Aug 19 04:29:38 PM PDT 24
Peak memory 221836 kb
Host smart-dd75ac8c-b206-453e-ba58-77c64db33212
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277027631 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.1277027631
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.9797739
Short name T318
Test name
Test status
Simulation time 500250995 ps
CPU time 5.11 seconds
Started Aug 19 04:27:53 PM PDT 24
Finished Aug 19 04:27:58 PM PDT 24
Peak memory 211104 kb
Host smart-10b2f306-c880-4e11-bb69-0c6f878cb98f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9797739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.9797739
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.594655140
Short name T33
Test name
Test status
Simulation time 14043874099 ps
CPU time 129.35 seconds
Started Aug 19 04:26:50 PM PDT 24
Finished Aug 19 04:29:00 PM PDT 24
Peak memory 226408 kb
Host smart-754bbcb3-c2be-45cc-8f84-200cf895b1c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594655140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.594655140
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1850842504
Short name T290
Test name
Test status
Simulation time 256066373 ps
CPU time 10.69 seconds
Started Aug 19 04:26:50 PM PDT 24
Finished Aug 19 04:27:01 PM PDT 24
Peak memory 211412 kb
Host smart-a78e5a9b-0083-45b3-87cc-5246414ce697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850842504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1850842504
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.4144424913
Short name T229
Test name
Test status
Simulation time 137517714 ps
CPU time 5.99 seconds
Started Aug 19 04:27:05 PM PDT 24
Finished Aug 19 04:27:11 PM PDT 24
Peak memory 211024 kb
Host smart-2ec4e7fe-53ae-46ae-8092-78c01fc04066
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4144424913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.4144424913
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2854089588
Short name T340
Test name
Test status
Simulation time 6253292317 ps
CPU time 18.32 seconds
Started Aug 19 04:26:53 PM PDT 24
Finished Aug 19 04:27:11 PM PDT 24
Peak memory 216988 kb
Host smart-d3d6330f-4a38-4144-8057-0977e9ea41b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854089588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2854089588
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2429521897
Short name T259
Test name
Test status
Simulation time 3903522716 ps
CPU time 134.39 seconds
Started Aug 19 04:27:05 PM PDT 24
Finished Aug 19 04:29:19 PM PDT 24
Peak memory 222668 kb
Host smart-e4398715-7dfb-4b53-a271-94807c4b8c20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429521897 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2429521897
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3932015623
Short name T23
Test name
Test status
Simulation time 128135614 ps
CPU time 4.84 seconds
Started Aug 19 04:26:52 PM PDT 24
Finished Aug 19 04:26:56 PM PDT 24
Peak memory 210984 kb
Host smart-628e55c5-d0bb-4e2c-808c-41aaf5ee8893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932015623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3932015623
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2867894637
Short name T228
Test name
Test status
Simulation time 4195472263 ps
CPU time 187.42 seconds
Started Aug 19 04:26:37 PM PDT 24
Finished Aug 19 04:29:44 PM PDT 24
Peak memory 236664 kb
Host smart-5289d45c-f169-47ad-acce-9b711645e266
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867894637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2867894637
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3949360877
Short name T226
Test name
Test status
Simulation time 333613585 ps
CPU time 9.31 seconds
Started Aug 19 04:26:31 PM PDT 24
Finished Aug 19 04:26:41 PM PDT 24
Peak memory 211540 kb
Host smart-9a0b3d0b-27ed-40bc-abc3-74ad4b0dd650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949360877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3949360877
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.906943059
Short name T150
Test name
Test status
Simulation time 372798855 ps
CPU time 5.31 seconds
Started Aug 19 04:26:27 PM PDT 24
Finished Aug 19 04:26:35 PM PDT 24
Peak memory 211008 kb
Host smart-3f048a84-057b-4b57-ace2-f6595588fc00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=906943059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.906943059
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2010360045
Short name T76
Test name
Test status
Simulation time 287880352 ps
CPU time 6.24 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:25 PM PDT 24
Peak memory 211324 kb
Host smart-5c9c6304-a4cd-49b8-ae97-cfe443456893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010360045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2010360045
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2778807141
Short name T329
Test name
Test status
Simulation time 210418733 ps
CPU time 11.38 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:31 PM PDT 24
Peak memory 213720 kb
Host smart-86a719fe-65c2-417f-99ef-b647ca9063db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778807141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2778807141
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2526059687
Short name T130
Test name
Test status
Simulation time 26956114743 ps
CPU time 210.23 seconds
Started Aug 19 04:26:28 PM PDT 24
Finished Aug 19 04:29:58 PM PDT 24
Peak memory 224852 kb
Host smart-568198ef-a0c0-4862-8d9f-84249dea7caf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526059687 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2526059687
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1582188642
Short name T275
Test name
Test status
Simulation time 114935155 ps
CPU time 4.02 seconds
Started Aug 19 04:26:37 PM PDT 24
Finished Aug 19 04:26:41 PM PDT 24
Peak memory 210984 kb
Host smart-bf7d4e00-f556-4f7d-afdf-36ba84c70998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582188642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1582188642
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3831322290
Short name T182
Test name
Test status
Simulation time 4971363540 ps
CPU time 65.93 seconds
Started Aug 19 04:26:33 PM PDT 24
Finished Aug 19 04:27:39 PM PDT 24
Peak memory 236532 kb
Host smart-39ecb708-28e5-4244-a6f7-e10caaa5c066
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831322290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3831322290
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1687733674
Short name T248
Test name
Test status
Simulation time 1035747851 ps
CPU time 10.95 seconds
Started Aug 19 04:26:55 PM PDT 24
Finished Aug 19 04:27:06 PM PDT 24
Peak memory 211492 kb
Host smart-9fb01000-b8d6-405e-a5f5-7175ec4ead70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687733674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1687733674
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.4193973505
Short name T34
Test name
Test status
Simulation time 143360618 ps
CPU time 6.22 seconds
Started Aug 19 04:26:28 PM PDT 24
Finished Aug 19 04:26:34 PM PDT 24
Peak memory 210968 kb
Host smart-a7eaa985-d9ff-406e-b402-ab73c210bdb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4193973505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.4193973505
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2148793232
Short name T13
Test name
Test status
Simulation time 104030774 ps
CPU time 5.3 seconds
Started Aug 19 04:26:49 PM PDT 24
Finished Aug 19 04:26:55 PM PDT 24
Peak memory 212028 kb
Host smart-d1b600b1-47a7-4b38-9164-b4ee4363de4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148793232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2148793232
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3826901385
Short name T337
Test name
Test status
Simulation time 224669439 ps
CPU time 12.02 seconds
Started Aug 19 04:26:25 PM PDT 24
Finished Aug 19 04:26:37 PM PDT 24
Peak memory 214908 kb
Host smart-4ccdf42c-301f-4d0e-8161-414a028dcd7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826901385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3826901385
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2360580889
Short name T221
Test name
Test status
Simulation time 10543034939 ps
CPU time 139.58 seconds
Started Aug 19 04:26:29 PM PDT 24
Finished Aug 19 04:28:49 PM PDT 24
Peak memory 222668 kb
Host smart-8d71d359-e43d-4ae1-9c48-30046f34b60e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360580889 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.2360580889
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.990004818
Short name T57
Test name
Test status
Simulation time 1127330734 ps
CPU time 4.67 seconds
Started Aug 19 04:26:28 PM PDT 24
Finished Aug 19 04:26:33 PM PDT 24
Peak memory 210960 kb
Host smart-bb7b40af-3945-40b0-bc43-970d3f29ca23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990004818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.990004818
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2694393569
Short name T159
Test name
Test status
Simulation time 5281109186 ps
CPU time 119.42 seconds
Started Aug 19 04:27:00 PM PDT 24
Finished Aug 19 04:28:59 PM PDT 24
Peak memory 233404 kb
Host smart-6cc3f636-ec32-4e65-a330-2254b101b1a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694393569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2694393569
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1700236231
Short name T305
Test name
Test status
Simulation time 175564034 ps
CPU time 8.8 seconds
Started Aug 19 04:26:48 PM PDT 24
Finished Aug 19 04:26:57 PM PDT 24
Peak memory 211392 kb
Host smart-3ef0f218-2fc0-4975-bdbe-0b0636d975ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700236231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1700236231
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2528033787
Short name T207
Test name
Test status
Simulation time 276283861 ps
CPU time 5.99 seconds
Started Aug 19 04:26:22 PM PDT 24
Finished Aug 19 04:26:28 PM PDT 24
Peak memory 211004 kb
Host smart-7f55f5b4-b898-4b46-8225-14d6062eab38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2528033787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2528033787
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.901807631
Short name T301
Test name
Test status
Simulation time 99445485 ps
CPU time 5.17 seconds
Started Aug 19 04:26:23 PM PDT 24
Finished Aug 19 04:26:29 PM PDT 24
Peak memory 210968 kb
Host smart-53742607-dfb1-4881-a45d-e5dbb1d48bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901807631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.901807631
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3031556002
Short name T59
Test name
Test status
Simulation time 212749055 ps
CPU time 7.54 seconds
Started Aug 19 04:26:22 PM PDT 24
Finished Aug 19 04:26:30 PM PDT 24
Peak memory 212412 kb
Host smart-7c47bef5-8176-4f61-92cc-9017589ce1d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031556002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3031556002
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.92627317
Short name T267
Test name
Test status
Simulation time 3003779210 ps
CPU time 60.72 seconds
Started Aug 19 04:27:01 PM PDT 24
Finished Aug 19 04:28:02 PM PDT 24
Peak memory 219596 kb
Host smart-84ce22f5-de77-41e9-843e-c71e1eaf3907
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92627317 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.92627317
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2723933120
Short name T287
Test name
Test status
Simulation time 127834719 ps
CPU time 4.89 seconds
Started Aug 19 04:26:34 PM PDT 24
Finished Aug 19 04:26:39 PM PDT 24
Peak memory 210992 kb
Host smart-2da2e33e-b61b-4c01-bd81-25b82af42bc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723933120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2723933120
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.260443602
Short name T236
Test name
Test status
Simulation time 9692890104 ps
CPU time 102.68 seconds
Started Aug 19 04:26:21 PM PDT 24
Finished Aug 19 04:28:05 PM PDT 24
Peak memory 213528 kb
Host smart-179d8414-444c-402b-819c-931fedcce5f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260443602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.260443602
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2166484702
Short name T356
Test name
Test status
Simulation time 509344364 ps
CPU time 10.45 seconds
Started Aug 19 04:26:46 PM PDT 24
Finished Aug 19 04:26:56 PM PDT 24
Peak memory 211340 kb
Host smart-5c07d9aa-b54a-44c7-8a3b-3379f95f4175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166484702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2166484702
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2284197690
Short name T183
Test name
Test status
Simulation time 194211717 ps
CPU time 5.6 seconds
Started Aug 19 04:26:44 PM PDT 24
Finished Aug 19 04:26:50 PM PDT 24
Peak memory 211004 kb
Host smart-e1b76a90-76bb-4670-8918-a3875e9aae1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2284197690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2284197690
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1599304197
Short name T244
Test name
Test status
Simulation time 508105824 ps
CPU time 7.34 seconds
Started Aug 19 04:26:21 PM PDT 24
Finished Aug 19 04:26:29 PM PDT 24
Peak memory 210980 kb
Host smart-9cc0e3db-6155-41d8-9691-0ebd87280a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599304197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1599304197
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2866194267
Short name T77
Test name
Test status
Simulation time 598646948 ps
CPU time 6.16 seconds
Started Aug 19 04:26:55 PM PDT 24
Finished Aug 19 04:27:01 PM PDT 24
Peak memory 211256 kb
Host smart-7878e0ef-0f04-48a9-ab47-58d6ee6144b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866194267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2866194267
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.467456278
Short name T242
Test name
Test status
Simulation time 1616406910 ps
CPU time 64.34 seconds
Started Aug 19 04:26:57 PM PDT 24
Finished Aug 19 04:28:01 PM PDT 24
Peak memory 219120 kb
Host smart-a32a40e2-8491-4cde-974e-fe5fc27045cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467456278 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.467456278
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1180807960
Short name T299
Test name
Test status
Simulation time 136513434 ps
CPU time 4.9 seconds
Started Aug 19 04:26:48 PM PDT 24
Finished Aug 19 04:26:53 PM PDT 24
Peak memory 211068 kb
Host smart-f3aa1094-0220-401e-8809-f1bbebf601a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180807960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1180807960
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1132720664
Short name T195
Test name
Test status
Simulation time 13754169272 ps
CPU time 94.04 seconds
Started Aug 19 04:26:51 PM PDT 24
Finished Aug 19 04:28:25 PM PDT 24
Peak memory 236928 kb
Host smart-c001ed6b-d59a-4253-b14b-48473f2e739d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132720664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1132720664
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2269568001
Short name T43
Test name
Test status
Simulation time 199903328 ps
CPU time 8.86 seconds
Started Aug 19 04:26:49 PM PDT 24
Finished Aug 19 04:26:58 PM PDT 24
Peak memory 211492 kb
Host smart-58e90572-37ac-4faf-9047-cee9b5d72315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269568001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2269568001
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2774839795
Short name T136
Test name
Test status
Simulation time 135909766 ps
CPU time 5.98 seconds
Started Aug 19 04:26:31 PM PDT 24
Finished Aug 19 04:26:37 PM PDT 24
Peak memory 210992 kb
Host smart-0a41f99c-e97f-4afe-9739-0e1dd62e8bef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2774839795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2774839795
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2239542326
Short name T198
Test name
Test status
Simulation time 595462868 ps
CPU time 5.38 seconds
Started Aug 19 04:26:38 PM PDT 24
Finished Aug 19 04:26:43 PM PDT 24
Peak memory 212592 kb
Host smart-61d1903f-6480-463d-82d0-7b6946cdebf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239542326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2239542326
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.354894882
Short name T165
Test name
Test status
Simulation time 283056272 ps
CPU time 13.51 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:34 PM PDT 24
Peak memory 214624 kb
Host smart-a65a6f84-17e0-4b9d-a568-c2724e27ec4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354894882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.354894882
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.919873205
Short name T292
Test name
Test status
Simulation time 9572613808 ps
CPU time 135.16 seconds
Started Aug 19 04:26:21 PM PDT 24
Finished Aug 19 04:28:36 PM PDT 24
Peak memory 223040 kb
Host smart-89e0a851-e883-43e0-9807-5feb87ec7875
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919873205 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.919873205
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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