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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.48 96.97 92.87 97.88 100.00 98.37 97.89 98.37


Total test records in report: 457
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T300 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1600101314 Apr 21 12:45:57 PM PDT 24 Apr 21 12:48:58 PM PDT 24 2342649147 ps
T301 /workspace/coverage/default/15.rom_ctrl_alert_test.361056354 Apr 21 12:45:36 PM PDT 24 Apr 21 12:46:03 PM PDT 24 3188541036 ps
T302 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1617352560 Apr 21 12:45:21 PM PDT 24 Apr 21 12:53:37 PM PDT 24 48988007609 ps
T303 /workspace/coverage/default/14.rom_ctrl_alert_test.4019587549 Apr 21 12:45:28 PM PDT 24 Apr 21 12:45:54 PM PDT 24 5595665877 ps
T304 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3120719187 Apr 21 12:45:41 PM PDT 24 Apr 21 12:51:03 PM PDT 24 85376522241 ps
T305 /workspace/coverage/default/4.rom_ctrl_stress_all.1865800249 Apr 21 12:45:20 PM PDT 24 Apr 21 12:45:33 PM PDT 24 479338884 ps
T306 /workspace/coverage/default/1.rom_ctrl_stress_all.364051287 Apr 21 12:45:26 PM PDT 24 Apr 21 12:45:44 PM PDT 24 377841908 ps
T307 /workspace/coverage/default/41.rom_ctrl_stress_all.3343401058 Apr 21 12:46:00 PM PDT 24 Apr 21 12:46:41 PM PDT 24 33010959309 ps
T308 /workspace/coverage/default/22.rom_ctrl_alert_test.2513873693 Apr 21 12:45:30 PM PDT 24 Apr 21 12:45:51 PM PDT 24 1952237966 ps
T309 /workspace/coverage/default/1.rom_ctrl_smoke.1149405009 Apr 21 12:45:14 PM PDT 24 Apr 21 12:45:35 PM PDT 24 348180445 ps
T310 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.645947309 Apr 21 12:45:56 PM PDT 24 Apr 21 12:46:08 PM PDT 24 353546232 ps
T311 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2971381955 Apr 21 12:45:28 PM PDT 24 Apr 21 12:45:54 PM PDT 24 29005230509 ps
T312 /workspace/coverage/default/39.rom_ctrl_smoke.1291673058 Apr 21 12:45:59 PM PDT 24 Apr 21 12:47:00 PM PDT 24 28141012615 ps
T313 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2870532805 Apr 21 12:45:25 PM PDT 24 Apr 21 12:46:19 PM PDT 24 26739480207 ps
T314 /workspace/coverage/default/30.rom_ctrl_alert_test.2375337949 Apr 21 12:45:32 PM PDT 24 Apr 21 12:45:53 PM PDT 24 1982200286 ps
T315 /workspace/coverage/default/22.rom_ctrl_smoke.3888468509 Apr 21 12:45:45 PM PDT 24 Apr 21 12:47:04 PM PDT 24 15054584758 ps
T316 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.4112013261 Apr 21 12:45:30 PM PDT 24 Apr 21 12:45:41 PM PDT 24 199053716 ps
T317 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.573313572 Apr 21 12:45:22 PM PDT 24 Apr 21 12:45:48 PM PDT 24 10877693530 ps
T318 /workspace/coverage/default/33.rom_ctrl_alert_test.89798002 Apr 21 12:45:46 PM PDT 24 Apr 21 12:46:02 PM PDT 24 1194024411 ps
T319 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.246826439 Apr 21 12:45:57 PM PDT 24 Apr 21 12:46:14 PM PDT 24 754470196 ps
T320 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2024362980 Apr 21 12:45:34 PM PDT 24 Apr 21 12:51:43 PM PDT 24 27833130762 ps
T321 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.157595055 Apr 21 12:45:55 PM PDT 24 Apr 21 12:46:57 PM PDT 24 7937768375 ps
T322 /workspace/coverage/default/26.rom_ctrl_smoke.306915985 Apr 21 12:45:38 PM PDT 24 Apr 21 12:46:36 PM PDT 24 5071186278 ps
T323 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1275400939 Apr 21 12:45:29 PM PDT 24 Apr 21 12:54:38 PM PDT 24 101412244228 ps
T36 /workspace/coverage/default/4.rom_ctrl_sec_cm.2555402189 Apr 21 12:45:10 PM PDT 24 Apr 21 12:47:23 PM PDT 24 11644225906 ps
T324 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3147779119 Apr 21 12:45:50 PM PDT 24 Apr 21 01:02:10 PM PDT 24 51268212286 ps
T325 /workspace/coverage/default/34.rom_ctrl_stress_all.2990135032 Apr 21 12:45:58 PM PDT 24 Apr 21 12:47:20 PM PDT 24 16624151705 ps
T326 /workspace/coverage/default/21.rom_ctrl_stress_all.3216184686 Apr 21 12:45:42 PM PDT 24 Apr 21 12:46:23 PM PDT 24 16466048799 ps
T327 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3223213214 Apr 21 12:45:59 PM PDT 24 Apr 21 12:46:20 PM PDT 24 3373377281 ps
T328 /workspace/coverage/default/40.rom_ctrl_smoke.3754743963 Apr 21 12:46:02 PM PDT 24 Apr 21 12:47:22 PM PDT 24 16131151271 ps
T329 /workspace/coverage/default/24.rom_ctrl_smoke.3909230128 Apr 21 12:45:36 PM PDT 24 Apr 21 12:46:46 PM PDT 24 7658663252 ps
T330 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1376615605 Apr 21 12:45:31 PM PDT 24 Apr 21 12:51:24 PM PDT 24 86872613545 ps
T331 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.972862737 Apr 21 12:45:13 PM PDT 24 Apr 21 12:56:26 PM PDT 24 126376002264 ps
T332 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4062995989 Apr 21 12:45:36 PM PDT 24 Apr 21 12:50:23 PM PDT 24 88693843646 ps
T333 /workspace/coverage/default/35.rom_ctrl_alert_test.3685823825 Apr 21 12:45:43 PM PDT 24 Apr 21 12:46:05 PM PDT 24 3943827266 ps
T334 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2069713300 Apr 21 12:45:59 PM PDT 24 Apr 21 12:52:02 PM PDT 24 127571381471 ps
T335 /workspace/coverage/default/23.rom_ctrl_alert_test.3258203426 Apr 21 12:45:39 PM PDT 24 Apr 21 12:45:58 PM PDT 24 7403844252 ps
T336 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.16261801 Apr 21 12:45:32 PM PDT 24 Apr 21 12:45:57 PM PDT 24 2581731706 ps
T337 /workspace/coverage/default/2.rom_ctrl_stress_all.745194582 Apr 21 12:45:22 PM PDT 24 Apr 21 12:46:33 PM PDT 24 1192012578 ps
T338 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1637370192 Apr 21 12:45:37 PM PDT 24 Apr 21 12:46:10 PM PDT 24 11638939289 ps
T339 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.441597662 Apr 21 12:45:44 PM PDT 24 Apr 21 12:59:27 PM PDT 24 283607563085 ps
T340 /workspace/coverage/default/11.rom_ctrl_smoke.3000490349 Apr 21 12:45:27 PM PDT 24 Apr 21 12:46:31 PM PDT 24 16014795569 ps
T341 /workspace/coverage/default/29.rom_ctrl_stress_all.3072720607 Apr 21 12:45:53 PM PDT 24 Apr 21 12:46:58 PM PDT 24 2803391964 ps
T342 /workspace/coverage/default/27.rom_ctrl_smoke.2476996047 Apr 21 12:45:42 PM PDT 24 Apr 21 12:46:34 PM PDT 24 4623599346 ps
T343 /workspace/coverage/default/45.rom_ctrl_smoke.3058542465 Apr 21 12:46:01 PM PDT 24 Apr 21 12:47:04 PM PDT 24 57325019576 ps
T344 /workspace/coverage/default/3.rom_ctrl_smoke.2917050907 Apr 21 12:45:16 PM PDT 24 Apr 21 12:46:01 PM PDT 24 6930354876 ps
T345 /workspace/coverage/default/18.rom_ctrl_stress_all.2278398653 Apr 21 12:45:45 PM PDT 24 Apr 21 12:46:36 PM PDT 24 9809110043 ps
T346 /workspace/coverage/default/20.rom_ctrl_stress_all.429053896 Apr 21 12:45:34 PM PDT 24 Apr 21 12:45:55 PM PDT 24 3356571222 ps
T347 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1567993797 Apr 21 12:45:28 PM PDT 24 Apr 21 12:45:39 PM PDT 24 358731957 ps
T348 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1167617116 Apr 21 12:46:00 PM PDT 24 Apr 21 12:47:05 PM PDT 24 31440668964 ps
T349 /workspace/coverage/default/41.rom_ctrl_smoke.3022350321 Apr 21 12:45:53 PM PDT 24 Apr 21 12:46:34 PM PDT 24 13106993018 ps
T350 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2097843447 Apr 21 12:45:01 PM PDT 24 Apr 21 12:58:56 PM PDT 24 83901719811 ps
T351 /workspace/coverage/default/38.rom_ctrl_stress_all.1166185069 Apr 21 12:45:47 PM PDT 24 Apr 21 12:46:09 PM PDT 24 1401922736 ps
T352 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1035278068 Apr 21 12:45:45 PM PDT 24 Apr 21 12:46:11 PM PDT 24 2344485616 ps
T353 /workspace/coverage/default/30.rom_ctrl_smoke.2732066338 Apr 21 12:45:59 PM PDT 24 Apr 21 12:46:44 PM PDT 24 56281161613 ps
T354 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2989924122 Apr 21 12:45:43 PM PDT 24 Apr 21 12:56:17 PM PDT 24 480624138930 ps
T355 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3902716409 Apr 21 12:45:45 PM PDT 24 Apr 21 12:46:36 PM PDT 24 5719369662 ps
T356 /workspace/coverage/default/9.rom_ctrl_smoke.2589181448 Apr 21 12:45:20 PM PDT 24 Apr 21 12:46:20 PM PDT 24 6418609105 ps
T357 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3142028086 Apr 21 12:45:38 PM PDT 24 Apr 21 12:51:51 PM PDT 24 5748793777 ps
T358 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1628591912 Apr 21 12:45:28 PM PDT 24 Apr 21 12:45:38 PM PDT 24 357980964 ps
T359 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.4255568609 Apr 21 12:46:04 PM PDT 24 Apr 21 12:46:52 PM PDT 24 17761098018 ps
T360 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.947395993 Apr 21 12:45:58 PM PDT 24 Apr 21 12:55:20 PM PDT 24 31556472540 ps
T76 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1511601628 Apr 21 12:42:40 PM PDT 24 Apr 21 12:43:09 PM PDT 24 13159227234 ps
T77 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1436954872 Apr 21 12:42:38 PM PDT 24 Apr 21 12:42:51 PM PDT 24 687914986 ps
T78 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2564212223 Apr 21 12:42:55 PM PDT 24 Apr 21 12:43:28 PM PDT 24 7668995390 ps
T361 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3589028 Apr 21 12:42:41 PM PDT 24 Apr 21 12:43:13 PM PDT 24 8058265814 ps
T362 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2761154931 Apr 21 12:42:16 PM PDT 24 Apr 21 12:42:39 PM PDT 24 1795566675 ps
T85 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2882756583 Apr 21 12:42:42 PM PDT 24 Apr 21 12:44:50 PM PDT 24 16579087787 ps
T86 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1122576124 Apr 21 12:42:32 PM PDT 24 Apr 21 12:42:47 PM PDT 24 904173255 ps
T87 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2779725755 Apr 21 12:42:53 PM PDT 24 Apr 21 12:43:20 PM PDT 24 28692107409 ps
T363 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1157287866 Apr 21 12:42:37 PM PDT 24 Apr 21 12:42:46 PM PDT 24 722932225 ps
T364 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1961580169 Apr 21 12:42:38 PM PDT 24 Apr 21 12:42:50 PM PDT 24 360691916 ps
T88 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2715091147 Apr 21 12:42:19 PM PDT 24 Apr 21 12:42:48 PM PDT 24 3657021243 ps
T89 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1685740952 Apr 21 12:42:59 PM PDT 24 Apr 21 12:43:11 PM PDT 24 2465836224 ps
T111 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2635065511 Apr 21 12:42:49 PM PDT 24 Apr 21 12:43:14 PM PDT 24 12713222604 ps
T365 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3003631062 Apr 21 12:42:56 PM PDT 24 Apr 21 12:43:34 PM PDT 24 4252801957 ps
T112 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2260686791 Apr 21 12:42:25 PM PDT 24 Apr 21 12:42:48 PM PDT 24 5172710005 ps
T90 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.880513429 Apr 21 12:42:41 PM PDT 24 Apr 21 12:44:47 PM PDT 24 40536837956 ps
T366 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2810572627 Apr 21 12:42:44 PM PDT 24 Apr 21 12:43:02 PM PDT 24 3222700013 ps
T113 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2073514888 Apr 21 12:42:48 PM PDT 24 Apr 21 12:42:56 PM PDT 24 176375484 ps
T367 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2925140508 Apr 21 12:42:37 PM PDT 24 Apr 21 12:43:09 PM PDT 24 9144862267 ps
T71 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2512715986 Apr 21 12:42:39 PM PDT 24 Apr 21 12:44:19 PM PDT 24 3770877263 ps
T368 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2311323952 Apr 21 12:42:38 PM PDT 24 Apr 21 12:43:08 PM PDT 24 43185631016 ps
T114 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1709924077 Apr 21 12:42:52 PM PDT 24 Apr 21 12:43:09 PM PDT 24 1410964131 ps
T91 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.133098661 Apr 21 12:42:53 PM PDT 24 Apr 21 12:44:56 PM PDT 24 10663439861 ps
T92 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1507886444 Apr 21 12:42:58 PM PDT 24 Apr 21 12:44:52 PM PDT 24 65721968944 ps
T72 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3021035805 Apr 21 12:42:53 PM PDT 24 Apr 21 12:45:43 PM PDT 24 18990221205 ps
T115 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2025949780 Apr 21 12:42:52 PM PDT 24 Apr 21 12:43:05 PM PDT 24 187569579 ps
T116 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2221245713 Apr 21 12:42:41 PM PDT 24 Apr 21 12:43:18 PM PDT 24 2832615896 ps
T369 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2895072773 Apr 21 12:42:42 PM PDT 24 Apr 21 12:42:51 PM PDT 24 205632627 ps
T370 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.448636778 Apr 21 12:42:32 PM PDT 24 Apr 21 12:43:00 PM PDT 24 2684362826 ps
T371 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.647119187 Apr 21 12:42:48 PM PDT 24 Apr 21 12:43:12 PM PDT 24 5826834014 ps
T372 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1844322478 Apr 21 12:42:51 PM PDT 24 Apr 21 12:43:30 PM PDT 24 14845081427 ps
T73 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.961689058 Apr 21 12:42:48 PM PDT 24 Apr 21 12:44:10 PM PDT 24 959950032 ps
T373 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1435367090 Apr 21 12:42:48 PM PDT 24 Apr 21 12:44:32 PM PDT 24 7001493104 ps
T374 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.251040162 Apr 21 12:42:45 PM PDT 24 Apr 21 12:43:05 PM PDT 24 7888232081 ps
T375 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3677498624 Apr 21 12:42:43 PM PDT 24 Apr 21 12:43:05 PM PDT 24 4375977518 ps
T376 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2760595377 Apr 21 12:42:23 PM PDT 24 Apr 21 12:42:42 PM PDT 24 1597891726 ps
T118 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2226780522 Apr 21 12:42:27 PM PDT 24 Apr 21 12:44:03 PM PDT 24 2458990231 ps
T377 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.644982522 Apr 21 12:42:52 PM PDT 24 Apr 21 12:43:00 PM PDT 24 174537976 ps
T378 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.741839069 Apr 21 12:42:46 PM PDT 24 Apr 21 12:43:03 PM PDT 24 1501923065 ps
T379 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1628691750 Apr 21 12:42:54 PM PDT 24 Apr 21 12:43:29 PM PDT 24 29512160362 ps
T380 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4178391636 Apr 21 12:42:51 PM PDT 24 Apr 21 12:43:15 PM PDT 24 3844263907 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.371888796 Apr 21 12:42:26 PM PDT 24 Apr 21 12:42:38 PM PDT 24 517292109 ps
T382 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3265235784 Apr 21 12:42:52 PM PDT 24 Apr 21 12:43:06 PM PDT 24 241381721 ps
T125 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2105318493 Apr 21 12:42:47 PM PDT 24 Apr 21 12:44:27 PM PDT 24 3678086222 ps
T383 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4261737751 Apr 21 12:42:47 PM PDT 24 Apr 21 12:43:02 PM PDT 24 835058605 ps
T384 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3116911372 Apr 21 12:42:48 PM PDT 24 Apr 21 12:43:14 PM PDT 24 9251851954 ps
T119 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2954626050 Apr 21 12:42:46 PM PDT 24 Apr 21 12:44:20 PM PDT 24 10083646241 ps
T385 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1663139526 Apr 21 12:43:14 PM PDT 24 Apr 21 12:43:36 PM PDT 24 2683365383 ps
T386 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1877045276 Apr 21 12:42:24 PM PDT 24 Apr 21 12:42:55 PM PDT 24 7667206447 ps
T387 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3514194778 Apr 21 12:42:44 PM PDT 24 Apr 21 12:43:22 PM PDT 24 16385468624 ps
T388 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.248021710 Apr 21 12:42:36 PM PDT 24 Apr 21 12:42:55 PM PDT 24 7885702903 ps
T389 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.608672619 Apr 21 12:42:49 PM PDT 24 Apr 21 12:43:21 PM PDT 24 14919174384 ps
T390 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1534276801 Apr 21 12:42:27 PM PDT 24 Apr 21 12:43:05 PM PDT 24 4406622125 ps
T391 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2254248305 Apr 21 12:42:53 PM PDT 24 Apr 21 12:43:06 PM PDT 24 859865524 ps
T392 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1528597178 Apr 21 12:42:49 PM PDT 24 Apr 21 12:43:12 PM PDT 24 2380404481 ps
T393 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1111000973 Apr 21 12:42:45 PM PDT 24 Apr 21 12:42:59 PM PDT 24 967504890 ps
T128 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.973430826 Apr 21 12:43:05 PM PDT 24 Apr 21 12:44:48 PM PDT 24 8210848019 ps
T97 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2598764399 Apr 21 12:42:47 PM PDT 24 Apr 21 12:44:20 PM PDT 24 9603481613 ps
T394 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1428989499 Apr 21 12:42:19 PM PDT 24 Apr 21 12:42:28 PM PDT 24 661569338 ps
T122 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3837144376 Apr 21 12:42:41 PM PDT 24 Apr 21 12:44:04 PM PDT 24 326467383 ps
T395 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4035325842 Apr 21 12:42:41 PM PDT 24 Apr 21 12:42:59 PM PDT 24 15636981411 ps
T396 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2556463908 Apr 21 12:42:56 PM PDT 24 Apr 21 12:43:20 PM PDT 24 10803097054 ps
T397 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1994800520 Apr 21 12:42:32 PM PDT 24 Apr 21 12:43:02 PM PDT 24 15081521970 ps
T398 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1391108095 Apr 21 12:42:39 PM PDT 24 Apr 21 12:45:52 PM PDT 24 147656586008 ps
T399 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1120034589 Apr 21 12:42:44 PM PDT 24 Apr 21 12:43:05 PM PDT 24 10584858574 ps
T400 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2772307113 Apr 21 12:42:36 PM PDT 24 Apr 21 12:44:34 PM PDT 24 98578150265 ps
T401 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1875804196 Apr 21 12:42:36 PM PDT 24 Apr 21 12:42:44 PM PDT 24 688197265 ps
T98 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1677114566 Apr 21 12:42:46 PM PDT 24 Apr 21 12:42:55 PM PDT 24 612419009 ps
T402 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1259945951 Apr 21 12:42:36 PM PDT 24 Apr 21 12:42:58 PM PDT 24 2061945945 ps
T403 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4256471205 Apr 21 12:42:37 PM PDT 24 Apr 21 12:42:46 PM PDT 24 665095235 ps
T404 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1066341906 Apr 21 12:42:53 PM PDT 24 Apr 21 12:43:11 PM PDT 24 1444381177 ps
T99 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3039941261 Apr 21 12:42:38 PM PDT 24 Apr 21 12:43:03 PM PDT 24 5758337031 ps
T405 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.377150065 Apr 21 12:42:46 PM PDT 24 Apr 21 12:43:07 PM PDT 24 2089901152 ps
T406 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4110988378 Apr 21 12:42:53 PM PDT 24 Apr 21 12:43:03 PM PDT 24 1064837163 ps
T407 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.386746318 Apr 21 12:42:35 PM PDT 24 Apr 21 12:43:13 PM PDT 24 8626278913 ps
T408 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4067696479 Apr 21 12:42:52 PM PDT 24 Apr 21 12:43:00 PM PDT 24 436423817 ps
T126 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1528670456 Apr 21 12:43:00 PM PDT 24 Apr 21 12:45:59 PM PDT 24 15163510303 ps
T120 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.999239886 Apr 21 12:42:48 PM PDT 24 Apr 21 12:44:10 PM PDT 24 867906297 ps
T100 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2208680044 Apr 21 12:42:16 PM PDT 24 Apr 21 12:42:42 PM PDT 24 6893272136 ps
T101 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1499145563 Apr 21 12:42:38 PM PDT 24 Apr 21 12:43:10 PM PDT 24 9761987586 ps
T409 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2810512944 Apr 21 12:42:48 PM PDT 24 Apr 21 12:43:18 PM PDT 24 11125664445 ps
T410 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4228788898 Apr 21 12:42:35 PM PDT 24 Apr 21 12:42:55 PM PDT 24 1979408197 ps
T411 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3090635995 Apr 21 12:42:17 PM PDT 24 Apr 21 12:42:34 PM PDT 24 1427638534 ps
T412 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1302920849 Apr 21 12:42:48 PM PDT 24 Apr 21 12:43:20 PM PDT 24 16217016700 ps
T123 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4080167271 Apr 21 12:42:34 PM PDT 24 Apr 21 12:45:08 PM PDT 24 1211317318 ps
T413 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3706368158 Apr 21 12:42:41 PM PDT 24 Apr 21 12:43:07 PM PDT 24 11963067590 ps
T414 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3853852175 Apr 21 12:42:48 PM PDT 24 Apr 21 12:43:18 PM PDT 24 3585378679 ps
T415 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2159923225 Apr 21 12:42:51 PM PDT 24 Apr 21 12:42:59 PM PDT 24 181945201 ps
T416 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1844572685 Apr 21 12:42:31 PM PDT 24 Apr 21 12:42:53 PM PDT 24 2207802802 ps
T129 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.412601133 Apr 21 12:42:55 PM PDT 24 Apr 21 12:45:43 PM PDT 24 8336198919 ps
T417 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.684815596 Apr 21 12:42:46 PM PDT 24 Apr 21 12:43:15 PM PDT 24 5047633731 ps
T418 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.514571063 Apr 21 12:42:47 PM PDT 24 Apr 21 12:43:11 PM PDT 24 4938434193 ps
T419 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1623760966 Apr 21 12:42:41 PM PDT 24 Apr 21 12:42:58 PM PDT 24 2733224047 ps
T420 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1401637517 Apr 21 12:42:17 PM PDT 24 Apr 21 12:42:48 PM PDT 24 16024795182 ps
T421 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2449012108 Apr 21 12:42:50 PM PDT 24 Apr 21 12:43:17 PM PDT 24 5438186575 ps
T109 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2020997088 Apr 21 12:42:19 PM PDT 24 Apr 21 12:43:40 PM PDT 24 7252712828 ps
T422 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2017021971 Apr 21 12:42:55 PM PDT 24 Apr 21 12:45:04 PM PDT 24 49407468557 ps
T423 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1369766759 Apr 21 12:42:41 PM PDT 24 Apr 21 12:43:02 PM PDT 24 1964005485 ps
T424 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.447728229 Apr 21 12:42:57 PM PDT 24 Apr 21 12:44:54 PM PDT 24 156439834361 ps
T425 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1458977311 Apr 21 12:42:33 PM PDT 24 Apr 21 12:43:06 PM PDT 24 15942231296 ps
T110 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2002138567 Apr 21 12:43:04 PM PDT 24 Apr 21 12:44:38 PM PDT 24 17735606749 ps
T121 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.471580857 Apr 21 12:42:32 PM PDT 24 Apr 21 12:43:54 PM PDT 24 401470497 ps
T426 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2672219482 Apr 21 12:42:57 PM PDT 24 Apr 21 12:43:23 PM PDT 24 11411791918 ps
T103 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.520701324 Apr 21 12:42:51 PM PDT 24 Apr 21 12:45:16 PM PDT 24 14487997844 ps
T127 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3402964620 Apr 21 12:43:00 PM PDT 24 Apr 21 12:44:43 PM PDT 24 4233103618 ps
T427 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1856445486 Apr 21 12:42:52 PM PDT 24 Apr 21 12:43:12 PM PDT 24 2331796321 ps
T428 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2889661627 Apr 21 12:42:32 PM PDT 24 Apr 21 12:43:02 PM PDT 24 3736755072 ps
T429 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3632379611 Apr 21 12:42:50 PM PDT 24 Apr 21 12:43:04 PM PDT 24 3080564188 ps
T430 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3894229762 Apr 21 12:42:52 PM PDT 24 Apr 21 12:43:23 PM PDT 24 4698706414 ps
T431 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.438368303 Apr 21 12:42:30 PM PDT 24 Apr 21 12:42:56 PM PDT 24 4780791843 ps
T432 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.986694387 Apr 21 12:43:06 PM PDT 24 Apr 21 12:44:37 PM PDT 24 39353049774 ps
T433 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3011162091 Apr 21 12:42:37 PM PDT 24 Apr 21 12:42:52 PM PDT 24 392145474 ps
T434 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2813629826 Apr 21 12:42:46 PM PDT 24 Apr 21 12:43:25 PM PDT 24 694512071 ps
T104 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3998409404 Apr 21 12:42:40 PM PDT 24 Apr 21 12:42:56 PM PDT 24 244995781 ps
T435 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.635841304 Apr 21 12:43:02 PM PDT 24 Apr 21 12:43:37 PM PDT 24 3694214322 ps
T436 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1006022386 Apr 21 12:42:44 PM PDT 24 Apr 21 12:43:07 PM PDT 24 11087653444 ps
T437 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3371820576 Apr 21 12:42:45 PM PDT 24 Apr 21 12:45:26 PM PDT 24 4385278086 ps
T438 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3833110183 Apr 21 12:42:51 PM PDT 24 Apr 21 12:43:12 PM PDT 24 1234222362 ps
T439 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.536354116 Apr 21 12:42:39 PM PDT 24 Apr 21 12:43:36 PM PDT 24 2075419477 ps
T105 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4251913087 Apr 21 12:42:27 PM PDT 24 Apr 21 12:42:48 PM PDT 24 2143886398 ps
T131 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.340293267 Apr 21 12:42:31 PM PDT 24 Apr 21 12:44:11 PM PDT 24 12750356960 ps
T440 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.990603160 Apr 21 12:42:39 PM PDT 24 Apr 21 12:42:48 PM PDT 24 344414529 ps
T130 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2142791581 Apr 21 12:42:47 PM PDT 24 Apr 21 12:45:37 PM PDT 24 12372110034 ps
T441 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.427944856 Apr 21 12:42:54 PM PDT 24 Apr 21 12:43:12 PM PDT 24 2970425948 ps
T442 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2259763206 Apr 21 12:42:58 PM PDT 24 Apr 21 12:44:48 PM PDT 24 15609223269 ps
T443 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1678069962 Apr 21 12:42:55 PM PDT 24 Apr 21 12:43:05 PM PDT 24 497515145 ps
T444 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1322558956 Apr 21 12:42:32 PM PDT 24 Apr 21 12:42:41 PM PDT 24 331770281 ps
T445 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.295055276 Apr 21 12:42:39 PM PDT 24 Apr 21 12:43:02 PM PDT 24 4984325466 ps
T446 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3069042789 Apr 21 12:42:55 PM PDT 24 Apr 21 12:43:04 PM PDT 24 1048332526 ps
T102 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2207586343 Apr 21 12:42:44 PM PDT 24 Apr 21 12:43:20 PM PDT 24 9435816386 ps
T447 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2006059104 Apr 21 12:42:20 PM PDT 24 Apr 21 12:42:44 PM PDT 24 5092057746 ps
T106 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3908954609 Apr 21 12:43:16 PM PDT 24 Apr 21 12:43:24 PM PDT 24 1831878863 ps
T448 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.678682717 Apr 21 12:42:55 PM PDT 24 Apr 21 12:43:28 PM PDT 24 8678846430 ps
T449 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3081880530 Apr 21 12:42:59 PM PDT 24 Apr 21 12:43:26 PM PDT 24 10855585213 ps
T450 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.404967472 Apr 21 12:42:33 PM PDT 24 Apr 21 12:43:02 PM PDT 24 7186636416 ps
T451 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3475947635 Apr 21 12:42:42 PM PDT 24 Apr 21 12:44:21 PM PDT 24 44780078999 ps
T452 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1945954261 Apr 21 12:42:55 PM PDT 24 Apr 21 12:44:40 PM PDT 24 38697581948 ps
T107 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1266682026 Apr 21 12:42:46 PM PDT 24 Apr 21 12:43:00 PM PDT 24 872162990 ps
T124 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3593040126 Apr 21 12:42:51 PM PDT 24 Apr 21 12:45:27 PM PDT 24 1079962414 ps
T453 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.253035413 Apr 21 12:42:54 PM PDT 24 Apr 21 12:45:50 PM PDT 24 4104456616 ps
T454 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4125181975 Apr 21 12:43:06 PM PDT 24 Apr 21 12:43:33 PM PDT 24 6220591664 ps
T455 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2485221457 Apr 21 12:42:43 PM PDT 24 Apr 21 12:43:11 PM PDT 24 6499050800 ps
T456 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.134061185 Apr 21 12:42:48 PM PDT 24 Apr 21 12:43:01 PM PDT 24 927662307 ps
T108 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2223635279 Apr 21 12:42:29 PM PDT 24 Apr 21 12:42:44 PM PDT 24 4119093198 ps
T457 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4265512058 Apr 21 12:42:40 PM PDT 24 Apr 21 12:42:55 PM PDT 24 431756049 ps

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2306606052
Short name T6
Test name
Test status
Simulation time 11553283368 ps
CPU time 121.4 seconds
Started Apr 21 12:46:04 PM PDT 24
Finished Apr 21 12:48:07 PM PDT 24
Peak memory 221536 kb
Host smart-3078f10b-7673-40a2-8efa-1a686c919442
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306606052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2306606052
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3736650597
Short name T27
Test name
Test status
Simulation time 50263502513 ps
CPU time 403.35 seconds
Started Apr 21 12:45:11 PM PDT 24
Finished Apr 21 12:51:55 PM PDT 24
Peak memory 240032 kb
Host smart-13ff9112-58ff-4035-964b-b714418a89a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736650597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3736650597
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3544477744
Short name T16
Test name
Test status
Simulation time 153400410371 ps
CPU time 1643.03 seconds
Started Apr 21 12:45:07 PM PDT 24
Finished Apr 21 01:12:31 PM PDT 24
Peak memory 249996 kb
Host smart-da100482-285d-4de6-8e00-b5cd6ac0f0a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544477744 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3544477744
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.236744596
Short name T11
Test name
Test status
Simulation time 6594016978 ps
CPU time 42.31 seconds
Started Apr 21 12:45:59 PM PDT 24
Finished Apr 21 12:46:43 PM PDT 24
Peak memory 218524 kb
Host smart-4429a49e-f7f4-4f25-9d9a-f8ac346270c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236744596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.236744596
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.4238680994
Short name T13
Test name
Test status
Simulation time 723918779 ps
CPU time 10.56 seconds
Started Apr 21 12:45:50 PM PDT 24
Finished Apr 21 12:46:02 PM PDT 24
Peak memory 213196 kb
Host smart-89ffa466-2cc0-4d1a-892f-d6174a8db668
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4238680994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.4238680994
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2559785810
Short name T81
Test name
Test status
Simulation time 5045045823 ps
CPU time 24.16 seconds
Started Apr 21 12:45:03 PM PDT 24
Finished Apr 21 12:45:28 PM PDT 24
Peak memory 212852 kb
Host smart-498cda4d-d3f6-4479-886d-e01a329bea4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559785810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2559785810
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3021035805
Short name T72
Test name
Test status
Simulation time 18990221205 ps
CPU time 170 seconds
Started Apr 21 12:42:53 PM PDT 24
Finished Apr 21 12:45:43 PM PDT 24
Peak memory 213784 kb
Host smart-39aa0b4f-7d75-4871-b48a-b844564249b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021035805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3021035805
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4040519129
Short name T29
Test name
Test status
Simulation time 3608013397 ps
CPU time 268.31 seconds
Started Apr 21 12:45:57 PM PDT 24
Finished Apr 21 12:50:27 PM PDT 24
Peak memory 226196 kb
Host smart-4b435084-b22b-4b06-99c3-0f0cac3b9319
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040519129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4040519129
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1649408753
Short name T45
Test name
Test status
Simulation time 702939892 ps
CPU time 10.35 seconds
Started Apr 21 12:45:36 PM PDT 24
Finished Apr 21 12:45:47 PM PDT 24
Peak memory 213140 kb
Host smart-4e1adae9-f9d1-4663-ab0b-5127784bb358
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1649408753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1649408753
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1852051258
Short name T75
Test name
Test status
Simulation time 706646782 ps
CPU time 43.35 seconds
Started Apr 21 12:45:53 PM PDT 24
Finished Apr 21 12:46:38 PM PDT 24
Peak memory 219832 kb
Host smart-8bcd2e59-a697-4d74-bbf7-967b0d908ba9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852051258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1852051258
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1915747506
Short name T34
Test name
Test status
Simulation time 714003256 ps
CPU time 230.13 seconds
Started Apr 21 12:45:10 PM PDT 24
Finished Apr 21 12:49:01 PM PDT 24
Peak memory 238576 kb
Host smart-ead28f2d-1860-4c70-a411-1fb6a39807ee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915747506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1915747506
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.961689058
Short name T73
Test name
Test status
Simulation time 959950032 ps
CPU time 80.92 seconds
Started Apr 21 12:42:48 PM PDT 24
Finished Apr 21 12:44:10 PM PDT 24
Peak memory 213152 kb
Host smart-4a4adace-631a-407d-893a-b3dfe84831cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961689058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.961689058
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2715091147
Short name T88
Test name
Test status
Simulation time 3657021243 ps
CPU time 29.03 seconds
Started Apr 21 12:42:19 PM PDT 24
Finished Apr 21 12:42:48 PM PDT 24
Peak memory 211172 kb
Host smart-025d7267-4659-40d7-965e-6548c64e1475
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715091147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2715091147
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2020997088
Short name T109
Test name
Test status
Simulation time 7252712828 ps
CPU time 80.43 seconds
Started Apr 21 12:42:19 PM PDT 24
Finished Apr 21 12:43:40 PM PDT 24
Peak memory 215120 kb
Host smart-16a226a4-0d70-4fb6-81ca-a574997048f1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020997088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2020997088
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2823696588
Short name T15
Test name
Test status
Simulation time 150966769144 ps
CPU time 64.36 seconds
Started Apr 21 12:45:39 PM PDT 24
Finished Apr 21 12:46:45 PM PDT 24
Peak memory 214516 kb
Host smart-80a56d0c-8357-4427-b951-7949284c733f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823696588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2823696588
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1377937679
Short name T164
Test name
Test status
Simulation time 1319277752 ps
CPU time 19.53 seconds
Started Apr 21 12:45:55 PM PDT 24
Finished Apr 21 12:46:16 PM PDT 24
Peak memory 215112 kb
Host smart-22d9bbac-614b-4130-a755-7d5d9c4e9d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377937679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1377937679
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1528670456
Short name T126
Test name
Test status
Simulation time 15163510303 ps
CPU time 174.04 seconds
Started Apr 21 12:43:00 PM PDT 24
Finished Apr 21 12:45:59 PM PDT 24
Peak memory 219004 kb
Host smart-f7b936aa-c000-42cc-b8b0-9cff0deda1ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528670456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1528670456
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1507886444
Short name T92
Test name
Test status
Simulation time 65721968944 ps
CPU time 113.48 seconds
Started Apr 21 12:42:58 PM PDT 24
Finished Apr 21 12:44:52 PM PDT 24
Peak memory 214004 kb
Host smart-48eac948-d882-4ef4-9702-3dd7241fea7f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507886444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1507886444
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3593040126
Short name T124
Test name
Test status
Simulation time 1079962414 ps
CPU time 155.81 seconds
Started Apr 21 12:42:51 PM PDT 24
Finished Apr 21 12:45:27 PM PDT 24
Peak memory 213524 kb
Host smart-78b6b708-9e40-434c-8d08-d03c1085876f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593040126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3593040126
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2355196891
Short name T141
Test name
Test status
Simulation time 2035445152 ps
CPU time 22.8 seconds
Started Apr 21 12:45:34 PM PDT 24
Finished Apr 21 12:45:57 PM PDT 24
Peak memory 217708 kb
Host smart-d2318a00-cae1-46d4-8578-167d4a2b7e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355196891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2355196891
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.406738298
Short name T153
Test name
Test status
Simulation time 13030192237 ps
CPU time 26.16 seconds
Started Apr 21 12:45:28 PM PDT 24
Finished Apr 21 12:45:54 PM PDT 24
Peak memory 212956 kb
Host smart-e2e6430a-cc56-4f8d-af8e-39ca32955285
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406738298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.406738298
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1122576124
Short name T86
Test name
Test status
Simulation time 904173255 ps
CPU time 14.41 seconds
Started Apr 21 12:42:32 PM PDT 24
Finished Apr 21 12:42:47 PM PDT 24
Peak memory 210860 kb
Host smart-54805366-9bf4-45cc-a0e6-8553f9f59ae5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122576124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1122576124
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2889661627
Short name T428
Test name
Test status
Simulation time 3736755072 ps
CPU time 29.51 seconds
Started Apr 21 12:42:32 PM PDT 24
Finished Apr 21 12:43:02 PM PDT 24
Peak memory 219020 kb
Host smart-f818a1d2-dfde-4dcd-b115-a4eb21f6e672
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889661627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2889661627
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2208680044
Short name T100
Test name
Test status
Simulation time 6893272136 ps
CPU time 25.73 seconds
Started Apr 21 12:42:16 PM PDT 24
Finished Apr 21 12:42:42 PM PDT 24
Peak memory 212036 kb
Host smart-4775d9dc-7b60-4c53-9524-ec9a9b132067
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208680044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2208680044
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2760595377
Short name T376
Test name
Test status
Simulation time 1597891726 ps
CPU time 18.23 seconds
Started Apr 21 12:42:23 PM PDT 24
Finished Apr 21 12:42:42 PM PDT 24
Peak memory 215956 kb
Host smart-cfd74d53-933d-46e1-ae9a-5511219faff2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760595377 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2760595377
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2449012108
Short name T421
Test name
Test status
Simulation time 5438186575 ps
CPU time 26.65 seconds
Started Apr 21 12:42:50 PM PDT 24
Finished Apr 21 12:43:17 PM PDT 24
Peak memory 210860 kb
Host smart-f062f637-c685-4d55-b9d8-3b1504690d99
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449012108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2449012108
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3090635995
Short name T411
Test name
Test status
Simulation time 1427638534 ps
CPU time 17.16 seconds
Started Apr 21 12:42:17 PM PDT 24
Finished Apr 21 12:42:34 PM PDT 24
Peak memory 210848 kb
Host smart-85a9109f-2a84-47d7-b737-75502d590a34
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090635995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3090635995
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2259763206
Short name T442
Test name
Test status
Simulation time 15609223269 ps
CPU time 110.31 seconds
Started Apr 21 12:42:58 PM PDT 24
Finished Apr 21 12:44:48 PM PDT 24
Peak memory 219096 kb
Host smart-d9a752bc-3805-48b7-af82-fbf08bb4bccc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259763206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2259763206
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1458977311
Short name T425
Test name
Test status
Simulation time 15942231296 ps
CPU time 31.75 seconds
Started Apr 21 12:42:33 PM PDT 24
Finished Apr 21 12:43:06 PM PDT 24
Peak memory 211808 kb
Host smart-ef3b4307-5602-433a-967e-c11cc79663b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458977311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1458977311
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1623760966
Short name T419
Test name
Test status
Simulation time 2733224047 ps
CPU time 16.63 seconds
Started Apr 21 12:42:41 PM PDT 24
Finished Apr 21 12:42:58 PM PDT 24
Peak memory 217872 kb
Host smart-d9fc4d5b-73b4-46f3-932f-41032c9a6561
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623760966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1623760966
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2954626050
Short name T119
Test name
Test status
Simulation time 10083646241 ps
CPU time 93.55 seconds
Started Apr 21 12:42:46 PM PDT 24
Finished Apr 21 12:44:20 PM PDT 24
Peak memory 213504 kb
Host smart-f05f7706-c21f-4380-9850-603973ea291a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954626050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2954626050
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2564212223
Short name T78
Test name
Test status
Simulation time 7668995390 ps
CPU time 27.33 seconds
Started Apr 21 12:42:55 PM PDT 24
Finished Apr 21 12:43:28 PM PDT 24
Peak memory 211304 kb
Host smart-5aa79708-931e-4901-8ac7-a9eab8897741
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564212223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2564212223
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1436954872
Short name T77
Test name
Test status
Simulation time 687914986 ps
CPU time 8.23 seconds
Started Apr 21 12:42:38 PM PDT 24
Finished Apr 21 12:42:51 PM PDT 24
Peak memory 210832 kb
Host smart-c54e5e60-cd18-4bdf-8caf-f71083aee1c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436954872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1436954872
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3998409404
Short name T104
Test name
Test status
Simulation time 244995781 ps
CPU time 15.52 seconds
Started Apr 21 12:42:40 PM PDT 24
Finished Apr 21 12:42:56 PM PDT 24
Peak memory 211724 kb
Host smart-69f588ab-e144-4afb-bf1e-6e9c44bf5ff6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998409404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3998409404
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1157287866
Short name T363
Test name
Test status
Simulation time 722932225 ps
CPU time 8.6 seconds
Started Apr 21 12:42:37 PM PDT 24
Finished Apr 21 12:42:46 PM PDT 24
Peak memory 215516 kb
Host smart-be0ad561-3563-418c-bc82-48c912ca44ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157287866 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1157287866
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4251913087
Short name T105
Test name
Test status
Simulation time 2143886398 ps
CPU time 21.1 seconds
Started Apr 21 12:42:27 PM PDT 24
Finished Apr 21 12:42:48 PM PDT 24
Peak memory 211156 kb
Host smart-7d90d6bf-3370-447a-adf1-9c4759247ee1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251913087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4251913087
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1322558956
Short name T444
Test name
Test status
Simulation time 331770281 ps
CPU time 8.11 seconds
Started Apr 21 12:42:32 PM PDT 24
Finished Apr 21 12:42:41 PM PDT 24
Peak memory 210656 kb
Host smart-831253c6-2f64-47e7-98ac-76a90848079a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322558956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1322558956
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1877045276
Short name T386
Test name
Test status
Simulation time 7667206447 ps
CPU time 30.06 seconds
Started Apr 21 12:42:24 PM PDT 24
Finished Apr 21 12:42:55 PM PDT 24
Peak memory 210876 kb
Host smart-998663b9-c473-40f1-a7ef-4554a02e04b5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877045276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1877045276
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1511601628
Short name T76
Test name
Test status
Simulation time 13159227234 ps
CPU time 28.5 seconds
Started Apr 21 12:42:40 PM PDT 24
Finished Apr 21 12:43:09 PM PDT 24
Peak memory 212096 kb
Host smart-7db34935-efc7-4043-98fe-a856822ec93e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511601628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1511601628
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.438368303
Short name T431
Test name
Test status
Simulation time 4780791843 ps
CPU time 25.5 seconds
Started Apr 21 12:42:30 PM PDT 24
Finished Apr 21 12:42:56 PM PDT 24
Peak memory 219200 kb
Host smart-61675b69-3486-486f-9d44-344dd8728755
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438368303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.438368303
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.999239886
Short name T120
Test name
Test status
Simulation time 867906297 ps
CPU time 81.87 seconds
Started Apr 21 12:42:48 PM PDT 24
Finished Apr 21 12:44:10 PM PDT 24
Peak memory 212872 kb
Host smart-79763ecc-ecc7-4319-9283-536806dec189
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999239886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.999239886
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.377150065
Short name T405
Test name
Test status
Simulation time 2089901152 ps
CPU time 21.36 seconds
Started Apr 21 12:42:46 PM PDT 24
Finished Apr 21 12:43:07 PM PDT 24
Peak memory 216780 kb
Host smart-cc7b43c2-fb60-4ac4-b727-20fc4d3ee22b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377150065 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.377150065
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1066341906
Short name T404
Test name
Test status
Simulation time 1444381177 ps
CPU time 17.15 seconds
Started Apr 21 12:42:53 PM PDT 24
Finished Apr 21 12:43:11 PM PDT 24
Peak memory 211472 kb
Host smart-0e6dcb21-abe7-428f-84ed-21612aad52b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066341906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1066341906
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2017021971
Short name T422
Test name
Test status
Simulation time 49407468557 ps
CPU time 128.19 seconds
Started Apr 21 12:42:55 PM PDT 24
Finished Apr 21 12:45:04 PM PDT 24
Peak memory 219036 kb
Host smart-b20bb457-e492-4667-b135-9776a176b111
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017021971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2017021971
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.134061185
Short name T456
Test name
Test status
Simulation time 927662307 ps
CPU time 12.37 seconds
Started Apr 21 12:42:48 PM PDT 24
Finished Apr 21 12:43:01 PM PDT 24
Peak memory 211004 kb
Host smart-2608b104-e876-4770-a35b-28bb34d92f39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134061185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.134061185
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3003631062
Short name T365
Test name
Test status
Simulation time 4252801957 ps
CPU time 37.08 seconds
Started Apr 21 12:42:56 PM PDT 24
Finished Apr 21 12:43:34 PM PDT 24
Peak memory 217124 kb
Host smart-83c2b7bc-08e5-4ae6-b1c0-9a1c7733b09b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003631062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3003631062
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2105318493
Short name T125
Test name
Test status
Simulation time 3678086222 ps
CPU time 99.9 seconds
Started Apr 21 12:42:47 PM PDT 24
Finished Apr 21 12:44:27 PM PDT 24
Peak memory 212660 kb
Host smart-1e82274f-ef18-40b9-95ca-7ea44ba03fb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105318493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2105318493
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4035325842
Short name T395
Test name
Test status
Simulation time 15636981411 ps
CPU time 17.57 seconds
Started Apr 21 12:42:41 PM PDT 24
Finished Apr 21 12:42:59 PM PDT 24
Peak memory 216924 kb
Host smart-3617651d-d9a5-4ae1-83f5-7bf0503666f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035325842 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4035325842
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4178391636
Short name T380
Test name
Test status
Simulation time 3844263907 ps
CPU time 24.18 seconds
Started Apr 21 12:42:51 PM PDT 24
Finished Apr 21 12:43:15 PM PDT 24
Peak memory 211448 kb
Host smart-aaae8725-5a67-40dc-a4aa-bd448be0569b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178391636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.4178391636
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1435367090
Short name T373
Test name
Test status
Simulation time 7001493104 ps
CPU time 103.98 seconds
Started Apr 21 12:42:48 PM PDT 24
Finished Apr 21 12:44:32 PM PDT 24
Peak memory 215120 kb
Host smart-790276c8-1c32-4b2f-a4a6-6447926cc656
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435367090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1435367090
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.404967472
Short name T450
Test name
Test status
Simulation time 7186636416 ps
CPU time 28.8 seconds
Started Apr 21 12:42:33 PM PDT 24
Finished Apr 21 12:43:02 PM PDT 24
Peak memory 211968 kb
Host smart-703a84aa-b686-4793-afe9-499fd86c38f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404967472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.404967472
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.608672619
Short name T389
Test name
Test status
Simulation time 14919174384 ps
CPU time 32.6 seconds
Started Apr 21 12:42:49 PM PDT 24
Finished Apr 21 12:43:21 PM PDT 24
Peak memory 219212 kb
Host smart-5862c2cc-951e-4e81-acb8-c543123413d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608672619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.608672619
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3402964620
Short name T127
Test name
Test status
Simulation time 4233103618 ps
CPU time 103.02 seconds
Started Apr 21 12:43:00 PM PDT 24
Finished Apr 21 12:44:43 PM PDT 24
Peak memory 213064 kb
Host smart-e4169c82-d838-4e15-b85e-06b1b78654c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402964620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3402964620
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1120034589
Short name T399
Test name
Test status
Simulation time 10584858574 ps
CPU time 21.33 seconds
Started Apr 21 12:42:44 PM PDT 24
Finished Apr 21 12:43:05 PM PDT 24
Peak memory 219196 kb
Host smart-da0569b8-0d97-40f9-8d3a-25dad158a664
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120034589 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1120034589
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.248021710
Short name T388
Test name
Test status
Simulation time 7885702903 ps
CPU time 19.59 seconds
Started Apr 21 12:42:36 PM PDT 24
Finished Apr 21 12:42:55 PM PDT 24
Peak memory 211884 kb
Host smart-ce8bb709-be56-43ce-b3ab-d3f4a0888347
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248021710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.248021710
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.386746318
Short name T407
Test name
Test status
Simulation time 8626278913 ps
CPU time 37.88 seconds
Started Apr 21 12:42:35 PM PDT 24
Finished Apr 21 12:43:13 PM PDT 24
Peak memory 214096 kb
Host smart-0109d7f3-7950-4451-8058-6e43c48c8046
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386746318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.386746318
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1685740952
Short name T89
Test name
Test status
Simulation time 2465836224 ps
CPU time 11.78 seconds
Started Apr 21 12:42:59 PM PDT 24
Finished Apr 21 12:43:11 PM PDT 24
Peak memory 210852 kb
Host smart-8c0492cd-9a9c-4df4-ac5b-2450306a8b82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685740952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1685740952
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3011162091
Short name T433
Test name
Test status
Simulation time 392145474 ps
CPU time 14.83 seconds
Started Apr 21 12:42:37 PM PDT 24
Finished Apr 21 12:42:52 PM PDT 24
Peak memory 219028 kb
Host smart-eebc24cc-1f6c-495d-80c8-dd4b711e72a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011162091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3011162091
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.412601133
Short name T129
Test name
Test status
Simulation time 8336198919 ps
CPU time 162.61 seconds
Started Apr 21 12:42:55 PM PDT 24
Finished Apr 21 12:45:43 PM PDT 24
Peak memory 213852 kb
Host smart-3c304a2c-4525-46bb-b950-2586e240a708
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412601133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.412601133
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.990603160
Short name T440
Test name
Test status
Simulation time 344414529 ps
CPU time 8.62 seconds
Started Apr 21 12:42:39 PM PDT 24
Finished Apr 21 12:42:48 PM PDT 24
Peak memory 219020 kb
Host smart-d05d009b-e3ba-402d-a9c0-3a3f3039d2f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990603160 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.990603160
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.741839069
Short name T378
Test name
Test status
Simulation time 1501923065 ps
CPU time 17.07 seconds
Started Apr 21 12:42:46 PM PDT 24
Finished Apr 21 12:43:03 PM PDT 24
Peak memory 211084 kb
Host smart-05c9c3ae-4a23-4a76-acce-01d281d3ce21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741839069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.741839069
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2002138567
Short name T110
Test name
Test status
Simulation time 17735606749 ps
CPU time 93.19 seconds
Started Apr 21 12:43:04 PM PDT 24
Finished Apr 21 12:44:38 PM PDT 24
Peak memory 219152 kb
Host smart-d3ffff0d-41e5-42c8-8e19-e3fdfe53837e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002138567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2002138567
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1709924077
Short name T114
Test name
Test status
Simulation time 1410964131 ps
CPU time 17.43 seconds
Started Apr 21 12:42:52 PM PDT 24
Finished Apr 21 12:43:09 PM PDT 24
Peak memory 211824 kb
Host smart-d5e363c3-5fd7-4a76-827a-64f153c776ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709924077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1709924077
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3514194778
Short name T387
Test name
Test status
Simulation time 16385468624 ps
CPU time 37.57 seconds
Started Apr 21 12:42:44 PM PDT 24
Finished Apr 21 12:43:22 PM PDT 24
Peak memory 219096 kb
Host smart-c22eaeb1-199e-437e-8cab-7d45c670cd47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514194778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3514194778
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4256471205
Short name T403
Test name
Test status
Simulation time 665095235 ps
CPU time 8.97 seconds
Started Apr 21 12:42:37 PM PDT 24
Finished Apr 21 12:42:46 PM PDT 24
Peak memory 216144 kb
Host smart-50b6a095-f8c2-4e69-bef9-1aa7137b8a70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256471205 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4256471205
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.295055276
Short name T445
Test name
Test status
Simulation time 4984325466 ps
CPU time 22.49 seconds
Started Apr 21 12:42:39 PM PDT 24
Finished Apr 21 12:43:02 PM PDT 24
Peak memory 211616 kb
Host smart-517dc407-0cb5-490a-88e5-d69ad0bcd4ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295055276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.295055276
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2221245713
Short name T116
Test name
Test status
Simulation time 2832615896 ps
CPU time 37.3 seconds
Started Apr 21 12:42:41 PM PDT 24
Finished Apr 21 12:43:18 PM PDT 24
Peak memory 212976 kb
Host smart-74301d06-f178-4c83-8d8c-8de30c238567
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221245713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2221245713
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1678069962
Short name T443
Test name
Test status
Simulation time 497515145 ps
CPU time 9.87 seconds
Started Apr 21 12:42:55 PM PDT 24
Finished Apr 21 12:43:05 PM PDT 24
Peak memory 210932 kb
Host smart-6f7d013e-6393-4d45-b1c7-cc8252fbfaa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678069962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1678069962
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.684815596
Short name T417
Test name
Test status
Simulation time 5047633731 ps
CPU time 28.43 seconds
Started Apr 21 12:42:46 PM PDT 24
Finished Apr 21 12:43:15 PM PDT 24
Peak memory 217428 kb
Host smart-57071fac-0761-4468-bd27-94aa4c05d652
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684815596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.684815596
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.973430826
Short name T128
Test name
Test status
Simulation time 8210848019 ps
CPU time 101.8 seconds
Started Apr 21 12:43:05 PM PDT 24
Finished Apr 21 12:44:48 PM PDT 24
Peak memory 213512 kb
Host smart-bfffd73d-bec0-44d4-9b0d-72892e9bea2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973430826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.973430826
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3677498624
Short name T375
Test name
Test status
Simulation time 4375977518 ps
CPU time 22.37 seconds
Started Apr 21 12:42:43 PM PDT 24
Finished Apr 21 12:43:05 PM PDT 24
Peak memory 219236 kb
Host smart-4de57752-90c1-4304-a73d-ce4b4569cf21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677498624 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3677498624
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.678682717
Short name T448
Test name
Test status
Simulation time 8678846430 ps
CPU time 32.3 seconds
Started Apr 21 12:42:55 PM PDT 24
Finished Apr 21 12:43:28 PM PDT 24
Peak memory 212108 kb
Host smart-a0f7ab18-c85b-4281-bdf9-44736cd939ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678682717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.678682717
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2882756583
Short name T85
Test name
Test status
Simulation time 16579087787 ps
CPU time 127.41 seconds
Started Apr 21 12:42:42 PM PDT 24
Finished Apr 21 12:44:50 PM PDT 24
Peak memory 219088 kb
Host smart-eb02ae5d-82b7-450d-896d-9b10c355ce1f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882756583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2882756583
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2073514888
Short name T113
Test name
Test status
Simulation time 176375484 ps
CPU time 8.28 seconds
Started Apr 21 12:42:48 PM PDT 24
Finished Apr 21 12:42:56 PM PDT 24
Peak memory 210896 kb
Host smart-032ce69d-d840-4e7c-920f-197b6533c6c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073514888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2073514888
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2810572627
Short name T366
Test name
Test status
Simulation time 3222700013 ps
CPU time 17.91 seconds
Started Apr 21 12:42:44 PM PDT 24
Finished Apr 21 12:43:02 PM PDT 24
Peak memory 218028 kb
Host smart-c2b80f14-070f-41d5-8306-efa14a943813
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810572627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2810572627
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2311323952
Short name T368
Test name
Test status
Simulation time 43185631016 ps
CPU time 29.85 seconds
Started Apr 21 12:42:38 PM PDT 24
Finished Apr 21 12:43:08 PM PDT 24
Peak memory 217516 kb
Host smart-4eb6d58c-af67-45f8-90f5-2e490e3e60e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311323952 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2311323952
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.251040162
Short name T374
Test name
Test status
Simulation time 7888232081 ps
CPU time 20.08 seconds
Started Apr 21 12:42:45 PM PDT 24
Finished Apr 21 12:43:05 PM PDT 24
Peak memory 211976 kb
Host smart-83ea4a32-4c88-4c53-977d-3ddc0aa9ff52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251040162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.251040162
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.520701324
Short name T103
Test name
Test status
Simulation time 14487997844 ps
CPU time 145.03 seconds
Started Apr 21 12:42:51 PM PDT 24
Finished Apr 21 12:45:16 PM PDT 24
Peak memory 215328 kb
Host smart-62831e68-eea0-42fd-8997-97d117deb53e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520701324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.520701324
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2025949780
Short name T115
Test name
Test status
Simulation time 187569579 ps
CPU time 12.33 seconds
Started Apr 21 12:42:52 PM PDT 24
Finished Apr 21 12:43:05 PM PDT 24
Peak memory 210940 kb
Host smart-a3f75283-122c-4f0b-ad9c-1b20826acbdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025949780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2025949780
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1111000973
Short name T393
Test name
Test status
Simulation time 967504890 ps
CPU time 13.61 seconds
Started Apr 21 12:42:45 PM PDT 24
Finished Apr 21 12:42:59 PM PDT 24
Peak memory 216860 kb
Host smart-eaa0b4cd-cdf6-4f70-961c-83e2c5fed1e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111000973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1111000973
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2159923225
Short name T415
Test name
Test status
Simulation time 181945201 ps
CPU time 8.26 seconds
Started Apr 21 12:42:51 PM PDT 24
Finished Apr 21 12:42:59 PM PDT 24
Peak memory 214232 kb
Host smart-e4b70296-fbab-4c7a-b492-3e16177359ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159923225 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2159923225
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1528597178
Short name T392
Test name
Test status
Simulation time 2380404481 ps
CPU time 22.56 seconds
Started Apr 21 12:42:49 PM PDT 24
Finished Apr 21 12:43:12 PM PDT 24
Peak memory 211284 kb
Host smart-f86f25bc-f7cd-420c-aa89-1c6b7b4b01f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528597178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1528597178
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1856445486
Short name T427
Test name
Test status
Simulation time 2331796321 ps
CPU time 19.61 seconds
Started Apr 21 12:42:52 PM PDT 24
Finished Apr 21 12:43:12 PM PDT 24
Peak memory 212192 kb
Host smart-b57ee72d-1489-4876-8801-25db4d743851
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856445486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1856445486
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.635841304
Short name T435
Test name
Test status
Simulation time 3694214322 ps
CPU time 34.67 seconds
Started Apr 21 12:43:02 PM PDT 24
Finished Apr 21 12:43:37 PM PDT 24
Peak memory 219164 kb
Host smart-7a8ac9f6-3936-4b37-91c8-20191cfd4fb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635841304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.635841304
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4110988378
Short name T406
Test name
Test status
Simulation time 1064837163 ps
CPU time 8.8 seconds
Started Apr 21 12:42:53 PM PDT 24
Finished Apr 21 12:43:03 PM PDT 24
Peak memory 213964 kb
Host smart-637f8b60-7add-4104-9fe5-49bc8abcd64a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110988378 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.4110988378
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3908954609
Short name T106
Test name
Test status
Simulation time 1831878863 ps
CPU time 8.11 seconds
Started Apr 21 12:43:16 PM PDT 24
Finished Apr 21 12:43:24 PM PDT 24
Peak memory 210932 kb
Host smart-59a1b5f5-ae20-4254-9150-ea476075248c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908954609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3908954609
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.447728229
Short name T424
Test name
Test status
Simulation time 156439834361 ps
CPU time 116.61 seconds
Started Apr 21 12:42:57 PM PDT 24
Finished Apr 21 12:44:54 PM PDT 24
Peak memory 211580 kb
Host smart-73c1a606-14ea-42c5-a5dd-c807ea13987b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447728229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.447728229
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3116911372
Short name T384
Test name
Test status
Simulation time 9251851954 ps
CPU time 25.74 seconds
Started Apr 21 12:42:48 PM PDT 24
Finished Apr 21 12:43:14 PM PDT 24
Peak memory 212192 kb
Host smart-d2117a83-ab63-40c5-be7a-e4a4e95c5760
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116911372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3116911372
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1663139526
Short name T385
Test name
Test status
Simulation time 2683365383 ps
CPU time 22.13 seconds
Started Apr 21 12:43:14 PM PDT 24
Finished Apr 21 12:43:36 PM PDT 24
Peak memory 219228 kb
Host smart-e95efc86-fa5e-400f-89d1-b7239a44faec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663139526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1663139526
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2512715986
Short name T71
Test name
Test status
Simulation time 3770877263 ps
CPU time 100.09 seconds
Started Apr 21 12:42:39 PM PDT 24
Finished Apr 21 12:44:19 PM PDT 24
Peak memory 219092 kb
Host smart-7c41952f-7d76-4a89-a454-e85c500ba53b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512715986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2512715986
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3706368158
Short name T413
Test name
Test status
Simulation time 11963067590 ps
CPU time 25.77 seconds
Started Apr 21 12:42:41 PM PDT 24
Finished Apr 21 12:43:07 PM PDT 24
Peak memory 215060 kb
Host smart-312cb36c-bc05-4b71-8935-27742761c53d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706368158 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3706368158
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1302920849
Short name T412
Test name
Test status
Simulation time 16217016700 ps
CPU time 31.07 seconds
Started Apr 21 12:42:48 PM PDT 24
Finished Apr 21 12:43:20 PM PDT 24
Peak memory 210840 kb
Host smart-2ce74c6b-3099-41ae-8de4-167b3f24be6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302920849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1302920849
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.986694387
Short name T432
Test name
Test status
Simulation time 39353049774 ps
CPU time 91.19 seconds
Started Apr 21 12:43:06 PM PDT 24
Finished Apr 21 12:44:37 PM PDT 24
Peak memory 213388 kb
Host smart-ca271815-44f9-4655-bca3-425311bf7e62
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986694387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.986694387
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.427944856
Short name T441
Test name
Test status
Simulation time 2970425948 ps
CPU time 17.94 seconds
Started Apr 21 12:42:54 PM PDT 24
Finished Apr 21 12:43:12 PM PDT 24
Peak memory 211844 kb
Host smart-84c26250-b84f-48ea-bff0-c8464647e039
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427944856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.427944856
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1628691750
Short name T379
Test name
Test status
Simulation time 29512160362 ps
CPU time 34.46 seconds
Started Apr 21 12:42:54 PM PDT 24
Finished Apr 21 12:43:29 PM PDT 24
Peak memory 218224 kb
Host smart-3367ab7a-7a6b-465a-a49a-4b01b1d687bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628691750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1628691750
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1945954261
Short name T452
Test name
Test status
Simulation time 38697581948 ps
CPU time 104.62 seconds
Started Apr 21 12:42:55 PM PDT 24
Finished Apr 21 12:44:40 PM PDT 24
Peak memory 213504 kb
Host smart-90a727b0-d05b-4631-a3f8-11082aedaf82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945954261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1945954261
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2223635279
Short name T108
Test name
Test status
Simulation time 4119093198 ps
CPU time 14.62 seconds
Started Apr 21 12:42:29 PM PDT 24
Finished Apr 21 12:42:44 PM PDT 24
Peak memory 210960 kb
Host smart-f7647ca2-d2c9-41de-b284-28e3a48a7759
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223635279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2223635279
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3853852175
Short name T414
Test name
Test status
Simulation time 3585378679 ps
CPU time 29.66 seconds
Started Apr 21 12:42:48 PM PDT 24
Finished Apr 21 12:43:18 PM PDT 24
Peak memory 211412 kb
Host smart-12ee16ec-8eaf-4b85-a1ce-e526b51d9104
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853852175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3853852175
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3081880530
Short name T449
Test name
Test status
Simulation time 10855585213 ps
CPU time 26.71 seconds
Started Apr 21 12:42:59 PM PDT 24
Finished Apr 21 12:43:26 PM PDT 24
Peak memory 211920 kb
Host smart-ea9406f5-4ede-48bf-a276-4315da92c382
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081880530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3081880530
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2895072773
Short name T369
Test name
Test status
Simulation time 205632627 ps
CPU time 8.95 seconds
Started Apr 21 12:42:42 PM PDT 24
Finished Apr 21 12:42:51 PM PDT 24
Peak memory 219048 kb
Host smart-4bd189d5-76ca-49c2-b0b5-2f95e5dabfa7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895072773 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2895072773
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2556463908
Short name T396
Test name
Test status
Simulation time 10803097054 ps
CPU time 24.2 seconds
Started Apr 21 12:42:56 PM PDT 24
Finished Apr 21 12:43:20 PM PDT 24
Peak memory 211768 kb
Host smart-d758ebfe-e359-47fa-99b1-7aa2698dae93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556463908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2556463908
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.371888796
Short name T381
Test name
Test status
Simulation time 517292109 ps
CPU time 11.8 seconds
Started Apr 21 12:42:26 PM PDT 24
Finished Apr 21 12:42:38 PM PDT 24
Peak memory 210776 kb
Host smart-14fcb8a8-9e2b-4759-b026-2f84e0945eeb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371888796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.371888796
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1369766759
Short name T423
Test name
Test status
Simulation time 1964005485 ps
CPU time 20.59 seconds
Started Apr 21 12:42:41 PM PDT 24
Finished Apr 21 12:43:02 PM PDT 24
Peak memory 210728 kb
Host smart-8edda1d6-0f1d-493e-9de6-d3f23203fc3e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369766759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1369766759
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2772307113
Short name T400
Test name
Test status
Simulation time 98578150265 ps
CPU time 117.01 seconds
Started Apr 21 12:42:36 PM PDT 24
Finished Apr 21 12:44:34 PM PDT 24
Peak memory 214044 kb
Host smart-07795047-3ebe-4ca0-a738-b7f6c16cd4cc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772307113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2772307113
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2260686791
Short name T112
Test name
Test status
Simulation time 5172710005 ps
CPU time 23.2 seconds
Started Apr 21 12:42:25 PM PDT 24
Finished Apr 21 12:42:48 PM PDT 24
Peak memory 211964 kb
Host smart-2a96c888-99e5-4c75-a021-4902f094c820
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260686791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2260686791
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2925140508
Short name T367
Test name
Test status
Simulation time 9144862267 ps
CPU time 31.45 seconds
Started Apr 21 12:42:37 PM PDT 24
Finished Apr 21 12:43:09 PM PDT 24
Peak memory 217528 kb
Host smart-6f957ea4-7c5e-48dd-a99f-2332874914eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925140508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2925140508
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4080167271
Short name T123
Test name
Test status
Simulation time 1211317318 ps
CPU time 153.51 seconds
Started Apr 21 12:42:34 PM PDT 24
Finished Apr 21 12:45:08 PM PDT 24
Peak memory 213780 kb
Host smart-2642e0f4-4765-4d7c-a63e-50e06c60bf55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080167271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.4080167271
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.644982522
Short name T377
Test name
Test status
Simulation time 174537976 ps
CPU time 8.11 seconds
Started Apr 21 12:42:52 PM PDT 24
Finished Apr 21 12:43:00 PM PDT 24
Peak memory 210832 kb
Host smart-d5d0991e-ffa9-49b7-8338-b65d5db2ee2b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644982522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.644982522
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2485221457
Short name T455
Test name
Test status
Simulation time 6499050800 ps
CPU time 27.56 seconds
Started Apr 21 12:42:43 PM PDT 24
Finished Apr 21 12:43:11 PM PDT 24
Peak memory 211436 kb
Host smart-cc725f22-7dbd-4b20-b93b-f877c2baf635
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485221457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2485221457
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2207586343
Short name T102
Test name
Test status
Simulation time 9435816386 ps
CPU time 35.19 seconds
Started Apr 21 12:42:44 PM PDT 24
Finished Apr 21 12:43:20 PM PDT 24
Peak memory 211948 kb
Host smart-d403d7ee-9dbe-42c0-bd8f-009183d9ee99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207586343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2207586343
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3069042789
Short name T446
Test name
Test status
Simulation time 1048332526 ps
CPU time 8.34 seconds
Started Apr 21 12:42:55 PM PDT 24
Finished Apr 21 12:43:04 PM PDT 24
Peak memory 214508 kb
Host smart-4cd6a74c-d07e-4539-9133-8a12b5765e01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069042789 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3069042789
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4228788898
Short name T410
Test name
Test status
Simulation time 1979408197 ps
CPU time 20.19 seconds
Started Apr 21 12:42:35 PM PDT 24
Finished Apr 21 12:42:55 PM PDT 24
Peak memory 211512 kb
Host smart-9524ccdc-9dcc-4ad9-bfee-f57545cd9236
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228788898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.4228788898
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1994800520
Short name T397
Test name
Test status
Simulation time 15081521970 ps
CPU time 29.47 seconds
Started Apr 21 12:42:32 PM PDT 24
Finished Apr 21 12:43:02 PM PDT 24
Peak memory 210716 kb
Host smart-3b2eb521-f639-471d-a7e9-8bdc2681a9b4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994800520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1994800520
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1844572685
Short name T416
Test name
Test status
Simulation time 2207802802 ps
CPU time 21.72 seconds
Started Apr 21 12:42:31 PM PDT 24
Finished Apr 21 12:42:53 PM PDT 24
Peak memory 210812 kb
Host smart-2b8d6f11-6aef-474c-87cd-98b8763822be
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844572685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1844572685
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.133098661
Short name T91
Test name
Test status
Simulation time 10663439861 ps
CPU time 123.28 seconds
Started Apr 21 12:42:53 PM PDT 24
Finished Apr 21 12:44:56 PM PDT 24
Peak memory 215056 kb
Host smart-9a6dad17-e854-491f-a8da-b256cc28b51d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133098661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.133098661
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1428989499
Short name T394
Test name
Test status
Simulation time 661569338 ps
CPU time 8.28 seconds
Started Apr 21 12:42:19 PM PDT 24
Finished Apr 21 12:42:28 PM PDT 24
Peak memory 210940 kb
Host smart-6ba58a8c-bdc3-46f6-aee8-2f5239ce5741
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428989499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1428989499
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1844322478
Short name T372
Test name
Test status
Simulation time 14845081427 ps
CPU time 38.58 seconds
Started Apr 21 12:42:51 PM PDT 24
Finished Apr 21 12:43:30 PM PDT 24
Peak memory 219156 kb
Host smart-19ac071e-8bb8-43e2-9ae4-2173aded3184
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844322478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1844322478
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2226780522
Short name T118
Test name
Test status
Simulation time 2458990231 ps
CPU time 95.52 seconds
Started Apr 21 12:42:27 PM PDT 24
Finished Apr 21 12:44:03 PM PDT 24
Peak memory 219160 kb
Host smart-a0f6a824-efe2-451e-85f7-325e934a75ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226780522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2226780522
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4265512058
Short name T457
Test name
Test status
Simulation time 431756049 ps
CPU time 11.15 seconds
Started Apr 21 12:42:40 PM PDT 24
Finished Apr 21 12:42:55 PM PDT 24
Peak memory 210796 kb
Host smart-9b60ea9e-f367-4f12-ad22-1343372499e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265512058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.4265512058
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2006059104
Short name T447
Test name
Test status
Simulation time 5092057746 ps
CPU time 24.34 seconds
Started Apr 21 12:42:20 PM PDT 24
Finished Apr 21 12:42:44 PM PDT 24
Peak memory 211868 kb
Host smart-21b9d98d-d3d2-40ef-be0b-beeb59ce26ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006059104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2006059104
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1499145563
Short name T101
Test name
Test status
Simulation time 9761987586 ps
CPU time 31.56 seconds
Started Apr 21 12:42:38 PM PDT 24
Finished Apr 21 12:43:10 PM PDT 24
Peak memory 211868 kb
Host smart-fe67c71f-ffe9-4644-99e2-7161df731149
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499145563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1499145563
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3894229762
Short name T430
Test name
Test status
Simulation time 4698706414 ps
CPU time 30.45 seconds
Started Apr 21 12:42:52 PM PDT 24
Finished Apr 21 12:43:23 PM PDT 24
Peak memory 216716 kb
Host smart-493893cf-9ff7-4274-862a-eb0235989b21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894229762 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3894229762
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3632379611
Short name T429
Test name
Test status
Simulation time 3080564188 ps
CPU time 13.38 seconds
Started Apr 21 12:42:50 PM PDT 24
Finished Apr 21 12:43:04 PM PDT 24
Peak memory 210868 kb
Host smart-9a8e93a2-1257-4793-86dd-efc8718c3140
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632379611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3632379611
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3589028
Short name T361
Test name
Test status
Simulation time 8058265814 ps
CPU time 31.76 seconds
Started Apr 21 12:42:41 PM PDT 24
Finished Apr 21 12:43:13 PM PDT 24
Peak memory 210720 kb
Host smart-8866f738-1818-4efc-bac2-65fdc4b3c4f3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_m
em_partial_access.3589028
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1401637517
Short name T420
Test name
Test status
Simulation time 16024795182 ps
CPU time 30.44 seconds
Started Apr 21 12:42:17 PM PDT 24
Finished Apr 21 12:42:48 PM PDT 24
Peak memory 210796 kb
Host smart-fcdb3a7e-79be-4dfa-948a-75267d88d17e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401637517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1401637517
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1391108095
Short name T398
Test name
Test status
Simulation time 147656586008 ps
CPU time 192.54 seconds
Started Apr 21 12:42:39 PM PDT 24
Finished Apr 21 12:45:52 PM PDT 24
Peak memory 215108 kb
Host smart-f89b591b-a893-4d38-a687-3a29aa0422d7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391108095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1391108095
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2779725755
Short name T87
Test name
Test status
Simulation time 28692107409 ps
CPU time 26.76 seconds
Started Apr 21 12:42:53 PM PDT 24
Finished Apr 21 12:43:20 PM PDT 24
Peak memory 212064 kb
Host smart-2ceac29e-56a7-4606-9389-a2a49b4f7386
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779725755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2779725755
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3265235784
Short name T382
Test name
Test status
Simulation time 241381721 ps
CPU time 13.96 seconds
Started Apr 21 12:42:52 PM PDT 24
Finished Apr 21 12:43:06 PM PDT 24
Peak memory 219144 kb
Host smart-6baa414f-d929-4c6c-b317-980527f97472
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265235784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3265235784
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3371820576
Short name T437
Test name
Test status
Simulation time 4385278086 ps
CPU time 160.89 seconds
Started Apr 21 12:42:45 PM PDT 24
Finished Apr 21 12:45:26 PM PDT 24
Peak memory 214668 kb
Host smart-756dc492-978e-44e1-862b-14f8ebd32582
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371820576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3371820576
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1961580169
Short name T364
Test name
Test status
Simulation time 360691916 ps
CPU time 11.68 seconds
Started Apr 21 12:42:38 PM PDT 24
Finished Apr 21 12:42:50 PM PDT 24
Peak memory 216980 kb
Host smart-37d1ed45-9832-47ba-b47d-2cb69740c699
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961580169 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1961580169
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4067696479
Short name T408
Test name
Test status
Simulation time 436423817 ps
CPU time 8.29 seconds
Started Apr 21 12:42:52 PM PDT 24
Finished Apr 21 12:43:00 PM PDT 24
Peak memory 210936 kb
Host smart-5ba2b774-4d86-4443-922b-b8b8b1ef56bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067696479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.4067696479
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.536354116
Short name T439
Test name
Test status
Simulation time 2075419477 ps
CPU time 56.43 seconds
Started Apr 21 12:42:39 PM PDT 24
Finished Apr 21 12:43:36 PM PDT 24
Peak memory 219132 kb
Host smart-53e6a911-10ef-4f2e-b8fd-b766031e1b48
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536354116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.536354116
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.514571063
Short name T418
Test name
Test status
Simulation time 4938434193 ps
CPU time 22.94 seconds
Started Apr 21 12:42:47 PM PDT 24
Finished Apr 21 12:43:11 PM PDT 24
Peak memory 212564 kb
Host smart-9d077341-50bf-4a43-bd1c-0d2e02a0ada6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514571063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.514571063
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1534276801
Short name T390
Test name
Test status
Simulation time 4406622125 ps
CPU time 38.02 seconds
Started Apr 21 12:42:27 PM PDT 24
Finished Apr 21 12:43:05 PM PDT 24
Peak memory 217280 kb
Host smart-c7550167-d826-48df-844f-d893ab2b918b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534276801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1534276801
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.340293267
Short name T131
Test name
Test status
Simulation time 12750356960 ps
CPU time 99.45 seconds
Started Apr 21 12:42:31 PM PDT 24
Finished Apr 21 12:44:11 PM PDT 24
Peak memory 214184 kb
Host smart-71586887-5653-46d0-87b9-a058591683e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340293267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.340293267
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4261737751
Short name T383
Test name
Test status
Simulation time 835058605 ps
CPU time 14.18 seconds
Started Apr 21 12:42:47 PM PDT 24
Finished Apr 21 12:43:02 PM PDT 24
Peak memory 219092 kb
Host smart-306bac3b-6916-4b51-b56c-1225b3881249
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261737751 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.4261737751
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1677114566
Short name T98
Test name
Test status
Simulation time 612419009 ps
CPU time 8.2 seconds
Started Apr 21 12:42:46 PM PDT 24
Finished Apr 21 12:42:55 PM PDT 24
Peak memory 210864 kb
Host smart-57a2a0ff-3716-435b-b341-2557742f5e60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677114566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1677114566
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.880513429
Short name T90
Test name
Test status
Simulation time 40536837956 ps
CPU time 126.23 seconds
Started Apr 21 12:42:41 PM PDT 24
Finished Apr 21 12:44:47 PM PDT 24
Peak memory 215092 kb
Host smart-525c6ad0-9a92-4e74-ab14-24d3c45ea654
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880513429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.880513429
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1875804196
Short name T401
Test name
Test status
Simulation time 688197265 ps
CPU time 8.01 seconds
Started Apr 21 12:42:36 PM PDT 24
Finished Apr 21 12:42:44 PM PDT 24
Peak memory 210932 kb
Host smart-646157a1-d03a-4a08-949d-4d8d4d49f6ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875804196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1875804196
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2761154931
Short name T362
Test name
Test status
Simulation time 1795566675 ps
CPU time 22.4 seconds
Started Apr 21 12:42:16 PM PDT 24
Finished Apr 21 12:42:39 PM PDT 24
Peak memory 216936 kb
Host smart-9a35ffe4-6dcf-4501-9c4d-4efe3d2d9b8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761154931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2761154931
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3837144376
Short name T122
Test name
Test status
Simulation time 326467383 ps
CPU time 83.02 seconds
Started Apr 21 12:42:41 PM PDT 24
Finished Apr 21 12:44:04 PM PDT 24
Peak memory 212884 kb
Host smart-1c5bb687-5018-4914-86fe-8c9806daae86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837144376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3837144376
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1259945951
Short name T402
Test name
Test status
Simulation time 2061945945 ps
CPU time 21.7 seconds
Started Apr 21 12:42:36 PM PDT 24
Finished Apr 21 12:42:58 PM PDT 24
Peak memory 217616 kb
Host smart-9bfd9e72-1f70-404f-bd92-2e69f47571c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259945951 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1259945951
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1266682026
Short name T107
Test name
Test status
Simulation time 872162990 ps
CPU time 13.59 seconds
Started Apr 21 12:42:46 PM PDT 24
Finished Apr 21 12:43:00 PM PDT 24
Peak memory 210936 kb
Host smart-33c81dbb-947b-4663-bdc5-482c1944e576
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266682026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1266682026
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2598764399
Short name T97
Test name
Test status
Simulation time 9603481613 ps
CPU time 92.79 seconds
Started Apr 21 12:42:47 PM PDT 24
Finished Apr 21 12:44:20 PM PDT 24
Peak memory 214056 kb
Host smart-4da28018-791b-453c-93de-bcb406cf8e01
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598764399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2598764399
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2254248305
Short name T391
Test name
Test status
Simulation time 859865524 ps
CPU time 12.3 seconds
Started Apr 21 12:42:53 PM PDT 24
Finished Apr 21 12:43:06 PM PDT 24
Peak memory 212136 kb
Host smart-8e9a0234-25d9-41c5-a71f-d867c7f6dc14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254248305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2254248305
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3833110183
Short name T438
Test name
Test status
Simulation time 1234222362 ps
CPU time 20.99 seconds
Started Apr 21 12:42:51 PM PDT 24
Finished Apr 21 12:43:12 PM PDT 24
Peak memory 219012 kb
Host smart-73e16f6d-9394-4909-9450-7884b83a8ad2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833110183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3833110183
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.471580857
Short name T121
Test name
Test status
Simulation time 401470497 ps
CPU time 81.67 seconds
Started Apr 21 12:42:32 PM PDT 24
Finished Apr 21 12:43:54 PM PDT 24
Peak memory 213088 kb
Host smart-7d9babd9-88fe-4967-92d1-7573aedfea80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471580857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.471580857
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1006022386
Short name T436
Test name
Test status
Simulation time 11087653444 ps
CPU time 22.46 seconds
Started Apr 21 12:42:44 PM PDT 24
Finished Apr 21 12:43:07 PM PDT 24
Peak memory 219112 kb
Host smart-387a8e18-dc6b-4aea-9e09-fafdf9fdacab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006022386 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1006022386
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3039941261
Short name T99
Test name
Test status
Simulation time 5758337031 ps
CPU time 24.76 seconds
Started Apr 21 12:42:38 PM PDT 24
Finished Apr 21 12:43:03 PM PDT 24
Peak memory 211696 kb
Host smart-daa5b10f-75ca-46b8-87bf-467bcef7b2fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039941261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3039941261
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2813629826
Short name T434
Test name
Test status
Simulation time 694512071 ps
CPU time 38.01 seconds
Started Apr 21 12:42:46 PM PDT 24
Finished Apr 21 12:43:25 PM PDT 24
Peak memory 212916 kb
Host smart-207d67d2-045e-40b7-851f-9afabbe3e568
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813629826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2813629826
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4125181975
Short name T454
Test name
Test status
Simulation time 6220591664 ps
CPU time 26.85 seconds
Started Apr 21 12:43:06 PM PDT 24
Finished Apr 21 12:43:33 PM PDT 24
Peak memory 211816 kb
Host smart-79915e72-3351-4f6a-9792-39b0ed03fe34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125181975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.4125181975
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2810512944
Short name T409
Test name
Test status
Simulation time 11125664445 ps
CPU time 29.08 seconds
Started Apr 21 12:42:48 PM PDT 24
Finished Apr 21 12:43:18 PM PDT 24
Peak memory 217408 kb
Host smart-5d048d30-c766-43c2-9c4c-ca9a12afa688
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810512944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2810512944
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2142791581
Short name T130
Test name
Test status
Simulation time 12372110034 ps
CPU time 169.44 seconds
Started Apr 21 12:42:47 PM PDT 24
Finished Apr 21 12:45:37 PM PDT 24
Peak memory 219128 kb
Host smart-a823b811-27d7-4162-88f0-1c0d63c73445
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142791581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2142791581
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.647119187
Short name T371
Test name
Test status
Simulation time 5826834014 ps
CPU time 23.98 seconds
Started Apr 21 12:42:48 PM PDT 24
Finished Apr 21 12:43:12 PM PDT 24
Peak memory 219196 kb
Host smart-257c615f-aec9-4aaf-8b52-f45d133bc416
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647119187 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.647119187
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2672219482
Short name T426
Test name
Test status
Simulation time 11411791918 ps
CPU time 26.25 seconds
Started Apr 21 12:42:57 PM PDT 24
Finished Apr 21 12:43:23 PM PDT 24
Peak memory 211860 kb
Host smart-9129d86a-d01c-4491-9df3-058429282a00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672219482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2672219482
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3475947635
Short name T451
Test name
Test status
Simulation time 44780078999 ps
CPU time 98.69 seconds
Started Apr 21 12:42:42 PM PDT 24
Finished Apr 21 12:44:21 PM PDT 24
Peak memory 219368 kb
Host smart-f926f3a2-5946-46ec-b160-6c4002782cea
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475947635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3475947635
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2635065511
Short name T111
Test name
Test status
Simulation time 12713222604 ps
CPU time 24.15 seconds
Started Apr 21 12:42:49 PM PDT 24
Finished Apr 21 12:43:14 PM PDT 24
Peak memory 212300 kb
Host smart-1adac013-d0c2-4930-a58b-e429be60fbea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635065511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2635065511
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.448636778
Short name T370
Test name
Test status
Simulation time 2684362826 ps
CPU time 27.69 seconds
Started Apr 21 12:42:32 PM PDT 24
Finished Apr 21 12:43:00 PM PDT 24
Peak memory 219188 kb
Host smart-d51baaa3-b9c1-4ca0-853f-8a7184a61531
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448636778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.448636778
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.253035413
Short name T453
Test name
Test status
Simulation time 4104456616 ps
CPU time 176.12 seconds
Started Apr 21 12:42:54 PM PDT 24
Finished Apr 21 12:45:50 PM PDT 24
Peak memory 214592 kb
Host smart-07807083-05ba-4d68-93b0-25b8d4e3a39a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253035413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.253035413
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2809238565
Short name T66
Test name
Test status
Simulation time 346321569 ps
CPU time 10.66 seconds
Started Apr 21 12:45:27 PM PDT 24
Finished Apr 21 12:45:38 PM PDT 24
Peak memory 211836 kb
Host smart-1c9266e0-a3b8-47f5-8f6f-17a5a7b67788
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809238565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2809238565
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2097843447
Short name T350
Test name
Test status
Simulation time 83901719811 ps
CPU time 833.48 seconds
Started Apr 21 12:45:01 PM PDT 24
Finished Apr 21 12:58:56 PM PDT 24
Peak memory 241392 kb
Host smart-5fa76e75-0e5e-40e7-a4ec-82daa40ab21a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097843447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2097843447
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1960274158
Short name T23
Test name
Test status
Simulation time 4360871424 ps
CPU time 46.29 seconds
Started Apr 21 12:45:29 PM PDT 24
Finished Apr 21 12:46:16 PM PDT 24
Peak memory 215692 kb
Host smart-b376936b-4861-4303-8363-a0528444f72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960274158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1960274158
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.4091892070
Short name T247
Test name
Test status
Simulation time 857286325 ps
CPU time 15.92 seconds
Started Apr 21 12:45:05 PM PDT 24
Finished Apr 21 12:45:22 PM PDT 24
Peak memory 211868 kb
Host smart-b1cb9433-c678-420a-b23f-518eec87b375
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4091892070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.4091892070
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3499827912
Short name T295
Test name
Test status
Simulation time 8172027261 ps
CPU time 80.03 seconds
Started Apr 21 12:45:11 PM PDT 24
Finished Apr 21 12:46:32 PM PDT 24
Peak memory 217828 kb
Host smart-4ba2e225-28ed-4c78-85f0-1344c7232700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499827912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3499827912
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1827770309
Short name T242
Test name
Test status
Simulation time 3100783806 ps
CPU time 34.67 seconds
Started Apr 21 12:45:13 PM PDT 24
Finished Apr 21 12:45:48 PM PDT 24
Peak memory 219960 kb
Host smart-2132d52f-4f2c-4e98-897a-712840632c37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827770309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1827770309
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2180113700
Short name T203
Test name
Test status
Simulation time 4912103092 ps
CPU time 23.73 seconds
Started Apr 21 12:45:15 PM PDT 24
Finished Apr 21 12:45:39 PM PDT 24
Peak memory 212880 kb
Host smart-dc839158-a3ce-4f2e-839f-41076f9a2324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180113700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2180113700
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1398354220
Short name T31
Test name
Test status
Simulation time 36642430245 ps
CPU time 418.06 seconds
Started Apr 21 12:45:08 PM PDT 24
Finished Apr 21 12:52:07 PM PDT 24
Peak memory 240472 kb
Host smart-cbc77b99-6c11-429b-b30c-7fc29febc968
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398354220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1398354220
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1613496059
Short name T210
Test name
Test status
Simulation time 37012271045 ps
CPU time 56.07 seconds
Started Apr 21 12:45:19 PM PDT 24
Finished Apr 21 12:46:15 PM PDT 24
Peak memory 215644 kb
Host smart-4a5396e2-3e23-40ae-9166-f1103c9a27e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613496059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1613496059
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1567993797
Short name T347
Test name
Test status
Simulation time 358731957 ps
CPU time 10.27 seconds
Started Apr 21 12:45:28 PM PDT 24
Finished Apr 21 12:45:39 PM PDT 24
Peak memory 212128 kb
Host smart-77260a96-879d-4caf-8be8-e5c3ed48f0eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1567993797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1567993797
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.348169561
Short name T35
Test name
Test status
Simulation time 17243384428 ps
CPU time 248.01 seconds
Started Apr 21 12:45:10 PM PDT 24
Finished Apr 21 12:49:19 PM PDT 24
Peak memory 237440 kb
Host smart-9bbb58af-93f7-4d3f-a16e-e3573398b2e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348169561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.348169561
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1149405009
Short name T309
Test name
Test status
Simulation time 348180445 ps
CPU time 20.19 seconds
Started Apr 21 12:45:14 PM PDT 24
Finished Apr 21 12:45:35 PM PDT 24
Peak memory 217976 kb
Host smart-b76c28f1-0678-44b1-97e1-41dc0c209487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149405009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1149405009
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.364051287
Short name T306
Test name
Test status
Simulation time 377841908 ps
CPU time 17.29 seconds
Started Apr 21 12:45:26 PM PDT 24
Finished Apr 21 12:45:44 PM PDT 24
Peak memory 212140 kb
Host smart-14168448-3f09-4462-aef9-48e237e569f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364051287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.364051287
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.7387755
Short name T46
Test name
Test status
Simulation time 3137137895 ps
CPU time 25.64 seconds
Started Apr 21 12:45:25 PM PDT 24
Finished Apr 21 12:45:50 PM PDT 24
Peak memory 212516 kb
Host smart-1cc06528-a027-4f37-be55-54d8aed7e1ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7387755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.7387755
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1617352560
Short name T302
Test name
Test status
Simulation time 48988007609 ps
CPU time 495.15 seconds
Started Apr 21 12:45:21 PM PDT 24
Finished Apr 21 12:53:37 PM PDT 24
Peak memory 218348 kb
Host smart-cc462931-104b-4c02-b23a-c364fe13a162
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617352560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1617352560
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2900861183
Short name T221
Test name
Test status
Simulation time 17128595755 ps
CPU time 44.42 seconds
Started Apr 21 12:45:27 PM PDT 24
Finished Apr 21 12:46:12 PM PDT 24
Peak memory 215756 kb
Host smart-409ecde4-79f4-4fde-8126-016e2bb9cc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900861183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2900861183
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3942055604
Short name T229
Test name
Test status
Simulation time 3457352800 ps
CPU time 30.34 seconds
Started Apr 21 12:45:26 PM PDT 24
Finished Apr 21 12:45:57 PM PDT 24
Peak memory 212764 kb
Host smart-35e219ec-d125-4e19-96b2-d617372444d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3942055604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3942055604
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2543263236
Short name T94
Test name
Test status
Simulation time 5408780828 ps
CPU time 58.58 seconds
Started Apr 21 12:45:27 PM PDT 24
Finished Apr 21 12:46:26 PM PDT 24
Peak memory 217880 kb
Host smart-741ed464-a030-4d18-8962-47608523259d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543263236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2543263236
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3962964234
Short name T95
Test name
Test status
Simulation time 47522221500 ps
CPU time 175.28 seconds
Started Apr 21 12:45:21 PM PDT 24
Finished Apr 21 12:48:17 PM PDT 24
Peak memory 220580 kb
Host smart-3a855d10-3180-4a9b-b61c-3407778c3c2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962964234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3962964234
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2247054695
Short name T57
Test name
Test status
Simulation time 138210482457 ps
CPU time 9747.73 seconds
Started Apr 21 12:45:29 PM PDT 24
Finished Apr 21 03:27:59 PM PDT 24
Peak memory 236428 kb
Host smart-ccd8d57e-0928-4469-9e22-59c60c0ef283
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247054695 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.2247054695
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.969391067
Short name T54
Test name
Test status
Simulation time 3402702132 ps
CPU time 26.52 seconds
Started Apr 21 12:45:20 PM PDT 24
Finished Apr 21 12:45:47 PM PDT 24
Peak memory 212580 kb
Host smart-154a7cc7-d131-4853-9f26-e24c732a5795
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969391067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.969391067
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.4193884611
Short name T226
Test name
Test status
Simulation time 3616400669 ps
CPU time 42.18 seconds
Started Apr 21 12:45:31 PM PDT 24
Finished Apr 21 12:46:14 PM PDT 24
Peak memory 215392 kb
Host smart-573c6ce5-7eab-46ac-b1ce-e3a6a2c0cb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193884611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.4193884611
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1814208146
Short name T265
Test name
Test status
Simulation time 4788917261 ps
CPU time 17.29 seconds
Started Apr 21 12:45:25 PM PDT 24
Finished Apr 21 12:45:43 PM PDT 24
Peak memory 212364 kb
Host smart-027562b0-862c-495e-adfe-8419a61b643f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1814208146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1814208146
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3000490349
Short name T340
Test name
Test status
Simulation time 16014795569 ps
CPU time 62.89 seconds
Started Apr 21 12:45:27 PM PDT 24
Finished Apr 21 12:46:31 PM PDT 24
Peak memory 218852 kb
Host smart-dba1e776-4be2-493b-b129-e2e94519e7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000490349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3000490349
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2627133850
Short name T12
Test name
Test status
Simulation time 5297894851 ps
CPU time 56.17 seconds
Started Apr 21 12:45:23 PM PDT 24
Finished Apr 21 12:46:19 PM PDT 24
Peak memory 219944 kb
Host smart-7954059f-13b8-40f3-833e-779562154260
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627133850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2627133850
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2707094956
Short name T255
Test name
Test status
Simulation time 95378013786 ps
CPU time 311.62 seconds
Started Apr 21 12:45:23 PM PDT 24
Finished Apr 21 12:50:35 PM PDT 24
Peak memory 227920 kb
Host smart-acfaae16-8627-44a9-83b2-d37b07db6026
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707094956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2707094956
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.363947162
Short name T207
Test name
Test status
Simulation time 24174533473 ps
CPU time 56.03 seconds
Started Apr 21 12:45:26 PM PDT 24
Finished Apr 21 12:46:22 PM PDT 24
Peak memory 215588 kb
Host smart-c97809ac-ae29-40e2-b622-fb4108bc8153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363947162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.363947162
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4193293067
Short name T69
Test name
Test status
Simulation time 1318501622 ps
CPU time 18.25 seconds
Started Apr 21 12:45:32 PM PDT 24
Finished Apr 21 12:45:50 PM PDT 24
Peak memory 212772 kb
Host smart-54066137-8cff-4307-b3b9-f8ef9406e35e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4193293067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.4193293067
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1273840581
Short name T267
Test name
Test status
Simulation time 78814956976 ps
CPU time 66.35 seconds
Started Apr 21 12:45:26 PM PDT 24
Finished Apr 21 12:46:32 PM PDT 24
Peak memory 217348 kb
Host smart-88fbdf3c-1e83-4297-9032-8f94c9abc4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273840581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1273840581
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3926314340
Short name T252
Test name
Test status
Simulation time 3576226706 ps
CPU time 73.74 seconds
Started Apr 21 12:45:36 PM PDT 24
Finished Apr 21 12:46:50 PM PDT 24
Peak memory 221036 kb
Host smart-f644e54c-5e2f-4437-902d-d50c1e363748
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926314340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3926314340
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2070179245
Short name T151
Test name
Test status
Simulation time 6008780997 ps
CPU time 19.88 seconds
Started Apr 21 12:45:38 PM PDT 24
Finished Apr 21 12:45:58 PM PDT 24
Peak memory 212912 kb
Host smart-d306b999-bdb1-4c0d-835a-7204f9d70c51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070179245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2070179245
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3120719187
Short name T304
Test name
Test status
Simulation time 85376522241 ps
CPU time 322.01 seconds
Started Apr 21 12:45:41 PM PDT 24
Finished Apr 21 12:51:03 PM PDT 24
Peak memory 237280 kb
Host smart-15b907cb-ee28-4c5c-8ad9-c3f2d43b4b3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120719187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3120719187
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1456302152
Short name T68
Test name
Test status
Simulation time 961340986 ps
CPU time 23.93 seconds
Started Apr 21 12:45:29 PM PDT 24
Finished Apr 21 12:45:54 PM PDT 24
Peak memory 215928 kb
Host smart-feeb644b-03af-4ad0-8f65-e7fadc8ce77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456302152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1456302152
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.752167501
Short name T64
Test name
Test status
Simulation time 14112701471 ps
CPU time 24.66 seconds
Started Apr 21 12:45:27 PM PDT 24
Finished Apr 21 12:45:52 PM PDT 24
Peak memory 211872 kb
Host smart-35eeff96-5cb2-443d-a5bf-2296d3b66d35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=752167501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.752167501
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.31750452
Short name T236
Test name
Test status
Simulation time 1117474808 ps
CPU time 37.61 seconds
Started Apr 21 12:45:35 PM PDT 24
Finished Apr 21 12:46:13 PM PDT 24
Peak memory 216380 kb
Host smart-73c75bff-9fcf-4edd-a9ef-f662ecab90a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31750452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 13.rom_ctrl_stress_all.31750452
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.4019587549
Short name T303
Test name
Test status
Simulation time 5595665877 ps
CPU time 25.34 seconds
Started Apr 21 12:45:28 PM PDT 24
Finished Apr 21 12:45:54 PM PDT 24
Peak memory 212876 kb
Host smart-79e55657-7c2d-4e2b-9299-24f18768867f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019587549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.4019587549
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1956392877
Short name T159
Test name
Test status
Simulation time 82938117265 ps
CPU time 423.43 seconds
Started Apr 21 12:45:35 PM PDT 24
Finished Apr 21 12:52:39 PM PDT 24
Peak memory 238300 kb
Host smart-b1223b8a-0a6a-4740-b017-890e63f39998
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956392877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1956392877
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.4148583108
Short name T145
Test name
Test status
Simulation time 4944957399 ps
CPU time 48.85 seconds
Started Apr 21 12:45:41 PM PDT 24
Finished Apr 21 12:46:30 PM PDT 24
Peak memory 215676 kb
Host smart-cb50a262-6d31-48c2-9de0-8b84e536db87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148583108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.4148583108
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2814251094
Short name T163
Test name
Test status
Simulation time 1562317174 ps
CPU time 15.52 seconds
Started Apr 21 12:45:37 PM PDT 24
Finished Apr 21 12:45:53 PM PDT 24
Peak memory 213080 kb
Host smart-ddef9a62-a1f6-48aa-a34d-b0b2120ca3c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2814251094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2814251094
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2107851442
Short name T209
Test name
Test status
Simulation time 7829407436 ps
CPU time 74.71 seconds
Started Apr 21 12:45:28 PM PDT 24
Finished Apr 21 12:46:43 PM PDT 24
Peak memory 217240 kb
Host smart-99824e5e-18d6-4bd2-b2ad-afaf36c89d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107851442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2107851442
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.602423347
Short name T156
Test name
Test status
Simulation time 65315379462 ps
CPU time 205.54 seconds
Started Apr 21 12:45:47 PM PDT 24
Finished Apr 21 12:49:13 PM PDT 24
Peak memory 221920 kb
Host smart-cae8a964-2767-45be-8b90-58455479c4f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602423347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.602423347
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3521664578
Short name T60
Test name
Test status
Simulation time 286241398250 ps
CPU time 2046.29 seconds
Started Apr 21 12:45:33 PM PDT 24
Finished Apr 21 01:19:40 PM PDT 24
Peak memory 246528 kb
Host smart-b0068b8d-3f3c-4fd4-a8ca-bf0f1bca3447
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521664578 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3521664578
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.361056354
Short name T301
Test name
Test status
Simulation time 3188541036 ps
CPU time 27.07 seconds
Started Apr 21 12:45:36 PM PDT 24
Finished Apr 21 12:46:03 PM PDT 24
Peak memory 212476 kb
Host smart-23e728e4-188b-47bc-a11d-c4ee14828c7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361056354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.361056354
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1275400939
Short name T323
Test name
Test status
Simulation time 101412244228 ps
CPU time 549.07 seconds
Started Apr 21 12:45:29 PM PDT 24
Finished Apr 21 12:54:38 PM PDT 24
Peak memory 240864 kb
Host smart-32da9d3f-8716-4888-84c5-51189c41a9dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275400939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1275400939
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.4112013261
Short name T316
Test name
Test status
Simulation time 199053716 ps
CPU time 10.28 seconds
Started Apr 21 12:45:30 PM PDT 24
Finished Apr 21 12:45:41 PM PDT 24
Peak memory 212720 kb
Host smart-d9ab951a-15cd-4fe8-a315-cb172f88330d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4112013261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.4112013261
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2192201176
Short name T250
Test name
Test status
Simulation time 7012674677 ps
CPU time 37.55 seconds
Started Apr 21 12:45:22 PM PDT 24
Finished Apr 21 12:46:00 PM PDT 24
Peak memory 216904 kb
Host smart-61f9c1e7-e13a-4eb6-a979-123fd444580a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192201176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2192201176
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1646303568
Short name T42
Test name
Test status
Simulation time 13968393227 ps
CPU time 55.93 seconds
Started Apr 21 12:45:28 PM PDT 24
Finished Apr 21 12:46:25 PM PDT 24
Peak memory 219948 kb
Host smart-6bc4163c-2ee4-4699-8761-ec422ff45ecd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646303568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1646303568
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.685174328
Short name T260
Test name
Test status
Simulation time 3785892939 ps
CPU time 30.69 seconds
Started Apr 21 12:45:27 PM PDT 24
Finished Apr 21 12:45:59 PM PDT 24
Peak memory 212504 kb
Host smart-0192f611-1352-4ecf-8c48-56592fd4c9b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685174328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.685174328
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3685997906
Short name T1
Test name
Test status
Simulation time 5494595675 ps
CPU time 194.13 seconds
Started Apr 21 12:45:32 PM PDT 24
Finished Apr 21 12:48:46 PM PDT 24
Peak memory 240648 kb
Host smart-7225aaf5-f3a7-4f10-848e-14f8c2ec2df0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685997906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3685997906
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.4163391894
Short name T167
Test name
Test status
Simulation time 24542117088 ps
CPU time 54.75 seconds
Started Apr 21 12:45:29 PM PDT 24
Finished Apr 21 12:46:25 PM PDT 24
Peak memory 215876 kb
Host smart-7eb3d3b3-20cc-45fa-b3f1-d5d34b5eac67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163391894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.4163391894
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.116799962
Short name T276
Test name
Test status
Simulation time 3721349897 ps
CPU time 20.84 seconds
Started Apr 21 12:45:32 PM PDT 24
Finished Apr 21 12:45:54 PM PDT 24
Peak memory 212812 kb
Host smart-6f7d22af-994c-4727-9ed1-07d0e815340f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=116799962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.116799962
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1918548746
Short name T80
Test name
Test status
Simulation time 26723934096 ps
CPU time 58.23 seconds
Started Apr 21 12:45:27 PM PDT 24
Finished Apr 21 12:46:26 PM PDT 24
Peak memory 217364 kb
Host smart-00cdb628-6cc0-4d56-9f89-b081d0f88672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918548746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1918548746
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.4153821766
Short name T173
Test name
Test status
Simulation time 78684868206 ps
CPU time 80.08 seconds
Started Apr 21 12:45:34 PM PDT 24
Finished Apr 21 12:46:55 PM PDT 24
Peak memory 219884 kb
Host smart-c9e09db1-ede6-4811-9918-9b2480c56191
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153821766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.4153821766
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3171168579
Short name T205
Test name
Test status
Simulation time 2793396054 ps
CPU time 17.57 seconds
Started Apr 21 12:45:32 PM PDT 24
Finished Apr 21 12:45:51 PM PDT 24
Peak memory 212044 kb
Host smart-6a62a773-68ae-4492-a5a2-442d2987f2da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171168579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3171168579
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3142028086
Short name T357
Test name
Test status
Simulation time 5748793777 ps
CPU time 371.52 seconds
Started Apr 21 12:45:38 PM PDT 24
Finished Apr 21 12:51:51 PM PDT 24
Peak memory 235900 kb
Host smart-37a337e3-228d-48ac-8944-c717da8eaf6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142028086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3142028086
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1144952701
Short name T196
Test name
Test status
Simulation time 9819336265 ps
CPU time 49.56 seconds
Started Apr 21 12:45:29 PM PDT 24
Finished Apr 21 12:46:19 PM PDT 24
Peak memory 215676 kb
Host smart-f666fa0e-d380-41bf-8ccd-819537379ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144952701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1144952701
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2711993109
Short name T133
Test name
Test status
Simulation time 181505008 ps
CPU time 10.72 seconds
Started Apr 21 12:45:31 PM PDT 24
Finished Apr 21 12:45:42 PM PDT 24
Peak memory 213364 kb
Host smart-b19cb036-1f33-4bfd-97b3-3bddbec6babf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2711993109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2711993109
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1468750569
Short name T140
Test name
Test status
Simulation time 10859588826 ps
CPU time 58.17 seconds
Started Apr 21 12:45:36 PM PDT 24
Finished Apr 21 12:46:35 PM PDT 24
Peak memory 218144 kb
Host smart-39cb71bf-3a51-40f4-95e7-cfd0c23c2f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468750569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1468750569
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2254667258
Short name T297
Test name
Test status
Simulation time 14293359012 ps
CPU time 34.13 seconds
Started Apr 21 12:45:36 PM PDT 24
Finished Apr 21 12:46:11 PM PDT 24
Peak memory 214680 kb
Host smart-b2298e6b-fed4-4a65-b44c-a73d8fab9632
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254667258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2254667258
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1974599262
Short name T187
Test name
Test status
Simulation time 7728737420 ps
CPU time 32.26 seconds
Started Apr 21 12:45:31 PM PDT 24
Finished Apr 21 12:46:03 PM PDT 24
Peak memory 212924 kb
Host smart-347c7088-0140-4824-8574-9d7b5cc68251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974599262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1974599262
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2160292458
Short name T30
Test name
Test status
Simulation time 196942544035 ps
CPU time 274.45 seconds
Started Apr 21 12:45:29 PM PDT 24
Finished Apr 21 12:50:04 PM PDT 24
Peak memory 241404 kb
Host smart-faea8b6e-38d2-4eb2-8bc0-2ce716ad1e4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160292458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2160292458
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.897633650
Short name T185
Test name
Test status
Simulation time 40005573231 ps
CPU time 68.72 seconds
Started Apr 21 12:45:32 PM PDT 24
Finished Apr 21 12:46:41 PM PDT 24
Peak memory 215352 kb
Host smart-e5387bc9-54c5-43b3-98b4-7536ec24b732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897633650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.897633650
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1035278068
Short name T352
Test name
Test status
Simulation time 2344485616 ps
CPU time 24.56 seconds
Started Apr 21 12:45:45 PM PDT 24
Finished Apr 21 12:46:11 PM PDT 24
Peak memory 211904 kb
Host smart-b54f00a2-2709-4ff7-a9ee-a0060f5906ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1035278068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1035278068
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3954600236
Short name T277
Test name
Test status
Simulation time 43807365328 ps
CPU time 58.93 seconds
Started Apr 21 12:45:37 PM PDT 24
Finished Apr 21 12:46:36 PM PDT 24
Peak memory 218728 kb
Host smart-cb9ace57-02b8-4495-8a87-447fc61eae1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954600236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3954600236
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2278398653
Short name T345
Test name
Test status
Simulation time 9809110043 ps
CPU time 50.37 seconds
Started Apr 21 12:45:45 PM PDT 24
Finished Apr 21 12:46:36 PM PDT 24
Peak memory 218188 kb
Host smart-1078b0c2-f918-4138-a0fe-2884fdff42c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278398653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2278398653
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.621051440
Short name T63
Test name
Test status
Simulation time 167336612 ps
CPU time 8.27 seconds
Started Apr 21 12:46:04 PM PDT 24
Finished Apr 21 12:46:14 PM PDT 24
Peak memory 211888 kb
Host smart-2f946ca8-b0dd-4287-94d2-b9cce38dc501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621051440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.621051440
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1847913363
Short name T179
Test name
Test status
Simulation time 314760134345 ps
CPU time 757.44 seconds
Started Apr 21 12:45:38 PM PDT 24
Finished Apr 21 12:58:17 PM PDT 24
Peak memory 241284 kb
Host smart-d61bf6e6-ec0b-40ec-a246-ef599d94bc97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847913363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1847913363
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3302949485
Short name T70
Test name
Test status
Simulation time 30228953079 ps
CPU time 66.5 seconds
Started Apr 21 12:45:42 PM PDT 24
Finished Apr 21 12:46:49 PM PDT 24
Peak memory 215640 kb
Host smart-71376ad7-02d7-44fb-a7c2-ccaec8171673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302949485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3302949485
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2045786412
Short name T259
Test name
Test status
Simulation time 343046564 ps
CPU time 12.78 seconds
Started Apr 21 12:45:34 PM PDT 24
Finished Apr 21 12:45:47 PM PDT 24
Peak memory 211840 kb
Host smart-292b577d-c32c-4a06-8947-393fbf310ac6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2045786412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2045786412
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2902697770
Short name T135
Test name
Test status
Simulation time 21860629614 ps
CPU time 56.09 seconds
Started Apr 21 12:45:31 PM PDT 24
Finished Apr 21 12:46:27 PM PDT 24
Peak memory 218400 kb
Host smart-61172e3a-e8d3-4bef-982e-de010d9b4218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902697770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2902697770
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1689487064
Short name T172
Test name
Test status
Simulation time 369543363 ps
CPU time 20.46 seconds
Started Apr 21 12:45:43 PM PDT 24
Finished Apr 21 12:46:05 PM PDT 24
Peak memory 218232 kb
Host smart-48e29941-3d0d-4de3-97e0-426773c8b2d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689487064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1689487064
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1892936259
Short name T83
Test name
Test status
Simulation time 268471796 ps
CPU time 8.21 seconds
Started Apr 21 12:45:14 PM PDT 24
Finished Apr 21 12:45:23 PM PDT 24
Peak memory 211892 kb
Host smart-59338da3-78eb-4b1e-aae8-8185ac91e666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892936259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1892936259
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1296912869
Short name T67
Test name
Test status
Simulation time 3728689442 ps
CPU time 167.1 seconds
Started Apr 21 12:45:07 PM PDT 24
Finished Apr 21 12:47:55 PM PDT 24
Peak memory 241352 kb
Host smart-69e2f633-d07e-4ddb-a337-4066fdb9bca2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296912869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1296912869
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1866124881
Short name T190
Test name
Test status
Simulation time 3629464596 ps
CPU time 34.35 seconds
Started Apr 21 12:45:27 PM PDT 24
Finished Apr 21 12:46:02 PM PDT 24
Peak memory 215260 kb
Host smart-d8104ab8-0cca-4c41-a04b-a4a1846ffaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866124881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1866124881
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2188460845
Short name T274
Test name
Test status
Simulation time 3445260817 ps
CPU time 28.91 seconds
Started Apr 21 12:45:11 PM PDT 24
Finished Apr 21 12:45:41 PM PDT 24
Peak memory 211924 kb
Host smart-d29b3644-88b2-4459-9f08-838e49c74b04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2188460845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2188460845
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3025666541
Short name T33
Test name
Test status
Simulation time 10539287560 ps
CPU time 240.01 seconds
Started Apr 21 12:45:14 PM PDT 24
Finished Apr 21 12:49:14 PM PDT 24
Peak memory 237332 kb
Host smart-c8cb0ec4-d3f8-4fff-865d-48d47c91040b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025666541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3025666541
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.609638911
Short name T169
Test name
Test status
Simulation time 79225916466 ps
CPU time 54.15 seconds
Started Apr 21 12:45:15 PM PDT 24
Finished Apr 21 12:46:10 PM PDT 24
Peak memory 218452 kb
Host smart-d27f8e2d-e0b5-4949-8688-efbb898fa7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609638911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.609638911
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.745194582
Short name T337
Test name
Test status
Simulation time 1192012578 ps
CPU time 70.55 seconds
Started Apr 21 12:45:22 PM PDT 24
Finished Apr 21 12:46:33 PM PDT 24
Peak memory 219800 kb
Host smart-477be4be-1412-4e68-b1e5-a632afd1d9dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745194582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.745194582
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.658609774
Short name T9
Test name
Test status
Simulation time 5181628098 ps
CPU time 24.06 seconds
Started Apr 21 12:45:36 PM PDT 24
Finished Apr 21 12:46:00 PM PDT 24
Peak memory 212776 kb
Host smart-ae287bc1-a609-4934-aab0-fb6d1be0a1d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658609774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.658609774
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2989924122
Short name T354
Test name
Test status
Simulation time 480624138930 ps
CPU time 633.71 seconds
Started Apr 21 12:45:43 PM PDT 24
Finished Apr 21 12:56:17 PM PDT 24
Peak memory 217896 kb
Host smart-5eee9ec0-bec8-4a84-bf05-13c9ba1bf744
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989924122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2989924122
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3902716409
Short name T355
Test name
Test status
Simulation time 5719369662 ps
CPU time 50.98 seconds
Started Apr 21 12:45:45 PM PDT 24
Finished Apr 21 12:46:36 PM PDT 24
Peak memory 215568 kb
Host smart-9afdb9b0-05ec-495b-b699-af5272aeb114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902716409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3902716409
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.678495918
Short name T257
Test name
Test status
Simulation time 762339045 ps
CPU time 10.74 seconds
Started Apr 21 12:45:37 PM PDT 24
Finished Apr 21 12:45:49 PM PDT 24
Peak memory 213020 kb
Host smart-5e44f42b-0af6-41d4-b7ff-fb1905ac1452
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=678495918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.678495918
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1432487656
Short name T144
Test name
Test status
Simulation time 64298232805 ps
CPU time 62.88 seconds
Started Apr 21 12:45:45 PM PDT 24
Finished Apr 21 12:46:49 PM PDT 24
Peak memory 218140 kb
Host smart-8cc25d72-34c5-4d38-a3af-4c7d37851e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432487656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1432487656
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.429053896
Short name T346
Test name
Test status
Simulation time 3356571222 ps
CPU time 20.63 seconds
Started Apr 21 12:45:34 PM PDT 24
Finished Apr 21 12:45:55 PM PDT 24
Peak memory 214308 kb
Host smart-92fee49a-8c82-458d-89c5-fb7cc1545bbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429053896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.429053896
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2612887830
Short name T194
Test name
Test status
Simulation time 7323810756 ps
CPU time 17.54 seconds
Started Apr 21 12:45:46 PM PDT 24
Finished Apr 21 12:46:04 PM PDT 24
Peak memory 212796 kb
Host smart-cb144d45-52af-403b-9fa8-21d78f447433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612887830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2612887830
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2476639567
Short name T280
Test name
Test status
Simulation time 83282666372 ps
CPU time 526.59 seconds
Started Apr 21 12:45:59 PM PDT 24
Finished Apr 21 12:54:47 PM PDT 24
Peak memory 220240 kb
Host smart-0f9da13d-0b38-4ce3-9b80-5e6bc8c8943d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476639567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2476639567
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.439772260
Short name T170
Test name
Test status
Simulation time 2057766579 ps
CPU time 26.03 seconds
Started Apr 21 12:45:42 PM PDT 24
Finished Apr 21 12:46:09 PM PDT 24
Peak memory 215316 kb
Host smart-1bb010e7-5f5a-4e10-b8cd-82450516f166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439772260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.439772260
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2360016619
Short name T161
Test name
Test status
Simulation time 178548962 ps
CPU time 10.59 seconds
Started Apr 21 12:45:31 PM PDT 24
Finished Apr 21 12:45:42 PM PDT 24
Peak memory 212648 kb
Host smart-53051de9-5791-429b-bf7b-479e973d1c45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2360016619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2360016619
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3874532809
Short name T44
Test name
Test status
Simulation time 8921781960 ps
CPU time 35.78 seconds
Started Apr 21 12:45:37 PM PDT 24
Finished Apr 21 12:46:13 PM PDT 24
Peak memory 218272 kb
Host smart-ece7bdba-de61-4a0a-a3f4-844b56bd61a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874532809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3874532809
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3216184686
Short name T326
Test name
Test status
Simulation time 16466048799 ps
CPU time 41.06 seconds
Started Apr 21 12:45:42 PM PDT 24
Finished Apr 21 12:46:23 PM PDT 24
Peak memory 214604 kb
Host smart-7fa818bd-d933-42dc-81d1-092b91ae7587
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216184686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3216184686
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2513873693
Short name T308
Test name
Test status
Simulation time 1952237966 ps
CPU time 20.87 seconds
Started Apr 21 12:45:30 PM PDT 24
Finished Apr 21 12:45:51 PM PDT 24
Peak memory 211952 kb
Host smart-e17108de-cf2d-4cec-a239-217edbbbc128
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513873693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2513873693
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2024362980
Short name T320
Test name
Test status
Simulation time 27833130762 ps
CPU time 368.71 seconds
Started Apr 21 12:45:34 PM PDT 24
Finished Apr 21 12:51:43 PM PDT 24
Peak memory 241136 kb
Host smart-9c3af8ec-6051-4908-8ce6-c0c229936a3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024362980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2024362980
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1858602034
Short name T198
Test name
Test status
Simulation time 217940092 ps
CPU time 10.5 seconds
Started Apr 21 12:45:40 PM PDT 24
Finished Apr 21 12:45:51 PM PDT 24
Peak memory 213084 kb
Host smart-ec086211-a5fb-4641-8c49-8e5f3fddced0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1858602034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1858602034
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3888468509
Short name T315
Test name
Test status
Simulation time 15054584758 ps
CPU time 78.27 seconds
Started Apr 21 12:45:45 PM PDT 24
Finished Apr 21 12:47:04 PM PDT 24
Peak memory 218484 kb
Host smart-7c0cb113-97f9-4e02-9806-d5db4012080c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888468509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3888468509
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2724362490
Short name T200
Test name
Test status
Simulation time 22191570620 ps
CPU time 107.99 seconds
Started Apr 21 12:45:33 PM PDT 24
Finished Apr 21 12:47:21 PM PDT 24
Peak memory 219892 kb
Host smart-b5c97ff1-bccb-4a09-a815-d2ddd384d0ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724362490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2724362490
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1358193519
Short name T61
Test name
Test status
Simulation time 21412565160 ps
CPU time 859.47 seconds
Started Apr 21 12:45:42 PM PDT 24
Finished Apr 21 01:00:02 PM PDT 24
Peak memory 236452 kb
Host smart-46e0396b-63e7-4a94-bfa6-a7b9efb13b53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358193519 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.1358193519
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3258203426
Short name T335
Test name
Test status
Simulation time 7403844252 ps
CPU time 18.03 seconds
Started Apr 21 12:45:39 PM PDT 24
Finished Apr 21 12:45:58 PM PDT 24
Peak memory 212084 kb
Host smart-4739e129-0939-4b6f-ba0e-a220fe8355fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258203426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3258203426
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4062995989
Short name T332
Test name
Test status
Simulation time 88693843646 ps
CPU time 286.25 seconds
Started Apr 21 12:45:36 PM PDT 24
Finished Apr 21 12:50:23 PM PDT 24
Peak memory 240364 kb
Host smart-cd9c46bd-27fd-4097-9ef2-0735e41ea556
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062995989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.4062995989
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1474556473
Short name T288
Test name
Test status
Simulation time 31459176625 ps
CPU time 65.58 seconds
Started Apr 21 12:45:36 PM PDT 24
Finished Apr 21 12:46:42 PM PDT 24
Peak memory 215504 kb
Host smart-ae5a8a50-923d-49a8-8e96-23cd3f55ef1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474556473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1474556473
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.4220535808
Short name T268
Test name
Test status
Simulation time 27553843509 ps
CPU time 60.12 seconds
Started Apr 21 12:45:47 PM PDT 24
Finished Apr 21 12:46:48 PM PDT 24
Peak memory 218524 kb
Host smart-572210de-a84c-4417-b36f-c26cae8c31c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220535808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.4220535808
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1076644629
Short name T146
Test name
Test status
Simulation time 24695614990 ps
CPU time 43.46 seconds
Started Apr 21 12:45:53 PM PDT 24
Finished Apr 21 12:46:38 PM PDT 24
Peak memory 214736 kb
Host smart-0eef625c-faf3-4161-862b-2b0ac1cfb43f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076644629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1076644629
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3810756701
Short name T261
Test name
Test status
Simulation time 4105548861 ps
CPU time 15.72 seconds
Started Apr 21 12:45:52 PM PDT 24
Finished Apr 21 12:46:09 PM PDT 24
Peak memory 212048 kb
Host smart-729663cb-a7ce-4873-ab86-aec924299ab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810756701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3810756701
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3232604770
Short name T217
Test name
Test status
Simulation time 21982199772 ps
CPU time 300.24 seconds
Started Apr 21 12:45:39 PM PDT 24
Finished Apr 21 12:50:40 PM PDT 24
Peak memory 238380 kb
Host smart-40478387-f0d6-42fd-a23f-5cea59741933
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232604770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3232604770
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3467254945
Short name T296
Test name
Test status
Simulation time 1321952751 ps
CPU time 18.92 seconds
Started Apr 21 12:45:28 PM PDT 24
Finished Apr 21 12:45:48 PM PDT 24
Peak memory 215132 kb
Host smart-1e7d1ead-70ec-484d-865e-be8c4afae8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467254945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3467254945
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.16261801
Short name T336
Test name
Test status
Simulation time 2581731706 ps
CPU time 24.41 seconds
Started Apr 21 12:45:32 PM PDT 24
Finished Apr 21 12:45:57 PM PDT 24
Peak memory 211860 kb
Host smart-7392955f-81ee-4f2d-a5ba-56ac05d32e1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16261801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.16261801
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3909230128
Short name T329
Test name
Test status
Simulation time 7658663252 ps
CPU time 69.57 seconds
Started Apr 21 12:45:36 PM PDT 24
Finished Apr 21 12:46:46 PM PDT 24
Peak memory 218092 kb
Host smart-0f80e206-f389-4300-87c6-0d025917dd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909230128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3909230128
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1219308994
Short name T96
Test name
Test status
Simulation time 58714121653 ps
CPU time 148.02 seconds
Started Apr 21 12:45:47 PM PDT 24
Finished Apr 21 12:48:15 PM PDT 24
Peak memory 219960 kb
Host smart-86a1bd67-ff2b-48a3-8199-f553810f0b1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219308994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1219308994
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2171991474
Short name T138
Test name
Test status
Simulation time 2853890912 ps
CPU time 25.46 seconds
Started Apr 21 12:45:36 PM PDT 24
Finished Apr 21 12:46:07 PM PDT 24
Peak memory 212592 kb
Host smart-03f1c4bb-ec7d-4b6f-be26-23cf4e2f7863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171991474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2171991474
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2675353459
Short name T212
Test name
Test status
Simulation time 2037090984 ps
CPU time 175.44 seconds
Started Apr 21 12:45:37 PM PDT 24
Finished Apr 21 12:48:33 PM PDT 24
Peak memory 240820 kb
Host smart-da0e80f0-df3c-4ce3-a4c3-f8efa8144466
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675353459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2675353459
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.494000724
Short name T275
Test name
Test status
Simulation time 1223484467 ps
CPU time 19.63 seconds
Started Apr 21 12:45:44 PM PDT 24
Finished Apr 21 12:46:05 PM PDT 24
Peak memory 215248 kb
Host smart-6633a95d-20fd-4f85-94b0-4339a88d00f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494000724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.494000724
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1637370192
Short name T338
Test name
Test status
Simulation time 11638939289 ps
CPU time 26.34 seconds
Started Apr 21 12:45:37 PM PDT 24
Finished Apr 21 12:46:10 PM PDT 24
Peak memory 211912 kb
Host smart-6c759bb1-b50d-4d14-aa7f-b0ca04f782dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1637370192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1637370192
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3761577212
Short name T41
Test name
Test status
Simulation time 4560649500 ps
CPU time 34.76 seconds
Started Apr 21 12:45:43 PM PDT 24
Finished Apr 21 12:46:18 PM PDT 24
Peak memory 218044 kb
Host smart-4ea10743-eec0-4486-9341-d103d5a4bdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761577212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3761577212
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2294929221
Short name T235
Test name
Test status
Simulation time 13914608369 ps
CPU time 59.73 seconds
Started Apr 21 12:45:35 PM PDT 24
Finished Apr 21 12:46:35 PM PDT 24
Peak memory 219852 kb
Host smart-4b765f7b-b265-4d20-9512-a795feda5388
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294929221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2294929221
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.486903751
Short name T53
Test name
Test status
Simulation time 3017724173 ps
CPU time 25.95 seconds
Started Apr 21 12:45:44 PM PDT 24
Finished Apr 21 12:46:11 PM PDT 24
Peak memory 212008 kb
Host smart-f24e00ef-53dd-4013-9033-11e78440c000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486903751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.486903751
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2810237564
Short name T193
Test name
Test status
Simulation time 33005003075 ps
CPU time 429.3 seconds
Started Apr 21 12:45:58 PM PDT 24
Finished Apr 21 12:53:09 PM PDT 24
Peak memory 240912 kb
Host smart-cc3bd618-9f70-43f8-a860-f2e8117b4662
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810237564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2810237564
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1304101318
Short name T240
Test name
Test status
Simulation time 2747383970 ps
CPU time 24.13 seconds
Started Apr 21 12:45:39 PM PDT 24
Finished Apr 21 12:46:04 PM PDT 24
Peak memory 215288 kb
Host smart-5bccf6ca-f9ac-4036-b810-a7da53876d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304101318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1304101318
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2518037724
Short name T7
Test name
Test status
Simulation time 4663690428 ps
CPU time 20 seconds
Started Apr 21 12:45:44 PM PDT 24
Finished Apr 21 12:46:05 PM PDT 24
Peak memory 211996 kb
Host smart-1f5152aa-9d92-4120-9f6c-646cd45998bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2518037724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2518037724
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.306915985
Short name T322
Test name
Test status
Simulation time 5071186278 ps
CPU time 52.32 seconds
Started Apr 21 12:45:38 PM PDT 24
Finished Apr 21 12:46:36 PM PDT 24
Peak memory 215572 kb
Host smart-2b547e13-d9f5-4a32-8dbd-2cf985fc4354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306915985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.306915985
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2857249932
Short name T206
Test name
Test status
Simulation time 3403738157 ps
CPU time 53.14 seconds
Started Apr 21 12:45:53 PM PDT 24
Finished Apr 21 12:46:48 PM PDT 24
Peak memory 219868 kb
Host smart-460fe239-e956-4f22-bc71-450aa6ae1817
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857249932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2857249932
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.434990146
Short name T142
Test name
Test status
Simulation time 947234337 ps
CPU time 14.79 seconds
Started Apr 21 12:45:43 PM PDT 24
Finished Apr 21 12:46:00 PM PDT 24
Peak memory 212492 kb
Host smart-d306620b-6e50-4fdb-b1f7-6ac5d0d7dc52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434990146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.434990146
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1340050333
Short name T48
Test name
Test status
Simulation time 101663595329 ps
CPU time 416.96 seconds
Started Apr 21 12:45:40 PM PDT 24
Finished Apr 21 12:52:38 PM PDT 24
Peak memory 252596 kb
Host smart-c8f2dad9-76b8-4ef5-9814-b5e72fce9455
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340050333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1340050333
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1240621828
Short name T294
Test name
Test status
Simulation time 5098870487 ps
CPU time 51.99 seconds
Started Apr 21 12:45:53 PM PDT 24
Finished Apr 21 12:46:47 PM PDT 24
Peak memory 215692 kb
Host smart-92effbe6-d471-470b-bb5f-d5892eca56d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240621828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1240621828
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1541641526
Short name T248
Test name
Test status
Simulation time 2839454559 ps
CPU time 23.82 seconds
Started Apr 21 12:45:37 PM PDT 24
Finished Apr 21 12:46:01 PM PDT 24
Peak memory 212052 kb
Host smart-79e1add9-5d9c-4fab-98ee-60fa4d304d3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1541641526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1541641526
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2476996047
Short name T342
Test name
Test status
Simulation time 4623599346 ps
CPU time 50.56 seconds
Started Apr 21 12:45:42 PM PDT 24
Finished Apr 21 12:46:34 PM PDT 24
Peak memory 217644 kb
Host smart-135d0a8b-0df1-4620-bfb0-7cc55a4e006b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476996047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2476996047
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2507120386
Short name T253
Test name
Test status
Simulation time 19068365300 ps
CPU time 124.81 seconds
Started Apr 21 12:45:32 PM PDT 24
Finished Apr 21 12:47:38 PM PDT 24
Peak memory 221156 kb
Host smart-fbabb54b-2085-4d13-8b4f-77320cea0b86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507120386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2507120386
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2050899124
Short name T177
Test name
Test status
Simulation time 4109675449 ps
CPU time 31.13 seconds
Started Apr 21 12:45:52 PM PDT 24
Finished Apr 21 12:46:24 PM PDT 24
Peak memory 211820 kb
Host smart-084ba0e6-2f71-436a-954e-a9122d360568
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050899124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2050899124
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.512638527
Short name T49
Test name
Test status
Simulation time 333426965492 ps
CPU time 763.66 seconds
Started Apr 21 12:45:43 PM PDT 24
Finished Apr 21 12:58:28 PM PDT 24
Peak memory 217816 kb
Host smart-28190662-1015-459d-9c94-18c7041b1c96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512638527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.512638527
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2364262142
Short name T286
Test name
Test status
Simulation time 5295216703 ps
CPU time 49.77 seconds
Started Apr 21 12:45:38 PM PDT 24
Finished Apr 21 12:46:28 PM PDT 24
Peak memory 215672 kb
Host smart-4a721b3e-1b89-4b08-8f80-951cddd5576f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364262142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2364262142
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2735340330
Short name T40
Test name
Test status
Simulation time 11196455931 ps
CPU time 27.15 seconds
Started Apr 21 12:45:45 PM PDT 24
Finished Apr 21 12:46:12 PM PDT 24
Peak memory 212288 kb
Host smart-9cf0cc8e-536d-4753-acbe-b38128b73032
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2735340330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2735340330
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.588865780
Short name T147
Test name
Test status
Simulation time 13875520123 ps
CPU time 42.82 seconds
Started Apr 21 12:45:46 PM PDT 24
Finished Apr 21 12:46:30 PM PDT 24
Peak memory 217856 kb
Host smart-c9f9b272-d2af-4962-b3af-01c9f497f969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588865780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.588865780
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1137814118
Short name T208
Test name
Test status
Simulation time 21101227085 ps
CPU time 49.64 seconds
Started Apr 21 12:45:50 PM PDT 24
Finished Apr 21 12:46:41 PM PDT 24
Peak memory 217228 kb
Host smart-7bfc6d9a-99f9-4928-b041-a1f0cba65c66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137814118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1137814118
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1859752614
Short name T176
Test name
Test status
Simulation time 3552544895 ps
CPU time 29.75 seconds
Started Apr 21 12:45:54 PM PDT 24
Finished Apr 21 12:46:25 PM PDT 24
Peak memory 212600 kb
Host smart-1cef832b-305b-4645-9f07-bc94720fc1a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859752614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1859752614
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1960759764
Short name T28
Test name
Test status
Simulation time 2163024084 ps
CPU time 143.53 seconds
Started Apr 21 12:45:53 PM PDT 24
Finished Apr 21 12:48:17 PM PDT 24
Peak memory 216524 kb
Host smart-b0c812ac-4f80-4c91-9142-16efbcb971e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960759764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1960759764
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1930206352
Short name T43
Test name
Test status
Simulation time 12879743602 ps
CPU time 60.74 seconds
Started Apr 21 12:46:04 PM PDT 24
Finished Apr 21 12:47:06 PM PDT 24
Peak memory 215568 kb
Host smart-065159d3-8375-4d01-b0b8-e2db8d2744e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930206352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1930206352
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.690856782
Short name T299
Test name
Test status
Simulation time 12078255500 ps
CPU time 24.52 seconds
Started Apr 21 12:45:43 PM PDT 24
Finished Apr 21 12:46:09 PM PDT 24
Peak memory 212420 kb
Host smart-07c709b9-2425-4a66-8b39-442a97e63f12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=690856782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.690856782
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3549439401
Short name T284
Test name
Test status
Simulation time 1332605591 ps
CPU time 20.24 seconds
Started Apr 21 12:45:38 PM PDT 24
Finished Apr 21 12:45:59 PM PDT 24
Peak memory 217792 kb
Host smart-9d0e0b8d-1487-4fac-a34c-bf499a87b905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549439401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3549439401
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3072720607
Short name T341
Test name
Test status
Simulation time 2803391964 ps
CPU time 63.98 seconds
Started Apr 21 12:45:53 PM PDT 24
Finished Apr 21 12:46:58 PM PDT 24
Peak memory 219944 kb
Host smart-9e71056d-1295-4277-a7e2-7d4e519ab365
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072720607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3072720607
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3581979689
Short name T18
Test name
Test status
Simulation time 38826010495 ps
CPU time 1636.97 seconds
Started Apr 21 12:45:43 PM PDT 24
Finished Apr 21 01:13:01 PM PDT 24
Peak memory 238888 kb
Host smart-daf7ab5b-49da-4f21-84ed-73dc3c66c089
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581979689 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3581979689
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2965448371
Short name T249
Test name
Test status
Simulation time 8265268030 ps
CPU time 67.95 seconds
Started Apr 21 12:45:09 PM PDT 24
Finished Apr 21 12:46:18 PM PDT 24
Peak memory 215460 kb
Host smart-5c9b8619-bcba-4f16-a47c-16713720c7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965448371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2965448371
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2217248020
Short name T214
Test name
Test status
Simulation time 15520916761 ps
CPU time 20.32 seconds
Started Apr 21 12:45:10 PM PDT 24
Finished Apr 21 12:45:31 PM PDT 24
Peak memory 212636 kb
Host smart-2f79a475-1719-4f0a-a0e0-c75e3cf6abc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2217248020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2217248020
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3271825406
Short name T32
Test name
Test status
Simulation time 906209590 ps
CPU time 117.12 seconds
Started Apr 21 12:45:22 PM PDT 24
Finished Apr 21 12:47:19 PM PDT 24
Peak memory 237284 kb
Host smart-079c8c6b-044f-481c-842c-d55cef96439b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271825406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3271825406
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2917050907
Short name T344
Test name
Test status
Simulation time 6930354876 ps
CPU time 45.14 seconds
Started Apr 21 12:45:16 PM PDT 24
Finished Apr 21 12:46:01 PM PDT 24
Peak memory 218484 kb
Host smart-5770a1ff-e712-4903-ad93-8ed09d6c62d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917050907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2917050907
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.51975734
Short name T182
Test name
Test status
Simulation time 365851845 ps
CPU time 23.65 seconds
Started Apr 21 12:45:14 PM PDT 24
Finished Apr 21 12:45:38 PM PDT 24
Peak memory 217660 kb
Host smart-f10ab97c-c0cf-4444-a236-89d2815b91ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51975734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.rom_ctrl_stress_all.51975734
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2375337949
Short name T314
Test name
Test status
Simulation time 1982200286 ps
CPU time 20.25 seconds
Started Apr 21 12:45:32 PM PDT 24
Finished Apr 21 12:45:53 PM PDT 24
Peak memory 212400 kb
Host smart-cecabacb-e949-44af-8371-5c746b6eadb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375337949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2375337949
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1665678122
Short name T271
Test name
Test status
Simulation time 22854284465 ps
CPU time 257.52 seconds
Started Apr 21 12:45:40 PM PDT 24
Finished Apr 21 12:49:58 PM PDT 24
Peak memory 238312 kb
Host smart-53c2a961-787d-4866-8e6f-c1a5245e7f57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665678122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1665678122
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2434046840
Short name T233
Test name
Test status
Simulation time 81793090241 ps
CPU time 58.09 seconds
Started Apr 21 12:45:48 PM PDT 24
Finished Apr 21 12:46:46 PM PDT 24
Peak memory 214536 kb
Host smart-d0463620-bec8-47af-b542-9a2327cf6ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434046840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2434046840
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3187999149
Short name T218
Test name
Test status
Simulation time 3957872594 ps
CPU time 22.57 seconds
Started Apr 21 12:45:44 PM PDT 24
Finished Apr 21 12:46:08 PM PDT 24
Peak memory 212204 kb
Host smart-d7e81a70-7900-4451-b9cc-ded3d50367e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3187999149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3187999149
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2732066338
Short name T353
Test name
Test status
Simulation time 56281161613 ps
CPU time 43.8 seconds
Started Apr 21 12:45:59 PM PDT 24
Finished Apr 21 12:46:44 PM PDT 24
Peak memory 218712 kb
Host smart-59055878-53bf-416f-974e-dcda153350fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732066338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2732066338
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3501137782
Short name T197
Test name
Test status
Simulation time 11305813419 ps
CPU time 110.5 seconds
Started Apr 21 12:46:05 PM PDT 24
Finished Apr 21 12:47:57 PM PDT 24
Peak memory 219932 kb
Host smart-df0700e3-61a0-4d73-9191-fa86371916fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501137782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3501137782
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.197264214
Short name T59
Test name
Test status
Simulation time 21180900032 ps
CPU time 831.85 seconds
Started Apr 21 12:45:39 PM PDT 24
Finished Apr 21 12:59:31 PM PDT 24
Peak memory 236364 kb
Host smart-dcffab45-4a09-421b-b675-c5ae26acb4d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197264214 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.197264214
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.137952090
Short name T213
Test name
Test status
Simulation time 15746779924 ps
CPU time 31.19 seconds
Started Apr 21 12:45:43 PM PDT 24
Finished Apr 21 12:46:15 PM PDT 24
Peak memory 212704 kb
Host smart-4ef5bafa-31f3-42de-955d-4403ee78ad18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137952090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.137952090
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1316844961
Short name T181
Test name
Test status
Simulation time 462138192853 ps
CPU time 437.04 seconds
Started Apr 21 12:45:52 PM PDT 24
Finished Apr 21 12:53:10 PM PDT 24
Peak memory 229020 kb
Host smart-09b6a538-f67d-4d0a-962d-db958e210fb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316844961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1316844961
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.4161147691
Short name T20
Test name
Test status
Simulation time 676386221 ps
CPU time 18.89 seconds
Started Apr 21 12:45:45 PM PDT 24
Finished Apr 21 12:46:04 PM PDT 24
Peak memory 215752 kb
Host smart-ca204c2b-acb3-4feb-af22-b66086514698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161147691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.4161147691
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2296452907
Short name T238
Test name
Test status
Simulation time 9516463990 ps
CPU time 23.98 seconds
Started Apr 21 12:45:41 PM PDT 24
Finished Apr 21 12:46:05 PM PDT 24
Peak memory 212368 kb
Host smart-84467133-eb29-40d3-baf6-6b9d4e850ef7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2296452907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2296452907
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.308080590
Short name T55
Test name
Test status
Simulation time 442953208 ps
CPU time 20.34 seconds
Started Apr 21 12:45:49 PM PDT 24
Finished Apr 21 12:46:10 PM PDT 24
Peak memory 214444 kb
Host smart-28c2cf71-3582-4fee-b6ee-240b66bce0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308080590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.308080590
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3735190460
Short name T256
Test name
Test status
Simulation time 44314554672 ps
CPU time 104.69 seconds
Started Apr 21 12:46:03 PM PDT 24
Finished Apr 21 12:47:49 PM PDT 24
Peak memory 219864 kb
Host smart-2967c5f5-d2d0-439f-b7b5-c51eb18e53cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735190460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3735190460
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.592091695
Short name T264
Test name
Test status
Simulation time 338526210 ps
CPU time 7.97 seconds
Started Apr 21 12:45:45 PM PDT 24
Finished Apr 21 12:45:54 PM PDT 24
Peak memory 211888 kb
Host smart-41a28d90-bf45-4bc3-a7f8-20540d2cbd9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592091695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.592091695
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1741986025
Short name T168
Test name
Test status
Simulation time 267125903376 ps
CPU time 385.86 seconds
Started Apr 21 12:45:57 PM PDT 24
Finished Apr 21 12:52:25 PM PDT 24
Peak memory 216376 kb
Host smart-647c2a08-81a3-4586-8789-1c5250946134
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741986025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1741986025
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.717665844
Short name T155
Test name
Test status
Simulation time 5969857612 ps
CPU time 52.91 seconds
Started Apr 21 12:45:45 PM PDT 24
Finished Apr 21 12:46:38 PM PDT 24
Peak memory 215720 kb
Host smart-9ee3d7aa-e08c-4124-a9b6-9e60d12110af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717665844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.717665844
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3366139148
Short name T239
Test name
Test status
Simulation time 595555359 ps
CPU time 14.4 seconds
Started Apr 21 12:45:48 PM PDT 24
Finished Apr 21 12:46:03 PM PDT 24
Peak memory 211872 kb
Host smart-52175fba-c715-4a8f-bda7-bbbd374522b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3366139148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3366139148
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1795870329
Short name T38
Test name
Test status
Simulation time 356302166 ps
CPU time 20.36 seconds
Started Apr 21 12:45:50 PM PDT 24
Finished Apr 21 12:46:11 PM PDT 24
Peak memory 217300 kb
Host smart-0c446b72-e951-470c-999a-64998087e084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795870329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1795870329
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2553999357
Short name T246
Test name
Test status
Simulation time 33334652057 ps
CPU time 82.11 seconds
Started Apr 21 12:45:48 PM PDT 24
Finished Apr 21 12:47:10 PM PDT 24
Peak memory 218748 kb
Host smart-303ff835-0505-4341-bdd3-3fc897ad4172
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553999357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2553999357
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.89798002
Short name T318
Test name
Test status
Simulation time 1194024411 ps
CPU time 15.54 seconds
Started Apr 21 12:45:46 PM PDT 24
Finished Apr 21 12:46:02 PM PDT 24
Peak memory 211876 kb
Host smart-27129ec5-3a7c-44ca-9d44-b8a87f3bc658
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89798002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.89798002
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3532281159
Short name T143
Test name
Test status
Simulation time 124407540121 ps
CPU time 425.51 seconds
Started Apr 21 12:45:49 PM PDT 24
Finished Apr 21 12:52:55 PM PDT 24
Peak memory 236448 kb
Host smart-4dc2397d-4231-48e3-a7d3-c5679e79b39d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532281159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3532281159
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.846305991
Short name T220
Test name
Test status
Simulation time 5709828538 ps
CPU time 42.47 seconds
Started Apr 21 12:45:39 PM PDT 24
Finished Apr 21 12:46:22 PM PDT 24
Peak memory 214644 kb
Host smart-6878bb39-f4f9-4ac2-b622-2abe6b521473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846305991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.846305991
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.246826439
Short name T319
Test name
Test status
Simulation time 754470196 ps
CPU time 15.3 seconds
Started Apr 21 12:45:57 PM PDT 24
Finished Apr 21 12:46:14 PM PDT 24
Peak memory 212612 kb
Host smart-6b28cba4-85d2-4840-bde4-21341ded98fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246826439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.246826439
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2733572640
Short name T50
Test name
Test status
Simulation time 345404041 ps
CPU time 20.33 seconds
Started Apr 21 12:46:01 PM PDT 24
Finished Apr 21 12:46:22 PM PDT 24
Peak memory 216172 kb
Host smart-370ff4a4-659a-436f-9666-5ce4de657fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733572640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2733572640
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2645953173
Short name T74
Test name
Test status
Simulation time 737307331 ps
CPU time 47.19 seconds
Started Apr 21 12:45:43 PM PDT 24
Finished Apr 21 12:46:31 PM PDT 24
Peak memory 219748 kb
Host smart-4bfe6f89-e14f-4dc7-a9fd-82bde0b53035
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645953173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2645953173
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.442051646
Short name T10
Test name
Test status
Simulation time 16706327236 ps
CPU time 32.92 seconds
Started Apr 21 12:45:51 PM PDT 24
Finished Apr 21 12:46:24 PM PDT 24
Peak memory 212700 kb
Host smart-24ca3063-6557-4b78-8392-620ab6f24394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442051646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.442051646
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.4057300592
Short name T279
Test name
Test status
Simulation time 214178798688 ps
CPU time 507.11 seconds
Started Apr 21 12:45:47 PM PDT 24
Finished Apr 21 12:54:15 PM PDT 24
Peak memory 238948 kb
Host smart-773124c0-c48a-49d2-ae14-fcf2712874b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057300592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.4057300592
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3175897104
Short name T290
Test name
Test status
Simulation time 4124160130 ps
CPU time 19.11 seconds
Started Apr 21 12:45:44 PM PDT 24
Finished Apr 21 12:46:04 PM PDT 24
Peak memory 215360 kb
Host smart-c1fca117-d48d-436b-b0d3-7082b6136fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175897104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3175897104
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3223213214
Short name T327
Test name
Test status
Simulation time 3373377281 ps
CPU time 20.04 seconds
Started Apr 21 12:45:59 PM PDT 24
Finished Apr 21 12:46:20 PM PDT 24
Peak memory 211868 kb
Host smart-93c19f85-3278-4ebc-ad49-0567af93d53d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3223213214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3223213214
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.180154798
Short name T278
Test name
Test status
Simulation time 4144498884 ps
CPU time 51.74 seconds
Started Apr 21 12:45:40 PM PDT 24
Finished Apr 21 12:46:32 PM PDT 24
Peak memory 216272 kb
Host smart-73f26485-45e4-4b9f-a24d-b180b4236264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180154798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.180154798
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2990135032
Short name T325
Test name
Test status
Simulation time 16624151705 ps
CPU time 80.88 seconds
Started Apr 21 12:45:58 PM PDT 24
Finished Apr 21 12:47:20 PM PDT 24
Peak memory 221832 kb
Host smart-f38cd8da-371d-45bd-8db9-ac36b2dd2a91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990135032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2990135032
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3685823825
Short name T333
Test name
Test status
Simulation time 3943827266 ps
CPU time 21.16 seconds
Started Apr 21 12:45:43 PM PDT 24
Finished Apr 21 12:46:05 PM PDT 24
Peak memory 212036 kb
Host smart-2709e83e-84da-435c-b2e7-3a89bd3e97f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685823825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3685823825
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1749914075
Short name T175
Test name
Test status
Simulation time 9952010238 ps
CPU time 105.33 seconds
Started Apr 21 12:45:59 PM PDT 24
Finished Apr 21 12:47:45 PM PDT 24
Peak memory 239376 kb
Host smart-0ec86000-b365-4758-9aaf-f86c3229e9b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749914075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1749914075
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3602014548
Short name T237
Test name
Test status
Simulation time 6893620789 ps
CPU time 30.1 seconds
Started Apr 21 12:45:57 PM PDT 24
Finished Apr 21 12:46:28 PM PDT 24
Peak memory 215892 kb
Host smart-db906043-bcd9-4cdd-aeab-6693bcbf395f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602014548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3602014548
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1971230267
Short name T4
Test name
Test status
Simulation time 4045379207 ps
CPU time 32.23 seconds
Started Apr 21 12:45:52 PM PDT 24
Finished Apr 21 12:46:25 PM PDT 24
Peak memory 211876 kb
Host smart-5637de69-0ce9-461a-9896-299c426c0a6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1971230267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1971230267
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3323688936
Short name T270
Test name
Test status
Simulation time 7199558260 ps
CPU time 66.44 seconds
Started Apr 21 12:45:56 PM PDT 24
Finished Apr 21 12:47:03 PM PDT 24
Peak memory 218184 kb
Host smart-29ca0fd8-4509-4f24-851e-fd915cc190a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323688936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3323688936
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2874689101
Short name T281
Test name
Test status
Simulation time 3493057450 ps
CPU time 41.63 seconds
Started Apr 21 12:45:48 PM PDT 24
Finished Apr 21 12:46:30 PM PDT 24
Peak memory 214800 kb
Host smart-d72822dc-b98a-4f93-8831-39cc08fc4597
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874689101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2874689101
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2952602480
Short name T82
Test name
Test status
Simulation time 1482322378 ps
CPU time 18.34 seconds
Started Apr 21 12:46:00 PM PDT 24
Finished Apr 21 12:46:19 PM PDT 24
Peak memory 211916 kb
Host smart-35f8a704-c333-41ec-b60a-0c1c733a118f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952602480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2952602480
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2069713300
Short name T334
Test name
Test status
Simulation time 127571381471 ps
CPU time 361.41 seconds
Started Apr 21 12:45:59 PM PDT 24
Finished Apr 21 12:52:02 PM PDT 24
Peak memory 217276 kb
Host smart-225ae8f7-226a-4adb-9313-cb3c3d32464e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069713300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2069713300
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2020788961
Short name T289
Test name
Test status
Simulation time 13728714678 ps
CPU time 60.65 seconds
Started Apr 21 12:45:54 PM PDT 24
Finished Apr 21 12:46:56 PM PDT 24
Peak memory 215600 kb
Host smart-4d93a088-3e48-4d6e-8c6f-125618311b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020788961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2020788961
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1497957964
Short name T157
Test name
Test status
Simulation time 387976448 ps
CPU time 10.53 seconds
Started Apr 21 12:45:43 PM PDT 24
Finished Apr 21 12:45:55 PM PDT 24
Peak memory 212712 kb
Host smart-6304b8ab-c1e7-4c11-9a12-e6a52dcb4535
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1497957964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1497957964
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2778627011
Short name T5
Test name
Test status
Simulation time 16721112203 ps
CPU time 64.01 seconds
Started Apr 21 12:45:51 PM PDT 24
Finished Apr 21 12:46:56 PM PDT 24
Peak memory 218408 kb
Host smart-aeace969-9e3d-47fe-a351-e0333af666e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778627011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2778627011
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.569164089
Short name T186
Test name
Test status
Simulation time 209374348 ps
CPU time 20.89 seconds
Started Apr 21 12:46:03 PM PDT 24
Finished Apr 21 12:46:25 PM PDT 24
Peak memory 211936 kb
Host smart-63fb2d58-4c31-4705-8a4c-afa9338d4087
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569164089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.569164089
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.979955069
Short name T62
Test name
Test status
Simulation time 47740874113 ps
CPU time 1825.62 seconds
Started Apr 21 12:45:57 PM PDT 24
Finished Apr 21 01:16:24 PM PDT 24
Peak memory 245400 kb
Host smart-ab401114-f06f-443e-9b26-a64569d7f77a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979955069 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.979955069
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.752224828
Short name T158
Test name
Test status
Simulation time 22495004316 ps
CPU time 23.26 seconds
Started Apr 21 12:45:48 PM PDT 24
Finished Apr 21 12:46:12 PM PDT 24
Peak memory 212732 kb
Host smart-31f7527f-f3d6-40f7-8669-7aae451826e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752224828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.752224828
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1384880508
Short name T47
Test name
Test status
Simulation time 250615718938 ps
CPU time 699.83 seconds
Started Apr 21 12:45:50 PM PDT 24
Finished Apr 21 12:57:30 PM PDT 24
Peak memory 241068 kb
Host smart-3dff7d08-a1c4-47f0-9b96-3eebb93acaee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384880508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1384880508
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3072699437
Short name T244
Test name
Test status
Simulation time 4781431904 ps
CPU time 47.08 seconds
Started Apr 21 12:45:47 PM PDT 24
Finished Apr 21 12:46:34 PM PDT 24
Peak memory 215512 kb
Host smart-86697761-0a5c-4d76-a0e1-ccb4e7a035f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072699437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3072699437
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2652291098
Short name T291
Test name
Test status
Simulation time 2569574155 ps
CPU time 25.69 seconds
Started Apr 21 12:45:50 PM PDT 24
Finished Apr 21 12:46:17 PM PDT 24
Peak memory 212908 kb
Host smart-20f4af71-3824-4cb7-9c2c-748f718691bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2652291098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2652291098
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2833819372
Short name T272
Test name
Test status
Simulation time 32050636689 ps
CPU time 63.34 seconds
Started Apr 21 12:45:56 PM PDT 24
Finished Apr 21 12:47:01 PM PDT 24
Peak memory 217948 kb
Host smart-00558126-f0e2-4ddc-9e75-7a111a17c782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833819372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2833819372
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1698233946
Short name T211
Test name
Test status
Simulation time 4821826557 ps
CPU time 56.01 seconds
Started Apr 21 12:45:54 PM PDT 24
Finished Apr 21 12:46:51 PM PDT 24
Peak memory 216500 kb
Host smart-a15ae0e5-1962-4190-ba70-5fe96f4d24a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698233946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1698233946
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3147779119
Short name T324
Test name
Test status
Simulation time 51268212286 ps
CPU time 979.43 seconds
Started Apr 21 12:45:50 PM PDT 24
Finished Apr 21 01:02:10 PM PDT 24
Peak memory 236436 kb
Host smart-7a91742a-0916-44a1-a618-02fde63d5e90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147779119 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3147779119
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3840371093
Short name T227
Test name
Test status
Simulation time 7193320017 ps
CPU time 19.56 seconds
Started Apr 21 12:45:55 PM PDT 24
Finished Apr 21 12:46:16 PM PDT 24
Peak memory 212824 kb
Host smart-7928d1e5-f4b0-4daf-93dd-4ae52078a9d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840371093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3840371093
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1600101314
Short name T300
Test name
Test status
Simulation time 2342649147 ps
CPU time 179.42 seconds
Started Apr 21 12:45:57 PM PDT 24
Finished Apr 21 12:48:58 PM PDT 24
Peak memory 229404 kb
Host smart-70ae14fe-37d6-4583-bc5b-bd65f66c3658
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600101314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1600101314
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2410148853
Short name T266
Test name
Test status
Simulation time 30196437479 ps
CPU time 66.53 seconds
Started Apr 21 12:45:48 PM PDT 24
Finished Apr 21 12:46:56 PM PDT 24
Peak memory 215484 kb
Host smart-3e7fbf7a-c6ba-4046-8aa6-41440454db4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410148853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2410148853
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2426872721
Short name T298
Test name
Test status
Simulation time 2350398846 ps
CPU time 14.54 seconds
Started Apr 21 12:45:57 PM PDT 24
Finished Apr 21 12:46:13 PM PDT 24
Peak memory 212336 kb
Host smart-9e6ca994-05b9-438a-adb4-2870d62f8809
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2426872721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2426872721
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.368325839
Short name T3
Test name
Test status
Simulation time 11702609346 ps
CPU time 38.04 seconds
Started Apr 21 12:45:50 PM PDT 24
Finished Apr 21 12:46:29 PM PDT 24
Peak memory 218212 kb
Host smart-0c775044-9236-42e7-9ab3-f0f12fab519a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368325839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.368325839
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1166185069
Short name T351
Test name
Test status
Simulation time 1401922736 ps
CPU time 20.77 seconds
Started Apr 21 12:45:47 PM PDT 24
Finished Apr 21 12:46:09 PM PDT 24
Peak memory 218460 kb
Host smart-9e500ca9-685f-45f1-b16a-e416e86ec496
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166185069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1166185069
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2811325931
Short name T58
Test name
Test status
Simulation time 14938306794 ps
CPU time 585.59 seconds
Started Apr 21 12:45:59 PM PDT 24
Finished Apr 21 12:55:46 PM PDT 24
Peak memory 236352 kb
Host smart-3882fae7-0b11-4f47-9ddc-89dab2d035c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811325931 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.2811325931
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.4140713011
Short name T51
Test name
Test status
Simulation time 2377262598 ps
CPU time 21.58 seconds
Started Apr 21 12:45:56 PM PDT 24
Finished Apr 21 12:46:18 PM PDT 24
Peak memory 212484 kb
Host smart-8b256a72-66a1-4d4e-8fa6-12fcf49219b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140713011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.4140713011
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.441597662
Short name T339
Test name
Test status
Simulation time 283607563085 ps
CPU time 822.45 seconds
Started Apr 21 12:45:44 PM PDT 24
Finished Apr 21 12:59:27 PM PDT 24
Peak memory 239356 kb
Host smart-fc99f96c-92e4-4054-9f94-4bed6565a659
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441597662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.441597662
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4053772862
Short name T223
Test name
Test status
Simulation time 4923593341 ps
CPU time 33.05 seconds
Started Apr 21 12:46:06 PM PDT 24
Finished Apr 21 12:46:40 PM PDT 24
Peak memory 213552 kb
Host smart-cb51097e-88be-4df3-8f61-1c8ce60b1860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053772862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.4053772862
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.578335981
Short name T65
Test name
Test status
Simulation time 30143893838 ps
CPU time 26.63 seconds
Started Apr 21 12:45:52 PM PDT 24
Finished Apr 21 12:46:19 PM PDT 24
Peak memory 212304 kb
Host smart-c05488dd-25ae-420c-aea0-92b464d2ace5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=578335981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.578335981
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1291673058
Short name T312
Test name
Test status
Simulation time 28141012615 ps
CPU time 59.14 seconds
Started Apr 21 12:45:59 PM PDT 24
Finished Apr 21 12:47:00 PM PDT 24
Peak memory 218680 kb
Host smart-3113a701-5321-45eb-83e9-713a2c88e70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291673058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1291673058
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2974412289
Short name T245
Test name
Test status
Simulation time 28601956886 ps
CPU time 43.93 seconds
Started Apr 21 12:45:53 PM PDT 24
Finished Apr 21 12:46:39 PM PDT 24
Peak memory 219952 kb
Host smart-a9dc507f-b93f-4d3d-9e5c-b3e58791571d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974412289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2974412289
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1735136739
Short name T52
Test name
Test status
Simulation time 4719470170 ps
CPU time 22.34 seconds
Started Apr 21 12:45:07 PM PDT 24
Finished Apr 21 12:45:30 PM PDT 24
Peak memory 212548 kb
Host smart-55314fa7-a046-400b-aae9-32b1172ea559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735136739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1735136739
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.4054052062
Short name T219
Test name
Test status
Simulation time 210441248108 ps
CPU time 303.43 seconds
Started Apr 21 12:45:21 PM PDT 24
Finished Apr 21 12:50:25 PM PDT 24
Peak memory 229032 kb
Host smart-10980481-4f36-4853-b241-0a0c1a779bcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054052062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.4054052062
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.573313572
Short name T317
Test name
Test status
Simulation time 10877693530 ps
CPU time 25.57 seconds
Started Apr 21 12:45:22 PM PDT 24
Finished Apr 21 12:45:48 PM PDT 24
Peak memory 211896 kb
Host smart-562f39b6-5c57-4ff7-a241-a68001bbf468
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=573313572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.573313572
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2555402189
Short name T36
Test name
Test status
Simulation time 11644225906 ps
CPU time 132.61 seconds
Started Apr 21 12:45:10 PM PDT 24
Finished Apr 21 12:47:23 PM PDT 24
Peak memory 240240 kb
Host smart-c28f34bc-fe68-404a-9244-86c7e139dc9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555402189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2555402189
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3948445747
Short name T139
Test name
Test status
Simulation time 1410958524 ps
CPU time 19.66 seconds
Started Apr 21 12:45:12 PM PDT 24
Finished Apr 21 12:45:33 PM PDT 24
Peak memory 217868 kb
Host smart-cd988088-12c0-45b2-8355-25593a0206ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948445747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3948445747
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1865800249
Short name T305
Test name
Test status
Simulation time 479338884 ps
CPU time 12.39 seconds
Started Apr 21 12:45:20 PM PDT 24
Finished Apr 21 12:45:33 PM PDT 24
Peak memory 214440 kb
Host smart-57e33420-8c57-4bf2-9549-9f9f56f0ffa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865800249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1865800249
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3364500667
Short name T84
Test name
Test status
Simulation time 6434090462 ps
CPU time 28.59 seconds
Started Apr 21 12:45:52 PM PDT 24
Finished Apr 21 12:46:21 PM PDT 24
Peak memory 212684 kb
Host smart-45c26a1a-86bd-4b24-b997-a5e50a760abd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364500667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3364500667
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3346669774
Short name T21
Test name
Test status
Simulation time 495088169 ps
CPU time 18.73 seconds
Started Apr 21 12:45:56 PM PDT 24
Finished Apr 21 12:46:16 PM PDT 24
Peak memory 215116 kb
Host smart-93fccd74-a0c6-416f-bf16-1a4c441b3514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346669774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3346669774
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3284811013
Short name T195
Test name
Test status
Simulation time 16019668761 ps
CPU time 33.38 seconds
Started Apr 21 12:46:04 PM PDT 24
Finished Apr 21 12:46:39 PM PDT 24
Peak memory 212292 kb
Host smart-3ff680ba-850a-44fb-ba73-5b93b94ec059
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3284811013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3284811013
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3754743963
Short name T328
Test name
Test status
Simulation time 16131151271 ps
CPU time 79.73 seconds
Started Apr 21 12:46:02 PM PDT 24
Finished Apr 21 12:47:22 PM PDT 24
Peak memory 218584 kb
Host smart-fabc6241-08ed-448a-a14f-4af81075360b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754743963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3754743963
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3202005358
Short name T37
Test name
Test status
Simulation time 11455537371 ps
CPU time 37.55 seconds
Started Apr 21 12:45:53 PM PDT 24
Finished Apr 21 12:46:32 PM PDT 24
Peak memory 214776 kb
Host smart-b130c694-7b08-4cfc-a463-76171ee74e62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202005358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3202005358
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2087209611
Short name T283
Test name
Test status
Simulation time 751044874 ps
CPU time 8.3 seconds
Started Apr 21 12:45:53 PM PDT 24
Finished Apr 21 12:46:03 PM PDT 24
Peak memory 211924 kb
Host smart-ecef91bc-bfb7-4574-83a6-a1c2dd0f6ef4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087209611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2087209611
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2162146733
Short name T26
Test name
Test status
Simulation time 37074320379 ps
CPU time 400.09 seconds
Started Apr 21 12:45:53 PM PDT 24
Finished Apr 21 12:52:35 PM PDT 24
Peak memory 234240 kb
Host smart-d809f5dd-d179-447a-bccc-01afdf9e8ac6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162146733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2162146733
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.765109385
Short name T204
Test name
Test status
Simulation time 40855457877 ps
CPU time 66.02 seconds
Started Apr 21 12:45:56 PM PDT 24
Finished Apr 21 12:47:04 PM PDT 24
Peak memory 215640 kb
Host smart-54a08989-d666-463d-b1c0-2cf34732813b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765109385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.765109385
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3828113748
Short name T14
Test name
Test status
Simulation time 6927555408 ps
CPU time 21.48 seconds
Started Apr 21 12:45:57 PM PDT 24
Finished Apr 21 12:46:20 PM PDT 24
Peak memory 211988 kb
Host smart-06095050-36d9-4c1e-ba67-7b92b44871a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3828113748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3828113748
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3022350321
Short name T349
Test name
Test status
Simulation time 13106993018 ps
CPU time 40.48 seconds
Started Apr 21 12:45:53 PM PDT 24
Finished Apr 21 12:46:34 PM PDT 24
Peak memory 217936 kb
Host smart-fd579140-e7fa-4eb2-a9b7-1f9fea6c3d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022350321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3022350321
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3343401058
Short name T307
Test name
Test status
Simulation time 33010959309 ps
CPU time 39.89 seconds
Started Apr 21 12:46:00 PM PDT 24
Finished Apr 21 12:46:41 PM PDT 24
Peak memory 211816 kb
Host smart-29f6ca7f-8c04-4a58-be3b-c3f80f6248c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343401058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3343401058
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4061490470
Short name T162
Test name
Test status
Simulation time 286481351 ps
CPU time 8.38 seconds
Started Apr 21 12:46:07 PM PDT 24
Finished Apr 21 12:46:17 PM PDT 24
Peak memory 211896 kb
Host smart-a4f45c5b-6380-4ce0-9f43-88b460dfa575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061490470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4061490470
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1016620482
Short name T132
Test name
Test status
Simulation time 230127022688 ps
CPU time 382.76 seconds
Started Apr 21 12:45:45 PM PDT 24
Finished Apr 21 12:52:08 PM PDT 24
Peak memory 240976 kb
Host smart-0156ece4-0e1b-4f3e-9dde-00b9002d3585
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016620482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1016620482
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2322090116
Short name T19
Test name
Test status
Simulation time 7517405207 ps
CPU time 44.58 seconds
Started Apr 21 12:45:58 PM PDT 24
Finished Apr 21 12:46:44 PM PDT 24
Peak memory 215504 kb
Host smart-787d27ec-ad87-4578-b2c5-3b18ae90f6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322090116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2322090116
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1052717058
Short name T199
Test name
Test status
Simulation time 3095494093 ps
CPU time 27.54 seconds
Started Apr 21 12:45:45 PM PDT 24
Finished Apr 21 12:46:13 PM PDT 24
Peak memory 211776 kb
Host smart-40b171a8-df6c-4c93-ad2a-9c548e2b1288
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1052717058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1052717058
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1371704839
Short name T134
Test name
Test status
Simulation time 39140065986 ps
CPU time 46.57 seconds
Started Apr 21 12:46:01 PM PDT 24
Finished Apr 21 12:46:48 PM PDT 24
Peak memory 217364 kb
Host smart-88790c36-7097-4494-bc97-5fb08844adc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371704839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1371704839
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2571515896
Short name T189
Test name
Test status
Simulation time 2236893698 ps
CPU time 21.01 seconds
Started Apr 21 12:46:52 PM PDT 24
Finished Apr 21 12:47:14 PM PDT 24
Peak memory 211876 kb
Host smart-dbbd3b87-c2e6-462d-929c-5a74f5a28500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571515896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2571515896
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.947395993
Short name T360
Test name
Test status
Simulation time 31556472540 ps
CPU time 560.09 seconds
Started Apr 21 12:45:58 PM PDT 24
Finished Apr 21 12:55:20 PM PDT 24
Peak memory 236340 kb
Host smart-010f823a-d9f1-4837-95c2-667412b7f4bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947395993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.947395993
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.305122510
Short name T184
Test name
Test status
Simulation time 30492241954 ps
CPU time 46.79 seconds
Started Apr 21 12:45:47 PM PDT 24
Finished Apr 21 12:46:35 PM PDT 24
Peak memory 215500 kb
Host smart-dbf0a823-81f1-4c51-80f6-b0e1427788ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305122510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.305122510
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2731651535
Short name T192
Test name
Test status
Simulation time 944989754 ps
CPU time 16.68 seconds
Started Apr 21 12:45:58 PM PDT 24
Finished Apr 21 12:46:16 PM PDT 24
Peak memory 212824 kb
Host smart-9e42c7b6-aeed-41d8-b175-2f6eeb2c93ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2731651535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2731651535
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3438807605
Short name T2
Test name
Test status
Simulation time 7079838438 ps
CPU time 59.2 seconds
Started Apr 21 12:45:51 PM PDT 24
Finished Apr 21 12:46:51 PM PDT 24
Peak memory 218704 kb
Host smart-86879675-002d-4475-912f-01291755c50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438807605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3438807605
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3456424833
Short name T148
Test name
Test status
Simulation time 3999319455 ps
CPU time 34.8 seconds
Started Apr 21 12:45:58 PM PDT 24
Finished Apr 21 12:46:34 PM PDT 24
Peak memory 219072 kb
Host smart-4d04338e-b8c0-40a3-87e0-6055696a6c80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456424833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3456424833
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3110551077
Short name T202
Test name
Test status
Simulation time 4919299878 ps
CPU time 31.88 seconds
Started Apr 21 12:45:57 PM PDT 24
Finished Apr 21 12:46:30 PM PDT 24
Peak memory 212704 kb
Host smart-0efe7194-6f24-4351-aae7-6881e769b754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110551077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3110551077
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1167617116
Short name T348
Test name
Test status
Simulation time 31440668964 ps
CPU time 63.81 seconds
Started Apr 21 12:46:00 PM PDT 24
Finished Apr 21 12:47:05 PM PDT 24
Peak memory 214760 kb
Host smart-23f54718-962a-4eec-9dee-15e189f1631a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167617116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1167617116
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.717383384
Short name T174
Test name
Test status
Simulation time 6423874669 ps
CPU time 29.8 seconds
Started Apr 21 12:45:59 PM PDT 24
Finished Apr 21 12:46:30 PM PDT 24
Peak memory 213432 kb
Host smart-19e181c1-354c-4fe6-9c08-af1f906b39f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=717383384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.717383384
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1884278513
Short name T22
Test name
Test status
Simulation time 5194408248 ps
CPU time 53.09 seconds
Started Apr 21 12:45:56 PM PDT 24
Finished Apr 21 12:46:50 PM PDT 24
Peak memory 217612 kb
Host smart-3a3c3656-95e9-4fd2-9092-702c48293af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884278513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1884278513
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.68612817
Short name T39
Test name
Test status
Simulation time 13389152815 ps
CPU time 101.36 seconds
Started Apr 21 12:46:00 PM PDT 24
Finished Apr 21 12:47:43 PM PDT 24
Peak memory 220528 kb
Host smart-fd17a0c7-0039-4635-bdd7-be29a8758d59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68612817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 44.rom_ctrl_stress_all.68612817
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2125247638
Short name T292
Test name
Test status
Simulation time 809625833 ps
CPU time 13.97 seconds
Started Apr 21 12:45:56 PM PDT 24
Finished Apr 21 12:46:12 PM PDT 24
Peak memory 211928 kb
Host smart-8296f96d-420a-454a-92dd-f15d1a07ba2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125247638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2125247638
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2827952732
Short name T232
Test name
Test status
Simulation time 4261281141 ps
CPU time 303.38 seconds
Started Apr 21 12:46:03 PM PDT 24
Finished Apr 21 12:51:07 PM PDT 24
Peak memory 238476 kb
Host smart-31c7ce74-a555-4886-9a7f-f4cb341e9bd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827952732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2827952732
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.4139052335
Short name T230
Test name
Test status
Simulation time 12270273678 ps
CPU time 37.99 seconds
Started Apr 21 12:45:47 PM PDT 24
Finished Apr 21 12:46:26 PM PDT 24
Peak memory 215576 kb
Host smart-a2dea38a-b9cd-40d6-8f4c-177d1ee50d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139052335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.4139052335
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4236285707
Short name T117
Test name
Test status
Simulation time 357011748 ps
CPU time 10.46 seconds
Started Apr 21 12:45:59 PM PDT 24
Finished Apr 21 12:46:11 PM PDT 24
Peak memory 212788 kb
Host smart-436f3411-d61a-4d01-b684-c8bf8092243f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4236285707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4236285707
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3058542465
Short name T343
Test name
Test status
Simulation time 57325019576 ps
CPU time 62.12 seconds
Started Apr 21 12:46:01 PM PDT 24
Finished Apr 21 12:47:04 PM PDT 24
Peak memory 218240 kb
Host smart-086f5511-98e3-448b-a68d-467ff8aa18c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058542465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3058542465
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.543931395
Short name T178
Test name
Test status
Simulation time 8288151770 ps
CPU time 58 seconds
Started Apr 21 12:45:50 PM PDT 24
Finished Apr 21 12:46:49 PM PDT 24
Peak memory 219848 kb
Host smart-c0543563-1cc3-472b-af3b-b66dc3829875
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543931395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.543931395
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.261383428
Short name T17
Test name
Test status
Simulation time 19804935329 ps
CPU time 1484.4 seconds
Started Apr 21 12:45:46 PM PDT 24
Finished Apr 21 01:10:31 PM PDT 24
Peak memory 236424 kb
Host smart-29950964-6c81-4641-bdae-88962449ed18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261383428 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.261383428
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.151986021
Short name T222
Test name
Test status
Simulation time 339248088 ps
CPU time 8.35 seconds
Started Apr 21 12:45:58 PM PDT 24
Finished Apr 21 12:46:08 PM PDT 24
Peak memory 211944 kb
Host smart-8d476b2c-863f-4dbc-bd38-3f0489d4f548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151986021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.151986021
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4284279309
Short name T231
Test name
Test status
Simulation time 4180856927 ps
CPU time 263.74 seconds
Started Apr 21 12:45:54 PM PDT 24
Finished Apr 21 12:50:19 PM PDT 24
Peak memory 217380 kb
Host smart-cd011773-ea65-4bc6-965d-f3ed3bcca106
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284279309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4284279309
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.157595055
Short name T321
Test name
Test status
Simulation time 7937768375 ps
CPU time 61.36 seconds
Started Apr 21 12:45:55 PM PDT 24
Finished Apr 21 12:46:57 PM PDT 24
Peak memory 215940 kb
Host smart-ec1c0843-4149-41b5-9513-0a923de40a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157595055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.157595055
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.4092673932
Short name T165
Test name
Test status
Simulation time 1412767652 ps
CPU time 19.92 seconds
Started Apr 21 12:46:03 PM PDT 24
Finished Apr 21 12:46:24 PM PDT 24
Peak memory 218096 kb
Host smart-ba16a8f4-04e7-4e5c-a788-652374390afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092673932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.4092673932
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3663497287
Short name T263
Test name
Test status
Simulation time 16048329465 ps
CPU time 105.81 seconds
Started Apr 21 12:46:06 PM PDT 24
Finished Apr 21 12:47:53 PM PDT 24
Peak memory 221692 kb
Host smart-19ef0ae4-c2df-443c-be80-c8aae5e0b3c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663497287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3663497287
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2072076936
Short name T149
Test name
Test status
Simulation time 5839241198 ps
CPU time 26.7 seconds
Started Apr 21 12:46:04 PM PDT 24
Finished Apr 21 12:46:33 PM PDT 24
Peak memory 212812 kb
Host smart-c4349b99-0259-47c0-9298-afe891db428c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072076936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2072076936
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1005563750
Short name T25
Test name
Test status
Simulation time 31841368994 ps
CPU time 172.23 seconds
Started Apr 21 12:46:05 PM PDT 24
Finished Apr 21 12:48:59 PM PDT 24
Peak memory 241376 kb
Host smart-fa9af4ae-a1f5-456f-9400-c530d58e48a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005563750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1005563750
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.338894119
Short name T24
Test name
Test status
Simulation time 37381767662 ps
CPU time 65.98 seconds
Started Apr 21 12:46:03 PM PDT 24
Finished Apr 21 12:47:10 PM PDT 24
Peak memory 215572 kb
Host smart-05792fb3-e05b-4451-8f91-d974c3f15b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338894119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.338894119
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2534434775
Short name T228
Test name
Test status
Simulation time 1100378104 ps
CPU time 15.65 seconds
Started Apr 21 12:46:02 PM PDT 24
Finished Apr 21 12:46:19 PM PDT 24
Peak memory 212656 kb
Host smart-f05d2f44-79f8-4b8a-9af6-5c8066c1b92b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2534434775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2534434775
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1603016097
Short name T293
Test name
Test status
Simulation time 41098149656 ps
CPU time 141.9 seconds
Started Apr 21 12:46:04 PM PDT 24
Finished Apr 21 12:48:28 PM PDT 24
Peak memory 219868 kb
Host smart-c6faf1b4-87ff-441d-85d6-a41a7ee5631b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603016097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1603016097
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3783136167
Short name T215
Test name
Test status
Simulation time 59726317143 ps
CPU time 33.14 seconds
Started Apr 21 12:46:07 PM PDT 24
Finished Apr 21 12:46:41 PM PDT 24
Peak memory 212940 kb
Host smart-e85c2a63-7c27-4389-9824-0f8d45a98d07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783136167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3783136167
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2217008294
Short name T150
Test name
Test status
Simulation time 42640760376 ps
CPU time 411.02 seconds
Started Apr 21 12:46:00 PM PDT 24
Finished Apr 21 12:52:52 PM PDT 24
Peak memory 234436 kb
Host smart-05a7969f-5e25-4441-8535-c098ae99c11f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217008294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2217008294
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.4255568609
Short name T359
Test name
Test status
Simulation time 17761098018 ps
CPU time 46.43 seconds
Started Apr 21 12:46:04 PM PDT 24
Finished Apr 21 12:46:52 PM PDT 24
Peak memory 215508 kb
Host smart-e0f06cbc-44c9-4eaa-84be-3fc2bce24652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255568609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.4255568609
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.645947309
Short name T310
Test name
Test status
Simulation time 353546232 ps
CPU time 10.62 seconds
Started Apr 21 12:45:56 PM PDT 24
Finished Apr 21 12:46:08 PM PDT 24
Peak memory 212756 kb
Host smart-f313f8e9-c57b-4f41-9e20-d44ad5bc5917
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=645947309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.645947309
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3137359240
Short name T137
Test name
Test status
Simulation time 5673771809 ps
CPU time 51.22 seconds
Started Apr 21 12:46:08 PM PDT 24
Finished Apr 21 12:47:00 PM PDT 24
Peak memory 218148 kb
Host smart-4d56d8fb-d226-4165-bfa6-dd7df1e16182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137359240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3137359240
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2927922992
Short name T8
Test name
Test status
Simulation time 2974484098 ps
CPU time 12.89 seconds
Started Apr 21 12:46:03 PM PDT 24
Finished Apr 21 12:46:17 PM PDT 24
Peak memory 212036 kb
Host smart-9b84b47c-2689-4f2d-a78c-9e6e8b92a2b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927922992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2927922992
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3906452849
Short name T287
Test name
Test status
Simulation time 44456464295 ps
CPU time 379.71 seconds
Started Apr 21 12:46:07 PM PDT 24
Finished Apr 21 12:52:27 PM PDT 24
Peak memory 225820 kb
Host smart-aa117f9c-92af-4c3b-86b1-17dca04bc3dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906452849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3906452849
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1582072578
Short name T225
Test name
Test status
Simulation time 1572306069 ps
CPU time 19.29 seconds
Started Apr 21 12:45:57 PM PDT 24
Finished Apr 21 12:46:18 PM PDT 24
Peak memory 215164 kb
Host smart-a4d2ab1f-3be6-4f1e-9ad6-a4fb9cb82700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582072578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1582072578
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1647166738
Short name T258
Test name
Test status
Simulation time 5126083488 ps
CPU time 25.37 seconds
Started Apr 21 12:46:07 PM PDT 24
Finished Apr 21 12:46:33 PM PDT 24
Peak memory 212016 kb
Host smart-38684375-dee9-45a0-a32c-a7c83b6b8eb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647166738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1647166738
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3631015982
Short name T180
Test name
Test status
Simulation time 55985982998 ps
CPU time 92.38 seconds
Started Apr 21 12:46:04 PM PDT 24
Finished Apr 21 12:47:38 PM PDT 24
Peak memory 219916 kb
Host smart-e757b87e-698c-43c1-acaf-15270389e86c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631015982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3631015982
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.696447696
Short name T183
Test name
Test status
Simulation time 1485731507 ps
CPU time 18.19 seconds
Started Apr 21 12:45:19 PM PDT 24
Finished Apr 21 12:45:38 PM PDT 24
Peak memory 211884 kb
Host smart-b4216aba-fc57-4d1b-b0bd-86a6fa2ec9af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696447696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.696447696
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1216754137
Short name T224
Test name
Test status
Simulation time 286396818235 ps
CPU time 665.05 seconds
Started Apr 21 12:45:22 PM PDT 24
Finished Apr 21 12:56:27 PM PDT 24
Peak memory 228812 kb
Host smart-c2fcd1f7-b2f6-4896-9fd0-bb2c7482851e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216754137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1216754137
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1428537396
Short name T152
Test name
Test status
Simulation time 5613287826 ps
CPU time 52.85 seconds
Started Apr 21 12:45:22 PM PDT 24
Finished Apr 21 12:46:15 PM PDT 24
Peak memory 215672 kb
Host smart-792f5074-7555-4490-b39c-2b24e366056a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428537396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1428537396
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.172148521
Short name T166
Test name
Test status
Simulation time 10915300886 ps
CPU time 26.32 seconds
Started Apr 21 12:45:20 PM PDT 24
Finished Apr 21 12:45:47 PM PDT 24
Peak memory 212320 kb
Host smart-e0cb402a-1c48-4b3f-81ef-2439ac02e89b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=172148521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.172148521
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3203587862
Short name T79
Test name
Test status
Simulation time 8105321295 ps
CPU time 66.16 seconds
Started Apr 21 12:45:36 PM PDT 24
Finished Apr 21 12:46:43 PM PDT 24
Peak memory 218008 kb
Host smart-51966ba8-94bf-46f4-ae1f-63799d42476e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203587862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3203587862
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.4232058659
Short name T273
Test name
Test status
Simulation time 26975613200 ps
CPU time 269.79 seconds
Started Apr 21 12:45:09 PM PDT 24
Finished Apr 21 12:49:39 PM PDT 24
Peak memory 222032 kb
Host smart-9e1beb90-4a23-48de-924b-d6ee04bb7edc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232058659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.4232058659
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2178293319
Short name T269
Test name
Test status
Simulation time 167760828 ps
CPU time 8.55 seconds
Started Apr 21 12:45:34 PM PDT 24
Finished Apr 21 12:45:43 PM PDT 24
Peak memory 211868 kb
Host smart-7aa0005e-f552-4f0b-b5da-1492baf53a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178293319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2178293319
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3643108440
Short name T188
Test name
Test status
Simulation time 21900789670 ps
CPU time 364.41 seconds
Started Apr 21 12:45:25 PM PDT 24
Finished Apr 21 12:51:30 PM PDT 24
Peak memory 240416 kb
Host smart-cfafcdf8-4718-43a8-89ef-8d6324994246
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643108440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3643108440
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.4154605264
Short name T262
Test name
Test status
Simulation time 23252971655 ps
CPU time 53.47 seconds
Started Apr 21 12:45:26 PM PDT 24
Finished Apr 21 12:46:25 PM PDT 24
Peak memory 215580 kb
Host smart-384026f2-7106-45a5-9e11-13523d6cdc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154605264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.4154605264
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2971381955
Short name T311
Test name
Test status
Simulation time 29005230509 ps
CPU time 25.02 seconds
Started Apr 21 12:45:28 PM PDT 24
Finished Apr 21 12:45:54 PM PDT 24
Peak memory 213400 kb
Host smart-241f53eb-11ef-49cc-98f4-77319272cabd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2971381955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2971381955
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3932666559
Short name T136
Test name
Test status
Simulation time 23651211149 ps
CPU time 44 seconds
Started Apr 21 12:45:32 PM PDT 24
Finished Apr 21 12:46:17 PM PDT 24
Peak memory 218688 kb
Host smart-36c5567c-266f-4a3e-be0a-1fdcc89bb73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932666559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3932666559
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1503555655
Short name T93
Test name
Test status
Simulation time 1075106508 ps
CPU time 38.03 seconds
Started Apr 21 12:45:20 PM PDT 24
Finished Apr 21 12:45:58 PM PDT 24
Peak memory 215892 kb
Host smart-6a9c7c3c-d01b-43a5-99c7-dc784ed9c6fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503555655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1503555655
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.4131794203
Short name T254
Test name
Test status
Simulation time 1270181461 ps
CPU time 8.39 seconds
Started Apr 21 12:45:22 PM PDT 24
Finished Apr 21 12:45:31 PM PDT 24
Peak memory 211860 kb
Host smart-578adbc2-1b46-471b-8bce-734f8fe7b3f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131794203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.4131794203
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1376615605
Short name T330
Test name
Test status
Simulation time 86872613545 ps
CPU time 352.44 seconds
Started Apr 21 12:45:31 PM PDT 24
Finished Apr 21 12:51:24 PM PDT 24
Peak memory 230316 kb
Host smart-46618813-d731-4f98-af42-9ef922b61e71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376615605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1376615605
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2833108147
Short name T201
Test name
Test status
Simulation time 1842401320 ps
CPU time 19.38 seconds
Started Apr 21 12:45:27 PM PDT 24
Finished Apr 21 12:45:47 PM PDT 24
Peak memory 217196 kb
Host smart-a07759f0-50a3-4d94-9665-432016a3976d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833108147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2833108147
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1628591912
Short name T358
Test name
Test status
Simulation time 357980964 ps
CPU time 10.07 seconds
Started Apr 21 12:45:28 PM PDT 24
Finished Apr 21 12:45:38 PM PDT 24
Peak memory 211884 kb
Host smart-8a66ecf6-b88c-4658-9ab6-1fda18aa335a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1628591912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1628591912
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.531289051
Short name T191
Test name
Test status
Simulation time 8958211222 ps
CPU time 33.91 seconds
Started Apr 21 12:45:11 PM PDT 24
Finished Apr 21 12:45:46 PM PDT 24
Peak memory 218772 kb
Host smart-518b29ae-acff-48c5-ba3b-1a625ef9b7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531289051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.531289051
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.191463492
Short name T241
Test name
Test status
Simulation time 41157093766 ps
CPU time 91.4 seconds
Started Apr 21 12:45:13 PM PDT 24
Finished Apr 21 12:46:45 PM PDT 24
Peak memory 220796 kb
Host smart-1254b82a-8b99-4ea8-b46a-66eb07f37cae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191463492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.191463492
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1054602084
Short name T282
Test name
Test status
Simulation time 174268892 ps
CPU time 8.23 seconds
Started Apr 21 12:45:31 PM PDT 24
Finished Apr 21 12:45:39 PM PDT 24
Peak memory 211820 kb
Host smart-34e768b2-4c19-44ed-923a-6d7419a102f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054602084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1054602084
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3433387114
Short name T216
Test name
Test status
Simulation time 115044410671 ps
CPU time 562.2 seconds
Started Apr 21 12:45:18 PM PDT 24
Finished Apr 21 12:54:41 PM PDT 24
Peak memory 230340 kb
Host smart-05a9b971-6cef-4a9b-863b-c390cd83270e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433387114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3433387114
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.703913640
Short name T160
Test name
Test status
Simulation time 24985558578 ps
CPU time 60.17 seconds
Started Apr 21 12:45:25 PM PDT 24
Finished Apr 21 12:46:25 PM PDT 24
Peak memory 214556 kb
Host smart-4fbf1e02-ae19-45ff-9636-d7916999ce39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703913640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.703913640
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3253375964
Short name T171
Test name
Test status
Simulation time 434133259 ps
CPU time 13.54 seconds
Started Apr 21 12:45:26 PM PDT 24
Finished Apr 21 12:45:40 PM PDT 24
Peak memory 211708 kb
Host smart-ae3ae8ab-d6b7-44c9-a89a-4fd4cffa45f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3253375964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3253375964
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.995923612
Short name T243
Test name
Test status
Simulation time 10555237108 ps
CPU time 40.38 seconds
Started Apr 21 12:45:30 PM PDT 24
Finished Apr 21 12:46:11 PM PDT 24
Peak memory 217804 kb
Host smart-1b6922d7-2c5d-466c-8604-5adafb6507bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995923612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.995923612
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.760439523
Short name T251
Test name
Test status
Simulation time 7087683841 ps
CPU time 89.42 seconds
Started Apr 21 12:45:27 PM PDT 24
Finished Apr 21 12:47:01 PM PDT 24
Peak memory 220100 kb
Host smart-6b28ced8-e3b6-4358-a124-55195246c592
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760439523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.760439523
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3909023328
Short name T154
Test name
Test status
Simulation time 660569992 ps
CPU time 8.6 seconds
Started Apr 21 12:45:33 PM PDT 24
Finished Apr 21 12:45:42 PM PDT 24
Peak memory 211824 kb
Host smart-3c427b8f-05a6-4755-a86e-af245da23eec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909023328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3909023328
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.972862737
Short name T331
Test name
Test status
Simulation time 126376002264 ps
CPU time 673.04 seconds
Started Apr 21 12:45:13 PM PDT 24
Finished Apr 21 12:56:26 PM PDT 24
Peak memory 225544 kb
Host smart-e1e736ba-b167-42b0-aaba-1ff314b6dd86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972862737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.972862737
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2870532805
Short name T313
Test name
Test status
Simulation time 26739480207 ps
CPU time 53.91 seconds
Started Apr 21 12:45:25 PM PDT 24
Finished Apr 21 12:46:19 PM PDT 24
Peak memory 214976 kb
Host smart-fccf311a-435c-45d1-8475-9cf68728b848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870532805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2870532805
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3807724933
Short name T285
Test name
Test status
Simulation time 14306115315 ps
CPU time 23.54 seconds
Started Apr 21 12:45:35 PM PDT 24
Finished Apr 21 12:46:05 PM PDT 24
Peak memory 212080 kb
Host smart-4ef80849-6bde-4b91-8fa0-e6fc26fe35cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3807724933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3807724933
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2589181448
Short name T356
Test name
Test status
Simulation time 6418609105 ps
CPU time 59.75 seconds
Started Apr 21 12:45:20 PM PDT 24
Finished Apr 21 12:46:20 PM PDT 24
Peak memory 217192 kb
Host smart-3a5a8baa-76cf-4a43-b114-0368cf5543e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589181448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2589181448
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.933882781
Short name T234
Test name
Test status
Simulation time 73684981334 ps
CPU time 71.83 seconds
Started Apr 21 12:45:35 PM PDT 24
Finished Apr 21 12:46:48 PM PDT 24
Peak memory 218348 kb
Host smart-704fb2a9-72d3-480a-9b71-be38f4b0605f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933882781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.933882781
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1335797502
Short name T56
Test name
Test status
Simulation time 25683623874 ps
CPU time 1087.08 seconds
Started Apr 21 12:45:32 PM PDT 24
Finished Apr 21 01:03:40 PM PDT 24
Peak memory 233884 kb
Host smart-7984812b-a329-4550-a75f-b7225f3f2cb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335797502 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.1335797502
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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