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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.50 96.97 93.01 97.88 100.00 98.37 97.88 98.37


Total test records in report: 452
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T304 /workspace/coverage/default/46.rom_ctrl_stress_all.781380764 Apr 23 02:40:12 PM PDT 24 Apr 23 02:41:03 PM PDT 24 10598453095 ps
T305 /workspace/coverage/default/36.rom_ctrl_smoke.2207768508 Apr 23 02:40:03 PM PDT 24 Apr 23 02:41:24 PM PDT 24 35532503446 ps
T306 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.672654011 Apr 23 02:39:28 PM PDT 24 Apr 23 02:39:39 PM PDT 24 357014987 ps
T307 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1370408369 Apr 23 02:39:52 PM PDT 24 Apr 23 02:40:24 PM PDT 24 7844028939 ps
T308 /workspace/coverage/default/47.rom_ctrl_smoke.3354542235 Apr 23 02:40:14 PM PDT 24 Apr 23 02:41:23 PM PDT 24 34264292637 ps
T309 /workspace/coverage/default/41.rom_ctrl_stress_all.2602296980 Apr 23 02:40:09 PM PDT 24 Apr 23 02:41:14 PM PDT 24 15869770958 ps
T310 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1175946844 Apr 23 02:40:17 PM PDT 24 Apr 23 02:41:00 PM PDT 24 4001053538 ps
T311 /workspace/coverage/default/48.rom_ctrl_stress_all.1300324454 Apr 23 02:40:15 PM PDT 24 Apr 23 02:41:07 PM PDT 24 3875156186 ps
T312 /workspace/coverage/default/13.rom_ctrl_stress_all.1915376213 Apr 23 02:39:32 PM PDT 24 Apr 23 02:40:25 PM PDT 24 860172470 ps
T313 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1128134027 Apr 23 02:39:59 PM PDT 24 Apr 23 02:40:31 PM PDT 24 3709797186 ps
T314 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1700138239 Apr 23 02:39:48 PM PDT 24 Apr 23 02:45:42 PM PDT 24 108478271909 ps
T315 /workspace/coverage/default/14.rom_ctrl_stress_all.87226944 Apr 23 02:39:34 PM PDT 24 Apr 23 02:40:55 PM PDT 24 13780993792 ps
T316 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2382463084 Apr 23 02:39:15 PM PDT 24 Apr 23 02:40:03 PM PDT 24 4844854880 ps
T317 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.703427419 Apr 23 02:39:27 PM PDT 24 Apr 23 02:40:33 PM PDT 24 8006556900 ps
T318 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3347854874 Apr 23 02:39:28 PM PDT 24 Apr 23 02:48:29 PM PDT 24 39319337717 ps
T319 /workspace/coverage/default/10.rom_ctrl_smoke.1683534571 Apr 23 02:39:20 PM PDT 24 Apr 23 02:39:59 PM PDT 24 21443261827 ps
T320 /workspace/coverage/default/7.rom_ctrl_smoke.437677586 Apr 23 02:39:16 PM PDT 24 Apr 23 02:39:58 PM PDT 24 7263930733 ps
T37 /workspace/coverage/default/3.rom_ctrl_sec_cm.2632300013 Apr 23 02:39:15 PM PDT 24 Apr 23 02:41:39 PM PDT 24 4579435447 ps
T321 /workspace/coverage/default/0.rom_ctrl_alert_test.2146539281 Apr 23 02:39:05 PM PDT 24 Apr 23 02:39:38 PM PDT 24 4342985403 ps
T322 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3344278217 Apr 23 02:39:18 PM PDT 24 Apr 23 02:39:43 PM PDT 24 2587126562 ps
T323 /workspace/coverage/default/23.rom_ctrl_alert_test.3300424609 Apr 23 02:39:45 PM PDT 24 Apr 23 02:39:54 PM PDT 24 167538828 ps
T324 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3449846732 Apr 23 02:40:15 PM PDT 24 Apr 23 02:53:24 PM PDT 24 68373427934 ps
T325 /workspace/coverage/default/8.rom_ctrl_alert_test.979078168 Apr 23 02:39:16 PM PDT 24 Apr 23 02:39:37 PM PDT 24 9332019261 ps
T326 /workspace/coverage/default/7.rom_ctrl_alert_test.2468238363 Apr 23 02:39:17 PM PDT 24 Apr 23 02:39:40 PM PDT 24 9149800848 ps
T327 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3327512841 Apr 23 02:40:17 PM PDT 24 Apr 23 02:40:50 PM PDT 24 19500038133 ps
T328 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.13911207 Apr 23 02:39:35 PM PDT 24 Apr 23 02:43:06 PM PDT 24 4498960590 ps
T329 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.240450441 Apr 23 02:39:08 PM PDT 24 Apr 23 02:40:14 PM PDT 24 8218633893 ps
T330 /workspace/coverage/default/2.rom_ctrl_stress_all.2520593637 Apr 23 02:39:13 PM PDT 24 Apr 23 02:40:18 PM PDT 24 23709342033 ps
T331 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2174506830 Apr 23 02:39:24 PM PDT 24 Apr 23 02:49:52 PM PDT 24 258336664564 ps
T332 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1907665261 Apr 23 02:39:48 PM PDT 24 Apr 23 02:39:58 PM PDT 24 374139051 ps
T333 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.670730830 Apr 23 02:39:34 PM PDT 24 Apr 23 02:39:53 PM PDT 24 688577574 ps
T334 /workspace/coverage/default/3.rom_ctrl_alert_test.458997078 Apr 23 02:39:17 PM PDT 24 Apr 23 02:39:43 PM PDT 24 26357196164 ps
T335 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.324626810 Apr 23 02:40:06 PM PDT 24 Apr 23 02:41:06 PM PDT 24 7100167651 ps
T336 /workspace/coverage/default/19.rom_ctrl_alert_test.2266341212 Apr 23 02:39:35 PM PDT 24 Apr 23 02:40:08 PM PDT 24 19697454016 ps
T337 /workspace/coverage/default/24.rom_ctrl_alert_test.2954063675 Apr 23 02:39:37 PM PDT 24 Apr 23 02:39:48 PM PDT 24 257369711 ps
T338 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3591440004 Apr 23 02:39:31 PM PDT 24 Apr 23 02:39:51 PM PDT 24 674789262 ps
T339 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3332978251 Apr 23 02:39:25 PM PDT 24 Apr 23 02:40:16 PM PDT 24 23109616072 ps
T340 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3590975385 Apr 23 02:39:26 PM PDT 24 Apr 23 02:40:05 PM PDT 24 34771348704 ps
T341 /workspace/coverage/default/18.rom_ctrl_stress_all.1490175335 Apr 23 02:39:28 PM PDT 24 Apr 23 02:40:22 PM PDT 24 4287744481 ps
T342 /workspace/coverage/default/41.rom_ctrl_smoke.2766554437 Apr 23 02:40:07 PM PDT 24 Apr 23 02:40:40 PM PDT 24 1632095869 ps
T343 /workspace/coverage/default/28.rom_ctrl_stress_all.3698944612 Apr 23 02:39:45 PM PDT 24 Apr 23 02:41:00 PM PDT 24 2225448462 ps
T344 /workspace/coverage/default/9.rom_ctrl_stress_all.2376397817 Apr 23 02:39:16 PM PDT 24 Apr 23 02:39:51 PM PDT 24 2947745299 ps
T345 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1330152943 Apr 23 02:39:33 PM PDT 24 Apr 23 02:39:46 PM PDT 24 271347877 ps
T346 /workspace/coverage/default/4.rom_ctrl_smoke.2628956195 Apr 23 02:39:10 PM PDT 24 Apr 23 02:40:17 PM PDT 24 16479186848 ps
T347 /workspace/coverage/default/9.rom_ctrl_alert_test.3442820214 Apr 23 02:39:22 PM PDT 24 Apr 23 02:39:31 PM PDT 24 517370296 ps
T348 /workspace/coverage/default/42.rom_ctrl_stress_all.2887845936 Apr 23 02:40:04 PM PDT 24 Apr 23 02:41:32 PM PDT 24 34682552954 ps
T349 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1267154450 Apr 23 02:39:56 PM PDT 24 Apr 23 02:40:24 PM PDT 24 5761166438 ps
T350 /workspace/coverage/default/39.rom_ctrl_smoke.3794670332 Apr 23 02:40:04 PM PDT 24 Apr 23 02:40:49 PM PDT 24 3585903660 ps
T351 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.583775612 Apr 23 02:40:13 PM PDT 24 Apr 23 02:46:40 PM PDT 24 102702227823 ps
T352 /workspace/coverage/default/20.rom_ctrl_alert_test.370632429 Apr 23 02:39:33 PM PDT 24 Apr 23 02:39:42 PM PDT 24 167560012 ps
T353 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.200756490 Apr 23 02:40:14 PM PDT 24 Apr 23 02:42:45 PM PDT 24 11070072495 ps
T354 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3176966005 Apr 23 02:39:33 PM PDT 24 Apr 23 02:43:58 PM PDT 24 5068288544 ps
T355 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1559128636 Apr 23 02:40:09 PM PDT 24 Apr 23 02:40:41 PM PDT 24 17697638598 ps
T356 /workspace/coverage/default/30.rom_ctrl_alert_test.3399613517 Apr 23 02:39:48 PM PDT 24 Apr 23 02:40:20 PM PDT 24 8195260436 ps
T357 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4239440847 Apr 23 02:39:19 PM PDT 24 Apr 23 02:40:26 PM PDT 24 87115463643 ps
T358 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.4073995037 Apr 23 02:39:59 PM PDT 24 Apr 23 02:40:56 PM PDT 24 32780490048 ps
T359 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3119011278 Apr 23 02:39:35 PM PDT 24 Apr 23 02:54:22 PM PDT 24 361589673579 ps
T52 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1807642045 Apr 23 02:38:58 PM PDT 24 Apr 23 02:39:12 PM PDT 24 792790363 ps
T53 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2354780496 Apr 23 02:38:56 PM PDT 24 Apr 23 02:39:57 PM PDT 24 6749135747 ps
T54 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1798567165 Apr 23 02:39:12 PM PDT 24 Apr 23 02:39:45 PM PDT 24 27240813658 ps
T360 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1787875251 Apr 23 02:38:50 PM PDT 24 Apr 23 02:38:59 PM PDT 24 533003572 ps
T92 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1049602721 Apr 23 02:39:04 PM PDT 24 Apr 23 02:40:04 PM PDT 24 6888035884 ps
T93 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2122128403 Apr 23 02:39:05 PM PDT 24 Apr 23 02:39:31 PM PDT 24 4040496560 ps
T46 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1064125668 Apr 23 02:39:03 PM PDT 24 Apr 23 02:39:22 PM PDT 24 683871266 ps
T47 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4293089002 Apr 23 02:39:10 PM PDT 24 Apr 23 02:42:04 PM PDT 24 3587405718 ps
T48 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2112266864 Apr 23 02:39:14 PM PDT 24 Apr 23 02:39:27 PM PDT 24 331663478 ps
T94 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.446826277 Apr 23 02:38:55 PM PDT 24 Apr 23 02:39:14 PM PDT 24 1161605485 ps
T61 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3404534878 Apr 23 02:39:07 PM PDT 24 Apr 23 02:39:31 PM PDT 24 2611542546 ps
T60 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4288377030 Apr 23 02:38:57 PM PDT 24 Apr 23 02:39:07 PM PDT 24 466244012 ps
T62 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1294000280 Apr 23 02:39:03 PM PDT 24 Apr 23 02:39:34 PM PDT 24 4090318152 ps
T361 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.55866960 Apr 23 02:39:11 PM PDT 24 Apr 23 02:39:25 PM PDT 24 1818981810 ps
T84 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3043435137 Apr 23 02:39:11 PM PDT 24 Apr 23 02:39:35 PM PDT 24 2786461987 ps
T362 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.36690519 Apr 23 02:38:55 PM PDT 24 Apr 23 02:39:09 PM PDT 24 1730150136 ps
T85 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3102788167 Apr 23 02:38:57 PM PDT 24 Apr 23 02:39:06 PM PDT 24 687930593 ps
T49 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.187778301 Apr 23 02:38:51 PM PDT 24 Apr 23 02:40:24 PM PDT 24 2410369810 ps
T363 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2045344395 Apr 23 02:38:49 PM PDT 24 Apr 23 02:39:21 PM PDT 24 4469577794 ps
T86 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3153820778 Apr 23 02:38:52 PM PDT 24 Apr 23 02:39:01 PM PDT 24 169150644 ps
T63 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3283507730 Apr 23 02:38:57 PM PDT 24 Apr 23 02:39:09 PM PDT 24 1641149046 ps
T364 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2012123235 Apr 23 02:39:12 PM PDT 24 Apr 23 02:39:24 PM PDT 24 1011579539 ps
T87 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1200600461 Apr 23 02:38:59 PM PDT 24 Apr 23 02:41:03 PM PDT 24 30749094980 ps
T365 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4148210472 Apr 23 02:38:56 PM PDT 24 Apr 23 02:39:25 PM PDT 24 3510409322 ps
T366 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2756215122 Apr 23 02:38:55 PM PDT 24 Apr 23 02:39:23 PM PDT 24 3334730739 ps
T367 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3312147478 Apr 23 02:39:15 PM PDT 24 Apr 23 02:39:24 PM PDT 24 810903623 ps
T88 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3988570342 Apr 23 02:39:06 PM PDT 24 Apr 23 02:39:26 PM PDT 24 1893259476 ps
T50 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.168477064 Apr 23 02:39:11 PM PDT 24 Apr 23 02:40:42 PM PDT 24 7150101819 ps
T64 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3519028412 Apr 23 02:38:51 PM PDT 24 Apr 23 02:41:08 PM PDT 24 17435065615 ps
T368 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.514443866 Apr 23 02:39:00 PM PDT 24 Apr 23 02:39:16 PM PDT 24 4937831351 ps
T369 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1033138828 Apr 23 02:39:11 PM PDT 24 Apr 23 02:39:43 PM PDT 24 7011274292 ps
T97 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.491805111 Apr 23 02:38:45 PM PDT 24 Apr 23 02:40:17 PM PDT 24 7157942475 ps
T89 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3354399468 Apr 23 02:39:11 PM PDT 24 Apr 23 02:39:32 PM PDT 24 2720992122 ps
T370 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.319282296 Apr 23 02:38:55 PM PDT 24 Apr 23 02:39:08 PM PDT 24 1821385451 ps
T371 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2725593618 Apr 23 02:39:03 PM PDT 24 Apr 23 02:39:23 PM PDT 24 6882421043 ps
T102 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2632301931 Apr 23 02:39:14 PM PDT 24 Apr 23 02:40:46 PM PDT 24 7659217987 ps
T90 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2328439868 Apr 23 02:39:07 PM PDT 24 Apr 23 02:41:23 PM PDT 24 106860724145 ps
T372 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3698322757 Apr 23 02:39:06 PM PDT 24 Apr 23 02:39:15 PM PDT 24 174412298 ps
T98 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2838787621 Apr 23 02:39:11 PM PDT 24 Apr 23 02:40:31 PM PDT 24 982152326 ps
T91 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1221483215 Apr 23 02:39:07 PM PDT 24 Apr 23 02:39:35 PM PDT 24 2531996833 ps
T65 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1681409264 Apr 23 02:39:12 PM PDT 24 Apr 23 02:39:20 PM PDT 24 170959838 ps
T103 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.919852817 Apr 23 02:39:01 PM PDT 24 Apr 23 02:41:57 PM PDT 24 33839748355 ps
T373 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3103086990 Apr 23 02:39:00 PM PDT 24 Apr 23 02:39:28 PM PDT 24 3358724067 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2071595173 Apr 23 02:38:55 PM PDT 24 Apr 23 02:39:21 PM PDT 24 58645715289 ps
T375 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3606856694 Apr 23 02:39:15 PM PDT 24 Apr 23 02:39:39 PM PDT 24 13726927556 ps
T66 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3707433084 Apr 23 02:38:59 PM PDT 24 Apr 23 02:39:25 PM PDT 24 2872298688 ps
T376 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4284068517 Apr 23 02:38:49 PM PDT 24 Apr 23 02:39:05 PM PDT 24 19936052111 ps
T377 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1583471707 Apr 23 02:39:10 PM PDT 24 Apr 23 02:39:21 PM PDT 24 502339910 ps
T378 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3208987727 Apr 23 02:39:15 PM PDT 24 Apr 23 02:39:39 PM PDT 24 2492276491 ps
T110 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3626355471 Apr 23 02:39:02 PM PDT 24 Apr 23 02:40:40 PM PDT 24 6246370888 ps
T379 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.512633450 Apr 23 02:39:06 PM PDT 24 Apr 23 02:39:27 PM PDT 24 8550981673 ps
T380 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3426474789 Apr 23 02:39:00 PM PDT 24 Apr 23 02:39:26 PM PDT 24 3007184511 ps
T67 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3509825442 Apr 23 02:39:12 PM PDT 24 Apr 23 02:39:39 PM PDT 24 19512173900 ps
T381 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1000729732 Apr 23 02:39:09 PM PDT 24 Apr 23 02:41:41 PM PDT 24 3110589505 ps
T382 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3053764946 Apr 23 02:39:07 PM PDT 24 Apr 23 02:39:35 PM PDT 24 10875490896 ps
T383 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3488762793 Apr 23 02:39:11 PM PDT 24 Apr 23 02:40:44 PM PDT 24 5459047665 ps
T384 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3474784531 Apr 23 02:39:03 PM PDT 24 Apr 23 02:41:12 PM PDT 24 51523377765 ps
T385 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4070294318 Apr 23 02:39:13 PM PDT 24 Apr 23 02:39:38 PM PDT 24 2839352691 ps
T386 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.368453241 Apr 23 02:38:55 PM PDT 24 Apr 23 02:39:22 PM PDT 24 6144770494 ps
T106 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4267210126 Apr 23 02:39:14 PM PDT 24 Apr 23 02:41:52 PM PDT 24 6668880674 ps
T387 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.565391564 Apr 23 02:39:15 PM PDT 24 Apr 23 02:41:29 PM PDT 24 13395466127 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3403587413 Apr 23 02:38:57 PM PDT 24 Apr 23 02:39:18 PM PDT 24 1299227560 ps
T100 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.25938118 Apr 23 02:39:09 PM PDT 24 Apr 23 02:40:42 PM PDT 24 11851520980 ps
T73 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.104933514 Apr 23 02:39:00 PM PDT 24 Apr 23 02:39:09 PM PDT 24 1647461004 ps
T389 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1943170387 Apr 23 02:38:54 PM PDT 24 Apr 23 02:39:34 PM PDT 24 10481849924 ps
T390 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3855889579 Apr 23 02:39:09 PM PDT 24 Apr 23 02:39:32 PM PDT 24 2463739673 ps
T391 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2173490698 Apr 23 02:39:02 PM PDT 24 Apr 23 02:39:37 PM PDT 24 13674426626 ps
T392 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1250979340 Apr 23 02:39:17 PM PDT 24 Apr 23 02:39:48 PM PDT 24 6387278076 ps
T74 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1207111988 Apr 23 02:38:51 PM PDT 24 Apr 23 02:39:08 PM PDT 24 1233789013 ps
T75 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2604207005 Apr 23 02:38:59 PM PDT 24 Apr 23 02:41:46 PM PDT 24 69273345172 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3818528158 Apr 23 02:38:51 PM PDT 24 Apr 23 02:39:23 PM PDT 24 2853559459 ps
T394 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2841877899 Apr 23 02:39:11 PM PDT 24 Apr 23 02:39:37 PM PDT 24 10388406293 ps
T395 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3662864269 Apr 23 02:38:49 PM PDT 24 Apr 23 02:39:22 PM PDT 24 4193104575 ps
T396 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1434905642 Apr 23 02:38:52 PM PDT 24 Apr 23 02:39:26 PM PDT 24 17107077240 ps
T397 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3403222491 Apr 23 02:39:04 PM PDT 24 Apr 23 02:39:14 PM PDT 24 188860698 ps
T76 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.330137184 Apr 23 02:38:55 PM PDT 24 Apr 23 02:40:42 PM PDT 24 12018109670 ps
T398 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.691104445 Apr 23 02:39:04 PM PDT 24 Apr 23 02:39:25 PM PDT 24 17655032248 ps
T399 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4079934436 Apr 23 02:39:05 PM PDT 24 Apr 23 02:39:24 PM PDT 24 1818719122 ps
T400 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2226397511 Apr 23 02:39:14 PM PDT 24 Apr 23 02:39:49 PM PDT 24 3599182250 ps
T401 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2429190135 Apr 23 02:39:13 PM PDT 24 Apr 23 02:39:47 PM PDT 24 14738170568 ps
T402 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.638204590 Apr 23 02:39:06 PM PDT 24 Apr 23 02:39:30 PM PDT 24 1850284543 ps
T403 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4009425637 Apr 23 02:38:59 PM PDT 24 Apr 23 02:39:09 PM PDT 24 323951319 ps
T77 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2325320986 Apr 23 02:39:03 PM PDT 24 Apr 23 02:42:05 PM PDT 24 23138042329 ps
T404 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3583638082 Apr 23 02:38:56 PM PDT 24 Apr 23 02:39:17 PM PDT 24 4006162266 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.746389238 Apr 23 02:39:02 PM PDT 24 Apr 23 02:39:10 PM PDT 24 688669314 ps
T406 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3069635910 Apr 23 02:39:10 PM PDT 24 Apr 23 02:39:19 PM PDT 24 338313675 ps
T407 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2590093514 Apr 23 02:39:11 PM PDT 24 Apr 23 02:39:34 PM PDT 24 2557123274 ps
T78 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1767757441 Apr 23 02:39:10 PM PDT 24 Apr 23 02:41:40 PM PDT 24 72846508193 ps
T408 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1903574129 Apr 23 02:38:49 PM PDT 24 Apr 23 02:39:20 PM PDT 24 15046672203 ps
T409 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2375913889 Apr 23 02:38:56 PM PDT 24 Apr 23 02:39:18 PM PDT 24 12924332896 ps
T101 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1805395706 Apr 23 02:39:14 PM PDT 24 Apr 23 02:42:09 PM PDT 24 4483096443 ps
T410 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2870840095 Apr 23 02:39:09 PM PDT 24 Apr 23 02:39:40 PM PDT 24 3531381724 ps
T82 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3940680783 Apr 23 02:39:11 PM PDT 24 Apr 23 02:41:00 PM PDT 24 178235960033 ps
T107 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3655536805 Apr 23 02:39:11 PM PDT 24 Apr 23 02:41:56 PM PDT 24 3338161849 ps
T411 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1291125175 Apr 23 02:38:55 PM PDT 24 Apr 23 02:39:04 PM PDT 24 636301441 ps
T104 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2950257490 Apr 23 02:39:11 PM PDT 24 Apr 23 02:41:55 PM PDT 24 13992837494 ps
T412 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4048870431 Apr 23 02:39:07 PM PDT 24 Apr 23 02:39:33 PM PDT 24 5294513117 ps
T413 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2805293970 Apr 23 02:38:56 PM PDT 24 Apr 23 02:39:18 PM PDT 24 3012713355 ps
T414 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3142339235 Apr 23 02:39:15 PM PDT 24 Apr 23 02:41:21 PM PDT 24 49231504459 ps
T415 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4119519384 Apr 23 02:39:03 PM PDT 24 Apr 23 02:39:12 PM PDT 24 332043086 ps
T105 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.209271393 Apr 23 02:39:11 PM PDT 24 Apr 23 02:40:44 PM PDT 24 2211579789 ps
T416 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3881070360 Apr 23 02:38:58 PM PDT 24 Apr 23 02:39:16 PM PDT 24 1393207381 ps
T417 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1934480887 Apr 23 02:39:17 PM PDT 24 Apr 23 02:39:46 PM PDT 24 3684299129 ps
T418 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1802083576 Apr 23 02:39:05 PM PDT 24 Apr 23 02:39:32 PM PDT 24 12463085887 ps
T419 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1119034501 Apr 23 02:38:53 PM PDT 24 Apr 23 02:39:05 PM PDT 24 429459736 ps
T420 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3618447927 Apr 23 02:39:10 PM PDT 24 Apr 23 02:41:40 PM PDT 24 63709310073 ps
T421 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1020772677 Apr 23 02:38:57 PM PDT 24 Apr 23 02:39:15 PM PDT 24 1374817834 ps
T422 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2200789424 Apr 23 02:39:13 PM PDT 24 Apr 23 02:39:51 PM PDT 24 2744712966 ps
T423 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1022539884 Apr 23 02:38:56 PM PDT 24 Apr 23 02:39:11 PM PDT 24 3418718943 ps
T424 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4035113611 Apr 23 02:38:55 PM PDT 24 Apr 23 02:39:23 PM PDT 24 11883163005 ps
T425 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1924459964 Apr 23 02:38:50 PM PDT 24 Apr 23 02:39:17 PM PDT 24 6584374306 ps
T426 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.705088025 Apr 23 02:39:04 PM PDT 24 Apr 23 02:39:37 PM PDT 24 31217203847 ps
T427 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1236211706 Apr 23 02:38:52 PM PDT 24 Apr 23 02:39:05 PM PDT 24 2390857515 ps
T428 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2135109374 Apr 23 02:39:02 PM PDT 24 Apr 23 02:39:15 PM PDT 24 174548509 ps
T429 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.410271784 Apr 23 02:38:59 PM PDT 24 Apr 23 02:39:13 PM PDT 24 677342426 ps
T430 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.364757009 Apr 23 02:39:16 PM PDT 24 Apr 23 02:39:33 PM PDT 24 2738174015 ps
T431 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4189795060 Apr 23 02:38:59 PM PDT 24 Apr 23 02:39:21 PM PDT 24 3421420801 ps
T99 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3119505658 Apr 23 02:38:57 PM PDT 24 Apr 23 02:41:41 PM PDT 24 1417807272 ps
T108 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3758897059 Apr 23 02:39:06 PM PDT 24 Apr 23 02:41:57 PM PDT 24 3320430758 ps
T432 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3705183796 Apr 23 02:39:03 PM PDT 24 Apr 23 02:41:49 PM PDT 24 6293373085 ps
T433 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.732008907 Apr 23 02:38:59 PM PDT 24 Apr 23 02:39:19 PM PDT 24 1141565114 ps
T434 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3586986080 Apr 23 02:38:51 PM PDT 24 Apr 23 02:39:02 PM PDT 24 1340275027 ps
T79 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2227203264 Apr 23 02:39:09 PM PDT 24 Apr 23 02:41:27 PM PDT 24 139442994036 ps
T435 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2448382750 Apr 23 02:38:57 PM PDT 24 Apr 23 02:41:04 PM PDT 24 47202138968 ps
T436 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.771480253 Apr 23 02:38:57 PM PDT 24 Apr 23 02:39:35 PM PDT 24 2867421995 ps
T437 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1824604478 Apr 23 02:38:51 PM PDT 24 Apr 23 02:39:03 PM PDT 24 996640230 ps
T438 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1030999259 Apr 23 02:39:02 PM PDT 24 Apr 23 02:39:27 PM PDT 24 5598338657 ps
T439 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.685966131 Apr 23 02:39:03 PM PDT 24 Apr 23 02:39:16 PM PDT 24 6397993099 ps
T80 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1099633532 Apr 23 02:39:05 PM PDT 24 Apr 23 02:39:29 PM PDT 24 2700957239 ps
T440 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.331067903 Apr 23 02:39:06 PM PDT 24 Apr 23 02:41:16 PM PDT 24 64339909307 ps
T441 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1890109902 Apr 23 02:39:04 PM PDT 24 Apr 23 02:39:21 PM PDT 24 1606028621 ps
T442 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1189862854 Apr 23 02:39:01 PM PDT 24 Apr 23 02:39:27 PM PDT 24 1966915793 ps
T443 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3055695729 Apr 23 02:39:03 PM PDT 24 Apr 23 02:39:11 PM PDT 24 174472135 ps
T444 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.447225960 Apr 23 02:39:14 PM PDT 24 Apr 23 02:39:48 PM PDT 24 28341656589 ps
T81 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1633758887 Apr 23 02:39:06 PM PDT 24 Apr 23 02:39:20 PM PDT 24 1655948635 ps
T445 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.642266143 Apr 23 02:38:46 PM PDT 24 Apr 23 02:39:08 PM PDT 24 8517111980 ps
T446 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3900520844 Apr 23 02:39:02 PM PDT 24 Apr 23 02:39:17 PM PDT 24 869714489 ps
T447 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.988127935 Apr 23 02:38:56 PM PDT 24 Apr 23 02:39:26 PM PDT 24 28679160239 ps
T448 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4291061225 Apr 23 02:39:00 PM PDT 24 Apr 23 02:39:31 PM PDT 24 13963587312 ps
T109 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3185494392 Apr 23 02:39:09 PM PDT 24 Apr 23 02:41:57 PM PDT 24 13358188992 ps
T83 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2904316719 Apr 23 02:38:58 PM PDT 24 Apr 23 02:39:25 PM PDT 24 33528476779 ps
T449 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1307849568 Apr 23 02:39:12 PM PDT 24 Apr 23 02:39:34 PM PDT 24 1318994167 ps
T450 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3029888803 Apr 23 02:38:58 PM PDT 24 Apr 23 02:39:32 PM PDT 24 3322680043 ps
T451 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2105705487 Apr 23 02:38:51 PM PDT 24 Apr 23 02:40:23 PM PDT 24 8781181923 ps
T452 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4201388579 Apr 23 02:39:03 PM PDT 24 Apr 23 02:39:28 PM PDT 24 3076645690 ps

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.212529877
Short name T2
Test name
Test status
Simulation time 670908939995 ps
CPU time 694.09 seconds
Started Apr 23 02:39:58 PM PDT 24
Finished Apr 23 02:51:32 PM PDT 24
Peak memory 217764 kb
Host smart-eb498b03-6acc-407c-9f1a-5bc2b5cd463b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212529877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.212529877
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1611227368
Short name T11
Test name
Test status
Simulation time 56505110735 ps
CPU time 6343.52 seconds
Started Apr 23 02:39:42 PM PDT 24
Finished Apr 23 04:25:27 PM PDT 24
Peak memory 236464 kb
Host smart-a270b24a-eb03-4932-91f9-d810f7538c52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611227368 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1611227368
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4062578319
Short name T28
Test name
Test status
Simulation time 3894584554 ps
CPU time 239.2 seconds
Started Apr 23 02:40:14 PM PDT 24
Finished Apr 23 02:44:14 PM PDT 24
Peak memory 240636 kb
Host smart-e61ca6fd-05ec-4ef1-81fc-af1c56a98c79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062578319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4062578319
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4293089002
Short name T47
Test name
Test status
Simulation time 3587405718 ps
CPU time 173.59 seconds
Started Apr 23 02:39:10 PM PDT 24
Finished Apr 23 02:42:04 PM PDT 24
Peak memory 213016 kb
Host smart-67fc36e5-6fb3-4c9a-a31b-84eaf411ec77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293089002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.4293089002
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.212723349
Short name T32
Test name
Test status
Simulation time 14685074538 ps
CPU time 135.27 seconds
Started Apr 23 02:39:15 PM PDT 24
Finished Apr 23 02:41:31 PM PDT 24
Peak memory 241012 kb
Host smart-664fc7f7-472c-4758-b691-0e163c58a1ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212723349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.212723349
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3519028412
Short name T64
Test name
Test status
Simulation time 17435065615 ps
CPU time 135.34 seconds
Started Apr 23 02:38:51 PM PDT 24
Finished Apr 23 02:41:08 PM PDT 24
Peak memory 212040 kb
Host smart-dd996e84-a0e2-473c-b08a-4c743d479bd4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519028412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3519028412
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2502886843
Short name T16
Test name
Test status
Simulation time 37145871987 ps
CPU time 48.5 seconds
Started Apr 23 02:39:16 PM PDT 24
Finished Apr 23 02:40:06 PM PDT 24
Peak memory 219068 kb
Host smart-ba4a0ba4-199e-4dec-88d0-d29419014677
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502886843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2502886843
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3655536805
Short name T107
Test name
Test status
Simulation time 3338161849 ps
CPU time 164.61 seconds
Started Apr 23 02:39:11 PM PDT 24
Finished Apr 23 02:41:56 PM PDT 24
Peak memory 212728 kb
Host smart-b86ef706-8d54-4d2e-bad9-4927f894f615
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655536805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3655536805
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1921931092
Short name T34
Test name
Test status
Simulation time 4106433341 ps
CPU time 12.73 seconds
Started Apr 23 02:39:57 PM PDT 24
Finished Apr 23 02:40:10 PM PDT 24
Peak memory 211756 kb
Host smart-01ce540c-953c-4d0f-b37a-a8106a2b7641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921931092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1921931092
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.248370968
Short name T123
Test name
Test status
Simulation time 16409616206 ps
CPU time 43.36 seconds
Started Apr 23 02:40:08 PM PDT 24
Finished Apr 23 02:40:52 PM PDT 24
Peak memory 215240 kb
Host smart-f3d66ce9-ff47-49d1-9436-bff86e2b610b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248370968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.248370968
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1424095713
Short name T22
Test name
Test status
Simulation time 335928469 ps
CPU time 19.12 seconds
Started Apr 23 02:39:19 PM PDT 24
Finished Apr 23 02:39:38 PM PDT 24
Peak memory 214876 kb
Host smart-4c8a5c14-27e0-498f-b381-e785fd6ea2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424095713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1424095713
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.209271393
Short name T105
Test name
Test status
Simulation time 2211579789 ps
CPU time 91.87 seconds
Started Apr 23 02:39:11 PM PDT 24
Finished Apr 23 02:40:44 PM PDT 24
Peak memory 213744 kb
Host smart-14e9e485-b6bd-4413-bd8d-334dd79b336f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209271393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.209271393
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3940680783
Short name T82
Test name
Test status
Simulation time 178235960033 ps
CPU time 108.52 seconds
Started Apr 23 02:39:11 PM PDT 24
Finished Apr 23 02:41:00 PM PDT 24
Peak memory 212908 kb
Host smart-41bfbde4-b1d2-404d-bce2-442cb26a4d98
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940680783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3940680783
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1798567165
Short name T54
Test name
Test status
Simulation time 27240813658 ps
CPU time 31.87 seconds
Started Apr 23 02:39:12 PM PDT 24
Finished Apr 23 02:39:45 PM PDT 24
Peak memory 211524 kb
Host smart-587b044f-df6e-48ca-9c59-0147f48e6e62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798567165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1798567165
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.785499112
Short name T43
Test name
Test status
Simulation time 586845746694 ps
CPU time 1896.54 seconds
Started Apr 23 02:40:12 PM PDT 24
Finished Apr 23 03:11:50 PM PDT 24
Peak memory 240044 kb
Host smart-7e59236e-edd2-421f-b138-0638be4b1cdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785499112 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.785499112
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.491805111
Short name T97
Test name
Test status
Simulation time 7157942475 ps
CPU time 90.83 seconds
Started Apr 23 02:38:45 PM PDT 24
Finished Apr 23 02:40:17 PM PDT 24
Peak memory 212596 kb
Host smart-e24102e8-afee-4a04-abbf-9c9bab1cc638
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491805111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.491805111
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3758897059
Short name T108
Test name
Test status
Simulation time 3320430758 ps
CPU time 170.89 seconds
Started Apr 23 02:39:06 PM PDT 24
Finished Apr 23 02:41:57 PM PDT 24
Peak memory 213036 kb
Host smart-a132bae4-ec3c-43f7-a89d-4831949c82ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758897059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3758897059
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2838787621
Short name T98
Test name
Test status
Simulation time 982152326 ps
CPU time 79.03 seconds
Started Apr 23 02:39:11 PM PDT 24
Finished Apr 23 02:40:31 PM PDT 24
Peak memory 212824 kb
Host smart-c8564399-8074-41ad-a91a-d14004134daa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838787621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2838787621
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1028501296
Short name T19
Test name
Test status
Simulation time 620319606308 ps
CPU time 1232.21 seconds
Started Apr 23 02:39:36 PM PDT 24
Finished Apr 23 03:00:09 PM PDT 24
Peak memory 236096 kb
Host smart-348e5100-8461-41ab-ae46-1b21f9a25341
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028501296 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.1028501296
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1207111988
Short name T74
Test name
Test status
Simulation time 1233789013 ps
CPU time 15.83 seconds
Started Apr 23 02:38:51 PM PDT 24
Finished Apr 23 02:39:08 PM PDT 24
Peak memory 209896 kb
Host smart-367c990d-88fc-4eae-829b-ebf7d85c025d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207111988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1207111988
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.642266143
Short name T445
Test name
Test status
Simulation time 8517111980 ps
CPU time 21.13 seconds
Started Apr 23 02:38:46 PM PDT 24
Finished Apr 23 02:39:08 PM PDT 24
Peak memory 218496 kb
Host smart-585a4be2-8a13-4c3c-8e21-90b4effcd3ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642266143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.642266143
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3818528158
Short name T393
Test name
Test status
Simulation time 2853559459 ps
CPU time 31.44 seconds
Started Apr 23 02:38:51 PM PDT 24
Finished Apr 23 02:39:23 PM PDT 24
Peak memory 210740 kb
Host smart-59281e6e-7d17-4b8b-9f09-1e98bc4d102d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818528158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3818528158
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4284068517
Short name T376
Test name
Test status
Simulation time 19936052111 ps
CPU time 15.41 seconds
Started Apr 23 02:38:49 PM PDT 24
Finished Apr 23 02:39:05 PM PDT 24
Peak memory 215912 kb
Host smart-d5bb4eb4-556a-4cb2-9083-6590a0acfcba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284068517 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.4284068517
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1291125175
Short name T411
Test name
Test status
Simulation time 636301441 ps
CPU time 8.15 seconds
Started Apr 23 02:38:55 PM PDT 24
Finished Apr 23 02:39:04 PM PDT 24
Peak memory 210320 kb
Host smart-07be4acf-4422-45f7-9ebd-295763dc2908
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291125175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1291125175
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1787875251
Short name T360
Test name
Test status
Simulation time 533003572 ps
CPU time 8.16 seconds
Started Apr 23 02:38:50 PM PDT 24
Finished Apr 23 02:38:59 PM PDT 24
Peak memory 210176 kb
Host smart-a8b221ad-0eee-4ee2-9c41-fe8f0ea797fd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787875251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1787875251
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1903574129
Short name T408
Test name
Test status
Simulation time 15046672203 ps
CPU time 30.51 seconds
Started Apr 23 02:38:49 PM PDT 24
Finished Apr 23 02:39:20 PM PDT 24
Peak memory 210260 kb
Host smart-eea72301-331c-432d-b48e-ef892358544f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903574129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1903574129
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.330137184
Short name T76
Test name
Test status
Simulation time 12018109670 ps
CPU time 106.17 seconds
Started Apr 23 02:38:55 PM PDT 24
Finished Apr 23 02:40:42 PM PDT 24
Peak memory 212828 kb
Host smart-22b3d810-155e-4d65-b7a5-f1c1401a713b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330137184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.330137184
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1924459964
Short name T425
Test name
Test status
Simulation time 6584374306 ps
CPU time 26.71 seconds
Started Apr 23 02:38:50 PM PDT 24
Finished Apr 23 02:39:17 PM PDT 24
Peak memory 211864 kb
Host smart-d5b08bf3-7374-4385-978a-993cfb13d245
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924459964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1924459964
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2805293970
Short name T413
Test name
Test status
Simulation time 3012713355 ps
CPU time 20.66 seconds
Started Apr 23 02:38:56 PM PDT 24
Finished Apr 23 02:39:18 PM PDT 24
Peak memory 217460 kb
Host smart-7397afc0-2e1b-4cfb-805f-9397a5e3a3c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805293970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2805293970
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3662864269
Short name T395
Test name
Test status
Simulation time 4193104575 ps
CPU time 32.81 seconds
Started Apr 23 02:38:49 PM PDT 24
Finished Apr 23 02:39:22 PM PDT 24
Peak memory 210800 kb
Host smart-f151a5ce-5f76-49b8-91c5-454cacf2fb6d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662864269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3662864269
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1434905642
Short name T396
Test name
Test status
Simulation time 17107077240 ps
CPU time 33.2 seconds
Started Apr 23 02:38:52 PM PDT 24
Finished Apr 23 02:39:26 PM PDT 24
Peak memory 218548 kb
Host smart-94285fe3-fbb5-4091-9f97-713a8e89c6d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434905642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1434905642
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1943170387
Short name T389
Test name
Test status
Simulation time 10481849924 ps
CPU time 39.91 seconds
Started Apr 23 02:38:54 PM PDT 24
Finished Apr 23 02:39:34 PM PDT 24
Peak memory 210952 kb
Host smart-b42be1de-2c7d-47f7-a7d9-f10a84c27cdd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943170387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1943170387
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2045344395
Short name T363
Test name
Test status
Simulation time 4469577794 ps
CPU time 30.56 seconds
Started Apr 23 02:38:49 PM PDT 24
Finished Apr 23 02:39:21 PM PDT 24
Peak memory 215088 kb
Host smart-8c0afa5e-dc6b-4d54-8d04-68bfb276fdbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045344395 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2045344395
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1236211706
Short name T427
Test name
Test status
Simulation time 2390857515 ps
CPU time 12.08 seconds
Started Apr 23 02:38:52 PM PDT 24
Finished Apr 23 02:39:05 PM PDT 24
Peak memory 210268 kb
Host smart-86296872-493b-4579-b47c-aabbdd478961
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236211706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1236211706
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1824604478
Short name T437
Test name
Test status
Simulation time 996640230 ps
CPU time 11.46 seconds
Started Apr 23 02:38:51 PM PDT 24
Finished Apr 23 02:39:03 PM PDT 24
Peak memory 210176 kb
Host smart-836cafb6-fb55-43ad-a388-fc8ee1099af6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824604478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1824604478
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1119034501
Short name T419
Test name
Test status
Simulation time 429459736 ps
CPU time 11.33 seconds
Started Apr 23 02:38:53 PM PDT 24
Finished Apr 23 02:39:05 PM PDT 24
Peak memory 210156 kb
Host smart-86c1729c-d437-49f6-8192-acaaaa7ae189
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119034501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1119034501
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4079934436
Short name T399
Test name
Test status
Simulation time 1818719122 ps
CPU time 18.77 seconds
Started Apr 23 02:39:05 PM PDT 24
Finished Apr 23 02:39:24 PM PDT 24
Peak memory 211400 kb
Host smart-122aa591-beb2-430d-aefd-811ee0ab6462
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079934436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.4079934436
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1020772677
Short name T421
Test name
Test status
Simulation time 1374817834 ps
CPU time 17.34 seconds
Started Apr 23 02:38:57 PM PDT 24
Finished Apr 23 02:39:15 PM PDT 24
Peak memory 215680 kb
Host smart-9a084690-6d24-48dd-934d-464b7c1e12b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020772677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1020772677
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.187778301
Short name T49
Test name
Test status
Simulation time 2410369810 ps
CPU time 92.45 seconds
Started Apr 23 02:38:51 PM PDT 24
Finished Apr 23 02:40:24 PM PDT 24
Peak memory 213640 kb
Host smart-dc515f03-6953-4032-839c-811a3a33deba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187778301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.187778301
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2725593618
Short name T371
Test name
Test status
Simulation time 6882421043 ps
CPU time 18.95 seconds
Started Apr 23 02:39:03 PM PDT 24
Finished Apr 23 02:39:23 PM PDT 24
Peak memory 216604 kb
Host smart-36f866f3-d047-4a72-99e9-f04c8269452c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725593618 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2725593618
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4291061225
Short name T448
Test name
Test status
Simulation time 13963587312 ps
CPU time 30.84 seconds
Started Apr 23 02:39:00 PM PDT 24
Finished Apr 23 02:39:31 PM PDT 24
Peak memory 211356 kb
Host smart-b43efdb0-213b-4aad-9e48-b37689c23129
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291061225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4291061225
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2354780496
Short name T53
Test name
Test status
Simulation time 6749135747 ps
CPU time 60.34 seconds
Started Apr 23 02:38:56 PM PDT 24
Finished Apr 23 02:39:57 PM PDT 24
Peak memory 213724 kb
Host smart-39252d35-9193-4e11-8749-c36c7f6f0a02
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354780496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2354780496
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3881070360
Short name T416
Test name
Test status
Simulation time 1393207381 ps
CPU time 17.42 seconds
Started Apr 23 02:38:58 PM PDT 24
Finished Apr 23 02:39:16 PM PDT 24
Peak memory 210540 kb
Host smart-1fe57ba0-33ed-4e69-84ff-ae3586744cc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881070360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3881070360
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2112266864
Short name T48
Test name
Test status
Simulation time 331663478 ps
CPU time 12.27 seconds
Started Apr 23 02:39:14 PM PDT 24
Finished Apr 23 02:39:27 PM PDT 24
Peak memory 216432 kb
Host smart-153b8bcc-82fb-4762-9a8b-8a44bc0481af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112266864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2112266864
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.25938118
Short name T100
Test name
Test status
Simulation time 11851520980 ps
CPU time 93.23 seconds
Started Apr 23 02:39:09 PM PDT 24
Finished Apr 23 02:40:42 PM PDT 24
Peak memory 218540 kb
Host smart-2c1fba9c-b90c-424f-9e27-937132a94ad3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25938118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_int
g_err.25938118
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3426474789
Short name T380
Test name
Test status
Simulation time 3007184511 ps
CPU time 25.42 seconds
Started Apr 23 02:39:00 PM PDT 24
Finished Apr 23 02:39:26 PM PDT 24
Peak memory 215296 kb
Host smart-405b57e2-dbc7-4a0e-bb50-dff848bfd0cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426474789 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3426474789
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1807642045
Short name T52
Test name
Test status
Simulation time 792790363 ps
CPU time 13.22 seconds
Started Apr 23 02:38:58 PM PDT 24
Finished Apr 23 02:39:12 PM PDT 24
Peak memory 210276 kb
Host smart-6738daa8-f4c1-4361-996d-44411f5beb54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807642045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1807642045
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2448382750
Short name T435
Test name
Test status
Simulation time 47202138968 ps
CPU time 126.2 seconds
Started Apr 23 02:38:57 PM PDT 24
Finished Apr 23 02:41:04 PM PDT 24
Peak memory 218624 kb
Host smart-8ad6a350-da87-4e51-a259-4b7841413e79
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448382750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2448382750
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.512633450
Short name T379
Test name
Test status
Simulation time 8550981673 ps
CPU time 20.67 seconds
Started Apr 23 02:39:06 PM PDT 24
Finished Apr 23 02:39:27 PM PDT 24
Peak memory 210628 kb
Host smart-5dd9c8ac-41be-422c-87e6-c4300df71862
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512633450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.512633450
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4189795060
Short name T431
Test name
Test status
Simulation time 3421420801 ps
CPU time 21.9 seconds
Started Apr 23 02:38:59 PM PDT 24
Finished Apr 23 02:39:21 PM PDT 24
Peak memory 217512 kb
Host smart-cd88b451-4fb6-4698-ae53-337df0f8642e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189795060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.4189795060
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3208987727
Short name T378
Test name
Test status
Simulation time 2492276491 ps
CPU time 24 seconds
Started Apr 23 02:39:15 PM PDT 24
Finished Apr 23 02:39:39 PM PDT 24
Peak memory 217188 kb
Host smart-40998c6e-3326-44d3-8a4e-eb220136b755
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208987727 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3208987727
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3103086990
Short name T373
Test name
Test status
Simulation time 3358724067 ps
CPU time 27.02 seconds
Started Apr 23 02:39:00 PM PDT 24
Finished Apr 23 02:39:28 PM PDT 24
Peak memory 210784 kb
Host smart-94006e59-a44f-4689-9324-0ddd7a2fa89f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103086990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3103086990
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1049602721
Short name T92
Test name
Test status
Simulation time 6888035884 ps
CPU time 59.6 seconds
Started Apr 23 02:39:04 PM PDT 24
Finished Apr 23 02:40:04 PM PDT 24
Peak memory 213780 kb
Host smart-8a144300-e6a0-4ef5-8ca2-07160e946214
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049602721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1049602721
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4070294318
Short name T385
Test name
Test status
Simulation time 2839352691 ps
CPU time 24.61 seconds
Started Apr 23 02:39:13 PM PDT 24
Finished Apr 23 02:39:38 PM PDT 24
Peak memory 211172 kb
Host smart-2d35f3ed-e8e9-4550-b141-dcf9895a3bed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070294318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.4070294318
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1064125668
Short name T46
Test name
Test status
Simulation time 683871266 ps
CPU time 18.39 seconds
Started Apr 23 02:39:03 PM PDT 24
Finished Apr 23 02:39:22 PM PDT 24
Peak memory 217792 kb
Host smart-f6e236e3-f574-4e7a-aac0-0772cc7012cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064125668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1064125668
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3626355471
Short name T110
Test name
Test status
Simulation time 6246370888 ps
CPU time 96.56 seconds
Started Apr 23 02:39:02 PM PDT 24
Finished Apr 23 02:40:40 PM PDT 24
Peak memory 213028 kb
Host smart-86215d8e-0570-4292-8e34-b1fdd4ef7697
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626355471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3626355471
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1030999259
Short name T438
Test name
Test status
Simulation time 5598338657 ps
CPU time 23.84 seconds
Started Apr 23 02:39:02 PM PDT 24
Finished Apr 23 02:39:27 PM PDT 24
Peak memory 214280 kb
Host smart-aa532225-1e1c-4173-abae-d17a8b93517f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030999259 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1030999259
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1294000280
Short name T62
Test name
Test status
Simulation time 4090318152 ps
CPU time 29.85 seconds
Started Apr 23 02:39:03 PM PDT 24
Finished Apr 23 02:39:34 PM PDT 24
Peak memory 210820 kb
Host smart-6bae7dc6-8a95-4b89-9d09-83750b9bbd35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294000280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1294000280
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3618447927
Short name T420
Test name
Test status
Simulation time 63709310073 ps
CPU time 149.26 seconds
Started Apr 23 02:39:10 PM PDT 24
Finished Apr 23 02:41:40 PM PDT 24
Peak memory 214548 kb
Host smart-b9a71e64-550e-4137-bb18-833b51bcf03d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618447927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3618447927
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3354399468
Short name T89
Test name
Test status
Simulation time 2720992122 ps
CPU time 20.23 seconds
Started Apr 23 02:39:11 PM PDT 24
Finished Apr 23 02:39:32 PM PDT 24
Peak memory 211616 kb
Host smart-bbdff26f-bd57-4fc5-be1e-d7acd5dcd0ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354399468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3354399468
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1033138828
Short name T369
Test name
Test status
Simulation time 7011274292 ps
CPU time 30.46 seconds
Started Apr 23 02:39:11 PM PDT 24
Finished Apr 23 02:39:43 PM PDT 24
Peak memory 216736 kb
Host smart-63b89e2c-39b0-402e-a279-088384ab1a97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033138828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1033138828
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.168477064
Short name T50
Test name
Test status
Simulation time 7150101819 ps
CPU time 89.76 seconds
Started Apr 23 02:39:11 PM PDT 24
Finished Apr 23 02:40:42 PM PDT 24
Peak memory 211892 kb
Host smart-8552a0b1-7ccc-47bd-83df-266a9f328680
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168477064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.168477064
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4201388579
Short name T452
Test name
Test status
Simulation time 3076645690 ps
CPU time 24.87 seconds
Started Apr 23 02:39:03 PM PDT 24
Finished Apr 23 02:39:28 PM PDT 24
Peak memory 214112 kb
Host smart-d0bf1772-d807-457d-8090-6b7c7a301d75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201388579 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4201388579
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3988570342
Short name T88
Test name
Test status
Simulation time 1893259476 ps
CPU time 19.7 seconds
Started Apr 23 02:39:06 PM PDT 24
Finished Apr 23 02:39:26 PM PDT 24
Peak memory 210808 kb
Host smart-5102bdb5-1942-431c-8d19-8c49e0ff467e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988570342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3988570342
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.565391564
Short name T387
Test name
Test status
Simulation time 13395466127 ps
CPU time 133.78 seconds
Started Apr 23 02:39:15 PM PDT 24
Finished Apr 23 02:41:29 PM PDT 24
Peak memory 213632 kb
Host smart-e7c8a657-9642-4aed-9c4d-6949d352d1a4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565391564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.565391564
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.447225960
Short name T444
Test name
Test status
Simulation time 28341656589 ps
CPU time 33.23 seconds
Started Apr 23 02:39:14 PM PDT 24
Finished Apr 23 02:39:48 PM PDT 24
Peak memory 211904 kb
Host smart-05600d20-050b-4842-acca-97ec49917bad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447225960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.447225960
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.638204590
Short name T402
Test name
Test status
Simulation time 1850284543 ps
CPU time 23.74 seconds
Started Apr 23 02:39:06 PM PDT 24
Finished Apr 23 02:39:30 PM PDT 24
Peak memory 216284 kb
Host smart-3f611eeb-a2a9-4fcb-819e-f7732b12ef0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638204590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.638204590
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3705183796
Short name T432
Test name
Test status
Simulation time 6293373085 ps
CPU time 165.36 seconds
Started Apr 23 02:39:03 PM PDT 24
Finished Apr 23 02:41:49 PM PDT 24
Peak memory 218596 kb
Host smart-99cdae48-768a-45ea-afbb-01cd801566de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705183796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3705183796
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1934480887
Short name T417
Test name
Test status
Simulation time 3684299129 ps
CPU time 28.12 seconds
Started Apr 23 02:39:17 PM PDT 24
Finished Apr 23 02:39:46 PM PDT 24
Peak memory 215888 kb
Host smart-ba7258b3-b5e8-434c-9d16-ec19ce4f0431
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934480887 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1934480887
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1681409264
Short name T65
Test name
Test status
Simulation time 170959838 ps
CPU time 8.07 seconds
Started Apr 23 02:39:12 PM PDT 24
Finished Apr 23 02:39:20 PM PDT 24
Peak memory 210284 kb
Host smart-d2eaea81-6ae4-4cfc-abdc-4594484a6915
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681409264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1681409264
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3474784531
Short name T384
Test name
Test status
Simulation time 51523377765 ps
CPU time 128.31 seconds
Started Apr 23 02:39:03 PM PDT 24
Finished Apr 23 02:41:12 PM PDT 24
Peak memory 210456 kb
Host smart-26247029-8813-4500-b170-d9047df753d9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474784531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3474784531
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.685966131
Short name T439
Test name
Test status
Simulation time 6397993099 ps
CPU time 12.67 seconds
Started Apr 23 02:39:03 PM PDT 24
Finished Apr 23 02:39:16 PM PDT 24
Peak memory 210616 kb
Host smart-242b1811-b864-444a-bdbc-f5aca10130e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685966131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.685966131
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1307849568
Short name T449
Test name
Test status
Simulation time 1318994167 ps
CPU time 21.66 seconds
Started Apr 23 02:39:12 PM PDT 24
Finished Apr 23 02:39:34 PM PDT 24
Peak memory 217344 kb
Host smart-6306be9a-a03f-4809-ab31-d3f97227d686
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307849568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1307849568
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1805395706
Short name T101
Test name
Test status
Simulation time 4483096443 ps
CPU time 174.79 seconds
Started Apr 23 02:39:14 PM PDT 24
Finished Apr 23 02:42:09 PM PDT 24
Peak memory 213236 kb
Host smart-a4a836a5-f87d-40bd-acf0-e4506ed4ad09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805395706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1805395706
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3900520844
Short name T446
Test name
Test status
Simulation time 869714489 ps
CPU time 14.12 seconds
Started Apr 23 02:39:02 PM PDT 24
Finished Apr 23 02:39:17 PM PDT 24
Peak memory 216416 kb
Host smart-375b87f7-ac8b-44ef-b094-c0670ea66e1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900520844 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3900520844
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1099633532
Short name T80
Test name
Test status
Simulation time 2700957239 ps
CPU time 24.27 seconds
Started Apr 23 02:39:05 PM PDT 24
Finished Apr 23 02:39:29 PM PDT 24
Peak memory 210844 kb
Host smart-81c24914-46e6-4e66-b4b6-0335c0665abd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099633532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1099633532
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3142339235
Short name T414
Test name
Test status
Simulation time 49231504459 ps
CPU time 125.12 seconds
Started Apr 23 02:39:15 PM PDT 24
Finished Apr 23 02:41:21 PM PDT 24
Peak memory 213752 kb
Host smart-24a3a77c-f33b-44a1-91a0-2c291202ca3f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142339235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3142339235
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.705088025
Short name T426
Test name
Test status
Simulation time 31217203847 ps
CPU time 31.57 seconds
Started Apr 23 02:39:04 PM PDT 24
Finished Apr 23 02:39:37 PM PDT 24
Peak memory 211752 kb
Host smart-a6b42240-6524-4e9b-88f1-db9a4d82590a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705088025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.705088025
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4048870431
Short name T412
Test name
Test status
Simulation time 5294513117 ps
CPU time 25.73 seconds
Started Apr 23 02:39:07 PM PDT 24
Finished Apr 23 02:39:33 PM PDT 24
Peak memory 216532 kb
Host smart-21109d58-16b4-4250-a972-71c3ac5c85a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048870431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.4048870431
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4267210126
Short name T106
Test name
Test status
Simulation time 6668880674 ps
CPU time 158.17 seconds
Started Apr 23 02:39:14 PM PDT 24
Finished Apr 23 02:41:52 PM PDT 24
Peak memory 213736 kb
Host smart-f7867841-5957-4658-b58e-6cfb5d1379f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267210126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.4267210126
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3312147478
Short name T367
Test name
Test status
Simulation time 810903623 ps
CPU time 8.67 seconds
Started Apr 23 02:39:15 PM PDT 24
Finished Apr 23 02:39:24 PM PDT 24
Peak memory 215396 kb
Host smart-397e0579-e34f-487a-911a-7dbec953184d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312147478 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3312147478
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1802083576
Short name T418
Test name
Test status
Simulation time 12463085887 ps
CPU time 26.42 seconds
Started Apr 23 02:39:05 PM PDT 24
Finished Apr 23 02:39:32 PM PDT 24
Peak memory 211228 kb
Host smart-e7cb06c8-9c41-47e5-9cd1-3036ecb78c31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802083576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1802083576
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.331067903
Short name T440
Test name
Test status
Simulation time 64339909307 ps
CPU time 129.71 seconds
Started Apr 23 02:39:06 PM PDT 24
Finished Apr 23 02:41:16 PM PDT 24
Peak memory 212908 kb
Host smart-87c3ddc6-49e5-4718-a1c7-a87a926aed58
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331067903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.331067903
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3509825442
Short name T67
Test name
Test status
Simulation time 19512173900 ps
CPU time 26.69 seconds
Started Apr 23 02:39:12 PM PDT 24
Finished Apr 23 02:39:39 PM PDT 24
Peak memory 211528 kb
Host smart-b3301d9d-8c11-41e2-9f29-f6c449788884
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509825442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3509825442
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2226397511
Short name T400
Test name
Test status
Simulation time 3599182250 ps
CPU time 33.79 seconds
Started Apr 23 02:39:14 PM PDT 24
Finished Apr 23 02:39:49 PM PDT 24
Peak memory 217556 kb
Host smart-a60441dd-d335-4e33-b87f-dcf113b7ed22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226397511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2226397511
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.55866960
Short name T361
Test name
Test status
Simulation time 1818981810 ps
CPU time 14.06 seconds
Started Apr 23 02:39:11 PM PDT 24
Finished Apr 23 02:39:25 PM PDT 24
Peak memory 213372 kb
Host smart-ee8ef4ee-9fad-4c75-8e13-63ad774f0239
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55866960 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.55866960
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2590093514
Short name T407
Test name
Test status
Simulation time 2557123274 ps
CPU time 22.22 seconds
Started Apr 23 02:39:11 PM PDT 24
Finished Apr 23 02:39:34 PM PDT 24
Peak memory 210916 kb
Host smart-dd076085-7c18-417a-b1ca-d3b9bd9ae51f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590093514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2590093514
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2135109374
Short name T428
Test name
Test status
Simulation time 174548509 ps
CPU time 11.61 seconds
Started Apr 23 02:39:02 PM PDT 24
Finished Apr 23 02:39:15 PM PDT 24
Peak memory 216320 kb
Host smart-bcf026d6-d169-4ad0-a906-cb8c84e5b55d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135109374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2135109374
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2429190135
Short name T401
Test name
Test status
Simulation time 14738170568 ps
CPU time 28.12 seconds
Started Apr 23 02:39:13 PM PDT 24
Finished Apr 23 02:39:47 PM PDT 24
Peak memory 216428 kb
Host smart-9fe55593-7de0-46db-8f13-df17292e5a62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429190135 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2429190135
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3698322757
Short name T372
Test name
Test status
Simulation time 174412298 ps
CPU time 8.13 seconds
Started Apr 23 02:39:06 PM PDT 24
Finished Apr 23 02:39:15 PM PDT 24
Peak memory 210272 kb
Host smart-88827a24-3fd5-4593-9b63-91d3530b22b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698322757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3698322757
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2200789424
Short name T422
Test name
Test status
Simulation time 2744712966 ps
CPU time 37.88 seconds
Started Apr 23 02:39:13 PM PDT 24
Finished Apr 23 02:39:51 PM PDT 24
Peak memory 212504 kb
Host smart-8fc07023-3508-42af-adfd-c7ecce6300dd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200789424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2200789424
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3606856694
Short name T375
Test name
Test status
Simulation time 13726927556 ps
CPU time 23.75 seconds
Started Apr 23 02:39:15 PM PDT 24
Finished Apr 23 02:39:39 PM PDT 24
Peak memory 211260 kb
Host smart-b6ebdc11-25a2-4a29-af5e-76aff5d02f52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606856694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3606856694
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1250979340
Short name T392
Test name
Test status
Simulation time 6387278076 ps
CPU time 30.05 seconds
Started Apr 23 02:39:17 PM PDT 24
Finished Apr 23 02:39:48 PM PDT 24
Peak memory 216772 kb
Host smart-0c95f960-cf52-4fe1-ae2f-0a8d9fc6d101
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250979340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1250979340
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1000729732
Short name T381
Test name
Test status
Simulation time 3110589505 ps
CPU time 151.86 seconds
Started Apr 23 02:39:09 PM PDT 24
Finished Apr 23 02:41:41 PM PDT 24
Peak memory 212864 kb
Host smart-2621b3d7-ed0e-4213-b08c-78a70aec7f65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000729732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1000729732
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2756215122
Short name T366
Test name
Test status
Simulation time 3334730739 ps
CPU time 26.99 seconds
Started Apr 23 02:38:55 PM PDT 24
Finished Apr 23 02:39:23 PM PDT 24
Peak memory 210500 kb
Host smart-4b41ddc1-963c-4259-ab7c-74dba2d77a70
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756215122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2756215122
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4148210472
Short name T365
Test name
Test status
Simulation time 3510409322 ps
CPU time 28.67 seconds
Started Apr 23 02:38:56 PM PDT 24
Finished Apr 23 02:39:25 PM PDT 24
Peak memory 210380 kb
Host smart-afe9974f-6917-45a4-b373-a3c91d8cc264
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148210472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.4148210472
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3029888803
Short name T450
Test name
Test status
Simulation time 3322680043 ps
CPU time 33.52 seconds
Started Apr 23 02:38:58 PM PDT 24
Finished Apr 23 02:39:32 PM PDT 24
Peak memory 211008 kb
Host smart-27d0bb6b-be0f-465f-b45b-9045234cbb6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029888803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3029888803
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3586986080
Short name T434
Test name
Test status
Simulation time 1340275027 ps
CPU time 10.79 seconds
Started Apr 23 02:38:51 PM PDT 24
Finished Apr 23 02:39:02 PM PDT 24
Peak memory 213996 kb
Host smart-6368d348-b041-484f-aeca-1d529e3ab476
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586986080 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3586986080
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1890109902
Short name T441
Test name
Test status
Simulation time 1606028621 ps
CPU time 16.58 seconds
Started Apr 23 02:39:04 PM PDT 24
Finished Apr 23 02:39:21 PM PDT 24
Peak memory 210320 kb
Host smart-69bd8541-1293-4727-8e72-8e7180890f52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890109902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1890109902
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3069635910
Short name T406
Test name
Test status
Simulation time 338313675 ps
CPU time 8.06 seconds
Started Apr 23 02:39:10 PM PDT 24
Finished Apr 23 02:39:19 PM PDT 24
Peak memory 210240 kb
Host smart-e6c31cd4-9bbe-4492-9ef1-76efacc7d1b1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069635910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3069635910
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3855889579
Short name T390
Test name
Test status
Simulation time 2463739673 ps
CPU time 22.06 seconds
Started Apr 23 02:39:09 PM PDT 24
Finished Apr 23 02:39:32 PM PDT 24
Peak memory 210224 kb
Host smart-bc098027-cfa4-42dd-a952-9e1c236fae1b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855889579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3855889579
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2328439868
Short name T90
Test name
Test status
Simulation time 106860724145 ps
CPU time 134.72 seconds
Started Apr 23 02:39:07 PM PDT 24
Finished Apr 23 02:41:23 PM PDT 24
Peak memory 212500 kb
Host smart-98a911f9-ed02-449e-bd48-5f299ba4c148
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328439868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2328439868
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1221483215
Short name T91
Test name
Test status
Simulation time 2531996833 ps
CPU time 27.13 seconds
Started Apr 23 02:39:07 PM PDT 24
Finished Apr 23 02:39:35 PM PDT 24
Peak memory 211300 kb
Host smart-fe0ada0f-3f5a-46e9-a0af-8c7abfbcc84e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221483215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1221483215
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3403587413
Short name T388
Test name
Test status
Simulation time 1299227560 ps
CPU time 20.74 seconds
Started Apr 23 02:38:57 PM PDT 24
Finished Apr 23 02:39:18 PM PDT 24
Peak memory 216608 kb
Host smart-333b1bf1-1c38-498f-8346-5a769c856c47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403587413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3403587413
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2105705487
Short name T451
Test name
Test status
Simulation time 8781181923 ps
CPU time 90.58 seconds
Started Apr 23 02:38:51 PM PDT 24
Finished Apr 23 02:40:23 PM PDT 24
Peak memory 213064 kb
Host smart-8a7703e3-d3e6-4f97-8dd8-ff28f6544840
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105705487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2105705487
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3583638082
Short name T404
Test name
Test status
Simulation time 4006162266 ps
CPU time 19.66 seconds
Started Apr 23 02:38:56 PM PDT 24
Finished Apr 23 02:39:17 PM PDT 24
Peak memory 210492 kb
Host smart-ba460734-0043-4dd4-80e2-414efb4d1c13
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583638082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3583638082
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.746389238
Short name T405
Test name
Test status
Simulation time 688669314 ps
CPU time 8.38 seconds
Started Apr 23 02:39:02 PM PDT 24
Finished Apr 23 02:39:10 PM PDT 24
Peak memory 210240 kb
Host smart-a4bad4d9-2b0a-4d5b-a855-af6d8f7a605d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746389238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.746389238
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.446826277
Short name T94
Test name
Test status
Simulation time 1161605485 ps
CPU time 18.13 seconds
Started Apr 23 02:38:55 PM PDT 24
Finished Apr 23 02:39:14 PM PDT 24
Peak memory 210288 kb
Host smart-2c16dd86-4f74-41ac-b38c-27105041dfe8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446826277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.446826277
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4288377030
Short name T60
Test name
Test status
Simulation time 466244012 ps
CPU time 8.79 seconds
Started Apr 23 02:38:57 PM PDT 24
Finished Apr 23 02:39:07 PM PDT 24
Peak memory 215480 kb
Host smart-5ae73b7b-6571-4cb2-94dd-0f9dbaedb333
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288377030 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.4288377030
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2904316719
Short name T83
Test name
Test status
Simulation time 33528476779 ps
CPU time 25.49 seconds
Started Apr 23 02:38:58 PM PDT 24
Finished Apr 23 02:39:25 PM PDT 24
Peak memory 211192 kb
Host smart-7ac486e3-7211-4b48-b121-79690339827e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904316719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2904316719
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2375913889
Short name T409
Test name
Test status
Simulation time 12924332896 ps
CPU time 21.53 seconds
Started Apr 23 02:38:56 PM PDT 24
Finished Apr 23 02:39:18 PM PDT 24
Peak memory 210280 kb
Host smart-ad12f68a-bb6c-4bb1-b006-7b8ad261a538
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375913889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2375913889
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3055695729
Short name T443
Test name
Test status
Simulation time 174472135 ps
CPU time 8.1 seconds
Started Apr 23 02:39:03 PM PDT 24
Finished Apr 23 02:39:11 PM PDT 24
Peak memory 210228 kb
Host smart-f0e20378-4602-4735-ac75-cb898700e76d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055695729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3055695729
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2325320986
Short name T77
Test name
Test status
Simulation time 23138042329 ps
CPU time 181.94 seconds
Started Apr 23 02:39:03 PM PDT 24
Finished Apr 23 02:42:05 PM PDT 24
Peak memory 214528 kb
Host smart-77c5e578-9b65-4264-af96-83467691cfad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325320986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2325320986
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.691104445
Short name T398
Test name
Test status
Simulation time 17655032248 ps
CPU time 21.16 seconds
Started Apr 23 02:39:04 PM PDT 24
Finished Apr 23 02:39:25 PM PDT 24
Peak memory 211480 kb
Host smart-75db6721-ee76-4f4a-9ece-2d3aee803730
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691104445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.691104445
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2870840095
Short name T410
Test name
Test status
Simulation time 3531381724 ps
CPU time 30.24 seconds
Started Apr 23 02:39:09 PM PDT 24
Finished Apr 23 02:39:40 PM PDT 24
Peak memory 217196 kb
Host smart-ab0490d7-efbc-4e12-8a1d-0d525444477a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870840095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2870840095
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3404534878
Short name T61
Test name
Test status
Simulation time 2611542546 ps
CPU time 22.69 seconds
Started Apr 23 02:39:07 PM PDT 24
Finished Apr 23 02:39:31 PM PDT 24
Peak memory 210604 kb
Host smart-3a61996a-d1c3-41d9-b049-8ea72003d92c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404534878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3404534878
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.319282296
Short name T370
Test name
Test status
Simulation time 1821385451 ps
CPU time 11.94 seconds
Started Apr 23 02:38:55 PM PDT 24
Finished Apr 23 02:39:08 PM PDT 24
Peak memory 210252 kb
Host smart-5071a1c0-7bb7-4452-a61c-f57288ce70be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319282296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.319282296
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2122128403
Short name T93
Test name
Test status
Simulation time 4040496560 ps
CPU time 25.85 seconds
Started Apr 23 02:39:05 PM PDT 24
Finished Apr 23 02:39:31 PM PDT 24
Peak memory 210788 kb
Host smart-802a745f-becf-4abc-94da-4e5e149b4d0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122128403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2122128403
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.364757009
Short name T430
Test name
Test status
Simulation time 2738174015 ps
CPU time 15.93 seconds
Started Apr 23 02:39:16 PM PDT 24
Finished Apr 23 02:39:33 PM PDT 24
Peak memory 215044 kb
Host smart-25552f8a-95aa-4eeb-a750-efd9fd0fe77a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364757009 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.364757009
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2012123235
Short name T364
Test name
Test status
Simulation time 1011579539 ps
CPU time 11.56 seconds
Started Apr 23 02:39:12 PM PDT 24
Finished Apr 23 02:39:24 PM PDT 24
Peak memory 210304 kb
Host smart-ff1e382d-acb0-4732-9016-902abb4eb14f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012123235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2012123235
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2071595173
Short name T374
Test name
Test status
Simulation time 58645715289 ps
CPU time 24.96 seconds
Started Apr 23 02:38:55 PM PDT 24
Finished Apr 23 02:39:21 PM PDT 24
Peak memory 210308 kb
Host smart-071c18e9-40eb-4bb7-88be-e4c0b5aa2384
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071595173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2071595173
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.36690519
Short name T362
Test name
Test status
Simulation time 1730150136 ps
CPU time 13.57 seconds
Started Apr 23 02:38:55 PM PDT 24
Finished Apr 23 02:39:09 PM PDT 24
Peak memory 210212 kb
Host smart-503e3d37-5ddf-4b18-a834-835ad359bbeb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36690519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.36690519
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2227203264
Short name T79
Test name
Test status
Simulation time 139442994036 ps
CPU time 138.01 seconds
Started Apr 23 02:39:09 PM PDT 24
Finished Apr 23 02:41:27 PM PDT 24
Peak memory 212908 kb
Host smart-2ab2cec6-80c8-4188-818b-d8cf4c7f0d55
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227203264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2227203264
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3153820778
Short name T86
Test name
Test status
Simulation time 169150644 ps
CPU time 8.16 seconds
Started Apr 23 02:38:52 PM PDT 24
Finished Apr 23 02:39:01 PM PDT 24
Peak memory 210320 kb
Host smart-6ad0b4cb-7ae4-454f-8b1c-02271d3e8836
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153820778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3153820778
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1189862854
Short name T442
Test name
Test status
Simulation time 1966915793 ps
CPU time 25.38 seconds
Started Apr 23 02:39:01 PM PDT 24
Finished Apr 23 02:39:27 PM PDT 24
Peak memory 216524 kb
Host smart-205ea017-98c1-40cd-ae7e-cd26819ce760
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189862854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1189862854
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2841877899
Short name T394
Test name
Test status
Simulation time 10388406293 ps
CPU time 25.01 seconds
Started Apr 23 02:39:11 PM PDT 24
Finished Apr 23 02:39:37 PM PDT 24
Peak memory 217380 kb
Host smart-c8ae9760-493e-49a7-8d0a-15d8c1eaf93d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841877899 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2841877899
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1583471707
Short name T377
Test name
Test status
Simulation time 502339910 ps
CPU time 10.98 seconds
Started Apr 23 02:39:10 PM PDT 24
Finished Apr 23 02:39:21 PM PDT 24
Peak memory 210064 kb
Host smart-ec49b74e-c4a2-4602-ad30-5d94f8adc7ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583471707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1583471707
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3488762793
Short name T383
Test name
Test status
Simulation time 5459047665 ps
CPU time 92.49 seconds
Started Apr 23 02:39:11 PM PDT 24
Finished Apr 23 02:40:44 PM PDT 24
Peak memory 214920 kb
Host smart-c3b4d0d0-00e0-4c7e-95f6-cc55b022a7db
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488762793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3488762793
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4119519384
Short name T415
Test name
Test status
Simulation time 332043086 ps
CPU time 8.27 seconds
Started Apr 23 02:39:03 PM PDT 24
Finished Apr 23 02:39:12 PM PDT 24
Peak memory 210476 kb
Host smart-39a024bb-486a-4eef-b963-08a4615d06f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119519384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.4119519384
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.732008907
Short name T433
Test name
Test status
Simulation time 1141565114 ps
CPU time 18.76 seconds
Started Apr 23 02:38:59 PM PDT 24
Finished Apr 23 02:39:19 PM PDT 24
Peak memory 217564 kb
Host smart-c0bbe1d9-0465-47f4-a539-053128336c24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732008907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.732008907
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.919852817
Short name T103
Test name
Test status
Simulation time 33839748355 ps
CPU time 176 seconds
Started Apr 23 02:39:01 PM PDT 24
Finished Apr 23 02:41:57 PM PDT 24
Peak memory 213204 kb
Host smart-c91d354b-1180-49fd-b64c-9362920d2c9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919852817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.919852817
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.410271784
Short name T429
Test name
Test status
Simulation time 677342426 ps
CPU time 12.86 seconds
Started Apr 23 02:38:59 PM PDT 24
Finished Apr 23 02:39:13 PM PDT 24
Peak memory 214712 kb
Host smart-9996679f-f407-4517-89f5-e9c580212b78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410271784 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.410271784
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.104933514
Short name T73
Test name
Test status
Simulation time 1647461004 ps
CPU time 8.4 seconds
Started Apr 23 02:39:00 PM PDT 24
Finished Apr 23 02:39:09 PM PDT 24
Peak memory 210252 kb
Host smart-c7355819-2a69-42f5-be26-df49ba9051c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104933514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.104933514
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2604207005
Short name T75
Test name
Test status
Simulation time 69273345172 ps
CPU time 166.81 seconds
Started Apr 23 02:38:59 PM PDT 24
Finished Apr 23 02:41:46 PM PDT 24
Peak memory 218584 kb
Host smart-4d91f667-f0d9-406e-bd6f-b48b48e0de4e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604207005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2604207005
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3707433084
Short name T66
Test name
Test status
Simulation time 2872298688 ps
CPU time 25.2 seconds
Started Apr 23 02:38:59 PM PDT 24
Finished Apr 23 02:39:25 PM PDT 24
Peak memory 211216 kb
Host smart-d818fa05-f59d-414e-b410-f8067e18ab67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707433084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3707433084
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.988127935
Short name T447
Test name
Test status
Simulation time 28679160239 ps
CPU time 29.64 seconds
Started Apr 23 02:38:56 PM PDT 24
Finished Apr 23 02:39:26 PM PDT 24
Peak memory 217564 kb
Host smart-a82c6d79-22e9-40a1-8e70-19141bdd4bba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988127935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.988127935
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3185494392
Short name T109
Test name
Test status
Simulation time 13358188992 ps
CPU time 167.05 seconds
Started Apr 23 02:39:09 PM PDT 24
Finished Apr 23 02:41:57 PM PDT 24
Peak memory 214284 kb
Host smart-d1955450-235e-4c92-b8d5-57b15b7f0734
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185494392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3185494392
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.514443866
Short name T368
Test name
Test status
Simulation time 4937831351 ps
CPU time 15.99 seconds
Started Apr 23 02:39:00 PM PDT 24
Finished Apr 23 02:39:16 PM PDT 24
Peak memory 215372 kb
Host smart-999b8e8e-1b22-408f-bc68-a6dda609e724
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514443866 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.514443866
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1633758887
Short name T81
Test name
Test status
Simulation time 1655948635 ps
CPU time 13.31 seconds
Started Apr 23 02:39:06 PM PDT 24
Finished Apr 23 02:39:20 PM PDT 24
Peak memory 210096 kb
Host smart-b6604062-3ffc-4f69-ae3c-9b2c5a409bd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633758887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1633758887
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1767757441
Short name T78
Test name
Test status
Simulation time 72846508193 ps
CPU time 149 seconds
Started Apr 23 02:39:10 PM PDT 24
Finished Apr 23 02:41:40 PM PDT 24
Peak memory 214356 kb
Host smart-0955edf5-8e15-4bd4-aa83-78d59cc9b410
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767757441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1767757441
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3102788167
Short name T85
Test name
Test status
Simulation time 687930593 ps
CPU time 8.37 seconds
Started Apr 23 02:38:57 PM PDT 24
Finished Apr 23 02:39:06 PM PDT 24
Peak memory 210356 kb
Host smart-81ce3c4f-301e-4409-ab13-6d99ed941e34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102788167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3102788167
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4035113611
Short name T424
Test name
Test status
Simulation time 11883163005 ps
CPU time 26.65 seconds
Started Apr 23 02:38:55 PM PDT 24
Finished Apr 23 02:39:23 PM PDT 24
Peak memory 216572 kb
Host smart-1545b145-c5ab-4dbc-ab5b-6db5a8de9642
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035113611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.4035113611
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2950257490
Short name T104
Test name
Test status
Simulation time 13992837494 ps
CPU time 163.07 seconds
Started Apr 23 02:39:11 PM PDT 24
Finished Apr 23 02:41:55 PM PDT 24
Peak memory 213020 kb
Host smart-0f133195-2bf1-4f73-8667-12b48e83034f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950257490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2950257490
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4009425637
Short name T403
Test name
Test status
Simulation time 323951319 ps
CPU time 8.78 seconds
Started Apr 23 02:38:59 PM PDT 24
Finished Apr 23 02:39:09 PM PDT 24
Peak memory 215704 kb
Host smart-0a0c3a28-1cb8-4dd3-9889-8b9fc46ce84d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009425637 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4009425637
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1022539884
Short name T423
Test name
Test status
Simulation time 3418718943 ps
CPU time 13.45 seconds
Started Apr 23 02:38:56 PM PDT 24
Finished Apr 23 02:39:11 PM PDT 24
Peak memory 210336 kb
Host smart-d3e15eb0-f194-4c71-afb0-d9c77cc8a59a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022539884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1022539884
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.771480253
Short name T436
Test name
Test status
Simulation time 2867421995 ps
CPU time 37.22 seconds
Started Apr 23 02:38:57 PM PDT 24
Finished Apr 23 02:39:35 PM PDT 24
Peak memory 212476 kb
Host smart-4fb0419c-4bbc-47cf-bb72-3657c5588673
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771480253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.771480253
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3043435137
Short name T84
Test name
Test status
Simulation time 2786461987 ps
CPU time 23.57 seconds
Started Apr 23 02:39:11 PM PDT 24
Finished Apr 23 02:39:35 PM PDT 24
Peak memory 211116 kb
Host smart-1fbcbe26-0b13-420a-b226-231ff11fee71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043435137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3043435137
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2173490698
Short name T391
Test name
Test status
Simulation time 13674426626 ps
CPU time 33.64 seconds
Started Apr 23 02:39:02 PM PDT 24
Finished Apr 23 02:39:37 PM PDT 24
Peak memory 216960 kb
Host smart-4e5e51e8-58a3-4070-866b-3cbc95a73564
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173490698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2173490698
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3119505658
Short name T99
Test name
Test status
Simulation time 1417807272 ps
CPU time 162.64 seconds
Started Apr 23 02:38:57 PM PDT 24
Finished Apr 23 02:41:41 PM PDT 24
Peak memory 213044 kb
Host smart-eaaa60fe-3420-4eb8-acfe-b3ebf933895e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119505658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3119505658
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3403222491
Short name T397
Test name
Test status
Simulation time 188860698 ps
CPU time 9.41 seconds
Started Apr 23 02:39:04 PM PDT 24
Finished Apr 23 02:39:14 PM PDT 24
Peak memory 216012 kb
Host smart-4984d59f-b58b-4f0c-b580-56ed0552360a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403222491 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3403222491
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.368453241
Short name T386
Test name
Test status
Simulation time 6144770494 ps
CPU time 26.51 seconds
Started Apr 23 02:38:55 PM PDT 24
Finished Apr 23 02:39:22 PM PDT 24
Peak memory 211612 kb
Host smart-bfdd6df1-83e8-4ee1-b887-1e7ac8943138
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368453241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.368453241
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1200600461
Short name T87
Test name
Test status
Simulation time 30749094980 ps
CPU time 123.17 seconds
Started Apr 23 02:38:59 PM PDT 24
Finished Apr 23 02:41:03 PM PDT 24
Peak memory 212468 kb
Host smart-077f112e-a2cc-4610-bf72-71c5525da812
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200600461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1200600461
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3283507730
Short name T63
Test name
Test status
Simulation time 1641149046 ps
CPU time 11.07 seconds
Started Apr 23 02:38:57 PM PDT 24
Finished Apr 23 02:39:09 PM PDT 24
Peak memory 210368 kb
Host smart-39be7508-d367-4181-8801-1d2199f98611
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283507730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3283507730
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3053764946
Short name T382
Test name
Test status
Simulation time 10875490896 ps
CPU time 27.59 seconds
Started Apr 23 02:39:07 PM PDT 24
Finished Apr 23 02:39:35 PM PDT 24
Peak memory 218652 kb
Host smart-b37cef48-87c1-4c5d-92e4-4870e97c86f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053764946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3053764946
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2632301931
Short name T102
Test name
Test status
Simulation time 7659217987 ps
CPU time 90.51 seconds
Started Apr 23 02:39:14 PM PDT 24
Finished Apr 23 02:40:46 PM PDT 24
Peak memory 218608 kb
Host smart-659d6796-98f1-4ed5-83cc-53c7bec121ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632301931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2632301931
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2146539281
Short name T321
Test name
Test status
Simulation time 4342985403 ps
CPU time 32.67 seconds
Started Apr 23 02:39:05 PM PDT 24
Finished Apr 23 02:39:38 PM PDT 24
Peak memory 212468 kb
Host smart-ce3e63c2-329b-4527-ad44-a260e057c770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146539281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2146539281
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1143536650
Short name T41
Test name
Test status
Simulation time 2448928155 ps
CPU time 153.23 seconds
Started Apr 23 02:39:17 PM PDT 24
Finished Apr 23 02:41:51 PM PDT 24
Peak memory 217356 kb
Host smart-8348f7d7-1a32-4062-8003-a53dc920c8e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143536650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1143536650
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2382463084
Short name T316
Test name
Test status
Simulation time 4844854880 ps
CPU time 47.6 seconds
Started Apr 23 02:39:15 PM PDT 24
Finished Apr 23 02:40:03 PM PDT 24
Peak memory 215264 kb
Host smart-65dceae9-b87f-4a93-8c06-1bbb52c6fca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382463084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2382463084
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.684167388
Short name T205
Test name
Test status
Simulation time 9989399240 ps
CPU time 23.81 seconds
Started Apr 23 02:39:17 PM PDT 24
Finished Apr 23 02:39:42 PM PDT 24
Peak memory 211652 kb
Host smart-be1e209a-6517-4b56-a98e-b479431ab958
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=684167388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.684167388
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.4236479916
Short name T29
Test name
Test status
Simulation time 4077084251 ps
CPU time 139.47 seconds
Started Apr 23 02:39:13 PM PDT 24
Finished Apr 23 02:41:33 PM PDT 24
Peak memory 238940 kb
Host smart-9c3092c0-17ea-4da3-beb7-9e6f3379846b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236479916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.4236479916
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3355563926
Short name T211
Test name
Test status
Simulation time 1815766075 ps
CPU time 19.83 seconds
Started Apr 23 02:39:16 PM PDT 24
Finished Apr 23 02:39:37 PM PDT 24
Peak memory 217204 kb
Host smart-7b5430e4-e6ce-4f48-a166-a0f079f734be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355563926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3355563926
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4034236056
Short name T227
Test name
Test status
Simulation time 10551343746 ps
CPU time 108.26 seconds
Started Apr 23 02:39:17 PM PDT 24
Finished Apr 23 02:41:06 PM PDT 24
Peak memory 221212 kb
Host smart-a21e666b-1432-413c-ae8c-04f68c81e530
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034236056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4034236056
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3915570246
Short name T131
Test name
Test status
Simulation time 9065914032 ps
CPU time 23.12 seconds
Started Apr 23 02:39:17 PM PDT 24
Finished Apr 23 02:39:40 PM PDT 24
Peak memory 212656 kb
Host smart-c95a685c-5138-498e-a88f-4b88e4e59966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915570246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3915570246
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1567428635
Short name T139
Test name
Test status
Simulation time 16037357187 ps
CPU time 276.78 seconds
Started Apr 23 02:39:06 PM PDT 24
Finished Apr 23 02:43:43 PM PDT 24
Peak memory 234048 kb
Host smart-2b389ccc-a3cb-49e2-823d-463d4c0cdb6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567428635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1567428635
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3620134802
Short name T283
Test name
Test status
Simulation time 19223804808 ps
CPU time 23.73 seconds
Started Apr 23 02:39:15 PM PDT 24
Finished Apr 23 02:39:40 PM PDT 24
Peak memory 213032 kb
Host smart-7a04548d-ce4b-49fa-bf9d-a9fdee4b2640
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3620134802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3620134802
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2245744202
Short name T282
Test name
Test status
Simulation time 15762650140 ps
CPU time 43.78 seconds
Started Apr 23 02:39:10 PM PDT 24
Finished Apr 23 02:39:54 PM PDT 24
Peak memory 218288 kb
Host smart-1ea67541-4734-49fb-bf98-7bae95356f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245744202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2245744202
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2095337797
Short name T70
Test name
Test status
Simulation time 28584616901 ps
CPU time 95.97 seconds
Started Apr 23 02:39:14 PM PDT 24
Finished Apr 23 02:40:51 PM PDT 24
Peak memory 222412 kb
Host smart-d9e96e2a-2c71-46e7-9402-c9288910d7b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095337797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2095337797
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3994140590
Short name T160
Test name
Test status
Simulation time 1185051702 ps
CPU time 15.94 seconds
Started Apr 23 02:39:19 PM PDT 24
Finished Apr 23 02:39:36 PM PDT 24
Peak memory 211660 kb
Host smart-6075afd3-d26e-4f60-974a-2dc684a8a79b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994140590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3994140590
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1961332158
Short name T166
Test name
Test status
Simulation time 191896343186 ps
CPU time 465.98 seconds
Started Apr 23 02:39:18 PM PDT 24
Finished Apr 23 02:47:05 PM PDT 24
Peak memory 228468 kb
Host smart-1a0a4eb9-e912-4048-b9cd-3c82de0ef664
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961332158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1961332158
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.178676638
Short name T236
Test name
Test status
Simulation time 31447494614 ps
CPU time 66.09 seconds
Started Apr 23 02:39:22 PM PDT 24
Finished Apr 23 02:40:29 PM PDT 24
Peak memory 213164 kb
Host smart-7ddc5d25-7133-4ea0-b8e2-0c2896aabdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178676638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.178676638
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3344278217
Short name T322
Test name
Test status
Simulation time 2587126562 ps
CPU time 24.27 seconds
Started Apr 23 02:39:18 PM PDT 24
Finished Apr 23 02:39:43 PM PDT 24
Peak memory 212532 kb
Host smart-6815c54f-fc2d-4c81-9fb4-2ed71a05685c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3344278217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3344278217
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1683534571
Short name T319
Test name
Test status
Simulation time 21443261827 ps
CPU time 38.38 seconds
Started Apr 23 02:39:20 PM PDT 24
Finished Apr 23 02:39:59 PM PDT 24
Peak memory 218376 kb
Host smart-f3d1536f-8442-4d35-a85a-2c34cb338f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683534571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1683534571
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4032857456
Short name T72
Test name
Test status
Simulation time 4464524631 ps
CPU time 65.02 seconds
Started Apr 23 02:39:22 PM PDT 24
Finished Apr 23 02:40:27 PM PDT 24
Peak memory 219676 kb
Host smart-f33d2963-213b-4312-8b30-71c5a8d46228
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032857456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.4032857456
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1202117959
Short name T146
Test name
Test status
Simulation time 19546001341 ps
CPU time 18.48 seconds
Started Apr 23 02:39:22 PM PDT 24
Finished Apr 23 02:39:41 PM PDT 24
Peak memory 212592 kb
Host smart-a4282ce1-d0f2-47ea-9833-53d7b139c7f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202117959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1202117959
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2561356397
Short name T137
Test name
Test status
Simulation time 4773403050 ps
CPU time 130.3 seconds
Started Apr 23 02:39:20 PM PDT 24
Finished Apr 23 02:41:30 PM PDT 24
Peak memory 217048 kb
Host smart-d8b1febb-c298-403b-b8c8-10cdd0a5e453
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561356397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2561356397
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.295031042
Short name T208
Test name
Test status
Simulation time 27868753308 ps
CPU time 66.27 seconds
Started Apr 23 02:39:27 PM PDT 24
Finished Apr 23 02:40:34 PM PDT 24
Peak memory 213132 kb
Host smart-b4d6ea50-b1b6-4d0e-a5f2-1a8eac3c37cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295031042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.295031042
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.4091456890
Short name T113
Test name
Test status
Simulation time 18162142008 ps
CPU time 33.62 seconds
Started Apr 23 02:39:22 PM PDT 24
Finished Apr 23 02:39:56 PM PDT 24
Peak memory 211512 kb
Host smart-070e4e52-254c-41bc-b759-9cd83d3db065
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4091456890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.4091456890
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3399222137
Short name T161
Test name
Test status
Simulation time 8372220965 ps
CPU time 64.99 seconds
Started Apr 23 02:39:20 PM PDT 24
Finished Apr 23 02:40:25 PM PDT 24
Peak memory 218212 kb
Host smart-20bfaf07-0076-4b73-84e7-f587ea360f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399222137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3399222137
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2017204702
Short name T213
Test name
Test status
Simulation time 56485527218 ps
CPU time 117.44 seconds
Started Apr 23 02:39:18 PM PDT 24
Finished Apr 23 02:41:16 PM PDT 24
Peak memory 220560 kb
Host smart-aba79471-359c-4620-93ac-18f530cc9c85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017204702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2017204702
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3210227266
Short name T159
Test name
Test status
Simulation time 4187172084 ps
CPU time 31.38 seconds
Started Apr 23 02:39:22 PM PDT 24
Finished Apr 23 02:39:54 PM PDT 24
Peak memory 212200 kb
Host smart-98b67dba-1a30-498b-ae2a-f2795a6148bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210227266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3210227266
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.789906512
Short name T255
Test name
Test status
Simulation time 2870591851 ps
CPU time 220.89 seconds
Started Apr 23 02:39:21 PM PDT 24
Finished Apr 23 02:43:02 PM PDT 24
Peak memory 228536 kb
Host smart-ba2dde41-f054-49fe-a413-3357ba0bc942
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789906512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.789906512
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3332978251
Short name T339
Test name
Test status
Simulation time 23109616072 ps
CPU time 50.69 seconds
Started Apr 23 02:39:25 PM PDT 24
Finished Apr 23 02:40:16 PM PDT 24
Peak memory 215500 kb
Host smart-8d4a20a2-f4bb-4cce-9b6c-2291a36b07c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332978251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3332978251
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3593118763
Short name T14
Test name
Test status
Simulation time 705586976 ps
CPU time 10.35 seconds
Started Apr 23 02:39:28 PM PDT 24
Finished Apr 23 02:39:40 PM PDT 24
Peak memory 212444 kb
Host smart-53675448-2d16-4fc8-93cb-9c3bbd1fd47a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3593118763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3593118763
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1735114216
Short name T140
Test name
Test status
Simulation time 359596054 ps
CPU time 20.38 seconds
Started Apr 23 02:39:22 PM PDT 24
Finished Apr 23 02:39:43 PM PDT 24
Peak memory 216372 kb
Host smart-580019d1-5b92-4b02-a402-7b6b07419614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735114216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1735114216
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1288362861
Short name T38
Test name
Test status
Simulation time 31940797525 ps
CPU time 60.43 seconds
Started Apr 23 02:39:34 PM PDT 24
Finished Apr 23 02:40:35 PM PDT 24
Peak memory 221140 kb
Host smart-5cb3452e-8ce3-402e-b35a-524b13990369
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288362861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1288362861
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2069967636
Short name T56
Test name
Test status
Simulation time 174445888 ps
CPU time 8.83 seconds
Started Apr 23 02:39:22 PM PDT 24
Finished Apr 23 02:39:31 PM PDT 24
Peak memory 211720 kb
Host smart-f800ae3c-562a-4b06-a721-8e46ae437fc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069967636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2069967636
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4196110601
Short name T144
Test name
Test status
Simulation time 144794872961 ps
CPU time 335.7 seconds
Started Apr 23 02:39:30 PM PDT 24
Finished Apr 23 02:45:06 PM PDT 24
Peak memory 224848 kb
Host smart-89a41c2b-d012-4fc8-8ead-b735a0d7cd98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196110601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.4196110601
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.4079631159
Short name T169
Test name
Test status
Simulation time 35896042421 ps
CPU time 65.37 seconds
Started Apr 23 02:39:22 PM PDT 24
Finished Apr 23 02:40:28 PM PDT 24
Peak memory 215212 kb
Host smart-20b726fe-ad42-4602-a034-8ae4eb0cc4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079631159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.4079631159
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2538351222
Short name T20
Test name
Test status
Simulation time 2989758851 ps
CPU time 26.52 seconds
Started Apr 23 02:39:33 PM PDT 24
Finished Apr 23 02:40:00 PM PDT 24
Peak memory 211836 kb
Host smart-54c65b9d-4cf0-4604-86f2-9f551a324aef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2538351222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2538351222
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.253124304
Short name T281
Test name
Test status
Simulation time 1189556839 ps
CPU time 27.31 seconds
Started Apr 23 02:39:22 PM PDT 24
Finished Apr 23 02:39:50 PM PDT 24
Peak memory 218228 kb
Host smart-733a589c-af0d-485c-84e8-baa454857d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253124304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.253124304
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1915376213
Short name T312
Test name
Test status
Simulation time 860172470 ps
CPU time 52.17 seconds
Started Apr 23 02:39:32 PM PDT 24
Finished Apr 23 02:40:25 PM PDT 24
Peak memory 219636 kb
Host smart-ecb775a0-6bdb-43b6-bb0b-7fac76d17908
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915376213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1915376213
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3632591854
Short name T173
Test name
Test status
Simulation time 32959241186 ps
CPU time 25.4 seconds
Started Apr 23 02:39:35 PM PDT 24
Finished Apr 23 02:40:01 PM PDT 24
Peak memory 212576 kb
Host smart-8398da1b-37f4-43be-a4a6-d9e71c9c4e2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632591854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3632591854
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.13911207
Short name T328
Test name
Test status
Simulation time 4498960590 ps
CPU time 210.08 seconds
Started Apr 23 02:39:35 PM PDT 24
Finished Apr 23 02:43:06 PM PDT 24
Peak memory 237928 kb
Host smart-f3b14bba-8c71-4931-9b05-7980459e21c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13911207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_co
rrupt_sig_fatal_chk.13911207
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.621094048
Short name T267
Test name
Test status
Simulation time 3267352551 ps
CPU time 38.2 seconds
Started Apr 23 02:39:27 PM PDT 24
Finished Apr 23 02:40:06 PM PDT 24
Peak memory 215104 kb
Host smart-5541d91d-9291-4395-8bc1-606a2b7994ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621094048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.621094048
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1878415726
Short name T132
Test name
Test status
Simulation time 5992800089 ps
CPU time 34.35 seconds
Started Apr 23 02:39:26 PM PDT 24
Finished Apr 23 02:40:01 PM PDT 24
Peak memory 211772 kb
Host smart-2e7568b0-4721-4400-9dae-2c9ad1efa076
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1878415726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1878415726
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2628515343
Short name T172
Test name
Test status
Simulation time 12485189126 ps
CPU time 62.66 seconds
Started Apr 23 02:39:33 PM PDT 24
Finished Apr 23 02:40:36 PM PDT 24
Peak memory 215280 kb
Host smart-ced55143-f987-4ff6-905e-c0a7031db2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628515343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2628515343
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.87226944
Short name T315
Test name
Test status
Simulation time 13780993792 ps
CPU time 80.29 seconds
Started Apr 23 02:39:34 PM PDT 24
Finished Apr 23 02:40:55 PM PDT 24
Peak memory 219624 kb
Host smart-8656bb40-0b36-460e-a01b-5790e5de1cf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87226944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 14.rom_ctrl_stress_all.87226944
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3100501799
Short name T246
Test name
Test status
Simulation time 11937902274 ps
CPU time 24.61 seconds
Started Apr 23 02:39:32 PM PDT 24
Finished Apr 23 02:39:58 PM PDT 24
Peak memory 212496 kb
Host smart-3c3fc50f-6bb0-4284-917a-15363702eb76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100501799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3100501799
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3229019304
Short name T27
Test name
Test status
Simulation time 344871125261 ps
CPU time 796.32 seconds
Started Apr 23 02:39:26 PM PDT 24
Finished Apr 23 02:52:43 PM PDT 24
Peak memory 240652 kb
Host smart-368e45d2-c4ff-4f24-9fe7-5b9784504c5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229019304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3229019304
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3590975385
Short name T340
Test name
Test status
Simulation time 34771348704 ps
CPU time 38.32 seconds
Started Apr 23 02:39:26 PM PDT 24
Finished Apr 23 02:40:05 PM PDT 24
Peak memory 215308 kb
Host smart-c4f90bbc-c481-4a02-acbc-13555cba90b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590975385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3590975385
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.137385486
Short name T112
Test name
Test status
Simulation time 1810395897 ps
CPU time 20.78 seconds
Started Apr 23 02:39:34 PM PDT 24
Finished Apr 23 02:39:55 PM PDT 24
Peak memory 211600 kb
Host smart-b52b2fa9-46ef-49b5-a325-930a0abe5a89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=137385486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.137385486
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.82919443
Short name T5
Test name
Test status
Simulation time 1326187943 ps
CPU time 20.5 seconds
Started Apr 23 02:39:32 PM PDT 24
Finished Apr 23 02:39:53 PM PDT 24
Peak memory 218000 kb
Host smart-ffa1fe72-969f-4005-ba8e-d9076a68d907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82919443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.82919443
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2375686476
Short name T293
Test name
Test status
Simulation time 7740498668 ps
CPU time 41.79 seconds
Started Apr 23 02:39:36 PM PDT 24
Finished Apr 23 02:40:19 PM PDT 24
Peak memory 214784 kb
Host smart-648e6cd7-9773-4ed5-8a1f-3cd83b658d83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375686476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2375686476
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1812562642
Short name T18
Test name
Test status
Simulation time 38713667022 ps
CPU time 1686.99 seconds
Started Apr 23 02:39:26 PM PDT 24
Finished Apr 23 03:07:34 PM PDT 24
Peak memory 237688 kb
Host smart-cc119b6b-376c-4b7f-b17d-924fc5af3e75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812562642 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1812562642
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.116702701
Short name T259
Test name
Test status
Simulation time 174160852 ps
CPU time 8.49 seconds
Started Apr 23 02:39:26 PM PDT 24
Finished Apr 23 02:39:35 PM PDT 24
Peak memory 211676 kb
Host smart-4a370a7e-45dc-4987-82a3-a1581777f587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116702701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.116702701
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2622699233
Short name T178
Test name
Test status
Simulation time 9816863199 ps
CPU time 271.58 seconds
Started Apr 23 02:39:29 PM PDT 24
Finished Apr 23 02:44:01 PM PDT 24
Peak memory 219552 kb
Host smart-1c5083ce-021c-4adf-8b70-e3316cca344a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622699233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2622699233
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.672654011
Short name T306
Test name
Test status
Simulation time 357014987 ps
CPU time 9.98 seconds
Started Apr 23 02:39:28 PM PDT 24
Finished Apr 23 02:39:39 PM PDT 24
Peak memory 212460 kb
Host smart-5988dea5-381a-41ff-9cdb-779154c79320
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=672654011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.672654011
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1753714651
Short name T195
Test name
Test status
Simulation time 31073399695 ps
CPU time 99.54 seconds
Started Apr 23 02:39:29 PM PDT 24
Finished Apr 23 02:41:09 PM PDT 24
Peak memory 219884 kb
Host smart-f77d1729-8873-44ea-a01f-be8b30117e2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753714651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1753714651
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1140541765
Short name T303
Test name
Test status
Simulation time 3596390877 ps
CPU time 29.09 seconds
Started Apr 23 02:39:26 PM PDT 24
Finished Apr 23 02:39:56 PM PDT 24
Peak memory 212292 kb
Host smart-e6131567-48c9-4b06-80d0-f068c4a7d71a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140541765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1140541765
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3347854874
Short name T318
Test name
Test status
Simulation time 39319337717 ps
CPU time 540.58 seconds
Started Apr 23 02:39:28 PM PDT 24
Finished Apr 23 02:48:29 PM PDT 24
Peak memory 241064 kb
Host smart-32b61783-c449-41c5-a884-9e918b32ca82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347854874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3347854874
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3017390584
Short name T269
Test name
Test status
Simulation time 20311167201 ps
CPU time 50.51 seconds
Started Apr 23 02:39:27 PM PDT 24
Finished Apr 23 02:40:18 PM PDT 24
Peak memory 215216 kb
Host smart-aabe1fca-0110-4d57-b6cc-7a602cea7da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017390584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3017390584
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2887640503
Short name T300
Test name
Test status
Simulation time 6529324003 ps
CPU time 27.88 seconds
Started Apr 23 02:39:32 PM PDT 24
Finished Apr 23 02:40:00 PM PDT 24
Peak memory 212104 kb
Host smart-2a6e3d9b-fb52-4529-86be-ceda654bfe1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2887640503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2887640503
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1997727689
Short name T51
Test name
Test status
Simulation time 706983005 ps
CPU time 19.99 seconds
Started Apr 23 02:39:26 PM PDT 24
Finished Apr 23 02:39:46 PM PDT 24
Peak memory 217076 kb
Host smart-b8964b58-ca22-4c4d-a0b5-70222f22eb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997727689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1997727689
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2147108594
Short name T301
Test name
Test status
Simulation time 99121807410 ps
CPU time 109.3 seconds
Started Apr 23 02:39:26 PM PDT 24
Finished Apr 23 02:41:16 PM PDT 24
Peak memory 218588 kb
Host smart-508f435e-9794-46ed-92be-2d8b186b409c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147108594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2147108594
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.4216030262
Short name T184
Test name
Test status
Simulation time 915728536 ps
CPU time 8.32 seconds
Started Apr 23 02:39:32 PM PDT 24
Finished Apr 23 02:39:41 PM PDT 24
Peak memory 211668 kb
Host smart-51a9df82-ca1a-44a1-8595-d164470260a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216030262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.4216030262
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3176966005
Short name T354
Test name
Test status
Simulation time 5068288544 ps
CPU time 264.62 seconds
Started Apr 23 02:39:33 PM PDT 24
Finished Apr 23 02:43:58 PM PDT 24
Peak memory 225312 kb
Host smart-d084f025-f931-45a0-9ecd-8fa651111310
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176966005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3176966005
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.670730830
Short name T333
Test name
Test status
Simulation time 688577574 ps
CPU time 18.7 seconds
Started Apr 23 02:39:34 PM PDT 24
Finished Apr 23 02:39:53 PM PDT 24
Peak memory 215040 kb
Host smart-08007def-bd3d-45ff-9967-8f889e57d96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670730830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.670730830
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2192781988
Short name T129
Test name
Test status
Simulation time 185913919 ps
CPU time 10.18 seconds
Started Apr 23 02:39:36 PM PDT 24
Finished Apr 23 02:39:47 PM PDT 24
Peak memory 212804 kb
Host smart-d2853719-8abb-4dd4-9347-7280323545a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2192781988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2192781988
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.123831958
Short name T196
Test name
Test status
Simulation time 10718575420 ps
CPU time 37.94 seconds
Started Apr 23 02:39:28 PM PDT 24
Finished Apr 23 02:40:06 PM PDT 24
Peak memory 218392 kb
Host smart-ff14c9bc-b8c6-46b3-a216-c25b04a83f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123831958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.123831958
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1490175335
Short name T341
Test name
Test status
Simulation time 4287744481 ps
CPU time 52.71 seconds
Started Apr 23 02:39:28 PM PDT 24
Finished Apr 23 02:40:22 PM PDT 24
Peak memory 219660 kb
Host smart-b1f0d99d-a6ae-4b5c-8f88-3b83e8923e6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490175335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1490175335
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2266341212
Short name T336
Test name
Test status
Simulation time 19697454016 ps
CPU time 32.28 seconds
Started Apr 23 02:39:35 PM PDT 24
Finished Apr 23 02:40:08 PM PDT 24
Peak memory 212580 kb
Host smart-99de72d4-4081-4269-9e12-4d53b52a66db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266341212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2266341212
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3113916192
Short name T212
Test name
Test status
Simulation time 128294910377 ps
CPU time 409.62 seconds
Started Apr 23 02:39:33 PM PDT 24
Finished Apr 23 02:46:24 PM PDT 24
Peak memory 238060 kb
Host smart-ff9e86be-f117-4ea2-a2a1-58af01ccda07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113916192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3113916192
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3591440004
Short name T338
Test name
Test status
Simulation time 674789262 ps
CPU time 19.13 seconds
Started Apr 23 02:39:31 PM PDT 24
Finished Apr 23 02:39:51 PM PDT 24
Peak memory 214836 kb
Host smart-074498a9-4d30-4cad-8303-86e6a563be11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591440004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3591440004
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1330152943
Short name T345
Test name
Test status
Simulation time 271347877 ps
CPU time 12.25 seconds
Started Apr 23 02:39:33 PM PDT 24
Finished Apr 23 02:39:46 PM PDT 24
Peak memory 212564 kb
Host smart-c59124ab-4b79-4d4a-8316-f82d3eb3e39f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330152943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1330152943
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1245239702
Short name T1
Test name
Test status
Simulation time 19838258762 ps
CPU time 54.55 seconds
Started Apr 23 02:39:32 PM PDT 24
Finished Apr 23 02:40:28 PM PDT 24
Peak memory 215796 kb
Host smart-d21e657d-7433-456e-abb8-4fc2866dda27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245239702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1245239702
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.544884768
Short name T197
Test name
Test status
Simulation time 30154896210 ps
CPU time 76.16 seconds
Started Apr 23 02:39:31 PM PDT 24
Finished Apr 23 02:40:47 PM PDT 24
Peak memory 219664 kb
Host smart-cc148d73-3c92-4e59-bb50-cf0344011196
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544884768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.544884768
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2528664158
Short name T203
Test name
Test status
Simulation time 414670137 ps
CPU time 8.36 seconds
Started Apr 23 02:39:07 PM PDT 24
Finished Apr 23 02:39:16 PM PDT 24
Peak memory 211612 kb
Host smart-349b80e3-016b-47a2-aedd-cbfced8f2e34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528664158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2528664158
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2685715818
Short name T280
Test name
Test status
Simulation time 10446924047 ps
CPU time 350.86 seconds
Started Apr 23 02:39:07 PM PDT 24
Finished Apr 23 02:44:58 PM PDT 24
Peak memory 230060 kb
Host smart-6ae9c898-29be-46f6-b45e-af6c5d872ce1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685715818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2685715818
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3205286124
Short name T278
Test name
Test status
Simulation time 11352640239 ps
CPU time 52.13 seconds
Started Apr 23 02:39:10 PM PDT 24
Finished Apr 23 02:40:03 PM PDT 24
Peak memory 215372 kb
Host smart-c3932077-d2d7-40ac-b0ef-d86d93592695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205286124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3205286124
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1792156927
Short name T163
Test name
Test status
Simulation time 1036017342 ps
CPU time 13.55 seconds
Started Apr 23 02:39:17 PM PDT 24
Finished Apr 23 02:39:32 PM PDT 24
Peak memory 211680 kb
Host smart-239472f4-ba64-4642-923e-2eb466df3179
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1792156927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1792156927
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1597351719
Short name T36
Test name
Test status
Simulation time 1904868704 ps
CPU time 232.09 seconds
Started Apr 23 02:39:10 PM PDT 24
Finished Apr 23 02:43:03 PM PDT 24
Peak memory 237080 kb
Host smart-7d92b5bc-4285-4501-8325-6b92f9c5a807
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597351719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1597351719
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2915011740
Short name T127
Test name
Test status
Simulation time 4627838632 ps
CPU time 51.26 seconds
Started Apr 23 02:39:17 PM PDT 24
Finished Apr 23 02:40:09 PM PDT 24
Peak memory 218316 kb
Host smart-dc04cee7-9d0c-497e-89a5-d79e5220902a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915011740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2915011740
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2520593637
Short name T330
Test name
Test status
Simulation time 23709342033 ps
CPU time 64.76 seconds
Started Apr 23 02:39:13 PM PDT 24
Finished Apr 23 02:40:18 PM PDT 24
Peak memory 220028 kb
Host smart-83645155-5791-4f57-9d8a-b330669e263c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520593637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2520593637
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.370632429
Short name T352
Test name
Test status
Simulation time 167560012 ps
CPU time 8.3 seconds
Started Apr 23 02:39:33 PM PDT 24
Finished Apr 23 02:39:42 PM PDT 24
Peak memory 211632 kb
Host smart-a08ed326-d12c-4d62-90ce-c8eec6424a21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370632429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.370632429
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3119011278
Short name T359
Test name
Test status
Simulation time 361589673579 ps
CPU time 886.08 seconds
Started Apr 23 02:39:35 PM PDT 24
Finished Apr 23 02:54:22 PM PDT 24
Peak memory 237732 kb
Host smart-e8289921-49e2-4f86-a7d7-a00cbd168c8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119011278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3119011278
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.703427419
Short name T317
Test name
Test status
Simulation time 8006556900 ps
CPU time 64.82 seconds
Started Apr 23 02:39:27 PM PDT 24
Finished Apr 23 02:40:33 PM PDT 24
Peak memory 215368 kb
Host smart-d327712a-8410-433d-81cd-d63bdb3934e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703427419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.703427419
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2193895887
Short name T270
Test name
Test status
Simulation time 8401274498 ps
CPU time 33.36 seconds
Started Apr 23 02:39:30 PM PDT 24
Finished Apr 23 02:40:04 PM PDT 24
Peak memory 211928 kb
Host smart-69748e6c-b1a0-4b20-aef7-367325ffaf07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2193895887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2193895887
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3681954163
Short name T141
Test name
Test status
Simulation time 1753187958 ps
CPU time 30.38 seconds
Started Apr 23 02:39:33 PM PDT 24
Finished Apr 23 02:40:04 PM PDT 24
Peak memory 217008 kb
Host smart-99caed74-07c2-414f-9eec-146fbd8ed396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681954163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3681954163
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3770972871
Short name T142
Test name
Test status
Simulation time 6418732868 ps
CPU time 35.3 seconds
Started Apr 23 02:39:35 PM PDT 24
Finished Apr 23 02:40:11 PM PDT 24
Peak memory 212956 kb
Host smart-eb678bba-dce0-448a-bda8-6d11eec969fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770972871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3770972871
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1820941966
Short name T265
Test name
Test status
Simulation time 1767334797 ps
CPU time 17.3 seconds
Started Apr 23 02:39:42 PM PDT 24
Finished Apr 23 02:40:00 PM PDT 24
Peak memory 211632 kb
Host smart-9a5ad47c-ea58-4cc7-ae94-e07bd89e06a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820941966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1820941966
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1725194505
Short name T254
Test name
Test status
Simulation time 71681144075 ps
CPU time 286.89 seconds
Started Apr 23 02:39:33 PM PDT 24
Finished Apr 23 02:44:20 PM PDT 24
Peak memory 238052 kb
Host smart-d34f44e3-f0d5-42dc-b719-2846f84e2909
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725194505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1725194505
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2102343158
Short name T241
Test name
Test status
Simulation time 662283995 ps
CPU time 19.03 seconds
Started Apr 23 02:39:31 PM PDT 24
Finished Apr 23 02:39:51 PM PDT 24
Peak memory 215000 kb
Host smart-d6f92d63-508c-4e4d-9e73-59ec526fd441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102343158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2102343158
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1077869026
Short name T242
Test name
Test status
Simulation time 345535013 ps
CPU time 10.7 seconds
Started Apr 23 02:39:32 PM PDT 24
Finished Apr 23 02:39:43 PM PDT 24
Peak memory 212916 kb
Host smart-67755a35-fc44-4f64-a09b-f142ad822291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1077869026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1077869026
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3196573523
Short name T12
Test name
Test status
Simulation time 4534308080 ps
CPU time 27.68 seconds
Started Apr 23 02:39:33 PM PDT 24
Finished Apr 23 02:40:02 PM PDT 24
Peak memory 217316 kb
Host smart-ce312c01-549d-4f5a-ab2c-487d4186247a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196573523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3196573523
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2003280397
Short name T164
Test name
Test status
Simulation time 13758079077 ps
CPU time 143.8 seconds
Started Apr 23 02:39:34 PM PDT 24
Finished Apr 23 02:41:59 PM PDT 24
Peak memory 221840 kb
Host smart-30aa7ad6-95fc-4b61-94b0-965a3a0ed83e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003280397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2003280397
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1856347098
Short name T148
Test name
Test status
Simulation time 2864819921 ps
CPU time 24.8 seconds
Started Apr 23 02:39:32 PM PDT 24
Finished Apr 23 02:39:58 PM PDT 24
Peak memory 211664 kb
Host smart-577ed3e5-a22e-4d9a-ae48-0d5d2bdd25b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856347098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1856347098
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1900871427
Short name T290
Test name
Test status
Simulation time 53644684115 ps
CPU time 587.81 seconds
Started Apr 23 02:39:31 PM PDT 24
Finished Apr 23 02:49:19 PM PDT 24
Peak memory 234292 kb
Host smart-9a35c88c-98c6-4dfc-89d0-38c1eb3f5732
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900871427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1900871427
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2584314956
Short name T21
Test name
Test status
Simulation time 344233223 ps
CPU time 18.8 seconds
Started Apr 23 02:39:32 PM PDT 24
Finished Apr 23 02:39:51 PM PDT 24
Peak memory 217172 kb
Host smart-6f0e95c5-fda8-445c-ae78-c191aff25cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584314956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2584314956
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2486424084
Short name T145
Test name
Test status
Simulation time 338521353 ps
CPU time 10.52 seconds
Started Apr 23 02:39:32 PM PDT 24
Finished Apr 23 02:39:44 PM PDT 24
Peak memory 212440 kb
Host smart-17c54165-fd9b-47e4-a23e-55bdcd866c40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2486424084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2486424084
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2999723445
Short name T134
Test name
Test status
Simulation time 1001213546 ps
CPU time 27.11 seconds
Started Apr 23 02:39:32 PM PDT 24
Finished Apr 23 02:39:59 PM PDT 24
Peak memory 217580 kb
Host smart-6c829d37-aff1-4c73-91c4-ec5966678fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999723445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2999723445
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3300424609
Short name T323
Test name
Test status
Simulation time 167538828 ps
CPU time 8.4 seconds
Started Apr 23 02:39:45 PM PDT 24
Finished Apr 23 02:39:54 PM PDT 24
Peak memory 211664 kb
Host smart-fc8e0f8f-6546-4b34-bf7c-a371de3e1e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300424609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3300424609
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1971853432
Short name T256
Test name
Test status
Simulation time 22618251254 ps
CPU time 255.45 seconds
Started Apr 23 02:39:34 PM PDT 24
Finished Apr 23 02:43:50 PM PDT 24
Peak memory 240208 kb
Host smart-298fc506-2018-4307-9014-ba09b17a1414
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971853432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1971853432
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.966891908
Short name T135
Test name
Test status
Simulation time 1372168749 ps
CPU time 28.05 seconds
Started Apr 23 02:39:33 PM PDT 24
Finished Apr 23 02:40:02 PM PDT 24
Peak memory 213928 kb
Host smart-b0d2b31a-6314-4096-bbd2-d01dc5492294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966891908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.966891908
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3271273382
Short name T297
Test name
Test status
Simulation time 185363794 ps
CPU time 10.61 seconds
Started Apr 23 02:39:34 PM PDT 24
Finished Apr 23 02:39:46 PM PDT 24
Peak memory 212496 kb
Host smart-c37e3faa-ca90-4a52-be48-e79428ab0904
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3271273382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3271273382
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1888847565
Short name T207
Test name
Test status
Simulation time 22778662308 ps
CPU time 54.44 seconds
Started Apr 23 02:39:36 PM PDT 24
Finished Apr 23 02:40:31 PM PDT 24
Peak memory 214516 kb
Host smart-d4e79527-d5f7-4daa-82b0-9ca1d17673b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888847565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1888847565
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.237427324
Short name T3
Test name
Test status
Simulation time 7004191173 ps
CPU time 79.04 seconds
Started Apr 23 02:39:35 PM PDT 24
Finished Apr 23 02:40:55 PM PDT 24
Peak memory 221172 kb
Host smart-e2669091-2e53-4727-bfb4-814d2a6e169d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237427324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.237427324
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2954063675
Short name T337
Test name
Test status
Simulation time 257369711 ps
CPU time 9.89 seconds
Started Apr 23 02:39:37 PM PDT 24
Finished Apr 23 02:39:48 PM PDT 24
Peak memory 211628 kb
Host smart-54abd41b-e13e-45b0-85ea-cb9551e968ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954063675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2954063675
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2974514337
Short name T23
Test name
Test status
Simulation time 102723552177 ps
CPU time 657.65 seconds
Started Apr 23 02:39:35 PM PDT 24
Finished Apr 23 02:50:33 PM PDT 24
Peak memory 229988 kb
Host smart-73f42703-6b84-481e-bd6e-6838c47ac4db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974514337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2974514337
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3350338727
Short name T165
Test name
Test status
Simulation time 7017996097 ps
CPU time 58.19 seconds
Started Apr 23 02:39:35 PM PDT 24
Finished Apr 23 02:40:34 PM PDT 24
Peak memory 215288 kb
Host smart-5249066d-dc30-4a1c-b26c-622d3de79501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350338727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3350338727
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.729173493
Short name T157
Test name
Test status
Simulation time 3600141645 ps
CPU time 28.71 seconds
Started Apr 23 02:39:41 PM PDT 24
Finished Apr 23 02:40:10 PM PDT 24
Peak memory 212464 kb
Host smart-35faec52-7029-4825-9072-ec2a06752ab1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=729173493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.729173493
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1220189223
Short name T275
Test name
Test status
Simulation time 7906887190 ps
CPU time 50.97 seconds
Started Apr 23 02:39:35 PM PDT 24
Finished Apr 23 02:40:27 PM PDT 24
Peak memory 217552 kb
Host smart-72758179-96aa-40ee-b367-4a5c4a8d2209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220189223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1220189223
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.851338161
Short name T294
Test name
Test status
Simulation time 13774544450 ps
CPU time 74.13 seconds
Started Apr 23 02:39:35 PM PDT 24
Finished Apr 23 02:40:50 PM PDT 24
Peak memory 219724 kb
Host smart-c014dd46-f385-4b9a-9283-514380fa020b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851338161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.851338161
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2453149894
Short name T171
Test name
Test status
Simulation time 167813197 ps
CPU time 8.29 seconds
Started Apr 23 02:39:39 PM PDT 24
Finished Apr 23 02:39:48 PM PDT 24
Peak memory 211628 kb
Host smart-cac8b219-ae88-4d7e-82f9-6a144f2b2d8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453149894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2453149894
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1749132280
Short name T24
Test name
Test status
Simulation time 24888995002 ps
CPU time 380.07 seconds
Started Apr 23 02:39:37 PM PDT 24
Finished Apr 23 02:45:58 PM PDT 24
Peak memory 237160 kb
Host smart-a98110f0-5c80-486b-bfdf-913a177b6d4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749132280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1749132280
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2720687605
Short name T235
Test name
Test status
Simulation time 5867618497 ps
CPU time 29.98 seconds
Started Apr 23 02:39:38 PM PDT 24
Finished Apr 23 02:40:09 PM PDT 24
Peak memory 215528 kb
Host smart-cb343ed3-4be1-4ea2-96bd-a52a3c6e1b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720687605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2720687605
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1315108979
Short name T287
Test name
Test status
Simulation time 4928332946 ps
CPU time 28.23 seconds
Started Apr 23 02:39:44 PM PDT 24
Finished Apr 23 02:40:13 PM PDT 24
Peak memory 211772 kb
Host smart-77211a76-8bf7-45a9-a1ff-c015bc5cbcde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1315108979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1315108979
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2754634071
Short name T152
Test name
Test status
Simulation time 6344838399 ps
CPU time 60.18 seconds
Started Apr 23 02:39:43 PM PDT 24
Finished Apr 23 02:40:43 PM PDT 24
Peak memory 217952 kb
Host smart-c4a0ab2b-7d6d-4719-ab1e-c22981b3f221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754634071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2754634071
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2857945860
Short name T229
Test name
Test status
Simulation time 16139301350 ps
CPU time 168.28 seconds
Started Apr 23 02:39:44 PM PDT 24
Finished Apr 23 02:42:33 PM PDT 24
Peak memory 220736 kb
Host smart-c2effa6e-4ea5-4a80-8d8c-3d02cc438505
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857945860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2857945860
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2854470421
Short name T230
Test name
Test status
Simulation time 21672433532 ps
CPU time 19.34 seconds
Started Apr 23 02:39:47 PM PDT 24
Finished Apr 23 02:40:07 PM PDT 24
Peak memory 212604 kb
Host smart-31c6e6b6-6269-4223-b7e3-0bb1839805c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854470421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2854470421
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3183771307
Short name T253
Test name
Test status
Simulation time 165373076075 ps
CPU time 331.21 seconds
Started Apr 23 02:39:38 PM PDT 24
Finished Apr 23 02:45:10 PM PDT 24
Peak memory 236524 kb
Host smart-624bdda5-3b7a-4c08-98b6-53d76ffab705
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183771307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3183771307
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4143749519
Short name T299
Test name
Test status
Simulation time 11364200843 ps
CPU time 51.89 seconds
Started Apr 23 02:39:48 PM PDT 24
Finished Apr 23 02:40:40 PM PDT 24
Peak memory 214252 kb
Host smart-6dc38cad-0d26-487d-ab0f-76e41889b470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143749519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4143749519
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1003798373
Short name T276
Test name
Test status
Simulation time 1084129768 ps
CPU time 17.24 seconds
Started Apr 23 02:39:43 PM PDT 24
Finished Apr 23 02:40:01 PM PDT 24
Peak memory 212480 kb
Host smart-5e351a98-e9b3-47b6-a130-4f1053353a52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1003798373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1003798373
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2739833396
Short name T143
Test name
Test status
Simulation time 14053343748 ps
CPU time 58.18 seconds
Started Apr 23 02:39:39 PM PDT 24
Finished Apr 23 02:40:37 PM PDT 24
Peak memory 218316 kb
Host smart-be1c3587-f1ca-4cd6-8c90-bd60b0146a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739833396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2739833396
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.261279614
Short name T40
Test name
Test status
Simulation time 4625469984 ps
CPU time 52.33 seconds
Started Apr 23 02:39:37 PM PDT 24
Finished Apr 23 02:40:30 PM PDT 24
Peak memory 219724 kb
Host smart-32d4d10a-bda7-402e-bdbd-b8547b516342
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261279614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.261279614
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1684357169
Short name T234
Test name
Test status
Simulation time 16881111829 ps
CPU time 31.23 seconds
Started Apr 23 02:39:42 PM PDT 24
Finished Apr 23 02:40:14 PM PDT 24
Peak memory 212488 kb
Host smart-c723baf8-81ba-426d-ba43-3149a6ddc1a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684357169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1684357169
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1608758537
Short name T9
Test name
Test status
Simulation time 132925625607 ps
CPU time 294.03 seconds
Started Apr 23 02:39:45 PM PDT 24
Finished Apr 23 02:44:39 PM PDT 24
Peak memory 216908 kb
Host smart-57755c30-6ece-44d1-8391-4fca1661a3cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608758537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1608758537
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2674206294
Short name T186
Test name
Test status
Simulation time 4122620753 ps
CPU time 18.83 seconds
Started Apr 23 02:39:41 PM PDT 24
Finished Apr 23 02:40:01 PM PDT 24
Peak memory 215100 kb
Host smart-aa50c0f1-a27e-4036-8b79-23382c863391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674206294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2674206294
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1086768665
Short name T302
Test name
Test status
Simulation time 4159940896 ps
CPU time 15.08 seconds
Started Apr 23 02:39:42 PM PDT 24
Finished Apr 23 02:39:58 PM PDT 24
Peak memory 212840 kb
Host smart-3e5adf21-3b12-4d34-a668-1f9d3a7d9d1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1086768665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1086768665
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2564622290
Short name T262
Test name
Test status
Simulation time 5201022456 ps
CPU time 48.47 seconds
Started Apr 23 02:39:42 PM PDT 24
Finished Apr 23 02:40:31 PM PDT 24
Peak memory 216760 kb
Host smart-5cd166ce-9632-49eb-a95e-aff86277b700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564622290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2564622290
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1179788406
Short name T292
Test name
Test status
Simulation time 2196390045 ps
CPU time 23.91 seconds
Started Apr 23 02:39:48 PM PDT 24
Finished Apr 23 02:40:12 PM PDT 24
Peak memory 218188 kb
Host smart-6ca05dc9-53da-4fab-b5ce-89e053d14338
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179788406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1179788406
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.989319375
Short name T188
Test name
Test status
Simulation time 910941747 ps
CPU time 13.99 seconds
Started Apr 23 02:39:45 PM PDT 24
Finished Apr 23 02:39:59 PM PDT 24
Peak memory 211668 kb
Host smart-8c835698-6e7a-4161-a172-484e025c96e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989319375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.989319375
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.991801200
Short name T42
Test name
Test status
Simulation time 242059376778 ps
CPU time 641.76 seconds
Started Apr 23 02:39:46 PM PDT 24
Finished Apr 23 02:50:28 PM PDT 24
Peak memory 239272 kb
Host smart-fa83d876-9d6f-4309-b597-958509f470b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991801200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.991801200
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2607860308
Short name T284
Test name
Test status
Simulation time 11196295803 ps
CPU time 37.08 seconds
Started Apr 23 02:39:46 PM PDT 24
Finished Apr 23 02:40:24 PM PDT 24
Peak memory 215224 kb
Host smart-1be06131-9df1-47be-bce7-d36dda4e729c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607860308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2607860308
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.175390657
Short name T130
Test name
Test status
Simulation time 2026663567 ps
CPU time 20.58 seconds
Started Apr 23 02:39:41 PM PDT 24
Finished Apr 23 02:40:03 PM PDT 24
Peak memory 212532 kb
Host smart-10056ee6-bcb4-4b80-9f1a-2f0942815830
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=175390657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.175390657
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.4099765919
Short name T149
Test name
Test status
Simulation time 2123706327 ps
CPU time 22.8 seconds
Started Apr 23 02:39:50 PM PDT 24
Finished Apr 23 02:40:13 PM PDT 24
Peak memory 216948 kb
Host smart-529f100a-556d-4721-afb8-0aa0a16c3c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099765919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.4099765919
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3698944612
Short name T343
Test name
Test status
Simulation time 2225448462 ps
CPU time 74.3 seconds
Started Apr 23 02:39:45 PM PDT 24
Finished Apr 23 02:41:00 PM PDT 24
Peak memory 220184 kb
Host smart-b6e37cd7-4358-4bac-aae4-d0ae6d4f2675
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698944612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3698944612
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.824231877
Short name T44
Test name
Test status
Simulation time 54352018361 ps
CPU time 1580.74 seconds
Started Apr 23 02:39:45 PM PDT 24
Finished Apr 23 03:06:06 PM PDT 24
Peak memory 236072 kb
Host smart-24dc4d42-3945-4b45-986f-4961d6aad532
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824231877 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.824231877
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2276122479
Short name T57
Test name
Test status
Simulation time 663366893 ps
CPU time 10.68 seconds
Started Apr 23 02:39:48 PM PDT 24
Finished Apr 23 02:39:59 PM PDT 24
Peak memory 211668 kb
Host smart-683b9613-0e7f-4409-ae77-e096d6331ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276122479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2276122479
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2730233072
Short name T295
Test name
Test status
Simulation time 38057881953 ps
CPU time 510.99 seconds
Started Apr 23 02:39:47 PM PDT 24
Finished Apr 23 02:48:18 PM PDT 24
Peak memory 240264 kb
Host smart-7f74397c-cc88-4b98-a7dc-042ee7f95652
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730233072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2730233072
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3888678694
Short name T126
Test name
Test status
Simulation time 8964004239 ps
CPU time 67.36 seconds
Started Apr 23 02:39:46 PM PDT 24
Finished Apr 23 02:40:54 PM PDT 24
Peak memory 215836 kb
Host smart-34a6eb46-e78f-49b1-9cf1-1518231e1e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888678694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3888678694
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1907665261
Short name T332
Test name
Test status
Simulation time 374139051 ps
CPU time 10.02 seconds
Started Apr 23 02:39:48 PM PDT 24
Finished Apr 23 02:39:58 PM PDT 24
Peak memory 212364 kb
Host smart-bbcd4d05-84e3-49e8-81a8-323764d81a3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1907665261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1907665261
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3991658547
Short name T285
Test name
Test status
Simulation time 5598289893 ps
CPU time 19.41 seconds
Started Apr 23 02:39:44 PM PDT 24
Finished Apr 23 02:40:04 PM PDT 24
Peak memory 218460 kb
Host smart-75eba90f-cdf9-4302-8255-bbd8e3fbfa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991658547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3991658547
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3107395275
Short name T167
Test name
Test status
Simulation time 4635778551 ps
CPU time 56.66 seconds
Started Apr 23 02:39:46 PM PDT 24
Finished Apr 23 02:40:43 PM PDT 24
Peak memory 216996 kb
Host smart-27fcd422-afe6-4356-823b-e4f3418cba37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107395275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3107395275
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.379706005
Short name T45
Test name
Test status
Simulation time 261356529391 ps
CPU time 1002.76 seconds
Started Apr 23 02:39:47 PM PDT 24
Finished Apr 23 02:56:30 PM PDT 24
Peak memory 233824 kb
Host smart-6f32011d-058d-4ed9-bb57-307ab299da06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379706005 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.379706005
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.458997078
Short name T334
Test name
Test status
Simulation time 26357196164 ps
CPU time 25.08 seconds
Started Apr 23 02:39:17 PM PDT 24
Finished Apr 23 02:39:43 PM PDT 24
Peak memory 212476 kb
Host smart-b05e041a-139c-448d-88be-e8d7e783f82c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458997078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.458997078
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1458464057
Short name T289
Test name
Test status
Simulation time 23378083757 ps
CPU time 243.37 seconds
Started Apr 23 02:39:07 PM PDT 24
Finished Apr 23 02:43:11 PM PDT 24
Peak memory 240252 kb
Host smart-65664713-0625-40f8-8cc6-c7c97ab5119a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458464057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1458464057
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.240450441
Short name T329
Test name
Test status
Simulation time 8218633893 ps
CPU time 64.91 seconds
Started Apr 23 02:39:08 PM PDT 24
Finished Apr 23 02:40:14 PM PDT 24
Peak memory 215252 kb
Host smart-d22cad8c-1d8e-4777-922a-5cdbdd678bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240450441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.240450441
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3986250190
Short name T111
Test name
Test status
Simulation time 265301708 ps
CPU time 12.13 seconds
Started Apr 23 02:39:17 PM PDT 24
Finished Apr 23 02:39:30 PM PDT 24
Peak memory 212504 kb
Host smart-7256cda8-7e80-4f80-91ae-00766bdbdac3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3986250190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3986250190
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2632300013
Short name T37
Test name
Test status
Simulation time 4579435447 ps
CPU time 142.87 seconds
Started Apr 23 02:39:15 PM PDT 24
Finished Apr 23 02:41:39 PM PDT 24
Peak memory 239064 kb
Host smart-cd3be6c4-431d-4e0f-b4d0-b3c0e57cc86c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632300013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2632300013
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3931168021
Short name T69
Test name
Test status
Simulation time 16794029873 ps
CPU time 82.35 seconds
Started Apr 23 02:39:17 PM PDT 24
Finished Apr 23 02:40:40 PM PDT 24
Peak memory 218524 kb
Host smart-d71bc3b2-eefa-4226-8502-3c03b4940ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931168021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3931168021
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2052516390
Short name T182
Test name
Test status
Simulation time 43339073150 ps
CPU time 65.76 seconds
Started Apr 23 02:39:18 PM PDT 24
Finished Apr 23 02:40:25 PM PDT 24
Peak memory 217540 kb
Host smart-0274eae3-0b2c-4407-a5d8-df19c800d03f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052516390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2052516390
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3399613517
Short name T356
Test name
Test status
Simulation time 8195260436 ps
CPU time 31.15 seconds
Started Apr 23 02:39:48 PM PDT 24
Finished Apr 23 02:40:20 PM PDT 24
Peak memory 212584 kb
Host smart-0367b70e-f901-4681-adc8-6fe2b6aa5d11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399613517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3399613517
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1487214861
Short name T168
Test name
Test status
Simulation time 177345436410 ps
CPU time 909.76 seconds
Started Apr 23 02:39:48 PM PDT 24
Finished Apr 23 02:54:58 PM PDT 24
Peak memory 229608 kb
Host smart-1ca761f4-c085-4fc8-84a6-b47245f162b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487214861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1487214861
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2599156572
Short name T239
Test name
Test status
Simulation time 8231557167 ps
CPU time 25.53 seconds
Started Apr 23 02:39:49 PM PDT 24
Finished Apr 23 02:40:16 PM PDT 24
Peak memory 214392 kb
Host smart-61b9fa31-314a-413a-af5a-2ef144c89990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599156572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2599156572
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.607679746
Short name T216
Test name
Test status
Simulation time 12878628851 ps
CPU time 26.76 seconds
Started Apr 23 02:39:47 PM PDT 24
Finished Apr 23 02:40:14 PM PDT 24
Peak memory 212028 kb
Host smart-26321adc-506a-4e3d-bfb3-371da5e42d3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=607679746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.607679746
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1695401332
Short name T180
Test name
Test status
Simulation time 8725921648 ps
CPU time 70.76 seconds
Started Apr 23 02:39:47 PM PDT 24
Finished Apr 23 02:40:58 PM PDT 24
Peak memory 215720 kb
Host smart-1b6bc70e-480e-434d-9728-a350ec47f955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695401332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1695401332
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2917673456
Short name T198
Test name
Test status
Simulation time 17075997455 ps
CPU time 60.09 seconds
Started Apr 23 02:39:48 PM PDT 24
Finished Apr 23 02:40:48 PM PDT 24
Peak memory 216128 kb
Host smart-63740acd-8093-4d71-ade0-b93acf3b635c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917673456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2917673456
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3965402273
Short name T59
Test name
Test status
Simulation time 3609746975 ps
CPU time 30.32 seconds
Started Apr 23 02:39:57 PM PDT 24
Finished Apr 23 02:40:28 PM PDT 24
Peak memory 212288 kb
Host smart-9cbe0d84-2308-430a-82a4-6e227b511a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965402273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3965402273
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1700138239
Short name T314
Test name
Test status
Simulation time 108478271909 ps
CPU time 353.38 seconds
Started Apr 23 02:39:48 PM PDT 24
Finished Apr 23 02:45:42 PM PDT 24
Peak memory 238512 kb
Host smart-af8a25ea-00ee-4747-80a0-80761345e8be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700138239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1700138239
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1142321150
Short name T220
Test name
Test status
Simulation time 15391166334 ps
CPU time 62.04 seconds
Started Apr 23 02:39:50 PM PDT 24
Finished Apr 23 02:40:52 PM PDT 24
Peak memory 216852 kb
Host smart-64c769e6-24b5-4342-9656-e6b6c4f3719c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142321150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1142321150
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2097101045
Short name T272
Test name
Test status
Simulation time 40869049906 ps
CPU time 24.6 seconds
Started Apr 23 02:39:48 PM PDT 24
Finished Apr 23 02:40:13 PM PDT 24
Peak memory 213100 kb
Host smart-137bc5e5-05ae-4bac-8021-006212bbdf1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2097101045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2097101045
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2965194786
Short name T237
Test name
Test status
Simulation time 7539906847 ps
CPU time 58.15 seconds
Started Apr 23 02:39:46 PM PDT 24
Finished Apr 23 02:40:45 PM PDT 24
Peak memory 218112 kb
Host smart-a73eb313-258d-4761-b743-3e432b66e516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965194786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2965194786
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.711424726
Short name T250
Test name
Test status
Simulation time 2909590091 ps
CPU time 56.14 seconds
Started Apr 23 02:39:46 PM PDT 24
Finished Apr 23 02:40:42 PM PDT 24
Peak memory 218724 kb
Host smart-0becbb06-7c18-40e5-a433-51b5dca4a68a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711424726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.711424726
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.1762656654
Short name T17
Test name
Test status
Simulation time 80405803358 ps
CPU time 8911.62 seconds
Started Apr 23 02:39:52 PM PDT 24
Finished Apr 23 05:08:25 PM PDT 24
Peak memory 232432 kb
Host smart-85bfc6cc-647b-4ae4-a1ca-74fa9589e411
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762656654 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.1762656654
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.955010739
Short name T151
Test name
Test status
Simulation time 661059615 ps
CPU time 8.31 seconds
Started Apr 23 02:39:51 PM PDT 24
Finished Apr 23 02:40:00 PM PDT 24
Peak memory 211656 kb
Host smart-8e3714e6-2fcd-4f1c-ba7c-b694d89f8ec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955010739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.955010739
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1794330984
Short name T223
Test name
Test status
Simulation time 130426203735 ps
CPU time 704.4 seconds
Started Apr 23 02:39:51 PM PDT 24
Finished Apr 23 02:51:36 PM PDT 24
Peak memory 240388 kb
Host smart-4b819d99-a3a6-48b2-bbec-8fc2e1a0b9b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794330984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1794330984
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.478905587
Short name T155
Test name
Test status
Simulation time 7419617665 ps
CPU time 62.04 seconds
Started Apr 23 02:39:55 PM PDT 24
Finished Apr 23 02:40:57 PM PDT 24
Peak memory 215224 kb
Host smart-bb4e57b2-4eb4-4283-bac3-5366ac8bac49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478905587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.478905587
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1370408369
Short name T307
Test name
Test status
Simulation time 7844028939 ps
CPU time 31.77 seconds
Started Apr 23 02:39:52 PM PDT 24
Finished Apr 23 02:40:24 PM PDT 24
Peak memory 211592 kb
Host smart-330a13cc-582b-44fa-b8bf-1e3b2a0cf892
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1370408369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1370408369
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3049624186
Short name T150
Test name
Test status
Simulation time 5955909303 ps
CPU time 29.77 seconds
Started Apr 23 02:39:50 PM PDT 24
Finished Apr 23 02:40:20 PM PDT 24
Peak memory 218316 kb
Host smart-8f2df0b2-2d42-43e1-aaa8-f188d795958f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049624186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3049624186
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3425715012
Short name T279
Test name
Test status
Simulation time 358377031 ps
CPU time 23.21 seconds
Started Apr 23 02:39:51 PM PDT 24
Finished Apr 23 02:40:15 PM PDT 24
Peak memory 218220 kb
Host smart-ede4c5be-1e61-4377-bd64-a56b0c1e81f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425715012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3425715012
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2650238767
Short name T214
Test name
Test status
Simulation time 3776400398 ps
CPU time 14.95 seconds
Started Apr 23 02:39:53 PM PDT 24
Finished Apr 23 02:40:09 PM PDT 24
Peak memory 211712 kb
Host smart-a56b1df7-efa7-4c00-a200-126291c21c19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650238767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2650238767
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2665421717
Short name T121
Test name
Test status
Simulation time 3224731598 ps
CPU time 201.11 seconds
Started Apr 23 02:39:56 PM PDT 24
Finished Apr 23 02:43:18 PM PDT 24
Peak memory 219608 kb
Host smart-08da3683-c0e2-4c17-b087-2f2d2b730493
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665421717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2665421717
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4132472667
Short name T263
Test name
Test status
Simulation time 806928644 ps
CPU time 18.71 seconds
Started Apr 23 02:39:56 PM PDT 24
Finished Apr 23 02:40:15 PM PDT 24
Peak memory 214920 kb
Host smart-69d34b59-3f3b-4e29-89c2-0167060da85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132472667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.4132472667
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3222783619
Short name T138
Test name
Test status
Simulation time 4690563468 ps
CPU time 24.28 seconds
Started Apr 23 02:39:50 PM PDT 24
Finished Apr 23 02:40:14 PM PDT 24
Peak memory 211496 kb
Host smart-275a1d08-73d9-495f-a36b-a1a881ce8d7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3222783619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3222783619
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.583782607
Short name T191
Test name
Test status
Simulation time 55660019969 ps
CPU time 65.15 seconds
Started Apr 23 02:39:55 PM PDT 24
Finished Apr 23 02:41:00 PM PDT 24
Peak memory 218116 kb
Host smart-b875a1ef-e234-43bb-b850-fa7830162bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583782607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.583782607
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1027310217
Short name T179
Test name
Test status
Simulation time 70956734867 ps
CPU time 104.88 seconds
Started Apr 23 02:39:50 PM PDT 24
Finished Apr 23 02:41:35 PM PDT 24
Peak memory 221892 kb
Host smart-d2ab6e6d-362c-4c9d-b617-85d77bee193b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027310217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1027310217
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2137810909
Short name T200
Test name
Test status
Simulation time 10176320650 ps
CPU time 23.21 seconds
Started Apr 23 02:39:52 PM PDT 24
Finished Apr 23 02:40:15 PM PDT 24
Peak memory 212476 kb
Host smart-0081e552-0213-4b48-9903-fa021236b5c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137810909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2137810909
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1470605864
Short name T124
Test name
Test status
Simulation time 184272110882 ps
CPU time 717.87 seconds
Started Apr 23 02:39:58 PM PDT 24
Finished Apr 23 02:51:56 PM PDT 24
Peak memory 239696 kb
Host smart-b967d049-3a14-4883-a8a8-59fcc7f4562f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470605864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1470605864
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1207224386
Short name T25
Test name
Test status
Simulation time 15106225309 ps
CPU time 43.26 seconds
Started Apr 23 02:39:53 PM PDT 24
Finished Apr 23 02:40:37 PM PDT 24
Peak memory 215200 kb
Host smart-6e3f4c2a-f9ef-4f02-964c-24640edc7466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207224386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1207224386
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1128134027
Short name T313
Test name
Test status
Simulation time 3709797186 ps
CPU time 30.71 seconds
Started Apr 23 02:39:59 PM PDT 24
Finished Apr 23 02:40:31 PM PDT 24
Peak memory 212540 kb
Host smart-38f99edb-0407-4a81-bd74-3acc45c6b3ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1128134027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1128134027
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3621921944
Short name T115
Test name
Test status
Simulation time 9891992052 ps
CPU time 34.95 seconds
Started Apr 23 02:39:56 PM PDT 24
Finished Apr 23 02:40:32 PM PDT 24
Peak memory 218212 kb
Host smart-0b8c8650-30b2-47ba-ad03-92716e1a484e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621921944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3621921944
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2096536557
Short name T194
Test name
Test status
Simulation time 2695440991 ps
CPU time 44.54 seconds
Started Apr 23 02:39:57 PM PDT 24
Finished Apr 23 02:40:42 PM PDT 24
Peak memory 219728 kb
Host smart-d2d8613a-aa68-47a5-a2d3-674ba6f28044
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096536557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2096536557
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2565679700
Short name T7
Test name
Test status
Simulation time 8225172934 ps
CPU time 20.64 seconds
Started Apr 23 02:39:59 PM PDT 24
Finished Apr 23 02:40:20 PM PDT 24
Peak memory 212532 kb
Host smart-b96aac5a-7f16-45a1-80b7-a0da11bd20cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565679700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2565679700
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1565859984
Short name T273
Test name
Test status
Simulation time 3847832163 ps
CPU time 261.42 seconds
Started Apr 23 02:39:58 PM PDT 24
Finished Apr 23 02:44:20 PM PDT 24
Peak memory 225472 kb
Host smart-b71b312b-8a1e-4c99-b549-b4179fb37220
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565859984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1565859984
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.4073995037
Short name T358
Test name
Test status
Simulation time 32780490048 ps
CPU time 56.92 seconds
Started Apr 23 02:39:59 PM PDT 24
Finished Apr 23 02:40:56 PM PDT 24
Peak memory 215488 kb
Host smart-46550095-7c48-494e-8b90-3f13309954d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073995037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.4073995037
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4207076385
Short name T175
Test name
Test status
Simulation time 661482313 ps
CPU time 14.17 seconds
Started Apr 23 02:39:57 PM PDT 24
Finished Apr 23 02:40:12 PM PDT 24
Peak memory 212556 kb
Host smart-edb651bd-2990-4297-99dc-8bbbf5086561
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4207076385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4207076385
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3330361231
Short name T4
Test name
Test status
Simulation time 9744431981 ps
CPU time 57.95 seconds
Started Apr 23 02:40:01 PM PDT 24
Finished Apr 23 02:40:59 PM PDT 24
Peak memory 217936 kb
Host smart-57daa4dd-023f-4291-811d-58666eede645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330361231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3330361231
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1135398526
Short name T183
Test name
Test status
Simulation time 5444186231 ps
CPU time 27.01 seconds
Started Apr 23 02:39:55 PM PDT 24
Finished Apr 23 02:40:22 PM PDT 24
Peak memory 214224 kb
Host smart-ef9353c2-f9ec-4b27-94ec-a0a5c56269ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135398526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1135398526
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.653091035
Short name T147
Test name
Test status
Simulation time 46116600691 ps
CPU time 53.84 seconds
Started Apr 23 02:39:59 PM PDT 24
Finished Apr 23 02:40:54 PM PDT 24
Peak memory 214184 kb
Host smart-1d27e528-244e-4bce-bbf8-00f56289fc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653091035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.653091035
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3683999631
Short name T177
Test name
Test status
Simulation time 18460829366 ps
CPU time 34.74 seconds
Started Apr 23 02:39:57 PM PDT 24
Finished Apr 23 02:40:33 PM PDT 24
Peak memory 212108 kb
Host smart-14047aa6-819f-4a8b-811d-8f261a590562
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3683999631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3683999631
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2207768508
Short name T305
Test name
Test status
Simulation time 35532503446 ps
CPU time 80.41 seconds
Started Apr 23 02:40:03 PM PDT 24
Finished Apr 23 02:41:24 PM PDT 24
Peak memory 218216 kb
Host smart-69c7ad77-f860-4823-ae8c-70898097693b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207768508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2207768508
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2882742455
Short name T228
Test name
Test status
Simulation time 60528569962 ps
CPU time 100.26 seconds
Started Apr 23 02:39:59 PM PDT 24
Finished Apr 23 02:41:40 PM PDT 24
Peak memory 219716 kb
Host smart-ee4d8077-d4af-4ec4-a49a-bad7ea2d4600
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882742455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2882742455
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1504295224
Short name T286
Test name
Test status
Simulation time 338293060 ps
CPU time 8.19 seconds
Started Apr 23 02:40:02 PM PDT 24
Finished Apr 23 02:40:10 PM PDT 24
Peak memory 211696 kb
Host smart-1c27cdd2-96a1-460b-9bb1-5754688116d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504295224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1504295224
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.218432685
Short name T202
Test name
Test status
Simulation time 238961849291 ps
CPU time 473.91 seconds
Started Apr 23 02:40:01 PM PDT 24
Finished Apr 23 02:47:56 PM PDT 24
Peak memory 216908 kb
Host smart-ae9cfab4-1089-4a24-8d26-2cdfe2b37389
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218432685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.218432685
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1404010331
Short name T6
Test name
Test status
Simulation time 4109668104 ps
CPU time 43.55 seconds
Started Apr 23 02:39:58 PM PDT 24
Finished Apr 23 02:40:42 PM PDT 24
Peak memory 214940 kb
Host smart-ed3d71b5-0947-4dd8-85ba-f06e65ffc0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404010331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1404010331
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1267154450
Short name T349
Test name
Test status
Simulation time 5761166438 ps
CPU time 27.1 seconds
Started Apr 23 02:39:56 PM PDT 24
Finished Apr 23 02:40:24 PM PDT 24
Peak memory 211688 kb
Host smart-c3354138-6b4c-4a2a-bb8b-10ed933cc328
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1267154450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1267154450
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3807673515
Short name T118
Test name
Test status
Simulation time 8884819527 ps
CPU time 69.74 seconds
Started Apr 23 02:40:01 PM PDT 24
Finished Apr 23 02:41:11 PM PDT 24
Peak memory 215560 kb
Host smart-2cf668ca-363c-4f6d-b5ab-cdbd3a54c48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807673515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3807673515
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1019804870
Short name T238
Test name
Test status
Simulation time 36214424146 ps
CPU time 167.34 seconds
Started Apr 23 02:39:57 PM PDT 24
Finished Apr 23 02:42:45 PM PDT 24
Peak memory 228424 kb
Host smart-f215ef0f-d68d-43c3-91b2-b01bdf1c2dc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019804870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1019804870
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3550458819
Short name T257
Test name
Test status
Simulation time 172833338 ps
CPU time 8.24 seconds
Started Apr 23 02:40:02 PM PDT 24
Finished Apr 23 02:40:11 PM PDT 24
Peak memory 211656 kb
Host smart-ed96ae31-cb83-49f6-b6fa-ef17b55a2960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550458819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3550458819
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3156623266
Short name T215
Test name
Test status
Simulation time 241131451588 ps
CPU time 565.19 seconds
Started Apr 23 02:40:01 PM PDT 24
Finished Apr 23 02:49:27 PM PDT 24
Peak memory 238156 kb
Host smart-8e0620dd-6424-4ac8-ac9e-c16171eecdc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156623266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3156623266
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1104100772
Short name T217
Test name
Test status
Simulation time 675177881 ps
CPU time 19.02 seconds
Started Apr 23 02:40:01 PM PDT 24
Finished Apr 23 02:40:21 PM PDT 24
Peak memory 214872 kb
Host smart-ad166af0-2fc7-48c6-bc42-7524fcf4f3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104100772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1104100772
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2396281526
Short name T204
Test name
Test status
Simulation time 3227945414 ps
CPU time 27.77 seconds
Started Apr 23 02:40:00 PM PDT 24
Finished Apr 23 02:40:29 PM PDT 24
Peak memory 212432 kb
Host smart-2234ecee-2ff4-4ef5-bbfc-e4ddcd01a9a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2396281526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2396281526
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.4167664811
Short name T232
Test name
Test status
Simulation time 688245957 ps
CPU time 19.77 seconds
Started Apr 23 02:40:06 PM PDT 24
Finished Apr 23 02:40:27 PM PDT 24
Peak memory 216064 kb
Host smart-55b2744e-7ca7-4a91-80eb-773bb0a544cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167664811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.4167664811
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2629616539
Short name T274
Test name
Test status
Simulation time 31681501011 ps
CPU time 155.09 seconds
Started Apr 23 02:40:01 PM PDT 24
Finished Apr 23 02:42:37 PM PDT 24
Peak memory 221172 kb
Host smart-f19f7110-ecef-4a2d-9ccf-0ad788210cd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629616539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2629616539
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2252819370
Short name T251
Test name
Test status
Simulation time 2750149526 ps
CPU time 11.09 seconds
Started Apr 23 02:40:03 PM PDT 24
Finished Apr 23 02:40:15 PM PDT 24
Peak memory 212220 kb
Host smart-75fd2151-a8fb-4eb6-93ce-5217393b0087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252819370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2252819370
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1597004709
Short name T271
Test name
Test status
Simulation time 68459890310 ps
CPU time 733.45 seconds
Started Apr 23 02:40:03 PM PDT 24
Finished Apr 23 02:52:17 PM PDT 24
Peak memory 238172 kb
Host smart-ea670f90-0fa2-4f1a-8cf0-e860e71e3ed7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597004709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1597004709
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3590845097
Short name T176
Test name
Test status
Simulation time 689270436 ps
CPU time 18.98 seconds
Started Apr 23 02:40:02 PM PDT 24
Finished Apr 23 02:40:22 PM PDT 24
Peak memory 214884 kb
Host smart-41c2e58a-68f3-4ab0-9f57-681c3cf61743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590845097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3590845097
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1231844423
Short name T222
Test name
Test status
Simulation time 16714241095 ps
CPU time 32.45 seconds
Started Apr 23 02:40:05 PM PDT 24
Finished Apr 23 02:40:38 PM PDT 24
Peak memory 212956 kb
Host smart-8d5ca721-25c0-47c0-97e9-372c26884fb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1231844423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1231844423
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3794670332
Short name T350
Test name
Test status
Simulation time 3585903660 ps
CPU time 44.46 seconds
Started Apr 23 02:40:04 PM PDT 24
Finished Apr 23 02:40:49 PM PDT 24
Peak memory 217984 kb
Host smart-e1ad2062-4d99-42e0-ad87-23384481e9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794670332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3794670332
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1969540556
Short name T298
Test name
Test status
Simulation time 9375087132 ps
CPU time 102.9 seconds
Started Apr 23 02:40:03 PM PDT 24
Finished Apr 23 02:41:47 PM PDT 24
Peak memory 219752 kb
Host smart-06e30752-4a35-4dea-aaae-a52d2aad583a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969540556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1969540556
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2781919312
Short name T35
Test name
Test status
Simulation time 590661861 ps
CPU time 8.47 seconds
Started Apr 23 02:39:11 PM PDT 24
Finished Apr 23 02:39:20 PM PDT 24
Peak memory 211676 kb
Host smart-bca97a1a-0912-4dc0-8b95-488a71d73936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781919312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2781919312
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.746615566
Short name T266
Test name
Test status
Simulation time 13689504285 ps
CPU time 56.16 seconds
Started Apr 23 02:39:14 PM PDT 24
Finished Apr 23 02:40:16 PM PDT 24
Peak memory 215292 kb
Host smart-42a6bb61-816b-488d-b651-d5a063856dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746615566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.746615566
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1379487336
Short name T192
Test name
Test status
Simulation time 1552174065 ps
CPU time 15.14 seconds
Started Apr 23 02:39:09 PM PDT 24
Finished Apr 23 02:39:24 PM PDT 24
Peak memory 212840 kb
Host smart-246f5eea-dcbf-4206-9e20-8faa851799d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1379487336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1379487336
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.543066520
Short name T33
Test name
Test status
Simulation time 15219586575 ps
CPU time 140.75 seconds
Started Apr 23 02:39:10 PM PDT 24
Finished Apr 23 02:41:32 PM PDT 24
Peak memory 239104 kb
Host smart-c0d7c75f-c858-4bd7-8be7-0f6341f928c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543066520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.543066520
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2628956195
Short name T346
Test name
Test status
Simulation time 16479186848 ps
CPU time 66.46 seconds
Started Apr 23 02:39:10 PM PDT 24
Finished Apr 23 02:40:17 PM PDT 24
Peak memory 218048 kb
Host smart-48d443d5-15c4-4d6d-9129-58582cafc0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628956195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2628956195
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.722864527
Short name T264
Test name
Test status
Simulation time 35986160763 ps
CPU time 170.26 seconds
Started Apr 23 02:39:08 PM PDT 24
Finished Apr 23 02:41:59 PM PDT 24
Peak memory 227904 kb
Host smart-7361313c-92e8-470b-a619-8e84aeaaeae8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722864527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.722864527
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1067879125
Short name T55
Test name
Test status
Simulation time 751820102 ps
CPU time 8.67 seconds
Started Apr 23 02:40:09 PM PDT 24
Finished Apr 23 02:40:18 PM PDT 24
Peak memory 211580 kb
Host smart-b182f886-b840-4e03-a7b9-9a13b7c73c0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067879125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1067879125
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.294641377
Short name T252
Test name
Test status
Simulation time 248741914566 ps
CPU time 1216.4 seconds
Started Apr 23 02:40:04 PM PDT 24
Finished Apr 23 03:00:21 PM PDT 24
Peak memory 239152 kb
Host smart-84cedc8d-c12a-4469-afcd-df12826e43c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294641377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.294641377
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.324626810
Short name T335
Test name
Test status
Simulation time 7100167651 ps
CPU time 59.82 seconds
Started Apr 23 02:40:06 PM PDT 24
Finished Apr 23 02:41:06 PM PDT 24
Peak memory 215452 kb
Host smart-0a15c463-8834-40e9-96b8-b883e169b24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324626810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.324626810
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1123437702
Short name T240
Test name
Test status
Simulation time 10530370684 ps
CPU time 24.72 seconds
Started Apr 23 02:40:05 PM PDT 24
Finished Apr 23 02:40:30 PM PDT 24
Peak memory 211684 kb
Host smart-fdb1efa8-963a-4ce0-bfc3-3fc89df26bf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1123437702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1123437702
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3330232181
Short name T68
Test name
Test status
Simulation time 349186646 ps
CPU time 20.3 seconds
Started Apr 23 02:40:06 PM PDT 24
Finished Apr 23 02:40:27 PM PDT 24
Peak memory 218172 kb
Host smart-cfd19b53-45a9-40f4-ae8c-8ea395386e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330232181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3330232181
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2481467348
Short name T125
Test name
Test status
Simulation time 3705026180 ps
CPU time 60.39 seconds
Started Apr 23 02:40:04 PM PDT 24
Finished Apr 23 02:41:04 PM PDT 24
Peak memory 216948 kb
Host smart-c4353952-cbe4-400f-b33a-0e0ab968ad15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481467348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2481467348
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3746128107
Short name T156
Test name
Test status
Simulation time 2301044111 ps
CPU time 17.98 seconds
Started Apr 23 02:40:05 PM PDT 24
Finished Apr 23 02:40:24 PM PDT 24
Peak memory 211716 kb
Host smart-73e015f1-73ba-4299-a96e-8488990c93fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746128107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3746128107
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1059012789
Short name T128
Test name
Test status
Simulation time 666334723 ps
CPU time 23.85 seconds
Started Apr 23 02:40:05 PM PDT 24
Finished Apr 23 02:40:29 PM PDT 24
Peak memory 214812 kb
Host smart-bdd4c611-9ba2-4591-bf3f-823fcb263a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059012789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1059012789
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1714033156
Short name T231
Test name
Test status
Simulation time 3170518625 ps
CPU time 27.49 seconds
Started Apr 23 02:40:04 PM PDT 24
Finished Apr 23 02:40:32 PM PDT 24
Peak memory 212408 kb
Host smart-2f270475-c77d-4fbf-8413-31aa2a5268d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1714033156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1714033156
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2766554437
Short name T342
Test name
Test status
Simulation time 1632095869 ps
CPU time 32.31 seconds
Started Apr 23 02:40:07 PM PDT 24
Finished Apr 23 02:40:40 PM PDT 24
Peak memory 217524 kb
Host smart-893d736c-862d-470b-b778-5a69bd1088e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766554437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2766554437
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2602296980
Short name T309
Test name
Test status
Simulation time 15869770958 ps
CPU time 64.73 seconds
Started Apr 23 02:40:09 PM PDT 24
Finished Apr 23 02:41:14 PM PDT 24
Peak memory 216080 kb
Host smart-974d617a-8d39-409d-8584-9d16408b2b51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602296980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2602296980
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2652149952
Short name T185
Test name
Test status
Simulation time 172513768 ps
CPU time 8.54 seconds
Started Apr 23 02:40:11 PM PDT 24
Finished Apr 23 02:40:21 PM PDT 24
Peak memory 211604 kb
Host smart-8fa72bec-7ded-453b-aeb9-43516de6bb0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652149952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2652149952
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3059592032
Short name T190
Test name
Test status
Simulation time 12760284929 ps
CPU time 260.54 seconds
Started Apr 23 02:40:07 PM PDT 24
Finished Apr 23 02:44:29 PM PDT 24
Peak memory 217492 kb
Host smart-a11e102b-9f0c-4798-b4f9-c6c351ede995
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059592032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3059592032
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1559128636
Short name T355
Test name
Test status
Simulation time 17697638598 ps
CPU time 31.77 seconds
Started Apr 23 02:40:09 PM PDT 24
Finished Apr 23 02:40:41 PM PDT 24
Peak memory 212004 kb
Host smart-5db77bc4-bec1-4afb-8cd1-a36060270a98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559128636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1559128636
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3023673233
Short name T224
Test name
Test status
Simulation time 6642362716 ps
CPU time 30.57 seconds
Started Apr 23 02:40:08 PM PDT 24
Finished Apr 23 02:40:39 PM PDT 24
Peak memory 218240 kb
Host smart-46755416-4d00-4933-9b74-42de5adef238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023673233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3023673233
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2887845936
Short name T348
Test name
Test status
Simulation time 34682552954 ps
CPU time 87.09 seconds
Started Apr 23 02:40:04 PM PDT 24
Finished Apr 23 02:41:32 PM PDT 24
Peak memory 219756 kb
Host smart-d923bce2-09d3-49a3-ad36-167dd8aabe59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887845936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2887845936
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2727891009
Short name T233
Test name
Test status
Simulation time 687605167 ps
CPU time 12.94 seconds
Started Apr 23 02:40:11 PM PDT 24
Finished Apr 23 02:40:25 PM PDT 24
Peak memory 211640 kb
Host smart-20ee05cc-6247-4ef6-be06-adb04bb64c87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727891009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2727891009
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2080361773
Short name T31
Test name
Test status
Simulation time 8151628396 ps
CPU time 163.59 seconds
Started Apr 23 02:40:09 PM PDT 24
Finished Apr 23 02:42:54 PM PDT 24
Peak memory 234536 kb
Host smart-b815d871-40c5-4b18-8fa4-f928d0ffe442
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080361773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2080361773
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2445367966
Short name T116
Test name
Test status
Simulation time 675346315 ps
CPU time 19.15 seconds
Started Apr 23 02:40:09 PM PDT 24
Finished Apr 23 02:40:29 PM PDT 24
Peak memory 214904 kb
Host smart-2d25a6b9-e7c3-4636-917f-d83ebb381f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445367966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2445367966
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2687882046
Short name T199
Test name
Test status
Simulation time 183455582 ps
CPU time 10.09 seconds
Started Apr 23 02:40:07 PM PDT 24
Finished Apr 23 02:40:18 PM PDT 24
Peak memory 212504 kb
Host smart-a2665430-c6b6-4715-9475-b997b9cfdd37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2687882046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2687882046
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.278221701
Short name T114
Test name
Test status
Simulation time 347062809 ps
CPU time 19.52 seconds
Started Apr 23 02:40:09 PM PDT 24
Finished Apr 23 02:40:29 PM PDT 24
Peak memory 216428 kb
Host smart-aca5e113-132a-4ec6-93d6-b75580a7de92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278221701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.278221701
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2477608826
Short name T187
Test name
Test status
Simulation time 31039087624 ps
CPU time 66.54 seconds
Started Apr 23 02:40:09 PM PDT 24
Finished Apr 23 02:41:16 PM PDT 24
Peak memory 216528 kb
Host smart-6ae0c4b9-2199-4e3b-a55b-3ca82bfd2943
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477608826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2477608826
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2368069972
Short name T247
Test name
Test status
Simulation time 5023089995 ps
CPU time 13.66 seconds
Started Apr 23 02:40:14 PM PDT 24
Finished Apr 23 02:40:29 PM PDT 24
Peak memory 211556 kb
Host smart-6436d185-161b-477b-bb4d-68b6828a2f7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368069972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2368069972
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.583775612
Short name T351
Test name
Test status
Simulation time 102702227823 ps
CPU time 386.67 seconds
Started Apr 23 02:40:13 PM PDT 24
Finished Apr 23 02:46:40 PM PDT 24
Peak memory 240984 kb
Host smart-41ff1407-fecd-48c6-9e26-820b1236b70e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583775612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.583775612
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1600159097
Short name T277
Test name
Test status
Simulation time 117116331424 ps
CPU time 70.13 seconds
Started Apr 23 02:40:10 PM PDT 24
Finished Apr 23 02:41:21 PM PDT 24
Peak memory 214220 kb
Host smart-f862a64f-cf23-4273-93cf-c50a3cb7f773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600159097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1600159097
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1117549372
Short name T296
Test name
Test status
Simulation time 1171804249 ps
CPU time 14.81 seconds
Started Apr 23 02:40:11 PM PDT 24
Finished Apr 23 02:40:26 PM PDT 24
Peak memory 211500 kb
Host smart-32181a50-f268-4173-a302-ccc5aa9e6dba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1117549372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1117549372
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2290081591
Short name T122
Test name
Test status
Simulation time 33374472162 ps
CPU time 67.21 seconds
Started Apr 23 02:40:07 PM PDT 24
Finished Apr 23 02:41:15 PM PDT 24
Peak memory 218332 kb
Host smart-4a5df16d-40e7-4f84-8d90-16f775e68674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290081591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2290081591
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.95521999
Short name T162
Test name
Test status
Simulation time 46310927858 ps
CPU time 125.74 seconds
Started Apr 23 02:40:08 PM PDT 24
Finished Apr 23 02:42:14 PM PDT 24
Peak memory 216504 kb
Host smart-f720fadf-696e-44c8-af29-e37303337a90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95521999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 44.rom_ctrl_stress_all.95521999
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2276045125
Short name T225
Test name
Test status
Simulation time 2137330191 ps
CPU time 21.09 seconds
Started Apr 23 02:40:14 PM PDT 24
Finished Apr 23 02:40:35 PM PDT 24
Peak memory 211672 kb
Host smart-8a64e6fa-e353-45f3-af89-1d6c748e107e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276045125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2276045125
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1208902023
Short name T261
Test name
Test status
Simulation time 13677381907 ps
CPU time 58.49 seconds
Started Apr 23 02:40:12 PM PDT 24
Finished Apr 23 02:41:11 PM PDT 24
Peak memory 214168 kb
Host smart-dc9cb9bc-a0bd-4b57-a3cb-607cecba08c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208902023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1208902023
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4237394985
Short name T288
Test name
Test status
Simulation time 345154878 ps
CPU time 12.3 seconds
Started Apr 23 02:40:14 PM PDT 24
Finished Apr 23 02:40:28 PM PDT 24
Peak memory 211424 kb
Host smart-94806b56-61ee-476f-9b12-146b25d0cbcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4237394985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4237394985
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2689957880
Short name T218
Test name
Test status
Simulation time 32086295766 ps
CPU time 65.57 seconds
Started Apr 23 02:40:13 PM PDT 24
Finished Apr 23 02:41:20 PM PDT 24
Peak memory 217816 kb
Host smart-00c9a089-3371-442d-97c9-16ca489464c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689957880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2689957880
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3704164779
Short name T39
Test name
Test status
Simulation time 43196033945 ps
CPU time 97.17 seconds
Started Apr 23 02:40:13 PM PDT 24
Finished Apr 23 02:41:51 PM PDT 24
Peak memory 219804 kb
Host smart-08e234f8-6d50-4ebb-bb1c-7d07a560193e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704164779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3704164779
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3717740227
Short name T206
Test name
Test status
Simulation time 7468849027 ps
CPU time 19.53 seconds
Started Apr 23 02:40:20 PM PDT 24
Finished Apr 23 02:40:40 PM PDT 24
Peak memory 212616 kb
Host smart-97d79fae-14a5-4a8b-be2e-f029158305ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717740227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3717740227
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.108042046
Short name T136
Test name
Test status
Simulation time 19823954517 ps
CPU time 330.19 seconds
Started Apr 23 02:40:14 PM PDT 24
Finished Apr 23 02:45:45 PM PDT 24
Peak memory 225984 kb
Host smart-a72d003e-d11a-4bf1-9778-1182ea381c4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108042046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.108042046
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2409215023
Short name T244
Test name
Test status
Simulation time 5383650719 ps
CPU time 37.15 seconds
Started Apr 23 02:40:14 PM PDT 24
Finished Apr 23 02:40:52 PM PDT 24
Peak memory 215312 kb
Host smart-2d15bdcb-3430-400d-a852-c8eba6c338f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409215023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2409215023
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3543780899
Short name T291
Test name
Test status
Simulation time 15161342193 ps
CPU time 30.7 seconds
Started Apr 23 02:40:14 PM PDT 24
Finished Apr 23 02:40:45 PM PDT 24
Peak memory 211956 kb
Host smart-e228fdca-d6dc-4036-8574-28978247303c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3543780899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3543780899
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.196140948
Short name T258
Test name
Test status
Simulation time 33404478747 ps
CPU time 79.94 seconds
Started Apr 23 02:40:14 PM PDT 24
Finished Apr 23 02:41:35 PM PDT 24
Peak memory 218240 kb
Host smart-053247c2-10aa-4360-b92e-a8f1e3f204d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196140948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.196140948
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.781380764
Short name T304
Test name
Test status
Simulation time 10598453095 ps
CPU time 50 seconds
Started Apr 23 02:40:12 PM PDT 24
Finished Apr 23 02:41:03 PM PDT 24
Peak memory 219292 kb
Host smart-fb07e669-8b91-4cec-9801-bf415fd577b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781380764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.781380764
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3667119609
Short name T58
Test name
Test status
Simulation time 2302936958 ps
CPU time 15.69 seconds
Started Apr 23 02:40:16 PM PDT 24
Finished Apr 23 02:40:32 PM PDT 24
Peak memory 211724 kb
Host smart-110780f7-f642-4a71-9b2f-90bf4a06079a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667119609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3667119609
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3449846732
Short name T324
Test name
Test status
Simulation time 68373427934 ps
CPU time 788.64 seconds
Started Apr 23 02:40:15 PM PDT 24
Finished Apr 23 02:53:24 PM PDT 24
Peak memory 238180 kb
Host smart-809531a8-6e3a-422d-9938-9b56c6014434
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449846732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3449846732
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.883284423
Short name T10
Test name
Test status
Simulation time 17197710610 ps
CPU time 42.75 seconds
Started Apr 23 02:40:19 PM PDT 24
Finished Apr 23 02:41:02 PM PDT 24
Peak memory 215208 kb
Host smart-66ff1660-cfc6-46e3-9456-c041893c2dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883284423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.883284423
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1611831287
Short name T15
Test name
Test status
Simulation time 687903560 ps
CPU time 9.96 seconds
Started Apr 23 02:40:14 PM PDT 24
Finished Apr 23 02:40:25 PM PDT 24
Peak memory 211716 kb
Host smart-c0e0c761-b185-448c-8ea7-4f92f2965f26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1611831287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1611831287
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3354542235
Short name T308
Test name
Test status
Simulation time 34264292637 ps
CPU time 67.33 seconds
Started Apr 23 02:40:14 PM PDT 24
Finished Apr 23 02:41:23 PM PDT 24
Peak memory 215588 kb
Host smart-d61481eb-46b4-4d47-8aca-ac5b542e8434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354542235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3354542235
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2334485817
Short name T96
Test name
Test status
Simulation time 70742054281 ps
CPU time 97 seconds
Started Apr 23 02:40:18 PM PDT 24
Finished Apr 23 02:41:55 PM PDT 24
Peak memory 220348 kb
Host smart-455af4d0-351a-457c-8e1b-01e91bbc3595
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334485817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2334485817
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3167236933
Short name T170
Test name
Test status
Simulation time 751605565 ps
CPU time 8.07 seconds
Started Apr 23 02:40:18 PM PDT 24
Finished Apr 23 02:40:26 PM PDT 24
Peak memory 211624 kb
Host smart-a87f405c-5f10-4e1e-8652-8eb97137621b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167236933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3167236933
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.200756490
Short name T353
Test name
Test status
Simulation time 11070072495 ps
CPU time 150.42 seconds
Started Apr 23 02:40:14 PM PDT 24
Finished Apr 23 02:42:45 PM PDT 24
Peak memory 236920 kb
Host smart-0fc3e393-a6ac-45cf-bfdc-f06c4d658fde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200756490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.200756490
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1175946844
Short name T310
Test name
Test status
Simulation time 4001053538 ps
CPU time 42.85 seconds
Started Apr 23 02:40:17 PM PDT 24
Finished Apr 23 02:41:00 PM PDT 24
Peak memory 214984 kb
Host smart-f28c17a6-c928-4729-a9d8-d4578f67a85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175946844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1175946844
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3172016401
Short name T221
Test name
Test status
Simulation time 187596239 ps
CPU time 10.66 seconds
Started Apr 23 02:40:16 PM PDT 24
Finished Apr 23 02:40:27 PM PDT 24
Peak memory 212568 kb
Host smart-e7010790-7443-4554-9f6d-564c30e898d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3172016401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3172016401
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.230934961
Short name T120
Test name
Test status
Simulation time 59821631092 ps
CPU time 88.16 seconds
Started Apr 23 02:40:15 PM PDT 24
Finished Apr 23 02:41:44 PM PDT 24
Peak memory 217872 kb
Host smart-4b24ac25-3027-4a88-84b8-52346e11b551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230934961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.230934961
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1300324454
Short name T311
Test name
Test status
Simulation time 3875156186 ps
CPU time 51.61 seconds
Started Apr 23 02:40:15 PM PDT 24
Finished Apr 23 02:41:07 PM PDT 24
Peak memory 219776 kb
Host smart-d453c49e-7dd4-467b-8bc0-60499de53a88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300324454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1300324454
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2626873323
Short name T154
Test name
Test status
Simulation time 24550705858 ps
CPU time 20.94 seconds
Started Apr 23 02:40:17 PM PDT 24
Finished Apr 23 02:40:39 PM PDT 24
Peak memory 212532 kb
Host smart-b3ee37bd-d692-400f-9ba1-5dbab868837a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626873323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2626873323
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3109727191
Short name T117
Test name
Test status
Simulation time 17896531647 ps
CPU time 300.75 seconds
Started Apr 23 02:40:21 PM PDT 24
Finished Apr 23 02:45:22 PM PDT 24
Peak memory 238136 kb
Host smart-6bdff28e-0c33-416a-93d3-936f644fbc13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109727191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3109727191
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.892021345
Short name T8
Test name
Test status
Simulation time 12448856693 ps
CPU time 54.66 seconds
Started Apr 23 02:40:18 PM PDT 24
Finished Apr 23 02:41:13 PM PDT 24
Peak memory 215188 kb
Host smart-e310b407-f6d5-40b1-b1a9-ba913c6fd4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892021345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.892021345
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3327512841
Short name T327
Test name
Test status
Simulation time 19500038133 ps
CPU time 31.78 seconds
Started Apr 23 02:40:17 PM PDT 24
Finished Apr 23 02:40:50 PM PDT 24
Peak memory 211972 kb
Host smart-f0d4b804-15b3-462a-b387-65fbcb49dfb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3327512841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3327512841
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1991727031
Short name T153
Test name
Test status
Simulation time 363522623 ps
CPU time 19.43 seconds
Started Apr 23 02:40:17 PM PDT 24
Finished Apr 23 02:40:37 PM PDT 24
Peak memory 216508 kb
Host smart-d32023cb-6709-492b-a496-8a7809568e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991727031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1991727031
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1108218094
Short name T249
Test name
Test status
Simulation time 31669043162 ps
CPU time 94.64 seconds
Started Apr 23 02:40:20 PM PDT 24
Finished Apr 23 02:41:55 PM PDT 24
Peak memory 221352 kb
Host smart-0213b96e-d6f7-46d5-ae97-179295b10a67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108218094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1108218094
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1702652406
Short name T174
Test name
Test status
Simulation time 14214075238 ps
CPU time 28.51 seconds
Started Apr 23 02:39:17 PM PDT 24
Finished Apr 23 02:39:46 PM PDT 24
Peak memory 212548 kb
Host smart-48b04ae9-bdaa-4ae1-94d0-1d89691b73b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702652406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1702652406
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3925763681
Short name T30
Test name
Test status
Simulation time 22864315224 ps
CPU time 205.11 seconds
Started Apr 23 02:39:14 PM PDT 24
Finished Apr 23 02:42:40 PM PDT 24
Peak memory 241152 kb
Host smart-9e5c893d-1f6e-4a75-a982-96736e99f9b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925763681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3925763681
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4239440847
Short name T357
Test name
Test status
Simulation time 87115463643 ps
CPU time 66.82 seconds
Started Apr 23 02:39:19 PM PDT 24
Finished Apr 23 02:40:26 PM PDT 24
Peak memory 214312 kb
Host smart-53978aed-344b-4635-b84d-eae88d6121db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239440847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.4239440847
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.689582696
Short name T243
Test name
Test status
Simulation time 8974007072 ps
CPU time 35.02 seconds
Started Apr 23 02:39:11 PM PDT 24
Finished Apr 23 02:39:47 PM PDT 24
Peak memory 211512 kb
Host smart-d2964d86-0550-40c6-a7aa-588a0f28781e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=689582696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.689582696
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1159334902
Short name T71
Test name
Test status
Simulation time 19813063879 ps
CPU time 55.33 seconds
Started Apr 23 02:39:17 PM PDT 24
Finished Apr 23 02:40:13 PM PDT 24
Peak memory 217988 kb
Host smart-bed05b1b-3473-44d1-bd43-11f7e4f3ec1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159334902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1159334902
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3183507036
Short name T181
Test name
Test status
Simulation time 1329292898 ps
CPU time 16.68 seconds
Started Apr 23 02:39:13 PM PDT 24
Finished Apr 23 02:39:30 PM PDT 24
Peak memory 212096 kb
Host smart-78ba7bc5-a816-4048-b3ea-7f4684f9f5e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183507036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3183507036
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2396604629
Short name T26
Test name
Test status
Simulation time 108389797392 ps
CPU time 563.54 seconds
Started Apr 23 02:39:12 PM PDT 24
Finished Apr 23 02:48:36 PM PDT 24
Peak memory 228292 kb
Host smart-81d612be-43f2-45a2-adb5-cc0434d95036
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396604629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2396604629
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.920085435
Short name T226
Test name
Test status
Simulation time 6423935560 ps
CPU time 56.83 seconds
Started Apr 23 02:39:18 PM PDT 24
Finished Apr 23 02:40:16 PM PDT 24
Peak memory 215284 kb
Host smart-93acf596-1869-491d-94d6-e3f1e802b1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920085435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.920085435
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2553341603
Short name T268
Test name
Test status
Simulation time 8837974776 ps
CPU time 24.71 seconds
Started Apr 23 02:39:12 PM PDT 24
Finished Apr 23 02:39:37 PM PDT 24
Peak memory 213056 kb
Host smart-0201669a-02bc-4ca5-9dec-e4a13541ce79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2553341603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2553341603
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.982801482
Short name T95
Test name
Test status
Simulation time 7538425926 ps
CPU time 62.73 seconds
Started Apr 23 02:39:12 PM PDT 24
Finished Apr 23 02:40:16 PM PDT 24
Peak memory 217356 kb
Host smart-193dd8e1-bdcf-4d0e-a825-cb29016bc11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982801482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.982801482
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1589832188
Short name T245
Test name
Test status
Simulation time 24355670578 ps
CPU time 65.11 seconds
Started Apr 23 02:39:12 PM PDT 24
Finished Apr 23 02:40:18 PM PDT 24
Peak memory 216080 kb
Host smart-aa43da5b-b283-41cb-87d5-09735dc5d4ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589832188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1589832188
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2468238363
Short name T326
Test name
Test status
Simulation time 9149800848 ps
CPU time 22.09 seconds
Started Apr 23 02:39:17 PM PDT 24
Finished Apr 23 02:39:40 PM PDT 24
Peak memory 212484 kb
Host smart-0512d85d-ff39-4f73-96f0-91e53c54a930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468238363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2468238363
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2174506830
Short name T331
Test name
Test status
Simulation time 258336664564 ps
CPU time 627.99 seconds
Started Apr 23 02:39:24 PM PDT 24
Finished Apr 23 02:49:52 PM PDT 24
Peak memory 229196 kb
Host smart-2088b520-b080-4239-bddb-830ad3963adf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174506830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2174506830
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1557841941
Short name T158
Test name
Test status
Simulation time 2534386515 ps
CPU time 18.88 seconds
Started Apr 23 02:39:12 PM PDT 24
Finished Apr 23 02:39:32 PM PDT 24
Peak memory 214880 kb
Host smart-7c45604c-ef18-48d1-842b-76285f46a5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557841941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1557841941
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2050111241
Short name T13
Test name
Test status
Simulation time 3332283014 ps
CPU time 28.16 seconds
Started Apr 23 02:39:12 PM PDT 24
Finished Apr 23 02:39:41 PM PDT 24
Peak memory 211556 kb
Host smart-1a8a85c2-6afa-489f-87fc-6e56fc54dc8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2050111241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2050111241
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.437677586
Short name T320
Test name
Test status
Simulation time 7263930733 ps
CPU time 40.68 seconds
Started Apr 23 02:39:16 PM PDT 24
Finished Apr 23 02:39:58 PM PDT 24
Peak memory 219044 kb
Host smart-9031daeb-3bf3-456c-9ff5-7ff06c9ad949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437677586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.437677586
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2950318979
Short name T119
Test name
Test status
Simulation time 3326893104 ps
CPU time 30.62 seconds
Started Apr 23 02:39:13 PM PDT 24
Finished Apr 23 02:39:45 PM PDT 24
Peak memory 219636 kb
Host smart-75caa571-1887-490c-a85c-2e66308b84df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950318979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2950318979
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.979078168
Short name T325
Test name
Test status
Simulation time 9332019261 ps
CPU time 20.19 seconds
Started Apr 23 02:39:16 PM PDT 24
Finished Apr 23 02:39:37 PM PDT 24
Peak memory 211656 kb
Host smart-1ee6e086-7d67-4cd8-b96e-dffd22095a82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979078168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.979078168
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2992033619
Short name T260
Test name
Test status
Simulation time 13979351910 ps
CPU time 296.53 seconds
Started Apr 23 02:39:18 PM PDT 24
Finished Apr 23 02:44:15 PM PDT 24
Peak memory 229860 kb
Host smart-3dbb7bdf-8bad-41bb-8dc9-cf7f7fe1f23c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992033619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2992033619
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1400749965
Short name T133
Test name
Test status
Simulation time 6424898682 ps
CPU time 29.7 seconds
Started Apr 23 02:39:26 PM PDT 24
Finished Apr 23 02:39:56 PM PDT 24
Peak memory 215568 kb
Host smart-eac16d16-e684-4725-a713-18d4bfba4072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400749965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1400749965
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2292667236
Short name T219
Test name
Test status
Simulation time 15714394726 ps
CPU time 33.92 seconds
Started Apr 23 02:39:17 PM PDT 24
Finished Apr 23 02:39:52 PM PDT 24
Peak memory 211992 kb
Host smart-637dbdb1-2944-479e-85bb-5bccd3984b8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2292667236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2292667236
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.4008265152
Short name T201
Test name
Test status
Simulation time 4677577565 ps
CPU time 52.3 seconds
Started Apr 23 02:39:18 PM PDT 24
Finished Apr 23 02:40:11 PM PDT 24
Peak memory 217376 kb
Host smart-557d4530-36ff-4f8f-936b-2c2c8d5b3f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008265152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4008265152
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.716138257
Short name T209
Test name
Test status
Simulation time 2348056781 ps
CPU time 54.25 seconds
Started Apr 23 02:39:17 PM PDT 24
Finished Apr 23 02:40:12 PM PDT 24
Peak memory 219680 kb
Host smart-f07ae05f-55a9-4bab-bf48-fac62f860bfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716138257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.716138257
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3442820214
Short name T347
Test name
Test status
Simulation time 517370296 ps
CPU time 8.19 seconds
Started Apr 23 02:39:22 PM PDT 24
Finished Apr 23 02:39:31 PM PDT 24
Peak memory 211604 kb
Host smart-8f385b7e-7992-434a-9c9e-3bd0519a3799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442820214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3442820214
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.110756214
Short name T193
Test name
Test status
Simulation time 4127193738 ps
CPU time 272.8 seconds
Started Apr 23 02:39:29 PM PDT 24
Finished Apr 23 02:44:03 PM PDT 24
Peak memory 218012 kb
Host smart-31aad67a-8bb3-4580-b43b-423d612d8531
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110756214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.110756214
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.914479224
Short name T189
Test name
Test status
Simulation time 1319931073 ps
CPU time 19.17 seconds
Started Apr 23 02:39:15 PM PDT 24
Finished Apr 23 02:39:35 PM PDT 24
Peak memory 214836 kb
Host smart-06f8b9a1-3b24-4182-8cf4-853d090fb582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914479224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.914479224
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1308152457
Short name T248
Test name
Test status
Simulation time 690831141 ps
CPU time 10.43 seconds
Started Apr 23 02:39:16 PM PDT 24
Finished Apr 23 02:39:28 PM PDT 24
Peak memory 211664 kb
Host smart-6e9d06aa-2d0c-473a-a12f-96ff860b3c64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1308152457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1308152457
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2727224505
Short name T210
Test name
Test status
Simulation time 5713788523 ps
CPU time 62.97 seconds
Started Apr 23 02:39:16 PM PDT 24
Finished Apr 23 02:40:20 PM PDT 24
Peak memory 215500 kb
Host smart-e9428f32-1be6-4bc3-bf30-33a1cee3e16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727224505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2727224505
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2376397817
Short name T344
Test name
Test status
Simulation time 2947745299 ps
CPU time 34.4 seconds
Started Apr 23 02:39:16 PM PDT 24
Finished Apr 23 02:39:51 PM PDT 24
Peak memory 213168 kb
Host smart-a7186970-bc9c-44c6-aee7-0029f2076073
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376397817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2376397817
Directory /workspace/9.rom_ctrl_stress_all/latest
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