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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.59 96.97 93.15 97.88 100.00 98.69 98.03 98.37


Total test records in report: 458
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T303 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.573863001 Apr 25 12:41:48 PM PDT 24 Apr 25 12:42:24 PM PDT 24 4182108113 ps
T304 /workspace/coverage/default/22.rom_ctrl_smoke.2993229533 Apr 25 12:41:53 PM PDT 24 Apr 25 12:42:44 PM PDT 24 18974172642 ps
T305 /workspace/coverage/default/49.rom_ctrl_stress_all.1371556590 Apr 25 12:42:12 PM PDT 24 Apr 25 12:44:03 PM PDT 24 7856352958 ps
T306 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4076181638 Apr 25 12:41:37 PM PDT 24 Apr 25 12:49:31 PM PDT 24 46417125730 ps
T307 /workspace/coverage/default/22.rom_ctrl_stress_all.229519987 Apr 25 12:41:39 PM PDT 24 Apr 25 12:43:48 PM PDT 24 14434802226 ps
T308 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2666753490 Apr 25 12:41:51 PM PDT 24 Apr 25 12:45:04 PM PDT 24 7267612548 ps
T309 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.300980796 Apr 25 12:41:26 PM PDT 24 Apr 25 12:56:42 PM PDT 24 393876549289 ps
T310 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.219154812 Apr 25 12:41:05 PM PDT 24 Apr 25 12:41:41 PM PDT 24 5115923096 ps
T311 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3017471896 Apr 25 12:41:20 PM PDT 24 Apr 25 12:47:15 PM PDT 24 58220672573 ps
T312 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1068747441 Apr 25 12:41:42 PM PDT 24 Apr 25 12:58:39 PM PDT 24 706038207854 ps
T37 /workspace/coverage/default/4.rom_ctrl_sec_cm.2263329569 Apr 25 12:41:06 PM PDT 24 Apr 25 12:43:06 PM PDT 24 374327516 ps
T313 /workspace/coverage/default/20.rom_ctrl_smoke.654990054 Apr 25 12:41:48 PM PDT 24 Apr 25 12:43:05 PM PDT 24 16380037619 ps
T314 /workspace/coverage/default/23.rom_ctrl_smoke.390956421 Apr 25 12:41:43 PM PDT 24 Apr 25 12:42:27 PM PDT 24 7718772428 ps
T315 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1336626822 Apr 25 12:41:58 PM PDT 24 Apr 25 12:42:14 PM PDT 24 1193585740 ps
T55 /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1580775855 Apr 25 12:41:43 PM PDT 24 Apr 25 01:28:54 PM PDT 24 448265171700 ps
T16 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1201325202 Apr 25 12:41:49 PM PDT 24 Apr 25 01:09:33 PM PDT 24 49096603966 ps
T316 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1991916485 Apr 25 12:41:04 PM PDT 24 Apr 25 12:41:32 PM PDT 24 12466218673 ps
T317 /workspace/coverage/default/46.rom_ctrl_smoke.840017980 Apr 25 12:41:50 PM PDT 24 Apr 25 12:43:06 PM PDT 24 7816646498 ps
T318 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2634991694 Apr 25 12:41:47 PM PDT 24 Apr 25 12:42:11 PM PDT 24 7016760488 ps
T319 /workspace/coverage/default/1.rom_ctrl_stress_all.2320709174 Apr 25 12:41:18 PM PDT 24 Apr 25 12:42:34 PM PDT 24 27560932224 ps
T320 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3088800538 Apr 25 12:41:27 PM PDT 24 Apr 25 12:48:59 PM PDT 24 597061974150 ps
T321 /workspace/coverage/default/0.rom_ctrl_smoke.3407879045 Apr 25 12:41:08 PM PDT 24 Apr 25 12:41:57 PM PDT 24 15121726856 ps
T322 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1186041089 Apr 25 12:41:49 PM PDT 24 Apr 25 12:47:34 PM PDT 24 151001954893 ps
T323 /workspace/coverage/default/42.rom_ctrl_alert_test.4038482785 Apr 25 12:41:47 PM PDT 24 Apr 25 12:42:04 PM PDT 24 1026306020 ps
T324 /workspace/coverage/default/28.rom_ctrl_stress_all.1092690024 Apr 25 12:41:49 PM PDT 24 Apr 25 12:43:57 PM PDT 24 5456789646 ps
T325 /workspace/coverage/default/47.rom_ctrl_alert_test.300047121 Apr 25 12:41:58 PM PDT 24 Apr 25 12:42:26 PM PDT 24 3387815328 ps
T326 /workspace/coverage/default/23.rom_ctrl_stress_all.2230494794 Apr 25 12:41:43 PM PDT 24 Apr 25 12:42:29 PM PDT 24 734079312 ps
T327 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1250526669 Apr 25 12:41:21 PM PDT 24 Apr 25 12:41:51 PM PDT 24 3376886507 ps
T328 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.340906857 Apr 25 12:41:38 PM PDT 24 Apr 25 12:48:33 PM PDT 24 73912001420 ps
T329 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.578328926 Apr 25 12:41:39 PM PDT 24 Apr 25 12:41:52 PM PDT 24 596048173 ps
T330 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.328603158 Apr 25 12:41:44 PM PDT 24 Apr 25 12:53:14 PM PDT 24 68406941857 ps
T331 /workspace/coverage/default/14.rom_ctrl_stress_all.3333148889 Apr 25 12:41:39 PM PDT 24 Apr 25 12:42:42 PM PDT 24 6856314268 ps
T332 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.4197280218 Apr 25 12:41:35 PM PDT 24 Apr 25 12:51:36 PM PDT 24 257546745900 ps
T333 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1311260681 Apr 25 12:41:56 PM PDT 24 Apr 25 12:42:31 PM PDT 24 15188475843 ps
T334 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2093543021 Apr 25 12:41:23 PM PDT 24 Apr 25 12:46:00 PM PDT 24 7733068187 ps
T335 /workspace/coverage/default/44.rom_ctrl_stress_all.2560370740 Apr 25 12:41:50 PM PDT 24 Apr 25 12:43:47 PM PDT 24 13701231645 ps
T336 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2049243398 Apr 25 12:41:55 PM PDT 24 Apr 25 12:42:16 PM PDT 24 675923582 ps
T337 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3260511169 Apr 25 12:42:01 PM PDT 24 Apr 25 12:59:28 PM PDT 24 512223581192 ps
T338 /workspace/coverage/default/8.rom_ctrl_smoke.3049172848 Apr 25 12:41:19 PM PDT 24 Apr 25 12:42:25 PM PDT 24 6570852050 ps
T339 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.167144836 Apr 25 12:42:01 PM PDT 24 Apr 25 12:49:36 PM PDT 24 35112613264 ps
T340 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1580654017 Apr 25 12:41:56 PM PDT 24 Apr 25 12:42:29 PM PDT 24 6663123144 ps
T341 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1714670829 Apr 25 12:41:49 PM PDT 24 Apr 25 12:50:12 PM PDT 24 38655972533 ps
T342 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1840782217 Apr 25 12:41:50 PM PDT 24 Apr 25 12:47:28 PM PDT 24 59479805697 ps
T343 /workspace/coverage/default/26.rom_ctrl_stress_all.1369729877 Apr 25 12:41:33 PM PDT 24 Apr 25 12:43:07 PM PDT 24 8032053298 ps
T344 /workspace/coverage/default/34.rom_ctrl_alert_test.516952822 Apr 25 12:41:46 PM PDT 24 Apr 25 12:42:18 PM PDT 24 7533959327 ps
T345 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2519209838 Apr 25 12:41:10 PM PDT 24 Apr 25 12:46:34 PM PDT 24 58293849153 ps
T56 /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1543720262 Apr 25 12:41:47 PM PDT 24 Apr 25 01:22:02 PM PDT 24 128906959896 ps
T346 /workspace/coverage/default/28.rom_ctrl_alert_test.1250918710 Apr 25 12:41:45 PM PDT 24 Apr 25 12:41:55 PM PDT 24 1269671526 ps
T347 /workspace/coverage/default/28.rom_ctrl_smoke.3672480282 Apr 25 12:41:49 PM PDT 24 Apr 25 12:42:10 PM PDT 24 344336058 ps
T38 /workspace/coverage/default/3.rom_ctrl_sec_cm.3343489289 Apr 25 12:41:10 PM PDT 24 Apr 25 12:43:10 PM PDT 24 423754260 ps
T348 /workspace/coverage/default/5.rom_ctrl_alert_test.2889010379 Apr 25 12:41:07 PM PDT 24 Apr 25 12:41:40 PM PDT 24 4008554755 ps
T349 /workspace/coverage/default/14.rom_ctrl_alert_test.352683433 Apr 25 12:41:40 PM PDT 24 Apr 25 12:42:08 PM PDT 24 11411139132 ps
T350 /workspace/coverage/default/43.rom_ctrl_alert_test.1262375605 Apr 25 12:41:56 PM PDT 24 Apr 25 12:42:25 PM PDT 24 34841933222 ps
T17 /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2999041355 Apr 25 12:41:53 PM PDT 24 Apr 25 03:24:21 PM PDT 24 124011866818 ps
T351 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1059639675 Apr 25 12:41:16 PM PDT 24 Apr 25 12:41:41 PM PDT 24 2393428398 ps
T352 /workspace/coverage/default/1.rom_ctrl_alert_test.685575932 Apr 25 12:40:53 PM PDT 24 Apr 25 12:41:26 PM PDT 24 8349632898 ps
T353 /workspace/coverage/default/45.rom_ctrl_smoke.1581961849 Apr 25 12:41:49 PM PDT 24 Apr 25 12:42:16 PM PDT 24 2506309903 ps
T354 /workspace/coverage/default/15.rom_ctrl_smoke.949363595 Apr 25 12:41:31 PM PDT 24 Apr 25 12:42:32 PM PDT 24 11953064748 ps
T355 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2955753485 Apr 25 12:41:11 PM PDT 24 Apr 25 12:47:15 PM PDT 24 35537192358 ps
T356 /workspace/coverage/default/46.rom_ctrl_stress_all.1029585438 Apr 25 12:41:55 PM PDT 24 Apr 25 12:45:06 PM PDT 24 30960962257 ps
T357 /workspace/coverage/default/7.rom_ctrl_smoke.2648536837 Apr 25 12:41:23 PM PDT 24 Apr 25 12:41:44 PM PDT 24 1909566054 ps
T358 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.993544687 Apr 25 12:41:20 PM PDT 24 Apr 25 12:49:29 PM PDT 24 130278972249 ps
T359 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2331547425 Apr 25 12:42:02 PM PDT 24 Apr 25 12:42:47 PM PDT 24 8734431842 ps
T360 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3796874187 Apr 25 12:37:27 PM PDT 24 Apr 25 12:37:41 PM PDT 24 577643920 ps
T65 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3480399842 Apr 25 12:37:33 PM PDT 24 Apr 25 12:37:54 PM PDT 24 2033237410 ps
T361 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1339592380 Apr 25 12:37:27 PM PDT 24 Apr 25 12:38:02 PM PDT 24 17689807911 ps
T362 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2016793897 Apr 25 12:37:40 PM PDT 24 Apr 25 12:38:13 PM PDT 24 18370045515 ps
T62 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3364841648 Apr 25 12:37:50 PM PDT 24 Apr 25 12:40:45 PM PDT 24 8702834685 ps
T66 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2870059261 Apr 25 12:37:52 PM PDT 24 Apr 25 12:38:19 PM PDT 24 2985848775 ps
T363 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.853217754 Apr 25 12:37:44 PM PDT 24 Apr 25 12:38:18 PM PDT 24 7726843795 ps
T71 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4169170618 Apr 25 12:37:51 PM PDT 24 Apr 25 12:38:09 PM PDT 24 9546366988 ps
T364 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.167839834 Apr 25 12:37:52 PM PDT 24 Apr 25 12:38:18 PM PDT 24 13431985711 ps
T72 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.640108885 Apr 25 12:37:55 PM PDT 24 Apr 25 12:38:20 PM PDT 24 2548480531 ps
T73 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3833829764 Apr 25 12:37:41 PM PDT 24 Apr 25 12:38:15 PM PDT 24 12452548011 ps
T365 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.410517599 Apr 25 12:37:32 PM PDT 24 Apr 25 12:37:54 PM PDT 24 8456832881 ps
T366 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1075558664 Apr 25 12:37:27 PM PDT 24 Apr 25 12:38:01 PM PDT 24 3377081360 ps
T367 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4232262080 Apr 25 12:37:45 PM PDT 24 Apr 25 12:38:02 PM PDT 24 911169401 ps
T368 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2891059815 Apr 25 12:37:53 PM PDT 24 Apr 25 12:38:22 PM PDT 24 9891117459 ps
T101 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2164408550 Apr 25 12:38:07 PM PDT 24 Apr 25 12:38:34 PM PDT 24 7038321942 ps
T63 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1818799884 Apr 25 12:37:53 PM PDT 24 Apr 25 12:39:37 PM PDT 24 14789732315 ps
T369 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3021753411 Apr 25 12:37:32 PM PDT 24 Apr 25 12:38:05 PM PDT 24 11016850586 ps
T64 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1568612126 Apr 25 12:37:51 PM PDT 24 Apr 25 12:39:21 PM PDT 24 10144199312 ps
T74 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.74036652 Apr 25 12:37:24 PM PDT 24 Apr 25 12:39:44 PM PDT 24 13980240141 ps
T370 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.881414868 Apr 25 12:37:44 PM PDT 24 Apr 25 12:38:00 PM PDT 24 1017817507 ps
T371 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.13859448 Apr 25 12:38:11 PM PDT 24 Apr 25 12:38:43 PM PDT 24 24152004242 ps
T75 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.878280375 Apr 25 12:38:08 PM PDT 24 Apr 25 12:38:34 PM PDT 24 10301428059 ps
T109 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3909480662 Apr 25 12:37:56 PM PDT 24 Apr 25 12:39:33 PM PDT 24 3947629978 ps
T105 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3030740320 Apr 25 12:37:53 PM PDT 24 Apr 25 12:39:52 PM PDT 24 13765101963 ps
T106 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4132276061 Apr 25 12:37:45 PM PDT 24 Apr 25 12:37:56 PM PDT 24 170712878 ps
T102 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2014555703 Apr 25 12:37:57 PM PDT 24 Apr 25 12:38:15 PM PDT 24 1200454859 ps
T76 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.960678290 Apr 25 12:37:26 PM PDT 24 Apr 25 12:37:46 PM PDT 24 1445782034 ps
T112 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1474092544 Apr 25 12:37:38 PM PDT 24 Apr 25 12:39:13 PM PDT 24 7134695413 ps
T372 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3541037273 Apr 25 12:37:51 PM PDT 24 Apr 25 12:38:11 PM PDT 24 1815156829 ps
T373 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1005867996 Apr 25 12:37:51 PM PDT 24 Apr 25 12:38:10 PM PDT 24 585998878 ps
T374 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1299755882 Apr 25 12:38:03 PM PDT 24 Apr 25 12:38:30 PM PDT 24 3510861142 ps
T77 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2575634141 Apr 25 12:37:44 PM PDT 24 Apr 25 12:38:13 PM PDT 24 12278220355 ps
T78 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3200410189 Apr 25 12:37:52 PM PDT 24 Apr 25 12:38:04 PM PDT 24 259007241 ps
T79 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2110476599 Apr 25 12:37:44 PM PDT 24 Apr 25 12:38:05 PM PDT 24 3392528184 ps
T375 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.83164328 Apr 25 12:37:53 PM PDT 24 Apr 25 12:38:10 PM PDT 24 3434317281 ps
T376 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.949806995 Apr 25 12:37:36 PM PDT 24 Apr 25 12:39:44 PM PDT 24 15638822965 ps
T377 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3374478601 Apr 25 12:37:33 PM PDT 24 Apr 25 12:38:02 PM PDT 24 10896178345 ps
T80 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3719758840 Apr 25 12:37:54 PM PDT 24 Apr 25 12:40:05 PM PDT 24 12274164167 ps
T378 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.244049305 Apr 25 12:37:53 PM PDT 24 Apr 25 12:38:24 PM PDT 24 14907550053 ps
T379 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1563522405 Apr 25 12:37:45 PM PDT 24 Apr 25 12:38:14 PM PDT 24 12417933715 ps
T380 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.248714767 Apr 25 12:37:38 PM PDT 24 Apr 25 12:37:47 PM PDT 24 751252790 ps
T103 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2837026824 Apr 25 12:37:40 PM PDT 24 Apr 25 12:38:17 PM PDT 24 7892839084 ps
T83 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1455129258 Apr 25 12:37:42 PM PDT 24 Apr 25 12:37:56 PM PDT 24 336852150 ps
T381 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3259275071 Apr 25 12:37:53 PM PDT 24 Apr 25 12:38:18 PM PDT 24 21619086882 ps
T382 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2540824669 Apr 25 12:37:44 PM PDT 24 Apr 25 12:38:02 PM PDT 24 1128917710 ps
T84 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3457499351 Apr 25 12:37:44 PM PDT 24 Apr 25 12:38:25 PM PDT 24 695701714 ps
T383 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.522772090 Apr 25 12:37:48 PM PDT 24 Apr 25 12:39:53 PM PDT 24 45382486835 ps
T384 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.301028608 Apr 25 12:37:28 PM PDT 24 Apr 25 12:37:48 PM PDT 24 1485027095 ps
T114 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3829409421 Apr 25 12:37:27 PM PDT 24 Apr 25 12:40:20 PM PDT 24 16185378010 ps
T385 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4068043038 Apr 25 12:37:42 PM PDT 24 Apr 25 12:38:00 PM PDT 24 4753113169 ps
T386 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2191211575 Apr 25 12:37:48 PM PDT 24 Apr 25 12:38:14 PM PDT 24 9983283655 ps
T387 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4245114850 Apr 25 12:37:33 PM PDT 24 Apr 25 12:37:50 PM PDT 24 4425403755 ps
T388 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1889503071 Apr 25 12:37:54 PM PDT 24 Apr 25 12:38:07 PM PDT 24 214150299 ps
T104 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3134295892 Apr 25 12:38:01 PM PDT 24 Apr 25 12:38:35 PM PDT 24 18376022151 ps
T389 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3222776699 Apr 25 12:37:43 PM PDT 24 Apr 25 12:38:17 PM PDT 24 15624128226 ps
T390 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2202945648 Apr 25 12:38:06 PM PDT 24 Apr 25 12:38:20 PM PDT 24 169233028 ps
T85 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1014096476 Apr 25 12:37:44 PM PDT 24 Apr 25 12:40:54 PM PDT 24 23230552012 ps
T86 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4025347373 Apr 25 12:37:49 PM PDT 24 Apr 25 12:39:24 PM PDT 24 5514386023 ps
T391 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.501162586 Apr 25 12:37:48 PM PDT 24 Apr 25 12:38:00 PM PDT 24 367089748 ps
T392 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2851124964 Apr 25 12:37:35 PM PDT 24 Apr 25 12:37:57 PM PDT 24 2139553680 ps
T393 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.592356631 Apr 25 12:37:59 PM PDT 24 Apr 25 12:38:30 PM PDT 24 3340911745 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.916150954 Apr 25 12:37:25 PM PDT 24 Apr 25 12:37:52 PM PDT 24 10229629122 ps
T395 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1054465440 Apr 25 12:37:49 PM PDT 24 Apr 25 12:38:16 PM PDT 24 52189366871 ps
T396 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.181078463 Apr 25 12:37:39 PM PDT 24 Apr 25 12:37:49 PM PDT 24 2355252905 ps
T87 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2199881863 Apr 25 12:37:54 PM PDT 24 Apr 25 12:39:56 PM PDT 24 54348196022 ps
T110 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3942388304 Apr 25 12:38:03 PM PDT 24 Apr 25 12:40:40 PM PDT 24 1244498186 ps
T397 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1962664454 Apr 25 12:37:25 PM PDT 24 Apr 25 12:37:48 PM PDT 24 4204571254 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3838789840 Apr 25 12:37:42 PM PDT 24 Apr 25 12:37:59 PM PDT 24 859812431 ps
T399 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2318023400 Apr 25 12:37:51 PM PDT 24 Apr 25 12:40:30 PM PDT 24 16277260203 ps
T400 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4216113140 Apr 25 12:37:31 PM PDT 24 Apr 25 12:37:48 PM PDT 24 1221284355 ps
T401 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1534117012 Apr 25 12:37:49 PM PDT 24 Apr 25 12:38:02 PM PDT 24 274718291 ps
T111 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4091446702 Apr 25 12:37:40 PM PDT 24 Apr 25 12:40:33 PM PDT 24 7020294232 ps
T88 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2188385847 Apr 25 12:37:41 PM PDT 24 Apr 25 12:39:13 PM PDT 24 8219205201 ps
T402 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1613920499 Apr 25 12:37:43 PM PDT 24 Apr 25 12:38:18 PM PDT 24 5878705610 ps
T403 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2943052890 Apr 25 12:37:41 PM PDT 24 Apr 25 12:39:24 PM PDT 24 38560717291 ps
T404 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.512545194 Apr 25 12:37:43 PM PDT 24 Apr 25 12:38:18 PM PDT 24 4126313028 ps
T89 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.939201842 Apr 25 12:37:48 PM PDT 24 Apr 25 12:38:29 PM PDT 24 725280058 ps
T90 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4282494339 Apr 25 12:37:39 PM PDT 24 Apr 25 12:40:16 PM PDT 24 32545405089 ps
T405 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3000030502 Apr 25 12:37:51 PM PDT 24 Apr 25 12:38:02 PM PDT 24 735711400 ps
T406 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.251586964 Apr 25 12:37:45 PM PDT 24 Apr 25 12:38:12 PM PDT 24 2618025318 ps
T117 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2005386159 Apr 25 12:37:42 PM PDT 24 Apr 25 12:40:16 PM PDT 24 2418255490 ps
T407 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1697196071 Apr 25 12:37:51 PM PDT 24 Apr 25 12:39:18 PM PDT 24 3021098751 ps
T408 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1341897902 Apr 25 12:37:53 PM PDT 24 Apr 25 12:38:06 PM PDT 24 689552279 ps
T118 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1060814180 Apr 25 12:37:55 PM PDT 24 Apr 25 12:39:19 PM PDT 24 6120430488 ps
T409 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1419582902 Apr 25 12:37:32 PM PDT 24 Apr 25 12:39:36 PM PDT 24 15254869216 ps
T410 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.693275331 Apr 25 12:37:54 PM PDT 24 Apr 25 12:40:08 PM PDT 24 17480516074 ps
T411 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.452863409 Apr 25 12:37:46 PM PDT 24 Apr 25 12:38:18 PM PDT 24 3553395932 ps
T412 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2789003754 Apr 25 12:37:49 PM PDT 24 Apr 25 12:39:22 PM PDT 24 2444828313 ps
T413 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2714106606 Apr 25 12:37:52 PM PDT 24 Apr 25 12:39:34 PM PDT 24 13475258030 ps
T414 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4139521094 Apr 25 12:37:46 PM PDT 24 Apr 25 12:37:58 PM PDT 24 345934812 ps
T415 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3190079376 Apr 25 12:37:33 PM PDT 24 Apr 25 12:37:57 PM PDT 24 3852554013 ps
T91 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3652176751 Apr 25 12:37:52 PM PDT 24 Apr 25 12:39:38 PM PDT 24 28509005922 ps
T113 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1801513227 Apr 25 12:37:49 PM PDT 24 Apr 25 12:40:39 PM PDT 24 3373985945 ps
T94 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3151464885 Apr 25 12:37:26 PM PDT 24 Apr 25 12:37:44 PM PDT 24 180309915 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1477153733 Apr 25 12:37:41 PM PDT 24 Apr 25 12:38:04 PM PDT 24 4277113908 ps
T417 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1079976173 Apr 25 12:37:34 PM PDT 24 Apr 25 12:37:44 PM PDT 24 661607636 ps
T96 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2015917336 Apr 25 12:38:05 PM PDT 24 Apr 25 12:38:31 PM PDT 24 5497553834 ps
T418 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2584530166 Apr 25 12:37:36 PM PDT 24 Apr 25 12:38:11 PM PDT 24 13294906179 ps
T419 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4286689735 Apr 25 12:37:35 PM PDT 24 Apr 25 12:39:01 PM PDT 24 1863199626 ps
T420 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1000436266 Apr 25 12:37:30 PM PDT 24 Apr 25 12:37:40 PM PDT 24 167578523 ps
T421 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3706572318 Apr 25 12:37:53 PM PDT 24 Apr 25 12:38:23 PM PDT 24 2145401036 ps
T422 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2794027358 Apr 25 12:37:55 PM PDT 24 Apr 25 12:38:30 PM PDT 24 12121077039 ps
T423 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.731383832 Apr 25 12:37:38 PM PDT 24 Apr 25 12:38:07 PM PDT 24 7497540689 ps
T424 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2009289093 Apr 25 12:37:45 PM PDT 24 Apr 25 12:38:07 PM PDT 24 2083081295 ps
T425 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.268485544 Apr 25 12:37:36 PM PDT 24 Apr 25 12:37:46 PM PDT 24 167643972 ps
T95 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2745363441 Apr 25 12:37:29 PM PDT 24 Apr 25 12:37:58 PM PDT 24 6267481720 ps
T426 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2336140520 Apr 25 12:37:43 PM PDT 24 Apr 25 12:38:07 PM PDT 24 2053856664 ps
T427 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.260461226 Apr 25 12:37:51 PM PDT 24 Apr 25 12:38:18 PM PDT 24 12268682618 ps
T428 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.908066328 Apr 25 12:37:37 PM PDT 24 Apr 25 12:38:06 PM PDT 24 12128039608 ps
T429 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1797038880 Apr 25 12:37:43 PM PDT 24 Apr 25 12:39:18 PM PDT 24 3987457316 ps
T430 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3846622274 Apr 25 12:37:52 PM PDT 24 Apr 25 12:38:07 PM PDT 24 1341613248 ps
T431 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1295027975 Apr 25 12:37:57 PM PDT 24 Apr 25 12:38:23 PM PDT 24 2465126750 ps
T432 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.826746970 Apr 25 12:37:46 PM PDT 24 Apr 25 12:39:28 PM PDT 24 19110106794 ps
T92 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2073601778 Apr 25 12:37:42 PM PDT 24 Apr 25 12:39:51 PM PDT 24 45452074965 ps
T433 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.926833734 Apr 25 12:37:51 PM PDT 24 Apr 25 12:38:05 PM PDT 24 4083818089 ps
T434 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.326718964 Apr 25 12:37:46 PM PDT 24 Apr 25 12:38:12 PM PDT 24 3143955462 ps
T435 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.785259596 Apr 25 12:37:47 PM PDT 24 Apr 25 12:37:59 PM PDT 24 184259786 ps
T436 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2748882483 Apr 25 12:37:17 PM PDT 24 Apr 25 12:37:44 PM PDT 24 2537007276 ps
T437 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.958148756 Apr 25 12:37:51 PM PDT 24 Apr 25 12:38:06 PM PDT 24 507772483 ps
T438 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1728443887 Apr 25 12:37:44 PM PDT 24 Apr 25 12:39:34 PM PDT 24 140029803408 ps
T439 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2021651176 Apr 25 12:37:59 PM PDT 24 Apr 25 12:40:34 PM PDT 24 1115343666 ps
T440 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.125633961 Apr 25 12:37:40 PM PDT 24 Apr 25 12:38:11 PM PDT 24 2712282677 ps
T441 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1696874643 Apr 25 12:37:51 PM PDT 24 Apr 25 12:38:14 PM PDT 24 1476989906 ps
T442 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2589944517 Apr 25 12:37:26 PM PDT 24 Apr 25 12:37:42 PM PDT 24 661171100 ps
T93 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1751960452 Apr 25 12:37:48 PM PDT 24 Apr 25 12:38:18 PM PDT 24 12533550388 ps
T443 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3138646995 Apr 25 12:37:33 PM PDT 24 Apr 25 12:37:53 PM PDT 24 6961337710 ps
T444 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3318764429 Apr 25 12:37:36 PM PDT 24 Apr 25 12:37:58 PM PDT 24 2041290810 ps
T115 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.834298069 Apr 25 12:37:45 PM PDT 24 Apr 25 12:40:25 PM PDT 24 659103995 ps
T445 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3643769583 Apr 25 12:37:45 PM PDT 24 Apr 25 12:37:58 PM PDT 24 305994154 ps
T446 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.465871130 Apr 25 12:37:56 PM PDT 24 Apr 25 12:38:15 PM PDT 24 5442560645 ps
T447 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3838375341 Apr 25 12:37:42 PM PDT 24 Apr 25 12:38:01 PM PDT 24 4455443040 ps
T448 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3697205748 Apr 25 12:37:56 PM PDT 24 Apr 25 12:38:10 PM PDT 24 1454787425 ps
T449 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2935321896 Apr 25 12:37:30 PM PDT 24 Apr 25 12:37:40 PM PDT 24 171051859 ps
T450 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1527957942 Apr 25 12:37:28 PM PDT 24 Apr 25 12:37:39 PM PDT 24 1498395899 ps
T451 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2328430391 Apr 25 12:37:55 PM PDT 24 Apr 25 12:38:32 PM PDT 24 4122465752 ps
T452 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1904001276 Apr 25 12:37:46 PM PDT 24 Apr 25 12:38:00 PM PDT 24 409726337 ps
T119 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3426931282 Apr 25 12:37:26 PM PDT 24 Apr 25 12:40:06 PM PDT 24 6908422466 ps
T453 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3424562068 Apr 25 12:37:43 PM PDT 24 Apr 25 12:38:03 PM PDT 24 10470925119 ps
T454 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3169156092 Apr 25 12:37:51 PM PDT 24 Apr 25 12:38:27 PM PDT 24 18271249216 ps
T455 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1644570366 Apr 25 12:37:25 PM PDT 24 Apr 25 12:37:49 PM PDT 24 14537846649 ps
T456 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2207757524 Apr 25 12:37:27 PM PDT 24 Apr 25 12:37:42 PM PDT 24 176354540 ps
T457 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3648337748 Apr 25 12:37:51 PM PDT 24 Apr 25 12:38:12 PM PDT 24 3125480258 ps
T116 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.905234059 Apr 25 12:37:41 PM PDT 24 Apr 25 12:40:16 PM PDT 24 1029538200 ps
T458 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2995494433 Apr 25 12:37:44 PM PDT 24 Apr 25 12:38:12 PM PDT 24 2464444642 ps

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3003650107
Short name T8
Test name
Test status
Simulation time 12979995009 ps
CPU time 364.57 seconds
Started Apr 25 12:41:19 PM PDT 24
Finished Apr 25 12:47:25 PM PDT 24
Peak memory 228904 kb
Host smart-3e634aa4-23ac-4221-b7d2-6df543049211
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003650107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3003650107
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3211710735
Short name T13
Test name
Test status
Simulation time 34486243432 ps
CPU time 5964.68 seconds
Started Apr 25 12:41:37 PM PDT 24
Finished Apr 25 02:21:03 PM PDT 24
Peak memory 236176 kb
Host smart-fe567634-b269-4436-acfa-2e28ed8a975d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211710735 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3211710735
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1082469273
Short name T12
Test name
Test status
Simulation time 3452463020 ps
CPU time 31 seconds
Started Apr 25 12:41:38 PM PDT 24
Finished Apr 25 12:42:11 PM PDT 24
Peak memory 215476 kb
Host smart-35bb1dc5-b8d0-4c10-93eb-17804fe47dc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082469273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1082469273
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3100861777
Short name T23
Test name
Test status
Simulation time 99679776487 ps
CPU time 980.08 seconds
Started Apr 25 12:42:07 PM PDT 24
Finished Apr 25 12:58:31 PM PDT 24
Peak memory 225984 kb
Host smart-63f8304b-a83c-480d-bc1f-8792c288db2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100861777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3100861777
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3364841648
Short name T62
Test name
Test status
Simulation time 8702834685 ps
CPU time 172.16 seconds
Started Apr 25 12:37:50 PM PDT 24
Finished Apr 25 12:40:45 PM PDT 24
Peak memory 213472 kb
Host smart-cc2202d7-91a1-4610-852b-81391b99b778
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364841648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3364841648
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3901457947
Short name T1
Test name
Test status
Simulation time 18557768965 ps
CPU time 79.39 seconds
Started Apr 25 12:41:51 PM PDT 24
Finished Apr 25 12:43:13 PM PDT 24
Peak memory 220336 kb
Host smart-b5607fed-ab26-49f7-9241-57aa37afd3ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901457947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3901457947
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.556241524
Short name T30
Test name
Test status
Simulation time 2899054113 ps
CPU time 134.05 seconds
Started Apr 25 12:41:11 PM PDT 24
Finished Apr 25 12:43:25 PM PDT 24
Peak memory 238732 kb
Host smart-506bd192-fe74-48a9-b42b-d53873532704
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556241524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.556241524
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.74036652
Short name T74
Test name
Test status
Simulation time 13980240141 ps
CPU time 136.87 seconds
Started Apr 25 12:37:24 PM PDT 24
Finished Apr 25 12:39:44 PM PDT 24
Peak memory 215664 kb
Host smart-40e15eab-2035-4e6e-9928-23a4bc21fcc8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74036652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pass
thru_mem_tl_intg_err.74036652
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4091446702
Short name T111
Test name
Test status
Simulation time 7020294232 ps
CPU time 171.55 seconds
Started Apr 25 12:37:40 PM PDT 24
Finished Apr 25 12:40:33 PM PDT 24
Peak memory 218752 kb
Host smart-43460de8-9ac7-4136-854e-ef8f0ce0bd2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091446702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.4091446702
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3583977957
Short name T58
Test name
Test status
Simulation time 2680367068 ps
CPU time 25.11 seconds
Started Apr 25 12:41:51 PM PDT 24
Finished Apr 25 12:42:18 PM PDT 24
Peak memory 211620 kb
Host smart-9012ae9d-286f-4042-9ad0-af9b83eee3f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583977957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3583977957
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.447980549
Short name T19
Test name
Test status
Simulation time 346129911 ps
CPU time 18.83 seconds
Started Apr 25 12:41:43 PM PDT 24
Finished Apr 25 12:42:04 PM PDT 24
Peak memory 214928 kb
Host smart-c1d37ae4-189b-4919-8951-a7ff9a1ad32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447980549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.447980549
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2584835263
Short name T131
Test name
Test status
Simulation time 17007278618 ps
CPU time 47.53 seconds
Started Apr 25 12:41:27 PM PDT 24
Finished Apr 25 12:42:15 PM PDT 24
Peak memory 215240 kb
Host smart-e4ef2405-6d05-4063-bf50-449e58d1a4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584835263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2584835263
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3415576516
Short name T24
Test name
Test status
Simulation time 12468919052 ps
CPU time 38.47 seconds
Started Apr 25 12:41:11 PM PDT 24
Finished Apr 25 12:41:50 PM PDT 24
Peak memory 215224 kb
Host smart-dfb77ee9-ab1d-402e-abf0-188a2f98924a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415576516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3415576516
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1801513227
Short name T113
Test name
Test status
Simulation time 3373985945 ps
CPU time 166.9 seconds
Started Apr 25 12:37:49 PM PDT 24
Finished Apr 25 12:40:39 PM PDT 24
Peak memory 213116 kb
Host smart-fb263293-4453-418c-8b16-a12ffce86cb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801513227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1801513227
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.316382295
Short name T14
Test name
Test status
Simulation time 78197755023 ps
CPU time 818.89 seconds
Started Apr 25 12:41:49 PM PDT 24
Finished Apr 25 12:55:31 PM PDT 24
Peak memory 235724 kb
Host smart-57425ad5-b39a-4967-8e56-c0c4d86104a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316382295 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.316382295
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3426931282
Short name T119
Test name
Test status
Simulation time 6908422466 ps
CPU time 158.15 seconds
Started Apr 25 12:37:26 PM PDT 24
Finished Apr 25 12:40:06 PM PDT 24
Peak memory 213728 kb
Host smart-1b0279b9-d6c6-4bcf-8c17-5acda3415148
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426931282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3426931282
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4025347373
Short name T86
Test name
Test status
Simulation time 5514386023 ps
CPU time 91.36 seconds
Started Apr 25 12:37:49 PM PDT 24
Finished Apr 25 12:39:24 PM PDT 24
Peak memory 214220 kb
Host smart-85a5f815-83e0-459e-b663-a32eaec2db77
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025347373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.4025347373
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3480399842
Short name T65
Test name
Test status
Simulation time 2033237410 ps
CPU time 19.99 seconds
Started Apr 25 12:37:33 PM PDT 24
Finished Apr 25 12:37:54 PM PDT 24
Peak memory 211656 kb
Host smart-b97059ca-1320-43cb-98e7-9723dc77d1e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480399842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3480399842
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2238505741
Short name T45
Test name
Test status
Simulation time 9856196566 ps
CPU time 19.71 seconds
Started Apr 25 12:41:47 PM PDT 24
Finished Apr 25 12:42:09 PM PDT 24
Peak memory 211956 kb
Host smart-d0a9581d-2142-41e0-9cb2-7b270e7b7d17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2238505741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2238505741
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1201325202
Short name T16
Test name
Test status
Simulation time 49096603966 ps
CPU time 1661.13 seconds
Started Apr 25 12:41:49 PM PDT 24
Finished Apr 25 01:09:33 PM PDT 24
Peak memory 239404 kb
Host smart-4e657a3c-0b0b-49a6-a10c-c061d4e73882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201325202 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1201325202
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2207757524
Short name T456
Test name
Test status
Simulation time 176354540 ps
CPU time 8.07 seconds
Started Apr 25 12:37:27 PM PDT 24
Finished Apr 25 12:37:42 PM PDT 24
Peak memory 210476 kb
Host smart-a415fe0f-ac1c-4efe-b4d3-ab5d15e86ce8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207757524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2207757524
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.251586964
Short name T406
Test name
Test status
Simulation time 2618025318 ps
CPU time 23.53 seconds
Started Apr 25 12:37:45 PM PDT 24
Finished Apr 25 12:38:12 PM PDT 24
Peak memory 210936 kb
Host smart-719a33ad-9460-471c-82a9-40cd654edbd6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251586964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.251586964
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1613920499
Short name T402
Test name
Test status
Simulation time 5878705610 ps
CPU time 32.22 seconds
Started Apr 25 12:37:43 PM PDT 24
Finished Apr 25 12:38:18 PM PDT 24
Peak memory 211096 kb
Host smart-957a4fe3-b6dc-48d8-8480-cabb969d2854
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613920499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1613920499
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3643769583
Short name T445
Test name
Test status
Simulation time 305994154 ps
CPU time 10.14 seconds
Started Apr 25 12:37:45 PM PDT 24
Finished Apr 25 12:37:58 PM PDT 24
Peak memory 215264 kb
Host smart-20954a86-4172-4ab4-ad4c-fabe83e27bb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643769583 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3643769583
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1000436266
Short name T420
Test name
Test status
Simulation time 167578523 ps
CPU time 8.62 seconds
Started Apr 25 12:37:30 PM PDT 24
Finished Apr 25 12:37:40 PM PDT 24
Peak memory 210400 kb
Host smart-87d733a9-5638-4d82-88a8-122c6ffff637
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000436266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1000436266
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.731383832
Short name T423
Test name
Test status
Simulation time 7497540689 ps
CPU time 28.29 seconds
Started Apr 25 12:37:38 PM PDT 24
Finished Apr 25 12:38:07 PM PDT 24
Peak memory 210408 kb
Host smart-87090046-b8ca-48c1-9511-3a8f4d8d9a2e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731383832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.731383832
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1563522405
Short name T379
Test name
Test status
Simulation time 12417933715 ps
CPU time 26.41 seconds
Started Apr 25 12:37:45 PM PDT 24
Finished Apr 25 12:38:14 PM PDT 24
Peak memory 210404 kb
Host smart-bbe13fd3-e2e2-4ad2-b722-cfa7e454d114
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563522405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1563522405
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2073601778
Short name T92
Test name
Test status
Simulation time 45452074965 ps
CPU time 125.59 seconds
Started Apr 25 12:37:42 PM PDT 24
Finished Apr 25 12:39:51 PM PDT 24
Peak memory 214716 kb
Host smart-1f8d6e88-855d-4429-882e-9dbe374b55b4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073601778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2073601778
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1075558664
Short name T366
Test name
Test status
Simulation time 3377081360 ps
CPU time 31.9 seconds
Started Apr 25 12:37:27 PM PDT 24
Finished Apr 25 12:38:01 PM PDT 24
Peak memory 217288 kb
Host smart-19f1f705-72ec-4b92-b756-8ecbe8738a3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075558664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1075558664
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1751960452
Short name T93
Test name
Test status
Simulation time 12533550388 ps
CPU time 27.03 seconds
Started Apr 25 12:37:48 PM PDT 24
Finished Apr 25 12:38:18 PM PDT 24
Peak memory 211540 kb
Host smart-848e234d-e555-42f2-93f0-5606dc05537e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751960452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1751960452
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3374478601
Short name T377
Test name
Test status
Simulation time 10896178345 ps
CPU time 27.19 seconds
Started Apr 25 12:37:33 PM PDT 24
Finished Apr 25 12:38:02 PM PDT 24
Peak memory 211620 kb
Host smart-449c876f-9eac-46c5-a3ea-bb63923e7cec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374478601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3374478601
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3151464885
Short name T94
Test name
Test status
Simulation time 180309915 ps
CPU time 15.62 seconds
Started Apr 25 12:37:26 PM PDT 24
Finished Apr 25 12:37:44 PM PDT 24
Peak memory 210820 kb
Host smart-ba1d3298-a5f7-46cb-8733-a3a6a15a334e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151464885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3151464885
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.916150954
Short name T394
Test name
Test status
Simulation time 10229629122 ps
CPU time 24.36 seconds
Started Apr 25 12:37:25 PM PDT 24
Finished Apr 25 12:37:52 PM PDT 24
Peak memory 218780 kb
Host smart-8300f840-c06b-46fc-8bf8-364849a2d9f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916150954 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.916150954
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2748882483
Short name T436
Test name
Test status
Simulation time 2537007276 ps
CPU time 23.32 seconds
Started Apr 25 12:37:17 PM PDT 24
Finished Apr 25 12:37:44 PM PDT 24
Peak memory 210964 kb
Host smart-70b84139-3286-4578-b4eb-be2a2b31866b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748882483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2748882483
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.248714767
Short name T380
Test name
Test status
Simulation time 751252790 ps
CPU time 8.01 seconds
Started Apr 25 12:37:38 PM PDT 24
Finished Apr 25 12:37:47 PM PDT 24
Peak memory 210184 kb
Host smart-b8485683-647b-4712-a6e6-dc281945754b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248714767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.248714767
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3838789840
Short name T398
Test name
Test status
Simulation time 859812431 ps
CPU time 13.4 seconds
Started Apr 25 12:37:42 PM PDT 24
Finished Apr 25 12:37:59 PM PDT 24
Peak memory 210336 kb
Host smart-8cc42b86-8034-4313-8465-f0099d7d22cf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838789840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3838789840
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.268485544
Short name T425
Test name
Test status
Simulation time 167643972 ps
CPU time 8.58 seconds
Started Apr 25 12:37:36 PM PDT 24
Finished Apr 25 12:37:46 PM PDT 24
Peak memory 210408 kb
Host smart-7c8586fd-cdf9-44ed-943e-207103555f39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268485544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.268485544
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3138646995
Short name T443
Test name
Test status
Simulation time 6961337710 ps
CPU time 18.19 seconds
Started Apr 25 12:37:33 PM PDT 24
Finished Apr 25 12:37:53 PM PDT 24
Peak memory 217804 kb
Host smart-0224f7fa-4d13-4f4a-93b8-273a8331f962
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138646995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3138646995
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.905234059
Short name T116
Test name
Test status
Simulation time 1029538200 ps
CPU time 152.69 seconds
Started Apr 25 12:37:41 PM PDT 24
Finished Apr 25 12:40:16 PM PDT 24
Peak memory 213072 kb
Host smart-44f92f19-b05c-4ebd-ae60-77da01cf9b8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905234059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.905234059
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3259275071
Short name T381
Test name
Test status
Simulation time 21619086882 ps
CPU time 22.84 seconds
Started Apr 25 12:37:53 PM PDT 24
Finished Apr 25 12:38:18 PM PDT 24
Peak memory 216572 kb
Host smart-11bbb196-3cec-4670-8785-7f648ffd390a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259275071 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3259275071
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1054465440
Short name T395
Test name
Test status
Simulation time 52189366871 ps
CPU time 24.65 seconds
Started Apr 25 12:37:49 PM PDT 24
Finished Apr 25 12:38:16 PM PDT 24
Peak memory 211452 kb
Host smart-e52da064-55ad-4842-96be-54d4d198a8a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054465440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1054465440
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.939201842
Short name T89
Test name
Test status
Simulation time 725280058 ps
CPU time 37.64 seconds
Started Apr 25 12:37:48 PM PDT 24
Finished Apr 25 12:38:29 PM PDT 24
Peak memory 212496 kb
Host smart-9f5f1648-ac65-4de8-b193-dce0f7cc7631
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939201842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.939201842
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.926833734
Short name T433
Test name
Test status
Simulation time 4083818089 ps
CPU time 12.19 seconds
Started Apr 25 12:37:51 PM PDT 24
Finished Apr 25 12:38:05 PM PDT 24
Peak memory 210536 kb
Host smart-d77f7699-7919-4db9-bf0e-1b574b5b7287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926833734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.926833734
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.592356631
Short name T393
Test name
Test status
Simulation time 3340911745 ps
CPU time 30.51 seconds
Started Apr 25 12:37:59 PM PDT 24
Finished Apr 25 12:38:30 PM PDT 24
Peak memory 217672 kb
Host smart-7edc9442-6148-45bb-b65d-7e0c2e3c77c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592356631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.592356631
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2789003754
Short name T412
Test name
Test status
Simulation time 2444828313 ps
CPU time 90.85 seconds
Started Apr 25 12:37:49 PM PDT 24
Finished Apr 25 12:39:22 PM PDT 24
Peak memory 213460 kb
Host smart-b7602f64-e800-471d-8ce8-a47201e2a908
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789003754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2789003754
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2540824669
Short name T382
Test name
Test status
Simulation time 1128917710 ps
CPU time 15.58 seconds
Started Apr 25 12:37:44 PM PDT 24
Finished Apr 25 12:38:02 PM PDT 24
Peak memory 214360 kb
Host smart-ee8d9b44-718a-4119-85d4-ddeda1a97561
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540824669 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2540824669
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2191211575
Short name T386
Test name
Test status
Simulation time 9983283655 ps
CPU time 22.22 seconds
Started Apr 25 12:37:48 PM PDT 24
Finished Apr 25 12:38:14 PM PDT 24
Peak memory 211444 kb
Host smart-e6635431-4965-4242-845a-701f935f9c0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191211575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2191211575
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2009289093
Short name T424
Test name
Test status
Simulation time 2083081295 ps
CPU time 19.3 seconds
Started Apr 25 12:37:45 PM PDT 24
Finished Apr 25 12:38:07 PM PDT 24
Peak memory 211636 kb
Host smart-dc488be0-1a50-4aa0-8946-dc95144290da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009289093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2009289093
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3541037273
Short name T372
Test name
Test status
Simulation time 1815156829 ps
CPU time 17.39 seconds
Started Apr 25 12:37:51 PM PDT 24
Finished Apr 25 12:38:11 PM PDT 24
Peak memory 217496 kb
Host smart-17d569d1-7a64-4219-8f33-07a0bda01daa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541037273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3541037273
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3648337748
Short name T457
Test name
Test status
Simulation time 3125480258 ps
CPU time 18.34 seconds
Started Apr 25 12:37:51 PM PDT 24
Finished Apr 25 12:38:12 PM PDT 24
Peak memory 214996 kb
Host smart-195db191-ce46-4975-a694-bb50efad0c57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648337748 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3648337748
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3200410189
Short name T78
Test name
Test status
Simulation time 259007241 ps
CPU time 9.7 seconds
Started Apr 25 12:37:52 PM PDT 24
Finished Apr 25 12:38:04 PM PDT 24
Peak memory 210360 kb
Host smart-3baa8909-ecec-42db-b550-ccdb8d8343a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200410189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3200410189
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2318023400
Short name T399
Test name
Test status
Simulation time 16277260203 ps
CPU time 156.74 seconds
Started Apr 25 12:37:51 PM PDT 24
Finished Apr 25 12:40:30 PM PDT 24
Peak memory 214792 kb
Host smart-40d8ac62-63d6-4d8a-be85-58182c8b206a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318023400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2318023400
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2575634141
Short name T77
Test name
Test status
Simulation time 12278220355 ps
CPU time 25.75 seconds
Started Apr 25 12:37:44 PM PDT 24
Finished Apr 25 12:38:13 PM PDT 24
Peak memory 211920 kb
Host smart-040c9844-4b79-427a-9f4d-3a5b2478f606
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575634141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2575634141
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1005867996
Short name T373
Test name
Test status
Simulation time 585998878 ps
CPU time 16.27 seconds
Started Apr 25 12:37:51 PM PDT 24
Finished Apr 25 12:38:10 PM PDT 24
Peak memory 216592 kb
Host smart-ed0bd8a7-5745-4659-85aa-ecc718582e04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005867996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1005867996
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3909480662
Short name T109
Test name
Test status
Simulation time 3947629978 ps
CPU time 94.23 seconds
Started Apr 25 12:37:56 PM PDT 24
Finished Apr 25 12:39:33 PM PDT 24
Peak memory 212668 kb
Host smart-511a426f-2c94-4186-a29f-b663da9546e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909480662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3909480662
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1534117012
Short name T401
Test name
Test status
Simulation time 274718291 ps
CPU time 10.16 seconds
Started Apr 25 12:37:49 PM PDT 24
Finished Apr 25 12:38:02 PM PDT 24
Peak memory 213328 kb
Host smart-4735b513-0014-4b3c-af67-0a772678088d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534117012 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1534117012
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.958148756
Short name T437
Test name
Test status
Simulation time 507772483 ps
CPU time 11.79 seconds
Started Apr 25 12:37:51 PM PDT 24
Finished Apr 25 12:38:06 PM PDT 24
Peak memory 210444 kb
Host smart-af85c314-5cde-4095-8224-56daf99ef02a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958148756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.958148756
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.826746970
Short name T432
Test name
Test status
Simulation time 19110106794 ps
CPU time 98.86 seconds
Started Apr 25 12:37:46 PM PDT 24
Finished Apr 25 12:39:28 PM PDT 24
Peak memory 214668 kb
Host smart-210e6427-9872-481e-bdd3-e1fd30e6c459
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826746970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.826746970
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1295027975
Short name T431
Test name
Test status
Simulation time 2465126750 ps
CPU time 23.87 seconds
Started Apr 25 12:37:57 PM PDT 24
Finished Apr 25 12:38:23 PM PDT 24
Peak memory 211676 kb
Host smart-521f3520-2960-4891-94f5-d9b2d8b84bb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295027975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1295027975
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2794027358
Short name T422
Test name
Test status
Simulation time 12121077039 ps
CPU time 32.67 seconds
Started Apr 25 12:37:55 PM PDT 24
Finished Apr 25 12:38:30 PM PDT 24
Peak memory 216868 kb
Host smart-1d56c5b0-7195-4b0f-a751-81512ad2e32f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794027358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2794027358
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1697196071
Short name T407
Test name
Test status
Simulation time 3021098751 ps
CPU time 84.53 seconds
Started Apr 25 12:37:51 PM PDT 24
Finished Apr 25 12:39:18 PM PDT 24
Peak memory 211336 kb
Host smart-356fb6db-1242-45b2-bd17-c8e0e7244cf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697196071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1697196071
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2870059261
Short name T66
Test name
Test status
Simulation time 2985848775 ps
CPU time 25.47 seconds
Started Apr 25 12:37:52 PM PDT 24
Finished Apr 25 12:38:19 PM PDT 24
Peak memory 216440 kb
Host smart-c45ea2c7-7344-47db-ba94-886e20fb4dc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870059261 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2870059261
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2014555703
Short name T102
Test name
Test status
Simulation time 1200454859 ps
CPU time 16.22 seconds
Started Apr 25 12:37:57 PM PDT 24
Finished Apr 25 12:38:15 PM PDT 24
Peak memory 210404 kb
Host smart-f0b88277-1b33-4512-a522-2c69f7d86143
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014555703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2014555703
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.693275331
Short name T410
Test name
Test status
Simulation time 17480516074 ps
CPU time 131.99 seconds
Started Apr 25 12:37:54 PM PDT 24
Finished Apr 25 12:40:08 PM PDT 24
Peak memory 212984 kb
Host smart-362f9478-3d14-468b-9fc2-86c4f015c6ad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693275331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.693275331
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2164408550
Short name T101
Test name
Test status
Simulation time 7038321942 ps
CPU time 24.1 seconds
Started Apr 25 12:38:07 PM PDT 24
Finished Apr 25 12:38:34 PM PDT 24
Peak memory 212044 kb
Host smart-cc175f6c-dbd0-44fd-87ec-85b2b7a7c2ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164408550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2164408550
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1341897902
Short name T408
Test name
Test status
Simulation time 689552279 ps
CPU time 11.24 seconds
Started Apr 25 12:37:53 PM PDT 24
Finished Apr 25 12:38:06 PM PDT 24
Peak memory 216352 kb
Host smart-52f4f5af-b994-45bd-ae6e-fc2cdce29a9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341897902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1341897902
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1060814180
Short name T118
Test name
Test status
Simulation time 6120430488 ps
CPU time 82.02 seconds
Started Apr 25 12:37:55 PM PDT 24
Finished Apr 25 12:39:19 PM PDT 24
Peak memory 212892 kb
Host smart-987c189e-8cfc-4ea2-8964-c6ada93e35c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060814180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1060814180
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.244049305
Short name T378
Test name
Test status
Simulation time 14907550053 ps
CPU time 28.28 seconds
Started Apr 25 12:37:53 PM PDT 24
Finished Apr 25 12:38:24 PM PDT 24
Peak memory 217268 kb
Host smart-bd1fadd1-1965-4f24-adb2-d6951cdf8dea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244049305 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.244049305
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.640108885
Short name T72
Test name
Test status
Simulation time 2548480531 ps
CPU time 23.34 seconds
Started Apr 25 12:37:55 PM PDT 24
Finished Apr 25 12:38:20 PM PDT 24
Peak memory 210936 kb
Host smart-4ad0ca0f-84e7-41df-bcb9-34ac4e73cc9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640108885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.640108885
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3652176751
Short name T91
Test name
Test status
Simulation time 28509005922 ps
CPU time 103.65 seconds
Started Apr 25 12:37:52 PM PDT 24
Finished Apr 25 12:39:38 PM PDT 24
Peak memory 214752 kb
Host smart-c75010e1-1eba-4b89-9aaa-f65041c73350
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652176751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3652176751
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4169170618
Short name T71
Test name
Test status
Simulation time 9546366988 ps
CPU time 15.37 seconds
Started Apr 25 12:37:51 PM PDT 24
Finished Apr 25 12:38:09 PM PDT 24
Peak memory 210808 kb
Host smart-8eaa63d5-7c5c-48b3-b725-d3b41163b12c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169170618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.4169170618
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2328430391
Short name T451
Test name
Test status
Simulation time 4122465752 ps
CPU time 34.68 seconds
Started Apr 25 12:37:55 PM PDT 24
Finished Apr 25 12:38:32 PM PDT 24
Peak memory 217744 kb
Host smart-81d4e4f2-deff-45c3-967d-7aae2d6b1443
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328430391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2328430391
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2714106606
Short name T413
Test name
Test status
Simulation time 13475258030 ps
CPU time 99.27 seconds
Started Apr 25 12:37:52 PM PDT 24
Finished Apr 25 12:39:34 PM PDT 24
Peak memory 218760 kb
Host smart-7daa1a01-5889-457f-8847-facf07079b2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714106606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2714106606
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3000030502
Short name T405
Test name
Test status
Simulation time 735711400 ps
CPU time 8.29 seconds
Started Apr 25 12:37:51 PM PDT 24
Finished Apr 25 12:38:02 PM PDT 24
Peak memory 213400 kb
Host smart-371aaadb-15ea-42f9-8d8f-bed184162d19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000030502 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3000030502
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2015917336
Short name T96
Test name
Test status
Simulation time 5497553834 ps
CPU time 24.83 seconds
Started Apr 25 12:38:05 PM PDT 24
Finished Apr 25 12:38:31 PM PDT 24
Peak memory 211644 kb
Host smart-ce21e4b9-bd22-4d4f-9d7d-8f9ab81776c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015917336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2015917336
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.522772090
Short name T383
Test name
Test status
Simulation time 45382486835 ps
CPU time 121.6 seconds
Started Apr 25 12:37:48 PM PDT 24
Finished Apr 25 12:39:53 PM PDT 24
Peak memory 214688 kb
Host smart-85cf0079-c3da-400d-8693-8ca354dec95e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522772090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.522772090
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3846622274
Short name T430
Test name
Test status
Simulation time 1341613248 ps
CPU time 12.27 seconds
Started Apr 25 12:37:52 PM PDT 24
Finished Apr 25 12:38:07 PM PDT 24
Peak memory 210692 kb
Host smart-df94771f-0a44-435b-b735-3b08d1194eb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846622274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3846622274
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3706572318
Short name T421
Test name
Test status
Simulation time 2145401036 ps
CPU time 27.54 seconds
Started Apr 25 12:37:53 PM PDT 24
Finished Apr 25 12:38:23 PM PDT 24
Peak memory 216748 kb
Host smart-0a1a316e-9e23-4fc6-9014-8466bac2a487
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706572318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3706572318
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3942388304
Short name T110
Test name
Test status
Simulation time 1244498186 ps
CPU time 155.8 seconds
Started Apr 25 12:38:03 PM PDT 24
Finished Apr 25 12:40:40 PM PDT 24
Peak memory 212932 kb
Host smart-e4ffcf97-114c-4191-94ee-3f372a47b00a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942388304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3942388304
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.167839834
Short name T364
Test name
Test status
Simulation time 13431985711 ps
CPU time 23.59 seconds
Started Apr 25 12:37:52 PM PDT 24
Finished Apr 25 12:38:18 PM PDT 24
Peak memory 216744 kb
Host smart-3be15673-68c5-4e08-b738-46a86ae37cb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167839834 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.167839834
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.83164328
Short name T375
Test name
Test status
Simulation time 3434317281 ps
CPU time 13.96 seconds
Started Apr 25 12:37:53 PM PDT 24
Finished Apr 25 12:38:10 PM PDT 24
Peak memory 210440 kb
Host smart-dbd69cf9-632f-4a07-813e-ab7347d492e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83164328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.83164328
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3030740320
Short name T105
Test name
Test status
Simulation time 13765101963 ps
CPU time 116.18 seconds
Started Apr 25 12:37:53 PM PDT 24
Finished Apr 25 12:39:52 PM PDT 24
Peak memory 213708 kb
Host smart-82c3a3da-6e3a-4dea-9286-31d4d4e7281c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030740320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3030740320
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.260461226
Short name T427
Test name
Test status
Simulation time 12268682618 ps
CPU time 25.14 seconds
Started Apr 25 12:37:51 PM PDT 24
Finished Apr 25 12:38:18 PM PDT 24
Peak memory 210552 kb
Host smart-99788076-ec96-4bfa-a079-e37db0845fd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260461226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.260461226
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2891059815
Short name T368
Test name
Test status
Simulation time 9891117459 ps
CPU time 26.33 seconds
Started Apr 25 12:37:53 PM PDT 24
Finished Apr 25 12:38:22 PM PDT 24
Peak memory 217664 kb
Host smart-2b53ec9a-18e9-403b-80fe-cea941d1baf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891059815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2891059815
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.13859448
Short name T371
Test name
Test status
Simulation time 24152004242 ps
CPU time 29.08 seconds
Started Apr 25 12:38:11 PM PDT 24
Finished Apr 25 12:38:43 PM PDT 24
Peak memory 218812 kb
Host smart-fab7aa79-aa9f-444b-a3d1-1925d1fca43e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13859448 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.13859448
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.465871130
Short name T446
Test name
Test status
Simulation time 5442560645 ps
CPU time 16.87 seconds
Started Apr 25 12:37:56 PM PDT 24
Finished Apr 25 12:38:15 PM PDT 24
Peak memory 211568 kb
Host smart-03dc88dd-e824-4b88-b0af-3e5b99807146
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465871130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.465871130
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2199881863
Short name T87
Test name
Test status
Simulation time 54348196022 ps
CPU time 120.14 seconds
Started Apr 25 12:37:54 PM PDT 24
Finished Apr 25 12:39:56 PM PDT 24
Peak memory 213032 kb
Host smart-7b972b6a-eb5b-4bb1-8119-bd7deec7f266
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199881863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2199881863
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3697205748
Short name T448
Test name
Test status
Simulation time 1454787425 ps
CPU time 11.66 seconds
Started Apr 25 12:37:56 PM PDT 24
Finished Apr 25 12:38:10 PM PDT 24
Peak memory 210420 kb
Host smart-04659ad1-7ca6-4eaa-8b37-b63cc49a3050
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697205748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3697205748
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1889503071
Short name T388
Test name
Test status
Simulation time 214150299 ps
CPU time 11.31 seconds
Started Apr 25 12:37:54 PM PDT 24
Finished Apr 25 12:38:07 PM PDT 24
Peak memory 216408 kb
Host smart-a9990cdc-3a06-4a93-a0ed-3ff7b0e1da6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889503071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1889503071
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1818799884
Short name T63
Test name
Test status
Simulation time 14789732315 ps
CPU time 101.24 seconds
Started Apr 25 12:37:53 PM PDT 24
Finished Apr 25 12:39:37 PM PDT 24
Peak memory 212980 kb
Host smart-475963a0-9f4f-42bf-b21a-29691bd71328
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818799884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1818799884
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1299755882
Short name T374
Test name
Test status
Simulation time 3510861142 ps
CPU time 25.95 seconds
Started Apr 25 12:38:03 PM PDT 24
Finished Apr 25 12:38:30 PM PDT 24
Peak memory 216672 kb
Host smart-d568ef2e-9fe1-4a69-a323-5b655ce6673a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299755882 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1299755882
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.878280375
Short name T75
Test name
Test status
Simulation time 10301428059 ps
CPU time 23.98 seconds
Started Apr 25 12:38:08 PM PDT 24
Finished Apr 25 12:38:34 PM PDT 24
Peak memory 211296 kb
Host smart-f917c3db-6541-478d-a5b2-bcadd016ce49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878280375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.878280375
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3719758840
Short name T80
Test name
Test status
Simulation time 12274164167 ps
CPU time 128.13 seconds
Started Apr 25 12:37:54 PM PDT 24
Finished Apr 25 12:40:05 PM PDT 24
Peak memory 214844 kb
Host smart-97711508-69a7-487e-8f87-2f5085ea31b1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719758840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3719758840
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3134295892
Short name T104
Test name
Test status
Simulation time 18376022151 ps
CPU time 33.13 seconds
Started Apr 25 12:38:01 PM PDT 24
Finished Apr 25 12:38:35 PM PDT 24
Peak memory 211576 kb
Host smart-d1c3e443-bc0e-41e6-8d80-08d83919a6b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134295892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3134295892
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2202945648
Short name T390
Test name
Test status
Simulation time 169233028 ps
CPU time 11.9 seconds
Started Apr 25 12:38:06 PM PDT 24
Finished Apr 25 12:38:20 PM PDT 24
Peak memory 216832 kb
Host smart-62fe2d41-d2cb-438d-b636-d2668a04e06d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202945648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2202945648
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2021651176
Short name T439
Test name
Test status
Simulation time 1115343666 ps
CPU time 153.27 seconds
Started Apr 25 12:37:59 PM PDT 24
Finished Apr 25 12:40:34 PM PDT 24
Peak memory 213224 kb
Host smart-f990e0d0-8552-46c3-9311-88bd74bf583a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021651176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2021651176
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1079976173
Short name T417
Test name
Test status
Simulation time 661607636 ps
CPU time 8.14 seconds
Started Apr 25 12:37:34 PM PDT 24
Finished Apr 25 12:37:44 PM PDT 24
Peak memory 210396 kb
Host smart-6b0a9608-b6ee-46ba-99a9-e8e5fef44ff9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079976173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1079976173
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2935321896
Short name T449
Test name
Test status
Simulation time 171051859 ps
CPU time 8.42 seconds
Started Apr 25 12:37:30 PM PDT 24
Finished Apr 25 12:37:40 PM PDT 24
Peak memory 210400 kb
Host smart-c08a3069-ecfc-4094-8247-9deca5a75d5d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935321896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2935321896
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.960678290
Short name T76
Test name
Test status
Simulation time 1445782034 ps
CPU time 17.51 seconds
Started Apr 25 12:37:26 PM PDT 24
Finished Apr 25 12:37:46 PM PDT 24
Peak memory 211128 kb
Host smart-4cdaa19f-6355-4cfb-8c89-4e020c90afcc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960678290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.960678290
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4216113140
Short name T400
Test name
Test status
Simulation time 1221284355 ps
CPU time 15.86 seconds
Started Apr 25 12:37:31 PM PDT 24
Finished Apr 25 12:37:48 PM PDT 24
Peak memory 216092 kb
Host smart-52bab873-5a1d-41df-936e-f510c282d9dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216113140 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4216113140
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1904001276
Short name T452
Test name
Test status
Simulation time 409726337 ps
CPU time 11.33 seconds
Started Apr 25 12:37:46 PM PDT 24
Finished Apr 25 12:38:00 PM PDT 24
Peak memory 210448 kb
Host smart-9cc0c429-5d54-429c-ba23-637d061d3d58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904001276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1904001276
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1644570366
Short name T455
Test name
Test status
Simulation time 14537846649 ps
CPU time 20.38 seconds
Started Apr 25 12:37:25 PM PDT 24
Finished Apr 25 12:37:49 PM PDT 24
Peak memory 210404 kb
Host smart-73ae7558-00ac-40a8-b93c-70f3bc55d96b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644570366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1644570366
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2016793897
Short name T362
Test name
Test status
Simulation time 18370045515 ps
CPU time 30.92 seconds
Started Apr 25 12:37:40 PM PDT 24
Finished Apr 25 12:38:13 PM PDT 24
Peak memory 210456 kb
Host smart-b95402ad-e8d0-4336-8024-18e969e12191
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016793897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2016793897
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4282494339
Short name T90
Test name
Test status
Simulation time 32545405089 ps
CPU time 155.93 seconds
Started Apr 25 12:37:39 PM PDT 24
Finished Apr 25 12:40:16 PM PDT 24
Peak memory 214668 kb
Host smart-d2758124-6396-4add-bc1c-698c7db75676
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282494339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.4282494339
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1527957942
Short name T450
Test name
Test status
Simulation time 1498395899 ps
CPU time 8.47 seconds
Started Apr 25 12:37:28 PM PDT 24
Finished Apr 25 12:37:39 PM PDT 24
Peak memory 210616 kb
Host smart-3f514b64-1121-46f5-bed5-af055feaa2b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527957942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1527957942
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2589944517
Short name T442
Test name
Test status
Simulation time 661171100 ps
CPU time 12.91 seconds
Started Apr 25 12:37:26 PM PDT 24
Finished Apr 25 12:37:42 PM PDT 24
Peak memory 215732 kb
Host smart-977d6900-36cf-4353-931f-b35036d4e579
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589944517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2589944517
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3829409421
Short name T114
Test name
Test status
Simulation time 16185378010 ps
CPU time 171.27 seconds
Started Apr 25 12:37:27 PM PDT 24
Finished Apr 25 12:40:20 PM PDT 24
Peak memory 213428 kb
Host smart-5d834562-9ee6-4f47-9215-3277e6621c5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829409421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3829409421
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1455129258
Short name T83
Test name
Test status
Simulation time 336852150 ps
CPU time 10.64 seconds
Started Apr 25 12:37:42 PM PDT 24
Finished Apr 25 12:37:56 PM PDT 24
Peak memory 210436 kb
Host smart-7ff1c6aa-0775-4529-9325-ddd7ea4ffa49
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455129258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1455129258
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3424562068
Short name T453
Test name
Test status
Simulation time 10470925119 ps
CPU time 17.26 seconds
Started Apr 25 12:37:43 PM PDT 24
Finished Apr 25 12:38:03 PM PDT 24
Peak memory 211100 kb
Host smart-60161443-ffea-48b3-b2bb-fb71221f837b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424562068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3424562068
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2745363441
Short name T95
Test name
Test status
Simulation time 6267481720 ps
CPU time 27.42 seconds
Started Apr 25 12:37:29 PM PDT 24
Finished Apr 25 12:37:58 PM PDT 24
Peak memory 211220 kb
Host smart-996d360b-c8e8-487e-816b-8e6f95bea006
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745363441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2745363441
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3190079376
Short name T415
Test name
Test status
Simulation time 3852554013 ps
CPU time 22.72 seconds
Started Apr 25 12:37:33 PM PDT 24
Finished Apr 25 12:37:57 PM PDT 24
Peak memory 215280 kb
Host smart-77e7722c-c836-40a0-a431-1756f12ebeec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190079376 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3190079376
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.301028608
Short name T384
Test name
Test status
Simulation time 1485027095 ps
CPU time 17.66 seconds
Started Apr 25 12:37:28 PM PDT 24
Finished Apr 25 12:37:48 PM PDT 24
Peak memory 211024 kb
Host smart-77edb04e-2ba4-40cd-9eaa-9c7cb1775424
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301028608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.301028608
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3796874187
Short name T360
Test name
Test status
Simulation time 577643920 ps
CPU time 11.91 seconds
Started Apr 25 12:37:27 PM PDT 24
Finished Apr 25 12:37:41 PM PDT 24
Peak memory 210004 kb
Host smart-7f2efa0d-df28-4ffc-9fe9-161000a00494
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796874187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3796874187
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1962664454
Short name T397
Test name
Test status
Simulation time 4204571254 ps
CPU time 20.04 seconds
Started Apr 25 12:37:25 PM PDT 24
Finished Apr 25 12:37:48 PM PDT 24
Peak memory 210444 kb
Host smart-85eebc0f-8a29-476f-800c-3b69484160f5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962664454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1962664454
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1419582902
Short name T409
Test name
Test status
Simulation time 15254869216 ps
CPU time 122.22 seconds
Started Apr 25 12:37:32 PM PDT 24
Finished Apr 25 12:39:36 PM PDT 24
Peak memory 213544 kb
Host smart-f8712eb7-e94d-44b8-8e39-d3284b0f1ef3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419582902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1419582902
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.181078463
Short name T396
Test name
Test status
Simulation time 2355252905 ps
CPU time 8.25 seconds
Started Apr 25 12:37:39 PM PDT 24
Finished Apr 25 12:37:49 PM PDT 24
Peak memory 210652 kb
Host smart-a2934abe-efc5-4df2-8674-c4d4f866d2d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181078463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.181078463
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4245114850
Short name T387
Test name
Test status
Simulation time 4425403755 ps
CPU time 15.26 seconds
Started Apr 25 12:37:33 PM PDT 24
Finished Apr 25 12:37:50 PM PDT 24
Peak memory 217772 kb
Host smart-8414b994-0913-4633-858c-db9de28097d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245114850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4245114850
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4286689735
Short name T419
Test name
Test status
Simulation time 1863199626 ps
CPU time 84.92 seconds
Started Apr 25 12:37:35 PM PDT 24
Finished Apr 25 12:39:01 PM PDT 24
Peak memory 212792 kb
Host smart-261d731e-864e-4357-9078-db6d87f908d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286689735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.4286689735
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4068043038
Short name T385
Test name
Test status
Simulation time 4753113169 ps
CPU time 14.12 seconds
Started Apr 25 12:37:42 PM PDT 24
Finished Apr 25 12:38:00 PM PDT 24
Peak memory 210548 kb
Host smart-8e80f7f2-48b7-4e11-88c7-922e57723188
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068043038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.4068043038
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2851124964
Short name T392
Test name
Test status
Simulation time 2139553680 ps
CPU time 21.64 seconds
Started Apr 25 12:37:35 PM PDT 24
Finished Apr 25 12:37:57 PM PDT 24
Peak memory 211008 kb
Host smart-cd5ffc3f-957f-452e-8db5-849920d699b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851124964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2851124964
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2584530166
Short name T418
Test name
Test status
Simulation time 13294906179 ps
CPU time 33.87 seconds
Started Apr 25 12:37:36 PM PDT 24
Finished Apr 25 12:38:11 PM PDT 24
Peak memory 211320 kb
Host smart-6f40155d-a0dd-4cc2-8b43-028edf76b220
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584530166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2584530166
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.881414868
Short name T370
Test name
Test status
Simulation time 1017817507 ps
CPU time 12.52 seconds
Started Apr 25 12:37:44 PM PDT 24
Finished Apr 25 12:38:00 PM PDT 24
Peak memory 216328 kb
Host smart-0ace4d40-f1f4-49d6-8073-f41cfc5b0173
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881414868 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.881414868
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4132276061
Short name T106
Test name
Test status
Simulation time 170712878 ps
CPU time 8.19 seconds
Started Apr 25 12:37:45 PM PDT 24
Finished Apr 25 12:37:56 PM PDT 24
Peak memory 210460 kb
Host smart-a0627596-3f08-4d0d-a570-e415a7257b1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132276061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.4132276061
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1477153733
Short name T416
Test name
Test status
Simulation time 4277113908 ps
CPU time 20.09 seconds
Started Apr 25 12:37:41 PM PDT 24
Finished Apr 25 12:38:04 PM PDT 24
Peak memory 210396 kb
Host smart-fe424f56-94cf-40a8-9517-23efd544b2b0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477153733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1477153733
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.410517599
Short name T365
Test name
Test status
Simulation time 8456832881 ps
CPU time 20.6 seconds
Started Apr 25 12:37:32 PM PDT 24
Finished Apr 25 12:37:54 PM PDT 24
Peak memory 210408 kb
Host smart-09319de6-6e96-41b8-aff6-0c7623e188fc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410517599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
410517599
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2188385847
Short name T88
Test name
Test status
Simulation time 8219205201 ps
CPU time 88.41 seconds
Started Apr 25 12:37:41 PM PDT 24
Finished Apr 25 12:39:13 PM PDT 24
Peak memory 213884 kb
Host smart-84b53814-7182-4c40-86f6-29fb67b900b5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188385847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2188385847
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3833829764
Short name T73
Test name
Test status
Simulation time 12452548011 ps
CPU time 31.32 seconds
Started Apr 25 12:37:41 PM PDT 24
Finished Apr 25 12:38:15 PM PDT 24
Peak memory 211916 kb
Host smart-151c1fe3-c798-481a-b07a-30cdc40f2bd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833829764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3833829764
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3021753411
Short name T369
Test name
Test status
Simulation time 11016850586 ps
CPU time 31.51 seconds
Started Apr 25 12:37:32 PM PDT 24
Finished Apr 25 12:38:05 PM PDT 24
Peak memory 218012 kb
Host smart-63088b30-0727-4d27-a8cb-96a178ac8488
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021753411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3021753411
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.785259596
Short name T435
Test name
Test status
Simulation time 184259786 ps
CPU time 9.16 seconds
Started Apr 25 12:37:47 PM PDT 24
Finished Apr 25 12:37:59 PM PDT 24
Peak memory 216140 kb
Host smart-21cbd40d-3e09-4e1a-90b9-43b90e9cbd2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785259596 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.785259596
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3318764429
Short name T444
Test name
Test status
Simulation time 2041290810 ps
CPU time 20.05 seconds
Started Apr 25 12:37:36 PM PDT 24
Finished Apr 25 12:37:58 PM PDT 24
Peak memory 210696 kb
Host smart-1a3dc073-cbc3-473d-8706-68406a190d19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318764429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3318764429
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.949806995
Short name T376
Test name
Test status
Simulation time 15638822965 ps
CPU time 126.53 seconds
Started Apr 25 12:37:36 PM PDT 24
Finished Apr 25 12:39:44 PM PDT 24
Peak memory 213784 kb
Host smart-53b1ee3f-4c57-4fad-a1f6-97f7d0547f83
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949806995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.949806995
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2837026824
Short name T103
Test name
Test status
Simulation time 7892839084 ps
CPU time 35.28 seconds
Started Apr 25 12:37:40 PM PDT 24
Finished Apr 25 12:38:17 PM PDT 24
Peak memory 211864 kb
Host smart-dd91968f-28ca-4e76-841c-08ec5024ad94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837026824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2837026824
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.125633961
Short name T440
Test name
Test status
Simulation time 2712282677 ps
CPU time 28.53 seconds
Started Apr 25 12:37:40 PM PDT 24
Finished Apr 25 12:38:11 PM PDT 24
Peak memory 217588 kb
Host smart-0f757454-c1fd-4b6d-8735-b77c4441a2c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125633961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.125633961
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1474092544
Short name T112
Test name
Test status
Simulation time 7134695413 ps
CPU time 93.86 seconds
Started Apr 25 12:37:38 PM PDT 24
Finished Apr 25 12:39:13 PM PDT 24
Peak memory 213148 kb
Host smart-92800ba7-5bca-4390-86fe-49fd63582d66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474092544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1474092544
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4232262080
Short name T367
Test name
Test status
Simulation time 911169401 ps
CPU time 14.51 seconds
Started Apr 25 12:37:45 PM PDT 24
Finished Apr 25 12:38:02 PM PDT 24
Peak memory 213016 kb
Host smart-851d51ca-f465-424f-af58-fba000bd3eaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232262080 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.4232262080
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2336140520
Short name T426
Test name
Test status
Simulation time 2053856664 ps
CPU time 20.45 seconds
Started Apr 25 12:37:43 PM PDT 24
Finished Apr 25 12:38:07 PM PDT 24
Peak memory 211272 kb
Host smart-c4c6ae26-940d-4106-b298-d1a6c878747e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336140520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2336140520
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3457499351
Short name T84
Test name
Test status
Simulation time 695701714 ps
CPU time 38.01 seconds
Started Apr 25 12:37:44 PM PDT 24
Finished Apr 25 12:38:25 PM PDT 24
Peak memory 212872 kb
Host smart-ec4bc5bf-39da-4370-93c4-724f8136ccb2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457499351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3457499351
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.908066328
Short name T428
Test name
Test status
Simulation time 12128039608 ps
CPU time 27.48 seconds
Started Apr 25 12:37:37 PM PDT 24
Finished Apr 25 12:38:06 PM PDT 24
Peak memory 211968 kb
Host smart-000329ec-d41f-4783-90cf-297b0c934a29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908066328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.908066328
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1339592380
Short name T361
Test name
Test status
Simulation time 17689807911 ps
CPU time 32.92 seconds
Started Apr 25 12:37:27 PM PDT 24
Finished Apr 25 12:38:02 PM PDT 24
Peak memory 217196 kb
Host smart-3eed5f9d-62b9-4bd0-8514-75a7715a65f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339592380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1339592380
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1568612126
Short name T64
Test name
Test status
Simulation time 10144199312 ps
CPU time 87.46 seconds
Started Apr 25 12:37:51 PM PDT 24
Finished Apr 25 12:39:21 PM PDT 24
Peak memory 213164 kb
Host smart-4d3200f8-9537-459f-a5af-33a9871c5382
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568612126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1568612126
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.512545194
Short name T404
Test name
Test status
Simulation time 4126313028 ps
CPU time 32.12 seconds
Started Apr 25 12:37:43 PM PDT 24
Finished Apr 25 12:38:18 PM PDT 24
Peak memory 214164 kb
Host smart-accdbb27-f259-4b98-9bf1-217c646f3bed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512545194 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.512545194
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4139521094
Short name T414
Test name
Test status
Simulation time 345934812 ps
CPU time 8.25 seconds
Started Apr 25 12:37:46 PM PDT 24
Finished Apr 25 12:37:58 PM PDT 24
Peak memory 210448 kb
Host smart-d8b42217-7dd6-40c5-b732-558307734e4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139521094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.4139521094
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2943052890
Short name T403
Test name
Test status
Simulation time 38560717291 ps
CPU time 100.44 seconds
Started Apr 25 12:37:41 PM PDT 24
Finished Apr 25 12:39:24 PM PDT 24
Peak memory 213628 kb
Host smart-11a644a6-1642-4757-9b68-1074577c4f73
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943052890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2943052890
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3222776699
Short name T389
Test name
Test status
Simulation time 15624128226 ps
CPU time 31.07 seconds
Started Apr 25 12:37:43 PM PDT 24
Finished Apr 25 12:38:17 PM PDT 24
Peak memory 212004 kb
Host smart-5271ab79-2990-4506-a7cb-c857adae0c7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222776699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3222776699
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.326718964
Short name T434
Test name
Test status
Simulation time 3143955462 ps
CPU time 22.6 seconds
Started Apr 25 12:37:46 PM PDT 24
Finished Apr 25 12:38:12 PM PDT 24
Peak memory 218000 kb
Host smart-a09097f5-5689-4e50-8794-19aa2a3993f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326718964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.326718964
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1797038880
Short name T429
Test name
Test status
Simulation time 3987457316 ps
CPU time 91.81 seconds
Started Apr 25 12:37:43 PM PDT 24
Finished Apr 25 12:39:18 PM PDT 24
Peak memory 211724 kb
Host smart-d528c763-3812-40f7-adc8-fca672e9eb46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797038880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1797038880
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.501162586
Short name T391
Test name
Test status
Simulation time 367089748 ps
CPU time 8.92 seconds
Started Apr 25 12:37:48 PM PDT 24
Finished Apr 25 12:38:00 PM PDT 24
Peak memory 216692 kb
Host smart-811b776b-ca4c-4f58-b2af-5247b562d948
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501162586 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.501162586
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2110476599
Short name T79
Test name
Test status
Simulation time 3392528184 ps
CPU time 17.84 seconds
Started Apr 25 12:37:44 PM PDT 24
Finished Apr 25 12:38:05 PM PDT 24
Peak memory 211080 kb
Host smart-5cbb63de-335b-4256-8f43-ca54b0ba7af6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110476599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2110476599
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1728443887
Short name T438
Test name
Test status
Simulation time 140029803408 ps
CPU time 106.7 seconds
Started Apr 25 12:37:44 PM PDT 24
Finished Apr 25 12:39:34 PM PDT 24
Peak memory 214644 kb
Host smart-f8348ba7-740c-4b01-8fe2-1f349167333e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728443887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1728443887
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3838375341
Short name T447
Test name
Test status
Simulation time 4455443040 ps
CPU time 15.17 seconds
Started Apr 25 12:37:42 PM PDT 24
Finished Apr 25 12:38:01 PM PDT 24
Peak memory 212072 kb
Host smart-196bcd18-9d1b-43d4-93e6-641220d20432
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838375341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3838375341
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2995494433
Short name T458
Test name
Test status
Simulation time 2464444642 ps
CPU time 25.27 seconds
Started Apr 25 12:37:44 PM PDT 24
Finished Apr 25 12:38:12 PM PDT 24
Peak memory 217660 kb
Host smart-bd83c96c-17ae-4eea-ae31-5d659639585f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995494433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2995494433
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.834298069
Short name T115
Test name
Test status
Simulation time 659103995 ps
CPU time 156.42 seconds
Started Apr 25 12:37:45 PM PDT 24
Finished Apr 25 12:40:25 PM PDT 24
Peak memory 213340 kb
Host smart-cc01f3c2-029e-4b7d-be7c-79abf72b039a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834298069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.834298069
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.853217754
Short name T363
Test name
Test status
Simulation time 7726843795 ps
CPU time 30.94 seconds
Started Apr 25 12:37:44 PM PDT 24
Finished Apr 25 12:38:18 PM PDT 24
Peak memory 218740 kb
Host smart-909d638a-a047-4126-9ba8-d9968681c561
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853217754 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.853217754
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.452863409
Short name T411
Test name
Test status
Simulation time 3553395932 ps
CPU time 28.91 seconds
Started Apr 25 12:37:46 PM PDT 24
Finished Apr 25 12:38:18 PM PDT 24
Peak memory 211256 kb
Host smart-d93318ea-352e-4e1c-86c6-8c6435f1e435
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452863409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.452863409
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1014096476
Short name T85
Test name
Test status
Simulation time 23230552012 ps
CPU time 187.12 seconds
Started Apr 25 12:37:44 PM PDT 24
Finished Apr 25 12:40:54 PM PDT 24
Peak memory 214948 kb
Host smart-0cc24b8b-3c37-427f-8f89-762b4b8d466a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014096476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1014096476
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3169156092
Short name T454
Test name
Test status
Simulation time 18271249216 ps
CPU time 33.28 seconds
Started Apr 25 12:37:51 PM PDT 24
Finished Apr 25 12:38:27 PM PDT 24
Peak memory 211552 kb
Host smart-005e419b-a844-4a22-ae4c-06f74d6d2ff7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169156092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3169156092
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1696874643
Short name T441
Test name
Test status
Simulation time 1476989906 ps
CPU time 20.83 seconds
Started Apr 25 12:37:51 PM PDT 24
Finished Apr 25 12:38:14 PM PDT 24
Peak memory 217416 kb
Host smart-5915d245-1f87-4e70-97ba-e06b104f7443
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696874643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1696874643
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2005386159
Short name T117
Test name
Test status
Simulation time 2418255490 ps
CPU time 150.92 seconds
Started Apr 25 12:37:42 PM PDT 24
Finished Apr 25 12:40:16 PM PDT 24
Peak memory 213216 kb
Host smart-0c72f007-6788-4da8-806b-fc34dd2a4e54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005386159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2005386159
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.245665038
Short name T191
Test name
Test status
Simulation time 6866847389 ps
CPU time 28.91 seconds
Started Apr 25 12:41:38 PM PDT 24
Finished Apr 25 12:42:09 PM PDT 24
Peak memory 212392 kb
Host smart-5344dbf5-5021-4d61-8564-3e95c9de0a28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245665038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.245665038
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2519209838
Short name T345
Test name
Test status
Simulation time 58293849153 ps
CPU time 323.08 seconds
Started Apr 25 12:41:10 PM PDT 24
Finished Apr 25 12:46:34 PM PDT 24
Peak memory 228992 kb
Host smart-addaa6b2-c021-49f7-8ac3-97a8be9420ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519209838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2519209838
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4118787461
Short name T160
Test name
Test status
Simulation time 6673938726 ps
CPU time 57.94 seconds
Started Apr 25 12:41:26 PM PDT 24
Finished Apr 25 12:42:24 PM PDT 24
Peak memory 214164 kb
Host smart-094c5777-dd19-45f6-a3cf-c8f00bfa256f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118787461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.4118787461
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3099422705
Short name T133
Test name
Test status
Simulation time 21583396504 ps
CPU time 23.38 seconds
Started Apr 25 12:41:08 PM PDT 24
Finished Apr 25 12:41:32 PM PDT 24
Peak memory 211920 kb
Host smart-53f2ac7d-36ef-48fd-82b4-c63b62a1582b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3099422705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3099422705
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.753620239
Short name T33
Test name
Test status
Simulation time 2169255007 ps
CPU time 127.24 seconds
Started Apr 25 12:41:18 PM PDT 24
Finished Apr 25 12:43:26 PM PDT 24
Peak memory 237664 kb
Host smart-6e931d40-1ab0-4c47-a684-35503dc94982
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753620239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.753620239
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3407879045
Short name T321
Test name
Test status
Simulation time 15121726856 ps
CPU time 48.3 seconds
Started Apr 25 12:41:08 PM PDT 24
Finished Apr 25 12:41:57 PM PDT 24
Peak memory 218152 kb
Host smart-d4023767-8d3a-4487-8afc-1ae3c08a18d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407879045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3407879045
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1361577268
Short name T235
Test name
Test status
Simulation time 15224314850 ps
CPU time 139.74 seconds
Started Apr 25 12:41:07 PM PDT 24
Finished Apr 25 12:43:27 PM PDT 24
Peak memory 220820 kb
Host smart-e0bb1ad0-1ae8-45cb-9b42-d45948f981df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361577268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1361577268
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.685575932
Short name T352
Test name
Test status
Simulation time 8349632898 ps
CPU time 33.31 seconds
Started Apr 25 12:40:53 PM PDT 24
Finished Apr 25 12:41:26 PM PDT 24
Peak memory 211576 kb
Host smart-4fae88b0-554f-4783-8974-f9ccf9b056ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685575932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.685575932
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2115715058
Short name T245
Test name
Test status
Simulation time 148099662283 ps
CPU time 306.55 seconds
Started Apr 25 12:41:04 PM PDT 24
Finished Apr 25 12:46:11 PM PDT 24
Peak memory 237952 kb
Host smart-475684d7-36ed-44c1-a70e-6d412f0f1c1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115715058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2115715058
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.219154812
Short name T310
Test name
Test status
Simulation time 5115923096 ps
CPU time 35.37 seconds
Started Apr 25 12:41:05 PM PDT 24
Finished Apr 25 12:41:41 PM PDT 24
Peak memory 215320 kb
Host smart-e49399a9-c3b7-4fc2-92bf-28ef0d201209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219154812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.219154812
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1991916485
Short name T316
Test name
Test status
Simulation time 12466218673 ps
CPU time 27.59 seconds
Started Apr 25 12:41:04 PM PDT 24
Finished Apr 25 12:41:32 PM PDT 24
Peak memory 213068 kb
Host smart-2cef5757-79b7-427a-8858-c4fdce10ceff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1991916485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1991916485
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1504958087
Short name T230
Test name
Test status
Simulation time 2293464433 ps
CPU time 22.68 seconds
Started Apr 25 12:41:19 PM PDT 24
Finished Apr 25 12:41:42 PM PDT 24
Peak memory 216956 kb
Host smart-5be6d547-030f-4519-939a-b93306c6ca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504958087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1504958087
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2320709174
Short name T319
Test name
Test status
Simulation time 27560932224 ps
CPU time 75.6 seconds
Started Apr 25 12:41:18 PM PDT 24
Finished Apr 25 12:42:34 PM PDT 24
Peak memory 219424 kb
Host smart-45d32e82-c7c7-4b15-8b44-daf1494f1e9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320709174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2320709174
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3533506117
Short name T185
Test name
Test status
Simulation time 3997362693 ps
CPU time 33.55 seconds
Started Apr 25 12:41:24 PM PDT 24
Finished Apr 25 12:41:58 PM PDT 24
Peak memory 212032 kb
Host smart-59910c7c-c949-4dca-9840-d9bd097d16a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533506117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3533506117
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.993544687
Short name T358
Test name
Test status
Simulation time 130278972249 ps
CPU time 487.6 seconds
Started Apr 25 12:41:20 PM PDT 24
Finished Apr 25 12:49:29 PM PDT 24
Peak memory 229952 kb
Host smart-7d7adece-e2e1-4087-ba1e-d328da1505bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993544687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.993544687
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2356294308
Short name T144
Test name
Test status
Simulation time 3074102714 ps
CPU time 14.88 seconds
Started Apr 25 12:41:39 PM PDT 24
Finished Apr 25 12:41:56 PM PDT 24
Peak memory 212840 kb
Host smart-8fda5473-c7fa-457a-bb49-d4cd5e4c8c29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2356294308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2356294308
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.329221125
Short name T241
Test name
Test status
Simulation time 13953980610 ps
CPU time 63 seconds
Started Apr 25 12:41:48 PM PDT 24
Finished Apr 25 12:42:53 PM PDT 24
Peak memory 218336 kb
Host smart-45e6a40b-3233-45ee-a488-527fd27f4013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329221125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.329221125
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4146103095
Short name T274
Test name
Test status
Simulation time 12548113803 ps
CPU time 43.49 seconds
Started Apr 25 12:41:28 PM PDT 24
Finished Apr 25 12:42:12 PM PDT 24
Peak memory 218108 kb
Host smart-3c86ec36-f573-4952-8afc-384d88e20256
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146103095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.4146103095
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.109870706
Short name T268
Test name
Test status
Simulation time 332077449 ps
CPU time 8.41 seconds
Started Apr 25 12:41:29 PM PDT 24
Finished Apr 25 12:41:37 PM PDT 24
Peak memory 211540 kb
Host smart-16ac0315-9f13-4ae2-a0a0-8f565ec12e56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109870706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.109870706
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1130477556
Short name T277
Test name
Test status
Simulation time 939248092 ps
CPU time 22.16 seconds
Started Apr 25 12:41:30 PM PDT 24
Finished Apr 25 12:41:53 PM PDT 24
Peak memory 212912 kb
Host smart-51448e0d-32db-404e-bd98-1cafcddc2d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130477556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1130477556
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.387223604
Short name T225
Test name
Test status
Simulation time 13303935950 ps
CPU time 28.61 seconds
Started Apr 25 12:41:21 PM PDT 24
Finished Apr 25 12:41:50 PM PDT 24
Peak memory 213116 kb
Host smart-80d1c2bc-82aa-4c93-9d46-e397d83739de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=387223604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.387223604
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3463146873
Short name T194
Test name
Test status
Simulation time 3935654701 ps
CPU time 44.22 seconds
Started Apr 25 12:41:27 PM PDT 24
Finished Apr 25 12:42:12 PM PDT 24
Peak memory 213848 kb
Host smart-bdee5204-66e9-455c-b392-fac3ded9f9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463146873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3463146873
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.299697894
Short name T179
Test name
Test status
Simulation time 4279459086 ps
CPU time 48.85 seconds
Started Apr 25 12:41:36 PM PDT 24
Finished Apr 25 12:42:25 PM PDT 24
Peak memory 218740 kb
Host smart-8c292eeb-406e-4b3c-897d-615e2cd5a87d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299697894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.299697894
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3715253962
Short name T68
Test name
Test status
Simulation time 8176420372 ps
CPU time 17.03 seconds
Started Apr 25 12:41:35 PM PDT 24
Finished Apr 25 12:41:53 PM PDT 24
Peak memory 211588 kb
Host smart-7f2db51b-433a-4853-bb23-8102630a70bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715253962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3715253962
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.192807764
Short name T48
Test name
Test status
Simulation time 101563850344 ps
CPU time 342.71 seconds
Started Apr 25 12:41:21 PM PDT 24
Finished Apr 25 12:47:05 PM PDT 24
Peak memory 238136 kb
Host smart-cd74331f-c292-4687-9ef6-d4a7ac3237a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192807764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.192807764
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1768505444
Short name T295
Test name
Test status
Simulation time 675482976 ps
CPU time 18.71 seconds
Started Apr 25 12:41:30 PM PDT 24
Finished Apr 25 12:41:49 PM PDT 24
Peak memory 214864 kb
Host smart-0a41a30d-29a6-4730-b509-d2e3d62e0337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768505444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1768505444
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1250526669
Short name T327
Test name
Test status
Simulation time 3376886507 ps
CPU time 29.06 seconds
Started Apr 25 12:41:21 PM PDT 24
Finished Apr 25 12:41:51 PM PDT 24
Peak memory 211772 kb
Host smart-6a2f076a-e4a5-4566-8277-ac794e3b77d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1250526669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1250526669
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.952557366
Short name T166
Test name
Test status
Simulation time 10994596367 ps
CPU time 36.1 seconds
Started Apr 25 12:41:28 PM PDT 24
Finished Apr 25 12:42:04 PM PDT 24
Peak memory 218660 kb
Host smart-264c6f53-626b-4364-a5a0-4b4498a65c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952557366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.952557366
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2165461598
Short name T41
Test name
Test status
Simulation time 548748131 ps
CPU time 37.72 seconds
Started Apr 25 12:41:29 PM PDT 24
Finished Apr 25 12:42:08 PM PDT 24
Peak memory 219508 kb
Host smart-98b3a960-3450-4cb0-991d-539da475d61f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165461598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2165461598
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3281226648
Short name T141
Test name
Test status
Simulation time 172781625 ps
CPU time 8.2 seconds
Started Apr 25 12:41:32 PM PDT 24
Finished Apr 25 12:41:41 PM PDT 24
Peak memory 211496 kb
Host smart-3b29339f-2256-4466-a465-423aeb8f744f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281226648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3281226648
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3017471896
Short name T311
Test name
Test status
Simulation time 58220672573 ps
CPU time 353.43 seconds
Started Apr 25 12:41:20 PM PDT 24
Finished Apr 25 12:47:15 PM PDT 24
Peak memory 240512 kb
Host smart-460a57fd-6b90-4507-9e49-29dc4d9a7246
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017471896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3017471896
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3555080663
Short name T276
Test name
Test status
Simulation time 3361070874 ps
CPU time 30.13 seconds
Started Apr 25 12:41:20 PM PDT 24
Finished Apr 25 12:41:51 PM PDT 24
Peak memory 215592 kb
Host smart-d115dff0-c33a-4bfb-94d6-f14f8dfb251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555080663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3555080663
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1405190008
Short name T271
Test name
Test status
Simulation time 4229239120 ps
CPU time 13.48 seconds
Started Apr 25 12:41:15 PM PDT 24
Finished Apr 25 12:41:29 PM PDT 24
Peak memory 211924 kb
Host smart-c3200677-eabb-4209-b3e1-7ba8e17fba8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1405190008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1405190008
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.840723193
Short name T238
Test name
Test status
Simulation time 4284165934 ps
CPU time 33.64 seconds
Started Apr 25 12:41:32 PM PDT 24
Finished Apr 25 12:42:07 PM PDT 24
Peak memory 218060 kb
Host smart-b1c31a06-2cb4-44a7-9ab4-3fc6570dbc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840723193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.840723193
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1527332770
Short name T197
Test name
Test status
Simulation time 30375788318 ps
CPU time 105.95 seconds
Started Apr 25 12:41:24 PM PDT 24
Finished Apr 25 12:43:10 PM PDT 24
Peak memory 227856 kb
Host smart-c54deecc-3132-41e9-ba4c-ef094c76329d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527332770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1527332770
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.352683433
Short name T349
Test name
Test status
Simulation time 11411139132 ps
CPU time 25.51 seconds
Started Apr 25 12:41:40 PM PDT 24
Finished Apr 25 12:42:08 PM PDT 24
Peak memory 211600 kb
Host smart-48fd042d-730d-4d27-84f3-6752cd833402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352683433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.352683433
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3169572877
Short name T219
Test name
Test status
Simulation time 327068395187 ps
CPU time 313.3 seconds
Started Apr 25 12:41:37 PM PDT 24
Finished Apr 25 12:46:52 PM PDT 24
Peak memory 240936 kb
Host smart-728ba4de-6ecb-42e5-a8d1-b6194b6ee0c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169572877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3169572877
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2200268439
Short name T199
Test name
Test status
Simulation time 24000200293 ps
CPU time 53.51 seconds
Started Apr 25 12:41:40 PM PDT 24
Finished Apr 25 12:42:36 PM PDT 24
Peak memory 214100 kb
Host smart-8674c2db-530d-4cc6-98cf-06bcd71d4f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200268439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2200268439
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1480886508
Short name T299
Test name
Test status
Simulation time 17855790406 ps
CPU time 32.27 seconds
Started Apr 25 12:41:30 PM PDT 24
Finished Apr 25 12:42:03 PM PDT 24
Peak memory 212028 kb
Host smart-af8b4fdc-d366-4e30-a510-454b73df7c25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1480886508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1480886508
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.4097800409
Short name T184
Test name
Test status
Simulation time 6435828130 ps
CPU time 54.84 seconds
Started Apr 25 12:41:30 PM PDT 24
Finished Apr 25 12:42:25 PM PDT 24
Peak memory 217852 kb
Host smart-9f167bc5-9e5a-4994-ae59-12294303aa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097800409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.4097800409
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3333148889
Short name T331
Test name
Test status
Simulation time 6856314268 ps
CPU time 61.55 seconds
Started Apr 25 12:41:39 PM PDT 24
Finished Apr 25 12:42:42 PM PDT 24
Peak memory 219656 kb
Host smart-93b5dc6a-d890-45a1-88e8-0d9df6f906aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333148889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3333148889
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3788738768
Short name T284
Test name
Test status
Simulation time 170897318 ps
CPU time 8.54 seconds
Started Apr 25 12:41:41 PM PDT 24
Finished Apr 25 12:41:52 PM PDT 24
Peak memory 211596 kb
Host smart-ee0b6bbe-f795-4103-b927-ff4d59bcfce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788738768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3788738768
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.598367588
Short name T163
Test name
Test status
Simulation time 112512675547 ps
CPU time 547.39 seconds
Started Apr 25 12:41:37 PM PDT 24
Finished Apr 25 12:50:45 PM PDT 24
Peak memory 238144 kb
Host smart-b4cb440c-5f0b-4820-a253-9dc9df4300cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598367588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.598367588
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2825393118
Short name T236
Test name
Test status
Simulation time 64320541240 ps
CPU time 65.31 seconds
Started Apr 25 12:41:37 PM PDT 24
Finished Apr 25 12:42:44 PM PDT 24
Peak memory 214288 kb
Host smart-a4b14049-597f-4c32-9a80-8761afca4f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825393118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2825393118
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.577390952
Short name T214
Test name
Test status
Simulation time 1356078327 ps
CPU time 12.42 seconds
Started Apr 25 12:41:39 PM PDT 24
Finished Apr 25 12:41:54 PM PDT 24
Peak memory 211496 kb
Host smart-642081c1-a7d0-473f-bbbc-c05ed55d5a7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=577390952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.577390952
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.949363595
Short name T354
Test name
Test status
Simulation time 11953064748 ps
CPU time 61.03 seconds
Started Apr 25 12:41:31 PM PDT 24
Finished Apr 25 12:42:32 PM PDT 24
Peak memory 217712 kb
Host smart-70793cbe-9028-451b-8b1e-9ba13f3439b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949363595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.949363595
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.568715727
Short name T57
Test name
Test status
Simulation time 5676395548 ps
CPU time 80.17 seconds
Started Apr 25 12:41:42 PM PDT 24
Finished Apr 25 12:43:05 PM PDT 24
Peak memory 221244 kb
Host smart-7914bc25-5b5d-4d2a-be3d-46fab8192815
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568715727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.568715727
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1809207739
Short name T188
Test name
Test status
Simulation time 3551939889 ps
CPU time 28.8 seconds
Started Apr 25 12:41:42 PM PDT 24
Finished Apr 25 12:42:14 PM PDT 24
Peak memory 212172 kb
Host smart-fd4fe2a6-cd88-49eb-9f2d-7899469ef78f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809207739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1809207739
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.4000218069
Short name T27
Test name
Test status
Simulation time 244683947875 ps
CPU time 628 seconds
Started Apr 25 12:41:44 PM PDT 24
Finished Apr 25 12:52:15 PM PDT 24
Peak memory 241040 kb
Host smart-ec0f0967-4852-4f43-82cb-06a2032e9300
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000218069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.4000218069
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1818496484
Short name T132
Test name
Test status
Simulation time 7743308156 ps
CPU time 65.57 seconds
Started Apr 25 12:41:56 PM PDT 24
Finished Apr 25 12:43:04 PM PDT 24
Peak memory 215260 kb
Host smart-67ce2678-b61b-4e6a-9975-3d8eff65ed2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818496484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1818496484
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.995445944
Short name T231
Test name
Test status
Simulation time 3005185914 ps
CPU time 27 seconds
Started Apr 25 12:41:28 PM PDT 24
Finished Apr 25 12:41:55 PM PDT 24
Peak memory 212540 kb
Host smart-645ed395-9353-4b32-8d03-bbd2ca52e1fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=995445944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.995445944
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1374623019
Short name T140
Test name
Test status
Simulation time 6474278165 ps
CPU time 68.7 seconds
Started Apr 25 12:41:41 PM PDT 24
Finished Apr 25 12:42:51 PM PDT 24
Peak memory 218196 kb
Host smart-c5244ce6-9b8b-43ed-82f7-9040a7774ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374623019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1374623019
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.4128069814
Short name T122
Test name
Test status
Simulation time 6250251627 ps
CPU time 67.16 seconds
Started Apr 25 12:41:44 PM PDT 24
Finished Apr 25 12:42:53 PM PDT 24
Peak memory 219040 kb
Host smart-f89deb2e-5b4c-4bdc-948b-406013422b9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128069814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.4128069814
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1249061805
Short name T168
Test name
Test status
Simulation time 14336389705 ps
CPU time 26.08 seconds
Started Apr 25 12:41:46 PM PDT 24
Finished Apr 25 12:42:14 PM PDT 24
Peak memory 211612 kb
Host smart-d3c4882c-65e7-4ae0-90a2-7a7157caf7a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249061805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1249061805
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2606794425
Short name T31
Test name
Test status
Simulation time 11664166934 ps
CPU time 218.41 seconds
Started Apr 25 12:41:46 PM PDT 24
Finished Apr 25 12:45:26 PM PDT 24
Peak memory 240516 kb
Host smart-5ca32480-b21d-40e6-a844-728cbd9b9daf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606794425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2606794425
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.606313930
Short name T211
Test name
Test status
Simulation time 3442872656 ps
CPU time 41.49 seconds
Started Apr 25 12:41:38 PM PDT 24
Finished Apr 25 12:42:21 PM PDT 24
Peak memory 213968 kb
Host smart-e499d6d6-4df3-4378-97f6-5af0d02428ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606313930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.606313930
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3771379433
Short name T9
Test name
Test status
Simulation time 908801519 ps
CPU time 12.14 seconds
Started Apr 25 12:41:40 PM PDT 24
Finished Apr 25 12:41:54 PM PDT 24
Peak memory 211480 kb
Host smart-7bad911a-eebe-4ad9-b282-72ce62a80588
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3771379433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3771379433
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1833006474
Short name T221
Test name
Test status
Simulation time 15029347033 ps
CPU time 57.84 seconds
Started Apr 25 12:41:42 PM PDT 24
Finished Apr 25 12:42:43 PM PDT 24
Peak memory 217476 kb
Host smart-60be2bea-f414-4f91-9775-98f0dd3ec669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833006474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1833006474
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1208002789
Short name T174
Test name
Test status
Simulation time 5855275972 ps
CPU time 25.02 seconds
Started Apr 25 12:41:39 PM PDT 24
Finished Apr 25 12:42:05 PM PDT 24
Peak memory 212448 kb
Host smart-c9c48a2d-a58b-4ab3-a5c4-7d6e0435a31e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208002789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1208002789
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.340906857
Short name T328
Test name
Test status
Simulation time 73912001420 ps
CPU time 414.01 seconds
Started Apr 25 12:41:38 PM PDT 24
Finished Apr 25 12:48:33 PM PDT 24
Peak memory 224852 kb
Host smart-9a4019fc-a352-486d-ae87-760a38fd8693
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340906857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.340906857
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3274371513
Short name T145
Test name
Test status
Simulation time 7159937657 ps
CPU time 59.65 seconds
Started Apr 25 12:41:35 PM PDT 24
Finished Apr 25 12:42:35 PM PDT 24
Peak memory 215400 kb
Host smart-2b572731-69ef-407b-ae27-6736a7fe2c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274371513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3274371513
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2376130742
Short name T167
Test name
Test status
Simulation time 5528478768 ps
CPU time 18.82 seconds
Started Apr 25 12:41:37 PM PDT 24
Finished Apr 25 12:41:56 PM PDT 24
Peak memory 211964 kb
Host smart-041dcfb9-2a11-4ce7-b97b-4ab4e996d5ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2376130742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2376130742
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.249817603
Short name T123
Test name
Test status
Simulation time 13842036994 ps
CPU time 45.72 seconds
Started Apr 25 12:41:34 PM PDT 24
Finished Apr 25 12:42:21 PM PDT 24
Peak memory 218748 kb
Host smart-4ee0c1ac-028c-4839-a070-4a62e6f3335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249817603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.249817603
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3886593143
Short name T5
Test name
Test status
Simulation time 13640897499 ps
CPU time 101.93 seconds
Started Apr 25 12:41:42 PM PDT 24
Finished Apr 25 12:43:26 PM PDT 24
Peak memory 219628 kb
Host smart-c5d89474-8d20-4090-90ef-459846535e52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886593143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3886593143
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2134821760
Short name T296
Test name
Test status
Simulation time 2059661215 ps
CPU time 12.16 seconds
Started Apr 25 12:41:41 PM PDT 24
Finished Apr 25 12:41:56 PM PDT 24
Peak memory 211556 kb
Host smart-390b78fb-d3dc-4f64-aefb-e15d5d93ae7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134821760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2134821760
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2495770338
Short name T47
Test name
Test status
Simulation time 285027112899 ps
CPU time 526.53 seconds
Started Apr 25 12:41:39 PM PDT 24
Finished Apr 25 12:50:28 PM PDT 24
Peak memory 225620 kb
Host smart-db7fceb5-7107-4b5d-8d01-0bf31bf37d3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495770338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2495770338
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2945044670
Short name T285
Test name
Test status
Simulation time 677881238 ps
CPU time 18.99 seconds
Started Apr 25 12:41:51 PM PDT 24
Finished Apr 25 12:42:12 PM PDT 24
Peak memory 216740 kb
Host smart-7e10edac-81a9-4e02-90de-61c2a6e73fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945044670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2945044670
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4208194096
Short name T302
Test name
Test status
Simulation time 185591414 ps
CPU time 10.78 seconds
Started Apr 25 12:41:26 PM PDT 24
Finished Apr 25 12:41:38 PM PDT 24
Peak memory 212468 kb
Host smart-bafd5ff6-340f-4682-81f8-ca3b41fb0561
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4208194096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4208194096
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.618989450
Short name T239
Test name
Test status
Simulation time 9206143440 ps
CPU time 52.15 seconds
Started Apr 25 12:41:27 PM PDT 24
Finished Apr 25 12:42:20 PM PDT 24
Peak memory 218664 kb
Host smart-a12a9e12-ca6b-49f4-adc6-4ba863a43d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618989450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.618989450
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3200927572
Short name T150
Test name
Test status
Simulation time 2191809283 ps
CPU time 30.56 seconds
Started Apr 25 12:41:29 PM PDT 24
Finished Apr 25 12:42:00 PM PDT 24
Peak memory 219612 kb
Host smart-d5699158-870a-42ba-89d4-6b15da3f4494
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200927572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3200927572
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3098417542
Short name T148
Test name
Test status
Simulation time 4690999614 ps
CPU time 29.46 seconds
Started Apr 25 12:41:00 PM PDT 24
Finished Apr 25 12:41:30 PM PDT 24
Peak memory 212440 kb
Host smart-c10c1222-e8b5-483c-babb-c1e21ffce878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098417542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3098417542
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2955753485
Short name T355
Test name
Test status
Simulation time 35537192358 ps
CPU time 363.12 seconds
Started Apr 25 12:41:11 PM PDT 24
Finished Apr 25 12:47:15 PM PDT 24
Peak memory 237924 kb
Host smart-061ec41e-b5b0-41e2-a566-ff15429290eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955753485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2955753485
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.604509668
Short name T286
Test name
Test status
Simulation time 61472295667 ps
CPU time 35.81 seconds
Started Apr 25 12:41:00 PM PDT 24
Finished Apr 25 12:41:36 PM PDT 24
Peak memory 211600 kb
Host smart-16096cd2-43dc-4c52-b3ab-9b40cc1f55a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=604509668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.604509668
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.260752505
Short name T32
Test name
Test status
Simulation time 1614020848 ps
CPU time 116.91 seconds
Started Apr 25 12:41:14 PM PDT 24
Finished Apr 25 12:43:12 PM PDT 24
Peak memory 237652 kb
Host smart-7f61682b-7388-4953-8f76-5ad4255f85a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260752505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.260752505
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1405271987
Short name T280
Test name
Test status
Simulation time 1066162231 ps
CPU time 23.85 seconds
Started Apr 25 12:41:18 PM PDT 24
Finished Apr 25 12:41:43 PM PDT 24
Peak memory 215396 kb
Host smart-48287e8d-f74e-451f-9270-05c41b49f4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405271987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1405271987
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2526018169
Short name T187
Test name
Test status
Simulation time 5925986526 ps
CPU time 57.28 seconds
Started Apr 25 12:41:12 PM PDT 24
Finished Apr 25 12:42:10 PM PDT 24
Peak memory 218964 kb
Host smart-af774d7a-613a-4f12-843d-7eac8e653e87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526018169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2526018169
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1244357303
Short name T193
Test name
Test status
Simulation time 14200434192 ps
CPU time 29.4 seconds
Started Apr 25 12:41:48 PM PDT 24
Finished Apr 25 12:42:19 PM PDT 24
Peak memory 212364 kb
Host smart-4d139a77-c0da-46b5-abca-3a56fb23b2bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244357303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1244357303
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3088800538
Short name T320
Test name
Test status
Simulation time 597061974150 ps
CPU time 451.21 seconds
Started Apr 25 12:41:27 PM PDT 24
Finished Apr 25 12:48:59 PM PDT 24
Peak memory 217392 kb
Host smart-541e8c45-dbe8-4686-b077-357e696842d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088800538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3088800538
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3185606689
Short name T136
Test name
Test status
Simulation time 26542479565 ps
CPU time 53.64 seconds
Started Apr 25 12:41:36 PM PDT 24
Finished Apr 25 12:42:30 PM PDT 24
Peak memory 214304 kb
Host smart-da6e63d7-4b25-4538-9e4f-88ff5ccf8c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185606689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3185606689
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2126432633
Short name T10
Test name
Test status
Simulation time 1204570042 ps
CPU time 18.42 seconds
Started Apr 25 12:41:37 PM PDT 24
Finished Apr 25 12:41:57 PM PDT 24
Peak memory 211484 kb
Host smart-e77f7fcb-4d05-4883-8092-6ca03bb48c67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2126432633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2126432633
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.654990054
Short name T313
Test name
Test status
Simulation time 16380037619 ps
CPU time 65.41 seconds
Started Apr 25 12:41:48 PM PDT 24
Finished Apr 25 12:43:05 PM PDT 24
Peak memory 214596 kb
Host smart-2c7f0b51-95a9-492c-b932-55d45587e2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654990054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.654990054
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.983020788
Short name T288
Test name
Test status
Simulation time 2228150907 ps
CPU time 33.98 seconds
Started Apr 25 12:41:33 PM PDT 24
Finished Apr 25 12:42:08 PM PDT 24
Peak memory 216436 kb
Host smart-f4dea982-9b65-4d0a-8652-d8e36f030ac5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983020788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.983020788
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3245376951
Short name T301
Test name
Test status
Simulation time 5501350531 ps
CPU time 24.53 seconds
Started Apr 25 12:41:43 PM PDT 24
Finished Apr 25 12:42:10 PM PDT 24
Peak memory 212376 kb
Host smart-399fa36b-c2d5-4b33-b0b0-770b5007c942
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245376951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3245376951
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1840782217
Short name T342
Test name
Test status
Simulation time 59479805697 ps
CPU time 335.01 seconds
Started Apr 25 12:41:50 PM PDT 24
Finished Apr 25 12:47:28 PM PDT 24
Peak memory 224848 kb
Host smart-c5b552f9-a9a9-4007-9146-61294883d00b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840782217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1840782217
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4280756074
Short name T165
Test name
Test status
Simulation time 3843203736 ps
CPU time 43.67 seconds
Started Apr 25 12:41:35 PM PDT 24
Finished Apr 25 12:42:19 PM PDT 24
Peak memory 215004 kb
Host smart-660e5a91-44c3-48f8-b585-d37d6b96f682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280756074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4280756074
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.448530329
Short name T222
Test name
Test status
Simulation time 4439294117 ps
CPU time 34.08 seconds
Started Apr 25 12:41:42 PM PDT 24
Finished Apr 25 12:42:19 PM PDT 24
Peak memory 211576 kb
Host smart-7128934e-d230-49d7-903a-bc01ac249b95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448530329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.448530329
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1923357284
Short name T99
Test name
Test status
Simulation time 27670855207 ps
CPU time 58.5 seconds
Started Apr 25 12:41:44 PM PDT 24
Finished Apr 25 12:42:45 PM PDT 24
Peak memory 218556 kb
Host smart-f9d387c5-b003-4f6a-857a-50c780e16e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923357284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1923357284
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2787530040
Short name T81
Test name
Test status
Simulation time 1359792360 ps
CPU time 44.37 seconds
Started Apr 25 12:41:47 PM PDT 24
Finished Apr 25 12:42:33 PM PDT 24
Peak memory 219544 kb
Host smart-7974843f-4134-43e0-b5eb-94f034197539
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787530040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2787530040
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2483202487
Short name T269
Test name
Test status
Simulation time 2638213265 ps
CPU time 23.63 seconds
Started Apr 25 12:41:38 PM PDT 24
Finished Apr 25 12:42:03 PM PDT 24
Peak memory 212124 kb
Host smart-bb4cb28a-a17d-4d09-90ef-2f00306eb4f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483202487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2483202487
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4076181638
Short name T306
Test name
Test status
Simulation time 46417125730 ps
CPU time 472.36 seconds
Started Apr 25 12:41:37 PM PDT 24
Finished Apr 25 12:49:31 PM PDT 24
Peak memory 240548 kb
Host smart-203813c8-a8ae-4e32-973a-14233fd3eec9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076181638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.4076181638
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.4163709224
Short name T100
Test name
Test status
Simulation time 3320436923 ps
CPU time 28.88 seconds
Started Apr 25 12:41:49 PM PDT 24
Finished Apr 25 12:42:21 PM PDT 24
Peak memory 211568 kb
Host smart-34251141-dbfb-4354-acdc-550452e2c904
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4163709224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.4163709224
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2993229533
Short name T304
Test name
Test status
Simulation time 18974172642 ps
CPU time 48.9 seconds
Started Apr 25 12:41:53 PM PDT 24
Finished Apr 25 12:42:44 PM PDT 24
Peak memory 217824 kb
Host smart-8ce5ff9c-ebb8-4a6a-8b3c-0bbdc6d980e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993229533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2993229533
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.229519987
Short name T307
Test name
Test status
Simulation time 14434802226 ps
CPU time 127.8 seconds
Started Apr 25 12:41:39 PM PDT 24
Finished Apr 25 12:43:48 PM PDT 24
Peak memory 221380 kb
Host smart-7e30e4c8-78e2-4831-b223-719e9c9c72db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229519987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.229519987
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1292432607
Short name T53
Test name
Test status
Simulation time 47131676214 ps
CPU time 1025.03 seconds
Started Apr 25 12:41:46 PM PDT 24
Finished Apr 25 12:58:53 PM PDT 24
Peak memory 236172 kb
Host smart-f02ddcbc-b63f-41d7-a6b1-fd0b6af98e33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292432607 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.1292432607
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2068463725
Short name T208
Test name
Test status
Simulation time 6144444695 ps
CPU time 188.49 seconds
Started Apr 25 12:41:49 PM PDT 24
Finished Apr 25 12:45:00 PM PDT 24
Peak memory 225972 kb
Host smart-3a01d08b-6a3e-4a30-9ec1-96157ff1864b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068463725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2068463725
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2753142487
Short name T20
Test name
Test status
Simulation time 332252792 ps
CPU time 18.75 seconds
Started Apr 25 12:41:38 PM PDT 24
Finished Apr 25 12:41:59 PM PDT 24
Peak memory 214796 kb
Host smart-b75ed293-e1da-4c5f-af4c-a38243338b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753142487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2753142487
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.619014750
Short name T108
Test name
Test status
Simulation time 510450418 ps
CPU time 10.21 seconds
Started Apr 25 12:41:43 PM PDT 24
Finished Apr 25 12:41:56 PM PDT 24
Peak memory 212544 kb
Host smart-1aa91f71-4f72-4ffa-a048-a524938382b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=619014750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.619014750
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.390956421
Short name T314
Test name
Test status
Simulation time 7718772428 ps
CPU time 41.27 seconds
Started Apr 25 12:41:43 PM PDT 24
Finished Apr 25 12:42:27 PM PDT 24
Peak memory 217856 kb
Host smart-4f5b7f00-ef65-4e2a-b487-c2a1a5bb2353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390956421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.390956421
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2230494794
Short name T326
Test name
Test status
Simulation time 734079312 ps
CPU time 43.83 seconds
Started Apr 25 12:41:43 PM PDT 24
Finished Apr 25 12:42:29 PM PDT 24
Peak memory 219620 kb
Host smart-6fcf57af-bb84-4193-9a86-f842f9c572b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230494794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2230494794
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1580775855
Short name T55
Test name
Test status
Simulation time 448265171700 ps
CPU time 2828.13 seconds
Started Apr 25 12:41:43 PM PDT 24
Finished Apr 25 01:28:54 PM PDT 24
Peak memory 252508 kb
Host smart-b497c798-229c-41c9-aa00-d5fba04e2c1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580775855 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1580775855
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.927277952
Short name T202
Test name
Test status
Simulation time 4286298850 ps
CPU time 20.26 seconds
Started Apr 25 12:41:54 PM PDT 24
Finished Apr 25 12:42:17 PM PDT 24
Peak memory 211588 kb
Host smart-10198510-e8e4-4175-aea7-7646743bb91b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927277952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.927277952
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.328603158
Short name T330
Test name
Test status
Simulation time 68406941857 ps
CPU time 687.33 seconds
Started Apr 25 12:41:44 PM PDT 24
Finished Apr 25 12:53:14 PM PDT 24
Peak memory 234476 kb
Host smart-021c951f-8a37-4cc9-b115-d020d205909d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328603158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.328603158
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2209398476
Short name T192
Test name
Test status
Simulation time 8566557641 ps
CPU time 69.4 seconds
Started Apr 25 12:41:51 PM PDT 24
Finished Apr 25 12:43:02 PM PDT 24
Peak memory 215520 kb
Host smart-48f3e975-6350-442a-b5df-81b4680526e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209398476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2209398476
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1760241618
Short name T142
Test name
Test status
Simulation time 2631078368 ps
CPU time 25.47 seconds
Started Apr 25 12:41:48 PM PDT 24
Finished Apr 25 12:42:15 PM PDT 24
Peak memory 212612 kb
Host smart-4183110e-3b22-4997-8e83-1baeca0e4b92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1760241618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1760241618
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1550701201
Short name T262
Test name
Test status
Simulation time 7515859303 ps
CPU time 60.21 seconds
Started Apr 25 12:41:48 PM PDT 24
Finished Apr 25 12:42:50 PM PDT 24
Peak memory 214820 kb
Host smart-b1f741f2-ea2a-4828-a0f0-b3633d23ff27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550701201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1550701201
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.894697687
Short name T157
Test name
Test status
Simulation time 9271006156 ps
CPU time 77.86 seconds
Started Apr 25 12:41:42 PM PDT 24
Finished Apr 25 12:43:02 PM PDT 24
Peak memory 220668 kb
Host smart-75e64ac7-c539-44cf-986f-7efda5584cb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894697687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.894697687
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2326716895
Short name T67
Test name
Test status
Simulation time 1031203082 ps
CPU time 10 seconds
Started Apr 25 12:41:55 PM PDT 24
Finished Apr 25 12:42:07 PM PDT 24
Peak memory 211496 kb
Host smart-d38fd7cf-6fd1-4cc7-9ad3-2b6d93668c11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326716895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2326716895
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3442641679
Short name T120
Test name
Test status
Simulation time 157260267761 ps
CPU time 400.98 seconds
Started Apr 25 12:41:41 PM PDT 24
Finished Apr 25 12:48:24 PM PDT 24
Peak memory 237488 kb
Host smart-f98f0dc2-9d6b-4d92-909c-ee2ba9f8a567
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442641679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3442641679
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1220795363
Short name T26
Test name
Test status
Simulation time 22229677568 ps
CPU time 52.9 seconds
Started Apr 25 12:41:50 PM PDT 24
Finished Apr 25 12:42:45 PM PDT 24
Peak memory 214176 kb
Host smart-0239fcf2-0274-44fb-bfe6-f65010e7dcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220795363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1220795363
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1223905367
Short name T251
Test name
Test status
Simulation time 7906836702 ps
CPU time 21.96 seconds
Started Apr 25 12:41:43 PM PDT 24
Finished Apr 25 12:42:08 PM PDT 24
Peak memory 213136 kb
Host smart-e5ff8326-cc36-4739-9196-2b22920858bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223905367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1223905367
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2640939817
Short name T51
Test name
Test status
Simulation time 708606703 ps
CPU time 19.56 seconds
Started Apr 25 12:41:36 PM PDT 24
Finished Apr 25 12:41:57 PM PDT 24
Peak memory 217200 kb
Host smart-192677cc-aff1-4141-ad18-d54117775ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640939817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2640939817
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.893853766
Short name T259
Test name
Test status
Simulation time 13188223061 ps
CPU time 118.64 seconds
Started Apr 25 12:41:39 PM PDT 24
Finished Apr 25 12:43:40 PM PDT 24
Peak memory 220084 kb
Host smart-d7fc5773-a1dc-46a7-9d39-acc33eda7e22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893853766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.893853766
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.4060573607
Short name T129
Test name
Test status
Simulation time 2332886964 ps
CPU time 21.48 seconds
Started Apr 25 12:41:51 PM PDT 24
Finished Apr 25 12:42:15 PM PDT 24
Peak memory 212244 kb
Host smart-8abef4cc-a5a3-41ca-bd89-a55730b79cbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060573607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.4060573607
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2666753490
Short name T308
Test name
Test status
Simulation time 7267612548 ps
CPU time 190.71 seconds
Started Apr 25 12:41:51 PM PDT 24
Finished Apr 25 12:45:04 PM PDT 24
Peak memory 238024 kb
Host smart-842f61bd-a7e0-4c70-9a63-9f3b43393df9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666753490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2666753490
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4055829291
Short name T21
Test name
Test status
Simulation time 3536671714 ps
CPU time 41.58 seconds
Started Apr 25 12:41:37 PM PDT 24
Finished Apr 25 12:42:20 PM PDT 24
Peak memory 214976 kb
Host smart-d158b44e-bcbb-4756-9367-c1b8c17d9b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055829291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4055829291
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.578328926
Short name T329
Test name
Test status
Simulation time 596048173 ps
CPU time 10.03 seconds
Started Apr 25 12:41:39 PM PDT 24
Finished Apr 25 12:41:52 PM PDT 24
Peak memory 212476 kb
Host smart-c34fda65-941f-4965-8bdd-e645453f6826
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=578328926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.578328926
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3180659840
Short name T220
Test name
Test status
Simulation time 1881919029 ps
CPU time 31.69 seconds
Started Apr 25 12:41:34 PM PDT 24
Finished Apr 25 12:42:07 PM PDT 24
Peak memory 215416 kb
Host smart-5fdf81b6-b517-4686-8211-e2c1ecb673cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180659840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3180659840
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1369729877
Short name T343
Test name
Test status
Simulation time 8032053298 ps
CPU time 93.34 seconds
Started Apr 25 12:41:33 PM PDT 24
Finished Apr 25 12:43:07 PM PDT 24
Peak memory 219592 kb
Host smart-c5233b73-a51d-41eb-923b-274db675d5ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369729877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1369729877
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1557953843
Short name T164
Test name
Test status
Simulation time 1091772136 ps
CPU time 15.3 seconds
Started Apr 25 12:41:51 PM PDT 24
Finished Apr 25 12:42:09 PM PDT 24
Peak memory 211584 kb
Host smart-e5fe0bac-ad17-4bcf-928b-f1035f84a12a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557953843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1557953843
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3791441271
Short name T292
Test name
Test status
Simulation time 12151502709 ps
CPU time 176.6 seconds
Started Apr 25 12:41:38 PM PDT 24
Finished Apr 25 12:44:36 PM PDT 24
Peak memory 218952 kb
Host smart-9885a6e2-4e5e-4526-9551-c240f9f7701d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791441271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3791441271
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2150574663
Short name T18
Test name
Test status
Simulation time 2062245499 ps
CPU time 19.13 seconds
Started Apr 25 12:41:43 PM PDT 24
Finished Apr 25 12:42:05 PM PDT 24
Peak memory 214948 kb
Host smart-a9ffb729-46b1-479d-b0f7-006692d00dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150574663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2150574663
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4077512989
Short name T154
Test name
Test status
Simulation time 1251682904 ps
CPU time 17.54 seconds
Started Apr 25 12:41:46 PM PDT 24
Finished Apr 25 12:42:06 PM PDT 24
Peak memory 211444 kb
Host smart-91a074ee-f225-49c7-a87d-82a86b12c188
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4077512989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4077512989
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2305027871
Short name T98
Test name
Test status
Simulation time 4608215415 ps
CPU time 33.73 seconds
Started Apr 25 12:41:40 PM PDT 24
Finished Apr 25 12:42:16 PM PDT 24
Peak memory 215600 kb
Host smart-642b5204-6267-4d97-b449-978c8f69620a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305027871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2305027871
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2209090988
Short name T121
Test name
Test status
Simulation time 2592126734 ps
CPU time 82.47 seconds
Started Apr 25 12:41:47 PM PDT 24
Finished Apr 25 12:43:11 PM PDT 24
Peak memory 219860 kb
Host smart-527b93ad-31f2-4cfd-8171-33472f3b8f82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209090988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2209090988
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1250918710
Short name T346
Test name
Test status
Simulation time 1269671526 ps
CPU time 8.28 seconds
Started Apr 25 12:41:45 PM PDT 24
Finished Apr 25 12:41:55 PM PDT 24
Peak memory 211608 kb
Host smart-587b2c8c-4a9c-4fd1-9826-fb62c2d3a13c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250918710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1250918710
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3481061815
Short name T209
Test name
Test status
Simulation time 60088799733 ps
CPU time 121.46 seconds
Started Apr 25 12:41:55 PM PDT 24
Finished Apr 25 12:43:59 PM PDT 24
Peak memory 215940 kb
Host smart-2f64cf15-827e-4553-a40b-6b38b76054d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481061815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3481061815
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3809159556
Short name T250
Test name
Test status
Simulation time 32015350033 ps
CPU time 61.78 seconds
Started Apr 25 12:41:55 PM PDT 24
Finished Apr 25 12:42:59 PM PDT 24
Peak memory 214400 kb
Host smart-5f81e612-6dc8-4c06-bdda-8e73b0b3e53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809159556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3809159556
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.4004211819
Short name T11
Test name
Test status
Simulation time 9537223312 ps
CPU time 30.65 seconds
Started Apr 25 12:41:43 PM PDT 24
Finished Apr 25 12:42:16 PM PDT 24
Peak memory 211620 kb
Host smart-d126ab31-8553-4d5c-aa81-3a8ea7dd1cd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4004211819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.4004211819
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3672480282
Short name T347
Test name
Test status
Simulation time 344336058 ps
CPU time 19.35 seconds
Started Apr 25 12:41:49 PM PDT 24
Finished Apr 25 12:42:10 PM PDT 24
Peak memory 216416 kb
Host smart-0be5856e-f723-46f4-8de0-193f6f2511df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672480282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3672480282
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1092690024
Short name T324
Test name
Test status
Simulation time 5456789646 ps
CPU time 125.36 seconds
Started Apr 25 12:41:49 PM PDT 24
Finished Apr 25 12:43:57 PM PDT 24
Peak memory 227784 kb
Host smart-17b677e2-2058-4b71-b9f7-ebb2f52cb6f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092690024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1092690024
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.986681902
Short name T205
Test name
Test status
Simulation time 24168606924 ps
CPU time 29.57 seconds
Started Apr 25 12:41:40 PM PDT 24
Finished Apr 25 12:42:12 PM PDT 24
Peak memory 212500 kb
Host smart-050b4b79-71e7-49f5-89cf-0a8be340f6b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986681902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.986681902
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1083531681
Short name T29
Test name
Test status
Simulation time 4498687245 ps
CPU time 274.79 seconds
Started Apr 25 12:41:45 PM PDT 24
Finished Apr 25 12:46:23 PM PDT 24
Peak memory 226076 kb
Host smart-aaae41be-a614-4b41-a74e-8ac0f65f8125
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083531681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1083531681
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1710639618
Short name T159
Test name
Test status
Simulation time 10824584820 ps
CPU time 50.19 seconds
Started Apr 25 12:41:44 PM PDT 24
Finished Apr 25 12:42:37 PM PDT 24
Peak memory 215716 kb
Host smart-9c4ea2d7-cc13-450a-b1e3-4f903809ebf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710639618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1710639618
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.684297744
Short name T264
Test name
Test status
Simulation time 1900863310 ps
CPU time 21.36 seconds
Started Apr 25 12:41:40 PM PDT 24
Finished Apr 25 12:42:04 PM PDT 24
Peak memory 211628 kb
Host smart-318e493b-a081-4e23-867e-b2ff35a24c04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=684297744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.684297744
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.898827992
Short name T146
Test name
Test status
Simulation time 11023887592 ps
CPU time 40.76 seconds
Started Apr 25 12:41:44 PM PDT 24
Finished Apr 25 12:42:28 PM PDT 24
Peak memory 218472 kb
Host smart-5782d9f1-4df5-4443-b183-49f5bbb37098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898827992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.898827992
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2123277433
Short name T246
Test name
Test status
Simulation time 10336885166 ps
CPU time 39.1 seconds
Started Apr 25 12:41:42 PM PDT 24
Finished Apr 25 12:42:23 PM PDT 24
Peak memory 219308 kb
Host smart-61efe5f8-dca3-4141-b1f8-81b30e130c49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123277433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2123277433
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3813096210
Short name T213
Test name
Test status
Simulation time 3264883241 ps
CPU time 12.84 seconds
Started Apr 25 12:41:08 PM PDT 24
Finished Apr 25 12:41:22 PM PDT 24
Peak memory 211540 kb
Host smart-3e07e20d-ccb2-4258-8ce0-88405ed42eb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813096210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3813096210
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.300980796
Short name T309
Test name
Test status
Simulation time 393876549289 ps
CPU time 916.06 seconds
Started Apr 25 12:41:26 PM PDT 24
Finished Apr 25 12:56:42 PM PDT 24
Peak memory 240156 kb
Host smart-fb1b1e63-5a23-4f93-b3b6-9d794e0ad44b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300980796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.300980796
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1686359337
Short name T207
Test name
Test status
Simulation time 6228620386 ps
CPU time 56.63 seconds
Started Apr 25 12:41:22 PM PDT 24
Finished Apr 25 12:42:20 PM PDT 24
Peak memory 215356 kb
Host smart-d7518d3d-5025-4ce0-adb9-818d71f57229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686359337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1686359337
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.795254069
Short name T206
Test name
Test status
Simulation time 189358936 ps
CPU time 10.5 seconds
Started Apr 25 12:41:26 PM PDT 24
Finished Apr 25 12:41:38 PM PDT 24
Peak memory 212432 kb
Host smart-8afb9752-cf8b-44a9-9bef-c45ffcf2a972
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=795254069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.795254069
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3343489289
Short name T38
Test name
Test status
Simulation time 423754260 ps
CPU time 118.84 seconds
Started Apr 25 12:41:10 PM PDT 24
Finished Apr 25 12:43:10 PM PDT 24
Peak memory 238712 kb
Host smart-566b22ec-0e05-41fb-a2b5-4b62c1bcb16a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343489289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3343489289
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3244375586
Short name T195
Test name
Test status
Simulation time 2424731991 ps
CPU time 34.52 seconds
Started Apr 25 12:41:18 PM PDT 24
Finished Apr 25 12:41:54 PM PDT 24
Peak memory 217328 kb
Host smart-24712af1-2504-4627-b4ed-822a7dda1a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244375586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3244375586
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3858936869
Short name T248
Test name
Test status
Simulation time 201287500 ps
CPU time 11.03 seconds
Started Apr 25 12:41:06 PM PDT 24
Finished Apr 25 12:41:17 PM PDT 24
Peak memory 212660 kb
Host smart-782eabb2-505a-426a-a0d7-4bb145bee9c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858936869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3858936869
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3855658246
Short name T189
Test name
Test status
Simulation time 23064759982 ps
CPU time 28.95 seconds
Started Apr 25 12:41:49 PM PDT 24
Finished Apr 25 12:42:25 PM PDT 24
Peak memory 212508 kb
Host smart-fc8368dd-9902-465f-a300-39b839058867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855658246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3855658246
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.239191113
Short name T172
Test name
Test status
Simulation time 81910401123 ps
CPU time 783.34 seconds
Started Apr 25 12:41:54 PM PDT 24
Finished Apr 25 12:55:00 PM PDT 24
Peak memory 225716 kb
Host smart-52db65c4-27c2-452f-a5b3-3cabf8c5eca1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239191113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.239191113
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1454258391
Short name T42
Test name
Test status
Simulation time 40070661673 ps
CPU time 57.62 seconds
Started Apr 25 12:41:56 PM PDT 24
Finished Apr 25 12:42:55 PM PDT 24
Peak memory 215296 kb
Host smart-b107a8f3-1922-4af8-a068-eb9de8fd9dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454258391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1454258391
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.621260974
Short name T237
Test name
Test status
Simulation time 6518000802 ps
CPU time 19.42 seconds
Started Apr 25 12:41:49 PM PDT 24
Finished Apr 25 12:42:10 PM PDT 24
Peak memory 212792 kb
Host smart-72b85ec3-fac0-4874-a8e7-c90f96932e6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=621260974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.621260974
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1883751030
Short name T278
Test name
Test status
Simulation time 8500798354 ps
CPU time 69.41 seconds
Started Apr 25 12:41:46 PM PDT 24
Finished Apr 25 12:42:58 PM PDT 24
Peak memory 217408 kb
Host smart-c2e063d4-2b81-4638-8cdf-0e329b367a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883751030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1883751030
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2148243345
Short name T82
Test name
Test status
Simulation time 7018819882 ps
CPU time 47.5 seconds
Started Apr 25 12:41:41 PM PDT 24
Finished Apr 25 12:42:31 PM PDT 24
Peak memory 219624 kb
Host smart-6b60cc42-bec9-42ae-8180-1dc866d9dbe2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148243345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2148243345
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.565143275
Short name T35
Test name
Test status
Simulation time 170808387 ps
CPU time 8.28 seconds
Started Apr 25 12:41:51 PM PDT 24
Finished Apr 25 12:42:02 PM PDT 24
Peak memory 211496 kb
Host smart-ede8bd89-fa1d-469f-b4f1-d838a1fdbd5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565143275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.565143275
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4005471392
Short name T50
Test name
Test status
Simulation time 107855402325 ps
CPU time 999.48 seconds
Started Apr 25 12:41:52 PM PDT 24
Finished Apr 25 12:58:34 PM PDT 24
Peak memory 239184 kb
Host smart-ec875ee1-9b86-482c-99d2-b3b05b0636c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005471392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.4005471392
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3693946865
Short name T281
Test name
Test status
Simulation time 689722919 ps
CPU time 19.73 seconds
Started Apr 25 12:41:31 PM PDT 24
Finished Apr 25 12:41:51 PM PDT 24
Peak memory 214852 kb
Host smart-36438326-8529-42d0-8293-324996ceddd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693946865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3693946865
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2241808355
Short name T178
Test name
Test status
Simulation time 1047859629 ps
CPU time 13.61 seconds
Started Apr 25 12:41:46 PM PDT 24
Finished Apr 25 12:42:02 PM PDT 24
Peak memory 212468 kb
Host smart-0d2abc27-c431-4f9c-91f8-e4d25ed5a403
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2241808355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2241808355
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2300866406
Short name T283
Test name
Test status
Simulation time 340860445 ps
CPU time 19.11 seconds
Started Apr 25 12:41:49 PM PDT 24
Finished Apr 25 12:42:10 PM PDT 24
Peak memory 214416 kb
Host smart-f49df0ae-22b9-4363-bb4e-59bd36194b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300866406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2300866406
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3351536296
Short name T7
Test name
Test status
Simulation time 4719909489 ps
CPU time 84.61 seconds
Started Apr 25 12:41:50 PM PDT 24
Finished Apr 25 12:43:17 PM PDT 24
Peak memory 219608 kb
Host smart-25623824-60cc-4c69-b03a-eb8c9748767b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351536296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3351536296
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3569911339
Short name T161
Test name
Test status
Simulation time 1242041917 ps
CPU time 11.56 seconds
Started Apr 25 12:41:48 PM PDT 24
Finished Apr 25 12:42:01 PM PDT 24
Peak memory 211576 kb
Host smart-16a625f8-9f6a-4cdd-a79d-69d164acf780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569911339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3569911339
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1068747441
Short name T312
Test name
Test status
Simulation time 706038207854 ps
CPU time 1015.07 seconds
Started Apr 25 12:41:42 PM PDT 24
Finished Apr 25 12:58:39 PM PDT 24
Peak memory 240216 kb
Host smart-4611df2f-3443-4233-a514-4dca061bd56d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068747441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1068747441
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2927725061
Short name T254
Test name
Test status
Simulation time 77848450568 ps
CPU time 61.74 seconds
Started Apr 25 12:41:45 PM PDT 24
Finished Apr 25 12:42:49 PM PDT 24
Peak memory 215408 kb
Host smart-799d71fa-0e5d-4a30-9722-5d67fb35e38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927725061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2927725061
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.4024238135
Short name T215
Test name
Test status
Simulation time 4770528355 ps
CPU time 23.85 seconds
Started Apr 25 12:41:44 PM PDT 24
Finished Apr 25 12:42:10 PM PDT 24
Peak memory 211912 kb
Host smart-6e5f3adf-f9d8-4742-9c7a-0bea6a610750
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4024238135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.4024238135
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1058113019
Short name T182
Test name
Test status
Simulation time 9932786770 ps
CPU time 29.67 seconds
Started Apr 25 12:41:43 PM PDT 24
Finished Apr 25 12:42:16 PM PDT 24
Peak memory 218236 kb
Host smart-a252fd3c-5346-47f7-a805-21567ba0c172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058113019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1058113019
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2195493303
Short name T210
Test name
Test status
Simulation time 2344092128 ps
CPU time 30.93 seconds
Started Apr 25 12:41:46 PM PDT 24
Finished Apr 25 12:42:19 PM PDT 24
Peak memory 212548 kb
Host smart-caece4e9-79da-483c-9c44-ec4c3437ba1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195493303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2195493303
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1865229338
Short name T70
Test name
Test status
Simulation time 1885080307 ps
CPU time 20.01 seconds
Started Apr 25 12:41:51 PM PDT 24
Finished Apr 25 12:42:14 PM PDT 24
Peak memory 211504 kb
Host smart-5a2ffef3-ed95-4de9-991b-b52783517cc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865229338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1865229338
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.220352329
Short name T261
Test name
Test status
Simulation time 24500128699 ps
CPU time 129.81 seconds
Started Apr 25 12:41:44 PM PDT 24
Finished Apr 25 12:43:56 PM PDT 24
Peak memory 216952 kb
Host smart-4b710cbc-c3e8-4a04-a4d5-54ed4a62a185
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220352329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.220352329
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.924121768
Short name T265
Test name
Test status
Simulation time 333336352 ps
CPU time 18.51 seconds
Started Apr 25 12:41:53 PM PDT 24
Finished Apr 25 12:42:13 PM PDT 24
Peak memory 216128 kb
Host smart-abf4f5b3-28a0-4cde-99b3-a7fee3162eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924121768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.924121768
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1794926267
Short name T190
Test name
Test status
Simulation time 3472199952 ps
CPU time 15.93 seconds
Started Apr 25 12:41:50 PM PDT 24
Finished Apr 25 12:42:08 PM PDT 24
Peak memory 211584 kb
Host smart-94b5512c-dfa9-4311-a2c3-949d5b730664
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1794926267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1794926267
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1341110221
Short name T287
Test name
Test status
Simulation time 664283570 ps
CPU time 19.54 seconds
Started Apr 25 12:41:53 PM PDT 24
Finished Apr 25 12:42:15 PM PDT 24
Peak memory 217104 kb
Host smart-791b1329-e9e5-45da-a1e0-e816469eca5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341110221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1341110221
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.816144247
Short name T22
Test name
Test status
Simulation time 24513053469 ps
CPU time 105.27 seconds
Started Apr 25 12:41:51 PM PDT 24
Finished Apr 25 12:43:39 PM PDT 24
Peak memory 219528 kb
Host smart-df6c93ef-0010-49eb-b916-b4069d021947
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816144247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.816144247
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.516952822
Short name T344
Test name
Test status
Simulation time 7533959327 ps
CPU time 29.17 seconds
Started Apr 25 12:41:46 PM PDT 24
Finished Apr 25 12:42:18 PM PDT 24
Peak memory 212380 kb
Host smart-e381e113-cc93-4f7d-886f-69845136e72c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516952822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.516952822
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1968871846
Short name T149
Test name
Test status
Simulation time 20695063769 ps
CPU time 395.1 seconds
Started Apr 25 12:41:52 PM PDT 24
Finished Apr 25 12:48:30 PM PDT 24
Peak memory 229840 kb
Host smart-890f6a26-af08-46f3-bc77-af2c6b82ab4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968871846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1968871846
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.678031127
Short name T162
Test name
Test status
Simulation time 8888028705 ps
CPU time 70.94 seconds
Started Apr 25 12:41:48 PM PDT 24
Finished Apr 25 12:43:01 PM PDT 24
Peak memory 215392 kb
Host smart-13afd254-f114-4180-9031-8e79b9a31353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678031127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.678031127
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2634991694
Short name T318
Test name
Test status
Simulation time 7016760488 ps
CPU time 22.39 seconds
Started Apr 25 12:41:47 PM PDT 24
Finished Apr 25 12:42:11 PM PDT 24
Peak memory 212088 kb
Host smart-96ec3944-77ec-4015-8c0a-b842ad62bef7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2634991694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2634991694
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3551070451
Short name T272
Test name
Test status
Simulation time 4705370440 ps
CPU time 35.34 seconds
Started Apr 25 12:41:36 PM PDT 24
Finished Apr 25 12:42:12 PM PDT 24
Peak memory 216964 kb
Host smart-1b362ef8-ad01-4bdf-8cbf-7393dd6d0a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551070451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3551070451
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3452279904
Short name T40
Test name
Test status
Simulation time 4989190286 ps
CPU time 66.39 seconds
Started Apr 25 12:41:46 PM PDT 24
Finished Apr 25 12:42:55 PM PDT 24
Peak memory 220436 kb
Host smart-e794f74f-a14c-4075-b32c-56c9efb13daf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452279904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3452279904
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.259117561
Short name T69
Test name
Test status
Simulation time 353415396 ps
CPU time 8.32 seconds
Started Apr 25 12:41:52 PM PDT 24
Finished Apr 25 12:42:03 PM PDT 24
Peak memory 211540 kb
Host smart-787f0863-7c85-491d-a799-f3d632442564
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259117561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.259117561
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2825418262
Short name T176
Test name
Test status
Simulation time 37078907462 ps
CPU time 448.89 seconds
Started Apr 25 12:41:46 PM PDT 24
Finished Apr 25 12:49:17 PM PDT 24
Peak memory 238028 kb
Host smart-63c4f108-9058-4bfc-9318-b14f220933e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825418262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2825418262
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.285518610
Short name T257
Test name
Test status
Simulation time 26877329392 ps
CPU time 56.4 seconds
Started Apr 25 12:41:55 PM PDT 24
Finished Apr 25 12:42:54 PM PDT 24
Peak memory 215312 kb
Host smart-7607b1b8-92c5-4ac7-ab3d-663a962a2a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285518610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.285518610
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.573863001
Short name T303
Test name
Test status
Simulation time 4182108113 ps
CPU time 33.47 seconds
Started Apr 25 12:41:48 PM PDT 24
Finished Apr 25 12:42:24 PM PDT 24
Peak memory 211680 kb
Host smart-5703ba72-d5aa-44c3-8d0b-ec011c87ebb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=573863001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.573863001
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.143601842
Short name T240
Test name
Test status
Simulation time 693445360 ps
CPU time 19.79 seconds
Started Apr 25 12:41:48 PM PDT 24
Finished Apr 25 12:42:10 PM PDT 24
Peak memory 217372 kb
Host smart-937f737d-7e23-434e-a000-b30ef81c47de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143601842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.143601842
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2724913466
Short name T227
Test name
Test status
Simulation time 6549341617 ps
CPU time 39.04 seconds
Started Apr 25 12:41:57 PM PDT 24
Finished Apr 25 12:42:38 PM PDT 24
Peak memory 211388 kb
Host smart-2e6371ed-6567-4907-a8a0-c8d0c6d34641
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724913466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2724913466
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1561771152
Short name T153
Test name
Test status
Simulation time 1640734977 ps
CPU time 17.76 seconds
Started Apr 25 12:41:38 PM PDT 24
Finished Apr 25 12:41:57 PM PDT 24
Peak memory 211516 kb
Host smart-5c40d4d4-11e9-4fa1-a1b6-d07f55f750ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561771152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1561771152
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.963910664
Short name T244
Test name
Test status
Simulation time 699412339003 ps
CPU time 643.19 seconds
Started Apr 25 12:41:51 PM PDT 24
Finished Apr 25 12:52:37 PM PDT 24
Peak memory 240880 kb
Host smart-cf795852-769b-46e0-aa41-35ce0bdc056d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963910664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.963910664
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1782929327
Short name T143
Test name
Test status
Simulation time 17950414486 ps
CPU time 31.53 seconds
Started Apr 25 12:41:52 PM PDT 24
Finished Apr 25 12:42:26 PM PDT 24
Peak memory 215364 kb
Host smart-e040bfdc-cbd9-49db-a295-421b128ae423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782929327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1782929327
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.857835668
Short name T270
Test name
Test status
Simulation time 38934648242 ps
CPU time 28.6 seconds
Started Apr 25 12:41:46 PM PDT 24
Finished Apr 25 12:42:17 PM PDT 24
Peak memory 211636 kb
Host smart-451647bc-01d3-421b-83f0-2ee82d1f4d98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=857835668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.857835668
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1504827604
Short name T242
Test name
Test status
Simulation time 23067987146 ps
CPU time 57.85 seconds
Started Apr 25 12:41:49 PM PDT 24
Finished Apr 25 12:42:50 PM PDT 24
Peak memory 218392 kb
Host smart-d3a7f639-35c1-4a01-9472-b1bc3091b02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504827604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1504827604
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3522381173
Short name T198
Test name
Test status
Simulation time 47876201364 ps
CPU time 127.92 seconds
Started Apr 25 12:41:44 PM PDT 24
Finished Apr 25 12:43:54 PM PDT 24
Peak memory 220752 kb
Host smart-f60141cf-8966-4a42-86db-d21913fc7f3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522381173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3522381173
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2652172754
Short name T300
Test name
Test status
Simulation time 5449694899 ps
CPU time 26.04 seconds
Started Apr 25 12:41:54 PM PDT 24
Finished Apr 25 12:42:22 PM PDT 24
Peak memory 211664 kb
Host smart-6cbd4901-dc33-40cf-bd5a-170497cafa42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652172754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2652172754
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.994825606
Short name T28
Test name
Test status
Simulation time 256967583699 ps
CPU time 541.94 seconds
Started Apr 25 12:41:55 PM PDT 24
Finished Apr 25 12:50:59 PM PDT 24
Peak memory 240228 kb
Host smart-926c18d8-6022-4f9c-9202-62fd2a0f475a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994825606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.994825606
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2134878961
Short name T97
Test name
Test status
Simulation time 22612929068 ps
CPU time 52.51 seconds
Started Apr 25 12:41:48 PM PDT 24
Finished Apr 25 12:42:43 PM PDT 24
Peak memory 215284 kb
Host smart-a21cc313-4c51-401c-bebd-85492cd68ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134878961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2134878961
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1580654017
Short name T340
Test name
Test status
Simulation time 6663123144 ps
CPU time 30.95 seconds
Started Apr 25 12:41:56 PM PDT 24
Finished Apr 25 12:42:29 PM PDT 24
Peak memory 211944 kb
Host smart-ac693b1c-73a6-47c3-ab78-9069b7914cb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1580654017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1580654017
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1122647223
Short name T59
Test name
Test status
Simulation time 13103947062 ps
CPU time 59.35 seconds
Started Apr 25 12:41:51 PM PDT 24
Finished Apr 25 12:42:53 PM PDT 24
Peak memory 217388 kb
Host smart-7731554a-bd11-4ce9-b6ca-1f9eaf8a4648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122647223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1122647223
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3967517215
Short name T60
Test name
Test status
Simulation time 3797481974 ps
CPU time 63.6 seconds
Started Apr 25 12:41:52 PM PDT 24
Finished Apr 25 12:42:58 PM PDT 24
Peak memory 220100 kb
Host smart-271dd90f-052d-44c3-b176-797e1796c175
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967517215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3967517215
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2738536858
Short name T15
Test name
Test status
Simulation time 67737938780 ps
CPU time 1281.67 seconds
Started Apr 25 12:41:57 PM PDT 24
Finished Apr 25 01:03:21 PM PDT 24
Peak memory 236104 kb
Host smart-2894c98f-3c0b-4d4e-a4b3-00b4498494b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738536858 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2738536858
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2306266716
Short name T3
Test name
Test status
Simulation time 3969865544 ps
CPU time 16.26 seconds
Started Apr 25 12:41:57 PM PDT 24
Finished Apr 25 12:42:15 PM PDT 24
Peak memory 211644 kb
Host smart-d4879e4b-ff9e-4a6d-b99e-f9a5f687e567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306266716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2306266716
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.277021367
Short name T247
Test name
Test status
Simulation time 675434162 ps
CPU time 18.32 seconds
Started Apr 25 12:41:48 PM PDT 24
Finished Apr 25 12:42:09 PM PDT 24
Peak memory 214924 kb
Host smart-4b8f1401-07c8-458e-ae8d-433dbb1e8e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277021367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.277021367
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3201736560
Short name T107
Test name
Test status
Simulation time 710459862 ps
CPU time 13.02 seconds
Started Apr 25 12:41:44 PM PDT 24
Finished Apr 25 12:42:00 PM PDT 24
Peak memory 211676 kb
Host smart-e73e7041-a881-426c-b69b-1448da60697c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3201736560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3201736560
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3142493232
Short name T124
Test name
Test status
Simulation time 1567020634 ps
CPU time 19.97 seconds
Started Apr 25 12:41:56 PM PDT 24
Finished Apr 25 12:42:18 PM PDT 24
Peak memory 216928 kb
Host smart-92acfbb2-0630-4bd2-840e-a17da19def9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142493232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3142493232
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1581881653
Short name T36
Test name
Test status
Simulation time 43050898059 ps
CPU time 104.86 seconds
Started Apr 25 12:41:46 PM PDT 24
Finished Apr 25 12:43:33 PM PDT 24
Peak memory 219652 kb
Host smart-707dacf7-65ca-4d4d-9ae4-51425e1c1962
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581881653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1581881653
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1543720262
Short name T56
Test name
Test status
Simulation time 128906959896 ps
CPU time 2412.29 seconds
Started Apr 25 12:41:47 PM PDT 24
Finished Apr 25 01:22:02 PM PDT 24
Peak memory 248660 kb
Host smart-035bc1ea-0e6f-417d-b6ab-cabc96f3f814
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543720262 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1543720262
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.4138125701
Short name T266
Test name
Test status
Simulation time 4040703923 ps
CPU time 30.98 seconds
Started Apr 25 12:41:43 PM PDT 24
Finished Apr 25 12:42:17 PM PDT 24
Peak memory 212048 kb
Host smart-c6705cc1-08e2-4325-a274-a68d806310c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138125701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.4138125701
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2430298745
Short name T293
Test name
Test status
Simulation time 75374526556 ps
CPU time 364.78 seconds
Started Apr 25 12:41:49 PM PDT 24
Finished Apr 25 12:47:57 PM PDT 24
Peak memory 239196 kb
Host smart-369c28a2-1e3d-4472-a4c5-f626fda29f62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430298745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2430298745
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2655985054
Short name T169
Test name
Test status
Simulation time 1970001697 ps
CPU time 26.03 seconds
Started Apr 25 12:41:51 PM PDT 24
Finished Apr 25 12:42:19 PM PDT 24
Peak memory 214948 kb
Host smart-88376679-5dc2-4cbe-9c9c-d98463317e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655985054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2655985054
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.223276815
Short name T226
Test name
Test status
Simulation time 3956958609 ps
CPU time 32.46 seconds
Started Apr 25 12:41:53 PM PDT 24
Finished Apr 25 12:42:32 PM PDT 24
Peak memory 212636 kb
Host smart-06ed71a3-7a15-4d2c-8dcd-e6a342005616
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=223276815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.223276815
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2900172318
Short name T156
Test name
Test status
Simulation time 4545668541 ps
CPU time 35.72 seconds
Started Apr 25 12:41:48 PM PDT 24
Finished Apr 25 12:42:25 PM PDT 24
Peak memory 217700 kb
Host smart-4ba23208-1947-4d15-a485-ad27dbc3918b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900172318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2900172318
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2800794394
Short name T201
Test name
Test status
Simulation time 10359050769 ps
CPU time 123.64 seconds
Started Apr 25 12:41:51 PM PDT 24
Finished Apr 25 12:43:57 PM PDT 24
Peak memory 222932 kb
Host smart-4eb50f76-c458-4b42-9b2a-70f951654e13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800794394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2800794394
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2632893132
Short name T52
Test name
Test status
Simulation time 66613811142 ps
CPU time 5076.14 seconds
Started Apr 25 12:41:48 PM PDT 24
Finished Apr 25 02:06:26 PM PDT 24
Peak memory 244576 kb
Host smart-3d1a82c6-731a-48a5-b3c6-31635c716513
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632893132 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.2632893132
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2294946537
Short name T170
Test name
Test status
Simulation time 3546965410 ps
CPU time 27.87 seconds
Started Apr 25 12:41:26 PM PDT 24
Finished Apr 25 12:41:54 PM PDT 24
Peak memory 212068 kb
Host smart-20160eca-20f5-43fa-8be5-e2beacef6b7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294946537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2294946537
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.4197280218
Short name T332
Test name
Test status
Simulation time 257546745900 ps
CPU time 599.77 seconds
Started Apr 25 12:41:35 PM PDT 24
Finished Apr 25 12:51:36 PM PDT 24
Peak memory 228588 kb
Host smart-dc21d313-2129-497b-83ac-6792ecd0974d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197280218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.4197280218
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2890008774
Short name T229
Test name
Test status
Simulation time 1434382540 ps
CPU time 19.27 seconds
Started Apr 25 12:41:16 PM PDT 24
Finished Apr 25 12:41:36 PM PDT 24
Peak memory 214944 kb
Host smart-c545cda0-0f77-4810-91ef-524116992837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890008774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2890008774
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1869087517
Short name T139
Test name
Test status
Simulation time 2455154903 ps
CPU time 23.65 seconds
Started Apr 25 12:41:05 PM PDT 24
Finished Apr 25 12:41:29 PM PDT 24
Peak memory 211532 kb
Host smart-59e5641b-0cfd-4f3e-a22d-98b9e4af2309
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1869087517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1869087517
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2263329569
Short name T37
Test name
Test status
Simulation time 374327516 ps
CPU time 119.35 seconds
Started Apr 25 12:41:06 PM PDT 24
Finished Apr 25 12:43:06 PM PDT 24
Peak memory 237012 kb
Host smart-ad3abf88-d552-484c-811e-370aeee44aa9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263329569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2263329569
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2115097901
Short name T217
Test name
Test status
Simulation time 11151881120 ps
CPU time 37.14 seconds
Started Apr 25 12:41:20 PM PDT 24
Finished Apr 25 12:41:58 PM PDT 24
Peak memory 218300 kb
Host smart-e8223924-ea06-42f4-a9cd-e7bd7b4f48d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115097901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2115097901
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1001110081
Short name T297
Test name
Test status
Simulation time 50510399842 ps
CPU time 90.36 seconds
Started Apr 25 12:41:18 PM PDT 24
Finished Apr 25 12:42:49 PM PDT 24
Peak memory 221368 kb
Host smart-97e728a2-d23c-49e0-b06d-aabb28c0a8c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001110081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1001110081
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2769150044
Short name T294
Test name
Test status
Simulation time 6355696638 ps
CPU time 19.4 seconds
Started Apr 25 12:42:01 PM PDT 24
Finished Apr 25 12:42:22 PM PDT 24
Peak memory 211676 kb
Host smart-5de054cc-2d58-4ec2-87d1-7eb63f51b453
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769150044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2769150044
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1186041089
Short name T322
Test name
Test status
Simulation time 151001954893 ps
CPU time 342.4 seconds
Started Apr 25 12:41:49 PM PDT 24
Finished Apr 25 12:47:34 PM PDT 24
Peak memory 237888 kb
Host smart-1d988e27-1169-47d0-8d3e-30ebe042eef2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186041089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1186041089
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.365170602
Short name T147
Test name
Test status
Simulation time 4478305015 ps
CPU time 45.24 seconds
Started Apr 25 12:41:56 PM PDT 24
Finished Apr 25 12:42:44 PM PDT 24
Peak memory 214244 kb
Host smart-b44c0c2b-9b66-4b1c-b3fe-674817e46900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365170602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.365170602
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2890493258
Short name T130
Test name
Test status
Simulation time 468634654 ps
CPU time 10.16 seconds
Started Apr 25 12:41:53 PM PDT 24
Finished Apr 25 12:42:05 PM PDT 24
Peak memory 212416 kb
Host smart-5777de29-b29c-4164-bfb8-46fd13944768
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890493258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2890493258
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2532006729
Short name T2
Test name
Test status
Simulation time 11855764152 ps
CPU time 39.4 seconds
Started Apr 25 12:41:52 PM PDT 24
Finished Apr 25 12:42:33 PM PDT 24
Peak memory 218128 kb
Host smart-73ed4370-7495-4513-9ecb-e6e46a1ed615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532006729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2532006729
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.4225324087
Short name T200
Test name
Test status
Simulation time 1453540620 ps
CPU time 44.34 seconds
Started Apr 25 12:41:45 PM PDT 24
Finished Apr 25 12:42:32 PM PDT 24
Peak memory 219584 kb
Host smart-2c0d537f-4582-4f8d-aaba-a261ea0a3c67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225324087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.4225324087
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2999041355
Short name T17
Test name
Test status
Simulation time 124011866818 ps
CPU time 9745.3 seconds
Started Apr 25 12:41:53 PM PDT 24
Finished Apr 25 03:24:21 PM PDT 24
Peak memory 233956 kb
Host smart-34f06fc3-809f-41e2-aefd-22d91196818e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999041355 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.2999041355
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3822694070
Short name T252
Test name
Test status
Simulation time 7881672431 ps
CPU time 20.78 seconds
Started Apr 25 12:41:54 PM PDT 24
Finished Apr 25 12:42:17 PM PDT 24
Peak memory 211608 kb
Host smart-66a9c72b-5321-4edc-89f9-8a356e62406b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822694070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3822694070
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.922737702
Short name T203
Test name
Test status
Simulation time 6114410553 ps
CPU time 214.67 seconds
Started Apr 25 12:41:45 PM PDT 24
Finished Apr 25 12:45:22 PM PDT 24
Peak memory 225188 kb
Host smart-2d15d801-cc76-41f7-8889-dbfed588ea17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922737702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.922737702
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3752293440
Short name T6
Test name
Test status
Simulation time 46398490856 ps
CPU time 52.38 seconds
Started Apr 25 12:41:53 PM PDT 24
Finished Apr 25 12:42:48 PM PDT 24
Peak memory 215884 kb
Host smart-aaf9acb0-a381-4612-a3ef-e757c1e0e410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752293440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3752293440
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1336626822
Short name T315
Test name
Test status
Simulation time 1193585740 ps
CPU time 14.53 seconds
Started Apr 25 12:41:58 PM PDT 24
Finished Apr 25 12:42:14 PM PDT 24
Peak memory 211488 kb
Host smart-509b0869-ab5e-4a67-9dc9-2341a1f208bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1336626822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1336626822
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3181622386
Short name T173
Test name
Test status
Simulation time 3704395060 ps
CPU time 44.01 seconds
Started Apr 25 12:41:49 PM PDT 24
Finished Apr 25 12:42:35 PM PDT 24
Peak memory 216016 kb
Host smart-6ace501a-f433-4871-b7e7-e4f838a86660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181622386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3181622386
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1765115011
Short name T255
Test name
Test status
Simulation time 2628984813 ps
CPU time 33.92 seconds
Started Apr 25 12:41:58 PM PDT 24
Finished Apr 25 12:42:34 PM PDT 24
Peak memory 219652 kb
Host smart-047baace-508d-4981-9f9b-7915f5b4bd68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765115011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1765115011
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4038482785
Short name T323
Test name
Test status
Simulation time 1026306020 ps
CPU time 14.62 seconds
Started Apr 25 12:41:47 PM PDT 24
Finished Apr 25 12:42:04 PM PDT 24
Peak memory 211540 kb
Host smart-2dd4c307-3aa4-4782-b2a6-e3ff0e01139f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038482785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4038482785
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.167144836
Short name T339
Test name
Test status
Simulation time 35112613264 ps
CPU time 452.63 seconds
Started Apr 25 12:42:01 PM PDT 24
Finished Apr 25 12:49:36 PM PDT 24
Peak memory 238096 kb
Host smart-fdc0f778-c84e-4398-9c12-03f51318c618
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167144836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.167144836
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2331547425
Short name T359
Test name
Test status
Simulation time 8734431842 ps
CPU time 43.35 seconds
Started Apr 25 12:42:02 PM PDT 24
Finished Apr 25 12:42:47 PM PDT 24
Peak memory 214372 kb
Host smart-c687da05-1e72-45e5-95a1-d421ab9e76a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331547425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2331547425
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1218778708
Short name T134
Test name
Test status
Simulation time 42623152695 ps
CPU time 25.8 seconds
Started Apr 25 12:41:44 PM PDT 24
Finished Apr 25 12:42:13 PM PDT 24
Peak memory 212140 kb
Host smart-27f4d706-98e9-4b9f-bc40-6dac6ed86792
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1218778708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1218778708
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1262375605
Short name T350
Test name
Test status
Simulation time 34841933222 ps
CPU time 26.2 seconds
Started Apr 25 12:41:56 PM PDT 24
Finished Apr 25 12:42:25 PM PDT 24
Peak memory 211688 kb
Host smart-a83d3630-4b88-43ed-844b-ff28bb21ff89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262375605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1262375605
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1714670829
Short name T341
Test name
Test status
Simulation time 38655972533 ps
CPU time 501.11 seconds
Started Apr 25 12:41:49 PM PDT 24
Finished Apr 25 12:50:12 PM PDT 24
Peak memory 240236 kb
Host smart-5e89654c-5632-4d7d-8baf-bb2c15bbc76a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714670829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1714670829
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2049243398
Short name T336
Test name
Test status
Simulation time 675923582 ps
CPU time 19.17 seconds
Started Apr 25 12:41:55 PM PDT 24
Finished Apr 25 12:42:16 PM PDT 24
Peak memory 214924 kb
Host smart-5d910ae9-c9eb-4573-ad4b-7be6bd818395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049243398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2049243398
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3276360922
Short name T135
Test name
Test status
Simulation time 219501982 ps
CPU time 10.49 seconds
Started Apr 25 12:41:53 PM PDT 24
Finished Apr 25 12:42:06 PM PDT 24
Peak memory 212580 kb
Host smart-1b4360c8-d0b9-4ad7-b5e7-491827f04fb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3276360922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3276360922
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1680633509
Short name T4
Test name
Test status
Simulation time 30866118172 ps
CPU time 78.98 seconds
Started Apr 25 12:41:56 PM PDT 24
Finished Apr 25 12:43:18 PM PDT 24
Peak memory 216840 kb
Host smart-d5bf1ae0-814e-493f-ab2b-dd1c87e0406e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680633509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1680633509
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.828931756
Short name T127
Test name
Test status
Simulation time 8140280537 ps
CPU time 62.22 seconds
Started Apr 25 12:41:55 PM PDT 24
Finished Apr 25 12:42:59 PM PDT 24
Peak memory 219584 kb
Host smart-0b7b94c0-4017-47f5-aaa6-b75a54047a09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828931756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.828931756
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.990575930
Short name T34
Test name
Test status
Simulation time 2257035823 ps
CPU time 21.19 seconds
Started Apr 25 12:41:57 PM PDT 24
Finished Apr 25 12:42:20 PM PDT 24
Peak memory 212100 kb
Host smart-9f8adc44-48a7-4fcd-85b0-9615ba0dd3b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990575930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.990575930
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1430415890
Short name T204
Test name
Test status
Simulation time 394316354415 ps
CPU time 932.91 seconds
Started Apr 25 12:42:03 PM PDT 24
Finished Apr 25 12:57:38 PM PDT 24
Peak memory 239068 kb
Host smart-0f6cc063-6bb5-4fbd-b592-1658d58050a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430415890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1430415890
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3191509165
Short name T291
Test name
Test status
Simulation time 3296444337 ps
CPU time 19.42 seconds
Started Apr 25 12:41:51 PM PDT 24
Finished Apr 25 12:42:13 PM PDT 24
Peak memory 214964 kb
Host smart-48ce5055-e359-490a-817d-3075d1be4e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191509165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3191509165
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1311260681
Short name T333
Test name
Test status
Simulation time 15188475843 ps
CPU time 28.25 seconds
Started Apr 25 12:41:56 PM PDT 24
Finished Apr 25 12:42:31 PM PDT 24
Peak memory 212128 kb
Host smart-5709ab8d-cf19-4e76-874e-b6759d829f28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1311260681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1311260681
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3841026045
Short name T249
Test name
Test status
Simulation time 17931345874 ps
CPU time 50.32 seconds
Started Apr 25 12:42:02 PM PDT 24
Finished Apr 25 12:42:54 PM PDT 24
Peak memory 218488 kb
Host smart-cd1154e1-a0a4-4b16-bc70-1934eb27e947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841026045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3841026045
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2560370740
Short name T335
Test name
Test status
Simulation time 13701231645 ps
CPU time 115.24 seconds
Started Apr 25 12:41:50 PM PDT 24
Finished Apr 25 12:43:47 PM PDT 24
Peak memory 219560 kb
Host smart-9d3bcdf0-b07c-4522-9438-e3b06cacef81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560370740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2560370740
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2625478861
Short name T54
Test name
Test status
Simulation time 179584115289 ps
CPU time 3368.27 seconds
Started Apr 25 12:41:54 PM PDT 24
Finished Apr 25 01:38:04 PM PDT 24
Peak memory 246896 kb
Host smart-5b4c156d-02ed-49b3-88a0-4ac8e0dc2ec2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625478861 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2625478861
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.4279597904
Short name T43
Test name
Test status
Simulation time 9002584513 ps
CPU time 22.09 seconds
Started Apr 25 12:41:49 PM PDT 24
Finished Apr 25 12:42:14 PM PDT 24
Peak memory 212392 kb
Host smart-db7d1fd6-06aa-4d6b-97a5-ac0a45813fdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279597904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.4279597904
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.795526877
Short name T279
Test name
Test status
Simulation time 8294950267 ps
CPU time 263.9 seconds
Started Apr 25 12:42:02 PM PDT 24
Finished Apr 25 12:46:28 PM PDT 24
Peak memory 241080 kb
Host smart-f7cf8d02-5f57-4a2c-9542-7b68ac4f8d09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795526877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.795526877
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.4160994440
Short name T125
Test name
Test status
Simulation time 2315449702 ps
CPU time 34.74 seconds
Started Apr 25 12:41:56 PM PDT 24
Finished Apr 25 12:42:33 PM PDT 24
Peak memory 215208 kb
Host smart-479dd5bb-d856-4dfc-a3ba-1bd1c061829e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160994440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.4160994440
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1344121386
Short name T186
Test name
Test status
Simulation time 10826516983 ps
CPU time 17.01 seconds
Started Apr 25 12:42:02 PM PDT 24
Finished Apr 25 12:42:20 PM PDT 24
Peak memory 212000 kb
Host smart-fc3e4c76-f18d-4473-84e9-e531a6ba027e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1344121386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1344121386
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1581961849
Short name T353
Test name
Test status
Simulation time 2506309903 ps
CPU time 24.62 seconds
Started Apr 25 12:41:49 PM PDT 24
Finished Apr 25 12:42:16 PM PDT 24
Peak memory 217068 kb
Host smart-8c42198f-a9b9-43d9-ba97-b4598a4a39fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581961849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1581961849
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.4029835011
Short name T61
Test name
Test status
Simulation time 26253222113 ps
CPU time 65.73 seconds
Started Apr 25 12:42:02 PM PDT 24
Finished Apr 25 12:43:10 PM PDT 24
Peak memory 219104 kb
Host smart-95a97a54-ec57-48bc-ac18-37b1390daecc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029835011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.4029835011
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2629858568
Short name T196
Test name
Test status
Simulation time 4711413009 ps
CPU time 22.47 seconds
Started Apr 25 12:41:53 PM PDT 24
Finished Apr 25 12:42:17 PM PDT 24
Peak memory 211416 kb
Host smart-fc83906c-988f-4d6d-8edc-d66efa94fa44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629858568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2629858568
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3260511169
Short name T337
Test name
Test status
Simulation time 512223581192 ps
CPU time 1044.96 seconds
Started Apr 25 12:42:01 PM PDT 24
Finished Apr 25 12:59:28 PM PDT 24
Peak memory 230904 kb
Host smart-9cac6901-8aea-4f46-881c-c88c1d496230
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260511169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3260511169
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3872447923
Short name T298
Test name
Test status
Simulation time 1374801664 ps
CPU time 19.02 seconds
Started Apr 25 12:42:01 PM PDT 24
Finished Apr 25 12:42:22 PM PDT 24
Peak memory 214960 kb
Host smart-1e91ff55-7aab-457b-8be7-d92ab0a59b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872447923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3872447923
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2712336750
Short name T151
Test name
Test status
Simulation time 13487273292 ps
CPU time 27.51 seconds
Started Apr 25 12:41:48 PM PDT 24
Finished Apr 25 12:42:18 PM PDT 24
Peak memory 213112 kb
Host smart-95127c19-6279-4584-93cc-c09a1696afa8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2712336750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2712336750
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.840017980
Short name T317
Test name
Test status
Simulation time 7816646498 ps
CPU time 73.29 seconds
Started Apr 25 12:41:50 PM PDT 24
Finished Apr 25 12:43:06 PM PDT 24
Peak memory 217596 kb
Host smart-bd349106-43ab-4ae6-bba0-1c497d2447d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840017980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.840017980
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1029585438
Short name T356
Test name
Test status
Simulation time 30960962257 ps
CPU time 188 seconds
Started Apr 25 12:41:55 PM PDT 24
Finished Apr 25 12:45:06 PM PDT 24
Peak memory 221476 kb
Host smart-ab10184c-b6d8-4f17-bc2e-2488a589da60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029585438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1029585438
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.300047121
Short name T325
Test name
Test status
Simulation time 3387815328 ps
CPU time 26.04 seconds
Started Apr 25 12:41:58 PM PDT 24
Finished Apr 25 12:42:26 PM PDT 24
Peak memory 212224 kb
Host smart-a98ec8d2-32ea-463b-b410-22e94266fc8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300047121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.300047121
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1869189277
Short name T171
Test name
Test status
Simulation time 169477689500 ps
CPU time 557.67 seconds
Started Apr 25 12:41:50 PM PDT 24
Finished Apr 25 12:51:10 PM PDT 24
Peak memory 234072 kb
Host smart-96abb651-2a63-4f0f-9733-d67349d6f6bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869189277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1869189277
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.247909618
Short name T180
Test name
Test status
Simulation time 12989795973 ps
CPU time 56.87 seconds
Started Apr 25 12:41:55 PM PDT 24
Finished Apr 25 12:42:54 PM PDT 24
Peak memory 213360 kb
Host smart-59f04b36-84b9-4e66-a5c6-6bbc890a26cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247909618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.247909618
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2679544990
Short name T155
Test name
Test status
Simulation time 30202642677 ps
CPU time 61.98 seconds
Started Apr 25 12:41:51 PM PDT 24
Finished Apr 25 12:42:55 PM PDT 24
Peak memory 217404 kb
Host smart-eb72653a-cae0-4002-9aa3-dd06403e5afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679544990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2679544990
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2561227963
Short name T228
Test name
Test status
Simulation time 4297082982 ps
CPU time 52.5 seconds
Started Apr 25 12:41:54 PM PDT 24
Finished Apr 25 12:42:49 PM PDT 24
Peak memory 217916 kb
Host smart-84c5c577-8c9e-4b3e-a63b-8f4e196acdef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561227963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2561227963
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1868120511
Short name T232
Test name
Test status
Simulation time 8784675041 ps
CPU time 23.09 seconds
Started Apr 25 12:42:04 PM PDT 24
Finished Apr 25 12:42:30 PM PDT 24
Peak memory 211848 kb
Host smart-d1bf33c4-3f80-483a-bf69-51ae694edda9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868120511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1868120511
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2963386224
Short name T46
Test name
Test status
Simulation time 41737406829 ps
CPU time 71.28 seconds
Started Apr 25 12:42:07 PM PDT 24
Finished Apr 25 12:43:23 PM PDT 24
Peak memory 215348 kb
Host smart-0a2697da-f248-4935-90b8-705ac5a54cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963386224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2963386224
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1357551794
Short name T44
Test name
Test status
Simulation time 5036003895 ps
CPU time 29.48 seconds
Started Apr 25 12:42:11 PM PDT 24
Finished Apr 25 12:42:47 PM PDT 24
Peak memory 212800 kb
Host smart-59407b13-c3b2-407e-ba32-0637b2e828d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1357551794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1357551794
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.890352542
Short name T128
Test name
Test status
Simulation time 2810090144 ps
CPU time 25.17 seconds
Started Apr 25 12:42:16 PM PDT 24
Finished Apr 25 12:42:46 PM PDT 24
Peak memory 216244 kb
Host smart-a0269074-ac52-4169-bc1f-6c0fc7a99914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890352542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.890352542
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1846862712
Short name T177
Test name
Test status
Simulation time 114446322919 ps
CPU time 195.56 seconds
Started Apr 25 12:42:09 PM PDT 24
Finished Apr 25 12:45:29 PM PDT 24
Peak memory 222384 kb
Host smart-d551e291-f203-45fe-b311-2fcd961f283e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846862712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1846862712
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.508376584
Short name T260
Test name
Test status
Simulation time 7806038423 ps
CPU time 20.75 seconds
Started Apr 25 12:42:07 PM PDT 24
Finished Apr 25 12:42:32 PM PDT 24
Peak memory 211604 kb
Host smart-332e5a82-d833-4406-a99f-839fcf9c6c32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508376584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.508376584
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.4091939028
Short name T218
Test name
Test status
Simulation time 31717573546 ps
CPU time 206.72 seconds
Started Apr 25 12:41:53 PM PDT 24
Finished Apr 25 12:45:22 PM PDT 24
Peak memory 224916 kb
Host smart-b1567a4b-fa68-4e5e-b5f2-a0ba6b27bbea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091939028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.4091939028
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.235440461
Short name T25
Test name
Test status
Simulation time 32125369260 ps
CPU time 63.42 seconds
Started Apr 25 12:42:08 PM PDT 24
Finished Apr 25 12:43:17 PM PDT 24
Peak memory 215068 kb
Host smart-91527096-3711-457d-9d75-b0559dc6b9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235440461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.235440461
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3856724678
Short name T234
Test name
Test status
Simulation time 2229499136 ps
CPU time 23.41 seconds
Started Apr 25 12:42:12 PM PDT 24
Finished Apr 25 12:42:42 PM PDT 24
Peak memory 212804 kb
Host smart-2ec8d01d-a6a5-4e6b-b996-44818c320d99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856724678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3856724678
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.385024616
Short name T152
Test name
Test status
Simulation time 2126711026 ps
CPU time 23.07 seconds
Started Apr 25 12:42:04 PM PDT 24
Finished Apr 25 12:42:30 PM PDT 24
Peak memory 218024 kb
Host smart-f1d4f125-8fc5-4dac-aeea-52fb66b39c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385024616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.385024616
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1371556590
Short name T305
Test name
Test status
Simulation time 7856352958 ps
CPU time 104.88 seconds
Started Apr 25 12:42:12 PM PDT 24
Finished Apr 25 12:44:03 PM PDT 24
Peak memory 219540 kb
Host smart-5fe6c06b-a95e-405d-9081-1d114f49cda8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371556590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1371556590
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2889010379
Short name T348
Test name
Test status
Simulation time 4008554755 ps
CPU time 32.85 seconds
Started Apr 25 12:41:07 PM PDT 24
Finished Apr 25 12:41:40 PM PDT 24
Peak memory 211520 kb
Host smart-8f31e546-e625-4e3d-af2a-53178da634b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889010379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2889010379
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3912244705
Short name T181
Test name
Test status
Simulation time 73958280774 ps
CPU time 464.18 seconds
Started Apr 25 12:41:18 PM PDT 24
Finished Apr 25 12:49:03 PM PDT 24
Peak memory 238200 kb
Host smart-658bc4e0-e691-45a9-b0a8-5de4a3a28997
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912244705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3912244705
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.971991666
Short name T223
Test name
Test status
Simulation time 31857449266 ps
CPU time 62.75 seconds
Started Apr 25 12:41:07 PM PDT 24
Finished Apr 25 12:42:11 PM PDT 24
Peak memory 215352 kb
Host smart-bbf28304-b05e-4d5e-9b53-192969efb9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971991666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.971991666
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1059639675
Short name T351
Test name
Test status
Simulation time 2393428398 ps
CPU time 23.89 seconds
Started Apr 25 12:41:16 PM PDT 24
Finished Apr 25 12:41:41 PM PDT 24
Peak memory 211780 kb
Host smart-eb03a2af-4b6a-427c-86f2-71f4a64b2613
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1059639675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1059639675
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2855402687
Short name T126
Test name
Test status
Simulation time 360590330 ps
CPU time 19.61 seconds
Started Apr 25 12:41:11 PM PDT 24
Finished Apr 25 12:41:31 PM PDT 24
Peak memory 217020 kb
Host smart-d1877179-81b6-4a23-a849-1e14f55f4fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855402687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2855402687
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1814660953
Short name T256
Test name
Test status
Simulation time 17442777583 ps
CPU time 66.35 seconds
Started Apr 25 12:41:15 PM PDT 24
Finished Apr 25 12:42:22 PM PDT 24
Peak memory 219492 kb
Host smart-6172ff8f-023e-429c-a1bf-47ac42d887fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814660953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1814660953
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2028949898
Short name T183
Test name
Test status
Simulation time 4385819111 ps
CPU time 16.12 seconds
Started Apr 25 12:41:25 PM PDT 24
Finished Apr 25 12:41:41 PM PDT 24
Peak memory 212448 kb
Host smart-12f5fea8-faac-4e6a-9c7d-6e2715caf6fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028949898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2028949898
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.521375825
Short name T49
Test name
Test status
Simulation time 330850006325 ps
CPU time 404.49 seconds
Started Apr 25 12:41:00 PM PDT 24
Finished Apr 25 12:47:45 PM PDT 24
Peak memory 229016 kb
Host smart-3139feaa-9029-4b8a-90ef-997c736157c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521375825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.521375825
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.279993705
Short name T233
Test name
Test status
Simulation time 6682658896 ps
CPU time 41.21 seconds
Started Apr 25 12:41:02 PM PDT 24
Finished Apr 25 12:41:43 PM PDT 24
Peak memory 215236 kb
Host smart-a74b5cde-f250-4573-8bb9-39b0a58be2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279993705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.279993705
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1338840115
Short name T138
Test name
Test status
Simulation time 185102198 ps
CPU time 10.4 seconds
Started Apr 25 12:41:33 PM PDT 24
Finished Apr 25 12:41:44 PM PDT 24
Peak memory 212308 kb
Host smart-b6cc7f8e-ef19-4914-a5d4-3a02708cbc32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1338840115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1338840115
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.4032452974
Short name T263
Test name
Test status
Simulation time 20786049262 ps
CPU time 68.97 seconds
Started Apr 25 12:41:22 PM PDT 24
Finished Apr 25 12:42:32 PM PDT 24
Peak memory 217700 kb
Host smart-c9629ae2-88ab-4fb0-a050-138d870d5b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032452974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.4032452974
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2393406446
Short name T282
Test name
Test status
Simulation time 4364852812 ps
CPU time 37.13 seconds
Started Apr 25 12:41:10 PM PDT 24
Finished Apr 25 12:41:47 PM PDT 24
Peak memory 219504 kb
Host smart-8dbb73de-a44a-4e8d-8c3f-83e1fcff4dd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393406446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2393406446
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3165579763
Short name T212
Test name
Test status
Simulation time 5536627050 ps
CPU time 24.93 seconds
Started Apr 25 12:41:19 PM PDT 24
Finished Apr 25 12:41:45 PM PDT 24
Peak memory 212344 kb
Host smart-8b61172a-89e1-48c6-bfbe-16af2c54b75b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165579763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3165579763
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2780329527
Short name T290
Test name
Test status
Simulation time 3015114369 ps
CPU time 197.78 seconds
Started Apr 25 12:41:26 PM PDT 24
Finished Apr 25 12:44:45 PM PDT 24
Peak memory 217924 kb
Host smart-e5e0e456-7185-4e4b-aa3d-08b77de5d241
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780329527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2780329527
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3557564480
Short name T216
Test name
Test status
Simulation time 5031246701 ps
CPU time 32.76 seconds
Started Apr 25 12:41:16 PM PDT 24
Finished Apr 25 12:41:50 PM PDT 24
Peak memory 214148 kb
Host smart-778977b9-9e2b-4000-b0be-ed7312d3ec1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557564480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3557564480
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.189797389
Short name T258
Test name
Test status
Simulation time 2158934917 ps
CPU time 17.33 seconds
Started Apr 25 12:41:14 PM PDT 24
Finished Apr 25 12:41:32 PM PDT 24
Peak memory 211636 kb
Host smart-c95d3f2f-5ff2-412c-b4f6-4a77104899b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=189797389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.189797389
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2648536837
Short name T357
Test name
Test status
Simulation time 1909566054 ps
CPU time 20.41 seconds
Started Apr 25 12:41:23 PM PDT 24
Finished Apr 25 12:41:44 PM PDT 24
Peak memory 217376 kb
Host smart-a9dc9523-9c19-4564-9042-fb12dc1f4fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648536837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2648536837
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3690734707
Short name T175
Test name
Test status
Simulation time 16946333204 ps
CPU time 36.98 seconds
Started Apr 25 12:41:20 PM PDT 24
Finished Apr 25 12:41:58 PM PDT 24
Peak memory 213200 kb
Host smart-9811fa43-f74e-4781-a2b8-e019cd56bf75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690734707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3690734707
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2917049617
Short name T273
Test name
Test status
Simulation time 3782598121 ps
CPU time 29.11 seconds
Started Apr 25 12:41:26 PM PDT 24
Finished Apr 25 12:41:56 PM PDT 24
Peak memory 212072 kb
Host smart-9fc54e5d-f93e-450e-87bd-85a8b45dc74b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917049617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2917049617
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.839407530
Short name T224
Test name
Test status
Simulation time 272923929072 ps
CPU time 1074.23 seconds
Started Apr 25 12:41:18 PM PDT 24
Finished Apr 25 12:59:13 PM PDT 24
Peak memory 240964 kb
Host smart-64348073-eae7-4718-a384-5c47bb150269
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839407530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.839407530
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.856127644
Short name T158
Test name
Test status
Simulation time 11236034978 ps
CPU time 51.35 seconds
Started Apr 25 12:41:36 PM PDT 24
Finished Apr 25 12:42:28 PM PDT 24
Peak memory 215376 kb
Host smart-dcb425a8-7682-46f7-8835-aa104f81e6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856127644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.856127644
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.927186129
Short name T289
Test name
Test status
Simulation time 2874058375 ps
CPU time 25.91 seconds
Started Apr 25 12:41:26 PM PDT 24
Finished Apr 25 12:41:53 PM PDT 24
Peak memory 212496 kb
Host smart-af854b0e-7057-4645-b2e6-3fb47bc2ae8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=927186129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.927186129
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3049172848
Short name T338
Test name
Test status
Simulation time 6570852050 ps
CPU time 65.82 seconds
Started Apr 25 12:41:19 PM PDT 24
Finished Apr 25 12:42:25 PM PDT 24
Peak memory 218068 kb
Host smart-83afa13b-475a-4114-8e69-1b5e9100576a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049172848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3049172848
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3469628207
Short name T267
Test name
Test status
Simulation time 776230215 ps
CPU time 30.76 seconds
Started Apr 25 12:41:21 PM PDT 24
Finished Apr 25 12:41:52 PM PDT 24
Peak memory 216472 kb
Host smart-98b5f1a8-3e84-4e87-889b-6eb0fb818eca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469628207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3469628207
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2075277857
Short name T275
Test name
Test status
Simulation time 8465660201 ps
CPU time 24.21 seconds
Started Apr 25 12:41:18 PM PDT 24
Finished Apr 25 12:41:43 PM PDT 24
Peak memory 211640 kb
Host smart-9061165d-566f-404d-937e-216b7d01f334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075277857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2075277857
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2093543021
Short name T334
Test name
Test status
Simulation time 7733068187 ps
CPU time 276.01 seconds
Started Apr 25 12:41:23 PM PDT 24
Finished Apr 25 12:46:00 PM PDT 24
Peak memory 234172 kb
Host smart-442aadae-d144-4bf6-98b3-41866359582b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093543021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2093543021
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1189566444
Short name T39
Test name
Test status
Simulation time 22652462085 ps
CPU time 38.26 seconds
Started Apr 25 12:41:25 PM PDT 24
Finished Apr 25 12:42:04 PM PDT 24
Peak memory 215276 kb
Host smart-d3adddb8-571a-41cc-bfad-f8213bef57c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189566444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1189566444
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3298638385
Short name T137
Test name
Test status
Simulation time 2153095118 ps
CPU time 22.71 seconds
Started Apr 25 12:41:13 PM PDT 24
Finished Apr 25 12:41:42 PM PDT 24
Peak memory 212576 kb
Host smart-453dc33c-5b29-4755-919a-222e8841e6fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3298638385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3298638385
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.912261520
Short name T243
Test name
Test status
Simulation time 351483505 ps
CPU time 19.9 seconds
Started Apr 25 12:41:18 PM PDT 24
Finished Apr 25 12:41:39 PM PDT 24
Peak memory 213860 kb
Host smart-1f22cfec-933d-42d3-a28c-c32e61964980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912261520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.912261520
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3484594992
Short name T253
Test name
Test status
Simulation time 6375686308 ps
CPU time 54.37 seconds
Started Apr 25 12:41:16 PM PDT 24
Finished Apr 25 12:42:11 PM PDT 24
Peak memory 217748 kb
Host smart-c63f3ff5-7431-49c6-8091-99cf9cbc33d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484594992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3484594992
Directory /workspace/9.rom_ctrl_stress_all/latest
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