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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.59 96.97 93.15 97.88 100.00 98.69 98.03 98.37


Total test records in report: 462
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T296 /workspace/coverage/default/48.rom_ctrl_alert_test.4267968386 Apr 30 12:41:15 PM PDT 24 Apr 30 12:41:35 PM PDT 24 1768027195 ps
T297 /workspace/coverage/default/35.rom_ctrl_smoke.782404213 Apr 30 12:40:43 PM PDT 24 Apr 30 12:41:42 PM PDT 24 24192828326 ps
T298 /workspace/coverage/default/12.rom_ctrl_alert_test.1024682486 Apr 30 12:39:53 PM PDT 24 Apr 30 12:40:02 PM PDT 24 717791399 ps
T299 /workspace/coverage/default/24.rom_ctrl_smoke.3500156934 Apr 30 12:40:18 PM PDT 24 Apr 30 12:41:07 PM PDT 24 16487574163 ps
T300 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1368097557 Apr 30 12:39:54 PM PDT 24 Apr 30 12:40:14 PM PDT 24 346064067 ps
T301 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3069483916 Apr 30 12:39:38 PM PDT 24 Apr 30 12:49:48 PM PDT 24 64881380627 ps
T302 /workspace/coverage/default/27.rom_ctrl_alert_test.1468500490 Apr 30 12:40:18 PM PDT 24 Apr 30 12:40:38 PM PDT 24 2590202142 ps
T303 /workspace/coverage/default/34.rom_ctrl_stress_all.3633813903 Apr 30 12:40:38 PM PDT 24 Apr 30 12:41:07 PM PDT 24 3233352041 ps
T304 /workspace/coverage/default/26.rom_ctrl_alert_test.3703326261 Apr 30 12:40:18 PM PDT 24 Apr 30 12:40:35 PM PDT 24 8835597866 ps
T305 /workspace/coverage/default/20.rom_ctrl_stress_all.3345084358 Apr 30 12:40:12 PM PDT 24 Apr 30 12:42:48 PM PDT 24 59707466612 ps
T306 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1703079553 Apr 30 12:39:45 PM PDT 24 Apr 30 12:40:47 PM PDT 24 7445511234 ps
T307 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.4276557476 Apr 30 12:39:53 PM PDT 24 Apr 30 12:40:30 PM PDT 24 15441649255 ps
T308 /workspace/coverage/default/9.rom_ctrl_stress_all.1590959094 Apr 30 12:39:47 PM PDT 24 Apr 30 12:40:54 PM PDT 24 3806708621 ps
T309 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3880594998 Apr 30 12:40:27 PM PDT 24 Apr 30 12:41:18 PM PDT 24 21850697760 ps
T310 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2955588619 Apr 30 12:41:15 PM PDT 24 Apr 30 12:49:28 PM PDT 24 47571729978 ps
T15 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2981839917 Apr 30 12:40:51 PM PDT 24 Apr 30 01:30:09 PM PDT 24 80172321421 ps
T311 /workspace/coverage/default/18.rom_ctrl_stress_all.3749169726 Apr 30 12:40:04 PM PDT 24 Apr 30 12:41:19 PM PDT 24 30576481494 ps
T312 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2235219238 Apr 30 12:40:18 PM PDT 24 Apr 30 12:40:41 PM PDT 24 2061086028 ps
T313 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1558776899 Apr 30 12:39:50 PM PDT 24 Apr 30 12:40:31 PM PDT 24 4767626260 ps
T314 /workspace/coverage/default/42.rom_ctrl_smoke.1008753138 Apr 30 12:41:00 PM PDT 24 Apr 30 12:41:27 PM PDT 24 3486952281 ps
T315 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2208820803 Apr 30 12:40:19 PM PDT 24 Apr 30 12:40:30 PM PDT 24 1957432396 ps
T316 /workspace/coverage/default/12.rom_ctrl_smoke.1415621110 Apr 30 12:39:53 PM PDT 24 Apr 30 12:40:13 PM PDT 24 1867659692 ps
T52 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3727142470 Apr 30 12:40:19 PM PDT 24 Apr 30 01:28:06 PM PDT 24 77319645463 ps
T317 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1428926734 Apr 30 12:40:53 PM PDT 24 Apr 30 12:45:55 PM PDT 24 9796775409 ps
T318 /workspace/coverage/default/28.rom_ctrl_smoke.1284689616 Apr 30 12:40:21 PM PDT 24 Apr 30 12:41:20 PM PDT 24 23288729706 ps
T319 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.4086920768 Apr 30 12:41:08 PM PDT 24 Apr 30 12:42:01 PM PDT 24 11405224523 ps
T320 /workspace/coverage/default/46.rom_ctrl_stress_all.4117162664 Apr 30 12:41:09 PM PDT 24 Apr 30 12:41:53 PM PDT 24 1547977856 ps
T321 /workspace/coverage/default/31.rom_ctrl_smoke.2696325159 Apr 30 12:40:33 PM PDT 24 Apr 30 12:41:09 PM PDT 24 8601946876 ps
T322 /workspace/coverage/default/5.rom_ctrl_alert_test.62673985 Apr 30 12:39:47 PM PDT 24 Apr 30 12:40:12 PM PDT 24 10997872633 ps
T323 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2779844571 Apr 30 12:39:49 PM PDT 24 Apr 30 12:40:17 PM PDT 24 1208250372 ps
T324 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4018132221 Apr 30 12:40:51 PM PDT 24 Apr 30 12:41:11 PM PDT 24 1319697905 ps
T325 /workspace/coverage/default/13.rom_ctrl_alert_test.2766010974 Apr 30 12:39:52 PM PDT 24 Apr 30 12:40:22 PM PDT 24 14364562208 ps
T326 /workspace/coverage/default/10.rom_ctrl_alert_test.1982268151 Apr 30 12:39:55 PM PDT 24 Apr 30 12:40:16 PM PDT 24 10747150721 ps
T53 /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3136681918 Apr 30 12:40:10 PM PDT 24 Apr 30 01:07:26 PM PDT 24 186731440520 ps
T327 /workspace/coverage/default/37.rom_ctrl_alert_test.938846236 Apr 30 12:40:52 PM PDT 24 Apr 30 12:41:01 PM PDT 24 174554156 ps
T328 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2786312927 Apr 30 12:40:41 PM PDT 24 Apr 30 12:41:33 PM PDT 24 21954802064 ps
T329 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3854315243 Apr 30 12:40:27 PM PDT 24 Apr 30 12:40:57 PM PDT 24 3342547841 ps
T330 /workspace/coverage/default/16.rom_ctrl_smoke.3739058282 Apr 30 12:40:02 PM PDT 24 Apr 30 12:41:09 PM PDT 24 7500430237 ps
T331 /workspace/coverage/default/24.rom_ctrl_stress_all.36506406 Apr 30 12:40:20 PM PDT 24 Apr 30 12:41:25 PM PDT 24 25603116387 ps
T332 /workspace/coverage/default/46.rom_ctrl_smoke.1249232718 Apr 30 12:41:09 PM PDT 24 Apr 30 12:41:54 PM PDT 24 3905275210 ps
T333 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.582525521 Apr 30 12:40:03 PM PDT 24 Apr 30 12:40:14 PM PDT 24 363229838 ps
T334 /workspace/coverage/default/16.rom_ctrl_stress_all.3108026749 Apr 30 12:40:03 PM PDT 24 Apr 30 12:40:26 PM PDT 24 4809193587 ps
T335 /workspace/coverage/default/38.rom_ctrl_alert_test.3203145600 Apr 30 12:40:50 PM PDT 24 Apr 30 12:41:07 PM PDT 24 2900821092 ps
T336 /workspace/coverage/default/25.rom_ctrl_smoke.3974121053 Apr 30 12:40:20 PM PDT 24 Apr 30 12:41:10 PM PDT 24 19081498075 ps
T337 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3052325682 Apr 30 12:39:56 PM PDT 24 Apr 30 12:40:15 PM PDT 24 339256715 ps
T338 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.213548281 Apr 30 12:41:06 PM PDT 24 Apr 30 01:05:40 PM PDT 24 143117377658 ps
T339 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.977129683 Apr 30 12:40:18 PM PDT 24 Apr 30 12:40:52 PM PDT 24 6963794358 ps
T340 /workspace/coverage/default/4.rom_ctrl_alert_test.1827569318 Apr 30 12:39:49 PM PDT 24 Apr 30 12:40:15 PM PDT 24 11622975433 ps
T341 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1541712347 Apr 30 12:41:01 PM PDT 24 Apr 30 12:41:12 PM PDT 24 199623617 ps
T342 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1273753292 Apr 30 12:40:51 PM PDT 24 Apr 30 12:41:24 PM PDT 24 3689853887 ps
T343 /workspace/coverage/default/39.rom_ctrl_stress_all.3897216907 Apr 30 12:40:51 PM PDT 24 Apr 30 12:43:39 PM PDT 24 15427458147 ps
T344 /workspace/coverage/default/42.rom_ctrl_alert_test.3679420473 Apr 30 12:41:02 PM PDT 24 Apr 30 12:41:19 PM PDT 24 2513758753 ps
T345 /workspace/coverage/default/9.rom_ctrl_alert_test.1816258896 Apr 30 12:39:57 PM PDT 24 Apr 30 12:40:12 PM PDT 24 1302410833 ps
T346 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2007084901 Apr 30 12:39:43 PM PDT 24 Apr 30 12:40:10 PM PDT 24 5871212335 ps
T347 /workspace/coverage/default/8.rom_ctrl_stress_all.46837633 Apr 30 12:39:51 PM PDT 24 Apr 30 12:40:19 PM PDT 24 770707655 ps
T348 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2842527298 Apr 30 12:39:55 PM PDT 24 Apr 30 12:44:17 PM PDT 24 26928755188 ps
T349 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2927045166 Apr 30 12:39:55 PM PDT 24 Apr 30 12:40:22 PM PDT 24 16531599424 ps
T350 /workspace/coverage/default/40.rom_ctrl_smoke.2601495571 Apr 30 12:40:51 PM PDT 24 Apr 30 12:41:57 PM PDT 24 30265933709 ps
T351 /workspace/coverage/default/21.rom_ctrl_stress_all.214824980 Apr 30 12:40:14 PM PDT 24 Apr 30 12:42:17 PM PDT 24 30887037993 ps
T352 /workspace/coverage/default/21.rom_ctrl_smoke.377355245 Apr 30 12:40:13 PM PDT 24 Apr 30 12:41:25 PM PDT 24 7858477759 ps
T35 /workspace/coverage/default/2.rom_ctrl_sec_cm.1341731031 Apr 30 12:39:47 PM PDT 24 Apr 30 12:43:42 PM PDT 24 6488165509 ps
T353 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3971597293 Apr 30 12:41:00 PM PDT 24 Apr 30 12:49:15 PM PDT 24 218460107941 ps
T354 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2049510636 Apr 30 12:40:35 PM PDT 24 Apr 30 12:41:09 PM PDT 24 4369795822 ps
T355 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2621628539 Apr 30 12:40:11 PM PDT 24 Apr 30 12:41:10 PM PDT 24 37567183638 ps
T356 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3072619654 Apr 30 12:40:03 PM PDT 24 Apr 30 12:45:39 PM PDT 24 8993790490 ps
T357 /workspace/coverage/default/1.rom_ctrl_alert_test.2210690872 Apr 30 12:39:37 PM PDT 24 Apr 30 12:40:02 PM PDT 24 2844071958 ps
T358 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2082287912 Apr 30 12:40:20 PM PDT 24 Apr 30 12:46:51 PM PDT 24 39665995147 ps
T57 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2100489671 Apr 30 12:23:54 PM PDT 24 Apr 30 12:25:52 PM PDT 24 28678271177 ps
T58 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.569215324 Apr 30 12:18:17 PM PDT 24 Apr 30 12:18:44 PM PDT 24 38309565176 ps
T59 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.638451926 Apr 30 12:23:39 PM PDT 24 Apr 30 12:24:17 PM PDT 24 707719621 ps
T359 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.622777661 Apr 30 12:23:42 PM PDT 24 Apr 30 12:24:15 PM PDT 24 3676960645 ps
T95 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.920266311 Apr 30 12:18:18 PM PDT 24 Apr 30 12:18:47 PM PDT 24 3515890803 ps
T63 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3882680815 Apr 30 12:22:32 PM PDT 24 Apr 30 12:25:32 PM PDT 24 23142985862 ps
T64 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.994486418 Apr 30 12:17:18 PM PDT 24 Apr 30 12:17:32 PM PDT 24 775989524 ps
T96 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4110884706 Apr 30 12:22:07 PM PDT 24 Apr 30 12:22:19 PM PDT 24 1965642705 ps
T360 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2136014526 Apr 30 12:17:13 PM PDT 24 Apr 30 12:17:44 PM PDT 24 3660585489 ps
T97 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2865496109 Apr 30 12:23:40 PM PDT 24 Apr 30 12:24:11 PM PDT 24 4339239792 ps
T65 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.166623197 Apr 30 12:21:58 PM PDT 24 Apr 30 12:22:10 PM PDT 24 689248063 ps
T361 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4155663500 Apr 30 12:23:07 PM PDT 24 Apr 30 12:23:32 PM PDT 24 36674350797 ps
T66 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.430047155 Apr 30 12:22:14 PM PDT 24 Apr 30 12:22:42 PM PDT 24 3117859355 ps
T67 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3143929198 Apr 30 12:18:49 PM PDT 24 Apr 30 12:19:20 PM PDT 24 13647633133 ps
T54 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3973315473 Apr 30 12:22:04 PM PDT 24 Apr 30 12:23:47 PM PDT 24 66805963602 ps
T362 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2349116376 Apr 30 12:17:16 PM PDT 24 Apr 30 12:17:40 PM PDT 24 5015787254 ps
T363 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2848248478 Apr 30 12:23:39 PM PDT 24 Apr 30 12:24:12 PM PDT 24 4508771220 ps
T364 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4129361485 Apr 30 12:22:13 PM PDT 24 Apr 30 12:22:46 PM PDT 24 7191866032 ps
T365 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.328371418 Apr 30 12:19:40 PM PDT 24 Apr 30 12:19:55 PM PDT 24 942364823 ps
T98 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1967021440 Apr 30 12:23:25 PM PDT 24 Apr 30 12:23:57 PM PDT 24 7041920618 ps
T366 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2668852219 Apr 30 12:24:13 PM PDT 24 Apr 30 12:24:34 PM PDT 24 21470899313 ps
T55 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.858427065 Apr 30 12:17:03 PM PDT 24 Apr 30 12:19:48 PM PDT 24 23590025768 ps
T56 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1539367673 Apr 30 12:17:18 PM PDT 24 Apr 30 12:19:52 PM PDT 24 698848371 ps
T105 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2238028523 Apr 30 12:23:35 PM PDT 24 Apr 30 12:26:16 PM PDT 24 8365990647 ps
T111 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1128952375 Apr 30 12:20:42 PM PDT 24 Apr 30 12:22:06 PM PDT 24 286823900 ps
T99 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2691832771 Apr 30 12:21:43 PM PDT 24 Apr 30 12:21:53 PM PDT 24 477758854 ps
T367 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2568041509 Apr 30 12:23:41 PM PDT 24 Apr 30 12:23:50 PM PDT 24 186934406 ps
T368 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2568123871 Apr 30 12:17:54 PM PDT 24 Apr 30 12:18:19 PM PDT 24 5688408879 ps
T369 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4095223344 Apr 30 12:17:17 PM PDT 24 Apr 30 12:17:31 PM PDT 24 1385457741 ps
T108 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2787494947 Apr 30 12:22:00 PM PDT 24 Apr 30 12:24:34 PM PDT 24 1260939653 ps
T370 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3022542824 Apr 30 12:23:55 PM PDT 24 Apr 30 12:24:06 PM PDT 24 184759021 ps
T371 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3416221659 Apr 30 12:22:14 PM PDT 24 Apr 30 12:22:31 PM PDT 24 514829564 ps
T113 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.810466094 Apr 30 12:22:14 PM PDT 24 Apr 30 12:23:53 PM PDT 24 14614553318 ps
T372 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4269561717 Apr 30 12:22:52 PM PDT 24 Apr 30 12:24:18 PM PDT 24 1161486498 ps
T68 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.257986344 Apr 30 12:22:58 PM PDT 24 Apr 30 12:26:12 PM PDT 24 47138774141 ps
T373 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3819276045 Apr 30 12:21:11 PM PDT 24 Apr 30 12:21:36 PM PDT 24 11311447870 ps
T374 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.749926347 Apr 30 12:17:10 PM PDT 24 Apr 30 12:17:23 PM PDT 24 2298653255 ps
T375 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3967319937 Apr 30 12:21:54 PM PDT 24 Apr 30 12:22:21 PM PDT 24 11403565341 ps
T376 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.14279021 Apr 30 12:22:58 PM PDT 24 Apr 30 12:23:10 PM PDT 24 507261331 ps
T69 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3546536285 Apr 30 12:17:10 PM PDT 24 Apr 30 12:17:19 PM PDT 24 167336932 ps
T377 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2591359006 Apr 30 12:18:50 PM PDT 24 Apr 30 12:19:19 PM PDT 24 4105217660 ps
T70 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2909670157 Apr 30 12:16:58 PM PDT 24 Apr 30 12:18:09 PM PDT 24 10286491956 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1978338147 Apr 30 12:22:02 PM PDT 24 Apr 30 12:22:16 PM PDT 24 902545378 ps
T379 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3312965792 Apr 30 12:17:13 PM PDT 24 Apr 30 12:17:41 PM PDT 24 3022662527 ps
T380 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3397565140 Apr 30 12:18:23 PM PDT 24 Apr 30 12:18:59 PM PDT 24 17083321202 ps
T381 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2631940005 Apr 30 12:22:16 PM PDT 24 Apr 30 12:22:37 PM PDT 24 3771540805 ps
T71 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3050311280 Apr 30 12:23:18 PM PDT 24 Apr 30 12:24:16 PM PDT 24 1077787543 ps
T382 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.241191747 Apr 30 12:20:05 PM PDT 24 Apr 30 12:20:29 PM PDT 24 5386613508 ps
T383 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2640093912 Apr 30 12:23:01 PM PDT 24 Apr 30 12:23:34 PM PDT 24 7042968308 ps
T384 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3804265678 Apr 30 12:20:31 PM PDT 24 Apr 30 12:20:40 PM PDT 24 183638851 ps
T100 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.508413545 Apr 30 12:21:57 PM PDT 24 Apr 30 12:22:18 PM PDT 24 1334368040 ps
T385 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1977691943 Apr 30 12:20:56 PM PDT 24 Apr 30 12:21:10 PM PDT 24 3447443542 ps
T101 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3209672158 Apr 30 12:19:08 PM PDT 24 Apr 30 12:19:42 PM PDT 24 18895767916 ps
T386 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1920579920 Apr 30 12:22:06 PM PDT 24 Apr 30 12:23:11 PM PDT 24 9007022452 ps
T387 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2743431305 Apr 30 12:22:15 PM PDT 24 Apr 30 12:22:25 PM PDT 24 167583965 ps
T102 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3286394576 Apr 30 12:20:43 PM PDT 24 Apr 30 12:20:52 PM PDT 24 345327446 ps
T388 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3662633239 Apr 30 12:20:34 PM PDT 24 Apr 30 12:21:04 PM PDT 24 24010417674 ps
T389 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2946962334 Apr 30 12:22:06 PM PDT 24 Apr 30 12:22:21 PM PDT 24 13393358924 ps
T106 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1277970339 Apr 30 12:22:00 PM PDT 24 Apr 30 12:24:40 PM PDT 24 9551653984 ps
T390 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1460165320 Apr 30 12:23:04 PM PDT 24 Apr 30 12:23:13 PM PDT 24 1496965764 ps
T391 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2459414297 Apr 30 12:21:56 PM PDT 24 Apr 30 12:22:54 PM PDT 24 3538228402 ps
T392 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.320091275 Apr 30 12:22:19 PM PDT 24 Apr 30 12:22:38 PM PDT 24 16542324322 ps
T393 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.200737329 Apr 30 12:22:13 PM PDT 24 Apr 30 12:23:59 PM PDT 24 67658083557 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.850222994 Apr 30 12:17:17 PM PDT 24 Apr 30 12:17:37 PM PDT 24 1175359068 ps
T395 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2439972042 Apr 30 12:18:41 PM PDT 24 Apr 30 12:19:12 PM PDT 24 3289608479 ps
T77 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.411992466 Apr 30 12:18:47 PM PDT 24 Apr 30 12:19:23 PM PDT 24 3720431090 ps
T396 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1572202489 Apr 30 12:22:14 PM PDT 24 Apr 30 12:22:41 PM PDT 24 6222502310 ps
T107 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1643972544 Apr 30 12:23:47 PM PDT 24 Apr 30 12:26:40 PM PDT 24 4359448778 ps
T397 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1402631552 Apr 30 12:23:03 PM PDT 24 Apr 30 12:23:31 PM PDT 24 13074544285 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1324942145 Apr 30 12:22:02 PM PDT 24 Apr 30 12:22:34 PM PDT 24 7000561911 ps
T109 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2532283028 Apr 30 12:20:43 PM PDT 24 Apr 30 12:23:29 PM PDT 24 925827964 ps
T399 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3372569465 Apr 30 12:18:20 PM PDT 24 Apr 30 12:18:52 PM PDT 24 6653539769 ps
T78 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1666926733 Apr 30 12:17:16 PM PDT 24 Apr 30 12:19:19 PM PDT 24 54673242493 ps
T400 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2826942837 Apr 30 12:23:00 PM PDT 24 Apr 30 12:24:03 PM PDT 24 5678927736 ps
T401 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4084549506 Apr 30 12:22:07 PM PDT 24 Apr 30 12:22:43 PM PDT 24 4013994126 ps
T402 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3241682137 Apr 30 12:23:41 PM PDT 24 Apr 30 12:24:09 PM PDT 24 3566645060 ps
T79 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2388295929 Apr 30 12:18:40 PM PDT 24 Apr 30 12:21:54 PM PDT 24 49214875553 ps
T110 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1316989037 Apr 30 12:21:56 PM PDT 24 Apr 30 12:23:32 PM PDT 24 6136907693 ps
T112 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3088556552 Apr 30 12:22:59 PM PDT 24 Apr 30 12:25:42 PM PDT 24 4875448493 ps
T403 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2471378736 Apr 30 12:22:51 PM PDT 24 Apr 30 12:23:23 PM PDT 24 35837313315 ps
T404 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.428957014 Apr 30 12:20:07 PM PDT 24 Apr 30 12:22:07 PM PDT 24 103392429441 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4046991937 Apr 30 12:23:04 PM PDT 24 Apr 30 12:23:33 PM PDT 24 20668912613 ps
T406 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1637778286 Apr 30 12:22:55 PM PDT 24 Apr 30 12:23:25 PM PDT 24 8036793700 ps
T407 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.93527149 Apr 30 12:17:10 PM PDT 24 Apr 30 12:17:42 PM PDT 24 73728051077 ps
T408 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1337020167 Apr 30 12:21:56 PM PDT 24 Apr 30 12:22:11 PM PDT 24 1663489494 ps
T409 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.297958566 Apr 30 12:19:54 PM PDT 24 Apr 30 12:20:30 PM PDT 24 7504640814 ps
T410 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3017814134 Apr 30 12:21:58 PM PDT 24 Apr 30 12:22:30 PM PDT 24 8184827796 ps
T411 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2738647075 Apr 30 12:22:54 PM PDT 24 Apr 30 12:23:06 PM PDT 24 516566741 ps
T412 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4089398690 Apr 30 12:21:58 PM PDT 24 Apr 30 12:22:33 PM PDT 24 4027833995 ps
T413 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.453752066 Apr 30 12:21:58 PM PDT 24 Apr 30 12:22:07 PM PDT 24 660160994 ps
T414 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2457943218 Apr 30 12:19:26 PM PDT 24 Apr 30 12:19:57 PM PDT 24 7054122163 ps
T415 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.175547675 Apr 30 12:17:17 PM PDT 24 Apr 30 12:19:01 PM PDT 24 4269094368 ps
T416 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.326723909 Apr 30 12:22:11 PM PDT 24 Apr 30 12:22:42 PM PDT 24 23967277565 ps
T417 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.356193033 Apr 30 12:16:58 PM PDT 24 Apr 30 12:17:07 PM PDT 24 169019350 ps
T418 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2315751596 Apr 30 12:22:46 PM PDT 24 Apr 30 12:23:10 PM PDT 24 2470447363 ps
T419 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3452095789 Apr 30 12:22:45 PM PDT 24 Apr 30 12:23:14 PM PDT 24 14779122328 ps
T420 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.767993737 Apr 30 12:17:17 PM PDT 24 Apr 30 12:19:53 PM PDT 24 366467079 ps
T421 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3146333651 Apr 30 12:19:25 PM PDT 24 Apr 30 12:19:41 PM PDT 24 2231757991 ps
T422 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2358927763 Apr 30 12:22:59 PM PDT 24 Apr 30 12:23:28 PM PDT 24 2393007148 ps
T423 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1373358540 Apr 30 12:22:44 PM PDT 24 Apr 30 12:23:01 PM PDT 24 1415699202 ps
T424 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.715393097 Apr 30 12:18:18 PM PDT 24 Apr 30 12:18:47 PM PDT 24 3553467432 ps
T425 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3717418098 Apr 30 12:22:09 PM PDT 24 Apr 30 12:22:41 PM PDT 24 3771814971 ps
T426 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1596202632 Apr 30 12:21:58 PM PDT 24 Apr 30 12:22:53 PM PDT 24 4299479772 ps
T83 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3742694034 Apr 30 12:18:19 PM PDT 24 Apr 30 12:18:39 PM PDT 24 2055636564 ps
T114 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2260395493 Apr 30 12:22:46 PM PDT 24 Apr 30 12:24:18 PM PDT 24 8732317713 ps
T427 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.666525990 Apr 30 12:24:30 PM PDT 24 Apr 30 12:25:50 PM PDT 24 233491986 ps
T428 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.203270674 Apr 30 12:22:47 PM PDT 24 Apr 30 12:24:26 PM PDT 24 11286558747 ps
T80 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1315147857 Apr 30 12:23:04 PM PDT 24 Apr 30 12:24:20 PM PDT 24 11990745475 ps
T429 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.889262353 Apr 30 12:17:10 PM PDT 24 Apr 30 12:17:19 PM PDT 24 750726712 ps
T430 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3685743403 Apr 30 12:22:59 PM PDT 24 Apr 30 12:23:23 PM PDT 24 6868211546 ps
T431 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2227337255 Apr 30 12:21:42 PM PDT 24 Apr 30 12:22:11 PM PDT 24 17760606803 ps
T432 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1452116273 Apr 30 12:23:03 PM PDT 24 Apr 30 12:24:41 PM PDT 24 6916272606 ps
T433 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3862786318 Apr 30 12:21:56 PM PDT 24 Apr 30 12:22:05 PM PDT 24 178408019 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1295525208 Apr 30 12:17:07 PM PDT 24 Apr 30 12:17:43 PM PDT 24 15766981936 ps
T435 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.783142458 Apr 30 12:22:58 PM PDT 24 Apr 30 12:23:18 PM PDT 24 1798107792 ps
T436 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3431816258 Apr 30 12:23:02 PM PDT 24 Apr 30 12:23:29 PM PDT 24 3105748569 ps
T437 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2254590433 Apr 30 12:23:54 PM PDT 24 Apr 30 12:24:31 PM PDT 24 32217047538 ps
T438 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.507651659 Apr 30 12:22:07 PM PDT 24 Apr 30 12:22:30 PM PDT 24 3678179592 ps
T81 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1523358585 Apr 30 12:23:54 PM PDT 24 Apr 30 12:25:54 PM PDT 24 58917406363 ps
T439 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.556297087 Apr 30 12:17:18 PM PDT 24 Apr 30 12:17:57 PM PDT 24 17476621566 ps
T440 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1711972582 Apr 30 12:22:27 PM PDT 24 Apr 30 12:22:36 PM PDT 24 174308387 ps
T441 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3367053925 Apr 30 12:17:36 PM PDT 24 Apr 30 12:17:48 PM PDT 24 3812933612 ps
T442 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4102132739 Apr 30 12:22:14 PM PDT 24 Apr 30 12:22:41 PM PDT 24 2169432445 ps
T443 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2633236630 Apr 30 12:22:16 PM PDT 24 Apr 30 12:22:43 PM PDT 24 8844155022 ps
T444 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.922013609 Apr 30 12:18:28 PM PDT 24 Apr 30 12:18:41 PM PDT 24 171074284 ps
T445 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.707339491 Apr 30 12:23:52 PM PDT 24 Apr 30 12:24:19 PM PDT 24 22357722460 ps
T446 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1980620500 Apr 30 12:22:58 PM PDT 24 Apr 30 12:23:07 PM PDT 24 313353756 ps
T447 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2950951324 Apr 30 12:21:54 PM PDT 24 Apr 30 12:22:03 PM PDT 24 678104240 ps
T448 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.384525700 Apr 30 12:22:51 PM PDT 24 Apr 30 12:23:16 PM PDT 24 34103384598 ps
T84 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3855041472 Apr 30 12:18:48 PM PDT 24 Apr 30 12:19:46 PM PDT 24 26588276495 ps
T449 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2250126553 Apr 30 12:20:17 PM PDT 24 Apr 30 12:20:26 PM PDT 24 174351089 ps
T82 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1091845166 Apr 30 12:23:34 PM PDT 24 Apr 30 12:24:00 PM PDT 24 11449025872 ps
T450 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4280889394 Apr 30 12:17:07 PM PDT 24 Apr 30 12:17:44 PM PDT 24 8696018060 ps
T451 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1363125159 Apr 30 12:19:56 PM PDT 24 Apr 30 12:21:36 PM PDT 24 23678827541 ps
T452 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3576206600 Apr 30 12:23:07 PM PDT 24 Apr 30 12:23:16 PM PDT 24 424696161 ps
T453 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2241448134 Apr 30 12:23:05 PM PDT 24 Apr 30 12:24:56 PM PDT 24 27384738963 ps
T454 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3444195009 Apr 30 12:17:25 PM PDT 24 Apr 30 12:20:51 PM PDT 24 111769035265 ps
T455 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4008478708 Apr 30 12:20:07 PM PDT 24 Apr 30 12:20:31 PM PDT 24 2373557734 ps
T456 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2637527698 Apr 30 12:22:14 PM PDT 24 Apr 30 12:22:27 PM PDT 24 688368302 ps
T457 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.315858129 Apr 30 12:24:04 PM PDT 24 Apr 30 12:24:14 PM PDT 24 352403030 ps
T458 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1142542543 Apr 30 12:19:15 PM PDT 24 Apr 30 12:19:33 PM PDT 24 23187873746 ps
T459 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.50381830 Apr 30 12:21:14 PM PDT 24 Apr 30 12:22:46 PM PDT 24 2250985310 ps
T460 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.669103583 Apr 30 12:17:03 PM PDT 24 Apr 30 12:17:12 PM PDT 24 167468234 ps
T461 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2923839721 Apr 30 12:23:48 PM PDT 24 Apr 30 12:24:19 PM PDT 24 3256895699 ps
T462 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.327942502 Apr 30 12:19:36 PM PDT 24 Apr 30 12:19:59 PM PDT 24 4800839351 ps

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3599359054
Short name T3
Test name
Test status
Simulation time 88147468580 ps
CPU time 1558.91 seconds
Started Apr 30 12:41:09 PM PDT 24
Finished Apr 30 01:07:08 PM PDT 24
Peak memory 248420 kb
Host smart-35fd36d0-152d-4e55-ab33-85a846768e0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599359054 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3599359054
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1091808778
Short name T12
Test name
Test status
Simulation time 45527490393 ps
CPU time 486.74 seconds
Started Apr 30 12:40:19 PM PDT 24
Finished Apr 30 12:48:27 PM PDT 24
Peak memory 237972 kb
Host smart-1ebf0dd9-2060-4760-ae9c-cb32a9c449df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091808778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1091808778
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1964422567
Short name T22
Test name
Test status
Simulation time 109693250626 ps
CPU time 660.56 seconds
Started Apr 30 12:41:13 PM PDT 24
Finished Apr 30 12:52:14 PM PDT 24
Peak memory 225992 kb
Host smart-96605301-9644-4f47-b48e-d920dea2fcc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964422567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1964422567
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2238028523
Short name T105
Test name
Test status
Simulation time 8365990647 ps
CPU time 159.5 seconds
Started Apr 30 12:23:35 PM PDT 24
Finished Apr 30 12:26:16 PM PDT 24
Peak memory 213532 kb
Host smart-f9d524f6-b05d-4fd2-a7bc-0cde36dee44b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238028523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2238028523
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.603522981
Short name T17
Test name
Test status
Simulation time 6215191255 ps
CPU time 28.83 seconds
Started Apr 30 12:39:47 PM PDT 24
Finished Apr 30 12:40:16 PM PDT 24
Peak memory 219132 kb
Host smart-fd28dcd3-79a7-4951-b00f-5382d8c80d97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603522981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.603522981
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2083247860
Short name T29
Test name
Test status
Simulation time 4651448363 ps
CPU time 230.11 seconds
Started Apr 30 12:39:41 PM PDT 24
Finished Apr 30 12:43:32 PM PDT 24
Peak memory 238856 kb
Host smart-b6e56946-173d-4f7b-bd02-49e85adfb7a6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083247860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2083247860
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3882680815
Short name T63
Test name
Test status
Simulation time 23142985862 ps
CPU time 179.29 seconds
Started Apr 30 12:22:32 PM PDT 24
Finished Apr 30 12:25:32 PM PDT 24
Peak memory 213592 kb
Host smart-c659c566-c360-4fa1-9131-c1dfe1f1068e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882680815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3882680815
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2532283028
Short name T109
Test name
Test status
Simulation time 925827964 ps
CPU time 165.53 seconds
Started Apr 30 12:20:43 PM PDT 24
Finished Apr 30 12:23:29 PM PDT 24
Peak memory 213168 kb
Host smart-c3bfa5f2-772c-408e-9364-651d2c8105a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532283028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2532283028
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1241840000
Short name T8
Test name
Test status
Simulation time 345488486 ps
CPU time 8.37 seconds
Started Apr 30 12:40:43 PM PDT 24
Finished Apr 30 12:40:52 PM PDT 24
Peak memory 211828 kb
Host smart-e60b7cbf-e505-4356-99ea-1481158f3a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241840000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1241840000
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1672049320
Short name T9
Test name
Test status
Simulation time 11421016251 ps
CPU time 52.84 seconds
Started Apr 30 12:40:51 PM PDT 24
Finished Apr 30 12:41:45 PM PDT 24
Peak memory 215284 kb
Host smart-949c9eff-a0f8-49f2-9680-e3030acdbcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672049320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1672049320
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1368097557
Short name T300
Test name
Test status
Simulation time 346064067 ps
CPU time 19.65 seconds
Started Apr 30 12:39:54 PM PDT 24
Finished Apr 30 12:40:14 PM PDT 24
Peak memory 214912 kb
Host smart-6b4a200d-b2b6-4294-bf32-0b841cb246d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368097557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1368097557
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3276116082
Short name T24
Test name
Test status
Simulation time 27330597746 ps
CPU time 58.55 seconds
Started Apr 30 12:40:24 PM PDT 24
Finished Apr 30 12:41:23 PM PDT 24
Peak memory 215224 kb
Host smart-4fb09f9c-94d6-44c3-9cce-399e7be41ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276116082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3276116082
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.17918324
Short name T129
Test name
Test status
Simulation time 97590395149 ps
CPU time 791.61 seconds
Started Apr 30 12:40:11 PM PDT 24
Finished Apr 30 12:53:23 PM PDT 24
Peak memory 238076 kb
Host smart-8dfe7c22-f775-428c-906d-8760c0b14831
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17918324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_co
rrupt_sig_fatal_chk.17918324
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3546536285
Short name T69
Test name
Test status
Simulation time 167336932 ps
CPU time 8.23 seconds
Started Apr 30 12:17:10 PM PDT 24
Finished Apr 30 12:17:19 PM PDT 24
Peak memory 209928 kb
Host smart-dfc7fa3e-1487-446d-be2b-5d572416e50f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546536285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3546536285
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1316989037
Short name T110
Test name
Test status
Simulation time 6136907693 ps
CPU time 95.52 seconds
Started Apr 30 12:21:56 PM PDT 24
Finished Apr 30 12:23:32 PM PDT 24
Peak memory 211764 kb
Host smart-addfac63-97ce-4d3b-b0de-d7ea8e294627
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316989037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1316989037
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1277970339
Short name T106
Test name
Test status
Simulation time 9551653984 ps
CPU time 158.69 seconds
Started Apr 30 12:22:00 PM PDT 24
Finished Apr 30 12:24:40 PM PDT 24
Peak memory 213208 kb
Host smart-df1d7fa6-4ccd-48e2-a918-38c1194a6862
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277970339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1277970339
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.57082264
Short name T48
Test name
Test status
Simulation time 33495759583 ps
CPU time 980.39 seconds
Started Apr 30 12:40:19 PM PDT 24
Finished Apr 30 12:56:41 PM PDT 24
Peak memory 236172 kb
Host smart-c3c38687-ec18-46f3-9f88-4b0f417814fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57082264 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.57082264
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.4279669664
Short name T85
Test name
Test status
Simulation time 672835928 ps
CPU time 15.23 seconds
Started Apr 30 12:41:03 PM PDT 24
Finished Apr 30 12:41:19 PM PDT 24
Peak memory 211636 kb
Host smart-4fad48ab-07c3-4a04-ad2a-b610db95b826
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4279669664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.4279669664
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2981839917
Short name T15
Test name
Test status
Simulation time 80172321421 ps
CPU time 2956.72 seconds
Started Apr 30 12:40:51 PM PDT 24
Finished Apr 30 01:30:09 PM PDT 24
Peak memory 246796 kb
Host smart-5c73035b-007e-49f8-93e2-a98c0e496859
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981839917 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2981839917
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.749926347
Short name T374
Test name
Test status
Simulation time 2298653255 ps
CPU time 12.03 seconds
Started Apr 30 12:17:10 PM PDT 24
Finished Apr 30 12:17:23 PM PDT 24
Peak memory 217256 kb
Host smart-9e051968-3bef-441a-9544-863845907106
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749926347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.749926347
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1295525208
Short name T434
Test name
Test status
Simulation time 15766981936 ps
CPU time 35.5 seconds
Started Apr 30 12:17:07 PM PDT 24
Finished Apr 30 12:17:43 PM PDT 24
Peak memory 210456 kb
Host smart-a271de56-8c67-4212-84b6-fec8c8155fe4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295525208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1295525208
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2349116376
Short name T362
Test name
Test status
Simulation time 5015787254 ps
CPU time 22.58 seconds
Started Apr 30 12:17:16 PM PDT 24
Finished Apr 30 12:17:40 PM PDT 24
Peak memory 214068 kb
Host smart-bf5f4d3c-716f-47f2-96b3-7a7b16de9dbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349116376 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2349116376
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.356193033
Short name T417
Test name
Test status
Simulation time 169019350 ps
CPU time 8.15 seconds
Started Apr 30 12:16:58 PM PDT 24
Finished Apr 30 12:17:07 PM PDT 24
Peak memory 210248 kb
Host smart-2a692eeb-fbe7-436a-8717-0102f9050876
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356193033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.356193033
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.93527149
Short name T407
Test name
Test status
Simulation time 73728051077 ps
CPU time 30.9 seconds
Started Apr 30 12:17:10 PM PDT 24
Finished Apr 30 12:17:42 PM PDT 24
Peak memory 209496 kb
Host smart-181446b8-31ae-49a8-a7f6-bb72eb468602
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93527149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_
mem_partial_access.93527149
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.889262353
Short name T429
Test name
Test status
Simulation time 750726712 ps
CPU time 8.05 seconds
Started Apr 30 12:17:10 PM PDT 24
Finished Apr 30 12:17:19 PM PDT 24
Peak memory 208884 kb
Host smart-d10c842f-b25b-47e5-9d7a-6063319acab1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889262353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
889262353
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2909670157
Short name T70
Test name
Test status
Simulation time 10286491956 ps
CPU time 70.73 seconds
Started Apr 30 12:16:58 PM PDT 24
Finished Apr 30 12:18:09 PM PDT 24
Peak memory 212868 kb
Host smart-e7e04064-7e66-4a61-9d1a-5b2eff028fe6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909670157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2909670157
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.669103583
Short name T460
Test name
Test status
Simulation time 167468234 ps
CPU time 8.76 seconds
Started Apr 30 12:17:03 PM PDT 24
Finished Apr 30 12:17:12 PM PDT 24
Peak memory 210704 kb
Host smart-99ce50e4-3331-43a0-ae36-593508c1b3b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669103583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.669103583
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4280889394
Short name T450
Test name
Test status
Simulation time 8696018060 ps
CPU time 35.88 seconds
Started Apr 30 12:17:07 PM PDT 24
Finished Apr 30 12:17:44 PM PDT 24
Peak memory 217552 kb
Host smart-30b044b4-2681-4d3a-bd85-35ae4d45cba2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280889394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.4280889394
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.858427065
Short name T55
Test name
Test status
Simulation time 23590025768 ps
CPU time 165.17 seconds
Started Apr 30 12:17:03 PM PDT 24
Finished Apr 30 12:19:48 PM PDT 24
Peak memory 214148 kb
Host smart-98523977-87e5-4ce4-83a8-e1d9485472c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858427065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.858427065
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.994486418
Short name T64
Test name
Test status
Simulation time 775989524 ps
CPU time 12.94 seconds
Started Apr 30 12:17:18 PM PDT 24
Finished Apr 30 12:17:32 PM PDT 24
Peak memory 210636 kb
Host smart-e051aac5-fd24-4f5a-be00-ac0f5f9cf837
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994486418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.994486418
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.241191747
Short name T382
Test name
Test status
Simulation time 5386613508 ps
CPU time 24.05 seconds
Started Apr 30 12:20:05 PM PDT 24
Finished Apr 30 12:20:29 PM PDT 24
Peak memory 218744 kb
Host smart-8788e5d5-2a21-48ae-b90a-7eb1d8e4061c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241191747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.241191747
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.850222994
Short name T394
Test name
Test status
Simulation time 1175359068 ps
CPU time 18.94 seconds
Started Apr 30 12:17:17 PM PDT 24
Finished Apr 30 12:17:37 PM PDT 24
Peak memory 210752 kb
Host smart-59964028-dcfe-4ea7-a33b-71dd7416b8ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850222994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.850222994
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1977691943
Short name T385
Test name
Test status
Simulation time 3447443542 ps
CPU time 13.7 seconds
Started Apr 30 12:20:56 PM PDT 24
Finished Apr 30 12:21:10 PM PDT 24
Peak memory 211864 kb
Host smart-c009d64b-ecb2-4a10-8307-a8f41eb73740
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977691943 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1977691943
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3742694034
Short name T83
Test name
Test status
Simulation time 2055636564 ps
CPU time 20.17 seconds
Started Apr 30 12:18:19 PM PDT 24
Finished Apr 30 12:18:39 PM PDT 24
Peak memory 210632 kb
Host smart-9c34d2d0-ab53-4d6d-801f-b59a9ca30a54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742694034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3742694034
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3312965792
Short name T379
Test name
Test status
Simulation time 3022662527 ps
CPU time 27.18 seconds
Started Apr 30 12:17:13 PM PDT 24
Finished Apr 30 12:17:41 PM PDT 24
Peak memory 210240 kb
Host smart-1d0282ac-6320-40aa-abb0-e27e3f736a9e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312965792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3312965792
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2136014526
Short name T360
Test name
Test status
Simulation time 3660585489 ps
CPU time 30.39 seconds
Started Apr 30 12:17:13 PM PDT 24
Finished Apr 30 12:17:44 PM PDT 24
Peak memory 210436 kb
Host smart-a55e1637-9087-44b8-9cc0-9bea81c21f83
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136014526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2136014526
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1666926733
Short name T78
Test name
Test status
Simulation time 54673242493 ps
CPU time 121.6 seconds
Started Apr 30 12:17:16 PM PDT 24
Finished Apr 30 12:19:19 PM PDT 24
Peak memory 213420 kb
Host smart-bf3d5001-8425-4512-a4c0-45f5df4ae63c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666926733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1666926733
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1324942145
Short name T398
Test name
Test status
Simulation time 7000561911 ps
CPU time 31.75 seconds
Started Apr 30 12:22:02 PM PDT 24
Finished Apr 30 12:22:34 PM PDT 24
Peak memory 211636 kb
Host smart-042ad2a2-89c1-4e12-95fe-932e1f629132
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324942145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1324942145
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4095223344
Short name T369
Test name
Test status
Simulation time 1385457741 ps
CPU time 13.24 seconds
Started Apr 30 12:17:17 PM PDT 24
Finished Apr 30 12:17:31 PM PDT 24
Peak memory 215280 kb
Host smart-8babbbcd-f0d2-4b3a-8f89-aeedae734c58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095223344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.4095223344
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.175547675
Short name T415
Test name
Test status
Simulation time 4269094368 ps
CPU time 103.74 seconds
Started Apr 30 12:17:17 PM PDT 24
Finished Apr 30 12:19:01 PM PDT 24
Peak memory 212328 kb
Host smart-189a2deb-e27d-4b95-8d21-a88a4a4c0fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175547675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.175547675
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4129361485
Short name T364
Test name
Test status
Simulation time 7191866032 ps
CPU time 31.28 seconds
Started Apr 30 12:22:13 PM PDT 24
Finished Apr 30 12:22:46 PM PDT 24
Peak memory 217256 kb
Host smart-064069f1-8560-46cf-9a39-3272d372d4a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129361485 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.4129361485
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2743431305
Short name T387
Test name
Test status
Simulation time 167583965 ps
CPU time 7.96 seconds
Started Apr 30 12:22:15 PM PDT 24
Finished Apr 30 12:22:25 PM PDT 24
Peak memory 210308 kb
Host smart-4141770e-c2c6-4aba-b792-b858e05166ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743431305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2743431305
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1315147857
Short name T80
Test name
Test status
Simulation time 11990745475 ps
CPU time 74.24 seconds
Started Apr 30 12:23:04 PM PDT 24
Finished Apr 30 12:24:20 PM PDT 24
Peak memory 214436 kb
Host smart-6273072e-217b-4c1b-8d02-a2c638db193e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315147857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1315147857
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3286394576
Short name T102
Test name
Test status
Simulation time 345327446 ps
CPU time 8.05 seconds
Started Apr 30 12:20:43 PM PDT 24
Finished Apr 30 12:20:52 PM PDT 24
Peak memory 210332 kb
Host smart-1a74be4b-3f74-4205-96ee-40fe970fdcd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286394576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3286394576
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2637527698
Short name T456
Test name
Test status
Simulation time 688368302 ps
CPU time 10.68 seconds
Started Apr 30 12:22:14 PM PDT 24
Finished Apr 30 12:22:27 PM PDT 24
Peak memory 216524 kb
Host smart-3b6cb475-4dfd-4a8f-a710-df6ad44f2aba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637527698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2637527698
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.810466094
Short name T113
Test name
Test status
Simulation time 14614553318 ps
CPU time 96.73 seconds
Started Apr 30 12:22:14 PM PDT 24
Finished Apr 30 12:23:53 PM PDT 24
Peak memory 212852 kb
Host smart-a983b1fa-f0fd-4614-bac7-e36f3439e4e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810466094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.810466094
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3967319937
Short name T375
Test name
Test status
Simulation time 11403565341 ps
CPU time 25.23 seconds
Started Apr 30 12:21:54 PM PDT 24
Finished Apr 30 12:22:21 PM PDT 24
Peak memory 215632 kb
Host smart-f76c2ef6-724d-49cc-9bdb-318d40025091
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967319937 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3967319937
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1980620500
Short name T446
Test name
Test status
Simulation time 313353756 ps
CPU time 7.82 seconds
Started Apr 30 12:22:58 PM PDT 24
Finished Apr 30 12:23:07 PM PDT 24
Peak memory 210304 kb
Host smart-bc3bf811-4ca0-4577-99e6-b0249e7ecbd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980620500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1980620500
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3444195009
Short name T454
Test name
Test status
Simulation time 111769035265 ps
CPU time 205.4 seconds
Started Apr 30 12:17:25 PM PDT 24
Finished Apr 30 12:20:51 PM PDT 24
Peak memory 214712 kb
Host smart-31cfaef2-e116-4e46-a268-97edff2555b8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444195009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3444195009
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3717418098
Short name T425
Test name
Test status
Simulation time 3771814971 ps
CPU time 30.58 seconds
Started Apr 30 12:22:09 PM PDT 24
Finished Apr 30 12:22:41 PM PDT 24
Peak memory 211560 kb
Host smart-d6d2d5f3-d94b-4f37-bb10-adb09604fd4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717418098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3717418098
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.297958566
Short name T409
Test name
Test status
Simulation time 7504640814 ps
CPU time 35.05 seconds
Started Apr 30 12:19:54 PM PDT 24
Finished Apr 30 12:20:30 PM PDT 24
Peak memory 218240 kb
Host smart-3ced3d7b-06ea-4041-af24-299796f00f7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297958566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.297958566
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2260395493
Short name T114
Test name
Test status
Simulation time 8732317713 ps
CPU time 90.52 seconds
Started Apr 30 12:22:46 PM PDT 24
Finished Apr 30 12:24:18 PM PDT 24
Peak memory 213100 kb
Host smart-607b6c59-3965-4a67-a46d-884b55fd6ef4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260395493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2260395493
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3241682137
Short name T402
Test name
Test status
Simulation time 3566645060 ps
CPU time 27.82 seconds
Started Apr 30 12:23:41 PM PDT 24
Finished Apr 30 12:24:09 PM PDT 24
Peak memory 213108 kb
Host smart-e27950ed-321f-4406-81b6-5c4e86394a14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241682137 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3241682137
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3452095789
Short name T419
Test name
Test status
Simulation time 14779122328 ps
CPU time 28.32 seconds
Started Apr 30 12:22:45 PM PDT 24
Finished Apr 30 12:23:14 PM PDT 24
Peak memory 210748 kb
Host smart-24afd9b3-9fbd-4a40-99f7-477741c9b951
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452095789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3452095789
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2826942837
Short name T400
Test name
Test status
Simulation time 5678927736 ps
CPU time 61.22 seconds
Started Apr 30 12:23:00 PM PDT 24
Finished Apr 30 12:24:03 PM PDT 24
Peak memory 212904 kb
Host smart-0ea674f4-45ca-412f-ae8e-73d0e7ad965e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826942837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2826942837
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2315751596
Short name T418
Test name
Test status
Simulation time 2470447363 ps
CPU time 22.12 seconds
Started Apr 30 12:22:46 PM PDT 24
Finished Apr 30 12:23:10 PM PDT 24
Peak memory 211280 kb
Host smart-49327b4c-00b2-4d0d-8d94-617d0330df6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315751596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2315751596
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2358927763
Short name T422
Test name
Test status
Simulation time 2393007148 ps
CPU time 27.65 seconds
Started Apr 30 12:22:59 PM PDT 24
Finished Apr 30 12:23:28 PM PDT 24
Peak memory 216688 kb
Host smart-54e2e457-dfeb-426a-8647-98b2c31169f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358927763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2358927763
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.50381830
Short name T459
Test name
Test status
Simulation time 2250985310 ps
CPU time 91.48 seconds
Started Apr 30 12:21:14 PM PDT 24
Finished Apr 30 12:22:46 PM PDT 24
Peak memory 212564 kb
Host smart-2de98d61-43f4-4ab2-b17e-d71671f99d22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50381830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_int
g_err.50381830
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3022542824
Short name T370
Test name
Test status
Simulation time 184759021 ps
CPU time 9.84 seconds
Started Apr 30 12:23:55 PM PDT 24
Finished Apr 30 12:24:06 PM PDT 24
Peak memory 216456 kb
Host smart-e1e5d8cb-80d4-4f6c-9035-777e2c2ad761
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022542824 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3022542824
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3431816258
Short name T436
Test name
Test status
Simulation time 3105748569 ps
CPU time 25.59 seconds
Started Apr 30 12:23:02 PM PDT 24
Finished Apr 30 12:23:29 PM PDT 24
Peak memory 210988 kb
Host smart-f2bbc317-92ab-41af-ab16-b32b0e578253
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431816258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3431816258
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1523358585
Short name T81
Test name
Test status
Simulation time 58917406363 ps
CPU time 119.42 seconds
Started Apr 30 12:23:54 PM PDT 24
Finished Apr 30 12:25:54 PM PDT 24
Peak memory 213600 kb
Host smart-94625c56-0c16-4d8b-aab6-a50479f937ca
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523358585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1523358585
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2691832771
Short name T99
Test name
Test status
Simulation time 477758854 ps
CPU time 9.81 seconds
Started Apr 30 12:21:43 PM PDT 24
Finished Apr 30 12:21:53 PM PDT 24
Peak memory 210292 kb
Host smart-04ff3039-0379-4977-82e0-5ace7fc3dcb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691832771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2691832771
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3397565140
Short name T380
Test name
Test status
Simulation time 17083321202 ps
CPU time 36.64 seconds
Started Apr 30 12:18:23 PM PDT 24
Finished Apr 30 12:18:59 PM PDT 24
Peak memory 216064 kb
Host smart-6f61d409-c2a6-4eb3-be4c-8ee76ae5a7d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397565140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3397565140
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4269561717
Short name T372
Test name
Test status
Simulation time 1161486498 ps
CPU time 85.23 seconds
Started Apr 30 12:22:52 PM PDT 24
Finished Apr 30 12:24:18 PM PDT 24
Peak memory 212668 kb
Host smart-6d30126a-2022-47fd-8215-a127573de2e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269561717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.4269561717
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3804265678
Short name T384
Test name
Test status
Simulation time 183638851 ps
CPU time 8.91 seconds
Started Apr 30 12:20:31 PM PDT 24
Finished Apr 30 12:20:40 PM PDT 24
Peak memory 216096 kb
Host smart-d8872d3b-a542-476d-b6cd-4b3a7928e85d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804265678 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3804265678
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.14279021
Short name T376
Test name
Test status
Simulation time 507261331 ps
CPU time 11.13 seconds
Started Apr 30 12:22:58 PM PDT 24
Finished Apr 30 12:23:10 PM PDT 24
Peak memory 210340 kb
Host smart-a9b251e4-88f9-4e83-a14c-b8e8e5b5ddf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14279021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.14279021
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2100489671
Short name T57
Test name
Test status
Simulation time 28678271177 ps
CPU time 117.38 seconds
Started Apr 30 12:23:54 PM PDT 24
Finished Apr 30 12:25:52 PM PDT 24
Peak memory 212136 kb
Host smart-8eaab7ed-7110-4c88-80ff-62efe15cb49d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100489671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2100489671
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.783142458
Short name T435
Test name
Test status
Simulation time 1798107792 ps
CPU time 18.95 seconds
Started Apr 30 12:22:58 PM PDT 24
Finished Apr 30 12:23:18 PM PDT 24
Peak memory 211220 kb
Host smart-760972a2-eb81-4d9d-8987-a5d59c658ce0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783142458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.783142458
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2227337255
Short name T431
Test name
Test status
Simulation time 17760606803 ps
CPU time 28.36 seconds
Started Apr 30 12:21:42 PM PDT 24
Finished Apr 30 12:22:11 PM PDT 24
Peak memory 217996 kb
Host smart-4aabc145-44d7-46b3-98e7-d1446d5a1fb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227337255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2227337255
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3819276045
Short name T373
Test name
Test status
Simulation time 11311447870 ps
CPU time 24.71 seconds
Started Apr 30 12:21:11 PM PDT 24
Finished Apr 30 12:21:36 PM PDT 24
Peak memory 218848 kb
Host smart-9b53a08e-4af0-4de9-9ecf-b7d54710f4e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819276045 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3819276045
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2738647075
Short name T411
Test name
Test status
Simulation time 516566741 ps
CPU time 12.06 seconds
Started Apr 30 12:22:54 PM PDT 24
Finished Apr 30 12:23:06 PM PDT 24
Peak memory 210476 kb
Host smart-a86db404-a889-4fa1-8595-d5692292e26d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738647075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2738647075
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1920579920
Short name T386
Test name
Test status
Simulation time 9007022452 ps
CPU time 63.27 seconds
Started Apr 30 12:22:06 PM PDT 24
Finished Apr 30 12:23:11 PM PDT 24
Peak memory 211532 kb
Host smart-45905484-22b9-4ea4-8a2b-159fd79d027f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920579920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1920579920
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3576206600
Short name T452
Test name
Test status
Simulation time 424696161 ps
CPU time 8.5 seconds
Started Apr 30 12:23:07 PM PDT 24
Finished Apr 30 12:23:16 PM PDT 24
Peak memory 210420 kb
Host smart-f63a868d-9808-4719-b30a-6665a5193084
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576206600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3576206600
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4084549506
Short name T401
Test name
Test status
Simulation time 4013994126 ps
CPU time 35.61 seconds
Started Apr 30 12:22:07 PM PDT 24
Finished Apr 30 12:22:43 PM PDT 24
Peak memory 217464 kb
Host smart-00657f67-4ada-4d2e-99f2-48447cb1a29b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084549506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.4084549506
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1452116273
Short name T432
Test name
Test status
Simulation time 6916272606 ps
CPU time 96.56 seconds
Started Apr 30 12:23:03 PM PDT 24
Finished Apr 30 12:24:41 PM PDT 24
Peak memory 218676 kb
Host smart-9ccf4b1f-9b1e-4bd2-8d1b-47e82f71bce4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452116273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1452116273
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1337020167
Short name T408
Test name
Test status
Simulation time 1663489494 ps
CPU time 14 seconds
Started Apr 30 12:21:56 PM PDT 24
Finished Apr 30 12:22:11 PM PDT 24
Peak memory 214756 kb
Host smart-1a370906-1f77-4b97-b855-cfa317996b1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337020167 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1337020167
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3146333651
Short name T421
Test name
Test status
Simulation time 2231757991 ps
CPU time 15.45 seconds
Started Apr 30 12:19:25 PM PDT 24
Finished Apr 30 12:19:41 PM PDT 24
Peak memory 210536 kb
Host smart-78fff144-a196-4e05-8e6b-acdeb8f75a27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146333651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3146333651
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1596202632
Short name T426
Test name
Test status
Simulation time 4299479772 ps
CPU time 54.77 seconds
Started Apr 30 12:21:58 PM PDT 24
Finished Apr 30 12:22:53 PM PDT 24
Peak memory 213640 kb
Host smart-6e8ab9d4-a36e-4d1f-8aaa-d443303aa10f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596202632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1596202632
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2633236630
Short name T443
Test name
Test status
Simulation time 8844155022 ps
CPU time 25.57 seconds
Started Apr 30 12:22:16 PM PDT 24
Finished Apr 30 12:22:43 PM PDT 24
Peak memory 212080 kb
Host smart-e0e9f2bd-0081-4629-8ef7-c5c91504c176
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633236630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2633236630
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4089398690
Short name T412
Test name
Test status
Simulation time 4027833995 ps
CPU time 34.67 seconds
Started Apr 30 12:21:58 PM PDT 24
Finished Apr 30 12:22:33 PM PDT 24
Peak memory 216536 kb
Host smart-7789229c-571d-416f-ba9a-2b37ae697683
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089398690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.4089398690
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2787494947
Short name T108
Test name
Test status
Simulation time 1260939653 ps
CPU time 153.48 seconds
Started Apr 30 12:22:00 PM PDT 24
Finished Apr 30 12:24:34 PM PDT 24
Peak memory 213144 kb
Host smart-541a0b6c-fd8b-4620-8bec-e0fb2495bb08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787494947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2787494947
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3862786318
Short name T433
Test name
Test status
Simulation time 178408019 ps
CPU time 8.39 seconds
Started Apr 30 12:21:56 PM PDT 24
Finished Apr 30 12:22:05 PM PDT 24
Peak memory 214256 kb
Host smart-d32e057d-558e-49a0-9674-9c3bf0f9b92a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862786318 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3862786318
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2848248478
Short name T363
Test name
Test status
Simulation time 4508771220 ps
CPU time 31.4 seconds
Started Apr 30 12:23:39 PM PDT 24
Finished Apr 30 12:24:12 PM PDT 24
Peak memory 211100 kb
Host smart-92c7e915-9793-42a9-9204-0d9a75d48a15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848248478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2848248478
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2241448134
Short name T453
Test name
Test status
Simulation time 27384738963 ps
CPU time 109.7 seconds
Started Apr 30 12:23:05 PM PDT 24
Finished Apr 30 12:24:56 PM PDT 24
Peak memory 213500 kb
Host smart-3463db19-56f4-4221-81d5-7aacf8c038a9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241448134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2241448134
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1373358540
Short name T423
Test name
Test status
Simulation time 1415699202 ps
CPU time 16.98 seconds
Started Apr 30 12:22:44 PM PDT 24
Finished Apr 30 12:23:01 PM PDT 24
Peak memory 211164 kb
Host smart-963f0216-c27d-46b6-8c43-acae6badc7e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373358540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1373358540
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.707339491
Short name T445
Test name
Test status
Simulation time 22357722460 ps
CPU time 26.35 seconds
Started Apr 30 12:23:52 PM PDT 24
Finished Apr 30 12:24:19 PM PDT 24
Peak memory 218020 kb
Host smart-382340d3-ae95-48e9-837e-371771065ebb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707339491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.707339491
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2668852219
Short name T366
Test name
Test status
Simulation time 21470899313 ps
CPU time 20.24 seconds
Started Apr 30 12:24:13 PM PDT 24
Finished Apr 30 12:24:34 PM PDT 24
Peak memory 217812 kb
Host smart-ce685f7a-34fd-4ffb-aad4-62c89598fc1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668852219 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2668852219
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1091845166
Short name T82
Test name
Test status
Simulation time 11449025872 ps
CPU time 24.64 seconds
Started Apr 30 12:23:34 PM PDT 24
Finished Apr 30 12:24:00 PM PDT 24
Peak memory 211564 kb
Host smart-01fca17f-c65a-4aeb-bd57-a8282b62e258
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091845166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1091845166
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3050311280
Short name T71
Test name
Test status
Simulation time 1077787543 ps
CPU time 57.26 seconds
Started Apr 30 12:23:18 PM PDT 24
Finished Apr 30 12:24:16 PM PDT 24
Peak memory 213944 kb
Host smart-3dbf5b48-e6d1-45bc-8695-79a11af37b6b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050311280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3050311280
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2254590433
Short name T437
Test name
Test status
Simulation time 32217047538 ps
CPU time 35.91 seconds
Started Apr 30 12:23:54 PM PDT 24
Finished Apr 30 12:24:31 PM PDT 24
Peak memory 211980 kb
Host smart-dae46a25-2bae-4fdb-99cb-52537b404926
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254590433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2254590433
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.622777661
Short name T359
Test name
Test status
Simulation time 3676960645 ps
CPU time 32.35 seconds
Started Apr 30 12:23:42 PM PDT 24
Finished Apr 30 12:24:15 PM PDT 24
Peak memory 216084 kb
Host smart-61eb53d1-1c51-4b03-a035-f237b388c0b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622777661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.622777661
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.666525990
Short name T427
Test name
Test status
Simulation time 233491986 ps
CPU time 79.04 seconds
Started Apr 30 12:24:30 PM PDT 24
Finished Apr 30 12:25:50 PM PDT 24
Peak memory 211872 kb
Host smart-14138282-96b9-4b01-8110-c3dc8abb80c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666525990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.666525990
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2568041509
Short name T367
Test name
Test status
Simulation time 186934406 ps
CPU time 8.75 seconds
Started Apr 30 12:23:41 PM PDT 24
Finished Apr 30 12:23:50 PM PDT 24
Peak memory 215044 kb
Host smart-114fc43c-9971-4c06-b63b-c395793aa0e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568041509 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2568041509
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2865496109
Short name T97
Test name
Test status
Simulation time 4339239792 ps
CPU time 30.77 seconds
Started Apr 30 12:23:40 PM PDT 24
Finished Apr 30 12:24:11 PM PDT 24
Peak memory 211476 kb
Host smart-f66d9bb6-d075-4564-b557-59f1bb8f6d7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865496109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2865496109
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.638451926
Short name T59
Test name
Test status
Simulation time 707719621 ps
CPU time 37.37 seconds
Started Apr 30 12:23:39 PM PDT 24
Finished Apr 30 12:24:17 PM PDT 24
Peak memory 213440 kb
Host smart-125f258b-0d4d-4bff-90af-7c08349b5140
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638451926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.638451926
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1967021440
Short name T98
Test name
Test status
Simulation time 7041920618 ps
CPU time 31.09 seconds
Started Apr 30 12:23:25 PM PDT 24
Finished Apr 30 12:23:57 PM PDT 24
Peak memory 212168 kb
Host smart-230b8a5b-b9c7-41ed-97b6-53f794fd0850
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967021440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1967021440
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2923839721
Short name T461
Test name
Test status
Simulation time 3256895699 ps
CPU time 29.96 seconds
Started Apr 30 12:23:48 PM PDT 24
Finished Apr 30 12:24:19 PM PDT 24
Peak memory 217372 kb
Host smart-caeaa03f-831f-4518-8555-d0666dec52ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923839721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2923839721
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3372569465
Short name T399
Test name
Test status
Simulation time 6653539769 ps
CPU time 31.55 seconds
Started Apr 30 12:18:20 PM PDT 24
Finished Apr 30 12:18:52 PM PDT 24
Peak memory 210744 kb
Host smart-6df06726-44f4-4f0a-8096-c475ce1af5ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372569465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3372569465
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.715393097
Short name T424
Test name
Test status
Simulation time 3553467432 ps
CPU time 28.03 seconds
Started Apr 30 12:18:18 PM PDT 24
Finished Apr 30 12:18:47 PM PDT 24
Peak memory 209536 kb
Host smart-5dd40733-48c7-4dc4-a362-af34d6bd90c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715393097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.715393097
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3143929198
Short name T67
Test name
Test status
Simulation time 13647633133 ps
CPU time 30.86 seconds
Started Apr 30 12:18:49 PM PDT 24
Finished Apr 30 12:19:20 PM PDT 24
Peak memory 211636 kb
Host smart-0a653c9c-251b-42f1-978e-538f8343ab3b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143929198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3143929198
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4155663500
Short name T361
Test name
Test status
Simulation time 36674350797 ps
CPU time 23.91 seconds
Started Apr 30 12:23:07 PM PDT 24
Finished Apr 30 12:23:32 PM PDT 24
Peak memory 215980 kb
Host smart-7c50bd79-2113-4824-ac7e-0143efa9d038
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155663500 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4155663500
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.920266311
Short name T95
Test name
Test status
Simulation time 3515890803 ps
CPU time 27.76 seconds
Started Apr 30 12:18:18 PM PDT 24
Finished Apr 30 12:18:47 PM PDT 24
Peak memory 210412 kb
Host smart-934ec496-a6de-43e1-b35f-cf60d02a27dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920266311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.920266311
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1637778286
Short name T406
Test name
Test status
Simulation time 8036793700 ps
CPU time 29.41 seconds
Started Apr 30 12:22:55 PM PDT 24
Finished Apr 30 12:23:25 PM PDT 24
Peak memory 210384 kb
Host smart-44d69bb4-2b36-483f-8b17-65221bc6370e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637778286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1637778286
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2568123871
Short name T368
Test name
Test status
Simulation time 5688408879 ps
CPU time 24.6 seconds
Started Apr 30 12:17:54 PM PDT 24
Finished Apr 30 12:18:19 PM PDT 24
Peak memory 210464 kb
Host smart-284b4a7c-e03a-4ac4-a909-c77affe27620
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568123871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2568123871
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3209672158
Short name T101
Test name
Test status
Simulation time 18895767916 ps
CPU time 34.12 seconds
Started Apr 30 12:19:08 PM PDT 24
Finished Apr 30 12:19:42 PM PDT 24
Peak memory 212376 kb
Host smart-c43da655-edd7-4ded-b1cc-3d52df078ffa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209672158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3209672158
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2439972042
Short name T395
Test name
Test status
Simulation time 3289608479 ps
CPU time 31.35 seconds
Started Apr 30 12:18:41 PM PDT 24
Finished Apr 30 12:19:12 PM PDT 24
Peak memory 217824 kb
Host smart-addbe3e3-f4e4-4792-aaa5-7ca283a20cf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439972042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2439972042
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1539367673
Short name T56
Test name
Test status
Simulation time 698848371 ps
CPU time 152.94 seconds
Started Apr 30 12:17:18 PM PDT 24
Finished Apr 30 12:19:52 PM PDT 24
Peak memory 213168 kb
Host smart-1efc2c3a-e685-4e8a-841f-d7c163c322f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539367673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1539367673
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1460165320
Short name T390
Test name
Test status
Simulation time 1496965764 ps
CPU time 8.04 seconds
Started Apr 30 12:23:04 PM PDT 24
Finished Apr 30 12:23:13 PM PDT 24
Peak memory 210264 kb
Host smart-df9d8b72-f5a5-49d9-85a0-01ada82c5b41
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460165320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1460165320
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.327942502
Short name T462
Test name
Test status
Simulation time 4800839351 ps
CPU time 22.46 seconds
Started Apr 30 12:19:36 PM PDT 24
Finished Apr 30 12:19:59 PM PDT 24
Peak memory 210776 kb
Host smart-5e150f20-340c-46d2-babb-197d17147696
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327942502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.327942502
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.569215324
Short name T58
Test name
Test status
Simulation time 38309565176 ps
CPU time 26.61 seconds
Started Apr 30 12:18:17 PM PDT 24
Finished Apr 30 12:18:44 PM PDT 24
Peak memory 211576 kb
Host smart-89f831c4-26d4-4a90-858c-1ad7d593ed44
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569215324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.569215324
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4046991937
Short name T405
Test name
Test status
Simulation time 20668912613 ps
CPU time 27.93 seconds
Started Apr 30 12:23:04 PM PDT 24
Finished Apr 30 12:23:33 PM PDT 24
Peak memory 216764 kb
Host smart-72e22c76-c5f3-4cad-ac1f-e37ee21ebedb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046991937 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.4046991937
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2457943218
Short name T414
Test name
Test status
Simulation time 7054122163 ps
CPU time 30.67 seconds
Started Apr 30 12:19:26 PM PDT 24
Finished Apr 30 12:19:57 PM PDT 24
Peak memory 210984 kb
Host smart-3642421f-1d21-4048-a25d-acf4ea652324
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457943218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2457943218
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1142542543
Short name T458
Test name
Test status
Simulation time 23187873746 ps
CPU time 17.36 seconds
Started Apr 30 12:19:15 PM PDT 24
Finished Apr 30 12:19:33 PM PDT 24
Peak memory 210480 kb
Host smart-d57df218-95f2-4a33-bff3-88ab6733e284
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142542543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1142542543
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1978338147
Short name T378
Test name
Test status
Simulation time 902545378 ps
CPU time 13.51 seconds
Started Apr 30 12:22:02 PM PDT 24
Finished Apr 30 12:22:16 PM PDT 24
Peak memory 209508 kb
Host smart-d4cf6b84-3c05-4498-ac64-30eb52026532
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978338147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1978338147
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3855041472
Short name T84
Test name
Test status
Simulation time 26588276495 ps
CPU time 56.75 seconds
Started Apr 30 12:18:48 PM PDT 24
Finished Apr 30 12:19:46 PM PDT 24
Peak memory 213680 kb
Host smart-dda97627-c083-4e38-906a-0b4125dd6eac
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855041472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3855041472
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.326723909
Short name T416
Test name
Test status
Simulation time 23967277565 ps
CPU time 29.4 seconds
Started Apr 30 12:22:11 PM PDT 24
Finished Apr 30 12:22:42 PM PDT 24
Peak memory 210424 kb
Host smart-c12f1211-deef-498b-a85c-72d09d489271
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326723909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.326723909
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.556297087
Short name T439
Test name
Test status
Simulation time 17476621566 ps
CPU time 38.38 seconds
Started Apr 30 12:17:18 PM PDT 24
Finished Apr 30 12:17:57 PM PDT 24
Peak memory 217008 kb
Host smart-119ac2c8-6f59-4447-b23f-42b50675b83f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556297087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.556297087
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.767993737
Short name T420
Test name
Test status
Simulation time 366467079 ps
CPU time 155.16 seconds
Started Apr 30 12:17:17 PM PDT 24
Finished Apr 30 12:19:53 PM PDT 24
Peak memory 212736 kb
Host smart-606bea6f-bf89-4139-a4a6-bd506ee95f56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767993737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.767993737
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2591359006
Short name T377
Test name
Test status
Simulation time 4105217660 ps
CPU time 28.79 seconds
Started Apr 30 12:18:50 PM PDT 24
Finished Apr 30 12:19:19 PM PDT 24
Peak memory 210656 kb
Host smart-0eab1cf2-2568-44fb-9513-923429e9e760
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591359006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2591359006
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3662633239
Short name T388
Test name
Test status
Simulation time 24010417674 ps
CPU time 29.01 seconds
Started Apr 30 12:20:34 PM PDT 24
Finished Apr 30 12:21:04 PM PDT 24
Peak memory 211024 kb
Host smart-d03eb2e7-ec90-461b-830d-6957707f6900
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662633239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3662633239
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.411992466
Short name T77
Test name
Test status
Simulation time 3720431090 ps
CPU time 35.56 seconds
Started Apr 30 12:18:47 PM PDT 24
Finished Apr 30 12:19:23 PM PDT 24
Peak memory 210904 kb
Host smart-31dc259e-3b92-4bc9-9167-27665e0caca4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411992466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.411992466
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3367053925
Short name T441
Test name
Test status
Simulation time 3812933612 ps
CPU time 11.49 seconds
Started Apr 30 12:17:36 PM PDT 24
Finished Apr 30 12:17:48 PM PDT 24
Peak memory 216228 kb
Host smart-35b47e35-137d-4e26-b7fb-b85d106a559e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367053925 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3367053925
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.453752066
Short name T413
Test name
Test status
Simulation time 660160994 ps
CPU time 7.9 seconds
Started Apr 30 12:21:58 PM PDT 24
Finished Apr 30 12:22:07 PM PDT 24
Peak memory 210192 kb
Host smart-562e5f90-f0b7-4123-9439-5ba86ef2de25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453752066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.453752066
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.320091275
Short name T392
Test name
Test status
Simulation time 16542324322 ps
CPU time 18.18 seconds
Started Apr 30 12:22:19 PM PDT 24
Finished Apr 30 12:22:38 PM PDT 24
Peak memory 210368 kb
Host smart-7353d4cd-96ac-4865-a70d-b2ad4264dc79
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320091275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.320091275
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.328371418
Short name T365
Test name
Test status
Simulation time 942364823 ps
CPU time 14.55 seconds
Started Apr 30 12:19:40 PM PDT 24
Finished Apr 30 12:19:55 PM PDT 24
Peak memory 210384 kb
Host smart-56db3c01-608c-4e2d-99cd-9bbfc2944777
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328371418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
328371418
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.200737329
Short name T393
Test name
Test status
Simulation time 67658083557 ps
CPU time 104.51 seconds
Started Apr 30 12:22:13 PM PDT 24
Finished Apr 30 12:23:59 PM PDT 24
Peak memory 213404 kb
Host smart-91841092-c57b-43bf-b83c-0f984f023e12
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200737329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.200737329
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.508413545
Short name T100
Test name
Test status
Simulation time 1334368040 ps
CPU time 19.84 seconds
Started Apr 30 12:21:57 PM PDT 24
Finished Apr 30 12:22:18 PM PDT 24
Peak memory 210464 kb
Host smart-302d5138-1f84-470a-8eec-21b9718fb7e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508413545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.508413545
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3416221659
Short name T371
Test name
Test status
Simulation time 514829564 ps
CPU time 15.46 seconds
Started Apr 30 12:22:14 PM PDT 24
Finished Apr 30 12:22:31 PM PDT 24
Peak memory 216548 kb
Host smart-17e9ed94-d035-49c4-989d-221278b3cb24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416221659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3416221659
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1128952375
Short name T111
Test name
Test status
Simulation time 286823900 ps
CPU time 83.19 seconds
Started Apr 30 12:20:42 PM PDT 24
Finished Apr 30 12:22:06 PM PDT 24
Peak memory 212508 kb
Host smart-4cb6b08a-f101-42d7-b718-ec50b70a2bad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128952375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1128952375
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1572202489
Short name T396
Test name
Test status
Simulation time 6222502310 ps
CPU time 24.88 seconds
Started Apr 30 12:22:14 PM PDT 24
Finished Apr 30 12:22:41 PM PDT 24
Peak memory 214676 kb
Host smart-cd51a147-ef91-4490-9cc9-5d267232570e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572202489 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1572202489
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.430047155
Short name T66
Test name
Test status
Simulation time 3117859355 ps
CPU time 26.45 seconds
Started Apr 30 12:22:14 PM PDT 24
Finished Apr 30 12:22:42 PM PDT 24
Peak memory 210280 kb
Host smart-aeaf2c3e-f3c2-4baa-829b-ba9266760ed6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430047155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.430047155
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2388295929
Short name T79
Test name
Test status
Simulation time 49214875553 ps
CPU time 193.42 seconds
Started Apr 30 12:18:40 PM PDT 24
Finished Apr 30 12:21:54 PM PDT 24
Peak memory 214672 kb
Host smart-ddaf4953-f70c-4de4-b1d1-ff38ac53965f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388295929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2388295929
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4102132739
Short name T442
Test name
Test status
Simulation time 2169432445 ps
CPU time 25.33 seconds
Started Apr 30 12:22:14 PM PDT 24
Finished Apr 30 12:22:41 PM PDT 24
Peak memory 210496 kb
Host smart-4d1e36bf-ae43-44fa-babf-c4e1273121a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102132739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.4102132739
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2631940005
Short name T381
Test name
Test status
Simulation time 3771540805 ps
CPU time 19.6 seconds
Started Apr 30 12:22:16 PM PDT 24
Finished Apr 30 12:22:37 PM PDT 24
Peak memory 217376 kb
Host smart-9c3b4da4-3854-443b-843b-d15a57a944bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631940005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2631940005
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2946962334
Short name T389
Test name
Test status
Simulation time 13393358924 ps
CPU time 12.98 seconds
Started Apr 30 12:22:06 PM PDT 24
Finished Apr 30 12:22:21 PM PDT 24
Peak memory 217680 kb
Host smart-a8805f24-9e91-4023-90d8-7a1bfa734002
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946962334 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2946962334
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.507651659
Short name T438
Test name
Test status
Simulation time 3678179592 ps
CPU time 21.89 seconds
Started Apr 30 12:22:07 PM PDT 24
Finished Apr 30 12:22:30 PM PDT 24
Peak memory 210100 kb
Host smart-2bebc3b1-dca5-404c-94d5-478a13dc5951
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507651659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.507651659
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.257986344
Short name T68
Test name
Test status
Simulation time 47138774141 ps
CPU time 192.59 seconds
Started Apr 30 12:22:58 PM PDT 24
Finished Apr 30 12:26:12 PM PDT 24
Peak memory 214580 kb
Host smart-2666020c-5e59-4a61-830c-ffdebc110645
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257986344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.257986344
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4110884706
Short name T96
Test name
Test status
Simulation time 1965642705 ps
CPU time 11.4 seconds
Started Apr 30 12:22:07 PM PDT 24
Finished Apr 30 12:22:19 PM PDT 24
Peak memory 210076 kb
Host smart-94ff5179-3bd7-4a6c-9682-5dd90adc7376
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110884706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.4110884706
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3685743403
Short name T430
Test name
Test status
Simulation time 6868211546 ps
CPU time 22.05 seconds
Started Apr 30 12:22:59 PM PDT 24
Finished Apr 30 12:23:23 PM PDT 24
Peak memory 218780 kb
Host smart-02cbe0dd-6f0c-40ff-9bc2-228d8a5c963d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685743403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3685743403
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3088556552
Short name T112
Test name
Test status
Simulation time 4875448493 ps
CPU time 161.28 seconds
Started Apr 30 12:22:59 PM PDT 24
Finished Apr 30 12:25:42 PM PDT 24
Peak memory 218680 kb
Host smart-60d78c2e-748e-44b8-bc80-1a26538deb76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088556552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3088556552
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2950951324
Short name T447
Test name
Test status
Simulation time 678104240 ps
CPU time 8.43 seconds
Started Apr 30 12:21:54 PM PDT 24
Finished Apr 30 12:22:03 PM PDT 24
Peak memory 212304 kb
Host smart-6c3d69b4-f428-4cbb-b121-2f932cd307fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950951324 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2950951324
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2250126553
Short name T449
Test name
Test status
Simulation time 174351089 ps
CPU time 8.56 seconds
Started Apr 30 12:20:17 PM PDT 24
Finished Apr 30 12:20:26 PM PDT 24
Peak memory 210376 kb
Host smart-44b031d9-122f-4320-8ae3-6e35056c7811
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250126553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2250126553
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.428957014
Short name T404
Test name
Test status
Simulation time 103392429441 ps
CPU time 120.43 seconds
Started Apr 30 12:20:07 PM PDT 24
Finished Apr 30 12:22:07 PM PDT 24
Peak memory 214636 kb
Host smart-64f35c28-bcde-4e76-be0a-f511451c5a4b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428957014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.428957014
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.166623197
Short name T65
Test name
Test status
Simulation time 689248063 ps
CPU time 11.51 seconds
Started Apr 30 12:21:58 PM PDT 24
Finished Apr 30 12:22:10 PM PDT 24
Peak memory 211368 kb
Host smart-43f26925-89b7-4706-94b7-7f042d192e3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166623197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.166623197
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2640093912
Short name T383
Test name
Test status
Simulation time 7042968308 ps
CPU time 31.12 seconds
Started Apr 30 12:23:01 PM PDT 24
Finished Apr 30 12:23:34 PM PDT 24
Peak memory 216700 kb
Host smart-1cf25f9e-988d-42b0-b82e-e66e25937d5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640093912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2640093912
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1363125159
Short name T451
Test name
Test status
Simulation time 23678827541 ps
CPU time 99.23 seconds
Started Apr 30 12:19:56 PM PDT 24
Finished Apr 30 12:21:36 PM PDT 24
Peak memory 218772 kb
Host smart-510600ca-e95f-4882-8a31-bed2829c14b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363125159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1363125159
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.315858129
Short name T457
Test name
Test status
Simulation time 352403030 ps
CPU time 8.96 seconds
Started Apr 30 12:24:04 PM PDT 24
Finished Apr 30 12:24:14 PM PDT 24
Peak memory 216296 kb
Host smart-f0936aa6-ad72-4238-9e00-dc753ae7b759
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315858129 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.315858129
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3017814134
Short name T410
Test name
Test status
Simulation time 8184827796 ps
CPU time 31.23 seconds
Started Apr 30 12:21:58 PM PDT 24
Finished Apr 30 12:22:30 PM PDT 24
Peak memory 211248 kb
Host smart-88aa75c0-629d-41fb-a088-a116388ca51d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017814134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3017814134
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2459414297
Short name T391
Test name
Test status
Simulation time 3538228402 ps
CPU time 56.92 seconds
Started Apr 30 12:21:56 PM PDT 24
Finished Apr 30 12:22:54 PM PDT 24
Peak memory 212692 kb
Host smart-d1550bf4-0e4d-4039-94ed-72ffb65d5857
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459414297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2459414297
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1711972582
Short name T440
Test name
Test status
Simulation time 174308387 ps
CPU time 8.24 seconds
Started Apr 30 12:22:27 PM PDT 24
Finished Apr 30 12:22:36 PM PDT 24
Peak memory 210484 kb
Host smart-a1a5710f-a8a5-49f1-a81b-f1eed57db6d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711972582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1711972582
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.922013609
Short name T444
Test name
Test status
Simulation time 171074284 ps
CPU time 12.59 seconds
Started Apr 30 12:18:28 PM PDT 24
Finished Apr 30 12:18:41 PM PDT 24
Peak memory 216232 kb
Host smart-1040b7d7-01e5-4c14-8e62-19d4497443d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922013609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.922013609
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3973315473
Short name T54
Test name
Test status
Simulation time 66805963602 ps
CPU time 101.79 seconds
Started Apr 30 12:22:04 PM PDT 24
Finished Apr 30 12:23:47 PM PDT 24
Peak memory 213072 kb
Host smart-277d7c5c-a982-4673-bb12-e81497a79136
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973315473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3973315473
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1402631552
Short name T397
Test name
Test status
Simulation time 13074544285 ps
CPU time 26.6 seconds
Started Apr 30 12:23:03 PM PDT 24
Finished Apr 30 12:23:31 PM PDT 24
Peak memory 215272 kb
Host smart-6b078b67-3a17-4a6b-8a78-48569922924a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402631552 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1402631552
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4008478708
Short name T455
Test name
Test status
Simulation time 2373557734 ps
CPU time 23.43 seconds
Started Apr 30 12:20:07 PM PDT 24
Finished Apr 30 12:20:31 PM PDT 24
Peak memory 211124 kb
Host smart-8d5e5e63-123c-44b4-a7c1-8121044b43cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008478708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.4008478708
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.203270674
Short name T428
Test name
Test status
Simulation time 11286558747 ps
CPU time 97.36 seconds
Started Apr 30 12:22:47 PM PDT 24
Finished Apr 30 12:24:26 PM PDT 24
Peak memory 213572 kb
Host smart-6321e4e3-bb49-48ea-bc9e-230d824f4583
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203270674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.203270674
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2471378736
Short name T403
Test name
Test status
Simulation time 35837313315 ps
CPU time 31.28 seconds
Started Apr 30 12:22:51 PM PDT 24
Finished Apr 30 12:23:23 PM PDT 24
Peak memory 211572 kb
Host smart-1ac5f34b-f3c5-4c53-b813-e53fb558dc40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471378736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2471378736
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.384525700
Short name T448
Test name
Test status
Simulation time 34103384598 ps
CPU time 23.51 seconds
Started Apr 30 12:22:51 PM PDT 24
Finished Apr 30 12:23:16 PM PDT 24
Peak memory 218780 kb
Host smart-899b9582-0c5a-408b-bcfd-c8e641baa931
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384525700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.384525700
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1643972544
Short name T107
Test name
Test status
Simulation time 4359448778 ps
CPU time 171.18 seconds
Started Apr 30 12:23:47 PM PDT 24
Finished Apr 30 12:26:40 PM PDT 24
Peak memory 211916 kb
Host smart-1dc98fee-ee5b-4a5b-9a37-53537bdde35f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643972544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1643972544
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2068762499
Short name T60
Test name
Test status
Simulation time 171157721 ps
CPU time 8.26 seconds
Started Apr 30 12:39:38 PM PDT 24
Finished Apr 30 12:39:48 PM PDT 24
Peak memory 211612 kb
Host smart-5baba7a9-88b1-4bb4-9c2c-791dbad08c63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068762499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2068762499
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3069483916
Short name T301
Test name
Test status
Simulation time 64881380627 ps
CPU time 607.5 seconds
Started Apr 30 12:39:38 PM PDT 24
Finished Apr 30 12:49:48 PM PDT 24
Peak memory 236968 kb
Host smart-5e85b794-d293-47d1-b52f-cad305f3df4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069483916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3069483916
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4185836686
Short name T182
Test name
Test status
Simulation time 48970096218 ps
CPU time 51.91 seconds
Started Apr 30 12:39:38 PM PDT 24
Finished Apr 30 12:40:31 PM PDT 24
Peak memory 213852 kb
Host smart-a571534b-be0a-4f4b-9ba7-496a1d061b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185836686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.4185836686
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.265972540
Short name T290
Test name
Test status
Simulation time 2903437695 ps
CPU time 14.32 seconds
Started Apr 30 12:39:38 PM PDT 24
Finished Apr 30 12:39:54 PM PDT 24
Peak memory 212800 kb
Host smart-e998b877-3bf9-4c07-9139-140711999832
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=265972540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.265972540
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.407937152
Short name T199
Test name
Test status
Simulation time 18426436056 ps
CPU time 37.34 seconds
Started Apr 30 12:39:36 PM PDT 24
Finished Apr 30 12:40:14 PM PDT 24
Peak memory 218772 kb
Host smart-4fe31c2b-d317-430a-97df-f7e8908d599c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407937152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.407937152
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2615396809
Short name T146
Test name
Test status
Simulation time 5336765281 ps
CPU time 65.56 seconds
Started Apr 30 12:39:39 PM PDT 24
Finished Apr 30 12:40:46 PM PDT 24
Peak memory 218888 kb
Host smart-cfdfe737-919c-4ec4-aadd-8b93581a7dcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615396809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2615396809
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2210690872
Short name T357
Test name
Test status
Simulation time 2844071958 ps
CPU time 24.07 seconds
Started Apr 30 12:39:37 PM PDT 24
Finished Apr 30 12:40:02 PM PDT 24
Peak memory 211584 kb
Host smart-ea5e4dcd-4a38-453d-8e6a-3157d6592cf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210690872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2210690872
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2674318608
Short name T184
Test name
Test status
Simulation time 2955619009 ps
CPU time 186.92 seconds
Started Apr 30 12:39:41 PM PDT 24
Finished Apr 30 12:42:48 PM PDT 24
Peak memory 219796 kb
Host smart-ff8927cd-f879-4af5-aa1b-de00317b8979
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674318608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2674318608
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2786312927
Short name T328
Test name
Test status
Simulation time 21954802064 ps
CPU time 50.15 seconds
Started Apr 30 12:40:41 PM PDT 24
Finished Apr 30 12:41:33 PM PDT 24
Peak memory 214396 kb
Host smart-ea5fffa0-b444-4a85-a66e-8f7fe88fb4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786312927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2786312927
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3317815299
Short name T142
Test name
Test status
Simulation time 2488417641 ps
CPU time 18.26 seconds
Started Apr 30 12:39:38 PM PDT 24
Finished Apr 30 12:39:58 PM PDT 24
Peak memory 212400 kb
Host smart-db7b15e2-f13e-413e-9c61-17f11bc0fcc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3317815299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3317815299
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3412857454
Short name T34
Test name
Test status
Simulation time 339340793 ps
CPU time 226.19 seconds
Started Apr 30 12:39:38 PM PDT 24
Finished Apr 30 12:43:26 PM PDT 24
Peak memory 238504 kb
Host smart-294ee3f2-9752-4e0d-bd34-b4a2fd207f4a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412857454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3412857454
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4196066075
Short name T144
Test name
Test status
Simulation time 1568472278 ps
CPU time 19.39 seconds
Started Apr 30 12:39:38 PM PDT 24
Finished Apr 30 12:39:59 PM PDT 24
Peak memory 217748 kb
Host smart-997b5120-8d13-4c96-91e3-2b3482f78dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196066075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4196066075
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2670425709
Short name T282
Test name
Test status
Simulation time 7019415720 ps
CPU time 71.31 seconds
Started Apr 30 12:39:38 PM PDT 24
Finished Apr 30 12:40:51 PM PDT 24
Peak memory 219336 kb
Host smart-7ff5ff53-6014-423d-99d8-dfa4edb33f13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670425709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2670425709
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1982268151
Short name T326
Test name
Test status
Simulation time 10747150721 ps
CPU time 19.88 seconds
Started Apr 30 12:39:55 PM PDT 24
Finished Apr 30 12:40:16 PM PDT 24
Peak memory 211576 kb
Host smart-f0ea8211-0857-4f3c-a34a-bcffbe8277e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982268151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1982268151
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4214862981
Short name T211
Test name
Test status
Simulation time 3461328379 ps
CPU time 251.35 seconds
Started Apr 30 12:39:55 PM PDT 24
Finished Apr 30 12:44:06 PM PDT 24
Peak memory 229964 kb
Host smart-01e64294-b740-4600-93e7-c564f1c9cde0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214862981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4214862981
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3052325682
Short name T337
Test name
Test status
Simulation time 339256715 ps
CPU time 18.85 seconds
Started Apr 30 12:39:56 PM PDT 24
Finished Apr 30 12:40:15 PM PDT 24
Peak memory 215076 kb
Host smart-0c0eed60-8cd1-4cbc-9c97-b35472788009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052325682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3052325682
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.339950142
Short name T194
Test name
Test status
Simulation time 183945590 ps
CPU time 9.99 seconds
Started Apr 30 12:41:09 PM PDT 24
Finished Apr 30 12:41:19 PM PDT 24
Peak memory 212088 kb
Host smart-a5864a02-17cf-481a-a72d-323754de6ca6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=339950142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.339950142
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.4002531126
Short name T289
Test name
Test status
Simulation time 35981161842 ps
CPU time 63.42 seconds
Started Apr 30 12:39:52 PM PDT 24
Finished Apr 30 12:40:56 PM PDT 24
Peak memory 217044 kb
Host smart-27c8371d-caee-404c-a71e-986157d3e5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002531126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.4002531126
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3670464104
Short name T236
Test name
Test status
Simulation time 10394478957 ps
CPU time 27.21 seconds
Started Apr 30 12:39:54 PM PDT 24
Finished Apr 30 12:40:22 PM PDT 24
Peak memory 214080 kb
Host smart-96148b06-e6b1-44c5-bc57-d64ea1084d59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670464104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3670464104
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2064302211
Short name T33
Test name
Test status
Simulation time 3082889313 ps
CPU time 25.9 seconds
Started Apr 30 12:39:53 PM PDT 24
Finished Apr 30 12:40:20 PM PDT 24
Peak memory 212156 kb
Host smart-3aa75cb2-c261-4c1b-bab8-04b4a128ebc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064302211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2064302211
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1067540442
Short name T206
Test name
Test status
Simulation time 110869917813 ps
CPU time 398.33 seconds
Started Apr 30 12:39:54 PM PDT 24
Finished Apr 30 12:46:32 PM PDT 24
Peak memory 240320 kb
Host smart-1ebdb15a-08bc-4ace-b692-9c55488045d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067540442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1067540442
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.4276557476
Short name T307
Test name
Test status
Simulation time 15441649255 ps
CPU time 36.28 seconds
Started Apr 30 12:39:53 PM PDT 24
Finished Apr 30 12:40:30 PM PDT 24
Peak memory 215432 kb
Host smart-76053bbd-a64b-4562-8973-d4254ea4f962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276557476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.4276557476
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.4071533803
Short name T121
Test name
Test status
Simulation time 15795047892 ps
CPU time 34 seconds
Started Apr 30 12:39:55 PM PDT 24
Finished Apr 30 12:40:29 PM PDT 24
Peak memory 212884 kb
Host smart-fb622841-9e35-4b29-a7f9-cf1f8ef7ddc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4071533803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.4071533803
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3216169788
Short name T41
Test name
Test status
Simulation time 2469813285 ps
CPU time 36.24 seconds
Started Apr 30 12:39:55 PM PDT 24
Finished Apr 30 12:40:32 PM PDT 24
Peak memory 217056 kb
Host smart-b49a75ed-e8fe-4fbf-96d4-3f70960194d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216169788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3216169788
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.264370365
Short name T171
Test name
Test status
Simulation time 4396187517 ps
CPU time 80.21 seconds
Started Apr 30 12:39:52 PM PDT 24
Finished Apr 30 12:41:13 PM PDT 24
Peak memory 221680 kb
Host smart-c7496788-2180-4de5-8e16-177375991419
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264370365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.264370365
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1024682486
Short name T298
Test name
Test status
Simulation time 717791399 ps
CPU time 8.45 seconds
Started Apr 30 12:39:53 PM PDT 24
Finished Apr 30 12:40:02 PM PDT 24
Peak memory 211468 kb
Host smart-1367a8cc-8ff7-4012-b1ea-536d20c562f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024682486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1024682486
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.33002394
Short name T292
Test name
Test status
Simulation time 20720234227 ps
CPU time 508.81 seconds
Started Apr 30 12:39:59 PM PDT 24
Finished Apr 30 12:48:29 PM PDT 24
Peak memory 249228 kb
Host smart-31372282-9c4f-4870-b279-97201efea94f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33002394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_co
rrupt_sig_fatal_chk.33002394
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4213242925
Short name T233
Test name
Test status
Simulation time 700184671 ps
CPU time 14.81 seconds
Started Apr 30 12:39:52 PM PDT 24
Finished Apr 30 12:40:08 PM PDT 24
Peak memory 211484 kb
Host smart-4bfa2822-d259-4bb4-9453-eb7b461e7ee7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4213242925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.4213242925
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1415621110
Short name T316
Test name
Test status
Simulation time 1867659692 ps
CPU time 20.1 seconds
Started Apr 30 12:39:53 PM PDT 24
Finished Apr 30 12:40:13 PM PDT 24
Peak memory 217400 kb
Host smart-faff6a86-9634-4cdb-86f7-c75375b54662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415621110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1415621110
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.182425443
Short name T75
Test name
Test status
Simulation time 10456512355 ps
CPU time 53.76 seconds
Started Apr 30 12:39:54 PM PDT 24
Finished Apr 30 12:40:49 PM PDT 24
Peak memory 215812 kb
Host smart-4d003123-1e5e-41d2-9b77-29aadce24a81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182425443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.182425443
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2766010974
Short name T325
Test name
Test status
Simulation time 14364562208 ps
CPU time 29.33 seconds
Started Apr 30 12:39:52 PM PDT 24
Finished Apr 30 12:40:22 PM PDT 24
Peak memory 212360 kb
Host smart-f01bb1e3-473b-41c0-a6ca-035cd24e3e14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766010974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2766010974
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4256797141
Short name T177
Test name
Test status
Simulation time 63293473492 ps
CPU time 578.83 seconds
Started Apr 30 12:39:55 PM PDT 24
Finished Apr 30 12:49:35 PM PDT 24
Peak memory 228104 kb
Host smart-0d5b8df2-1488-47c7-9ff8-a3f5b49fbed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256797141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.4256797141
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.268264000
Short name T179
Test name
Test status
Simulation time 170294815377 ps
CPU time 72.67 seconds
Started Apr 30 12:39:54 PM PDT 24
Finished Apr 30 12:41:07 PM PDT 24
Peak memory 215260 kb
Host smart-777e5017-a59c-4171-899f-8d88129bd663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268264000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.268264000
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2719923998
Short name T43
Test name
Test status
Simulation time 185204496 ps
CPU time 10.35 seconds
Started Apr 30 12:39:55 PM PDT 24
Finished Apr 30 12:40:07 PM PDT 24
Peak memory 212500 kb
Host smart-86f8254d-0911-43f3-b7d8-b212513f538f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2719923998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2719923998
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1684014308
Short name T13
Test name
Test status
Simulation time 1224518222 ps
CPU time 20.24 seconds
Started Apr 30 12:39:56 PM PDT 24
Finished Apr 30 12:40:17 PM PDT 24
Peak memory 217504 kb
Host smart-92119cc0-2f1b-4cb8-93eb-6e17440025c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684014308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1684014308
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2641979772
Short name T37
Test name
Test status
Simulation time 18321271214 ps
CPU time 199.02 seconds
Started Apr 30 12:39:54 PM PDT 24
Finished Apr 30 12:43:14 PM PDT 24
Peak memory 221056 kb
Host smart-5a47eb1f-a875-4b95-b429-b14cdcdd40d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641979772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2641979772
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.829981394
Short name T210
Test name
Test status
Simulation time 340303541 ps
CPU time 10.66 seconds
Started Apr 30 12:39:56 PM PDT 24
Finished Apr 30 12:40:07 PM PDT 24
Peak memory 211580 kb
Host smart-8371e898-4e06-4d29-ad6b-50a91c3ef7ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829981394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.829981394
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2842527298
Short name T348
Test name
Test status
Simulation time 26928755188 ps
CPU time 260.89 seconds
Started Apr 30 12:39:55 PM PDT 24
Finished Apr 30 12:44:17 PM PDT 24
Peak memory 217184 kb
Host smart-fadb1962-2079-49a7-9b96-23d1b26615df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842527298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2842527298
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2004164763
Short name T251
Test name
Test status
Simulation time 14391102876 ps
CPU time 40.9 seconds
Started Apr 30 12:39:56 PM PDT 24
Finished Apr 30 12:40:38 PM PDT 24
Peak memory 215428 kb
Host smart-3d1ab92a-1cf5-49e7-8e85-3be4f1e90371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004164763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2004164763
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1882864183
Short name T284
Test name
Test status
Simulation time 6362779903 ps
CPU time 28.18 seconds
Started Apr 30 12:39:59 PM PDT 24
Finished Apr 30 12:40:28 PM PDT 24
Peak memory 213000 kb
Host smart-5f8845f4-b046-414c-b14e-da9153624c1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1882864183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1882864183
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1328957196
Short name T161
Test name
Test status
Simulation time 5857019073 ps
CPU time 50.66 seconds
Started Apr 30 12:39:55 PM PDT 24
Finished Apr 30 12:40:47 PM PDT 24
Peak memory 216980 kb
Host smart-5aedca40-a73d-49d3-8c58-62e859cb9051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328957196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1328957196
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.717682061
Short name T164
Test name
Test status
Simulation time 3990179629 ps
CPU time 50.71 seconds
Started Apr 30 12:39:55 PM PDT 24
Finished Apr 30 12:40:47 PM PDT 24
Peak memory 214408 kb
Host smart-bf8ffdf5-25f8-4e65-9135-a2e5e786503c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717682061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.717682061
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2370486131
Short name T231
Test name
Test status
Simulation time 8881625332 ps
CPU time 22.06 seconds
Started Apr 30 12:40:02 PM PDT 24
Finished Apr 30 12:40:25 PM PDT 24
Peak memory 212508 kb
Host smart-2c9c816a-c79a-4d79-9746-889ce9e6d00d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370486131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2370486131
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1765418827
Short name T254
Test name
Test status
Simulation time 38120242569 ps
CPU time 313.4 seconds
Started Apr 30 12:39:56 PM PDT 24
Finished Apr 30 12:45:10 PM PDT 24
Peak memory 219212 kb
Host smart-c71cacab-3c7f-42fa-9e75-e203fc3e2985
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765418827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1765418827
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3166687144
Short name T116
Test name
Test status
Simulation time 5244383740 ps
CPU time 36.32 seconds
Started Apr 30 12:39:53 PM PDT 24
Finished Apr 30 12:40:30 PM PDT 24
Peak memory 215240 kb
Host smart-ce1529ee-4ac2-47d2-b9da-c21703a76e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166687144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3166687144
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2927045166
Short name T349
Test name
Test status
Simulation time 16531599424 ps
CPU time 25.98 seconds
Started Apr 30 12:39:55 PM PDT 24
Finished Apr 30 12:40:22 PM PDT 24
Peak memory 212988 kb
Host smart-e8193c1a-d3af-4ada-86d9-55d2158803e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2927045166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2927045166
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.688448314
Short name T234
Test name
Test status
Simulation time 504800159 ps
CPU time 22.01 seconds
Started Apr 30 12:39:55 PM PDT 24
Finished Apr 30 12:40:18 PM PDT 24
Peak memory 217280 kb
Host smart-332cae1a-674d-4949-9b6e-0d562fa82502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688448314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.688448314
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1624735368
Short name T126
Test name
Test status
Simulation time 8586063516 ps
CPU time 82.49 seconds
Started Apr 30 12:39:52 PM PDT 24
Finished Apr 30 12:41:15 PM PDT 24
Peak memory 219504 kb
Host smart-172cf0e9-3700-4e4e-9bdb-c6b6a8f9f049
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624735368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1624735368
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3952390367
Short name T237
Test name
Test status
Simulation time 3097009291 ps
CPU time 25.5 seconds
Started Apr 30 12:40:05 PM PDT 24
Finished Apr 30 12:40:31 PM PDT 24
Peak memory 212168 kb
Host smart-3619a0ed-0a7c-410d-aca9-26ae6ce2b93f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952390367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3952390367
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.828159660
Short name T148
Test name
Test status
Simulation time 74262109698 ps
CPU time 349.33 seconds
Started Apr 30 12:40:27 PM PDT 24
Finished Apr 30 12:46:17 PM PDT 24
Peak memory 236984 kb
Host smart-92ba84f8-f4ae-4966-8bb2-1d70250a86c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828159660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.828159660
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2226015044
Short name T125
Test name
Test status
Simulation time 2852241300 ps
CPU time 38.48 seconds
Started Apr 30 12:40:05 PM PDT 24
Finished Apr 30 12:40:44 PM PDT 24
Peak memory 214980 kb
Host smart-f68c9ad4-12cf-4425-b4f7-52ca74422203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226015044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2226015044
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1740559312
Short name T193
Test name
Test status
Simulation time 354628947 ps
CPU time 10.14 seconds
Started Apr 30 12:40:01 PM PDT 24
Finished Apr 30 12:40:12 PM PDT 24
Peak memory 212848 kb
Host smart-67cac30b-189b-4954-bbe7-d445286d4b4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1740559312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1740559312
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3739058282
Short name T330
Test name
Test status
Simulation time 7500430237 ps
CPU time 66.28 seconds
Started Apr 30 12:40:02 PM PDT 24
Finished Apr 30 12:41:09 PM PDT 24
Peak memory 218124 kb
Host smart-8d3839c1-1bcb-44b2-afa8-0a6cf34c61ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739058282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3739058282
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3108026749
Short name T334
Test name
Test status
Simulation time 4809193587 ps
CPU time 23.04 seconds
Started Apr 30 12:40:03 PM PDT 24
Finished Apr 30 12:40:26 PM PDT 24
Peak memory 214540 kb
Host smart-5e6c3334-2a26-45c7-9738-b7615aa10ce6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108026749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3108026749
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.4003622040
Short name T247
Test name
Test status
Simulation time 4966325067 ps
CPU time 17.22 seconds
Started Apr 30 12:40:12 PM PDT 24
Finished Apr 30 12:40:30 PM PDT 24
Peak memory 211580 kb
Host smart-5a7d15e5-91c4-4c68-aee6-b0709d5b3f4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003622040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.4003622040
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3648435856
Short name T115
Test name
Test status
Simulation time 148798530416 ps
CPU time 718.77 seconds
Started Apr 30 12:40:03 PM PDT 24
Finished Apr 30 12:52:02 PM PDT 24
Peak memory 240812 kb
Host smart-842175b8-b9f4-49c9-b590-8c7e7e6fbc18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648435856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3648435856
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2834707178
Short name T277
Test name
Test status
Simulation time 11359607029 ps
CPU time 51.49 seconds
Started Apr 30 12:40:03 PM PDT 24
Finished Apr 30 12:40:55 PM PDT 24
Peak memory 215340 kb
Host smart-3b55415c-e7d1-448f-91d6-a4e230d97acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834707178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2834707178
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.760057917
Short name T180
Test name
Test status
Simulation time 2917841570 ps
CPU time 26.55 seconds
Started Apr 30 12:40:05 PM PDT 24
Finished Apr 30 12:40:32 PM PDT 24
Peak memory 211540 kb
Host smart-b072971f-b8b2-48a1-961d-2b068556b9fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=760057917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.760057917
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2010071662
Short name T38
Test name
Test status
Simulation time 6080886086 ps
CPU time 53.43 seconds
Started Apr 30 12:40:36 PM PDT 24
Finished Apr 30 12:41:30 PM PDT 24
Peak memory 218020 kb
Host smart-2d10207f-0a65-460a-9fca-7c1b8fd26af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010071662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2010071662
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1199520514
Short name T191
Test name
Test status
Simulation time 9891677249 ps
CPU time 27.87 seconds
Started Apr 30 12:40:03 PM PDT 24
Finished Apr 30 12:40:31 PM PDT 24
Peak memory 211920 kb
Host smart-f4cc2cd4-26ff-4b63-88bc-16409b27d06a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199520514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1199520514
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3948566347
Short name T118
Test name
Test status
Simulation time 16478429807 ps
CPU time 24.42 seconds
Started Apr 30 12:40:05 PM PDT 24
Finished Apr 30 12:40:29 PM PDT 24
Peak memory 211536 kb
Host smart-61ccebc3-1fbd-43c8-9198-6338b7ccb83b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948566347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3948566347
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.726962824
Short name T26
Test name
Test status
Simulation time 7965313644 ps
CPU time 157.11 seconds
Started Apr 30 12:40:11 PM PDT 24
Finished Apr 30 12:42:49 PM PDT 24
Peak memory 237172 kb
Host smart-72a38424-17be-451a-8c17-2905e04cfae0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726962824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.726962824
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2038899774
Short name T183
Test name
Test status
Simulation time 6668227427 ps
CPU time 57.33 seconds
Started Apr 30 12:40:06 PM PDT 24
Finished Apr 30 12:41:04 PM PDT 24
Peak memory 215544 kb
Host smart-8a6b5de8-df36-423e-95bb-190c2e7f9416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038899774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2038899774
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2288158143
Short name T154
Test name
Test status
Simulation time 266778959 ps
CPU time 11.85 seconds
Started Apr 30 12:40:02 PM PDT 24
Finished Apr 30 12:40:14 PM PDT 24
Peak memory 211724 kb
Host smart-0860a4a1-4224-4d4f-8abd-6173fdbdaf17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2288158143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2288158143
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3982268833
Short name T286
Test name
Test status
Simulation time 1334499906 ps
CPU time 28.14 seconds
Started Apr 30 12:40:03 PM PDT 24
Finished Apr 30 12:40:31 PM PDT 24
Peak memory 216644 kb
Host smart-999599f1-91e4-452a-b6db-ee9efa9e9813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982268833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3982268833
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3749169726
Short name T311
Test name
Test status
Simulation time 30576481494 ps
CPU time 74.57 seconds
Started Apr 30 12:40:04 PM PDT 24
Finished Apr 30 12:41:19 PM PDT 24
Peak memory 217428 kb
Host smart-85734a98-3be1-43dc-9ca5-00c36e770fe0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749169726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3749169726
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1536746547
Short name T49
Test name
Test status
Simulation time 29039365547 ps
CPU time 1050.61 seconds
Started Apr 30 12:40:11 PM PDT 24
Finished Apr 30 12:57:43 PM PDT 24
Peak memory 236048 kb
Host smart-02169ae7-f5ed-4ce3-8744-39838ef840a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536746547 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.1536746547
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1187582780
Short name T232
Test name
Test status
Simulation time 689122079 ps
CPU time 8.18 seconds
Started Apr 30 12:40:01 PM PDT 24
Finished Apr 30 12:40:10 PM PDT 24
Peak memory 211460 kb
Host smart-cf08ed05-1631-48e4-b437-45058c36e47b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187582780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1187582780
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4272205161
Short name T257
Test name
Test status
Simulation time 206925545846 ps
CPU time 461.12 seconds
Started Apr 30 12:40:12 PM PDT 24
Finished Apr 30 12:47:54 PM PDT 24
Peak memory 217060 kb
Host smart-552c2423-a6fb-4b83-af7c-974d95b680e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272205161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.4272205161
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1065304116
Short name T16
Test name
Test status
Simulation time 507990761 ps
CPU time 22.11 seconds
Started Apr 30 12:40:02 PM PDT 24
Finished Apr 30 12:40:25 PM PDT 24
Peak memory 212788 kb
Host smart-b7df7d85-3f98-4284-8129-a8abb2f277aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065304116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1065304116
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1223795821
Short name T197
Test name
Test status
Simulation time 466309655 ps
CPU time 13.41 seconds
Started Apr 30 12:40:03 PM PDT 24
Finished Apr 30 12:40:17 PM PDT 24
Peak memory 211480 kb
Host smart-f41d51ff-b086-497d-a930-95399dea493b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223795821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1223795821
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1942347819
Short name T163
Test name
Test status
Simulation time 3108787847 ps
CPU time 20.24 seconds
Started Apr 30 12:40:04 PM PDT 24
Finished Apr 30 12:40:24 PM PDT 24
Peak memory 217776 kb
Host smart-33a1f549-de7f-44a5-907c-418a01c29223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942347819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1942347819
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.749972259
Short name T6
Test name
Test status
Simulation time 16758057795 ps
CPU time 97.71 seconds
Started Apr 30 12:40:02 PM PDT 24
Finished Apr 30 12:41:40 PM PDT 24
Peak memory 219712 kb
Host smart-a5d338c3-3e00-4255-8c47-500f9495fac5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749972259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.749972259
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3072619654
Short name T356
Test name
Test status
Simulation time 8993790490 ps
CPU time 335 seconds
Started Apr 30 12:40:03 PM PDT 24
Finished Apr 30 12:45:39 PM PDT 24
Peak memory 219644 kb
Host smart-2a9548bd-c0c0-438a-8632-3be1c12c864e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072619654 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.3072619654
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3401825755
Short name T42
Test name
Test status
Simulation time 1228815539 ps
CPU time 16.7 seconds
Started Apr 30 12:39:44 PM PDT 24
Finished Apr 30 12:40:01 PM PDT 24
Peak memory 211508 kb
Host smart-c61a8365-7c6c-4225-bba8-8b4e6030fb92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401825755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3401825755
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2052638922
Short name T274
Test name
Test status
Simulation time 175150969684 ps
CPU time 486.05 seconds
Started Apr 30 12:39:39 PM PDT 24
Finished Apr 30 12:47:46 PM PDT 24
Peak memory 236892 kb
Host smart-cb2d2cd9-7785-4811-96dd-c5a6cbf78c10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052638922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2052638922
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1703079553
Short name T306
Test name
Test status
Simulation time 7445511234 ps
CPU time 61.99 seconds
Started Apr 30 12:39:45 PM PDT 24
Finished Apr 30 12:40:47 PM PDT 24
Peak memory 215256 kb
Host smart-993b7596-3373-4464-b2ef-a44065b784c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703079553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1703079553
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2373639940
Short name T132
Test name
Test status
Simulation time 721175139 ps
CPU time 10.22 seconds
Started Apr 30 12:39:38 PM PDT 24
Finished Apr 30 12:39:49 PM PDT 24
Peak memory 212872 kb
Host smart-a8dbd239-415c-4995-8e54-b65beb5b87a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2373639940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2373639940
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1341731031
Short name T35
Test name
Test status
Simulation time 6488165509 ps
CPU time 234.75 seconds
Started Apr 30 12:39:47 PM PDT 24
Finished Apr 30 12:43:42 PM PDT 24
Peak memory 238816 kb
Host smart-00440d75-cb3a-4195-a702-4a9c9a70c7c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341731031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1341731031
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1053099607
Short name T201
Test name
Test status
Simulation time 15769318098 ps
CPU time 74.65 seconds
Started Apr 30 12:39:41 PM PDT 24
Finished Apr 30 12:40:56 PM PDT 24
Peak memory 215596 kb
Host smart-74978519-21d9-4d9f-a388-b57da2b8f44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053099607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1053099607
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.25668518
Short name T74
Test name
Test status
Simulation time 15938611054 ps
CPU time 64.2 seconds
Started Apr 30 12:40:53 PM PDT 24
Finished Apr 30 12:41:58 PM PDT 24
Peak memory 227456 kb
Host smart-af528419-90ae-446d-ad1d-342a5bf61912
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25668518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.rom_ctrl_stress_all.25668518
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3870243974
Short name T141
Test name
Test status
Simulation time 2295797901 ps
CPU time 21.66 seconds
Started Apr 30 12:40:09 PM PDT 24
Finished Apr 30 12:40:31 PM PDT 24
Peak memory 212192 kb
Host smart-0ff1349d-b48d-4a77-93d7-b6302bc8b9c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870243974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3870243974
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2682554714
Short name T45
Test name
Test status
Simulation time 198731671122 ps
CPU time 437.39 seconds
Started Apr 30 12:40:04 PM PDT 24
Finished Apr 30 12:47:22 PM PDT 24
Peak memory 240056 kb
Host smart-e33b75c5-d1c5-4697-ac31-b80cd61edbaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682554714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2682554714
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3162457861
Short name T145
Test name
Test status
Simulation time 1373568064 ps
CPU time 19.71 seconds
Started Apr 30 12:40:11 PM PDT 24
Finished Apr 30 12:40:31 PM PDT 24
Peak memory 214868 kb
Host smart-796e21be-d8bd-42d4-b8c8-d9dc23e7ac91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162457861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3162457861
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.582525521
Short name T333
Test name
Test status
Simulation time 363229838 ps
CPU time 10.36 seconds
Started Apr 30 12:40:03 PM PDT 24
Finished Apr 30 12:40:14 PM PDT 24
Peak memory 212500 kb
Host smart-f2eea13e-7868-4617-9bcd-bde662fb4aaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=582525521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.582525521
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3159534273
Short name T158
Test name
Test status
Simulation time 523011126 ps
CPU time 23.43 seconds
Started Apr 30 12:40:05 PM PDT 24
Finished Apr 30 12:40:29 PM PDT 24
Peak memory 215484 kb
Host smart-395826c2-4612-47ed-94ac-546c5ee6bb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159534273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3159534273
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3345084358
Short name T305
Test name
Test status
Simulation time 59707466612 ps
CPU time 156.31 seconds
Started Apr 30 12:40:12 PM PDT 24
Finished Apr 30 12:42:48 PM PDT 24
Peak memory 220068 kb
Host smart-b326d799-38f7-4c77-bded-036b746be140
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345084358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3345084358
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3438938609
Short name T278
Test name
Test status
Simulation time 12074591915 ps
CPU time 26.6 seconds
Started Apr 30 12:40:09 PM PDT 24
Finished Apr 30 12:40:36 PM PDT 24
Peak memory 212416 kb
Host smart-dcb66b64-5a4d-4e94-bf12-7202e020db81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438938609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3438938609
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.420994123
Short name T165
Test name
Test status
Simulation time 65639518848 ps
CPU time 538.23 seconds
Started Apr 30 12:40:09 PM PDT 24
Finished Apr 30 12:49:07 PM PDT 24
Peak memory 237944 kb
Host smart-cf71cd15-c275-464e-ab76-76cccbf7ea96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420994123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.420994123
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.535776692
Short name T19
Test name
Test status
Simulation time 23902871922 ps
CPU time 51.39 seconds
Started Apr 30 12:40:12 PM PDT 24
Finished Apr 30 12:41:04 PM PDT 24
Peak memory 215116 kb
Host smart-227fe5e3-048a-4663-aa17-7533353fd620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535776692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.535776692
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3585215459
Short name T243
Test name
Test status
Simulation time 6300375749 ps
CPU time 24.32 seconds
Started Apr 30 12:40:09 PM PDT 24
Finished Apr 30 12:40:34 PM PDT 24
Peak memory 211744 kb
Host smart-bab0ba2b-2c1e-43d7-b371-d003f2e4d65c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3585215459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3585215459
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.377355245
Short name T352
Test name
Test status
Simulation time 7858477759 ps
CPU time 71.13 seconds
Started Apr 30 12:40:13 PM PDT 24
Finished Apr 30 12:41:25 PM PDT 24
Peak memory 217960 kb
Host smart-97c9591e-617d-41c0-9cd5-c6b8155a5617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377355245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.377355245
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.214824980
Short name T351
Test name
Test status
Simulation time 30887037993 ps
CPU time 123.31 seconds
Started Apr 30 12:40:14 PM PDT 24
Finished Apr 30 12:42:17 PM PDT 24
Peak memory 220112 kb
Host smart-d7a773a8-d033-4dd3-a7fc-95cb8f1955e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214824980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.214824980
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3136681918
Short name T53
Test name
Test status
Simulation time 186731440520 ps
CPU time 1635.47 seconds
Started Apr 30 12:40:10 PM PDT 24
Finished Apr 30 01:07:26 PM PDT 24
Peak memory 244284 kb
Host smart-3868bdd4-3be1-4314-85ff-0f7e04c80b63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136681918 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.3136681918
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.111073889
Short name T229
Test name
Test status
Simulation time 2381906389 ps
CPU time 21.3 seconds
Started Apr 30 12:40:08 PM PDT 24
Finished Apr 30 12:40:30 PM PDT 24
Peak memory 211584 kb
Host smart-6f311114-eb56-4c92-8b8b-108d91565d21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111073889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.111073889
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2621628539
Short name T355
Test name
Test status
Simulation time 37567183638 ps
CPU time 58.09 seconds
Started Apr 30 12:40:11 PM PDT 24
Finished Apr 30 12:41:10 PM PDT 24
Peak memory 214080 kb
Host smart-f0c4f346-da80-40e2-82ff-591578c7679a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621628539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2621628539
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3476067931
Short name T134
Test name
Test status
Simulation time 183035118 ps
CPU time 10.6 seconds
Started Apr 30 12:40:10 PM PDT 24
Finished Apr 30 12:40:21 PM PDT 24
Peak memory 212504 kb
Host smart-2c8d7012-c564-4a3d-baba-4c8f2d9c6258
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3476067931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3476067931
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.122574246
Short name T218
Test name
Test status
Simulation time 26683903128 ps
CPU time 32.03 seconds
Started Apr 30 12:41:09 PM PDT 24
Finished Apr 30 12:41:42 PM PDT 24
Peak memory 217808 kb
Host smart-548b1f30-4f0e-429d-851f-8ea243957290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122574246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.122574246
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1098371757
Short name T136
Test name
Test status
Simulation time 2362679535 ps
CPU time 10.45 seconds
Started Apr 30 12:40:11 PM PDT 24
Finished Apr 30 12:40:22 PM PDT 24
Peak memory 213904 kb
Host smart-d194d617-c9fa-4b15-8c1e-c5bac0781bef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098371757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1098371757
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.524342794
Short name T222
Test name
Test status
Simulation time 22781306986 ps
CPU time 21.2 seconds
Started Apr 30 12:40:21 PM PDT 24
Finished Apr 30 12:40:43 PM PDT 24
Peak memory 212460 kb
Host smart-909d8c22-c4ab-46bf-aa8a-eb8e231ec4e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524342794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.524342794
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2101274053
Short name T46
Test name
Test status
Simulation time 13807971443 ps
CPU time 311.24 seconds
Started Apr 30 12:40:09 PM PDT 24
Finished Apr 30 12:45:21 PM PDT 24
Peak memory 225896 kb
Host smart-519b8e17-8155-4a98-8aad-962de3024108
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101274053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2101274053
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1988911407
Short name T89
Test name
Test status
Simulation time 3029402746 ps
CPU time 27.24 seconds
Started Apr 30 12:40:12 PM PDT 24
Finished Apr 30 12:40:40 PM PDT 24
Peak memory 212620 kb
Host smart-5d33adf7-1c0e-4f43-94d0-b30d3a0b9798
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988911407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1988911407
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2723520582
Short name T2
Test name
Test status
Simulation time 67157165015 ps
CPU time 64.49 seconds
Started Apr 30 12:40:14 PM PDT 24
Finished Apr 30 12:41:19 PM PDT 24
Peak memory 217748 kb
Host smart-24de07fa-eed0-4993-bc2f-0b4026e91474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723520582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2723520582
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1091076418
Short name T5
Test name
Test status
Simulation time 50458692240 ps
CPU time 97.6 seconds
Started Apr 30 12:40:10 PM PDT 24
Finished Apr 30 12:41:48 PM PDT 24
Peak memory 221164 kb
Host smart-4eab323c-0372-4a4b-89f7-a2670c9d88bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091076418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1091076418
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2335280869
Short name T291
Test name
Test status
Simulation time 431640768 ps
CPU time 11.51 seconds
Started Apr 30 12:40:19 PM PDT 24
Finished Apr 30 12:40:31 PM PDT 24
Peak memory 211548 kb
Host smart-31a1823b-d073-48a6-8889-147332a1bffc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335280869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2335280869
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3976911678
Short name T192
Test name
Test status
Simulation time 19803179625 ps
CPU time 316.71 seconds
Started Apr 30 12:40:22 PM PDT 24
Finished Apr 30 12:45:39 PM PDT 24
Peak memory 238712 kb
Host smart-a22126b5-d24d-49c5-abc6-a4119098e2d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976911678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3976911678
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.784226950
Short name T207
Test name
Test status
Simulation time 526056658 ps
CPU time 19.35 seconds
Started Apr 30 12:40:19 PM PDT 24
Finished Apr 30 12:40:39 PM PDT 24
Peak memory 214816 kb
Host smart-f82ce0c3-db80-48e8-a73b-a2346e4f2ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784226950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.784226950
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.977129683
Short name T339
Test name
Test status
Simulation time 6963794358 ps
CPU time 32.49 seconds
Started Apr 30 12:40:18 PM PDT 24
Finished Apr 30 12:40:52 PM PDT 24
Peak memory 211952 kb
Host smart-258b6430-7ce2-4064-aeb0-ec79edc61c64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=977129683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.977129683
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3500156934
Short name T299
Test name
Test status
Simulation time 16487574163 ps
CPU time 47.8 seconds
Started Apr 30 12:40:18 PM PDT 24
Finished Apr 30 12:41:07 PM PDT 24
Peak memory 217892 kb
Host smart-707c9800-015a-42e6-b21a-9a769ddc755c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500156934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3500156934
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.36506406
Short name T331
Test name
Test status
Simulation time 25603116387 ps
CPU time 64.05 seconds
Started Apr 30 12:40:20 PM PDT 24
Finished Apr 30 12:41:25 PM PDT 24
Peak memory 218244 kb
Host smart-281920a4-911c-465a-9c3b-d384eebd17d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36506406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 24.rom_ctrl_stress_all.36506406
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.599029069
Short name T249
Test name
Test status
Simulation time 2713800568 ps
CPU time 24.65 seconds
Started Apr 30 12:40:18 PM PDT 24
Finished Apr 30 12:40:43 PM PDT 24
Peak memory 211492 kb
Host smart-dd7cf41a-0384-428c-8bae-3dfc4a2bc5b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599029069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.599029069
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3885656388
Short name T268
Test name
Test status
Simulation time 407914440474 ps
CPU time 546.19 seconds
Started Apr 30 12:40:24 PM PDT 24
Finished Apr 30 12:49:31 PM PDT 24
Peak memory 235124 kb
Host smart-1f8cabdf-b24d-4b44-91f5-74d49c776bfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885656388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3885656388
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3538052691
Short name T173
Test name
Test status
Simulation time 6578852630 ps
CPU time 55.43 seconds
Started Apr 30 12:40:18 PM PDT 24
Finished Apr 30 12:41:14 PM PDT 24
Peak memory 215320 kb
Host smart-9a0806ed-3907-45ee-99c5-131b9977fa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538052691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3538052691
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3890998668
Short name T139
Test name
Test status
Simulation time 64159783138 ps
CPU time 33.53 seconds
Started Apr 30 12:40:19 PM PDT 24
Finished Apr 30 12:40:54 PM PDT 24
Peak memory 212924 kb
Host smart-92c7420b-f778-441d-aaa7-c443bfd4dc15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3890998668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3890998668
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3974121053
Short name T336
Test name
Test status
Simulation time 19081498075 ps
CPU time 49.15 seconds
Started Apr 30 12:40:20 PM PDT 24
Finished Apr 30 12:41:10 PM PDT 24
Peak memory 218096 kb
Host smart-5d38b96a-58fe-49de-9662-5c2af4411414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974121053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3974121053
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3040340992
Short name T91
Test name
Test status
Simulation time 12858162387 ps
CPU time 72.76 seconds
Started Apr 30 12:40:18 PM PDT 24
Finished Apr 30 12:41:32 PM PDT 24
Peak memory 220160 kb
Host smart-535f7bb6-da37-4e13-92dc-c8a6866c9885
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040340992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3040340992
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3703326261
Short name T304
Test name
Test status
Simulation time 8835597866 ps
CPU time 16.03 seconds
Started Apr 30 12:40:18 PM PDT 24
Finished Apr 30 12:40:35 PM PDT 24
Peak memory 211528 kb
Host smart-71ea9018-68a8-4a70-a484-7cd2ec5f8b3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703326261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3703326261
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2821921859
Short name T151
Test name
Test status
Simulation time 2529034722 ps
CPU time 28.22 seconds
Started Apr 30 12:40:18 PM PDT 24
Finished Apr 30 12:40:47 PM PDT 24
Peak memory 213876 kb
Host smart-22131e3f-2a03-44ea-ba91-09d5d0ce5db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821921859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2821921859
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2151426186
Short name T230
Test name
Test status
Simulation time 10543643239 ps
CPU time 24.35 seconds
Started Apr 30 12:40:20 PM PDT 24
Finished Apr 30 12:40:45 PM PDT 24
Peak memory 211676 kb
Host smart-9fb987c0-69e5-4c8d-8f93-5681b7a0b283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2151426186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2151426186
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.233774593
Short name T88
Test name
Test status
Simulation time 6862284099 ps
CPU time 19.42 seconds
Started Apr 30 12:40:18 PM PDT 24
Finished Apr 30 12:40:38 PM PDT 24
Peak memory 218572 kb
Host smart-cb8283bf-764f-435b-a084-d670e3fa5c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233774593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.233774593
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.343667882
Short name T198
Test name
Test status
Simulation time 1076330391 ps
CPU time 19.75 seconds
Started Apr 30 12:40:18 PM PDT 24
Finished Apr 30 12:40:38 PM PDT 24
Peak memory 213560 kb
Host smart-3daa8d10-a20d-4838-a930-ebed844984eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343667882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.343667882
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3727142470
Short name T52
Test name
Test status
Simulation time 77319645463 ps
CPU time 2865.94 seconds
Started Apr 30 12:40:19 PM PDT 24
Finished Apr 30 01:28:06 PM PDT 24
Peak memory 244372 kb
Host smart-f97e3d94-8616-429e-93c9-10cd3d677a50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727142470 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3727142470
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1468500490
Short name T302
Test name
Test status
Simulation time 2590202142 ps
CPU time 18.76 seconds
Started Apr 30 12:40:18 PM PDT 24
Finished Apr 30 12:40:38 PM PDT 24
Peak memory 211520 kb
Host smart-7081c4c4-6243-4cff-8e37-50549d87927d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468500490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1468500490
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3400633118
Short name T283
Test name
Test status
Simulation time 83305577290 ps
CPU time 824.41 seconds
Started Apr 30 12:40:18 PM PDT 24
Finished Apr 30 12:54:04 PM PDT 24
Peak memory 240040 kb
Host smart-87f77f82-a36e-4b96-a277-79e60873beff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400633118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3400633118
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3231742152
Short name T143
Test name
Test status
Simulation time 663019979 ps
CPU time 18.83 seconds
Started Apr 30 12:40:19 PM PDT 24
Finished Apr 30 12:40:39 PM PDT 24
Peak memory 215356 kb
Host smart-f05f1d0b-01b3-45a6-b976-4ab7d60fee2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231742152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3231742152
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.304830174
Short name T270
Test name
Test status
Simulation time 39173511518 ps
CPU time 33.8 seconds
Started Apr 30 12:40:18 PM PDT 24
Finished Apr 30 12:40:53 PM PDT 24
Peak memory 211484 kb
Host smart-50dbf65a-f27c-4b9f-8808-bdee4f4990a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=304830174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.304830174
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1729368331
Short name T147
Test name
Test status
Simulation time 38752508222 ps
CPU time 63.08 seconds
Started Apr 30 12:40:18 PM PDT 24
Finished Apr 30 12:41:22 PM PDT 24
Peak memory 218376 kb
Host smart-65312050-9f64-4ac9-a5d2-87abc4c83482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729368331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1729368331
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2198526160
Short name T223
Test name
Test status
Simulation time 14575187190 ps
CPU time 119.44 seconds
Started Apr 30 12:40:18 PM PDT 24
Finished Apr 30 12:42:19 PM PDT 24
Peak memory 219708 kb
Host smart-7ace982f-afd0-4b59-8c9a-ac5e60856e0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198526160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2198526160
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.232842404
Short name T160
Test name
Test status
Simulation time 225334147 ps
CPU time 8.61 seconds
Started Apr 30 12:40:21 PM PDT 24
Finished Apr 30 12:40:30 PM PDT 24
Peak memory 211528 kb
Host smart-25c44028-69cb-4e8a-afbe-ce56a1862093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232842404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.232842404
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1104296388
Short name T242
Test name
Test status
Simulation time 6030847876 ps
CPU time 200.44 seconds
Started Apr 30 12:40:23 PM PDT 24
Finished Apr 30 12:43:44 PM PDT 24
Peak memory 238220 kb
Host smart-8feeb972-76a3-45d9-b59f-899b8cfd0b1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104296388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1104296388
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2235219238
Short name T312
Test name
Test status
Simulation time 2061086028 ps
CPU time 21.83 seconds
Started Apr 30 12:40:18 PM PDT 24
Finished Apr 30 12:40:41 PM PDT 24
Peak memory 215148 kb
Host smart-24be907d-9a59-407e-9858-228ee0d9e7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235219238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2235219238
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3540408553
Short name T90
Test name
Test status
Simulation time 1356300763 ps
CPU time 18.75 seconds
Started Apr 30 12:40:19 PM PDT 24
Finished Apr 30 12:40:39 PM PDT 24
Peak memory 211496 kb
Host smart-3b3f7def-969b-4d6d-b322-4792f39b1d20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3540408553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3540408553
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1284689616
Short name T318
Test name
Test status
Simulation time 23288729706 ps
CPU time 58.09 seconds
Started Apr 30 12:40:21 PM PDT 24
Finished Apr 30 12:41:20 PM PDT 24
Peak memory 216932 kb
Host smart-6f4a72e3-58b9-4c64-9dc0-a1a72a271f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284689616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1284689616
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1714730246
Short name T93
Test name
Test status
Simulation time 16470029651 ps
CPU time 130.32 seconds
Started Apr 30 12:40:20 PM PDT 24
Finished Apr 30 12:42:31 PM PDT 24
Peak memory 220396 kb
Host smart-9a796bbb-28e2-49f4-96eb-d6bad3a6804c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714730246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1714730246
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3145234357
Short name T281
Test name
Test status
Simulation time 2468320865 ps
CPU time 23.18 seconds
Started Apr 30 12:40:20 PM PDT 24
Finished Apr 30 12:40:44 PM PDT 24
Peak memory 211572 kb
Host smart-ed1c71ab-7cf8-4e1c-b72a-7ad1b7a92c85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145234357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3145234357
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2014321383
Short name T157
Test name
Test status
Simulation time 112372205538 ps
CPU time 189.66 seconds
Started Apr 30 12:40:20 PM PDT 24
Finished Apr 30 12:43:30 PM PDT 24
Peak memory 228216 kb
Host smart-1962b7d8-4165-4649-adc8-9995a0f243e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014321383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2014321383
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1204715781
Short name T18
Test name
Test status
Simulation time 346130481 ps
CPU time 19.13 seconds
Started Apr 30 12:40:19 PM PDT 24
Finished Apr 30 12:40:39 PM PDT 24
Peak memory 215024 kb
Host smart-d8c69a23-4516-4f49-b1e3-b547e616cc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204715781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1204715781
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1954151570
Short name T104
Test name
Test status
Simulation time 4344962864 ps
CPU time 22.58 seconds
Started Apr 30 12:40:18 PM PDT 24
Finished Apr 30 12:40:41 PM PDT 24
Peak memory 212776 kb
Host smart-aee192c4-6778-4643-89de-74e8718f67bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1954151570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1954151570
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.312524708
Short name T250
Test name
Test status
Simulation time 2797139453 ps
CPU time 36.9 seconds
Started Apr 30 12:40:20 PM PDT 24
Finished Apr 30 12:40:58 PM PDT 24
Peak memory 217528 kb
Host smart-df8c982e-18ff-4f12-be8f-dbfdc7d2c32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312524708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.312524708
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2928922420
Short name T168
Test name
Test status
Simulation time 40997669506 ps
CPU time 204.08 seconds
Started Apr 30 12:40:24 PM PDT 24
Finished Apr 30 12:43:49 PM PDT 24
Peak memory 220416 kb
Host smart-42bff031-494c-481d-9152-58920b46971c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928922420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2928922420
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3751660799
Short name T32
Test name
Test status
Simulation time 16641138126 ps
CPU time 32.16 seconds
Started Apr 30 12:39:46 PM PDT 24
Finished Apr 30 12:40:19 PM PDT 24
Peak memory 212500 kb
Host smart-a09cc4ce-c960-414b-b1cf-69cdd8108d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751660799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3751660799
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2186377578
Short name T130
Test name
Test status
Simulation time 163552941034 ps
CPU time 211.99 seconds
Started Apr 30 12:39:46 PM PDT 24
Finished Apr 30 12:43:19 PM PDT 24
Peak memory 240628 kb
Host smart-04c57185-4f53-4ccb-9e08-ded7e71b84fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186377578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2186377578
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1558776899
Short name T313
Test name
Test status
Simulation time 4767626260 ps
CPU time 40.51 seconds
Started Apr 30 12:39:50 PM PDT 24
Finished Apr 30 12:40:31 PM PDT 24
Peak memory 215340 kb
Host smart-bba06a7b-9cd6-40af-ae2d-6c5df92a68e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558776899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1558776899
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.379281613
Short name T131
Test name
Test status
Simulation time 33097734832 ps
CPU time 28.44 seconds
Started Apr 30 12:39:44 PM PDT 24
Finished Apr 30 12:40:14 PM PDT 24
Peak memory 211996 kb
Host smart-3fdefb3e-db6d-4ae9-9261-95d96492dcda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=379281613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.379281613
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.4028337493
Short name T30
Test name
Test status
Simulation time 2212157953 ps
CPU time 121.25 seconds
Started Apr 30 12:39:46 PM PDT 24
Finished Apr 30 12:41:48 PM PDT 24
Peak memory 237656 kb
Host smart-58d9a569-0475-4e54-a204-6e90cb012be4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028337493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4028337493
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2790205592
Short name T190
Test name
Test status
Simulation time 22991927645 ps
CPU time 64.07 seconds
Started Apr 30 12:39:44 PM PDT 24
Finished Apr 30 12:40:49 PM PDT 24
Peak memory 217348 kb
Host smart-00ca674d-6fb7-42df-99f4-b5cabc16f813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790205592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2790205592
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3927541529
Short name T252
Test name
Test status
Simulation time 1395212094 ps
CPU time 27.78 seconds
Started Apr 30 12:39:49 PM PDT 24
Finished Apr 30 12:40:18 PM PDT 24
Peak memory 218112 kb
Host smart-4442592d-8dd1-43d0-904a-bde805055251
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927541529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3927541529
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1118805851
Short name T239
Test name
Test status
Simulation time 7551838820 ps
CPU time 19.89 seconds
Started Apr 30 12:40:26 PM PDT 24
Finished Apr 30 12:40:46 PM PDT 24
Peak memory 211548 kb
Host smart-252367a1-0726-44f8-af2d-330a1d887213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118805851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1118805851
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2082287912
Short name T358
Test name
Test status
Simulation time 39665995147 ps
CPU time 390.03 seconds
Started Apr 30 12:40:20 PM PDT 24
Finished Apr 30 12:46:51 PM PDT 24
Peak memory 237120 kb
Host smart-bcda77bd-079f-45c3-aa76-ece02e67bcf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082287912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2082287912
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3880594998
Short name T309
Test name
Test status
Simulation time 21850697760 ps
CPU time 51.15 seconds
Started Apr 30 12:40:27 PM PDT 24
Finished Apr 30 12:41:18 PM PDT 24
Peak memory 215148 kb
Host smart-b7ae5aee-2601-47bc-9d30-4283f3bcdab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880594998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3880594998
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2208820803
Short name T315
Test name
Test status
Simulation time 1957432396 ps
CPU time 10.46 seconds
Started Apr 30 12:40:19 PM PDT 24
Finished Apr 30 12:40:30 PM PDT 24
Peak memory 212904 kb
Host smart-1e9f5f45-1175-4553-acd7-41c6fd68c54f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2208820803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2208820803
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2586876553
Short name T176
Test name
Test status
Simulation time 684313347 ps
CPU time 20.2 seconds
Started Apr 30 12:40:24 PM PDT 24
Finished Apr 30 12:40:45 PM PDT 24
Peak memory 216928 kb
Host smart-c77c504e-5161-4d98-8cf9-a14dd1babb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586876553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2586876553
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.936120042
Short name T256
Test name
Test status
Simulation time 8045127736 ps
CPU time 25.65 seconds
Started Apr 30 12:40:18 PM PDT 24
Finished Apr 30 12:40:44 PM PDT 24
Peak memory 214472 kb
Host smart-90be2854-72b5-493b-9a0b-7c95457e881c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936120042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.936120042
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1381820361
Short name T235
Test name
Test status
Simulation time 6354713223 ps
CPU time 25.55 seconds
Started Apr 30 12:40:28 PM PDT 24
Finished Apr 30 12:40:54 PM PDT 24
Peak memory 212364 kb
Host smart-3aaacc08-cef8-4655-a394-3febf9b8e8c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381820361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1381820361
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1782652362
Short name T293
Test name
Test status
Simulation time 280645486738 ps
CPU time 718.89 seconds
Started Apr 30 12:40:27 PM PDT 24
Finished Apr 30 12:52:27 PM PDT 24
Peak memory 217472 kb
Host smart-75a1e7a4-f6c6-4bb3-9184-8bfaf9cf2995
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782652362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1782652362
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.480292293
Short name T135
Test name
Test status
Simulation time 14868152717 ps
CPU time 38.23 seconds
Started Apr 30 12:40:26 PM PDT 24
Finished Apr 30 12:41:05 PM PDT 24
Peak memory 215248 kb
Host smart-82df0cdd-4d7b-45ba-a673-009a7242e7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480292293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.480292293
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3854315243
Short name T329
Test name
Test status
Simulation time 3342547841 ps
CPU time 29.19 seconds
Started Apr 30 12:40:27 PM PDT 24
Finished Apr 30 12:40:57 PM PDT 24
Peak memory 211504 kb
Host smart-56cb5f21-9a02-4fec-92ae-df7ae097aeec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3854315243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3854315243
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2696325159
Short name T321
Test name
Test status
Simulation time 8601946876 ps
CPU time 35.46 seconds
Started Apr 30 12:40:33 PM PDT 24
Finished Apr 30 12:41:09 PM PDT 24
Peak memory 217680 kb
Host smart-a5fa8ed0-705b-4b9b-9c33-7ceca83f8541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696325159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2696325159
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.765103842
Short name T137
Test name
Test status
Simulation time 28745384027 ps
CPU time 69.45 seconds
Started Apr 30 12:40:28 PM PDT 24
Finished Apr 30 12:41:38 PM PDT 24
Peak memory 216548 kb
Host smart-cb82f3ef-e868-4e7a-88a9-bbceadc517f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765103842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.765103842
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1604650146
Short name T61
Test name
Test status
Simulation time 7517887576 ps
CPU time 29.54 seconds
Started Apr 30 12:40:37 PM PDT 24
Finished Apr 30 12:41:08 PM PDT 24
Peak memory 212300 kb
Host smart-77a36e7b-72a5-4500-b82a-a650bcc19042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604650146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1604650146
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3207740528
Short name T219
Test name
Test status
Simulation time 40959263191 ps
CPU time 407.31 seconds
Started Apr 30 12:40:34 PM PDT 24
Finished Apr 30 12:47:21 PM PDT 24
Peak memory 219168 kb
Host smart-897ba20b-23e8-4157-b89d-78bcc8a82a0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207740528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3207740528
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1518175001
Short name T25
Test name
Test status
Simulation time 2307631038 ps
CPU time 34.55 seconds
Started Apr 30 12:40:33 PM PDT 24
Finished Apr 30 12:41:08 PM PDT 24
Peak memory 214988 kb
Host smart-1297c91c-4379-450a-92df-c2983b7eba2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518175001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1518175001
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3676850901
Short name T258
Test name
Test status
Simulation time 342128324 ps
CPU time 10.12 seconds
Started Apr 30 12:40:26 PM PDT 24
Finished Apr 30 12:40:37 PM PDT 24
Peak memory 212676 kb
Host smart-507345c5-bf2c-4fa8-a7b2-2cc91ab82480
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3676850901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3676850901
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.522569763
Short name T7
Test name
Test status
Simulation time 17738134279 ps
CPU time 68.08 seconds
Started Apr 30 12:40:27 PM PDT 24
Finished Apr 30 12:41:36 PM PDT 24
Peak memory 218276 kb
Host smart-c892aa4f-d27d-4141-95bc-e9f445d065c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522569763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.522569763
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2744036408
Short name T128
Test name
Test status
Simulation time 11893596211 ps
CPU time 72.01 seconds
Started Apr 30 12:40:30 PM PDT 24
Finished Apr 30 12:41:42 PM PDT 24
Peak memory 219680 kb
Host smart-ca86cae2-3c7f-495c-8fad-70d8ae4ee04f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744036408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2744036408
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.717511489
Short name T224
Test name
Test status
Simulation time 15366983018 ps
CPU time 31.85 seconds
Started Apr 30 12:40:34 PM PDT 24
Finished Apr 30 12:41:06 PM PDT 24
Peak memory 211572 kb
Host smart-21eab7bd-7b75-46c1-a38c-e5d71db4aaff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717511489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.717511489
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2657221769
Short name T155
Test name
Test status
Simulation time 372249498086 ps
CPU time 947.27 seconds
Started Apr 30 12:40:35 PM PDT 24
Finished Apr 30 12:56:23 PM PDT 24
Peak memory 237992 kb
Host smart-183f3725-b6c5-445f-a200-1968750a5294
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657221769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2657221769
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.725455223
Short name T4
Test name
Test status
Simulation time 12290592449 ps
CPU time 41.72 seconds
Started Apr 30 12:40:34 PM PDT 24
Finished Apr 30 12:41:16 PM PDT 24
Peak memory 215160 kb
Host smart-4cee29b7-060f-49eb-be89-e4f36d76120d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725455223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.725455223
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2049510636
Short name T354
Test name
Test status
Simulation time 4369795822 ps
CPU time 33.39 seconds
Started Apr 30 12:40:35 PM PDT 24
Finished Apr 30 12:41:09 PM PDT 24
Peak memory 212756 kb
Host smart-d9575ea3-7245-4494-9fed-a464ca6553bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2049510636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2049510636
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.497860814
Short name T1
Test name
Test status
Simulation time 40436743759 ps
CPU time 51.48 seconds
Started Apr 30 12:40:34 PM PDT 24
Finished Apr 30 12:41:26 PM PDT 24
Peak memory 218796 kb
Host smart-348c40cf-9f45-4d97-ac20-5006994b38e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497860814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.497860814
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2364182883
Short name T47
Test name
Test status
Simulation time 4001947052 ps
CPU time 56.51 seconds
Started Apr 30 12:40:34 PM PDT 24
Finished Apr 30 12:41:31 PM PDT 24
Peak memory 219508 kb
Host smart-fad40087-0727-40ee-ba4c-8764d765838a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364182883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2364182883
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2009741505
Short name T21
Test name
Test status
Simulation time 55696809462 ps
CPU time 557.93 seconds
Started Apr 30 12:40:38 PM PDT 24
Finished Apr 30 12:49:57 PM PDT 24
Peak memory 238104 kb
Host smart-b3c7940b-3f22-4b18-a6d9-5796abe9e66c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009741505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2009741505
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2899203019
Short name T269
Test name
Test status
Simulation time 1434236144 ps
CPU time 19.28 seconds
Started Apr 30 12:40:43 PM PDT 24
Finished Apr 30 12:41:02 PM PDT 24
Peak memory 215104 kb
Host smart-048a0c77-68e0-44bf-95da-db9e12e2a5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899203019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2899203019
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3016069255
Short name T181
Test name
Test status
Simulation time 24583989195 ps
CPU time 23.91 seconds
Started Apr 30 12:40:35 PM PDT 24
Finished Apr 30 12:40:59 PM PDT 24
Peak memory 211984 kb
Host smart-3525cfb4-4afd-4404-9fe3-c3215e988621
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3016069255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3016069255
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1749132162
Short name T253
Test name
Test status
Simulation time 353217010 ps
CPU time 20.05 seconds
Started Apr 30 12:40:35 PM PDT 24
Finished Apr 30 12:40:56 PM PDT 24
Peak memory 218020 kb
Host smart-d6dc0fa0-30f3-495b-8fa6-1eff4fd17015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749132162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1749132162
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3633813903
Short name T303
Test name
Test status
Simulation time 3233352041 ps
CPU time 29.03 seconds
Started Apr 30 12:40:38 PM PDT 24
Finished Apr 30 12:41:07 PM PDT 24
Peak memory 213744 kb
Host smart-0bda8a58-dd00-4bb3-b82b-2eacc72a7087
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633813903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3633813903
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2567775406
Short name T216
Test name
Test status
Simulation time 345353686 ps
CPU time 8.34 seconds
Started Apr 30 12:40:43 PM PDT 24
Finished Apr 30 12:40:52 PM PDT 24
Peak memory 211488 kb
Host smart-9829d5b5-e6af-4a40-b4b9-c4fc5a641157
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567775406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2567775406
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.846014308
Short name T28
Test name
Test status
Simulation time 37864058740 ps
CPU time 400.72 seconds
Started Apr 30 12:40:43 PM PDT 24
Finished Apr 30 12:47:24 PM PDT 24
Peak memory 236168 kb
Host smart-fda8a204-34a4-4353-a0c6-d026dad9f9c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846014308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.846014308
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3695374421
Short name T276
Test name
Test status
Simulation time 32722908075 ps
CPU time 64.34 seconds
Started Apr 30 12:40:44 PM PDT 24
Finished Apr 30 12:41:49 PM PDT 24
Peak memory 215212 kb
Host smart-6443e68c-911f-4c4c-991e-640dd7e6fe2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695374421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3695374421
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3404361249
Short name T287
Test name
Test status
Simulation time 1175528233 ps
CPU time 14.79 seconds
Started Apr 30 12:40:43 PM PDT 24
Finished Apr 30 12:40:58 PM PDT 24
Peak memory 211508 kb
Host smart-0a1da0c5-e61b-4251-a7bf-2d835899243e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3404361249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3404361249
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.782404213
Short name T297
Test name
Test status
Simulation time 24192828326 ps
CPU time 58.53 seconds
Started Apr 30 12:40:43 PM PDT 24
Finished Apr 30 12:41:42 PM PDT 24
Peak memory 216988 kb
Host smart-d3a18341-ac31-43a5-9ac8-76b653f5c1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782404213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.782404213
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.824683623
Short name T259
Test name
Test status
Simulation time 11775156328 ps
CPU time 91.35 seconds
Started Apr 30 12:40:45 PM PDT 24
Finished Apr 30 12:42:16 PM PDT 24
Peak memory 218400 kb
Host smart-eb393c70-bc5c-4495-a6ff-beadd726a0de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824683623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.824683623
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1811104637
Short name T204
Test name
Test status
Simulation time 8933165257 ps
CPU time 30.36 seconds
Started Apr 30 12:40:52 PM PDT 24
Finished Apr 30 12:41:23 PM PDT 24
Peak memory 212428 kb
Host smart-dad1ebd7-d174-430e-a564-f71836b63289
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811104637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1811104637
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1575458202
Short name T23
Test name
Test status
Simulation time 28380547040 ps
CPU time 319.96 seconds
Started Apr 30 12:40:52 PM PDT 24
Finished Apr 30 12:46:13 PM PDT 24
Peak memory 236264 kb
Host smart-e82e98ea-b26f-4084-8a5a-7bf1b2488f14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575458202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1575458202
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4018132221
Short name T324
Test name
Test status
Simulation time 1319697905 ps
CPU time 18.76 seconds
Started Apr 30 12:40:51 PM PDT 24
Finished Apr 30 12:41:11 PM PDT 24
Peak memory 214924 kb
Host smart-cd477864-48b0-472f-bd5b-b21a31969c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018132221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4018132221
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3955678706
Short name T127
Test name
Test status
Simulation time 3352952614 ps
CPU time 28.08 seconds
Started Apr 30 12:40:53 PM PDT 24
Finished Apr 30 12:41:22 PM PDT 24
Peak memory 212360 kb
Host smart-bd600125-23bc-4f8a-ad47-237f0746c611
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3955678706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3955678706
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3937564201
Short name T215
Test name
Test status
Simulation time 20021093137 ps
CPU time 67.24 seconds
Started Apr 30 12:40:42 PM PDT 24
Finished Apr 30 12:41:50 PM PDT 24
Peak memory 215792 kb
Host smart-642036f4-073a-4932-93b2-7e429603e853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937564201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3937564201
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.355244271
Short name T178
Test name
Test status
Simulation time 103024631021 ps
CPU time 125.97 seconds
Started Apr 30 12:40:42 PM PDT 24
Finished Apr 30 12:42:49 PM PDT 24
Peak memory 219580 kb
Host smart-b5d45ad5-3b4a-4b1b-81d4-06a1a86ce7bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355244271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.355244271
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.938846236
Short name T327
Test name
Test status
Simulation time 174554156 ps
CPU time 8.23 seconds
Started Apr 30 12:40:52 PM PDT 24
Finished Apr 30 12:41:01 PM PDT 24
Peak memory 211468 kb
Host smart-5bd961ce-5a84-474b-aa08-6e421e02e4cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938846236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.938846236
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1590906659
Short name T260
Test name
Test status
Simulation time 13631264529 ps
CPU time 230.2 seconds
Started Apr 30 12:40:53 PM PDT 24
Finished Apr 30 12:44:44 PM PDT 24
Peak memory 240144 kb
Host smart-887b0e02-388c-4abe-a11a-225679dc13ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590906659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1590906659
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.150135406
Short name T94
Test name
Test status
Simulation time 21187084263 ps
CPU time 50.63 seconds
Started Apr 30 12:40:51 PM PDT 24
Finished Apr 30 12:41:42 PM PDT 24
Peak memory 215172 kb
Host smart-414d9600-dafc-4b00-9e30-f4efc3143bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150135406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.150135406
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1273753292
Short name T342
Test name
Test status
Simulation time 3689853887 ps
CPU time 31.1 seconds
Started Apr 30 12:40:51 PM PDT 24
Finished Apr 30 12:41:24 PM PDT 24
Peak memory 211556 kb
Host smart-a4aa7406-4d46-44cc-ad80-4f9e16e3b142
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1273753292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1273753292
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2263854861
Short name T185
Test name
Test status
Simulation time 8041375829 ps
CPU time 74.43 seconds
Started Apr 30 12:40:51 PM PDT 24
Finished Apr 30 12:42:06 PM PDT 24
Peak memory 215588 kb
Host smart-6ca69acb-3a3e-48ac-8d15-b94a9aa9e3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263854861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2263854861
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1144147254
Short name T92
Test name
Test status
Simulation time 11866507775 ps
CPU time 73.4 seconds
Started Apr 30 12:40:55 PM PDT 24
Finished Apr 30 12:42:09 PM PDT 24
Peak memory 219564 kb
Host smart-f6de11ca-0461-487f-96fe-865833f767d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144147254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1144147254
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3203145600
Short name T335
Test name
Test status
Simulation time 2900821092 ps
CPU time 16.72 seconds
Started Apr 30 12:40:50 PM PDT 24
Finished Apr 30 12:41:07 PM PDT 24
Peak memory 211508 kb
Host smart-6af9ddbe-041f-49ff-9641-d75dd0017a38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203145600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3203145600
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.120547643
Short name T205
Test name
Test status
Simulation time 38496867054 ps
CPU time 428.99 seconds
Started Apr 30 12:40:53 PM PDT 24
Finished Apr 30 12:48:03 PM PDT 24
Peak memory 240876 kb
Host smart-dd50d529-9b70-4b2f-b131-12f7a953a33d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120547643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.120547643
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4034445907
Short name T200
Test name
Test status
Simulation time 2164483225 ps
CPU time 23.48 seconds
Started Apr 30 12:40:51 PM PDT 24
Finished Apr 30 12:41:16 PM PDT 24
Peak memory 212640 kb
Host smart-8b1bd5f2-bcb8-451c-986d-63bd801c676d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4034445907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4034445907
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.4256788456
Short name T175
Test name
Test status
Simulation time 4550267134 ps
CPU time 50.38 seconds
Started Apr 30 12:40:52 PM PDT 24
Finished Apr 30 12:41:43 PM PDT 24
Peak memory 217796 kb
Host smart-84b85465-db1c-45a8-8872-e8f5080623e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256788456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.4256788456
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2219869212
Short name T244
Test name
Test status
Simulation time 91286439140 ps
CPU time 237.69 seconds
Started Apr 30 12:40:51 PM PDT 24
Finished Apr 30 12:44:50 PM PDT 24
Peak memory 222020 kb
Host smart-ffadafed-5a02-4d4d-9367-f076e689e65c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219869212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2219869212
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1664396436
Short name T279
Test name
Test status
Simulation time 24449440189 ps
CPU time 16.82 seconds
Started Apr 30 12:40:53 PM PDT 24
Finished Apr 30 12:41:10 PM PDT 24
Peak memory 211596 kb
Host smart-3bd0dd2b-c8ed-457d-9738-a4ed26075bfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664396436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1664396436
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4228152934
Short name T86
Test name
Test status
Simulation time 4231947589 ps
CPU time 302.01 seconds
Started Apr 30 12:40:53 PM PDT 24
Finished Apr 30 12:45:56 PM PDT 24
Peak memory 225900 kb
Host smart-e6ea047a-60ab-48ab-ae3a-c997bd51d281
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228152934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.4228152934
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3523372988
Short name T271
Test name
Test status
Simulation time 9670445757 ps
CPU time 68.87 seconds
Started Apr 30 12:40:51 PM PDT 24
Finished Apr 30 12:42:00 PM PDT 24
Peak memory 215168 kb
Host smart-b57ab100-3008-41e3-9069-11fc5c9453ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523372988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3523372988
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1810300974
Short name T264
Test name
Test status
Simulation time 15675595393 ps
CPU time 33.54 seconds
Started Apr 30 12:40:54 PM PDT 24
Finished Apr 30 12:41:28 PM PDT 24
Peak memory 212032 kb
Host smart-9076811e-a67b-4ffd-bf90-db2b408c7e85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1810300974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1810300974
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1492282395
Short name T240
Test name
Test status
Simulation time 1727214417 ps
CPU time 32.83 seconds
Started Apr 30 12:40:50 PM PDT 24
Finished Apr 30 12:41:24 PM PDT 24
Peak memory 217072 kb
Host smart-e6377dd4-4534-4bb7-9bc5-d73bd22eac56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492282395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1492282395
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3897216907
Short name T343
Test name
Test status
Simulation time 15427458147 ps
CPU time 167.7 seconds
Started Apr 30 12:40:51 PM PDT 24
Finished Apr 30 12:43:39 PM PDT 24
Peak memory 221012 kb
Host smart-205d0e66-bfaa-4a06-8283-74119db60879
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897216907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3897216907
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1827569318
Short name T340
Test name
Test status
Simulation time 11622975433 ps
CPU time 25.69 seconds
Started Apr 30 12:39:49 PM PDT 24
Finished Apr 30 12:40:15 PM PDT 24
Peak memory 211576 kb
Host smart-b8dc3421-80d2-451e-8140-35891232c6f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827569318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1827569318
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2006529089
Short name T246
Test name
Test status
Simulation time 87346381550 ps
CPU time 898.55 seconds
Started Apr 30 12:39:44 PM PDT 24
Finished Apr 30 12:54:44 PM PDT 24
Peak memory 237284 kb
Host smart-e1ed7376-1ace-4fb4-9d75-8b63b2045ef3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006529089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2006529089
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3480063977
Short name T227
Test name
Test status
Simulation time 8371087872 ps
CPU time 64.41 seconds
Started Apr 30 12:39:51 PM PDT 24
Finished Apr 30 12:40:56 PM PDT 24
Peak memory 215544 kb
Host smart-28db931a-9eed-44fa-8594-2242c1a84353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480063977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3480063977
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2007084901
Short name T346
Test name
Test status
Simulation time 5871212335 ps
CPU time 26.53 seconds
Started Apr 30 12:39:43 PM PDT 24
Finished Apr 30 12:40:10 PM PDT 24
Peak memory 211608 kb
Host smart-21e8ff95-138c-44ab-a135-94fb7f713255
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2007084901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2007084901
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1222626326
Short name T31
Test name
Test status
Simulation time 6872102081 ps
CPU time 133.34 seconds
Started Apr 30 12:39:48 PM PDT 24
Finished Apr 30 12:42:01 PM PDT 24
Peak memory 237020 kb
Host smart-c4e48691-cab2-4ce5-be38-fd842955bcbb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222626326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1222626326
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.734561829
Short name T221
Test name
Test status
Simulation time 30886201749 ps
CPU time 72.02 seconds
Started Apr 30 12:39:46 PM PDT 24
Finished Apr 30 12:40:58 PM PDT 24
Peak memory 218036 kb
Host smart-6dbf2ddf-d706-431f-a0ef-c106472b55bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734561829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.734561829
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1128935250
Short name T120
Test name
Test status
Simulation time 10287148713 ps
CPU time 23.36 seconds
Started Apr 30 12:40:58 PM PDT 24
Finished Apr 30 12:41:22 PM PDT 24
Peak memory 212376 kb
Host smart-4a49919b-0301-49ca-9d29-b3fee7db07fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128935250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1128935250
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3087997723
Short name T238
Test name
Test status
Simulation time 131943139524 ps
CPU time 367.88 seconds
Started Apr 30 12:41:03 PM PDT 24
Finished Apr 30 12:47:11 PM PDT 24
Peak memory 238012 kb
Host smart-5b8ea098-3537-4ffd-8542-77a85dbff579
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087997723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3087997723
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.369961774
Short name T20
Test name
Test status
Simulation time 1321136921 ps
CPU time 19.05 seconds
Started Apr 30 12:40:59 PM PDT 24
Finished Apr 30 12:41:19 PM PDT 24
Peak memory 214896 kb
Host smart-cbc44db4-6c40-4524-90e4-87b8ea3cd161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369961774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.369961774
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.884858973
Short name T149
Test name
Test status
Simulation time 181957843 ps
CPU time 10.39 seconds
Started Apr 30 12:40:52 PM PDT 24
Finished Apr 30 12:41:03 PM PDT 24
Peak memory 212772 kb
Host smart-74882be6-e9ac-4e66-a0d3-812621765cae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=884858973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.884858973
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2601495571
Short name T350
Test name
Test status
Simulation time 30265933709 ps
CPU time 64.99 seconds
Started Apr 30 12:40:51 PM PDT 24
Finished Apr 30 12:41:57 PM PDT 24
Peak memory 218136 kb
Host smart-9b093826-9085-4565-b68a-94e80960451c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601495571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2601495571
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3204959839
Short name T76
Test name
Test status
Simulation time 836975021 ps
CPU time 43.25 seconds
Started Apr 30 12:40:53 PM PDT 24
Finished Apr 30 12:41:37 PM PDT 24
Peak memory 219516 kb
Host smart-34954210-721a-437b-a385-426218d82d86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204959839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3204959839
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.199084601
Short name T62
Test name
Test status
Simulation time 18957764770 ps
CPU time 28.34 seconds
Started Apr 30 12:40:58 PM PDT 24
Finished Apr 30 12:41:27 PM PDT 24
Peak memory 212424 kb
Host smart-29bb51c3-d3f1-4dd2-b670-94331f93439d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199084601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.199084601
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2994536554
Short name T140
Test name
Test status
Simulation time 256028602640 ps
CPU time 335.65 seconds
Started Apr 30 12:40:57 PM PDT 24
Finished Apr 30 12:46:33 PM PDT 24
Peak memory 228412 kb
Host smart-7d20f715-9836-4a58-bde6-c0514e1339a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994536554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2994536554
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.682632904
Short name T166
Test name
Test status
Simulation time 342540717 ps
CPU time 18.93 seconds
Started Apr 30 12:41:00 PM PDT 24
Finished Apr 30 12:41:20 PM PDT 24
Peak memory 214944 kb
Host smart-bec11497-83e3-4aaa-b999-5c8bb4ea0596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682632904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.682632904
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3265740913
Short name T170
Test name
Test status
Simulation time 11786580365 ps
CPU time 54.01 seconds
Started Apr 30 12:40:59 PM PDT 24
Finished Apr 30 12:41:54 PM PDT 24
Peak memory 217952 kb
Host smart-4a447793-cfd7-478d-8aa2-e44b4313c62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265740913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3265740913
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2244942351
Short name T189
Test name
Test status
Simulation time 37430348236 ps
CPU time 65.56 seconds
Started Apr 30 12:41:00 PM PDT 24
Finished Apr 30 12:42:06 PM PDT 24
Peak memory 217564 kb
Host smart-cffbc649-9897-4461-90f9-b9272edf9d06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244942351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2244942351
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3679420473
Short name T344
Test name
Test status
Simulation time 2513758753 ps
CPU time 16.1 seconds
Started Apr 30 12:41:02 PM PDT 24
Finished Apr 30 12:41:19 PM PDT 24
Peak memory 212052 kb
Host smart-cb4b5957-2726-49a5-8bef-6b8777b386bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679420473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3679420473
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1273547948
Short name T162
Test name
Test status
Simulation time 42379621708 ps
CPU time 496.26 seconds
Started Apr 30 12:41:03 PM PDT 24
Finished Apr 30 12:49:19 PM PDT 24
Peak memory 238004 kb
Host smart-97fb707b-5176-4fc8-a267-8c587cf50cea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273547948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1273547948
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.4234168113
Short name T203
Test name
Test status
Simulation time 3911674526 ps
CPU time 43.17 seconds
Started Apr 30 12:40:58 PM PDT 24
Finished Apr 30 12:41:41 PM PDT 24
Peak memory 213764 kb
Host smart-c4f1c668-6bc0-43fc-ae30-c7cbb793f1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234168113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.4234168113
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.552450422
Short name T133
Test name
Test status
Simulation time 524824655 ps
CPU time 13.55 seconds
Started Apr 30 12:41:03 PM PDT 24
Finished Apr 30 12:41:17 PM PDT 24
Peak memory 212512 kb
Host smart-bb0c2c50-1d0e-4f28-b1e3-4f6e95033bd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=552450422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.552450422
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1008753138
Short name T314
Test name
Test status
Simulation time 3486952281 ps
CPU time 26.66 seconds
Started Apr 30 12:41:00 PM PDT 24
Finished Apr 30 12:41:27 PM PDT 24
Peak memory 218448 kb
Host smart-889fe7f7-afd0-4db0-9f2c-abfd675f1550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008753138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1008753138
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3175795726
Short name T228
Test name
Test status
Simulation time 6248033464 ps
CPU time 62.85 seconds
Started Apr 30 12:41:03 PM PDT 24
Finished Apr 30 12:42:06 PM PDT 24
Peak memory 221692 kb
Host smart-fbd85cec-da31-4f7b-b435-83fd779fc9d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175795726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3175795726
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2744509156
Short name T50
Test name
Test status
Simulation time 70431688378 ps
CPU time 2624.27 seconds
Started Apr 30 12:41:00 PM PDT 24
Finished Apr 30 01:24:44 PM PDT 24
Peak memory 245296 kb
Host smart-7c516abc-228a-4fb0-b77b-4efc26f87a99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744509156 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2744509156
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1444907259
Short name T188
Test name
Test status
Simulation time 331743678 ps
CPU time 8.42 seconds
Started Apr 30 12:41:00 PM PDT 24
Finished Apr 30 12:41:09 PM PDT 24
Peak memory 211500 kb
Host smart-6c6fda39-b1e5-4dc5-acfc-6b9268256a9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444907259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1444907259
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3971597293
Short name T353
Test name
Test status
Simulation time 218460107941 ps
CPU time 494.74 seconds
Started Apr 30 12:41:00 PM PDT 24
Finished Apr 30 12:49:15 PM PDT 24
Peak memory 216864 kb
Host smart-a2a954f7-0974-4ef1-ad41-a65dcdf70df9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971597293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3971597293
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1122884862
Short name T187
Test name
Test status
Simulation time 12078026846 ps
CPU time 54.11 seconds
Started Apr 30 12:41:03 PM PDT 24
Finished Apr 30 12:41:57 PM PDT 24
Peak memory 215832 kb
Host smart-2b8f2d35-b317-41bf-b685-3fcc3390d0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122884862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1122884862
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1541712347
Short name T341
Test name
Test status
Simulation time 199623617 ps
CPU time 10.54 seconds
Started Apr 30 12:41:01 PM PDT 24
Finished Apr 30 12:41:12 PM PDT 24
Peak memory 212860 kb
Host smart-eeb02af9-408e-4b93-b6d7-e9a79769d723
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1541712347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1541712347
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2819375206
Short name T153
Test name
Test status
Simulation time 4401836257 ps
CPU time 32.39 seconds
Started Apr 30 12:40:58 PM PDT 24
Finished Apr 30 12:41:31 PM PDT 24
Peak memory 215336 kb
Host smart-7fa29284-de5f-4822-af77-5b50dfbbb4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819375206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2819375206
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.751977088
Short name T72
Test name
Test status
Simulation time 22646566864 ps
CPU time 212.98 seconds
Started Apr 30 12:41:00 PM PDT 24
Finished Apr 30 12:44:34 PM PDT 24
Peak memory 220628 kb
Host smart-fd4c043d-0460-4fe2-9e5f-b323e4ea6ce3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751977088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.751977088
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.715052312
Short name T172
Test name
Test status
Simulation time 1351938754 ps
CPU time 12.92 seconds
Started Apr 30 12:41:07 PM PDT 24
Finished Apr 30 12:41:20 PM PDT 24
Peak memory 211528 kb
Host smart-ed63404e-3953-4651-9eb8-e36ee8ae5a97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715052312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.715052312
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.4086920768
Short name T319
Test name
Test status
Simulation time 11405224523 ps
CPU time 52.15 seconds
Started Apr 30 12:41:08 PM PDT 24
Finished Apr 30 12:42:01 PM PDT 24
Peak memory 215388 kb
Host smart-560cf3d3-7a9b-4f6d-b4b0-d7d943c02e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086920768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.4086920768
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2729791845
Short name T138
Test name
Test status
Simulation time 870937710 ps
CPU time 10.49 seconds
Started Apr 30 12:41:07 PM PDT 24
Finished Apr 30 12:41:18 PM PDT 24
Peak memory 211700 kb
Host smart-65513188-c4f7-493e-a27e-b705f91ddae3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2729791845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2729791845
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1837869667
Short name T262
Test name
Test status
Simulation time 2484754597 ps
CPU time 26.52 seconds
Started Apr 30 12:41:00 PM PDT 24
Finished Apr 30 12:41:27 PM PDT 24
Peak memory 217624 kb
Host smart-e43dce33-c97d-43f0-887b-e5a48df20e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837869667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1837869667
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3354420076
Short name T212
Test name
Test status
Simulation time 23185509671 ps
CPU time 92.19 seconds
Started Apr 30 12:40:58 PM PDT 24
Finished Apr 30 12:42:31 PM PDT 24
Peak memory 220044 kb
Host smart-0a75d06b-b52d-4871-bcc9-8eacef6a3920
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354420076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3354420076
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1453693075
Short name T11
Test name
Test status
Simulation time 59634720561 ps
CPU time 2257.42 seconds
Started Apr 30 12:41:09 PM PDT 24
Finished Apr 30 01:18:48 PM PDT 24
Peak memory 244804 kb
Host smart-8e7b6538-490b-46bc-8702-897557542f69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453693075 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.1453693075
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1277903068
Short name T266
Test name
Test status
Simulation time 10155594375 ps
CPU time 23.77 seconds
Started Apr 30 12:41:06 PM PDT 24
Finished Apr 30 12:41:30 PM PDT 24
Peak memory 212360 kb
Host smart-25bc0e0c-731d-4cb3-978c-b9efb1a3e3bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277903068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1277903068
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.121973233
Short name T44
Test name
Test status
Simulation time 5761042098 ps
CPU time 345.38 seconds
Started Apr 30 12:41:10 PM PDT 24
Finished Apr 30 12:46:56 PM PDT 24
Peak memory 241068 kb
Host smart-a6d113fe-d007-4f3b-b8ba-0c91c8bf5c6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121973233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.121973233
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3945977554
Short name T209
Test name
Test status
Simulation time 2740776131 ps
CPU time 35.82 seconds
Started Apr 30 12:41:06 PM PDT 24
Finished Apr 30 12:41:42 PM PDT 24
Peak memory 214956 kb
Host smart-a58d948d-25ed-4e67-b553-96f77b859d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945977554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3945977554
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.497464174
Short name T169
Test name
Test status
Simulation time 361774573 ps
CPU time 10.4 seconds
Started Apr 30 12:41:09 PM PDT 24
Finished Apr 30 12:41:20 PM PDT 24
Peak memory 212500 kb
Host smart-bbccafa7-66f9-40d6-9498-2456494177e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=497464174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.497464174
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.208403603
Short name T265
Test name
Test status
Simulation time 20576234095 ps
CPU time 54.84 seconds
Started Apr 30 12:41:08 PM PDT 24
Finished Apr 30 12:42:04 PM PDT 24
Peak memory 217636 kb
Host smart-5776e6ad-9a1f-46dd-9adb-3406d9e14ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208403603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.208403603
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3606628407
Short name T122
Test name
Test status
Simulation time 8577241268 ps
CPU time 35.34 seconds
Started Apr 30 12:41:08 PM PDT 24
Finished Apr 30 12:41:44 PM PDT 24
Peak memory 213152 kb
Host smart-7e4922eb-1c96-4808-98fc-3919a7bcc8ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606628407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3606628407
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3394961259
Short name T213
Test name
Test status
Simulation time 14078861341 ps
CPU time 20.33 seconds
Started Apr 30 12:41:07 PM PDT 24
Finished Apr 30 12:41:28 PM PDT 24
Peak memory 212432 kb
Host smart-464ce1ee-a719-4dc8-a4e1-a50d337e4f89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394961259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3394961259
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3602576908
Short name T10
Test name
Test status
Simulation time 2525141092 ps
CPU time 181.89 seconds
Started Apr 30 12:41:07 PM PDT 24
Finished Apr 30 12:44:09 PM PDT 24
Peak memory 240036 kb
Host smart-13a9e28e-e516-4348-b467-043f4c715c24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602576908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3602576908
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1344019023
Short name T208
Test name
Test status
Simulation time 33612697005 ps
CPU time 68.19 seconds
Started Apr 30 12:41:07 PM PDT 24
Finished Apr 30 12:42:16 PM PDT 24
Peak memory 215256 kb
Host smart-9ea6a051-8c1a-47fe-b71b-b9b6c06ae35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344019023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1344019023
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3068400196
Short name T186
Test name
Test status
Simulation time 4280326554 ps
CPU time 33.02 seconds
Started Apr 30 12:41:08 PM PDT 24
Finished Apr 30 12:41:42 PM PDT 24
Peak memory 212472 kb
Host smart-47be6e26-2eb1-4268-93d4-7c61b035fd16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3068400196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3068400196
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1249232718
Short name T332
Test name
Test status
Simulation time 3905275210 ps
CPU time 44.12 seconds
Started Apr 30 12:41:09 PM PDT 24
Finished Apr 30 12:41:54 PM PDT 24
Peak memory 218056 kb
Host smart-5a97c2cb-2bfa-45de-816c-27f4f865868b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249232718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1249232718
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.4117162664
Short name T320
Test name
Test status
Simulation time 1547977856 ps
CPU time 43.85 seconds
Started Apr 30 12:41:09 PM PDT 24
Finished Apr 30 12:41:53 PM PDT 24
Peak memory 219508 kb
Host smart-cd7328d7-7201-43c8-9c06-5da5c704275f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117162664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.4117162664
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.213548281
Short name T338
Test name
Test status
Simulation time 143117377658 ps
CPU time 1473.17 seconds
Started Apr 30 12:41:06 PM PDT 24
Finished Apr 30 01:05:40 PM PDT 24
Peak memory 241772 kb
Host smart-29031c5e-1848-4bef-876f-a2f8aceded25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213548281 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.213548281
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1561058672
Short name T275
Test name
Test status
Simulation time 8184262902 ps
CPU time 20.54 seconds
Started Apr 30 12:41:15 PM PDT 24
Finished Apr 30 12:41:36 PM PDT 24
Peak memory 212512 kb
Host smart-fc5e45b7-6590-4562-b589-687a0e35ed6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561058672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1561058672
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.250367883
Short name T245
Test name
Test status
Simulation time 79786637211 ps
CPU time 721.5 seconds
Started Apr 30 12:41:08 PM PDT 24
Finished Apr 30 12:53:10 PM PDT 24
Peak memory 234064 kb
Host smart-5502eeb2-e03c-4b1b-b879-ee6a09afa4f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250367883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.250367883
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2561106793
Short name T36
Test name
Test status
Simulation time 1483345461 ps
CPU time 28.53 seconds
Started Apr 30 12:41:22 PM PDT 24
Finished Apr 30 12:41:52 PM PDT 24
Peak memory 214972 kb
Host smart-b02f0af9-1c02-4a47-9b32-ffa3fb341fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561106793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2561106793
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1402510970
Short name T280
Test name
Test status
Simulation time 407900171 ps
CPU time 10.66 seconds
Started Apr 30 12:41:07 PM PDT 24
Finished Apr 30 12:41:18 PM PDT 24
Peak memory 212684 kb
Host smart-bf19a48e-80e5-4227-84a5-a5e20cd6a1e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1402510970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1402510970
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2483038157
Short name T273
Test name
Test status
Simulation time 30219132380 ps
CPU time 65.98 seconds
Started Apr 30 12:41:08 PM PDT 24
Finished Apr 30 12:42:14 PM PDT 24
Peak memory 217912 kb
Host smart-453a020a-7189-47e5-9fbf-3a2456a34f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483038157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2483038157
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2926032406
Short name T288
Test name
Test status
Simulation time 23813282039 ps
CPU time 93.09 seconds
Started Apr 30 12:41:07 PM PDT 24
Finished Apr 30 12:42:41 PM PDT 24
Peak memory 220472 kb
Host smart-beda6f43-f7d2-47ab-868f-b7353ecd1ba1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926032406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2926032406
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.4267968386
Short name T296
Test name
Test status
Simulation time 1768027195 ps
CPU time 19.1 seconds
Started Apr 30 12:41:15 PM PDT 24
Finished Apr 30 12:41:35 PM PDT 24
Peak memory 211456 kb
Host smart-b5088a65-6bef-4e96-a8ff-1cd5ab9891e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267968386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4267968386
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.539570641
Short name T195
Test name
Test status
Simulation time 71115316848 ps
CPU time 417.85 seconds
Started Apr 30 12:41:16 PM PDT 24
Finished Apr 30 12:48:14 PM PDT 24
Peak memory 229200 kb
Host smart-b9ee22d9-8198-461d-8385-c265b4c02edd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539570641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.539570641
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3615371953
Short name T202
Test name
Test status
Simulation time 34855117920 ps
CPU time 65.74 seconds
Started Apr 30 12:41:17 PM PDT 24
Finished Apr 30 12:42:23 PM PDT 24
Peak memory 214256 kb
Host smart-22f019a2-400c-4fb7-b6ed-171132202375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615371953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3615371953
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1336323262
Short name T174
Test name
Test status
Simulation time 349057218 ps
CPU time 10.32 seconds
Started Apr 30 12:41:17 PM PDT 24
Finished Apr 30 12:41:27 PM PDT 24
Peak memory 212784 kb
Host smart-432e8e1e-67ad-458f-a760-a4f4470f7c65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1336323262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1336323262
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2999126820
Short name T295
Test name
Test status
Simulation time 19805199499 ps
CPU time 52.98 seconds
Started Apr 30 12:41:15 PM PDT 24
Finished Apr 30 12:42:08 PM PDT 24
Peak memory 217976 kb
Host smart-8aa33bc2-064c-4e52-b52b-e69f518ec184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999126820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2999126820
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2583320307
Short name T267
Test name
Test status
Simulation time 4179760613 ps
CPU time 50.22 seconds
Started Apr 30 12:41:17 PM PDT 24
Finished Apr 30 12:42:07 PM PDT 24
Peak memory 219564 kb
Host smart-648043d3-ba7e-4c12-8b8e-af775db22d5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583320307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2583320307
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.169157791
Short name T294
Test name
Test status
Simulation time 3351303241 ps
CPU time 28.82 seconds
Started Apr 30 12:41:15 PM PDT 24
Finished Apr 30 12:41:44 PM PDT 24
Peak memory 212172 kb
Host smart-3ad0ed7e-7df2-4fae-884d-fccc644cf44d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169157791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.169157791
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2955588619
Short name T310
Test name
Test status
Simulation time 47571729978 ps
CPU time 492.34 seconds
Started Apr 30 12:41:15 PM PDT 24
Finished Apr 30 12:49:28 PM PDT 24
Peak memory 240144 kb
Host smart-1e8439b2-4840-4035-86b2-6f78c05d0e7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955588619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2955588619
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1343675617
Short name T261
Test name
Test status
Simulation time 9946345545 ps
CPU time 52.97 seconds
Started Apr 30 12:41:21 PM PDT 24
Finished Apr 30 12:42:14 PM PDT 24
Peak memory 214144 kb
Host smart-d6ce2098-d36c-4a55-b2fe-7a6e9f64df5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343675617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1343675617
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2336705609
Short name T255
Test name
Test status
Simulation time 2325879735 ps
CPU time 22.73 seconds
Started Apr 30 12:41:21 PM PDT 24
Finished Apr 30 12:41:45 PM PDT 24
Peak memory 211556 kb
Host smart-e2ff03dd-3fef-478e-a7d6-73cbc13b8132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2336705609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2336705609
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1775099721
Short name T87
Test name
Test status
Simulation time 7185131087 ps
CPU time 67.49 seconds
Started Apr 30 12:41:22 PM PDT 24
Finished Apr 30 12:42:30 PM PDT 24
Peak memory 218516 kb
Host smart-e09b5cac-82d0-464c-87a2-8ed476d1dc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775099721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1775099721
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2811676416
Short name T217
Test name
Test status
Simulation time 38672720739 ps
CPU time 177.8 seconds
Started Apr 30 12:41:15 PM PDT 24
Finished Apr 30 12:44:13 PM PDT 24
Peak memory 222952 kb
Host smart-90a14708-667f-4276-b607-7ec84bf3de55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811676416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2811676416
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.62673985
Short name T322
Test name
Test status
Simulation time 10997872633 ps
CPU time 24.4 seconds
Started Apr 30 12:39:47 PM PDT 24
Finished Apr 30 12:40:12 PM PDT 24
Peak memory 211492 kb
Host smart-9af1f22b-b236-4678-8f8a-796196e0672d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62673985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.62673985
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2051882738
Short name T39
Test name
Test status
Simulation time 146575811184 ps
CPU time 715.99 seconds
Started Apr 30 12:39:46 PM PDT 24
Finished Apr 30 12:51:42 PM PDT 24
Peak memory 234060 kb
Host smart-7d1ed870-1478-43a4-9dbe-d54beec28745
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051882738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2051882738
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1695235723
Short name T220
Test name
Test status
Simulation time 1011760270 ps
CPU time 22.12 seconds
Started Apr 30 12:39:44 PM PDT 24
Finished Apr 30 12:40:07 PM PDT 24
Peak memory 213240 kb
Host smart-66f52f99-7cf7-48df-be71-551452aa16be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695235723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1695235723
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3392628208
Short name T263
Test name
Test status
Simulation time 2785237726 ps
CPU time 19.01 seconds
Started Apr 30 12:39:44 PM PDT 24
Finished Apr 30 12:40:03 PM PDT 24
Peak memory 211792 kb
Host smart-f9d57adf-4438-4ecd-9356-561621fcee39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3392628208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3392628208
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.298095857
Short name T123
Test name
Test status
Simulation time 77668878253 ps
CPU time 70.49 seconds
Started Apr 30 12:39:45 PM PDT 24
Finished Apr 30 12:40:56 PM PDT 24
Peak memory 217892 kb
Host smart-d04d2b33-e324-48c7-a0fd-a807aebfe16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298095857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.298095857
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2902011218
Short name T150
Test name
Test status
Simulation time 8272261513 ps
CPU time 36.07 seconds
Started Apr 30 12:39:45 PM PDT 24
Finished Apr 30 12:40:22 PM PDT 24
Peak memory 214520 kb
Host smart-41e058f3-d699-403d-ac53-f17594d6bc30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902011218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2902011218
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2403999925
Short name T241
Test name
Test status
Simulation time 916034586 ps
CPU time 9.9 seconds
Started Apr 30 12:39:50 PM PDT 24
Finished Apr 30 12:40:00 PM PDT 24
Peak memory 211532 kb
Host smart-b5ef4ee0-671e-4293-9d46-bcbadea3346d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403999925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2403999925
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1584287415
Short name T196
Test name
Test status
Simulation time 10491375099 ps
CPU time 259.84 seconds
Started Apr 30 12:39:49 PM PDT 24
Finished Apr 30 12:44:09 PM PDT 24
Peak memory 238252 kb
Host smart-521dd7de-2a70-437e-8fbd-1a734ac66f3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584287415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1584287415
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.813973401
Short name T248
Test name
Test status
Simulation time 1993551803 ps
CPU time 32.17 seconds
Started Apr 30 12:39:50 PM PDT 24
Finished Apr 30 12:40:23 PM PDT 24
Peak memory 214960 kb
Host smart-9ae3eed1-4dbd-4118-b527-a470f6a1818c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813973401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.813973401
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3462175082
Short name T167
Test name
Test status
Simulation time 2232849129 ps
CPU time 23.47 seconds
Started Apr 30 12:39:46 PM PDT 24
Finished Apr 30 12:40:10 PM PDT 24
Peak memory 211468 kb
Host smart-342f1d86-9844-44ab-a1e2-2c9962633008
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3462175082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3462175082
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3461415938
Short name T156
Test name
Test status
Simulation time 1424885339 ps
CPU time 20.35 seconds
Started Apr 30 12:39:50 PM PDT 24
Finished Apr 30 12:40:11 PM PDT 24
Peak memory 216656 kb
Host smart-09995657-a919-4d56-8ebd-9c81efc9a58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461415938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3461415938
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3051258939
Short name T152
Test name
Test status
Simulation time 22652657142 ps
CPU time 128.71 seconds
Started Apr 30 12:39:45 PM PDT 24
Finished Apr 30 12:41:54 PM PDT 24
Peak memory 221372 kb
Host smart-86e25aa9-2805-4088-878e-b3577ba5ce86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051258939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3051258939
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3774915743
Short name T51
Test name
Test status
Simulation time 58817043278 ps
CPU time 2152.08 seconds
Started Apr 30 12:39:51 PM PDT 24
Finished Apr 30 01:15:44 PM PDT 24
Peak memory 244300 kb
Host smart-dd70591b-35fd-435e-8abe-906b403a404c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774915743 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.3774915743
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1711043498
Short name T272
Test name
Test status
Simulation time 18353057665 ps
CPU time 30.2 seconds
Started Apr 30 12:39:48 PM PDT 24
Finished Apr 30 12:40:18 PM PDT 24
Peak memory 212424 kb
Host smart-e14f6d2f-abca-44ea-9f3b-a605dfbf2ce7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711043498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1711043498
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3765446655
Short name T225
Test name
Test status
Simulation time 58242621926 ps
CPU time 334.43 seconds
Started Apr 30 12:39:45 PM PDT 24
Finished Apr 30 12:45:20 PM PDT 24
Peak memory 237056 kb
Host smart-e4ca7e89-ca6d-4c0a-87e9-1dd7daa38968
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765446655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3765446655
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2779844571
Short name T323
Test name
Test status
Simulation time 1208250372 ps
CPU time 27.23 seconds
Started Apr 30 12:39:49 PM PDT 24
Finished Apr 30 12:40:17 PM PDT 24
Peak memory 214872 kb
Host smart-4bf756a9-4f27-4399-9bd0-d091a3bad1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779844571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2779844571
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2644693675
Short name T40
Test name
Test status
Simulation time 181229586 ps
CPU time 10.95 seconds
Started Apr 30 12:39:45 PM PDT 24
Finished Apr 30 12:39:57 PM PDT 24
Peak memory 212564 kb
Host smart-998f58f8-6e19-4e70-b9d3-5a4efa396bfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644693675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2644693675
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.662397388
Short name T285
Test name
Test status
Simulation time 1802225164 ps
CPU time 26.6 seconds
Started Apr 30 12:39:46 PM PDT 24
Finished Apr 30 12:40:13 PM PDT 24
Peak memory 217032 kb
Host smart-93bda28e-ec02-40bc-b7fb-d8d9f119c325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662397388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.662397388
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.190896092
Short name T214
Test name
Test status
Simulation time 27797680398 ps
CPU time 59.44 seconds
Started Apr 30 12:39:44 PM PDT 24
Finished Apr 30 12:40:44 PM PDT 24
Peak memory 219592 kb
Host smart-b804f389-13b6-45fd-ad83-460b4fa739cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190896092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.190896092
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3923110813
Short name T124
Test name
Test status
Simulation time 1439928565 ps
CPU time 17.97 seconds
Started Apr 30 12:39:45 PM PDT 24
Finished Apr 30 12:40:04 PM PDT 24
Peak memory 212120 kb
Host smart-fa5fde9b-dce5-4409-bc8b-a0e8554c1ef6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923110813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3923110813
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2803296365
Short name T27
Test name
Test status
Simulation time 41602297151 ps
CPU time 406.26 seconds
Started Apr 30 12:39:47 PM PDT 24
Finished Apr 30 12:46:34 PM PDT 24
Peak memory 238064 kb
Host smart-c1e82b91-2bca-44c6-8a54-d8f34495184f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803296365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2803296365
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2044587002
Short name T117
Test name
Test status
Simulation time 16144284685 ps
CPU time 64.46 seconds
Started Apr 30 12:39:45 PM PDT 24
Finished Apr 30 12:40:50 PM PDT 24
Peak memory 215300 kb
Host smart-ccfad517-821e-4abb-a198-b8648ffc6b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044587002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2044587002
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3934916890
Short name T103
Test name
Test status
Simulation time 10576617637 ps
CPU time 25.03 seconds
Started Apr 30 12:39:50 PM PDT 24
Finished Apr 30 12:40:16 PM PDT 24
Peak memory 211636 kb
Host smart-250607f0-4d12-468a-8c0e-a9ed246b7498
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3934916890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3934916890
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1175885404
Short name T73
Test name
Test status
Simulation time 3028761580 ps
CPU time 40.01 seconds
Started Apr 30 12:39:51 PM PDT 24
Finished Apr 30 12:40:31 PM PDT 24
Peak memory 216112 kb
Host smart-831f849c-b652-4fc3-b5ed-6257a9d5fdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175885404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1175885404
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.46837633
Short name T347
Test name
Test status
Simulation time 770707655 ps
CPU time 26.7 seconds
Started Apr 30 12:39:51 PM PDT 24
Finished Apr 30 12:40:19 PM PDT 24
Peak memory 215640 kb
Host smart-ea9e7bde-9a43-445b-b805-88f36f36d659
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46837633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.rom_ctrl_stress_all.46837633
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.323850954
Short name T14
Test name
Test status
Simulation time 11419002981 ps
CPU time 474.52 seconds
Started Apr 30 12:39:48 PM PDT 24
Finished Apr 30 12:47:43 PM PDT 24
Peak memory 225068 kb
Host smart-3874cc96-03d9-4250-aed8-f8313a8ef201
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323850954 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.323850954
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1816258896
Short name T345
Test name
Test status
Simulation time 1302410833 ps
CPU time 14.31 seconds
Started Apr 30 12:39:57 PM PDT 24
Finished Apr 30 12:40:12 PM PDT 24
Peak memory 211528 kb
Host smart-4aa6fd6f-5c3c-4c61-a4a4-ece061ea4099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816258896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1816258896
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1428926734
Short name T317
Test name
Test status
Simulation time 9796775409 ps
CPU time 301.09 seconds
Started Apr 30 12:40:53 PM PDT 24
Finished Apr 30 12:45:55 PM PDT 24
Peak memory 240168 kb
Host smart-2a5d9520-0699-4359-b3f6-fdf4a7fbe618
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428926734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1428926734
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3010880548
Short name T119
Test name
Test status
Simulation time 6553476885 ps
CPU time 39.02 seconds
Started Apr 30 12:40:53 PM PDT 24
Finished Apr 30 12:41:33 PM PDT 24
Peak memory 214888 kb
Host smart-69881c55-5a86-4ef3-be67-34e8c6f7aa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010880548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3010880548
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2875152804
Short name T226
Test name
Test status
Simulation time 4666773237 ps
CPU time 22.54 seconds
Started Apr 30 12:39:46 PM PDT 24
Finished Apr 30 12:40:09 PM PDT 24
Peak memory 213036 kb
Host smart-a5b751ac-402a-47cb-a1cf-b0a8a0a35bf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2875152804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2875152804
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2909315333
Short name T159
Test name
Test status
Simulation time 12369904730 ps
CPU time 41.37 seconds
Started Apr 30 12:39:46 PM PDT 24
Finished Apr 30 12:40:27 PM PDT 24
Peak memory 218428 kb
Host smart-939cc13e-25ce-4db9-a901-b9a3e8ca9ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909315333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2909315333
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1590959094
Short name T308
Test name
Test status
Simulation time 3806708621 ps
CPU time 66.55 seconds
Started Apr 30 12:39:47 PM PDT 24
Finished Apr 30 12:40:54 PM PDT 24
Peak memory 219548 kb
Host smart-bb87e343-2092-4d0e-b03d-09b4e5c1338d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590959094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1590959094
Directory /workspace/9.rom_ctrl_stress_all/latest
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