Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.48 96.97 92.87 97.88 100.00 98.37 97.88 98.37


Total test records in report: 453
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T53 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3187765287 May 02 12:54:17 PM PDT 24 May 02 01:09:18 PM PDT 24 91646217465 ps
T305 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3927137875 May 02 12:54:38 PM PDT 24 May 02 12:55:01 PM PDT 24 6182185408 ps
T306 /workspace/coverage/default/24.rom_ctrl_stress_all.350710777 May 02 12:54:41 PM PDT 24 May 02 12:55:28 PM PDT 24 16486705454 ps
T307 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3408807301 May 02 12:55:08 PM PDT 24 May 02 01:05:01 PM PDT 24 43534733478 ps
T308 /workspace/coverage/default/40.rom_ctrl_alert_test.2024962254 May 02 12:55:09 PM PDT 24 May 02 12:55:43 PM PDT 24 7839671341 ps
T309 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.537625347 May 02 12:55:00 PM PDT 24 May 02 01:03:14 PM PDT 24 721810764271 ps
T310 /workspace/coverage/default/18.rom_ctrl_alert_test.334212769 May 02 12:54:29 PM PDT 24 May 02 12:54:51 PM PDT 24 32913067520 ps
T311 /workspace/coverage/default/44.rom_ctrl_stress_all.1932468400 May 02 12:55:16 PM PDT 24 May 02 12:56:11 PM PDT 24 962174015 ps
T312 /workspace/coverage/default/26.rom_ctrl_smoke.138017485 May 02 12:54:40 PM PDT 24 May 02 12:55:58 PM PDT 24 69973685496 ps
T313 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1746579761 May 02 12:54:11 PM PDT 24 May 02 12:54:51 PM PDT 24 43492428874 ps
T314 /workspace/coverage/default/15.rom_ctrl_stress_all.67749521 May 02 12:54:16 PM PDT 24 May 02 12:54:55 PM PDT 24 1945493099 ps
T315 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1037162771 May 02 12:54:10 PM PDT 24 May 02 12:54:35 PM PDT 24 1954668363 ps
T316 /workspace/coverage/default/8.rom_ctrl_alert_test.3003786102 May 02 12:54:04 PM PDT 24 May 02 12:54:40 PM PDT 24 7527692601 ps
T317 /workspace/coverage/default/4.rom_ctrl_alert_test.3606439506 May 02 12:53:54 PM PDT 24 May 02 12:54:30 PM PDT 24 3828025097 ps
T318 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2611595117 May 02 12:54:56 PM PDT 24 May 02 12:55:33 PM PDT 24 17490914041 ps
T319 /workspace/coverage/default/11.rom_ctrl_smoke.3973135712 May 02 12:54:12 PM PDT 24 May 02 12:55:07 PM PDT 24 15856600607 ps
T320 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.831842600 May 02 12:55:08 PM PDT 24 May 02 01:05:14 PM PDT 24 269394353145 ps
T321 /workspace/coverage/default/34.rom_ctrl_alert_test.1776887915 May 02 12:54:50 PM PDT 24 May 02 12:55:02 PM PDT 24 339147795 ps
T322 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1331249165 May 02 12:54:37 PM PDT 24 May 02 01:00:41 PM PDT 24 32339737878 ps
T323 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2089396635 May 02 12:55:15 PM PDT 24 May 02 01:05:19 PM PDT 24 97376381144 ps
T324 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2501049101 May 02 12:54:41 PM PDT 24 May 02 12:54:59 PM PDT 24 1505353461 ps
T325 /workspace/coverage/default/17.rom_ctrl_alert_test.1877787377 May 02 12:54:28 PM PDT 24 May 02 12:54:40 PM PDT 24 167622473 ps
T326 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2345765420 May 02 12:55:15 PM PDT 24 May 02 12:56:17 PM PDT 24 24674449212 ps
T327 /workspace/coverage/default/7.rom_ctrl_alert_test.2931787845 May 02 12:54:04 PM PDT 24 May 02 12:54:29 PM PDT 24 8172009810 ps
T328 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2186728656 May 02 12:54:27 PM PDT 24 May 02 01:01:38 PM PDT 24 48864615511 ps
T329 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.795620272 May 02 12:54:11 PM PDT 24 May 02 12:58:02 PM PDT 24 85442161455 ps
T330 /workspace/coverage/default/42.rom_ctrl_stress_all.3655674386 May 02 12:55:16 PM PDT 24 May 02 12:56:14 PM PDT 24 5327700115 ps
T331 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3987638110 May 02 12:55:00 PM PDT 24 May 02 12:55:31 PM PDT 24 8962652618 ps
T332 /workspace/coverage/default/20.rom_ctrl_smoke.2865800012 May 02 12:54:38 PM PDT 24 May 02 12:55:56 PM PDT 24 16668695981 ps
T333 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.4104670606 May 02 12:55:00 PM PDT 24 May 02 12:55:37 PM PDT 24 13817615646 ps
T334 /workspace/coverage/default/23.rom_ctrl_smoke.3616267425 May 02 12:54:37 PM PDT 24 May 02 12:55:39 PM PDT 24 6730410338 ps
T335 /workspace/coverage/default/42.rom_ctrl_smoke.3353312901 May 02 12:55:08 PM PDT 24 May 02 12:55:58 PM PDT 24 19256584964 ps
T336 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2287797602 May 02 12:54:04 PM PDT 24 May 02 12:57:47 PM PDT 24 5304688317 ps
T337 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4115076106 May 02 12:55:20 PM PDT 24 May 02 01:01:09 PM PDT 24 4798061126 ps
T338 /workspace/coverage/default/49.rom_ctrl_stress_all.1216738676 May 02 12:55:31 PM PDT 24 May 02 12:56:14 PM PDT 24 20886022924 ps
T339 /workspace/coverage/default/19.rom_ctrl_smoke.1094127154 May 02 12:54:28 PM PDT 24 May 02 12:55:13 PM PDT 24 2787075354 ps
T340 /workspace/coverage/default/48.rom_ctrl_smoke.1400045188 May 02 12:55:28 PM PDT 24 May 02 12:55:52 PM PDT 24 719203840 ps
T341 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.715008308 May 02 12:54:36 PM PDT 24 May 02 01:06:18 PM PDT 24 68574596258 ps
T342 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2805365249 May 02 12:54:16 PM PDT 24 May 02 01:00:59 PM PDT 24 15921921614 ps
T343 /workspace/coverage/default/48.rom_ctrl_stress_all.1176323549 May 02 12:55:27 PM PDT 24 May 02 12:56:13 PM PDT 24 8793871763 ps
T344 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.899289206 May 02 12:55:20 PM PDT 24 May 02 12:55:50 PM PDT 24 9572376390 ps
T345 /workspace/coverage/default/24.rom_ctrl_alert_test.3792193936 May 02 12:54:39 PM PDT 24 May 02 12:55:04 PM PDT 24 14095577834 ps
T346 /workspace/coverage/default/31.rom_ctrl_alert_test.1152913879 May 02 12:54:57 PM PDT 24 May 02 12:55:27 PM PDT 24 3277778086 ps
T347 /workspace/coverage/default/7.rom_ctrl_smoke.204089402 May 02 12:54:06 PM PDT 24 May 02 12:55:12 PM PDT 24 44595450630 ps
T348 /workspace/coverage/default/1.rom_ctrl_alert_test.1364152889 May 02 12:53:56 PM PDT 24 May 02 12:54:08 PM PDT 24 394527287 ps
T349 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.413543049 May 02 12:53:51 PM PDT 24 May 02 01:03:47 PM PDT 24 121576299883 ps
T350 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4238970238 May 02 12:55:21 PM PDT 24 May 02 12:56:01 PM PDT 24 2567277602 ps
T351 /workspace/coverage/default/30.rom_ctrl_alert_test.2454606848 May 02 12:54:43 PM PDT 24 May 02 12:55:10 PM PDT 24 5166018068 ps
T352 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.875989822 May 02 12:54:29 PM PDT 24 May 02 12:54:42 PM PDT 24 186238716 ps
T353 /workspace/coverage/default/21.rom_ctrl_alert_test.460806537 May 02 12:54:36 PM PDT 24 May 02 12:55:03 PM PDT 24 2569869681 ps
T354 /workspace/coverage/default/32.rom_ctrl_alert_test.4234737426 May 02 12:54:52 PM PDT 24 May 02 12:55:20 PM PDT 24 5907682829 ps
T355 /workspace/coverage/default/13.rom_ctrl_stress_all.1675143984 May 02 12:54:11 PM PDT 24 May 02 12:56:23 PM PDT 24 23705531560 ps
T54 /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3364857752 May 02 12:54:12 PM PDT 24 May 02 01:28:38 PM PDT 24 84946497907 ps
T356 /workspace/coverage/default/7.rom_ctrl_stress_all.133596727 May 02 12:54:04 PM PDT 24 May 02 12:56:01 PM PDT 24 51010860109 ps
T357 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1330465083 May 02 12:55:21 PM PDT 24 May 02 12:55:57 PM PDT 24 22489937886 ps
T358 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4207899215 May 02 12:54:36 PM PDT 24 May 02 01:02:33 PM PDT 24 49352401670 ps
T359 /workspace/coverage/default/35.rom_ctrl_stress_all.1279102602 May 02 12:54:57 PM PDT 24 May 02 12:56:22 PM PDT 24 2920643228 ps
T360 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1993181652 May 02 12:54:05 PM PDT 24 May 02 12:54:46 PM PDT 24 2792975087 ps
T55 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4064815205 May 02 12:53:34 PM PDT 24 May 02 12:54:07 PM PDT 24 3519042448 ps
T56 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1120746191 May 02 12:53:46 PM PDT 24 May 02 12:55:09 PM PDT 24 1631428516 ps
T57 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3840388790 May 02 12:53:46 PM PDT 24 May 02 12:54:02 PM PDT 24 2141424868 ps
T58 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.479151759 May 02 12:53:36 PM PDT 24 May 02 12:55:17 PM PDT 24 3411585832 ps
T81 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1645075513 May 02 12:53:37 PM PDT 24 May 02 12:55:32 PM PDT 24 9250948118 ps
T82 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1769231233 May 02 12:53:34 PM PDT 24 May 02 12:53:53 PM PDT 24 180793204 ps
T59 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1337872940 May 02 12:53:44 PM PDT 24 May 02 12:56:32 PM PDT 24 11342010613 ps
T115 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1231154347 May 02 12:53:50 PM PDT 24 May 02 12:56:56 PM PDT 24 22083343195 ps
T109 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3285980752 May 02 12:53:21 PM PDT 24 May 02 12:53:59 PM PDT 24 4505523195 ps
T361 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4216083726 May 02 12:53:22 PM PDT 24 May 02 12:53:54 PM PDT 24 3273373872 ps
T83 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2566846949 May 02 12:53:43 PM PDT 24 May 02 12:55:04 PM PDT 24 28759941289 ps
T121 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.67955434 May 02 12:53:54 PM PDT 24 May 02 12:55:35 PM PDT 24 6387034371 ps
T77 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2862381480 May 02 12:53:22 PM PDT 24 May 02 12:54:52 PM PDT 24 910419210 ps
T78 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1734779063 May 02 12:53:38 PM PDT 24 May 02 12:53:56 PM PDT 24 688104513 ps
T116 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3789906928 May 02 12:53:45 PM PDT 24 May 02 12:53:57 PM PDT 24 1374459438 ps
T117 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3496566778 May 02 12:53:28 PM PDT 24 May 02 12:53:55 PM PDT 24 2820224233 ps
T362 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.123340791 May 02 12:53:24 PM PDT 24 May 02 12:53:54 PM PDT 24 9457707969 ps
T125 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4280826481 May 02 12:53:55 PM PDT 24 May 02 12:55:36 PM PDT 24 4790417562 ps
T118 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1830901059 May 02 12:53:29 PM PDT 24 May 02 12:53:57 PM PDT 24 5770919145 ps
T84 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3518473749 May 02 12:53:44 PM PDT 24 May 02 12:56:54 PM PDT 24 98253260232 ps
T119 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1491856152 May 02 12:53:29 PM PDT 24 May 02 12:54:05 PM PDT 24 8167525459 ps
T85 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1418043391 May 02 12:53:36 PM PDT 24 May 02 12:54:13 PM PDT 24 3292846509 ps
T86 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2192785505 May 02 12:53:52 PM PDT 24 May 02 12:54:26 PM PDT 24 3684229647 ps
T79 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3162099383 May 02 12:53:38 PM PDT 24 May 02 12:56:33 PM PDT 24 19767869361 ps
T87 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2671602532 May 02 12:53:25 PM PDT 24 May 02 12:54:07 PM PDT 24 1412489132 ps
T110 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3905660919 May 02 12:53:43 PM PDT 24 May 02 12:56:53 PM PDT 24 22439448191 ps
T80 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2100639154 May 02 12:53:50 PM PDT 24 May 02 12:54:10 PM PDT 24 1916804708 ps
T363 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.117008588 May 02 12:53:49 PM PDT 24 May 02 12:54:06 PM PDT 24 1345335194 ps
T122 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1949382201 May 02 12:53:44 PM PDT 24 May 02 12:56:21 PM PDT 24 297494758 ps
T364 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1840397121 May 02 12:53:19 PM PDT 24 May 02 12:53:44 PM PDT 24 5407185332 ps
T88 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.887815562 May 02 12:53:22 PM PDT 24 May 02 12:53:50 PM PDT 24 7914148201 ps
T89 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2389678373 May 02 12:53:38 PM PDT 24 May 02 12:54:13 PM PDT 24 3123539872 ps
T90 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2325237899 May 02 12:53:37 PM PDT 24 May 02 12:56:49 PM PDT 24 23882637978 ps
T128 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2588417648 May 02 12:53:23 PM PDT 24 May 02 12:54:52 PM PDT 24 1369656843 ps
T120 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2898353607 May 02 12:53:49 PM PDT 24 May 02 12:56:24 PM PDT 24 4134171708 ps
T365 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2575250364 May 02 12:53:28 PM PDT 24 May 02 12:53:50 PM PDT 24 6855222502 ps
T111 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1576969982 May 02 12:53:51 PM PDT 24 May 02 12:54:07 PM PDT 24 172684594 ps
T366 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4061820923 May 02 12:53:27 PM PDT 24 May 02 12:53:50 PM PDT 24 1320402541 ps
T112 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3196552917 May 02 12:53:37 PM PDT 24 May 02 12:54:05 PM PDT 24 2545380245 ps
T367 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2050584498 May 02 12:53:27 PM PDT 24 May 02 12:53:59 PM PDT 24 14642606420 ps
T368 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3826936301 May 02 12:53:43 PM PDT 24 May 02 12:54:16 PM PDT 24 15064133073 ps
T96 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.972741629 May 02 12:53:55 PM PDT 24 May 02 12:55:47 PM PDT 24 11489423247 ps
T369 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.517378492 May 02 12:53:37 PM PDT 24 May 02 12:54:09 PM PDT 24 2542025036 ps
T370 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3158323950 May 02 12:53:29 PM PDT 24 May 02 12:54:03 PM PDT 24 14677781656 ps
T371 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.989462828 May 02 12:53:43 PM PDT 24 May 02 12:56:35 PM PDT 24 26880132281 ps
T97 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3379105335 May 02 12:53:49 PM PDT 24 May 02 12:55:48 PM PDT 24 58825327231 ps
T372 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.802500180 May 02 12:53:37 PM PDT 24 May 02 12:55:14 PM PDT 24 9824679670 ps
T373 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1006310856 May 02 12:53:37 PM PDT 24 May 02 12:56:35 PM PDT 24 13236454394 ps
T113 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3604117547 May 02 12:53:44 PM PDT 24 May 02 12:54:18 PM PDT 24 19932999711 ps
T114 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3963141184 May 02 12:53:22 PM PDT 24 May 02 12:53:55 PM PDT 24 3860934780 ps
T374 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3388422467 May 02 12:53:46 PM PDT 24 May 02 12:54:28 PM PDT 24 4440141221 ps
T375 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2185633634 May 02 12:53:30 PM PDT 24 May 02 12:53:54 PM PDT 24 2165287865 ps
T376 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2528990892 May 02 12:53:45 PM PDT 24 May 02 12:53:59 PM PDT 24 688045024 ps
T377 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3956416901 May 02 12:53:21 PM PDT 24 May 02 12:53:38 PM PDT 24 1029970122 ps
T378 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1979670767 May 02 12:53:44 PM PDT 24 May 02 12:54:03 PM PDT 24 1318650935 ps
T379 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2808836714 May 02 12:53:44 PM PDT 24 May 02 12:54:09 PM PDT 24 9877778469 ps
T380 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.150555756 May 02 12:53:38 PM PDT 24 May 02 12:53:52 PM PDT 24 183003108 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1584085266 May 02 12:53:25 PM PDT 24 May 02 12:53:48 PM PDT 24 5959538367 ps
T382 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3845461313 May 02 12:53:51 PM PDT 24 May 02 12:54:30 PM PDT 24 19289289600 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2724429429 May 02 12:53:20 PM PDT 24 May 02 12:53:48 PM PDT 24 2226735828 ps
T98 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1187156346 May 02 12:53:29 PM PDT 24 May 02 12:53:50 PM PDT 24 4251731621 ps
T384 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1160993263 May 02 12:53:29 PM PDT 24 May 02 12:53:54 PM PDT 24 10028543818 ps
T385 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1129320117 May 02 12:53:43 PM PDT 24 May 02 12:54:12 PM PDT 24 11811972368 ps
T386 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3865568119 May 02 12:53:51 PM PDT 24 May 02 12:54:18 PM PDT 24 10146323933 ps
T387 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3571771678 May 02 12:53:42 PM PDT 24 May 02 12:54:12 PM PDT 24 3380696172 ps
T388 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2580837628 May 02 12:53:36 PM PDT 24 May 02 12:53:50 PM PDT 24 167778980 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2142981738 May 02 12:53:24 PM PDT 24 May 02 12:53:53 PM PDT 24 16918447713 ps
T390 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.856284252 May 02 12:53:20 PM PDT 24 May 02 12:55:56 PM PDT 24 16786451760 ps
T123 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2715058128 May 02 12:53:27 PM PDT 24 May 02 12:54:51 PM PDT 24 1111843843 ps
T391 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.731806252 May 02 12:53:45 PM PDT 24 May 02 12:54:10 PM PDT 24 8542778881 ps
T392 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3685582649 May 02 12:53:23 PM PDT 24 May 02 12:53:40 PM PDT 24 579708234 ps
T393 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2412896018 May 02 12:53:38 PM PDT 24 May 02 12:54:06 PM PDT 24 2029537991 ps
T394 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.929284458 May 02 12:53:29 PM PDT 24 May 02 12:55:15 PM PDT 24 9193744023 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.943130723 May 02 12:53:37 PM PDT 24 May 02 12:54:16 PM PDT 24 11636182319 ps
T396 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.991076969 May 02 12:53:50 PM PDT 24 May 02 12:54:22 PM PDT 24 2466429496 ps
T99 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3239681202 May 02 12:53:28 PM PDT 24 May 02 12:53:56 PM PDT 24 2747325123 ps
T100 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1330043486 May 02 12:53:36 PM PDT 24 May 02 12:54:11 PM PDT 24 4007821436 ps
T101 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1713927628 May 02 12:53:35 PM PDT 24 May 02 12:54:59 PM PDT 24 7231762511 ps
T106 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.718826372 May 02 12:53:47 PM PDT 24 May 02 12:54:47 PM PDT 24 2157629029 ps
T397 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.635725315 May 02 12:53:44 PM PDT 24 May 02 12:54:18 PM PDT 24 16825008017 ps
T398 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1214485989 May 02 12:53:42 PM PDT 24 May 02 12:54:10 PM PDT 24 8905789561 ps
T399 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3241215943 May 02 12:53:33 PM PDT 24 May 02 12:53:59 PM PDT 24 2516865120 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4230479622 May 02 12:53:30 PM PDT 24 May 02 12:53:48 PM PDT 24 4094773774 ps
T107 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3273812018 May 02 12:53:27 PM PDT 24 May 02 12:54:08 PM PDT 24 690337186 ps
T401 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2570076052 May 02 12:53:38 PM PDT 24 May 02 12:53:51 PM PDT 24 174210690 ps
T402 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1684261089 May 02 12:53:53 PM PDT 24 May 02 12:55:25 PM PDT 24 3877979903 ps
T403 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.291230998 May 02 12:53:37 PM PDT 24 May 02 12:53:57 PM PDT 24 1081564289 ps
T404 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1743571544 May 02 12:53:44 PM PDT 24 May 02 12:54:06 PM PDT 24 1800043636 ps
T405 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3755436319 May 02 12:53:50 PM PDT 24 May 02 12:54:18 PM PDT 24 2623636041 ps
T406 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4076991842 May 02 12:53:30 PM PDT 24 May 02 12:53:50 PM PDT 24 2126891536 ps
T407 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3514321108 May 02 12:53:30 PM PDT 24 May 02 12:53:46 PM PDT 24 645431166 ps
T408 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3610697753 May 02 12:53:56 PM PDT 24 May 02 12:54:08 PM PDT 24 173610789 ps
T409 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.147935893 May 02 12:53:52 PM PDT 24 May 02 12:54:22 PM PDT 24 17534857433 ps
T410 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1127581016 May 02 12:53:27 PM PDT 24 May 02 12:54:02 PM PDT 24 32023945572 ps
T102 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3233205760 May 02 12:53:44 PM PDT 24 May 02 12:54:43 PM PDT 24 7338812066 ps
T411 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1791796611 May 02 12:53:50 PM PDT 24 May 02 12:54:22 PM PDT 24 12995178803 ps
T412 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4239226555 May 02 12:53:44 PM PDT 24 May 02 12:54:00 PM PDT 24 667019033 ps
T413 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3624202415 May 02 12:53:28 PM PDT 24 May 02 12:53:58 PM PDT 24 11418664427 ps
T414 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2312152133 May 02 12:53:31 PM PDT 24 May 02 12:53:58 PM PDT 24 2804065472 ps
T415 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4022794453 May 02 12:53:51 PM PDT 24 May 02 12:55:35 PM PDT 24 78339734029 ps
T416 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4244514062 May 02 12:53:24 PM PDT 24 May 02 12:53:49 PM PDT 24 18429278131 ps
T417 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.807251007 May 02 12:53:50 PM PDT 24 May 02 12:54:29 PM PDT 24 7644698397 ps
T418 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3371940273 May 02 12:53:29 PM PDT 24 May 02 12:55:31 PM PDT 24 10303148179 ps
T419 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3420179489 May 02 12:53:43 PM PDT 24 May 02 12:54:54 PM PDT 24 20563010939 ps
T420 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.287324569 May 02 12:53:41 PM PDT 24 May 02 12:53:53 PM PDT 24 1176999861 ps
T421 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.701266718 May 02 12:53:39 PM PDT 24 May 02 12:54:03 PM PDT 24 3924100587 ps
T422 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2609232117 May 02 12:53:23 PM PDT 24 May 02 12:53:36 PM PDT 24 661663435 ps
T423 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3692725907 May 02 12:53:49 PM PDT 24 May 02 12:54:25 PM PDT 24 3707167827 ps
T126 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4136118963 May 02 12:53:55 PM PDT 24 May 02 12:56:54 PM PDT 24 4550481688 ps
T424 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2500665206 May 02 12:53:22 PM PDT 24 May 02 12:53:39 PM PDT 24 4121334316 ps
T425 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3383946459 May 02 12:53:21 PM PDT 24 May 02 12:53:57 PM PDT 24 8892614437 ps
T426 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2851497343 May 02 12:53:28 PM PDT 24 May 02 12:55:00 PM PDT 24 6114099100 ps
T427 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.372123454 May 02 12:53:52 PM PDT 24 May 02 12:54:11 PM PDT 24 1189462915 ps
T428 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3499186103 May 02 12:53:38 PM PDT 24 May 02 12:54:00 PM PDT 24 1421740239 ps
T429 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3442651808 May 02 12:53:50 PM PDT 24 May 02 12:55:34 PM PDT 24 15193222760 ps
T430 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1427695725 May 02 12:53:45 PM PDT 24 May 02 12:54:05 PM PDT 24 4673257530 ps
T431 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2902163286 May 02 12:53:56 PM PDT 24 May 02 12:54:24 PM PDT 24 8892973090 ps
T103 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.545258859 May 02 12:53:22 PM PDT 24 May 02 12:53:34 PM PDT 24 231734044 ps
T432 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1160269061 May 02 12:53:22 PM PDT 24 May 02 12:53:59 PM PDT 24 12333581384 ps
T108 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2715352274 May 02 12:53:36 PM PDT 24 May 02 12:55:55 PM PDT 24 17106062973 ps
T433 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3924333614 May 02 12:53:22 PM PDT 24 May 02 12:53:39 PM PDT 24 3435739887 ps
T434 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1549735049 May 02 12:53:56 PM PDT 24 May 02 12:54:11 PM PDT 24 167591265 ps
T435 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.978360961 May 02 12:53:36 PM PDT 24 May 02 12:54:02 PM PDT 24 2131427960 ps
T436 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1871217279 May 02 12:53:43 PM PDT 24 May 02 12:54:14 PM PDT 24 3228060404 ps
T437 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1060877784 May 02 12:53:38 PM PDT 24 May 02 12:54:14 PM PDT 24 29600183793 ps
T438 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1009948368 May 02 12:53:44 PM PDT 24 May 02 12:54:19 PM PDT 24 16878666294 ps
T439 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1153408094 May 02 12:53:36 PM PDT 24 May 02 12:53:48 PM PDT 24 1179085241 ps
T440 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.95597326 May 02 12:53:46 PM PDT 24 May 02 12:54:14 PM PDT 24 15184326064 ps
T441 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3134088651 May 02 12:53:47 PM PDT 24 May 02 12:53:59 PM PDT 24 1179795701 ps
T124 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1932996887 May 02 12:53:42 PM PDT 24 May 02 12:56:26 PM PDT 24 4181143504 ps
T442 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3853318062 May 02 12:53:36 PM PDT 24 May 02 12:54:05 PM PDT 24 2926155788 ps
T443 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2021803557 May 02 12:53:37 PM PDT 24 May 02 12:54:13 PM PDT 24 6828474262 ps
T444 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2136077914 May 02 12:53:48 PM PDT 24 May 02 12:54:00 PM PDT 24 660284337 ps
T445 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3082216734 May 02 12:53:50 PM PDT 24 May 02 12:54:05 PM PDT 24 1369418176 ps
T446 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3945936945 May 02 12:53:51 PM PDT 24 May 02 12:54:20 PM PDT 24 4319089478 ps
T104 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2209093421 May 02 12:53:37 PM PDT 24 May 02 12:53:54 PM PDT 24 599147804 ps
T447 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2380207885 May 02 12:53:50 PM PDT 24 May 02 12:54:19 PM PDT 24 2829700168 ps
T448 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1684166787 May 02 12:53:26 PM PDT 24 May 02 12:53:38 PM PDT 24 660899438 ps
T127 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2406810725 May 02 12:53:36 PM PDT 24 May 02 12:55:16 PM PDT 24 3406500922 ps
T105 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.115636584 May 02 12:53:21 PM PDT 24 May 02 12:55:30 PM PDT 24 23119617775 ps
T449 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2639010837 May 02 12:53:20 PM PDT 24 May 02 12:53:35 PM PDT 24 750565891 ps
T450 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1954983723 May 02 12:53:50 PM PDT 24 May 02 12:54:23 PM PDT 24 14077667142 ps
T451 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2862746093 May 02 12:53:42 PM PDT 24 May 02 12:54:09 PM PDT 24 10939446584 ps
T452 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2228088865 May 02 12:53:55 PM PDT 24 May 02 12:54:19 PM PDT 24 8926455578 ps
T453 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2410431845 May 02 12:53:36 PM PDT 24 May 02 12:54:06 PM PDT 24 12360135067 ps

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2145345958
Short name T4
Test name
Test status
Simulation time 256184598717 ps
CPU time 641.63 seconds
Started May 02 12:54:37 PM PDT 24
Finished May 02 01:05:21 PM PDT 24
Peak memory 238308 kb
Host smart-a8b5e6ee-a215-4458-98ab-926015d4e58c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145345958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2145345958
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.4004717321
Short name T20
Test name
Test status
Simulation time 68834090603 ps
CPU time 3167.61 seconds
Started May 02 12:55:15 PM PDT 24
Finished May 02 01:48:06 PM PDT 24
Peak memory 231676 kb
Host smart-d5d17ed5-fcb8-4fb7-9b4e-c442efaef6db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004717321 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.4004717321
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2349557552
Short name T18
Test name
Test status
Simulation time 7973542791 ps
CPU time 49.19 seconds
Started May 02 12:54:49 PM PDT 24
Finished May 02 12:55:42 PM PDT 24
Peak memory 220088 kb
Host smart-02edf5aa-d34e-449f-b569-5c4f38dda792
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349557552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2349557552
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2386198525
Short name T135
Test name
Test status
Simulation time 930547127 ps
CPU time 10.25 seconds
Started May 02 12:54:52 PM PDT 24
Finished May 02 12:55:06 PM PDT 24
Peak memory 212532 kb
Host smart-ac0b9faf-be7e-4be5-a095-6acfe155f5db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2386198525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2386198525
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.36428294
Short name T9
Test name
Test status
Simulation time 48298939965 ps
CPU time 337.74 seconds
Started May 02 12:55:23 PM PDT 24
Finished May 02 01:01:06 PM PDT 24
Peak memory 240780 kb
Host smart-2f6c0f18-f29b-41c0-9b4d-30c117b65c60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36428294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_co
rrupt_sig_fatal_chk.36428294
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1337872940
Short name T59
Test name
Test status
Simulation time 11342010613 ps
CPU time 164.53 seconds
Started May 02 12:53:44 PM PDT 24
Finished May 02 12:56:32 PM PDT 24
Peak memory 213524 kb
Host smart-1b307846-659f-4bbc-9c01-3fcc7d53ee7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337872940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1337872940
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2727611372
Short name T15
Test name
Test status
Simulation time 7362704101 ps
CPU time 266.99 seconds
Started May 02 12:54:30 PM PDT 24
Finished May 02 12:59:00 PM PDT 24
Peak memory 239148 kb
Host smart-f57d9e3e-9274-480a-9605-9fa20f890570
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727611372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2727611372
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3608153601
Short name T69
Test name
Test status
Simulation time 170955546 ps
CPU time 8.47 seconds
Started May 02 12:54:04 PM PDT 24
Finished May 02 12:54:17 PM PDT 24
Peak memory 211576 kb
Host smart-17173ce7-223b-4981-96be-8216c2179bfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608153601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3608153601
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2587796206
Short name T142
Test name
Test status
Simulation time 5909658070 ps
CPU time 26.94 seconds
Started May 02 12:55:09 PM PDT 24
Finished May 02 12:55:39 PM PDT 24
Peak memory 213032 kb
Host smart-58b13ad0-fe45-4cba-ad9c-f59603cad21a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2587796206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2587796206
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3137084203
Short name T91
Test name
Test status
Simulation time 16578110910 ps
CPU time 53.44 seconds
Started May 02 12:54:44 PM PDT 24
Finished May 02 12:55:41 PM PDT 24
Peak memory 218640 kb
Host smart-bad7cda3-c4db-4f7d-9f95-24f22b98cea9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137084203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3137084203
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1002732249
Short name T32
Test name
Test status
Simulation time 7830479056 ps
CPU time 135.51 seconds
Started May 02 12:53:57 PM PDT 24
Finished May 02 12:56:16 PM PDT 24
Peak memory 239452 kb
Host smart-019739af-646f-4f4c-b008-443c21e0a78f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002732249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1002732249
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.972741629
Short name T96
Test name
Test status
Simulation time 11489423247 ps
CPU time 108.1 seconds
Started May 02 12:53:55 PM PDT 24
Finished May 02 12:55:47 PM PDT 24
Peak memory 212728 kb
Host smart-bb11b81d-0539-4e29-99fa-39749745c54a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972741629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.972741629
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3749774566
Short name T145
Test name
Test status
Simulation time 54954618597 ps
CPU time 113.28 seconds
Started May 02 12:53:55 PM PDT 24
Finished May 02 12:55:52 PM PDT 24
Peak memory 222476 kb
Host smart-0183575b-32ae-49cf-bdca-d1d1f38887c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749774566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3749774566
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3379105335
Short name T97
Test name
Test status
Simulation time 58825327231 ps
CPU time 115.46 seconds
Started May 02 12:53:49 PM PDT 24
Finished May 02 12:55:48 PM PDT 24
Peak memory 212700 kb
Host smart-976fbf29-79e9-450e-8009-e20f0a93507b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379105335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3379105335
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2925069488
Short name T1
Test name
Test status
Simulation time 33582292278 ps
CPU time 68.89 seconds
Started May 02 12:54:09 PM PDT 24
Finished May 02 12:55:21 PM PDT 24
Peak memory 215312 kb
Host smart-5d7bf406-9992-4056-a613-5edd024758fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925069488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2925069488
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3289410626
Short name T10
Test name
Test status
Simulation time 336076646 ps
CPU time 19.31 seconds
Started May 02 12:54:25 PM PDT 24
Finished May 02 12:54:47 PM PDT 24
Peak memory 215008 kb
Host smart-66fdf9f6-69d5-4534-ad36-020c7857a010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289410626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3289410626
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1932996887
Short name T124
Test name
Test status
Simulation time 4181143504 ps
CPU time 160.23 seconds
Started May 02 12:53:42 PM PDT 24
Finished May 02 12:56:26 PM PDT 24
Peak memory 214052 kb
Host smart-7f300493-6011-49bb-b027-80467f1f1390
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932996887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1932996887
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2898353607
Short name T120
Test name
Test status
Simulation time 4134171708 ps
CPU time 149.78 seconds
Started May 02 12:53:49 PM PDT 24
Finished May 02 12:56:24 PM PDT 24
Peak memory 213332 kb
Host smart-98736948-6ae4-4918-afce-56e5bc54e7da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898353607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2898353607
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1769231233
Short name T82
Test name
Test status
Simulation time 180793204 ps
CPU time 15.12 seconds
Started May 02 12:53:34 PM PDT 24
Finished May 02 12:53:53 PM PDT 24
Peak memory 210784 kb
Host smart-450aacb4-d45d-488a-ba0c-fe50985a0853
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769231233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1769231233
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2588417648
Short name T128
Test name
Test status
Simulation time 1369656843 ps
CPU time 83.77 seconds
Started May 02 12:53:23 PM PDT 24
Finished May 02 12:54:52 PM PDT 24
Peak memory 212852 kb
Host smart-9bd968f0-5513-4142-a932-e9e6f523f267
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588417648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2588417648
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3490654676
Short name T138
Test name
Test status
Simulation time 30809676373 ps
CPU time 68.19 seconds
Started May 02 12:53:51 PM PDT 24
Finished May 02 12:55:04 PM PDT 24
Peak memory 217440 kb
Host smart-e7c49fbb-d821-4bd9-8957-019dfee90f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490654676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3490654676
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3383946459
Short name T425
Test name
Test status
Simulation time 8892614437 ps
CPU time 31.61 seconds
Started May 02 12:53:21 PM PDT 24
Finished May 02 12:53:57 PM PDT 24
Peak memory 210824 kb
Host smart-35c47999-b966-4047-97f9-00d3f7b8c182
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383946459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3383946459
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4216083726
Short name T361
Test name
Test status
Simulation time 3273373872 ps
CPU time 26.7 seconds
Started May 02 12:53:22 PM PDT 24
Finished May 02 12:53:54 PM PDT 24
Peak memory 210436 kb
Host smart-c9fe767c-7f61-4475-b259-b66f59030c9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216083726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.4216083726
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1840397121
Short name T364
Test name
Test status
Simulation time 5407185332 ps
CPU time 21.46 seconds
Started May 02 12:53:19 PM PDT 24
Finished May 02 12:53:44 PM PDT 24
Peak memory 216868 kb
Host smart-3c062d6d-7e81-45cf-a310-0d14051158b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840397121 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1840397121
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2142981738
Short name T389
Test name
Test status
Simulation time 16918447713 ps
CPU time 23.64 seconds
Started May 02 12:53:24 PM PDT 24
Finished May 02 12:53:53 PM PDT 24
Peak memory 211368 kb
Host smart-fdac233c-3323-4e7a-be64-6504674fcac2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142981738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2142981738
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3956416901
Short name T377
Test name
Test status
Simulation time 1029970122 ps
CPU time 14.15 seconds
Started May 02 12:53:21 PM PDT 24
Finished May 02 12:53:38 PM PDT 24
Peak memory 210404 kb
Host smart-db198223-4b97-4df1-9ab8-835f83c32708
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956416901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3956416901
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.123340791
Short name T362
Test name
Test status
Simulation time 9457707969 ps
CPU time 25.96 seconds
Started May 02 12:53:24 PM PDT 24
Finished May 02 12:53:54 PM PDT 24
Peak memory 210492 kb
Host smart-faac3ea5-b842-48c3-81bc-2055ad2e0c13
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123340791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
123340791
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.856284252
Short name T390
Test name
Test status
Simulation time 16786451760 ps
CPU time 151.68 seconds
Started May 02 12:53:20 PM PDT 24
Finished May 02 12:55:56 PM PDT 24
Peak memory 214740 kb
Host smart-2b5c47ce-3ac7-4c07-862d-e63ed1f62418
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856284252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.856284252
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3285980752
Short name T109
Test name
Test status
Simulation time 4505523195 ps
CPU time 33.33 seconds
Started May 02 12:53:21 PM PDT 24
Finished May 02 12:53:59 PM PDT 24
Peak memory 212076 kb
Host smart-16ad71a1-da8d-4d67-8e3f-28ee805a8e9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285980752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3285980752
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2639010837
Short name T449
Test name
Test status
Simulation time 750565891 ps
CPU time 11.84 seconds
Started May 02 12:53:20 PM PDT 24
Finished May 02 12:53:35 PM PDT 24
Peak memory 216820 kb
Host smart-9f6c84ba-8875-4362-9e24-e19ad5f73e56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639010837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2639010837
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3924333614
Short name T433
Test name
Test status
Simulation time 3435739887 ps
CPU time 13.58 seconds
Started May 02 12:53:22 PM PDT 24
Finished May 02 12:53:39 PM PDT 24
Peak memory 218644 kb
Host smart-a790da77-3cd1-4566-affd-0ff6754b30af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924333614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3924333614
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2500665206
Short name T424
Test name
Test status
Simulation time 4121334316 ps
CPU time 11.53 seconds
Started May 02 12:53:22 PM PDT 24
Finished May 02 12:53:39 PM PDT 24
Peak memory 210460 kb
Host smart-19c2b436-dbd6-42ee-a291-8fa0da2be73c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500665206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2500665206
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.887815562
Short name T88
Test name
Test status
Simulation time 7914148201 ps
CPU time 22.97 seconds
Started May 02 12:53:22 PM PDT 24
Finished May 02 12:53:50 PM PDT 24
Peak memory 211636 kb
Host smart-5baf8bba-34d4-4d45-ac0c-16e57f852436
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887815562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.887815562
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3685582649
Short name T392
Test name
Test status
Simulation time 579708234 ps
CPU time 12.37 seconds
Started May 02 12:53:23 PM PDT 24
Finished May 02 12:53:40 PM PDT 24
Peak memory 213620 kb
Host smart-065322b9-14e3-48ad-8dde-5e90b4534574
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685582649 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3685582649
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.545258859
Short name T103
Test name
Test status
Simulation time 231734044 ps
CPU time 7.93 seconds
Started May 02 12:53:22 PM PDT 24
Finished May 02 12:53:34 PM PDT 24
Peak memory 210512 kb
Host smart-5117c087-2a70-4a26-a9ff-dbf2e7dfed5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545258859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.545258859
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4244514062
Short name T416
Test name
Test status
Simulation time 18429278131 ps
CPU time 20.83 seconds
Started May 02 12:53:24 PM PDT 24
Finished May 02 12:53:49 PM PDT 24
Peak memory 210416 kb
Host smart-4ac254d5-8639-4be1-ac67-d0b9639af81e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244514062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4244514062
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2609232117
Short name T422
Test name
Test status
Simulation time 661663435 ps
CPU time 8.01 seconds
Started May 02 12:53:23 PM PDT 24
Finished May 02 12:53:36 PM PDT 24
Peak memory 210380 kb
Host smart-1a1960de-5be7-4507-8148-69398e825195
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609232117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2609232117
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.115636584
Short name T105
Test name
Test status
Simulation time 23119617775 ps
CPU time 124.58 seconds
Started May 02 12:53:21 PM PDT 24
Finished May 02 12:55:30 PM PDT 24
Peak memory 214720 kb
Host smart-9d6fba43-6a2d-462c-a9d6-32323c2a51a4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115636584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.115636584
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3963141184
Short name T114
Test name
Test status
Simulation time 3860934780 ps
CPU time 29.09 seconds
Started May 02 12:53:22 PM PDT 24
Finished May 02 12:53:55 PM PDT 24
Peak memory 211356 kb
Host smart-a7480a32-dd9e-4af5-9a0c-7f887e7adeb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963141184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3963141184
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2724429429
Short name T383
Test name
Test status
Simulation time 2226735828 ps
CPU time 24.04 seconds
Started May 02 12:53:20 PM PDT 24
Finished May 02 12:53:48 PM PDT 24
Peak memory 216740 kb
Host smart-78544efb-d967-4e49-adfc-03e9377adb87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724429429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2724429429
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2862381480
Short name T77
Test name
Test status
Simulation time 910419210 ps
CPU time 84.5 seconds
Started May 02 12:53:22 PM PDT 24
Finished May 02 12:54:52 PM PDT 24
Peak memory 212736 kb
Host smart-00b0acd8-821a-4b40-b588-a22957334d37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862381480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2862381480
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.635725315
Short name T397
Test name
Test status
Simulation time 16825008017 ps
CPU time 30.95 seconds
Started May 02 12:53:44 PM PDT 24
Finished May 02 12:54:18 PM PDT 24
Peak memory 217616 kb
Host smart-e5124cd4-ee4c-42c1-b894-3aa2793bf50a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635725315 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.635725315
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1129320117
Short name T385
Test name
Test status
Simulation time 11811972368 ps
CPU time 25.46 seconds
Started May 02 12:53:43 PM PDT 24
Finished May 02 12:54:12 PM PDT 24
Peak memory 211376 kb
Host smart-28b7ccec-cdae-44e2-bda8-6180974eb5df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129320117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1129320117
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3420179489
Short name T419
Test name
Test status
Simulation time 20563010939 ps
CPU time 67.41 seconds
Started May 02 12:53:43 PM PDT 24
Finished May 02 12:54:54 PM PDT 24
Peak memory 212740 kb
Host smart-0534a17f-7c56-404c-8368-ab2a8d434be7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420179489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3420179489
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2862746093
Short name T451
Test name
Test status
Simulation time 10939446584 ps
CPU time 22.87 seconds
Started May 02 12:53:42 PM PDT 24
Finished May 02 12:54:09 PM PDT 24
Peak memory 211896 kb
Host smart-0d69902f-d77b-4ee4-979c-2f9f9c65daa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862746093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2862746093
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3388422467
Short name T374
Test name
Test status
Simulation time 4440141221 ps
CPU time 38.53 seconds
Started May 02 12:53:46 PM PDT 24
Finished May 02 12:54:28 PM PDT 24
Peak memory 218028 kb
Host smart-ee1b2f75-0b62-4b25-b125-18dbe53370e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388422467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3388422467
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1009948368
Short name T438
Test name
Test status
Simulation time 16878666294 ps
CPU time 31.08 seconds
Started May 02 12:53:44 PM PDT 24
Finished May 02 12:54:19 PM PDT 24
Peak memory 217788 kb
Host smart-c4736487-53a7-4123-86eb-5e02f16d91ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009948368 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1009948368
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3789906928
Short name T116
Test name
Test status
Simulation time 1374459438 ps
CPU time 7.91 seconds
Started May 02 12:53:45 PM PDT 24
Finished May 02 12:53:57 PM PDT 24
Peak memory 210516 kb
Host smart-5d361f6b-d99f-4d3e-8252-f0951876d72d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789906928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3789906928
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.718826372
Short name T106
Test name
Test status
Simulation time 2157629029 ps
CPU time 56.62 seconds
Started May 02 12:53:47 PM PDT 24
Finished May 02 12:54:47 PM PDT 24
Peak memory 214664 kb
Host smart-b305a5a9-cdb7-4b0f-90a7-b5463e644be3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718826372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.718826372
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1214485989
Short name T398
Test name
Test status
Simulation time 8905789561 ps
CPU time 24.58 seconds
Started May 02 12:53:42 PM PDT 24
Finished May 02 12:54:10 PM PDT 24
Peak memory 212136 kb
Host smart-4569a557-9167-401a-8df4-519d9308dc45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214485989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1214485989
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.95597326
Short name T440
Test name
Test status
Simulation time 15184326064 ps
CPU time 24.69 seconds
Started May 02 12:53:46 PM PDT 24
Finished May 02 12:54:14 PM PDT 24
Peak memory 217748 kb
Host smart-28b30f72-5a8f-4632-b21a-65d3aa67c4b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95597326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.95597326
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3826936301
Short name T368
Test name
Test status
Simulation time 15064133073 ps
CPU time 30.18 seconds
Started May 02 12:53:43 PM PDT 24
Finished May 02 12:54:16 PM PDT 24
Peak memory 215120 kb
Host smart-02e2a40d-f05e-4d79-85e6-1c3a23ff359f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826936301 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3826936301
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.287324569
Short name T420
Test name
Test status
Simulation time 1176999861 ps
CPU time 7.98 seconds
Started May 02 12:53:41 PM PDT 24
Finished May 02 12:53:53 PM PDT 24
Peak memory 210496 kb
Host smart-29c5a053-3863-4ac1-9851-eca1e90487a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287324569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.287324569
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2566846949
Short name T83
Test name
Test status
Simulation time 28759941289 ps
CPU time 78.07 seconds
Started May 02 12:53:43 PM PDT 24
Finished May 02 12:55:04 PM PDT 24
Peak memory 212856 kb
Host smart-5ab4d7a2-f6dc-4ecc-82b4-f7116ed7c4b4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566846949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2566846949
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3134088651
Short name T441
Test name
Test status
Simulation time 1179795701 ps
CPU time 8.12 seconds
Started May 02 12:53:47 PM PDT 24
Finished May 02 12:53:59 PM PDT 24
Peak memory 210448 kb
Host smart-9abbb681-8750-4cb3-a786-46578e0a8b9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134088651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3134088651
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1427695725
Short name T430
Test name
Test status
Simulation time 4673257530 ps
CPU time 16.26 seconds
Started May 02 12:53:45 PM PDT 24
Finished May 02 12:54:05 PM PDT 24
Peak memory 217204 kb
Host smart-55bf7161-e5fa-488e-a196-36a2869400e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427695725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1427695725
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.67955434
Short name T121
Test name
Test status
Simulation time 6387034371 ps
CPU time 97.72 seconds
Started May 02 12:53:54 PM PDT 24
Finished May 02 12:55:35 PM PDT 24
Peak memory 213044 kb
Host smart-5e2b17ca-196c-4402-ad55-9b2460fd7665
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67955434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_int
g_err.67955434
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3840388790
Short name T57
Test name
Test status
Simulation time 2141424868 ps
CPU time 12.74 seconds
Started May 02 12:53:46 PM PDT 24
Finished May 02 12:54:02 PM PDT 24
Peak memory 216228 kb
Host smart-5efd5da1-5fab-438f-85cc-c476849706f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840388790 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3840388790
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4239226555
Short name T412
Test name
Test status
Simulation time 667019033 ps
CPU time 12.52 seconds
Started May 02 12:53:44 PM PDT 24
Finished May 02 12:54:00 PM PDT 24
Peak memory 210460 kb
Host smart-bba197b9-78f2-4ccc-93fa-b946da193499
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239226555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.4239226555
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3233205760
Short name T102
Test name
Test status
Simulation time 7338812066 ps
CPU time 55.56 seconds
Started May 02 12:53:44 PM PDT 24
Finished May 02 12:54:43 PM PDT 24
Peak memory 211068 kb
Host smart-ca89d1a9-45b7-4cda-b6ba-c68b63641d20
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233205760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3233205760
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3604117547
Short name T113
Test name
Test status
Simulation time 19932999711 ps
CPU time 30.93 seconds
Started May 02 12:53:44 PM PDT 24
Finished May 02 12:54:18 PM PDT 24
Peak memory 211404 kb
Host smart-cacca746-2107-48fc-ac8c-6674dc995494
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604117547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3604117547
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2528990892
Short name T376
Test name
Test status
Simulation time 688045024 ps
CPU time 10.73 seconds
Started May 02 12:53:45 PM PDT 24
Finished May 02 12:53:59 PM PDT 24
Peak memory 218748 kb
Host smart-26a557e1-8d75-44c4-bb49-7848dc8565ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528990892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2528990892
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1120746191
Short name T56
Test name
Test status
Simulation time 1631428516 ps
CPU time 80.6 seconds
Started May 02 12:53:46 PM PDT 24
Finished May 02 12:55:09 PM PDT 24
Peak memory 212944 kb
Host smart-d5eb3eed-4ba1-412f-bae4-1a536b662c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120746191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1120746191
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3610697753
Short name T408
Test name
Test status
Simulation time 173610789 ps
CPU time 8.43 seconds
Started May 02 12:53:56 PM PDT 24
Finished May 02 12:54:08 PM PDT 24
Peak memory 213740 kb
Host smart-3b025368-96ba-46e0-8ca0-b974cce1f8b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610697753 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3610697753
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.731806252
Short name T391
Test name
Test status
Simulation time 8542778881 ps
CPU time 21.54 seconds
Started May 02 12:53:45 PM PDT 24
Finished May 02 12:54:10 PM PDT 24
Peak memory 211428 kb
Host smart-2e737f01-1314-437d-b3d9-2b509625d029
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731806252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.731806252
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3518473749
Short name T84
Test name
Test status
Simulation time 98253260232 ps
CPU time 186.87 seconds
Started May 02 12:53:44 PM PDT 24
Finished May 02 12:56:54 PM PDT 24
Peak memory 214716 kb
Host smart-e53a9cdc-7a35-476e-a10a-23314ef1ac1a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518473749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3518473749
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1871217279
Short name T436
Test name
Test status
Simulation time 3228060404 ps
CPU time 27.45 seconds
Started May 02 12:53:43 PM PDT 24
Finished May 02 12:54:14 PM PDT 24
Peak memory 211772 kb
Host smart-7906b0dc-5db7-487f-a3b9-9a2da28d2e4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871217279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1871217279
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1549735049
Short name T434
Test name
Test status
Simulation time 167591265 ps
CPU time 11.63 seconds
Started May 02 12:53:56 PM PDT 24
Finished May 02 12:54:11 PM PDT 24
Peak memory 216440 kb
Host smart-1ffee5c4-35a6-43c1-a452-d2644e512a99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549735049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1549735049
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.989462828
Short name T371
Test name
Test status
Simulation time 26880132281 ps
CPU time 168.36 seconds
Started May 02 12:53:43 PM PDT 24
Finished May 02 12:56:35 PM PDT 24
Peak memory 213396 kb
Host smart-66671ee4-5dfe-4218-a294-f68bf375391a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989462828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.989462828
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2380207885
Short name T447
Test name
Test status
Simulation time 2829700168 ps
CPU time 24.77 seconds
Started May 02 12:53:50 PM PDT 24
Finished May 02 12:54:19 PM PDT 24
Peak memory 214884 kb
Host smart-d6db57f0-f3a4-47d7-a0a0-91f20c98b1e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380207885 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2380207885
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2136077914
Short name T444
Test name
Test status
Simulation time 660284337 ps
CPU time 7.89 seconds
Started May 02 12:53:48 PM PDT 24
Finished May 02 12:54:00 PM PDT 24
Peak memory 210548 kb
Host smart-76d4c8a2-7279-4513-9a53-d083a7624932
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136077914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2136077914
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3905660919
Short name T110
Test name
Test status
Simulation time 22439448191 ps
CPU time 186.62 seconds
Started May 02 12:53:43 PM PDT 24
Finished May 02 12:56:53 PM PDT 24
Peak memory 214920 kb
Host smart-6595e4b9-1d59-447c-a249-dabca41fb6e7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905660919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3905660919
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.372123454
Short name T427
Test name
Test status
Simulation time 1189462915 ps
CPU time 14.71 seconds
Started May 02 12:53:52 PM PDT 24
Finished May 02 12:54:11 PM PDT 24
Peak memory 210416 kb
Host smart-308e6960-e1f0-4b27-b817-3331bb7c8d52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372123454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.372123454
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.991076969
Short name T396
Test name
Test status
Simulation time 2466429496 ps
CPU time 27.25 seconds
Started May 02 12:53:50 PM PDT 24
Finished May 02 12:54:22 PM PDT 24
Peak memory 218732 kb
Host smart-8e44bdb4-497e-4790-9d7a-cfbfe0bf4043
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991076969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.991076969
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3442651808
Short name T429
Test name
Test status
Simulation time 15193222760 ps
CPU time 99.66 seconds
Started May 02 12:53:50 PM PDT 24
Finished May 02 12:55:34 PM PDT 24
Peak memory 212864 kb
Host smart-ae30d1af-fc63-4ff0-ba04-ca300c11c38e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442651808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3442651808
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2100639154
Short name T80
Test name
Test status
Simulation time 1916804708 ps
CPU time 14.59 seconds
Started May 02 12:53:50 PM PDT 24
Finished May 02 12:54:10 PM PDT 24
Peak memory 216540 kb
Host smart-a91dd0c5-e65e-4b3c-b2a5-78cb03fe01c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100639154 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2100639154
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2228088865
Short name T452
Test name
Test status
Simulation time 8926455578 ps
CPU time 19.58 seconds
Started May 02 12:53:55 PM PDT 24
Finished May 02 12:54:19 PM PDT 24
Peak memory 211312 kb
Host smart-88c95dce-4858-4000-a39b-a86c80576d07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228088865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2228088865
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3945936945
Short name T446
Test name
Test status
Simulation time 4319089478 ps
CPU time 24.47 seconds
Started May 02 12:53:51 PM PDT 24
Finished May 02 12:54:20 PM PDT 24
Peak memory 211772 kb
Host smart-125f25f7-3108-4680-94b5-a09b084eefc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945936945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3945936945
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3692725907
Short name T423
Test name
Test status
Simulation time 3707167827 ps
CPU time 32.48 seconds
Started May 02 12:53:49 PM PDT 24
Finished May 02 12:54:25 PM PDT 24
Peak memory 217896 kb
Host smart-9d245346-3033-44b2-ace9-3e5166c8a614
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692725907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3692725907
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4280826481
Short name T125
Test name
Test status
Simulation time 4790417562 ps
CPU time 96.87 seconds
Started May 02 12:53:55 PM PDT 24
Finished May 02 12:55:36 PM PDT 24
Peak memory 213152 kb
Host smart-f4ffeba1-8613-4e86-ac74-7cbbaba65659
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280826481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.4280826481
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.147935893
Short name T409
Test name
Test status
Simulation time 17534857433 ps
CPU time 26.2 seconds
Started May 02 12:53:52 PM PDT 24
Finished May 02 12:54:22 PM PDT 24
Peak memory 217700 kb
Host smart-6627ccf6-5dc6-4667-93a3-e490c3bfeb1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147935893 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.147935893
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3082216734
Short name T445
Test name
Test status
Simulation time 1369418176 ps
CPU time 10.38 seconds
Started May 02 12:53:50 PM PDT 24
Finished May 02 12:54:05 PM PDT 24
Peak memory 210344 kb
Host smart-5300bd5b-2895-43de-802a-6412fdb28773
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082216734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3082216734
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1231154347
Short name T115
Test name
Test status
Simulation time 22083343195 ps
CPU time 181.58 seconds
Started May 02 12:53:50 PM PDT 24
Finished May 02 12:56:56 PM PDT 24
Peak memory 215012 kb
Host smart-bd17453c-0605-4260-b85b-72dd21d17ac3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231154347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1231154347
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1576969982
Short name T111
Test name
Test status
Simulation time 172684594 ps
CPU time 11.72 seconds
Started May 02 12:53:51 PM PDT 24
Finished May 02 12:54:07 PM PDT 24
Peak memory 211580 kb
Host smart-e1842373-e148-47d5-bcbb-a10672093c9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576969982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1576969982
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2902163286
Short name T431
Test name
Test status
Simulation time 8892973090 ps
CPU time 24.54 seconds
Started May 02 12:53:56 PM PDT 24
Finished May 02 12:54:24 PM PDT 24
Peak memory 216272 kb
Host smart-bb324573-fd72-4357-b50d-c76eaba84f74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902163286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2902163286
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1954983723
Short name T450
Test name
Test status
Simulation time 14077667142 ps
CPU time 29.45 seconds
Started May 02 12:53:50 PM PDT 24
Finished May 02 12:54:23 PM PDT 24
Peak memory 217760 kb
Host smart-b43b2dfa-c69f-44a0-a4c7-b12fb8bb06f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954983723 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1954983723
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3755436319
Short name T405
Test name
Test status
Simulation time 2623636041 ps
CPU time 23.7 seconds
Started May 02 12:53:50 PM PDT 24
Finished May 02 12:54:18 PM PDT 24
Peak memory 210444 kb
Host smart-cb007abd-83a6-416b-af99-7cacd5faacd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755436319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3755436319
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2192785505
Short name T86
Test name
Test status
Simulation time 3684229647 ps
CPU time 29.31 seconds
Started May 02 12:53:52 PM PDT 24
Finished May 02 12:54:26 PM PDT 24
Peak memory 211580 kb
Host smart-a6faa7ff-358f-4623-a029-8f9d4784fe63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192785505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2192785505
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.807251007
Short name T417
Test name
Test status
Simulation time 7644698397 ps
CPU time 34.03 seconds
Started May 02 12:53:50 PM PDT 24
Finished May 02 12:54:29 PM PDT 24
Peak memory 217184 kb
Host smart-ab2c7fae-46f3-4380-b9da-e6dc21b20212
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807251007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.807251007
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1684261089
Short name T402
Test name
Test status
Simulation time 3877979903 ps
CPU time 87.67 seconds
Started May 02 12:53:53 PM PDT 24
Finished May 02 12:55:25 PM PDT 24
Peak memory 211404 kb
Host smart-b38df19f-ae67-43a0-b068-998793ae0d50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684261089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1684261089
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.117008588
Short name T363
Test name
Test status
Simulation time 1345335194 ps
CPU time 13.01 seconds
Started May 02 12:53:49 PM PDT 24
Finished May 02 12:54:06 PM PDT 24
Peak memory 215968 kb
Host smart-cce1f2a2-048a-48a2-88ac-581e3f085ceb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117008588 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.117008588
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3865568119
Short name T386
Test name
Test status
Simulation time 10146323933 ps
CPU time 22.89 seconds
Started May 02 12:53:51 PM PDT 24
Finished May 02 12:54:18 PM PDT 24
Peak memory 211356 kb
Host smart-52587633-e93a-43b9-ba92-154be76567c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865568119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3865568119
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4022794453
Short name T415
Test name
Test status
Simulation time 78339734029 ps
CPU time 99.82 seconds
Started May 02 12:53:51 PM PDT 24
Finished May 02 12:55:35 PM PDT 24
Peak memory 212828 kb
Host smart-709f5b6e-fd6c-42dc-869a-3377fd9022d3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022794453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.4022794453
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1791796611
Short name T411
Test name
Test status
Simulation time 12995178803 ps
CPU time 26.91 seconds
Started May 02 12:53:50 PM PDT 24
Finished May 02 12:54:22 PM PDT 24
Peak memory 211804 kb
Host smart-e6b853ee-4eb9-4b3d-b094-cc015cf7e8c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791796611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1791796611
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3845461313
Short name T382
Test name
Test status
Simulation time 19289289600 ps
CPU time 34.65 seconds
Started May 02 12:53:51 PM PDT 24
Finished May 02 12:54:30 PM PDT 24
Peak memory 218268 kb
Host smart-7326cfb6-768f-4d00-8027-68d99fbcf588
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845461313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3845461313
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4136118963
Short name T126
Test name
Test status
Simulation time 4550481688 ps
CPU time 174.73 seconds
Started May 02 12:53:55 PM PDT 24
Finished May 02 12:56:54 PM PDT 24
Peak memory 214452 kb
Host smart-626af434-b0ec-4ea3-8420-54a07d0dafc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136118963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.4136118963
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1491856152
Short name T119
Test name
Test status
Simulation time 8167525459 ps
CPU time 32.61 seconds
Started May 02 12:53:29 PM PDT 24
Finished May 02 12:54:05 PM PDT 24
Peak memory 211480 kb
Host smart-dcd6f7c5-4bcf-4835-b65e-dafdf39f6c6f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491856152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1491856152
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3496566778
Short name T117
Test name
Test status
Simulation time 2820224233 ps
CPU time 23.66 seconds
Started May 02 12:53:28 PM PDT 24
Finished May 02 12:53:55 PM PDT 24
Peak memory 210548 kb
Host smart-3b905ced-ef59-4bae-b6a3-d66034450a29
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496566778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3496566778
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1830901059
Short name T118
Test name
Test status
Simulation time 5770919145 ps
CPU time 24.47 seconds
Started May 02 12:53:29 PM PDT 24
Finished May 02 12:53:57 PM PDT 24
Peak memory 211532 kb
Host smart-42ff0e2d-bc27-4203-889f-c5b7650d1bf9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830901059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1830901059
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1584085266
Short name T381
Test name
Test status
Simulation time 5959538367 ps
CPU time 18.26 seconds
Started May 02 12:53:25 PM PDT 24
Finished May 02 12:53:48 PM PDT 24
Peak memory 216924 kb
Host smart-b1b97ce4-6325-4031-8d29-9cba82b5425f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584085266 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1584085266
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1127581016
Short name T410
Test name
Test status
Simulation time 32023945572 ps
CPU time 31.22 seconds
Started May 02 12:53:27 PM PDT 24
Finished May 02 12:54:02 PM PDT 24
Peak memory 211524 kb
Host smart-08eb50a9-c2ac-4671-b798-6bf5fc62cff9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127581016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1127581016
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1684166787
Short name T448
Test name
Test status
Simulation time 660899438 ps
CPU time 8.01 seconds
Started May 02 12:53:26 PM PDT 24
Finished May 02 12:53:38 PM PDT 24
Peak memory 210336 kb
Host smart-cef1f7e1-0bc2-4df8-a3dd-779a55b81907
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684166787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1684166787
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3624202415
Short name T413
Test name
Test status
Simulation time 11418664427 ps
CPU time 26.4 seconds
Started May 02 12:53:28 PM PDT 24
Finished May 02 12:53:58 PM PDT 24
Peak memory 210540 kb
Host smart-6664d4e8-033f-4408-a359-6abcafd8461e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624202415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3624202415
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2671602532
Short name T87
Test name
Test status
Simulation time 1412489132 ps
CPU time 37.85 seconds
Started May 02 12:53:25 PM PDT 24
Finished May 02 12:54:07 PM PDT 24
Peak memory 212608 kb
Host smart-53a92d5d-4132-46f2-952c-64be2ead79b8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671602532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2671602532
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3514321108
Short name T407
Test name
Test status
Simulation time 645431166 ps
CPU time 12.15 seconds
Started May 02 12:53:30 PM PDT 24
Finished May 02 12:53:46 PM PDT 24
Peak memory 211712 kb
Host smart-799da896-e3a2-456b-8f10-9efff767ccfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514321108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3514321108
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1160269061
Short name T432
Test name
Test status
Simulation time 12333581384 ps
CPU time 32.01 seconds
Started May 02 12:53:22 PM PDT 24
Finished May 02 12:53:59 PM PDT 24
Peak memory 217084 kb
Host smart-1b2cd77f-cea0-48a0-8907-725cd7b1a588
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160269061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1160269061
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2851497343
Short name T426
Test name
Test status
Simulation time 6114099100 ps
CPU time 87.57 seconds
Started May 02 12:53:28 PM PDT 24
Finished May 02 12:55:00 PM PDT 24
Peak memory 212824 kb
Host smart-6780c567-e819-4960-beb5-0b0dcd2f94a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851497343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2851497343
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3239681202
Short name T99
Test name
Test status
Simulation time 2747325123 ps
CPU time 24.45 seconds
Started May 02 12:53:28 PM PDT 24
Finished May 02 12:53:56 PM PDT 24
Peak memory 210728 kb
Host smart-90363873-48c4-4444-9716-3e65e91c1d4e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239681202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3239681202
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2050584498
Short name T367
Test name
Test status
Simulation time 14642606420 ps
CPU time 28.81 seconds
Started May 02 12:53:27 PM PDT 24
Finished May 02 12:53:59 PM PDT 24
Peak memory 211156 kb
Host smart-453680ba-7546-4847-a7a5-243e25e6ab2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050584498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2050584498
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1187156346
Short name T98
Test name
Test status
Simulation time 4251731621 ps
CPU time 18.25 seconds
Started May 02 12:53:29 PM PDT 24
Finished May 02 12:53:50 PM PDT 24
Peak memory 211252 kb
Host smart-4bb168fb-6ad2-4e7e-b848-0f5881cbe8ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187156346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1187156346
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3241215943
Short name T399
Test name
Test status
Simulation time 2516865120 ps
CPU time 23.38 seconds
Started May 02 12:53:33 PM PDT 24
Finished May 02 12:53:59 PM PDT 24
Peak memory 214880 kb
Host smart-92558ec8-61c0-4d15-9845-fa5a8709529f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241215943 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3241215943
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1160993263
Short name T384
Test name
Test status
Simulation time 10028543818 ps
CPU time 21.66 seconds
Started May 02 12:53:29 PM PDT 24
Finished May 02 12:53:54 PM PDT 24
Peak memory 211628 kb
Host smart-70838022-184b-4982-985b-4c9fad5092b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160993263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1160993263
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4230479622
Short name T400
Test name
Test status
Simulation time 4094773774 ps
CPU time 14.23 seconds
Started May 02 12:53:30 PM PDT 24
Finished May 02 12:53:48 PM PDT 24
Peak memory 210324 kb
Host smart-4684514f-1b20-4e2f-853c-ec7ad20ccb26
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230479622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.4230479622
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2575250364
Short name T365
Test name
Test status
Simulation time 6855222502 ps
CPU time 19.35 seconds
Started May 02 12:53:28 PM PDT 24
Finished May 02 12:53:50 PM PDT 24
Peak memory 210544 kb
Host smart-e45df27a-4804-4fda-9075-ce0994ba51ec
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575250364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2575250364
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3273812018
Short name T107
Test name
Test status
Simulation time 690337186 ps
CPU time 37.62 seconds
Started May 02 12:53:27 PM PDT 24
Finished May 02 12:54:08 PM PDT 24
Peak memory 212608 kb
Host smart-4a09381d-e27d-493c-bd8e-cdf7f9f63977
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273812018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3273812018
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2312152133
Short name T414
Test name
Test status
Simulation time 2804065472 ps
CPU time 24.07 seconds
Started May 02 12:53:31 PM PDT 24
Finished May 02 12:53:58 PM PDT 24
Peak memory 211544 kb
Host smart-64c4ccef-749f-479b-9f04-5bc109dc06fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312152133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2312152133
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4061820923
Short name T366
Test name
Test status
Simulation time 1320402541 ps
CPU time 18.99 seconds
Started May 02 12:53:27 PM PDT 24
Finished May 02 12:53:50 PM PDT 24
Peak memory 218744 kb
Host smart-0caf187d-67e6-41a7-97fc-a795974c9bef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061820923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4061820923
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2715058128
Short name T123
Test name
Test status
Simulation time 1111843843 ps
CPU time 80.43 seconds
Started May 02 12:53:27 PM PDT 24
Finished May 02 12:54:51 PM PDT 24
Peak memory 212984 kb
Host smart-5da4ad3e-a993-4511-988b-e60e55aa4e82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715058128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2715058128
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2209093421
Short name T104
Test name
Test status
Simulation time 599147804 ps
CPU time 12.14 seconds
Started May 02 12:53:37 PM PDT 24
Finished May 02 12:53:54 PM PDT 24
Peak memory 210436 kb
Host smart-16d16e31-d9fd-471c-bd08-82c17d04b621
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209093421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2209093421
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2580837628
Short name T388
Test name
Test status
Simulation time 167778980 ps
CPU time 8.4 seconds
Started May 02 12:53:36 PM PDT 24
Finished May 02 12:53:50 PM PDT 24
Peak memory 210480 kb
Host smart-17f3e119-2224-4cc8-a0bc-965dcb6e1b2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580837628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2580837628
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.943130723
Short name T395
Test name
Test status
Simulation time 11636182319 ps
CPU time 34.2 seconds
Started May 02 12:53:37 PM PDT 24
Finished May 02 12:54:16 PM PDT 24
Peak memory 211616 kb
Host smart-82f01488-d322-4930-b1db-747228b43a9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943130723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.943130723
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.701266718
Short name T421
Test name
Test status
Simulation time 3924100587 ps
CPU time 20.22 seconds
Started May 02 12:53:39 PM PDT 24
Finished May 02 12:54:03 PM PDT 24
Peak memory 218792 kb
Host smart-479b50e6-55d8-4d91-901d-77dd75e6b6a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701266718 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.701266718
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1153408094
Short name T439
Test name
Test status
Simulation time 1179085241 ps
CPU time 8.05 seconds
Started May 02 12:53:36 PM PDT 24
Finished May 02 12:53:48 PM PDT 24
Peak memory 210456 kb
Host smart-0d3e5a8a-241a-4e43-8793-bcf859f33465
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153408094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1153408094
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3158323950
Short name T370
Test name
Test status
Simulation time 14677781656 ps
CPU time 30.04 seconds
Started May 02 12:53:29 PM PDT 24
Finished May 02 12:54:03 PM PDT 24
Peak memory 210416 kb
Host smart-53128df9-77fa-487a-a71c-d46d61d2414c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158323950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3158323950
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2185633634
Short name T375
Test name
Test status
Simulation time 2165287865 ps
CPU time 20.25 seconds
Started May 02 12:53:30 PM PDT 24
Finished May 02 12:53:54 PM PDT 24
Peak memory 210472 kb
Host smart-fc9f982e-961e-47c7-9694-27a5034a2bb3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185633634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2185633634
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3371940273
Short name T418
Test name
Test status
Simulation time 10303148179 ps
CPU time 118.48 seconds
Started May 02 12:53:29 PM PDT 24
Finished May 02 12:55:31 PM PDT 24
Peak memory 215004 kb
Host smart-133e9b60-6079-413f-83ef-54345d24e2e7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371940273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3371940273
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2570076052
Short name T401
Test name
Test status
Simulation time 174210690 ps
CPU time 8.27 seconds
Started May 02 12:53:38 PM PDT 24
Finished May 02 12:53:51 PM PDT 24
Peak memory 210484 kb
Host smart-a4b21925-d9e5-4344-86cc-87f2c87f6ac4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570076052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2570076052
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4076991842
Short name T406
Test name
Test status
Simulation time 2126891536 ps
CPU time 16.72 seconds
Started May 02 12:53:30 PM PDT 24
Finished May 02 12:53:50 PM PDT 24
Peak memory 216760 kb
Host smart-6ab74ca7-0d85-4cd4-b71d-78f0a0ea387b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076991842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.4076991842
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.929284458
Short name T394
Test name
Test status
Simulation time 9193744023 ps
CPU time 101.98 seconds
Started May 02 12:53:29 PM PDT 24
Finished May 02 12:55:15 PM PDT 24
Peak memory 218724 kb
Host smart-efeea8dd-0e13-43d6-9cf3-6844b87d9be0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929284458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.929284458
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.150555756
Short name T380
Test name
Test status
Simulation time 183003108 ps
CPU time 8.88 seconds
Started May 02 12:53:38 PM PDT 24
Finished May 02 12:53:52 PM PDT 24
Peak memory 215464 kb
Host smart-c8732521-9533-472e-8323-e2c3b068aded
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150555756 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.150555756
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.291230998
Short name T403
Test name
Test status
Simulation time 1081564289 ps
CPU time 14.91 seconds
Started May 02 12:53:37 PM PDT 24
Finished May 02 12:53:57 PM PDT 24
Peak memory 210480 kb
Host smart-b1602a3c-4409-41bb-a279-49f1a7ded62f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291230998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.291230998
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2715352274
Short name T108
Test name
Test status
Simulation time 17106062973 ps
CPU time 133.96 seconds
Started May 02 12:53:36 PM PDT 24
Finished May 02 12:55:55 PM PDT 24
Peak memory 214024 kb
Host smart-04947230-186b-4219-943a-c1c6d0243699
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715352274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2715352274
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2389678373
Short name T89
Test name
Test status
Simulation time 3123539872 ps
CPU time 29.85 seconds
Started May 02 12:53:38 PM PDT 24
Finished May 02 12:54:13 PM PDT 24
Peak memory 211760 kb
Host smart-07d02a27-3cc1-4773-8a08-9d3481cdc62d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389678373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2389678373
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.517378492
Short name T369
Test name
Test status
Simulation time 2542025036 ps
CPU time 27.23 seconds
Started May 02 12:53:37 PM PDT 24
Finished May 02 12:54:09 PM PDT 24
Peak memory 217736 kb
Host smart-5bc2dd66-5a34-4b59-9bc2-f9fd575ea3c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517378492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.517378492
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1006310856
Short name T373
Test name
Test status
Simulation time 13236454394 ps
CPU time 172.54 seconds
Started May 02 12:53:37 PM PDT 24
Finished May 02 12:56:35 PM PDT 24
Peak memory 213384 kb
Host smart-e2829ce5-6db3-4282-b79c-bd7f0e77d99a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006310856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1006310856
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1060877784
Short name T437
Test name
Test status
Simulation time 29600183793 ps
CPU time 31.22 seconds
Started May 02 12:53:38 PM PDT 24
Finished May 02 12:54:14 PM PDT 24
Peak memory 218824 kb
Host smart-8325eefb-934c-4a42-b5c8-7597c3cfff31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060877784 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1060877784
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1330043486
Short name T100
Test name
Test status
Simulation time 4007821436 ps
CPU time 30.53 seconds
Started May 02 12:53:36 PM PDT 24
Finished May 02 12:54:11 PM PDT 24
Peak memory 211320 kb
Host smart-bdedeb66-add4-4b64-ad6d-107f6d7238ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330043486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1330043486
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1645075513
Short name T81
Test name
Test status
Simulation time 9250948118 ps
CPU time 109.79 seconds
Started May 02 12:53:37 PM PDT 24
Finished May 02 12:55:32 PM PDT 24
Peak memory 214872 kb
Host smart-28e190e4-a684-40a2-b33d-9a2c14ca5447
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645075513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1645075513
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1418043391
Short name T85
Test name
Test status
Simulation time 3292846509 ps
CPU time 31.89 seconds
Started May 02 12:53:36 PM PDT 24
Finished May 02 12:54:13 PM PDT 24
Peak memory 211676 kb
Host smart-2e6a4a98-4ee8-4daa-b3fd-6389b88180ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418043391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1418043391
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2412896018
Short name T393
Test name
Test status
Simulation time 2029537991 ps
CPU time 23.72 seconds
Started May 02 12:53:38 PM PDT 24
Finished May 02 12:54:06 PM PDT 24
Peak memory 217600 kb
Host smart-e7d16c65-019f-4dea-bcf6-8a03d5062bd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412896018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2412896018
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2406810725
Short name T127
Test name
Test status
Simulation time 3406500922 ps
CPU time 94.19 seconds
Started May 02 12:53:36 PM PDT 24
Finished May 02 12:55:16 PM PDT 24
Peak memory 213556 kb
Host smart-83e28a1e-83c1-4c5f-b94e-3a0cc28c40fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406810725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2406810725
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3853318062
Short name T442
Test name
Test status
Simulation time 2926155788 ps
CPU time 24.92 seconds
Started May 02 12:53:36 PM PDT 24
Finished May 02 12:54:05 PM PDT 24
Peak memory 216740 kb
Host smart-676d8b36-0281-4f09-bb29-89cadfcb1e08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853318062 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3853318062
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.978360961
Short name T435
Test name
Test status
Simulation time 2131427960 ps
CPU time 20.9 seconds
Started May 02 12:53:36 PM PDT 24
Finished May 02 12:54:02 PM PDT 24
Peak memory 210612 kb
Host smart-67d3c3e4-23ef-4c0d-a5d0-8f810f0caade
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978360961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.978360961
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.802500180
Short name T372
Test name
Test status
Simulation time 9824679670 ps
CPU time 92.33 seconds
Started May 02 12:53:37 PM PDT 24
Finished May 02 12:55:14 PM PDT 24
Peak memory 213632 kb
Host smart-c5da55c2-d794-48e4-bb7e-ab0ab5849aeb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802500180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.802500180
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3499186103
Short name T428
Test name
Test status
Simulation time 1421740239 ps
CPU time 17.36 seconds
Started May 02 12:53:38 PM PDT 24
Finished May 02 12:54:00 PM PDT 24
Peak memory 211344 kb
Host smart-f55cac92-2d2d-4fde-a36c-42b42ab3b585
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499186103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3499186103
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1734779063
Short name T78
Test name
Test status
Simulation time 688104513 ps
CPU time 13.03 seconds
Started May 02 12:53:38 PM PDT 24
Finished May 02 12:53:56 PM PDT 24
Peak memory 216472 kb
Host smart-2a1bb895-a529-48c3-aa56-a2c884f72a96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734779063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1734779063
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3162099383
Short name T79
Test name
Test status
Simulation time 19767869361 ps
CPU time 170.37 seconds
Started May 02 12:53:38 PM PDT 24
Finished May 02 12:56:33 PM PDT 24
Peak memory 213656 kb
Host smart-d02d68da-a58a-4fc0-aff6-f75ad47028ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162099383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3162099383
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4064815205
Short name T55
Test name
Test status
Simulation time 3519042448 ps
CPU time 27.84 seconds
Started May 02 12:53:34 PM PDT 24
Finished May 02 12:54:07 PM PDT 24
Peak memory 217564 kb
Host smart-48a66229-2055-4cb7-9773-cf7d32ced7d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064815205 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4064815205
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2410431845
Short name T453
Test name
Test status
Simulation time 12360135067 ps
CPU time 25 seconds
Started May 02 12:53:36 PM PDT 24
Finished May 02 12:54:06 PM PDT 24
Peak memory 211532 kb
Host smart-fd404cbc-d26d-45d4-9345-5a076643c08c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410431845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2410431845
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2325237899
Short name T90
Test name
Test status
Simulation time 23882637978 ps
CPU time 187.24 seconds
Started May 02 12:53:37 PM PDT 24
Finished May 02 12:56:49 PM PDT 24
Peak memory 214928 kb
Host smart-2c2da6ee-057f-470f-b563-f7adefcb9689
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325237899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2325237899
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3196552917
Short name T112
Test name
Test status
Simulation time 2545380245 ps
CPU time 23.56 seconds
Started May 02 12:53:37 PM PDT 24
Finished May 02 12:54:05 PM PDT 24
Peak memory 211632 kb
Host smart-43c8f64f-dcce-40ea-8743-4b0c281f52e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196552917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3196552917
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2021803557
Short name T443
Test name
Test status
Simulation time 6828474262 ps
CPU time 30.91 seconds
Started May 02 12:53:37 PM PDT 24
Finished May 02 12:54:13 PM PDT 24
Peak memory 217440 kb
Host smart-63abb23b-332d-4f50-a897-4d4573bfb866
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021803557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2021803557
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.479151759
Short name T58
Test name
Test status
Simulation time 3411585832 ps
CPU time 95.47 seconds
Started May 02 12:53:36 PM PDT 24
Finished May 02 12:55:17 PM PDT 24
Peak memory 213760 kb
Host smart-25afc811-0257-4dde-8db7-8305469252fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479151759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.479151759
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1743571544
Short name T404
Test name
Test status
Simulation time 1800043636 ps
CPU time 18.69 seconds
Started May 02 12:53:44 PM PDT 24
Finished May 02 12:54:06 PM PDT 24
Peak memory 215892 kb
Host smart-0a019507-4f10-4eab-ab46-ae716e6894e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743571544 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1743571544
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2808836714
Short name T379
Test name
Test status
Simulation time 9877778469 ps
CPU time 21.89 seconds
Started May 02 12:53:44 PM PDT 24
Finished May 02 12:54:09 PM PDT 24
Peak memory 211416 kb
Host smart-6917b869-6436-458a-9282-50b0c1c0f618
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808836714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2808836714
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1713927628
Short name T101
Test name
Test status
Simulation time 7231762511 ps
CPU time 78.66 seconds
Started May 02 12:53:35 PM PDT 24
Finished May 02 12:54:59 PM PDT 24
Peak memory 213004 kb
Host smart-60c43ea2-3e58-43dc-a18b-93281d64dda7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713927628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1713927628
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3571771678
Short name T387
Test name
Test status
Simulation time 3380696172 ps
CPU time 27.21 seconds
Started May 02 12:53:42 PM PDT 24
Finished May 02 12:54:12 PM PDT 24
Peak memory 211748 kb
Host smart-6c8fc400-5bce-4b63-b27e-06f71b41265e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571771678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3571771678
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1979670767
Short name T378
Test name
Test status
Simulation time 1318650935 ps
CPU time 15.42 seconds
Started May 02 12:53:44 PM PDT 24
Finished May 02 12:54:03 PM PDT 24
Peak memory 216696 kb
Host smart-0147549c-0fea-4433-9aa2-795a06651e69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979670767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1979670767
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1949382201
Short name T122
Test name
Test status
Simulation time 297494758 ps
CPU time 153.17 seconds
Started May 02 12:53:44 PM PDT 24
Finished May 02 12:56:21 PM PDT 24
Peak memory 213240 kb
Host smart-69dc4b21-a012-47e6-9410-d72f49e3d966
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949382201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1949382201
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.4291957389
Short name T71
Test name
Test status
Simulation time 1538246785 ps
CPU time 13.64 seconds
Started May 02 12:53:51 PM PDT 24
Finished May 02 12:54:09 PM PDT 24
Peak memory 211572 kb
Host smart-b0f9ea1a-4c0e-460e-a44c-5d926a6d45d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291957389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.4291957389
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.413543049
Short name T349
Test name
Test status
Simulation time 121576299883 ps
CPU time 591.13 seconds
Started May 02 12:53:51 PM PDT 24
Finished May 02 01:03:47 PM PDT 24
Peak memory 217172 kb
Host smart-5caf7947-3598-42d9-aba9-64301a965718
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413543049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.413543049
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3025134899
Short name T183
Test name
Test status
Simulation time 16749918397 ps
CPU time 67.1 seconds
Started May 02 12:53:53 PM PDT 24
Finished May 02 12:55:04 PM PDT 24
Peak memory 214256 kb
Host smart-28d89bc5-a02d-4277-8467-96a579a5cef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025134899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3025134899
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.222028033
Short name T269
Test name
Test status
Simulation time 1436696405 ps
CPU time 19.37 seconds
Started May 02 12:53:49 PM PDT 24
Finished May 02 12:54:13 PM PDT 24
Peak memory 211436 kb
Host smart-96a6447d-40e1-4363-a603-d1e0e6ec5dde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=222028033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.222028033
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1042769922
Short name T39
Test name
Test status
Simulation time 5340643926 ps
CPU time 133.32 seconds
Started May 02 12:53:52 PM PDT 24
Finished May 02 12:56:10 PM PDT 24
Peak memory 237976 kb
Host smart-62d4a880-970d-4886-95a0-b3eef68ba757
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042769922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1042769922
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2063025909
Short name T164
Test name
Test status
Simulation time 8317273657 ps
CPU time 57.7 seconds
Started May 02 12:53:50 PM PDT 24
Finished May 02 12:54:52 PM PDT 24
Peak memory 220376 kb
Host smart-bebed0c6-6dbe-405a-8d1d-0bb57fd344bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063025909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2063025909
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1364152889
Short name T348
Test name
Test status
Simulation time 394527287 ps
CPU time 8.47 seconds
Started May 02 12:53:56 PM PDT 24
Finished May 02 12:54:08 PM PDT 24
Peak memory 211576 kb
Host smart-f65ad52b-f310-465c-ba18-b3e262602030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364152889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1364152889
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2329000247
Short name T41
Test name
Test status
Simulation time 199526576548 ps
CPU time 664.72 seconds
Started May 02 12:54:00 PM PDT 24
Finished May 02 01:05:09 PM PDT 24
Peak memory 217248 kb
Host smart-d225ebac-5739-4070-9e11-acd26292aa71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329000247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2329000247
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1188841509
Short name T276
Test name
Test status
Simulation time 13710930835 ps
CPU time 40.47 seconds
Started May 02 12:53:57 PM PDT 24
Finished May 02 12:54:41 PM PDT 24
Peak memory 215288 kb
Host smart-60eb71ea-4496-4f8a-a953-adfbdbdfab5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188841509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1188841509
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3213064278
Short name T221
Test name
Test status
Simulation time 2743061503 ps
CPU time 26.31 seconds
Started May 02 12:53:49 PM PDT 24
Finished May 02 12:54:20 PM PDT 24
Peak memory 211504 kb
Host smart-410af114-e14f-4d8a-9887-9843acb4f71b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3213064278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3213064278
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1109224694
Short name T38
Test name
Test status
Simulation time 4064954940 ps
CPU time 140.44 seconds
Started May 02 12:53:58 PM PDT 24
Finished May 02 12:56:22 PM PDT 24
Peak memory 238652 kb
Host smart-f9aa1024-24ff-4bf9-83f2-ce933e9f16be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109224694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1109224694
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3900287831
Short name T14
Test name
Test status
Simulation time 8097568544 ps
CPU time 45.33 seconds
Started May 02 12:53:52 PM PDT 24
Finished May 02 12:54:42 PM PDT 24
Peak memory 218740 kb
Host smart-0fc7cc86-a7d0-47ee-b73d-fe208ee154ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900287831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3900287831
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2153303549
Short name T293
Test name
Test status
Simulation time 4047468450 ps
CPU time 72.29 seconds
Started May 02 12:53:51 PM PDT 24
Finished May 02 12:55:08 PM PDT 24
Peak memory 219644 kb
Host smart-e8ee71a3-2c87-49d7-80ef-3bf35043aec3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153303549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2153303549
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1391261282
Short name T204
Test name
Test status
Simulation time 167352595 ps
CPU time 8.44 seconds
Started May 02 12:54:10 PM PDT 24
Finished May 02 12:54:21 PM PDT 24
Peak memory 211600 kb
Host smart-34d746ef-981b-4fd4-9021-ebbd2bd7c2f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391261282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1391261282
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.795620272
Short name T329
Test name
Test status
Simulation time 85442161455 ps
CPU time 227.65 seconds
Started May 02 12:54:11 PM PDT 24
Finished May 02 12:58:02 PM PDT 24
Peak memory 215896 kb
Host smart-78b2244b-5eb6-4f3a-b71e-afa5cbcd88b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795620272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.795620272
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1351012383
Short name T239
Test name
Test status
Simulation time 1316395225 ps
CPU time 27.95 seconds
Started May 02 12:54:13 PM PDT 24
Finished May 02 12:54:44 PM PDT 24
Peak memory 214996 kb
Host smart-f638c3ed-ba00-405c-ab5c-cbb152185344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351012383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1351012383
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2691449594
Short name T8
Test name
Test status
Simulation time 1359489658 ps
CPU time 14.69 seconds
Started May 02 12:54:04 PM PDT 24
Finished May 02 12:54:23 PM PDT 24
Peak memory 211516 kb
Host smart-7eb62b0f-7145-4eb7-b4a4-ad905d547418
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2691449594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2691449594
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3409701421
Short name T136
Test name
Test status
Simulation time 2000101624 ps
CPU time 32.85 seconds
Started May 02 12:54:03 PM PDT 24
Finished May 02 12:54:40 PM PDT 24
Peak memory 215544 kb
Host smart-83b22cde-d504-4c29-a661-602e070beada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409701421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3409701421
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.887263213
Short name T224
Test name
Test status
Simulation time 31646284874 ps
CPU time 88.21 seconds
Started May 02 12:54:05 PM PDT 24
Finished May 02 12:55:37 PM PDT 24
Peak memory 221216 kb
Host smart-bc184844-5c77-4883-b16f-cbd5387b6d98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887263213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.887263213
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3364857752
Short name T54
Test name
Test status
Simulation time 84946497907 ps
CPU time 2062.98 seconds
Started May 02 12:54:12 PM PDT 24
Finished May 02 01:28:38 PM PDT 24
Peak memory 244348 kb
Host smart-536ff2cb-9b8a-4725-ad67-0640cb05686a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364857752 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3364857752
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3431040052
Short name T248
Test name
Test status
Simulation time 2413508075 ps
CPU time 11.27 seconds
Started May 02 12:54:12 PM PDT 24
Finished May 02 12:54:26 PM PDT 24
Peak memory 211568 kb
Host smart-f32e8216-80ed-4f5a-8871-5086f12bac0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431040052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3431040052
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2741412
Short name T152
Test name
Test status
Simulation time 103738427928 ps
CPU time 872.83 seconds
Started May 02 12:54:12 PM PDT 24
Finished May 02 01:08:48 PM PDT 24
Peak memory 217868 kb
Host smart-34c72ea6-121b-4859-a0fb-2ccb1ce67323
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_s
ig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_cor
rupt_sig_fatal_chk.2741412
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1425488276
Short name T270
Test name
Test status
Simulation time 1799552163 ps
CPU time 30.39 seconds
Started May 02 12:54:11 PM PDT 24
Finished May 02 12:54:45 PM PDT 24
Peak memory 213196 kb
Host smart-b9cf1ee0-3300-4a6b-bc00-8c87d78e396c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425488276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1425488276
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3340017568
Short name T67
Test name
Test status
Simulation time 765807473 ps
CPU time 10.67 seconds
Started May 02 12:54:13 PM PDT 24
Finished May 02 12:54:26 PM PDT 24
Peak memory 212652 kb
Host smart-f4b0d42f-4e4d-4816-b572-0b767fa98c3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3340017568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3340017568
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3973135712
Short name T319
Test name
Test status
Simulation time 15856600607 ps
CPU time 51.38 seconds
Started May 02 12:54:12 PM PDT 24
Finished May 02 12:55:07 PM PDT 24
Peak memory 217192 kb
Host smart-1c005b5b-ee50-4e52-8ba4-80871f32ff68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973135712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3973135712
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1400107751
Short name T242
Test name
Test status
Simulation time 11529300686 ps
CPU time 85.54 seconds
Started May 02 12:54:10 PM PDT 24
Finished May 02 12:55:38 PM PDT 24
Peak memory 217824 kb
Host smart-74c5e680-b7d7-4fc9-adbb-38d9cc78c037
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400107751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1400107751
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.352690729
Short name T34
Test name
Test status
Simulation time 2797539884 ps
CPU time 25.86 seconds
Started May 02 12:54:11 PM PDT 24
Finished May 02 12:54:40 PM PDT 24
Peak memory 212112 kb
Host smart-4f47ba40-9dff-4ddc-9c2f-699b68a1e9ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352690729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.352690729
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1859497877
Short name T49
Test name
Test status
Simulation time 19589381578 ps
CPU time 318.85 seconds
Started May 02 12:54:13 PM PDT 24
Finished May 02 12:59:34 PM PDT 24
Peak memory 236360 kb
Host smart-5afed27a-08a1-435b-9d42-9f183367429a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859497877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1859497877
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1746579761
Short name T313
Test name
Test status
Simulation time 43492428874 ps
CPU time 36.83 seconds
Started May 02 12:54:11 PM PDT 24
Finished May 02 12:54:51 PM PDT 24
Peak memory 215248 kb
Host smart-b5398a58-e98a-42f9-b04c-fe1af01d768d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746579761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1746579761
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1037162771
Short name T315
Test name
Test status
Simulation time 1954668363 ps
CPU time 21.1 seconds
Started May 02 12:54:10 PM PDT 24
Finished May 02 12:54:35 PM PDT 24
Peak memory 211468 kb
Host smart-5a2d00c3-86ca-44ee-b7fe-fb37b7ce1b75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1037162771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1037162771
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.157851925
Short name T132
Test name
Test status
Simulation time 3477049288 ps
CPU time 25.53 seconds
Started May 02 12:54:10 PM PDT 24
Finished May 02 12:54:39 PM PDT 24
Peak memory 217160 kb
Host smart-dd9fd3aa-f40d-4057-a4e1-3adb9fedcc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157851925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.157851925
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2981072362
Short name T6
Test name
Test status
Simulation time 10927067968 ps
CPU time 61.38 seconds
Started May 02 12:54:11 PM PDT 24
Finished May 02 12:55:16 PM PDT 24
Peak memory 217920 kb
Host smart-5b82b04f-a7c4-4de9-8508-7b4012dae803
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981072362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2981072362
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2357634208
Short name T33
Test name
Test status
Simulation time 1307842418 ps
CPU time 16.33 seconds
Started May 02 12:54:17 PM PDT 24
Finished May 02 12:54:36 PM PDT 24
Peak memory 211540 kb
Host smart-4dd538c2-4589-449f-a49e-33c87d617b39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357634208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2357634208
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3756231291
Short name T130
Test name
Test status
Simulation time 97837876030 ps
CPU time 896.43 seconds
Started May 02 12:54:12 PM PDT 24
Finished May 02 01:09:12 PM PDT 24
Peak memory 240504 kb
Host smart-ee58f77d-796a-4c85-a102-378bf9cfaae2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756231291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3756231291
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2498532869
Short name T131
Test name
Test status
Simulation time 16764352920 ps
CPU time 34.32 seconds
Started May 02 12:54:13 PM PDT 24
Finished May 02 12:54:50 PM PDT 24
Peak memory 212012 kb
Host smart-e2f98c02-4f65-4191-9fbb-d2080b4f06ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2498532869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2498532869
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.427017337
Short name T146
Test name
Test status
Simulation time 31382704005 ps
CPU time 44.44 seconds
Started May 02 12:54:10 PM PDT 24
Finished May 02 12:54:57 PM PDT 24
Peak memory 218284 kb
Host smart-16365d64-e680-45a3-bdd1-dfe1409807f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427017337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.427017337
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1675143984
Short name T355
Test name
Test status
Simulation time 23705531560 ps
CPU time 129.01 seconds
Started May 02 12:54:11 PM PDT 24
Finished May 02 12:56:23 PM PDT 24
Peak memory 219600 kb
Host smart-083707df-9f7b-433c-b8de-2cc162f803fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675143984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1675143984
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3316090721
Short name T208
Test name
Test status
Simulation time 346129061 ps
CPU time 8.69 seconds
Started May 02 12:54:30 PM PDT 24
Finished May 02 12:54:43 PM PDT 24
Peak memory 211580 kb
Host smart-d496d62c-6415-4578-8d95-7c69c955c6d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316090721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3316090721
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2805365249
Short name T342
Test name
Test status
Simulation time 15921921614 ps
CPU time 400.98 seconds
Started May 02 12:54:16 PM PDT 24
Finished May 02 01:00:59 PM PDT 24
Peak memory 238388 kb
Host smart-826b9398-1f2c-4464-90cb-4dd00cfb2f6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805365249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2805365249
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2300836838
Short name T253
Test name
Test status
Simulation time 8691244219 ps
CPU time 68.33 seconds
Started May 02 12:54:16 PM PDT 24
Finished May 02 12:55:26 PM PDT 24
Peak memory 215396 kb
Host smart-11c0e3c3-528c-4f48-96a3-6c79872ed4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300836838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2300836838
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.615269360
Short name T46
Test name
Test status
Simulation time 16056916046 ps
CPU time 29.24 seconds
Started May 02 12:54:25 PM PDT 24
Finished May 02 12:54:57 PM PDT 24
Peak memory 211848 kb
Host smart-40241e0b-4034-4e91-82e9-5c6182042997
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=615269360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.615269360
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3527958989
Short name T159
Test name
Test status
Simulation time 31344066407 ps
CPU time 65.43 seconds
Started May 02 12:54:18 PM PDT 24
Finished May 02 12:55:25 PM PDT 24
Peak memory 218124 kb
Host smart-06b45914-1df3-41e1-a19f-7e2ef3091f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527958989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3527958989
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1528691607
Short name T61
Test name
Test status
Simulation time 1353762303 ps
CPU time 50.3 seconds
Started May 02 12:54:14 PM PDT 24
Finished May 02 12:55:07 PM PDT 24
Peak memory 219492 kb
Host smart-6cfc2d17-f80f-4bea-a5c8-5f2528d67fde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528691607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1528691607
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.668009143
Short name T72
Test name
Test status
Simulation time 7833746747 ps
CPU time 29.63 seconds
Started May 02 12:54:26 PM PDT 24
Finished May 02 12:54:59 PM PDT 24
Peak memory 212328 kb
Host smart-4c1ffd7c-76c8-40b5-a024-596a9c508985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668009143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.668009143
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3281338609
Short name T179
Test name
Test status
Simulation time 61689100552 ps
CPU time 608.28 seconds
Started May 02 12:54:25 PM PDT 24
Finished May 02 01:04:37 PM PDT 24
Peak memory 234084 kb
Host smart-b2da4254-cfc5-430a-b9a6-4eb41fde2bf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281338609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3281338609
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2886545909
Short name T227
Test name
Test status
Simulation time 13836374024 ps
CPU time 28.06 seconds
Started May 02 12:54:17 PM PDT 24
Finished May 02 12:54:48 PM PDT 24
Peak memory 211608 kb
Host smart-20a255d9-37c3-4ea1-8c5e-aa9fe7110d89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2886545909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2886545909
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3895849724
Short name T246
Test name
Test status
Simulation time 19751166455 ps
CPU time 54.28 seconds
Started May 02 12:54:25 PM PDT 24
Finished May 02 12:55:22 PM PDT 24
Peak memory 218396 kb
Host smart-217464bd-3726-4d09-bc52-8d26986f6b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895849724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3895849724
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.67749521
Short name T314
Test name
Test status
Simulation time 1945493099 ps
CPU time 37.2 seconds
Started May 02 12:54:16 PM PDT 24
Finished May 02 12:54:55 PM PDT 24
Peak memory 218316 kb
Host smart-55f52c37-a45c-4cb1-9985-feef85369c4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67749521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 15.rom_ctrl_stress_all.67749521
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3187765287
Short name T53
Test name
Test status
Simulation time 91646217465 ps
CPU time 898.14 seconds
Started May 02 12:54:17 PM PDT 24
Finished May 02 01:09:18 PM PDT 24
Peak memory 233236 kb
Host smart-aa774b06-ad7e-4ee4-9d69-e6deb56e0f6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187765287 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.3187765287
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.730244061
Short name T235
Test name
Test status
Simulation time 661608126 ps
CPU time 8.53 seconds
Started May 02 12:54:16 PM PDT 24
Finished May 02 12:54:27 PM PDT 24
Peak memory 211480 kb
Host smart-8d869ec0-ed19-4442-b3a8-ee0c4b2218c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730244061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.730244061
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1102812974
Short name T28
Test name
Test status
Simulation time 82115765505 ps
CPU time 1007.76 seconds
Started May 02 12:54:21 PM PDT 24
Finished May 02 01:11:11 PM PDT 24
Peak memory 218268 kb
Host smart-0a3afbb8-1c25-478c-96ef-0bbadc7c0719
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102812974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1102812974
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.360564579
Short name T188
Test name
Test status
Simulation time 16673138300 ps
CPU time 67.32 seconds
Started May 02 12:54:21 PM PDT 24
Finished May 02 12:55:31 PM PDT 24
Peak memory 215172 kb
Host smart-3d0924c1-a35f-4d6b-8f82-0b478c3eee19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360564579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.360564579
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2804981159
Short name T288
Test name
Test status
Simulation time 1223123207 ps
CPU time 14.61 seconds
Started May 02 12:54:29 PM PDT 24
Finished May 02 12:54:46 PM PDT 24
Peak memory 211576 kb
Host smart-e9c9c82f-2736-4693-9750-3ed2483a499a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2804981159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2804981159
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.69634258
Short name T75
Test name
Test status
Simulation time 6822951500 ps
CPU time 19.41 seconds
Started May 02 12:54:17 PM PDT 24
Finished May 02 12:54:39 PM PDT 24
Peak memory 217728 kb
Host smart-55599173-1c7a-494b-8cb9-33bc56beb4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69634258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.69634258
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2664508544
Short name T13
Test name
Test status
Simulation time 1093905865 ps
CPU time 36.38 seconds
Started May 02 12:54:16 PM PDT 24
Finished May 02 12:54:55 PM PDT 24
Peak memory 219492 kb
Host smart-df8e1806-6982-435f-96d2-1932111855c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664508544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2664508544
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1877787377
Short name T325
Test name
Test status
Simulation time 167622473 ps
CPU time 8.23 seconds
Started May 02 12:54:28 PM PDT 24
Finished May 02 12:54:40 PM PDT 24
Peak memory 211556 kb
Host smart-4d726952-3962-430c-be22-68a150e4c594
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877787377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1877787377
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.663432321
Short name T229
Test name
Test status
Simulation time 22806039235 ps
CPU time 40.81 seconds
Started May 02 12:54:29 PM PDT 24
Finished May 02 12:55:13 PM PDT 24
Peak memory 218248 kb
Host smart-c33cfbf9-c671-4a91-a91d-bdf7dd5d6fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663432321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.663432321
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.875989822
Short name T352
Test name
Test status
Simulation time 186238716 ps
CPU time 10.37 seconds
Started May 02 12:54:29 PM PDT 24
Finished May 02 12:54:42 PM PDT 24
Peak memory 212756 kb
Host smart-1bf8bbb6-f5a6-494e-a860-386285ca2905
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=875989822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.875989822
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1493842903
Short name T272
Test name
Test status
Simulation time 7595740581 ps
CPU time 58.75 seconds
Started May 02 12:54:20 PM PDT 24
Finished May 02 12:55:22 PM PDT 24
Peak memory 215948 kb
Host smart-c420bb64-e5ce-4e39-843b-3eb8a8162ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493842903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1493842903
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3230082038
Short name T261
Test name
Test status
Simulation time 4359710902 ps
CPU time 39.26 seconds
Started May 02 12:54:24 PM PDT 24
Finished May 02 12:55:06 PM PDT 24
Peak memory 212812 kb
Host smart-4afe2942-2fe2-4c47-b332-b9ae5df3dc88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230082038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3230082038
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.334212769
Short name T310
Test name
Test status
Simulation time 32913067520 ps
CPU time 18.49 seconds
Started May 02 12:54:29 PM PDT 24
Finished May 02 12:54:51 PM PDT 24
Peak memory 211668 kb
Host smart-8ccf152d-ff0c-4d0b-96d5-d549499890c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334212769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.334212769
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2186728656
Short name T328
Test name
Test status
Simulation time 48864615511 ps
CPU time 427.95 seconds
Started May 02 12:54:27 PM PDT 24
Finished May 02 01:01:38 PM PDT 24
Peak memory 229884 kb
Host smart-5be1943f-ff93-4f8d-8413-feb791350cbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186728656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2186728656
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2163776020
Short name T259
Test name
Test status
Simulation time 1375122988 ps
CPU time 19.46 seconds
Started May 02 12:54:29 PM PDT 24
Finished May 02 12:54:51 PM PDT 24
Peak memory 214996 kb
Host smart-ee861513-41be-4cec-95b4-c51f70334e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163776020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2163776020
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2792737570
Short name T17
Test name
Test status
Simulation time 11168840444 ps
CPU time 24.93 seconds
Started May 02 12:54:28 PM PDT 24
Finished May 02 12:54:56 PM PDT 24
Peak memory 211556 kb
Host smart-89a7f3f1-2a7f-4137-9fac-522dad01c73f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2792737570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2792737570
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.544579623
Short name T264
Test name
Test status
Simulation time 7917664448 ps
CPU time 34.21 seconds
Started May 02 12:54:28 PM PDT 24
Finished May 02 12:55:05 PM PDT 24
Peak memory 218352 kb
Host smart-6a8d5552-5c3e-49f5-8a11-f196e8dadd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544579623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.544579623
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2741366411
Short name T198
Test name
Test status
Simulation time 1038912579 ps
CPU time 33.02 seconds
Started May 02 12:54:28 PM PDT 24
Finished May 02 12:55:04 PM PDT 24
Peak memory 219168 kb
Host smart-9a96083c-e76a-447c-b21f-7be78588b12c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741366411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2741366411
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1944046172
Short name T73
Test name
Test status
Simulation time 9203926463 ps
CPU time 22.32 seconds
Started May 02 12:54:43 PM PDT 24
Finished May 02 12:55:09 PM PDT 24
Peak memory 211604 kb
Host smart-d33f2dd5-c146-47e0-be1a-d0b7efa4ab3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944046172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1944046172
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.773832886
Short name T50
Test name
Test status
Simulation time 352245631963 ps
CPU time 835.14 seconds
Started May 02 12:54:29 PM PDT 24
Finished May 02 01:08:28 PM PDT 24
Peak memory 234084 kb
Host smart-7f67d7f1-8caf-4ada-8006-1fb17c06e30d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773832886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.773832886
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3131370055
Short name T181
Test name
Test status
Simulation time 10937354877 ps
CPU time 34.19 seconds
Started May 02 12:54:31 PM PDT 24
Finished May 02 12:55:09 PM PDT 24
Peak memory 215692 kb
Host smart-9a83f9ca-c843-448d-9480-109b420f29d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131370055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3131370055
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3937221502
Short name T37
Test name
Test status
Simulation time 3809730148 ps
CPU time 16.19 seconds
Started May 02 12:54:29 PM PDT 24
Finished May 02 12:54:49 PM PDT 24
Peak memory 212884 kb
Host smart-7fa27998-bc76-44f2-8428-dbcf675647b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3937221502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3937221502
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1094127154
Short name T339
Test name
Test status
Simulation time 2787075354 ps
CPU time 42.11 seconds
Started May 02 12:54:28 PM PDT 24
Finished May 02 12:55:13 PM PDT 24
Peak memory 217316 kb
Host smart-d62f1d4a-11bb-4800-9440-b31e78bd1435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094127154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1094127154
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.276679287
Short name T252
Test name
Test status
Simulation time 39066362183 ps
CPU time 132.28 seconds
Started May 02 12:54:29 PM PDT 24
Finished May 02 12:56:44 PM PDT 24
Peak memory 219656 kb
Host smart-f8f22395-0ae5-41d8-a377-a396c9785f84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276679287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.276679287
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.196019953
Short name T178
Test name
Test status
Simulation time 4647899320 ps
CPU time 15 seconds
Started May 02 12:53:57 PM PDT 24
Finished May 02 12:54:16 PM PDT 24
Peak memory 211628 kb
Host smart-1e51ef2d-82b9-431e-8ab1-4a9d1a943142
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196019953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.196019953
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2995259197
Short name T68
Test name
Test status
Simulation time 273662108744 ps
CPU time 1283.76 seconds
Started May 02 12:53:59 PM PDT 24
Finished May 02 01:15:27 PM PDT 24
Peak memory 234244 kb
Host smart-49d2d054-557b-4ec6-b92b-b32ac6a24abc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995259197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2995259197
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.162835682
Short name T23
Test name
Test status
Simulation time 689917991 ps
CPU time 18.78 seconds
Started May 02 12:53:57 PM PDT 24
Finished May 02 12:54:19 PM PDT 24
Peak memory 215164 kb
Host smart-e2f5c7db-52ec-4d0d-9b8f-1128154eef6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162835682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.162835682
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2986790100
Short name T194
Test name
Test status
Simulation time 6431950723 ps
CPU time 32.51 seconds
Started May 02 12:53:56 PM PDT 24
Finished May 02 12:54:33 PM PDT 24
Peak memory 211576 kb
Host smart-04591b27-4764-40b3-9807-fb89357ac44e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2986790100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2986790100
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.745128474
Short name T31
Test name
Test status
Simulation time 826901695 ps
CPU time 122.98 seconds
Started May 02 12:53:57 PM PDT 24
Finished May 02 12:56:04 PM PDT 24
Peak memory 236940 kb
Host smart-21dbc705-8d1d-42cc-b3f7-88d741432ebd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745128474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.745128474
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1048760653
Short name T150
Test name
Test status
Simulation time 2923163350 ps
CPU time 39.9 seconds
Started May 02 12:54:00 PM PDT 24
Finished May 02 12:54:43 PM PDT 24
Peak memory 216764 kb
Host smart-7fb1b665-229d-4bcf-803b-35dd2dd34d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048760653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1048760653
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.949318440
Short name T47
Test name
Test status
Simulation time 345886378 ps
CPU time 8.35 seconds
Started May 02 12:54:37 PM PDT 24
Finished May 02 12:54:48 PM PDT 24
Peak memory 211608 kb
Host smart-a6d3553b-84d4-420c-ab95-febf939de8f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949318440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.949318440
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.715008308
Short name T341
Test name
Test status
Simulation time 68574596258 ps
CPU time 699.03 seconds
Started May 02 12:54:36 PM PDT 24
Finished May 02 01:06:18 PM PDT 24
Peak memory 234012 kb
Host smart-d00edc40-2d5f-4af3-a030-4326303c6d7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715008308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.715008308
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3221400969
Short name T251
Test name
Test status
Simulation time 1508375251 ps
CPU time 29.75 seconds
Started May 02 12:54:38 PM PDT 24
Finished May 02 12:55:12 PM PDT 24
Peak memory 214940 kb
Host smart-80ec1b16-34f1-40ee-9676-3a278a3ddf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221400969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3221400969
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2113334074
Short name T143
Test name
Test status
Simulation time 5978279746 ps
CPU time 31.21 seconds
Started May 02 12:54:36 PM PDT 24
Finished May 02 12:55:10 PM PDT 24
Peak memory 213188 kb
Host smart-6f48bc01-80ed-4dc4-a742-e6889e34a909
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2113334074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2113334074
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2865800012
Short name T332
Test name
Test status
Simulation time 16668695981 ps
CPU time 74.9 seconds
Started May 02 12:54:38 PM PDT 24
Finished May 02 12:55:56 PM PDT 24
Peak memory 218656 kb
Host smart-0ab5b709-2da4-4645-8d7d-1b90b9fbd181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865800012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2865800012
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2059775576
Short name T94
Test name
Test status
Simulation time 747816782 ps
CPU time 28.07 seconds
Started May 02 12:54:36 PM PDT 24
Finished May 02 12:55:07 PM PDT 24
Peak memory 217688 kb
Host smart-c0a12b37-a875-44df-bba6-74b3c7998426
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059775576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2059775576
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.460806537
Short name T353
Test name
Test status
Simulation time 2569869681 ps
CPU time 23.87 seconds
Started May 02 12:54:36 PM PDT 24
Finished May 02 12:55:03 PM PDT 24
Peak memory 212096 kb
Host smart-2ac08233-8dd7-4f1b-8f8f-6870e4fcadb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460806537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.460806537
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1331249165
Short name T322
Test name
Test status
Simulation time 32339737878 ps
CPU time 360.99 seconds
Started May 02 12:54:37 PM PDT 24
Finished May 02 01:00:41 PM PDT 24
Peak memory 234196 kb
Host smart-b64cbd80-727c-4a48-86e2-64eef76d51ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331249165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1331249165
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3790190813
Short name T186
Test name
Test status
Simulation time 848896108 ps
CPU time 25.44 seconds
Started May 02 12:54:40 PM PDT 24
Finished May 02 12:55:09 PM PDT 24
Peak memory 214924 kb
Host smart-507c1099-e895-4868-ab1a-4c2da3a563b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790190813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3790190813
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.137589229
Short name T182
Test name
Test status
Simulation time 8258484967 ps
CPU time 22.24 seconds
Started May 02 12:54:37 PM PDT 24
Finished May 02 12:55:02 PM PDT 24
Peak memory 213020 kb
Host smart-6cad000b-b609-4aa9-8208-9a5d6ca6f2e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=137589229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.137589229
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.264458561
Short name T216
Test name
Test status
Simulation time 353048892 ps
CPU time 20.85 seconds
Started May 02 12:54:36 PM PDT 24
Finished May 02 12:55:00 PM PDT 24
Peak memory 216656 kb
Host smart-f3c50994-5295-465c-b195-029320f32b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264458561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.264458561
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2610602591
Short name T303
Test name
Test status
Simulation time 6874219784 ps
CPU time 50.11 seconds
Started May 02 12:54:36 PM PDT 24
Finished May 02 12:55:29 PM PDT 24
Peak memory 220312 kb
Host smart-9732e758-6892-4ee4-a6b8-e84458fae913
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610602591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2610602591
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3641919291
Short name T36
Test name
Test status
Simulation time 178264757 ps
CPU time 8.14 seconds
Started May 02 12:54:41 PM PDT 24
Finished May 02 12:54:52 PM PDT 24
Peak memory 211480 kb
Host smart-dd2b197c-0f1e-401f-9a82-74af1f890994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641919291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3641919291
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3138263002
Short name T60
Test name
Test status
Simulation time 52039472402 ps
CPU time 218.81 seconds
Started May 02 12:54:42 PM PDT 24
Finished May 02 12:58:25 PM PDT 24
Peak memory 240348 kb
Host smart-a1cac3e4-fb79-44af-a8d5-f02e71ccc6bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138263002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3138263002
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.602958339
Short name T184
Test name
Test status
Simulation time 36947033816 ps
CPU time 37.28 seconds
Started May 02 12:54:39 PM PDT 24
Finished May 02 12:55:20 PM PDT 24
Peak memory 215444 kb
Host smart-98e82218-8462-4008-859c-848b23b74654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602958339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.602958339
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3927137875
Short name T305
Test name
Test status
Simulation time 6182185408 ps
CPU time 19.68 seconds
Started May 02 12:54:38 PM PDT 24
Finished May 02 12:55:01 PM PDT 24
Peak memory 211688 kb
Host smart-3e46656b-92d4-448b-a3ae-ca246d8f2ce7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927137875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3927137875
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1668405008
Short name T233
Test name
Test status
Simulation time 8272596056 ps
CPU time 63.06 seconds
Started May 02 12:54:40 PM PDT 24
Finished May 02 12:55:47 PM PDT 24
Peak memory 217212 kb
Host smart-80d91287-5108-4559-9a13-1dba6973cb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668405008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1668405008
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.390269687
Short name T162
Test name
Test status
Simulation time 34532892514 ps
CPU time 89.65 seconds
Started May 02 12:54:35 PM PDT 24
Finished May 02 12:56:08 PM PDT 24
Peak memory 219896 kb
Host smart-16f53a52-ce89-4bb5-8d49-0fd949cbd03f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390269687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.390269687
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1994757849
Short name T211
Test name
Test status
Simulation time 5102097611 ps
CPU time 14.09 seconds
Started May 02 12:54:42 PM PDT 24
Finished May 02 12:55:00 PM PDT 24
Peak memory 211640 kb
Host smart-a97a3ec8-4bdb-43da-ac96-7593f8a9c91a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994757849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1994757849
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1240204638
Short name T247
Test name
Test status
Simulation time 2266531008 ps
CPU time 191.56 seconds
Started May 02 12:54:42 PM PDT 24
Finished May 02 12:57:57 PM PDT 24
Peak memory 238112 kb
Host smart-ab0db4c5-1d04-4ef6-8664-826a80a8b225
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240204638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1240204638
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.647002760
Short name T27
Test name
Test status
Simulation time 21907855000 ps
CPU time 51.16 seconds
Started May 02 12:54:41 PM PDT 24
Finished May 02 12:55:35 PM PDT 24
Peak memory 214168 kb
Host smart-7cdd55dc-bed0-4cd1-b75e-2a9e0ca9e364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647002760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.647002760
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2501049101
Short name T324
Test name
Test status
Simulation time 1505353461 ps
CPU time 15.19 seconds
Started May 02 12:54:41 PM PDT 24
Finished May 02 12:54:59 PM PDT 24
Peak memory 212384 kb
Host smart-7f7d784e-8754-4da0-9078-1ad9f64d800b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2501049101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2501049101
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3616267425
Short name T334
Test name
Test status
Simulation time 6730410338 ps
CPU time 58.35 seconds
Started May 02 12:54:37 PM PDT 24
Finished May 02 12:55:39 PM PDT 24
Peak memory 217060 kb
Host smart-1f33f735-afdd-4e56-a760-20a2905ddf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616267425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3616267425
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2768664005
Short name T25
Test name
Test status
Simulation time 26218449484 ps
CPU time 229.65 seconds
Started May 02 12:54:36 PM PDT 24
Finished May 02 12:58:29 PM PDT 24
Peak memory 221452 kb
Host smart-8a67f643-3891-4b24-99d0-a130bd334f36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768664005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2768664005
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3792193936
Short name T345
Test name
Test status
Simulation time 14095577834 ps
CPU time 22.13 seconds
Started May 02 12:54:39 PM PDT 24
Finished May 02 12:55:04 PM PDT 24
Peak memory 212464 kb
Host smart-81bc2fd8-98b0-4302-ba13-defab24c2a57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792193936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3792193936
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1250816535
Short name T286
Test name
Test status
Simulation time 4892480431 ps
CPU time 35.3 seconds
Started May 02 12:54:45 PM PDT 24
Finished May 02 12:55:25 PM PDT 24
Peak memory 215328 kb
Host smart-0b3b1440-3d85-4372-9480-a30f2f825d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250816535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1250816535
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.758276105
Short name T205
Test name
Test status
Simulation time 9189658041 ps
CPU time 23.96 seconds
Started May 02 12:54:42 PM PDT 24
Finished May 02 12:55:09 PM PDT 24
Peak memory 212968 kb
Host smart-9e8e4fb7-c378-4feb-bf0d-e658bcadf08c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=758276105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.758276105
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.153293177
Short name T163
Test name
Test status
Simulation time 11580658910 ps
CPU time 37.81 seconds
Started May 02 12:54:41 PM PDT 24
Finished May 02 12:55:23 PM PDT 24
Peak memory 216664 kb
Host smart-645269f8-0b08-40bd-b211-03f795ed91cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153293177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.153293177
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.350710777
Short name T306
Test name
Test status
Simulation time 16486705454 ps
CPU time 42.67 seconds
Started May 02 12:54:41 PM PDT 24
Finished May 02 12:55:28 PM PDT 24
Peak memory 218384 kb
Host smart-e111c88b-886f-4a0d-bd34-bdc6694ac12f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350710777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.350710777
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3826103357
Short name T74
Test name
Test status
Simulation time 4251194885 ps
CPU time 32.17 seconds
Started May 02 12:54:42 PM PDT 24
Finished May 02 12:55:19 PM PDT 24
Peak memory 212152 kb
Host smart-646dac9e-b8a4-4ce9-81a6-182ba69cef6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826103357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3826103357
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1296877679
Short name T296
Test name
Test status
Simulation time 430779388314 ps
CPU time 563.44 seconds
Started May 02 12:54:42 PM PDT 24
Finished May 02 01:04:09 PM PDT 24
Peak memory 230056 kb
Host smart-02d4a251-5e0f-40a1-adfa-4f58a7fbf534
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296877679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1296877679
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3920731854
Short name T169
Test name
Test status
Simulation time 4245055272 ps
CPU time 29.62 seconds
Started May 02 12:54:42 PM PDT 24
Finished May 02 12:55:16 PM PDT 24
Peak memory 215024 kb
Host smart-9105ad19-c773-4186-b912-427676a4bbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920731854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3920731854
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3824302054
Short name T207
Test name
Test status
Simulation time 186306388 ps
CPU time 10.21 seconds
Started May 02 12:54:40 PM PDT 24
Finished May 02 12:54:53 PM PDT 24
Peak memory 212908 kb
Host smart-5b372d68-85ae-4d60-88bf-7ab07f35f248
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3824302054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3824302054
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2153970826
Short name T302
Test name
Test status
Simulation time 352314715 ps
CPU time 20.13 seconds
Started May 02 12:54:39 PM PDT 24
Finished May 02 12:55:02 PM PDT 24
Peak memory 216780 kb
Host smart-15fd6422-69d3-4955-b551-db82cef90027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153970826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2153970826
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2168818250
Short name T155
Test name
Test status
Simulation time 2788383101 ps
CPU time 42.37 seconds
Started May 02 12:54:41 PM PDT 24
Finished May 02 12:55:26 PM PDT 24
Peak memory 220976 kb
Host smart-eb6f2a03-01e4-4b37-be3f-34994bbc7629
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168818250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2168818250
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.552848895
Short name T280
Test name
Test status
Simulation time 7751644052 ps
CPU time 31.91 seconds
Started May 02 12:54:42 PM PDT 24
Finished May 02 12:55:18 PM PDT 24
Peak memory 211636 kb
Host smart-9adebeaf-a72f-4f92-87cb-e6a5af0e6647
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552848895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.552848895
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1305884444
Short name T168
Test name
Test status
Simulation time 175062055822 ps
CPU time 556.4 seconds
Started May 02 12:54:43 PM PDT 24
Finished May 02 01:04:04 PM PDT 24
Peak memory 217952 kb
Host smart-dde4adfb-7156-4aa9-b3b2-233489a27660
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305884444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1305884444
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1397071586
Short name T176
Test name
Test status
Simulation time 1318954552 ps
CPU time 19.72 seconds
Started May 02 12:54:37 PM PDT 24
Finished May 02 12:55:01 PM PDT 24
Peak memory 214880 kb
Host smart-c0ba28a1-e3d4-41c1-94b7-0635ced7cdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397071586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1397071586
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3594622492
Short name T260
Test name
Test status
Simulation time 1262022052 ps
CPU time 13.02 seconds
Started May 02 12:54:38 PM PDT 24
Finished May 02 12:54:54 PM PDT 24
Peak memory 211564 kb
Host smart-f0fe5538-3ee8-46cd-8fb0-2237d49ea914
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3594622492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3594622492
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.138017485
Short name T312
Test name
Test status
Simulation time 69973685496 ps
CPU time 74.34 seconds
Started May 02 12:54:40 PM PDT 24
Finished May 02 12:55:58 PM PDT 24
Peak memory 215684 kb
Host smart-8a832be2-883a-40a2-af97-b17b5f837a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138017485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.138017485
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1937825939
Short name T245
Test name
Test status
Simulation time 25121647106 ps
CPU time 110.86 seconds
Started May 02 12:54:41 PM PDT 24
Finished May 02 12:56:36 PM PDT 24
Peak memory 219104 kb
Host smart-e05e85f6-3c99-4b21-b497-151d0d800c9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937825939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1937825939
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2364154038
Short name T22
Test name
Test status
Simulation time 245434597893 ps
CPU time 2390.84 seconds
Started May 02 12:54:45 PM PDT 24
Finished May 02 01:34:41 PM PDT 24
Peak memory 252496 kb
Host smart-a559f937-91f0-468c-9272-d8e756d91cae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364154038 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.2364154038
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.34806196
Short name T65
Test name
Test status
Simulation time 2745529343 ps
CPU time 12.69 seconds
Started May 02 12:54:46 PM PDT 24
Finished May 02 12:55:03 PM PDT 24
Peak memory 211604 kb
Host smart-1ce50dca-440f-48f3-9aac-4991dac3dc8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34806196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.34806196
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4207899215
Short name T358
Test name
Test status
Simulation time 49352401670 ps
CPU time 473.79 seconds
Started May 02 12:54:36 PM PDT 24
Finished May 02 01:02:33 PM PDT 24
Peak memory 218072 kb
Host smart-357b2ac4-0323-4bb6-b1b4-0d806c526b59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207899215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.4207899215
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3208297985
Short name T275
Test name
Test status
Simulation time 2125898520 ps
CPU time 32.79 seconds
Started May 02 12:54:45 PM PDT 24
Finished May 02 12:55:22 PM PDT 24
Peak memory 215100 kb
Host smart-a562ff6f-9823-4cbe-8ef0-3b84fdbb1c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208297985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3208297985
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4153016486
Short name T62
Test name
Test status
Simulation time 2864134999 ps
CPU time 25.66 seconds
Started May 02 12:54:42 PM PDT 24
Finished May 02 12:55:11 PM PDT 24
Peak memory 212516 kb
Host smart-47e07af3-f7ff-44e1-9d57-fa57e5dd896b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4153016486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4153016486
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1439300788
Short name T153
Test name
Test status
Simulation time 3503883915 ps
CPU time 29.27 seconds
Started May 02 12:54:43 PM PDT 24
Finished May 02 12:55:16 PM PDT 24
Peak memory 217612 kb
Host smart-f4625d30-d667-40ad-a90b-381d27340c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439300788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1439300788
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2050862908
Short name T298
Test name
Test status
Simulation time 14616391070 ps
CPU time 34.92 seconds
Started May 02 12:54:43 PM PDT 24
Finished May 02 12:55:22 PM PDT 24
Peak memory 211992 kb
Host smart-7b42c995-5d35-432e-80ad-797df15f7c3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050862908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2050862908
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2993963673
Short name T70
Test name
Test status
Simulation time 35144207965 ps
CPU time 33.12 seconds
Started May 02 12:54:44 PM PDT 24
Finished May 02 12:55:22 PM PDT 24
Peak memory 211660 kb
Host smart-642c05ff-bf3c-403e-a8b0-60e90b930241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993963673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2993963673
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1963090336
Short name T160
Test name
Test status
Simulation time 26468640857 ps
CPU time 379.56 seconds
Started May 02 12:54:45 PM PDT 24
Finished May 02 01:01:09 PM PDT 24
Peak memory 240220 kb
Host smart-0b77a6ee-25d0-44d3-a8a4-efad19bb9d36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963090336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1963090336
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2069316537
Short name T24
Test name
Test status
Simulation time 1498526042 ps
CPU time 18.72 seconds
Started May 02 12:54:49 PM PDT 24
Finished May 02 12:55:12 PM PDT 24
Peak memory 214924 kb
Host smart-c6b169dd-a1cd-44bf-95e7-6cfeffca583c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069316537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2069316537
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1620192256
Short name T289
Test name
Test status
Simulation time 366630837 ps
CPU time 10.5 seconds
Started May 02 12:54:49 PM PDT 24
Finished May 02 12:55:03 PM PDT 24
Peak memory 212456 kb
Host smart-bd00d5ed-33c7-4c5e-a949-11a843a9ad37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1620192256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1620192256
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.4022066329
Short name T16
Test name
Test status
Simulation time 59505036953 ps
CPU time 65.28 seconds
Started May 02 12:54:43 PM PDT 24
Finished May 02 12:55:52 PM PDT 24
Peak memory 218152 kb
Host smart-0b06514c-445a-49d5-b8f5-ed76e333fbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022066329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.4022066329
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1884292952
Short name T240
Test name
Test status
Simulation time 7558833992 ps
CPU time 20.35 seconds
Started May 02 12:54:44 PM PDT 24
Finished May 02 12:55:09 PM PDT 24
Peak memory 211636 kb
Host smart-b2a0b8bd-13d7-4475-bd71-7a4d63716cbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884292952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1884292952
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2153938581
Short name T254
Test name
Test status
Simulation time 45283805237 ps
CPU time 467.52 seconds
Started May 02 12:54:43 PM PDT 24
Finished May 02 01:02:34 PM PDT 24
Peak memory 240796 kb
Host smart-0bc1f091-e0f8-4501-96f9-f0cf103946d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153938581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2153938581
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2169612680
Short name T193
Test name
Test status
Simulation time 25134534217 ps
CPU time 61.98 seconds
Started May 02 12:54:45 PM PDT 24
Finished May 02 12:55:51 PM PDT 24
Peak memory 215204 kb
Host smart-82938ee3-3e3f-4610-ab12-d222e18bb902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169612680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2169612680
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3133512839
Short name T133
Test name
Test status
Simulation time 731759179 ps
CPU time 10.24 seconds
Started May 02 12:54:49 PM PDT 24
Finished May 02 12:55:03 PM PDT 24
Peak memory 212728 kb
Host smart-fa8ac2d7-e156-4c24-a001-0f60c3b0a4dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3133512839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3133512839
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3049015176
Short name T137
Test name
Test status
Simulation time 5478848137 ps
CPU time 54.18 seconds
Started May 02 12:54:45 PM PDT 24
Finished May 02 12:55:43 PM PDT 24
Peak memory 218396 kb
Host smart-41af150b-dd33-4f05-be6f-20b81f12a028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049015176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3049015176
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1718357452
Short name T63
Test name
Test status
Simulation time 18464924989 ps
CPU time 59.61 seconds
Started May 02 12:54:44 PM PDT 24
Finished May 02 12:55:49 PM PDT 24
Peak memory 218820 kb
Host smart-054b324f-7d45-43d2-aa53-60938d6523b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718357452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1718357452
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1768280291
Short name T187
Test name
Test status
Simulation time 23520810695 ps
CPU time 27.46 seconds
Started May 02 12:53:56 PM PDT 24
Finished May 02 12:54:27 PM PDT 24
Peak memory 212352 kb
Host smart-bad4841a-cedf-4645-8f73-4541e5fb2a38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768280291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1768280291
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3580671437
Short name T161
Test name
Test status
Simulation time 55247883797 ps
CPU time 520.48 seconds
Started May 02 12:53:56 PM PDT 24
Finished May 02 01:02:41 PM PDT 24
Peak memory 237516 kb
Host smart-712babd1-1228-4f1b-836f-845174cbdbe9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580671437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3580671437
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4083374798
Short name T44
Test name
Test status
Simulation time 5334955261 ps
CPU time 37.62 seconds
Started May 02 12:53:57 PM PDT 24
Finished May 02 12:54:39 PM PDT 24
Peak memory 215312 kb
Host smart-3426f5ab-17b5-497f-af5a-22f5c6f4527c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083374798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4083374798
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.148210513
Short name T48
Test name
Test status
Simulation time 753442583 ps
CPU time 10.37 seconds
Started May 02 12:53:57 PM PDT 24
Finished May 02 12:54:12 PM PDT 24
Peak memory 212744 kb
Host smart-101e3ff4-a44c-4c0b-ae86-f16605ac67aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=148210513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.148210513
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1031597171
Short name T166
Test name
Test status
Simulation time 66976906387 ps
CPU time 63.87 seconds
Started May 02 12:53:56 PM PDT 24
Finished May 02 12:55:03 PM PDT 24
Peak memory 216120 kb
Host smart-f64522d9-6e1c-443f-846b-1441cc90351e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031597171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1031597171
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3369352940
Short name T2
Test name
Test status
Simulation time 4330796667 ps
CPU time 20.59 seconds
Started May 02 12:53:59 PM PDT 24
Finished May 02 12:54:24 PM PDT 24
Peak memory 213104 kb
Host smart-2e6c254a-b2e7-46d6-8c79-6f5e32cafb13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369352940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3369352940
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2454606848
Short name T351
Test name
Test status
Simulation time 5166018068 ps
CPU time 23.41 seconds
Started May 02 12:54:43 PM PDT 24
Finished May 02 12:55:10 PM PDT 24
Peak memory 212448 kb
Host smart-e1d4a307-0a40-4246-936c-a451d1611976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454606848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2454606848
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.4172257442
Short name T244
Test name
Test status
Simulation time 16902465821 ps
CPU time 246.48 seconds
Started May 02 12:54:52 PM PDT 24
Finished May 02 12:59:03 PM PDT 24
Peak memory 240380 kb
Host smart-c9a68ac2-4906-4213-8ec5-6f5879d7cb79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172257442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.4172257442
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.507531221
Short name T265
Test name
Test status
Simulation time 19368304499 ps
CPU time 50.31 seconds
Started May 02 12:54:44 PM PDT 24
Finished May 02 12:55:38 PM PDT 24
Peak memory 215928 kb
Host smart-40ccb1f6-ffa2-4fdf-85ce-047e49c0597d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507531221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.507531221
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.113840283
Short name T295
Test name
Test status
Simulation time 1021165868 ps
CPU time 16.89 seconds
Started May 02 12:54:44 PM PDT 24
Finished May 02 12:55:05 PM PDT 24
Peak memory 211556 kb
Host smart-dc693be3-4427-4607-b22a-c8d5394b9404
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=113840283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.113840283
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2320415932
Short name T220
Test name
Test status
Simulation time 6717770976 ps
CPU time 64.98 seconds
Started May 02 12:54:45 PM PDT 24
Finished May 02 12:55:54 PM PDT 24
Peak memory 218208 kb
Host smart-b22fbf00-c4dc-4a7b-8037-31996312811a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320415932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2320415932
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1152913879
Short name T346
Test name
Test status
Simulation time 3277778086 ps
CPU time 27.49 seconds
Started May 02 12:54:57 PM PDT 24
Finished May 02 12:55:27 PM PDT 24
Peak memory 211552 kb
Host smart-c55f3751-88b0-4f40-af9a-a955f2858e9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152913879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1152913879
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.424424376
Short name T180
Test name
Test status
Simulation time 2992593693 ps
CPU time 225.23 seconds
Started May 02 12:54:45 PM PDT 24
Finished May 02 12:58:35 PM PDT 24
Peak memory 239096 kb
Host smart-4d34adf2-56d9-4df8-8dfe-0c1b0ce4d6fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424424376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.424424376
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2438386913
Short name T170
Test name
Test status
Simulation time 8927284265 ps
CPU time 32.43 seconds
Started May 02 12:54:56 PM PDT 24
Finished May 02 12:55:31 PM PDT 24
Peak memory 214116 kb
Host smart-c3334208-1677-4f63-b7f8-af92684da400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438386913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2438386913
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1518077406
Short name T191
Test name
Test status
Simulation time 6482912149 ps
CPU time 20.22 seconds
Started May 02 12:54:51 PM PDT 24
Finished May 02 12:55:14 PM PDT 24
Peak memory 213032 kb
Host smart-5a439490-a41e-4ff0-896b-aa85832277be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1518077406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1518077406
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.259671777
Short name T219
Test name
Test status
Simulation time 15123315733 ps
CPU time 46.52 seconds
Started May 02 12:54:45 PM PDT 24
Finished May 02 12:55:36 PM PDT 24
Peak memory 217992 kb
Host smart-b2fc5569-bbc7-4ea1-824c-0542388e9476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259671777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.259671777
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1733240936
Short name T148
Test name
Test status
Simulation time 23052665449 ps
CPU time 99.24 seconds
Started May 02 12:54:43 PM PDT 24
Finished May 02 12:56:27 PM PDT 24
Peak memory 221484 kb
Host smart-d3f95c4f-23e0-42b8-9067-aea5fdaa5588
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733240936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1733240936
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.4234737426
Short name T354
Test name
Test status
Simulation time 5907682829 ps
CPU time 24.62 seconds
Started May 02 12:54:52 PM PDT 24
Finished May 02 12:55:20 PM PDT 24
Peak memory 211640 kb
Host smart-f4c1eb91-3ff9-4ebc-ad2c-32669871b13c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234737426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.4234737426
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2785011776
Short name T129
Test name
Test status
Simulation time 23884134657 ps
CPU time 268.95 seconds
Started May 02 12:54:51 PM PDT 24
Finished May 02 12:59:24 PM PDT 24
Peak memory 228932 kb
Host smart-87c69fa9-a1bb-4570-96c9-64125187edb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785011776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2785011776
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3334803462
Short name T263
Test name
Test status
Simulation time 2846956389 ps
CPU time 36.21 seconds
Started May 02 12:54:52 PM PDT 24
Finished May 02 12:55:32 PM PDT 24
Peak memory 215228 kb
Host smart-4de4425f-061d-4059-87a7-4c9fd3712990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334803462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3334803462
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.4251010061
Short name T175
Test name
Test status
Simulation time 2022358216 ps
CPU time 32.07 seconds
Started May 02 12:54:56 PM PDT 24
Finished May 02 12:55:31 PM PDT 24
Peak memory 216708 kb
Host smart-0b732ccc-8fb5-4fc5-95cd-7ad637f82a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251010061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.4251010061
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1915373564
Short name T156
Test name
Test status
Simulation time 272966716 ps
CPU time 11.58 seconds
Started May 02 12:54:52 PM PDT 24
Finished May 02 12:55:07 PM PDT 24
Peak memory 213968 kb
Host smart-8afc56da-6660-46ae-9dce-15308bcba7cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915373564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1915373564
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1429002474
Short name T35
Test name
Test status
Simulation time 176216686 ps
CPU time 8.52 seconds
Started May 02 12:54:53 PM PDT 24
Finished May 02 12:55:05 PM PDT 24
Peak memory 211476 kb
Host smart-66abe8ba-907f-4e12-a884-8a8c783e89f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429002474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1429002474
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3983346790
Short name T144
Test name
Test status
Simulation time 246602197786 ps
CPU time 627.42 seconds
Started May 02 12:54:51 PM PDT 24
Finished May 02 01:05:23 PM PDT 24
Peak memory 225684 kb
Host smart-b05d0555-9c95-4475-9598-028bf425aeef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983346790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3983346790
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.349302636
Short name T274
Test name
Test status
Simulation time 997060564 ps
CPU time 26.25 seconds
Started May 02 12:54:52 PM PDT 24
Finished May 02 12:55:22 PM PDT 24
Peak memory 214960 kb
Host smart-90ed59ef-70f1-45f2-9431-108abab5d509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349302636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.349302636
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3648081671
Short name T241
Test name
Test status
Simulation time 367937425 ps
CPU time 10.1 seconds
Started May 02 12:54:51 PM PDT 24
Finished May 02 12:55:05 PM PDT 24
Peak memory 212352 kb
Host smart-43fafb03-3e08-41de-9107-858e8f0b2473
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3648081671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3648081671
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1452808877
Short name T255
Test name
Test status
Simulation time 345663619 ps
CPU time 20.85 seconds
Started May 02 12:54:54 PM PDT 24
Finished May 02 12:55:19 PM PDT 24
Peak memory 216060 kb
Host smart-751904c3-d09b-4726-8642-e526be872076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452808877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1452808877
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2388847733
Short name T95
Test name
Test status
Simulation time 9652445781 ps
CPU time 149.04 seconds
Started May 02 12:54:57 PM PDT 24
Finished May 02 12:57:29 PM PDT 24
Peak memory 222160 kb
Host smart-10421085-debe-4e3d-8f14-8f0dbdb4666b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388847733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2388847733
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1776887915
Short name T321
Test name
Test status
Simulation time 339147795 ps
CPU time 8.28 seconds
Started May 02 12:54:50 PM PDT 24
Finished May 02 12:55:02 PM PDT 24
Peak memory 211560 kb
Host smart-ddc769d5-5662-4e07-8d1d-14cec504bb7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776887915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1776887915
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.236435649
Short name T271
Test name
Test status
Simulation time 193761375159 ps
CPU time 933.83 seconds
Started May 02 12:54:51 PM PDT 24
Finished May 02 01:10:29 PM PDT 24
Peak memory 225892 kb
Host smart-f15e7f5d-8a2f-48db-960c-aad00a773d43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236435649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.236435649
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.925729160
Short name T172
Test name
Test status
Simulation time 991290287 ps
CPU time 22.79 seconds
Started May 02 12:54:53 PM PDT 24
Finished May 02 12:55:20 PM PDT 24
Peak memory 212876 kb
Host smart-f372f743-6366-4247-9a13-b1eeb7b0cb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925729160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.925729160
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2611595117
Short name T318
Test name
Test status
Simulation time 17490914041 ps
CPU time 34.17 seconds
Started May 02 12:54:56 PM PDT 24
Finished May 02 12:55:33 PM PDT 24
Peak memory 213076 kb
Host smart-5fb39eaa-f96f-411c-a6ed-e84cafc09f3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2611595117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2611595117
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.208851775
Short name T157
Test name
Test status
Simulation time 10874804904 ps
CPU time 48.87 seconds
Started May 02 12:54:54 PM PDT 24
Finished May 02 12:55:47 PM PDT 24
Peak memory 217528 kb
Host smart-f1367678-9356-4009-bf8c-11efcfb28ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208851775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.208851775
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2355998843
Short name T12
Test name
Test status
Simulation time 8480488044 ps
CPU time 45.48 seconds
Started May 02 12:54:52 PM PDT 24
Finished May 02 12:55:41 PM PDT 24
Peak memory 218164 kb
Host smart-e70207f6-3d3d-4ad9-a6ee-97f4474ce5bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355998843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2355998843
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3149483409
Short name T21
Test name
Test status
Simulation time 82906834121 ps
CPU time 646.08 seconds
Started May 02 12:54:53 PM PDT 24
Finished May 02 01:05:43 PM PDT 24
Peak memory 231672 kb
Host smart-a6e90b36-eb40-44ed-aa1e-fedae1e0c230
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149483409 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3149483409
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1063858268
Short name T40
Test name
Test status
Simulation time 59947679260 ps
CPU time 29.63 seconds
Started May 02 12:55:00 PM PDT 24
Finished May 02 12:55:33 PM PDT 24
Peak memory 212516 kb
Host smart-64d88076-a4ce-445a-a622-21addf6b3026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063858268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1063858268
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3043638423
Short name T262
Test name
Test status
Simulation time 65545648009 ps
CPU time 677.66 seconds
Started May 02 12:54:53 PM PDT 24
Finished May 02 01:06:15 PM PDT 24
Peak memory 217924 kb
Host smart-406e0f98-d2d9-4f8c-a0e2-44de21df2015
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043638423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3043638423
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.251539959
Short name T218
Test name
Test status
Simulation time 9218203799 ps
CPU time 46.84 seconds
Started May 02 12:54:58 PM PDT 24
Finished May 02 12:55:47 PM PDT 24
Peak memory 215408 kb
Host smart-23c613ce-86cf-4d36-9827-ce305dd20763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251539959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.251539959
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3709470799
Short name T284
Test name
Test status
Simulation time 779425854 ps
CPU time 15.11 seconds
Started May 02 12:54:51 PM PDT 24
Finished May 02 12:55:10 PM PDT 24
Peak memory 212376 kb
Host smart-8510083e-e21b-4051-ab02-a776f1dbb292
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3709470799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3709470799
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1279102602
Short name T359
Test name
Test status
Simulation time 2920643228 ps
CPU time 81.68 seconds
Started May 02 12:54:57 PM PDT 24
Finished May 02 12:56:22 PM PDT 24
Peak memory 221776 kb
Host smart-25735570-5bc7-4ca5-86f0-80f3559faa8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279102602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1279102602
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3258698131
Short name T209
Test name
Test status
Simulation time 2538372974 ps
CPU time 23.53 seconds
Started May 02 12:55:00 PM PDT 24
Finished May 02 12:55:27 PM PDT 24
Peak memory 212088 kb
Host smart-3c4058c3-782b-4149-b6c5-036a769dbc34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258698131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3258698131
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.537625347
Short name T309
Test name
Test status
Simulation time 721810764271 ps
CPU time 489.98 seconds
Started May 02 12:55:00 PM PDT 24
Finished May 02 01:03:14 PM PDT 24
Peak memory 215964 kb
Host smart-6fb8cc73-6ba1-4c57-b43c-ac02ec205c73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537625347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.537625347
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1583065372
Short name T222
Test name
Test status
Simulation time 7562558016 ps
CPU time 62.68 seconds
Started May 02 12:55:00 PM PDT 24
Finished May 02 12:56:06 PM PDT 24
Peak memory 215356 kb
Host smart-52000971-aa18-4788-b14a-281244adbc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583065372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1583065372
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3987638110
Short name T331
Test name
Test status
Simulation time 8962652618 ps
CPU time 27.43 seconds
Started May 02 12:55:00 PM PDT 24
Finished May 02 12:55:31 PM PDT 24
Peak memory 211592 kb
Host smart-2a75861a-afc8-47b6-88f0-dda4a99a0a3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3987638110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3987638110
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1408227691
Short name T210
Test name
Test status
Simulation time 13814121168 ps
CPU time 82.16 seconds
Started May 02 12:55:09 PM PDT 24
Finished May 02 12:56:33 PM PDT 24
Peak memory 217076 kb
Host smart-6a26d5a7-2672-44d5-866a-f21b9380a011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408227691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1408227691
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1181197661
Short name T11
Test name
Test status
Simulation time 540336297 ps
CPU time 25.96 seconds
Started May 02 12:55:06 PM PDT 24
Finished May 02 12:55:34 PM PDT 24
Peak memory 214180 kb
Host smart-3b27bd66-1d7b-4cf9-a143-6a800226c246
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181197661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1181197661
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3306075580
Short name T291
Test name
Test status
Simulation time 9037324484 ps
CPU time 25.22 seconds
Started May 02 12:54:59 PM PDT 24
Finished May 02 12:55:27 PM PDT 24
Peak memory 211616 kb
Host smart-74bf5e19-3860-4f90-b58a-6068ce8587c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306075580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3306075580
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3168426274
Short name T171
Test name
Test status
Simulation time 73625213096 ps
CPU time 693.6 seconds
Started May 02 12:55:05 PM PDT 24
Finished May 02 01:06:41 PM PDT 24
Peak memory 216340 kb
Host smart-3a90a0b7-34a4-480a-a46d-193f39964bfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168426274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3168426274
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.4279140491
Short name T174
Test name
Test status
Simulation time 53077445218 ps
CPU time 56.41 seconds
Started May 02 12:55:03 PM PDT 24
Finished May 02 12:56:03 PM PDT 24
Peak memory 214340 kb
Host smart-9ef2a990-2f11-4fb4-b2d8-8d1e10ca6dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279140491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.4279140491
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3814952489
Short name T139
Test name
Test status
Simulation time 6518821035 ps
CPU time 28.85 seconds
Started May 02 12:55:01 PM PDT 24
Finished May 02 12:55:33 PM PDT 24
Peak memory 211480 kb
Host smart-601e72fe-1b55-4125-999d-df33064c3b8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3814952489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3814952489
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2210487333
Short name T26
Test name
Test status
Simulation time 15123593750 ps
CPU time 47.36 seconds
Started May 02 12:55:01 PM PDT 24
Finished May 02 12:55:52 PM PDT 24
Peak memory 218128 kb
Host smart-6bd51700-6ffe-4246-94c0-2cf565e3b5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210487333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2210487333
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3099769673
Short name T249
Test name
Test status
Simulation time 41356450222 ps
CPU time 61.53 seconds
Started May 02 12:55:00 PM PDT 24
Finished May 02 12:56:06 PM PDT 24
Peak memory 216348 kb
Host smart-ec35c503-5234-45e9-b855-f18377b53958
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099769673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3099769673
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.117396828
Short name T192
Test name
Test status
Simulation time 2950760470 ps
CPU time 17.61 seconds
Started May 02 12:55:00 PM PDT 24
Finished May 02 12:55:21 PM PDT 24
Peak memory 211572 kb
Host smart-c687dd60-b9c1-477d-b83e-205d5f290dc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117396828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.117396828
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2306978975
Short name T42
Test name
Test status
Simulation time 46348182265 ps
CPU time 569.85 seconds
Started May 02 12:55:01 PM PDT 24
Finished May 02 01:04:35 PM PDT 24
Peak memory 235532 kb
Host smart-c11d9ccf-7d10-48f4-bed2-bda088bf22ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306978975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2306978975
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.511411538
Short name T283
Test name
Test status
Simulation time 4610057777 ps
CPU time 43.12 seconds
Started May 02 12:55:08 PM PDT 24
Finished May 02 12:55:54 PM PDT 24
Peak memory 215268 kb
Host smart-e58bbfd3-5880-4909-a3d6-801f86105c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511411538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.511411538
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3591351892
Short name T299
Test name
Test status
Simulation time 4159310799 ps
CPU time 34.59 seconds
Started May 02 12:55:00 PM PDT 24
Finished May 02 12:55:38 PM PDT 24
Peak memory 211636 kb
Host smart-f80ac3a9-ed55-4b3a-a9c6-83d1c849e1b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3591351892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3591351892
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.90914769
Short name T197
Test name
Test status
Simulation time 8017158963 ps
CPU time 76.56 seconds
Started May 02 12:54:59 PM PDT 24
Finished May 02 12:56:18 PM PDT 24
Peak memory 217204 kb
Host smart-7de0bb1e-49dd-4aa2-a502-ff429689f903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90914769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.90914769
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.83815780
Short name T189
Test name
Test status
Simulation time 1193015423 ps
CPU time 42.14 seconds
Started May 02 12:55:09 PM PDT 24
Finished May 02 12:55:54 PM PDT 24
Peak memory 219524 kb
Host smart-8cbb03a9-6aa6-4059-9e96-7678a43a4d8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83815780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 38.rom_ctrl_stress_all.83815780
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3531893169
Short name T290
Test name
Test status
Simulation time 5207056830 ps
CPU time 29.8 seconds
Started May 02 12:55:01 PM PDT 24
Finished May 02 12:55:35 PM PDT 24
Peak memory 212384 kb
Host smart-7750d13f-06d9-40ab-b154-1a291c3bcbdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531893169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3531893169
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1685648218
Short name T52
Test name
Test status
Simulation time 46288032293 ps
CPU time 468.1 seconds
Started May 02 12:55:00 PM PDT 24
Finished May 02 01:02:51 PM PDT 24
Peak memory 229292 kb
Host smart-39f22222-f66c-45ea-a7b6-7499996a236d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685648218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1685648218
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3272441715
Short name T256
Test name
Test status
Simulation time 11735845276 ps
CPU time 55.2 seconds
Started May 02 12:55:02 PM PDT 24
Finished May 02 12:56:00 PM PDT 24
Peak memory 215164 kb
Host smart-4c714283-961f-4e1a-bdc7-d571d5546f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272441715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3272441715
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1909699716
Short name T92
Test name
Test status
Simulation time 359202399 ps
CPU time 20.77 seconds
Started May 02 12:55:03 PM PDT 24
Finished May 02 12:55:27 PM PDT 24
Peak memory 217104 kb
Host smart-41627815-8e04-4c67-986b-0c82e7b8b5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909699716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1909699716
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1312544318
Short name T228
Test name
Test status
Simulation time 7743387069 ps
CPU time 21.52 seconds
Started May 02 12:55:01 PM PDT 24
Finished May 02 12:55:26 PM PDT 24
Peak memory 213788 kb
Host smart-399eb93e-cfbe-45ab-8cf5-783034f479bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312544318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1312544318
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3606439506
Short name T317
Test name
Test status
Simulation time 3828025097 ps
CPU time 31.83 seconds
Started May 02 12:53:54 PM PDT 24
Finished May 02 12:54:30 PM PDT 24
Peak memory 212172 kb
Host smart-85cba527-2f52-4983-bb36-31350067ebd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606439506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3606439506
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.535743607
Short name T29
Test name
Test status
Simulation time 150241035641 ps
CPU time 715.96 seconds
Started May 02 12:53:56 PM PDT 24
Finished May 02 01:05:56 PM PDT 24
Peak memory 215992 kb
Host smart-d27ae139-1e9f-46ea-889e-006fff2a32d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535743607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.535743607
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3049138706
Short name T7
Test name
Test status
Simulation time 3115341701 ps
CPU time 38.21 seconds
Started May 02 12:53:56 PM PDT 24
Finished May 02 12:54:38 PM PDT 24
Peak memory 214388 kb
Host smart-76ee3339-fa9e-42ee-9111-5d813e90985c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049138706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3049138706
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1167468598
Short name T294
Test name
Test status
Simulation time 1199954651 ps
CPU time 17.99 seconds
Started May 02 12:53:57 PM PDT 24
Finished May 02 12:54:20 PM PDT 24
Peak memory 211468 kb
Host smart-86093f57-a096-4f21-acbf-9a242aaf1f45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1167468598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1167468598
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1208195131
Short name T30
Test name
Test status
Simulation time 17441617513 ps
CPU time 141.23 seconds
Started May 02 12:54:01 PM PDT 24
Finished May 02 12:56:26 PM PDT 24
Peak memory 239104 kb
Host smart-6b2fbddf-6b4b-46af-8027-67e247c82e04
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208195131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1208195131
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3837636593
Short name T234
Test name
Test status
Simulation time 352896432 ps
CPU time 20.2 seconds
Started May 02 12:53:58 PM PDT 24
Finished May 02 12:54:22 PM PDT 24
Peak memory 215924 kb
Host smart-702b16b9-a532-4397-9de1-a2c45faef6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837636593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3837636593
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3324901419
Short name T140
Test name
Test status
Simulation time 2902695206 ps
CPU time 47.2 seconds
Started May 02 12:53:57 PM PDT 24
Finished May 02 12:54:49 PM PDT 24
Peak memory 219620 kb
Host smart-a8dd94db-d244-4a1c-ba54-6f7905d03f38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324901419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3324901419
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2024962254
Short name T308
Test name
Test status
Simulation time 7839671341 ps
CPU time 31.87 seconds
Started May 02 12:55:09 PM PDT 24
Finished May 02 12:55:43 PM PDT 24
Peak memory 212188 kb
Host smart-f74c192f-529f-4eaa-bfc4-64428eb4a062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024962254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2024962254
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1234758959
Short name T214
Test name
Test status
Simulation time 9973858542 ps
CPU time 211.24 seconds
Started May 02 12:55:01 PM PDT 24
Finished May 02 12:58:36 PM PDT 24
Peak memory 240532 kb
Host smart-3a50983f-f2b2-4f44-ae37-44bde542e75c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234758959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1234758959
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2601629312
Short name T147
Test name
Test status
Simulation time 1321500395 ps
CPU time 19.45 seconds
Started May 02 12:55:00 PM PDT 24
Finished May 02 12:55:22 PM PDT 24
Peak memory 214884 kb
Host smart-96dc812a-a4c0-469b-ac65-249808a11d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601629312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2601629312
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.4104670606
Short name T333
Test name
Test status
Simulation time 13817615646 ps
CPU time 33.81 seconds
Started May 02 12:55:00 PM PDT 24
Finished May 02 12:55:37 PM PDT 24
Peak memory 212092 kb
Host smart-0ea8ea0f-c777-4519-acc7-61bc9c37697e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4104670606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.4104670606
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2322052365
Short name T3
Test name
Test status
Simulation time 2002430040 ps
CPU time 33.56 seconds
Started May 02 12:55:01 PM PDT 24
Finished May 02 12:55:38 PM PDT 24
Peak memory 217688 kb
Host smart-6b8757b3-f6fa-41d6-a0a2-079912f7e276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322052365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2322052365
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3393630239
Short name T149
Test name
Test status
Simulation time 11161313750 ps
CPU time 96.04 seconds
Started May 02 12:54:59 PM PDT 24
Finished May 02 12:56:38 PM PDT 24
Peak memory 219524 kb
Host smart-d3e69a06-2d57-4ab4-9091-e2f44e3047e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393630239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3393630239
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.4125607846
Short name T297
Test name
Test status
Simulation time 67222511684 ps
CPU time 33.46 seconds
Started May 02 12:55:08 PM PDT 24
Finished May 02 12:55:44 PM PDT 24
Peak memory 212408 kb
Host smart-3c0a9d73-ce2e-4d3b-974c-689c8759153d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125607846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.4125607846
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.831842600
Short name T320
Test name
Test status
Simulation time 269394353145 ps
CPU time 603.94 seconds
Started May 02 12:55:08 PM PDT 24
Finished May 02 01:05:14 PM PDT 24
Peak memory 238340 kb
Host smart-cc180a56-d114-46b3-a072-f2b0a7eed0e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831842600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.831842600
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3792670285
Short name T45
Test name
Test status
Simulation time 2134694315 ps
CPU time 33.09 seconds
Started May 02 12:55:15 PM PDT 24
Finished May 02 12:55:51 PM PDT 24
Peak memory 214992 kb
Host smart-25f64833-c8e6-4bda-b6ac-c24a81368a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792670285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3792670285
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.142216930
Short name T257
Test name
Test status
Simulation time 178690301 ps
CPU time 10.35 seconds
Started May 02 12:55:09 PM PDT 24
Finished May 02 12:55:21 PM PDT 24
Peak memory 212484 kb
Host smart-194ef297-a222-424d-a7b6-b2440ba3a5a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=142216930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.142216930
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3634419119
Short name T237
Test name
Test status
Simulation time 28013935507 ps
CPU time 62.13 seconds
Started May 02 12:55:06 PM PDT 24
Finished May 02 12:56:11 PM PDT 24
Peak memory 217828 kb
Host smart-a5c1b371-503c-4aa3-be8e-9ce94ba0da22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634419119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3634419119
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2005007389
Short name T19
Test name
Test status
Simulation time 208924222 ps
CPU time 18.1 seconds
Started May 02 12:55:08 PM PDT 24
Finished May 02 12:55:28 PM PDT 24
Peak memory 212824 kb
Host smart-705dda95-a816-4566-baed-8eafdf472450
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005007389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2005007389
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4209357541
Short name T268
Test name
Test status
Simulation time 10781880549 ps
CPU time 20.63 seconds
Started May 02 12:55:07 PM PDT 24
Finished May 02 12:55:30 PM PDT 24
Peak memory 212308 kb
Host smart-25e3dfbd-cd0f-454b-a873-b77fdf6401ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209357541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4209357541
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3408807301
Short name T307
Test name
Test status
Simulation time 43534733478 ps
CPU time 590.25 seconds
Started May 02 12:55:08 PM PDT 24
Finished May 02 01:05:01 PM PDT 24
Peak memory 217564 kb
Host smart-23bffa3a-9954-49d8-aab0-7421a3d865ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408807301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3408807301
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2081193943
Short name T203
Test name
Test status
Simulation time 689060483 ps
CPU time 18.96 seconds
Started May 02 12:55:09 PM PDT 24
Finished May 02 12:55:30 PM PDT 24
Peak memory 214908 kb
Host smart-96a9ac0f-dc77-4b0e-83dc-09f2ae168339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081193943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2081193943
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1056171733
Short name T258
Test name
Test status
Simulation time 5291345178 ps
CPU time 18.6 seconds
Started May 02 12:55:08 PM PDT 24
Finished May 02 12:55:29 PM PDT 24
Peak memory 211900 kb
Host smart-4080db14-c7fc-4bb6-b445-ef494ced9ab7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1056171733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1056171733
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3353312901
Short name T335
Test name
Test status
Simulation time 19256584964 ps
CPU time 47.72 seconds
Started May 02 12:55:08 PM PDT 24
Finished May 02 12:55:58 PM PDT 24
Peak memory 215852 kb
Host smart-6306c153-9186-4a17-a738-ff2497b28474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353312901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3353312901
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3655674386
Short name T330
Test name
Test status
Simulation time 5327700115 ps
CPU time 53.75 seconds
Started May 02 12:55:16 PM PDT 24
Finished May 02 12:56:14 PM PDT 24
Peak memory 217644 kb
Host smart-77a23338-e8af-4a1b-9566-7434cceb2cfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655674386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3655674386
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3433599892
Short name T273
Test name
Test status
Simulation time 2628598970 ps
CPU time 24.39 seconds
Started May 02 12:55:15 PM PDT 24
Finished May 02 12:55:43 PM PDT 24
Peak memory 211552 kb
Host smart-ed2593eb-a42d-40fb-9b95-0d6a0eb952e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433599892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3433599892
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2089396635
Short name T323
Test name
Test status
Simulation time 97376381144 ps
CPU time 600.4 seconds
Started May 02 12:55:15 PM PDT 24
Finished May 02 01:05:19 PM PDT 24
Peak memory 238120 kb
Host smart-68ebf7de-fdb2-41d3-9cfa-2e7725c42014
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089396635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2089396635
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2757887093
Short name T250
Test name
Test status
Simulation time 1321468513 ps
CPU time 18.82 seconds
Started May 02 12:55:15 PM PDT 24
Finished May 02 12:55:37 PM PDT 24
Peak memory 215020 kb
Host smart-46027559-ed04-457d-b189-5db097c1eed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757887093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2757887093
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2514213752
Short name T267
Test name
Test status
Simulation time 15420190598 ps
CPU time 31.69 seconds
Started May 02 12:55:15 PM PDT 24
Finished May 02 12:55:50 PM PDT 24
Peak memory 212692 kb
Host smart-ccfdd5be-8100-43cc-8958-c6635604f9ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2514213752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2514213752
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3118519198
Short name T154
Test name
Test status
Simulation time 29540239959 ps
CPU time 60.41 seconds
Started May 02 12:55:14 PM PDT 24
Finished May 02 12:56:17 PM PDT 24
Peak memory 218144 kb
Host smart-27d2945c-352b-410f-8c64-3819dbf33a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118519198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3118519198
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.4038319382
Short name T202
Test name
Test status
Simulation time 20226730507 ps
CPU time 76.26 seconds
Started May 02 12:55:17 PM PDT 24
Finished May 02 12:56:37 PM PDT 24
Peak memory 221276 kb
Host smart-a24a3484-2992-4240-beab-9c1d664515dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038319382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.4038319382
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.859360902
Short name T278
Test name
Test status
Simulation time 13273431995 ps
CPU time 27.61 seconds
Started May 02 12:55:15 PM PDT 24
Finished May 02 12:55:46 PM PDT 24
Peak memory 212464 kb
Host smart-6ca47d71-b294-4e1c-bdab-32ade739f2c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859360902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.859360902
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1535540509
Short name T151
Test name
Test status
Simulation time 6722332046 ps
CPU time 249.3 seconds
Started May 02 12:55:16 PM PDT 24
Finished May 02 12:59:29 PM PDT 24
Peak memory 237052 kb
Host smart-0087d7b2-ca69-4c45-b665-c52c35aec4eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535540509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1535540509
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2345765420
Short name T326
Test name
Test status
Simulation time 24674449212 ps
CPU time 58.45 seconds
Started May 02 12:55:15 PM PDT 24
Finished May 02 12:56:17 PM PDT 24
Peak memory 213112 kb
Host smart-daf94369-f9c5-46c2-aa0d-0ed4286775e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345765420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2345765420
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3065384038
Short name T231
Test name
Test status
Simulation time 8205986650 ps
CPU time 33.3 seconds
Started May 02 12:55:14 PM PDT 24
Finished May 02 12:55:49 PM PDT 24
Peak memory 211972 kb
Host smart-2b81be67-1cfe-4ec7-8bdf-7e0192df1f2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3065384038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3065384038
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2685173813
Short name T200
Test name
Test status
Simulation time 3934233623 ps
CPU time 46 seconds
Started May 02 12:55:14 PM PDT 24
Finished May 02 12:56:02 PM PDT 24
Peak memory 216120 kb
Host smart-0a6f1f3e-e592-4b1a-b639-df6e4f2e0d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685173813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2685173813
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1932468400
Short name T311
Test name
Test status
Simulation time 962174015 ps
CPU time 50.94 seconds
Started May 02 12:55:16 PM PDT 24
Finished May 02 12:56:11 PM PDT 24
Peak memory 219540 kb
Host smart-13604469-e9c0-423f-ac1e-071fc59dea8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932468400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1932468400
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2639362256
Short name T238
Test name
Test status
Simulation time 174379208 ps
CPU time 8.27 seconds
Started May 02 12:55:20 PM PDT 24
Finished May 02 12:55:34 PM PDT 24
Peak memory 211580 kb
Host smart-da504779-613a-4b20-8072-ee236475d28a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639362256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2639362256
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4115076106
Short name T337
Test name
Test status
Simulation time 4798061126 ps
CPU time 344.01 seconds
Started May 02 12:55:20 PM PDT 24
Finished May 02 01:01:09 PM PDT 24
Peak memory 241168 kb
Host smart-248a0b67-1560-4a4b-ae4b-8aaafb7c0fc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115076106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4115076106
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2797997046
Short name T225
Test name
Test status
Simulation time 4263667848 ps
CPU time 33.68 seconds
Started May 02 12:55:20 PM PDT 24
Finished May 02 12:55:59 PM PDT 24
Peak memory 215032 kb
Host smart-5fff8127-5082-4a7e-8dc1-e243fba6c818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797997046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2797997046
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1330465083
Short name T357
Test name
Test status
Simulation time 22489937886 ps
CPU time 31.56 seconds
Started May 02 12:55:21 PM PDT 24
Finished May 02 12:55:57 PM PDT 24
Peak memory 212008 kb
Host smart-8f4abfd9-ebc9-40b0-813b-252636efd642
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330465083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1330465083
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1858970487
Short name T281
Test name
Test status
Simulation time 1431352446 ps
CPU time 19.64 seconds
Started May 02 12:55:16 PM PDT 24
Finished May 02 12:55:40 PM PDT 24
Peak memory 218160 kb
Host smart-3c2c6a75-829f-4871-90e0-c7ed4e47d6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858970487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1858970487
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1218458940
Short name T277
Test name
Test status
Simulation time 11783100095 ps
CPU time 32.9 seconds
Started May 02 12:55:13 PM PDT 24
Finished May 02 12:55:47 PM PDT 24
Peak memory 212088 kb
Host smart-b164894d-96aa-4adf-84d5-9be8a987782a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218458940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1218458940
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3022792557
Short name T236
Test name
Test status
Simulation time 17924369209 ps
CPU time 33.98 seconds
Started May 02 12:55:22 PM PDT 24
Finished May 02 12:56:01 PM PDT 24
Peak memory 212404 kb
Host smart-8af182f1-1006-4583-821b-a4169a752539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022792557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3022792557
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4238970238
Short name T350
Test name
Test status
Simulation time 2567277602 ps
CPU time 34.89 seconds
Started May 02 12:55:21 PM PDT 24
Finished May 02 12:56:01 PM PDT 24
Peak memory 214976 kb
Host smart-d914a65a-1253-482e-a40e-84922bf248e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238970238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4238970238
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.899289206
Short name T344
Test name
Test status
Simulation time 9572376390 ps
CPU time 25.19 seconds
Started May 02 12:55:20 PM PDT 24
Finished May 02 12:55:50 PM PDT 24
Peak memory 211904 kb
Host smart-00c9f96a-d0af-4c62-a6cc-d625374bd961
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=899289206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.899289206
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.112466778
Short name T301
Test name
Test status
Simulation time 2836046092 ps
CPU time 19.46 seconds
Started May 02 12:55:23 PM PDT 24
Finished May 02 12:55:47 PM PDT 24
Peak memory 217212 kb
Host smart-637b589a-4517-403b-8243-28092214c516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112466778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.112466778
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.534355308
Short name T292
Test name
Test status
Simulation time 2110656914 ps
CPU time 58.89 seconds
Started May 02 12:55:23 PM PDT 24
Finished May 02 12:56:26 PM PDT 24
Peak memory 221320 kb
Host smart-ade46aa1-9fea-4235-8eea-e675b8e4cf7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534355308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.534355308
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3550690423
Short name T217
Test name
Test status
Simulation time 5454089789 ps
CPU time 16.31 seconds
Started May 02 12:55:30 PM PDT 24
Finished May 02 12:55:50 PM PDT 24
Peak memory 211624 kb
Host smart-00d22168-6dd1-4800-9b33-330d5ab40666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550690423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3550690423
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1136309346
Short name T141
Test name
Test status
Simulation time 20386313292 ps
CPU time 349.89 seconds
Started May 02 12:55:24 PM PDT 24
Finished May 02 01:01:19 PM PDT 24
Peak memory 219768 kb
Host smart-7cfeeaa1-1bd1-4b1c-9e57-f82e7046834b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136309346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1136309346
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.403925264
Short name T190
Test name
Test status
Simulation time 8684820408 ps
CPU time 67.79 seconds
Started May 02 12:55:32 PM PDT 24
Finished May 02 12:56:43 PM PDT 24
Peak memory 215144 kb
Host smart-1a61342f-93bc-473e-8122-916e5e7fcec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403925264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.403925264
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1088103895
Short name T76
Test name
Test status
Simulation time 5723185778 ps
CPU time 19.33 seconds
Started May 02 12:55:23 PM PDT 24
Finished May 02 12:55:47 PM PDT 24
Peak memory 213072 kb
Host smart-89ed90e4-a213-4f37-a217-3c11d9292bb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088103895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1088103895
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2285832840
Short name T213
Test name
Test status
Simulation time 1706645643 ps
CPU time 30.31 seconds
Started May 02 12:55:22 PM PDT 24
Finished May 02 12:55:57 PM PDT 24
Peak memory 216920 kb
Host smart-a5ffd957-e191-4287-8181-f1b5631e3b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285832840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2285832840
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.182313963
Short name T287
Test name
Test status
Simulation time 2208260254 ps
CPU time 21.44 seconds
Started May 02 12:55:29 PM PDT 24
Finished May 02 12:55:54 PM PDT 24
Peak memory 212196 kb
Host smart-40719bd2-f39f-4ead-97c9-2d48d1e6cf6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182313963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.182313963
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1160782565
Short name T158
Test name
Test status
Simulation time 91714652162 ps
CPU time 923.49 seconds
Started May 02 12:55:28 PM PDT 24
Finished May 02 01:10:56 PM PDT 24
Peak memory 234232 kb
Host smart-644afca5-8bc1-42e5-82e6-d26185f4ffff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160782565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1160782565
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3672264371
Short name T185
Test name
Test status
Simulation time 5190954072 ps
CPU time 49.14 seconds
Started May 02 12:55:28 PM PDT 24
Finished May 02 12:56:21 PM PDT 24
Peak memory 216536 kb
Host smart-d8ea4621-84f8-4cfe-a417-fc6c008007c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672264371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3672264371
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2201496605
Short name T266
Test name
Test status
Simulation time 11802279580 ps
CPU time 19.58 seconds
Started May 02 12:55:30 PM PDT 24
Finished May 02 12:55:53 PM PDT 24
Peak memory 211608 kb
Host smart-4036f177-2814-4ebb-a050-c0d5b39a82cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2201496605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2201496605
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1400045188
Short name T340
Test name
Test status
Simulation time 719203840 ps
CPU time 19.98 seconds
Started May 02 12:55:28 PM PDT 24
Finished May 02 12:55:52 PM PDT 24
Peak memory 217188 kb
Host smart-5b9765f2-676c-4405-b938-7ba94e78671a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400045188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1400045188
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1176323549
Short name T343
Test name
Test status
Simulation time 8793871763 ps
CPU time 41.46 seconds
Started May 02 12:55:27 PM PDT 24
Finished May 02 12:56:13 PM PDT 24
Peak memory 214308 kb
Host smart-24fd8917-8f06-4bd6-9d76-aa4d3dbe3ef9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176323549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1176323549
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.562286624
Short name T232
Test name
Test status
Simulation time 12159807224 ps
CPU time 26.03 seconds
Started May 02 12:55:27 PM PDT 24
Finished May 02 12:55:58 PM PDT 24
Peak memory 212404 kb
Host smart-e3736f74-87a2-434d-b3f5-31fdeb57ef94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562286624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.562286624
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1623537690
Short name T206
Test name
Test status
Simulation time 165021911849 ps
CPU time 316.28 seconds
Started May 02 12:55:29 PM PDT 24
Finished May 02 01:00:49 PM PDT 24
Peak memory 226280 kb
Host smart-801691bf-5cfe-4a8d-a76c-597daba00fc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623537690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1623537690
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3925524759
Short name T300
Test name
Test status
Simulation time 8517071664 ps
CPU time 33.46 seconds
Started May 02 12:55:32 PM PDT 24
Finished May 02 12:56:08 PM PDT 24
Peak memory 215576 kb
Host smart-844720cf-f567-4e20-ac8f-ffb8d3ccf0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925524759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3925524759
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2107761111
Short name T304
Test name
Test status
Simulation time 3984875158 ps
CPU time 16.2 seconds
Started May 02 12:55:32 PM PDT 24
Finished May 02 12:55:51 PM PDT 24
Peak memory 211448 kb
Host smart-fb8a83b1-62c7-4943-9a49-36baa2d00977
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2107761111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2107761111
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2495245725
Short name T223
Test name
Test status
Simulation time 33770359893 ps
CPU time 77.7 seconds
Started May 02 12:55:29 PM PDT 24
Finished May 02 12:56:51 PM PDT 24
Peak memory 218652 kb
Host smart-75badaf7-7dd6-4c68-adcb-860f7e33a2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495245725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2495245725
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1216738676
Short name T338
Test name
Test status
Simulation time 20886022924 ps
CPU time 40.27 seconds
Started May 02 12:55:31 PM PDT 24
Finished May 02 12:56:14 PM PDT 24
Peak memory 217028 kb
Host smart-66e71fe2-5d55-4308-99b6-1e36b909a50c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216738676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1216738676
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2100546209
Short name T5
Test name
Test status
Simulation time 326650388333 ps
CPU time 405.67 seconds
Started May 02 12:54:05 PM PDT 24
Finished May 02 01:00:55 PM PDT 24
Peak memory 216160 kb
Host smart-0b28edfa-236d-4abc-8188-41b423a57a9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100546209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2100546209
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2305044402
Short name T279
Test name
Test status
Simulation time 2303011409 ps
CPU time 27.74 seconds
Started May 02 12:54:03 PM PDT 24
Finished May 02 12:54:36 PM PDT 24
Peak memory 214984 kb
Host smart-1b1a47c3-9f00-4d7c-aa4e-1adde62fa16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305044402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2305044402
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.4206047766
Short name T134
Test name
Test status
Simulation time 383281890 ps
CPU time 10.38 seconds
Started May 02 12:53:57 PM PDT 24
Finished May 02 12:54:11 PM PDT 24
Peak memory 212584 kb
Host smart-65fa739c-a38d-4701-aad0-4fe9e88599da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4206047766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.4206047766
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1386991361
Short name T230
Test name
Test status
Simulation time 422209864 ps
CPU time 19.91 seconds
Started May 02 12:53:57 PM PDT 24
Finished May 02 12:54:21 PM PDT 24
Peak memory 216784 kb
Host smart-39457621-9d87-4961-a31d-5f938dcd039c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386991361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1386991361
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3473725889
Short name T93
Test name
Test status
Simulation time 1559174516 ps
CPU time 14.18 seconds
Started May 02 12:54:02 PM PDT 24
Finished May 02 12:54:21 PM PDT 24
Peak memory 214076 kb
Host smart-9b7e826f-3dcd-4829-abaa-17934f2c1bab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473725889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3473725889
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2164582237
Short name T285
Test name
Test status
Simulation time 10205719242 ps
CPU time 31 seconds
Started May 02 12:54:03 PM PDT 24
Finished May 02 12:54:38 PM PDT 24
Peak memory 212544 kb
Host smart-b4ff0152-184d-4033-913f-76a97fb13d0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164582237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2164582237
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1901538520
Short name T51
Test name
Test status
Simulation time 15395157163 ps
CPU time 258.24 seconds
Started May 02 12:54:03 PM PDT 24
Finished May 02 12:58:26 PM PDT 24
Peak memory 241124 kb
Host smart-e76ccd9f-8805-4480-b5a5-cb028c26b68d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901538520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1901538520
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.304277601
Short name T173
Test name
Test status
Simulation time 1376268391 ps
CPU time 18.74 seconds
Started May 02 12:54:02 PM PDT 24
Finished May 02 12:54:23 PM PDT 24
Peak memory 214944 kb
Host smart-5ffe9b78-cf2d-461e-84cc-9178012a55e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304277601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.304277601
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2173357290
Short name T243
Test name
Test status
Simulation time 182444971 ps
CPU time 10.58 seconds
Started May 02 12:54:07 PM PDT 24
Finished May 02 12:54:21 PM PDT 24
Peak memory 212676 kb
Host smart-3abed67e-340c-4216-8912-862e0c01065a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2173357290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2173357290
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3099675021
Short name T282
Test name
Test status
Simulation time 1435392532 ps
CPU time 20.66 seconds
Started May 02 12:54:03 PM PDT 24
Finished May 02 12:54:27 PM PDT 24
Peak memory 217576 kb
Host smart-1c5592de-9933-40fb-8b2e-1aa4fd526309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099675021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3099675021
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2513776248
Short name T212
Test name
Test status
Simulation time 758182807 ps
CPU time 27.47 seconds
Started May 02 12:54:04 PM PDT 24
Finished May 02 12:54:36 PM PDT 24
Peak memory 215488 kb
Host smart-40977e10-4ee0-44e8-9838-97434b50f72e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513776248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2513776248
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2931787845
Short name T327
Test name
Test status
Simulation time 8172009810 ps
CPU time 20.27 seconds
Started May 02 12:54:04 PM PDT 24
Finished May 02 12:54:29 PM PDT 24
Peak memory 211532 kb
Host smart-75057675-5535-447a-8045-39eb5f01625e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931787845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2931787845
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2814084617
Short name T43
Test name
Test status
Simulation time 165819791181 ps
CPU time 454.94 seconds
Started May 02 12:54:03 PM PDT 24
Finished May 02 01:01:42 PM PDT 24
Peak memory 235012 kb
Host smart-9a04d556-0c82-4af5-be13-c68d94131406
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814084617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2814084617
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2058107202
Short name T226
Test name
Test status
Simulation time 12856332448 ps
CPU time 54.75 seconds
Started May 02 12:54:03 PM PDT 24
Finished May 02 12:55:02 PM PDT 24
Peak memory 215304 kb
Host smart-f17904a3-1c4e-481d-9e21-aa3141b9be40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058107202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2058107202
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3149712371
Short name T66
Test name
Test status
Simulation time 17760073487 ps
CPU time 33.79 seconds
Started May 02 12:54:01 PM PDT 24
Finished May 02 12:54:39 PM PDT 24
Peak memory 211752 kb
Host smart-11be235e-a5cb-46bb-b42a-64dadceb767a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3149712371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3149712371
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.204089402
Short name T347
Test name
Test status
Simulation time 44595450630 ps
CPU time 61.93 seconds
Started May 02 12:54:06 PM PDT 24
Finished May 02 12:55:12 PM PDT 24
Peak memory 218692 kb
Host smart-b8bf9622-5821-4392-a660-74aa56a54b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204089402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.204089402
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.133596727
Short name T356
Test name
Test status
Simulation time 51010860109 ps
CPU time 112.89 seconds
Started May 02 12:54:04 PM PDT 24
Finished May 02 12:56:01 PM PDT 24
Peak memory 222164 kb
Host smart-40325da6-daab-42ec-bfd8-f409dc70af53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133596727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.133596727
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3003786102
Short name T316
Test name
Test status
Simulation time 7527692601 ps
CPU time 31.33 seconds
Started May 02 12:54:04 PM PDT 24
Finished May 02 12:54:40 PM PDT 24
Peak memory 212324 kb
Host smart-426367be-92b4-4d59-8ee3-7a875e2d92f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003786102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3003786102
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.57785029
Short name T196
Test name
Test status
Simulation time 361296326293 ps
CPU time 839.22 seconds
Started May 02 12:54:02 PM PDT 24
Finished May 02 01:08:05 PM PDT 24
Peak memory 225916 kb
Host smart-669cb017-0e1e-41a7-9cb1-e3bfaf959621
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57785029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_cor
rupt_sig_fatal_chk.57785029
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1993181652
Short name T360
Test name
Test status
Simulation time 2792975087 ps
CPU time 37.25 seconds
Started May 02 12:54:05 PM PDT 24
Finished May 02 12:54:46 PM PDT 24
Peak memory 214952 kb
Host smart-b4ef5c09-87bd-44c9-86b7-7038a29d56c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993181652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1993181652
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.976661806
Short name T201
Test name
Test status
Simulation time 181967982 ps
CPU time 10.56 seconds
Started May 02 12:54:04 PM PDT 24
Finished May 02 12:54:19 PM PDT 24
Peak memory 212488 kb
Host smart-e6394705-85f7-4f56-96c8-c05bbb456d2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=976661806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.976661806
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.4215367724
Short name T167
Test name
Test status
Simulation time 4283056001 ps
CPU time 49.1 seconds
Started May 02 12:54:03 PM PDT 24
Finished May 02 12:54:56 PM PDT 24
Peak memory 215192 kb
Host smart-e2a873af-8f9c-4ca8-901f-f79f88401445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215367724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4215367724
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2279705212
Short name T199
Test name
Test status
Simulation time 1042012152 ps
CPU time 65.81 seconds
Started May 02 12:54:02 PM PDT 24
Finished May 02 12:55:12 PM PDT 24
Peak memory 220140 kb
Host smart-178a338d-719f-4c23-83e9-6ae5ed210214
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279705212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2279705212
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1174767054
Short name T64
Test name
Test status
Simulation time 14691719131 ps
CPU time 29.02 seconds
Started May 02 12:54:03 PM PDT 24
Finished May 02 12:54:36 PM PDT 24
Peak memory 211520 kb
Host smart-54348ae5-786e-4124-8963-88cbd99454d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174767054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1174767054
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2287797602
Short name T336
Test name
Test status
Simulation time 5304688317 ps
CPU time 218.08 seconds
Started May 02 12:54:04 PM PDT 24
Finished May 02 12:57:47 PM PDT 24
Peak memory 228356 kb
Host smart-82019995-71c9-408d-a74a-19be3a311b2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287797602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2287797602
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1435294156
Short name T165
Test name
Test status
Simulation time 4346235263 ps
CPU time 44.98 seconds
Started May 02 12:54:04 PM PDT 24
Finished May 02 12:54:53 PM PDT 24
Peak memory 215156 kb
Host smart-3ed49f81-2923-47da-8d58-9ef81c465f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435294156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1435294156
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2460166508
Short name T177
Test name
Test status
Simulation time 1459699344 ps
CPU time 10.6 seconds
Started May 02 12:54:05 PM PDT 24
Finished May 02 12:54:20 PM PDT 24
Peak memory 211868 kb
Host smart-54413ea7-42c7-47cc-80ef-75dff99ccb5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2460166508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2460166508
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1754713757
Short name T195
Test name
Test status
Simulation time 38981408494 ps
CPU time 63.98 seconds
Started May 02 12:54:03 PM PDT 24
Finished May 02 12:55:11 PM PDT 24
Peak memory 217304 kb
Host smart-07718572-e670-4ce8-be69-52895dcb7e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754713757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1754713757
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.4217296270
Short name T215
Test name
Test status
Simulation time 5414081274 ps
CPU time 26.24 seconds
Started May 02 12:54:04 PM PDT 24
Finished May 02 12:54:35 PM PDT 24
Peak memory 214212 kb
Host smart-efe8c621-8f87-43e9-ae8c-0dd582c8da37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217296270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.4217296270
Directory /workspace/9.rom_ctrl_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%