Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.56 96.97 93.15 97.88 100.00 98.69 97.88 98.37


Total test records in report: 453
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T301 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1579170561 May 05 12:42:05 PM PDT 24 May 05 12:45:54 PM PDT 24 11165946355 ps
T302 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.373670180 May 05 12:42:44 PM PDT 24 May 05 12:43:13 PM PDT 24 2972461978 ps
T303 /workspace/coverage/default/22.rom_ctrl_stress_all.397512743 May 05 12:42:24 PM PDT 24 May 05 12:44:12 PM PDT 24 26769037583 ps
T304 /workspace/coverage/default/0.rom_ctrl_smoke.3895903775 May 05 12:42:15 PM PDT 24 May 05 12:42:37 PM PDT 24 366921848 ps
T305 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3928685031 May 05 12:42:46 PM PDT 24 May 05 12:43:09 PM PDT 24 3543627630 ps
T306 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.202191023 May 05 12:41:53 PM PDT 24 May 05 12:42:19 PM PDT 24 4840725125 ps
T307 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.796229786 May 05 12:42:36 PM PDT 24 May 05 12:43:07 PM PDT 24 3390647880 ps
T308 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1430257798 May 05 12:42:42 PM PDT 24 May 05 12:43:20 PM PDT 24 2838642161 ps
T309 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1861453921 May 05 12:42:41 PM PDT 24 May 05 12:42:58 PM PDT 24 914383260 ps
T310 /workspace/coverage/default/8.rom_ctrl_smoke.181013459 May 05 12:42:25 PM PDT 24 May 05 12:42:52 PM PDT 24 3489950122 ps
T311 /workspace/coverage/default/36.rom_ctrl_alert_test.3265980998 May 05 12:42:36 PM PDT 24 May 05 12:42:45 PM PDT 24 424480302 ps
T312 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2577835511 May 05 12:41:58 PM PDT 24 May 05 12:42:32 PM PDT 24 9365990166 ps
T313 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.588849496 May 05 12:42:39 PM PDT 24 May 05 12:42:50 PM PDT 24 349287585 ps
T314 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1950088209 May 05 12:42:38 PM PDT 24 May 05 12:48:31 PM PDT 24 47096274218 ps
T315 /workspace/coverage/default/22.rom_ctrl_smoke.1463257753 May 05 12:42:41 PM PDT 24 May 05 12:43:23 PM PDT 24 2643351591 ps
T316 /workspace/coverage/default/12.rom_ctrl_smoke.3592819400 May 05 12:42:28 PM PDT 24 May 05 12:42:49 PM PDT 24 580392744 ps
T317 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1235164615 May 05 12:42:34 PM PDT 24 May 05 12:54:48 PM PDT 24 81267791042 ps
T318 /workspace/coverage/default/26.rom_ctrl_stress_all.4097442543 May 05 12:42:43 PM PDT 24 May 05 12:45:51 PM PDT 24 67055404639 ps
T319 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3212833303 May 05 12:42:22 PM PDT 24 May 05 12:42:42 PM PDT 24 2749847807 ps
T320 /workspace/coverage/default/24.rom_ctrl_smoke.2703833845 May 05 12:42:33 PM PDT 24 May 05 12:43:39 PM PDT 24 40047097044 ps
T321 /workspace/coverage/default/24.rom_ctrl_alert_test.1364735190 May 05 12:42:42 PM PDT 24 May 05 12:42:51 PM PDT 24 394349042 ps
T322 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1224434023 May 05 12:42:50 PM PDT 24 May 05 12:57:09 PM PDT 24 347121396379 ps
T323 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.443051311 May 05 12:42:41 PM PDT 24 May 05 12:43:04 PM PDT 24 988813462 ps
T324 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.48318689 May 05 12:42:13 PM PDT 24 May 05 12:43:08 PM PDT 24 20592851186 ps
T325 /workspace/coverage/default/29.rom_ctrl_alert_test.1131921888 May 05 12:42:39 PM PDT 24 May 05 12:42:48 PM PDT 24 190077368 ps
T326 /workspace/coverage/default/9.rom_ctrl_stress_all.4184106671 May 05 12:42:09 PM PDT 24 May 05 12:43:32 PM PDT 24 12506332724 ps
T327 /workspace/coverage/default/41.rom_ctrl_alert_test.2894141823 May 05 12:42:44 PM PDT 24 May 05 12:43:05 PM PDT 24 6617687730 ps
T328 /workspace/coverage/default/3.rom_ctrl_smoke.156022660 May 05 12:42:33 PM PDT 24 May 05 12:42:54 PM PDT 24 1384358928 ps
T329 /workspace/coverage/default/17.rom_ctrl_stress_all.302365776 May 05 12:42:27 PM PDT 24 May 05 12:44:23 PM PDT 24 41417299037 ps
T330 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3877039250 May 05 12:42:21 PM PDT 24 May 05 12:42:42 PM PDT 24 690808101 ps
T331 /workspace/coverage/default/28.rom_ctrl_stress_all.3064401335 May 05 12:42:44 PM PDT 24 May 05 12:45:22 PM PDT 24 15418005698 ps
T332 /workspace/coverage/default/3.rom_ctrl_alert_test.3028809440 May 05 12:42:33 PM PDT 24 May 05 12:42:42 PM PDT 24 661218279 ps
T333 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.4016230487 May 05 12:42:46 PM PDT 24 May 05 12:43:18 PM PDT 24 3981656026 ps
T334 /workspace/coverage/default/32.rom_ctrl_stress_all.1937104927 May 05 12:42:43 PM PDT 24 May 05 12:44:00 PM PDT 24 31059987598 ps
T335 /workspace/coverage/default/8.rom_ctrl_alert_test.371496252 May 05 12:42:24 PM PDT 24 May 05 12:42:45 PM PDT 24 7857495741 ps
T336 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1067934381 May 05 12:42:20 PM PDT 24 May 05 12:42:49 PM PDT 24 3109316491 ps
T337 /workspace/coverage/default/44.rom_ctrl_stress_all.2216389160 May 05 12:42:44 PM PDT 24 May 05 12:43:35 PM PDT 24 4288712157 ps
T338 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3720971675 May 05 12:42:22 PM PDT 24 May 05 12:43:37 PM PDT 24 36991750720 ps
T339 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1532858798 May 05 12:42:40 PM PDT 24 May 05 12:42:54 PM PDT 24 2096246418 ps
T340 /workspace/coverage/default/42.rom_ctrl_alert_test.2895045454 May 05 12:42:48 PM PDT 24 May 05 12:43:14 PM PDT 24 10157532656 ps
T341 /workspace/coverage/default/47.rom_ctrl_smoke.1204569875 May 05 12:42:49 PM PDT 24 May 05 12:43:50 PM PDT 24 6728938507 ps
T342 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3033552884 May 05 12:42:46 PM PDT 24 May 05 12:43:22 PM PDT 24 6933131238 ps
T343 /workspace/coverage/default/15.rom_ctrl_alert_test.2907999887 May 05 12:42:20 PM PDT 24 May 05 12:42:36 PM PDT 24 1842491864 ps
T48 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2023346857 May 05 12:42:21 PM PDT 24 May 05 12:55:39 PM PDT 24 22610688571 ps
T344 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.237069871 May 05 12:42:46 PM PDT 24 May 05 12:43:45 PM PDT 24 13188524051 ps
T345 /workspace/coverage/default/40.rom_ctrl_alert_test.2772745835 May 05 12:42:45 PM PDT 24 May 05 12:43:12 PM PDT 24 11461842178 ps
T346 /workspace/coverage/default/47.rom_ctrl_alert_test.1722889034 May 05 12:42:47 PM PDT 24 May 05 12:43:18 PM PDT 24 3589418046 ps
T347 /workspace/coverage/default/45.rom_ctrl_stress_all.2264572519 May 05 12:42:48 PM PDT 24 May 05 12:44:18 PM PDT 24 7720273164 ps
T348 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2889812364 May 05 12:42:43 PM PDT 24 May 05 12:43:15 PM PDT 24 6825419781 ps
T349 /workspace/coverage/default/38.rom_ctrl_stress_all.3340494036 May 05 12:42:46 PM PDT 24 May 05 12:44:58 PM PDT 24 49812404711 ps
T350 /workspace/coverage/default/30.rom_ctrl_stress_all.1157035284 May 05 12:42:44 PM PDT 24 May 05 12:44:16 PM PDT 24 39243129892 ps
T351 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.549836991 May 05 12:43:02 PM PDT 24 May 05 12:43:23 PM PDT 24 4423243035 ps
T352 /workspace/coverage/default/21.rom_ctrl_alert_test.2815804008 May 05 12:42:42 PM PDT 24 May 05 12:43:04 PM PDT 24 2096871750 ps
T353 /workspace/coverage/default/32.rom_ctrl_alert_test.1061328406 May 05 12:42:47 PM PDT 24 May 05 12:43:18 PM PDT 24 3425091817 ps
T354 /workspace/coverage/default/17.rom_ctrl_smoke.1341909144 May 05 12:42:17 PM PDT 24 May 05 12:43:17 PM PDT 24 23851286979 ps
T355 /workspace/coverage/default/34.rom_ctrl_alert_test.533833876 May 05 12:42:47 PM PDT 24 May 05 12:43:09 PM PDT 24 3845279738 ps
T356 /workspace/coverage/default/8.rom_ctrl_stress_all.1555140165 May 05 12:42:40 PM PDT 24 May 05 12:42:58 PM PDT 24 194840669 ps
T357 /workspace/coverage/default/18.rom_ctrl_alert_test.4250492469 May 05 12:42:27 PM PDT 24 May 05 12:42:53 PM PDT 24 9840911640 ps
T49 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3936992036 May 05 12:42:01 PM PDT 24 May 05 12:42:11 PM PDT 24 373254693 ps
T61 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1346370801 May 05 12:42:21 PM PDT 24 May 05 12:42:44 PM PDT 24 1956473597 ps
T62 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.521702570 May 05 12:42:21 PM PDT 24 May 05 12:42:36 PM PDT 24 768703788 ps
T50 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2237027443 May 05 12:42:04 PM PDT 24 May 05 12:43:41 PM PDT 24 2932055129 ps
T100 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2895055105 May 05 12:42:15 PM PDT 24 May 05 12:42:46 PM PDT 24 11379979177 ps
T95 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3988082219 May 05 12:41:56 PM PDT 24 May 05 12:42:30 PM PDT 24 17377929526 ps
T96 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1541228683 May 05 12:42:13 PM PDT 24 May 05 12:42:46 PM PDT 24 13869512187 ps
T51 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1822210016 May 05 12:42:13 PM PDT 24 May 05 12:44:52 PM PDT 24 3638197033 ps
T358 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3100967078 May 05 12:41:55 PM PDT 24 May 05 12:42:05 PM PDT 24 172709949 ps
T52 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3386077025 May 05 12:41:57 PM PDT 24 May 05 12:42:29 PM PDT 24 20243578542 ps
T68 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.300510338 May 05 12:42:07 PM PDT 24 May 05 12:42:19 PM PDT 24 688241303 ps
T97 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2872798445 May 05 12:41:57 PM PDT 24 May 05 12:42:07 PM PDT 24 689188137 ps
T60 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3874239242 May 05 12:41:54 PM PDT 24 May 05 12:44:33 PM PDT 24 4430887718 ps
T69 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3454734888 May 05 12:41:56 PM PDT 24 May 05 12:42:21 PM PDT 24 8856390847 ps
T106 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3717840983 May 05 12:41:59 PM PDT 24 May 05 12:44:44 PM PDT 24 3714258173 ps
T359 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1226448409 May 05 12:41:51 PM PDT 24 May 05 12:42:00 PM PDT 24 179491233 ps
T105 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1218238380 May 05 12:42:16 PM PDT 24 May 05 12:45:05 PM PDT 24 5380260567 ps
T360 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4284689192 May 05 12:41:57 PM PDT 24 May 05 12:42:12 PM PDT 24 174402010 ps
T70 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2711061809 May 05 12:42:00 PM PDT 24 May 05 12:43:51 PM PDT 24 23896665870 ps
T111 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2822541486 May 05 12:42:13 PM PDT 24 May 05 12:43:41 PM PDT 24 4911961684 ps
T101 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.233416478 May 05 12:42:01 PM PDT 24 May 05 12:42:30 PM PDT 24 3501500014 ps
T71 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.748277958 May 05 12:42:36 PM PDT 24 May 05 12:43:33 PM PDT 24 1081408302 ps
T72 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.669543737 May 05 12:42:00 PM PDT 24 May 05 12:42:22 PM PDT 24 39178339748 ps
T361 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2095673974 May 05 12:41:55 PM PDT 24 May 05 12:42:28 PM PDT 24 3944424925 ps
T98 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.393115702 May 05 12:41:50 PM PDT 24 May 05 12:42:22 PM PDT 24 3812410333 ps
T73 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.917927954 May 05 12:41:58 PM PDT 24 May 05 12:42:27 PM PDT 24 2427315366 ps
T74 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3552477253 May 05 12:42:06 PM PDT 24 May 05 12:42:26 PM PDT 24 3768814103 ps
T110 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3389858697 May 05 12:41:56 PM PDT 24 May 05 12:44:34 PM PDT 24 657456131 ps
T75 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2773701509 May 05 12:42:32 PM PDT 24 May 05 12:45:43 PM PDT 24 172167774760 ps
T76 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2252910410 May 05 12:41:56 PM PDT 24 May 05 12:42:25 PM PDT 24 3265322050 ps
T362 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.305723926 May 05 12:41:54 PM PDT 24 May 05 12:42:19 PM PDT 24 20608556271 ps
T363 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.523765938 May 05 12:42:15 PM PDT 24 May 05 12:42:42 PM PDT 24 26575297981 ps
T364 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1194128257 May 05 12:41:50 PM PDT 24 May 05 12:42:04 PM PDT 24 1019295158 ps
T365 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3336261909 May 05 12:41:57 PM PDT 24 May 05 12:42:14 PM PDT 24 1822121815 ps
T113 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.768778715 May 05 12:41:56 PM PDT 24 May 05 12:43:31 PM PDT 24 2375742052 ps
T366 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1004828077 May 05 12:41:59 PM PDT 24 May 05 12:42:19 PM PDT 24 1618920994 ps
T77 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2228094316 May 05 12:42:12 PM PDT 24 May 05 12:42:34 PM PDT 24 6146422756 ps
T367 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4093399330 May 05 12:41:58 PM PDT 24 May 05 12:42:25 PM PDT 24 11039135853 ps
T99 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1752303001 May 05 12:42:00 PM PDT 24 May 05 12:44:26 PM PDT 24 31115420695 ps
T368 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1406937950 May 05 12:41:53 PM PDT 24 May 05 12:42:11 PM PDT 24 10915487479 ps
T103 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1369997600 May 05 12:41:58 PM PDT 24 May 05 12:43:39 PM PDT 24 23015222237 ps
T84 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4106464258 May 05 12:42:05 PM PDT 24 May 05 12:44:55 PM PDT 24 20024805642 ps
T85 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.704309784 May 05 12:41:57 PM PDT 24 May 05 12:42:15 PM PDT 24 2346141864 ps
T104 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4072784984 May 05 12:42:00 PM PDT 24 May 05 12:43:20 PM PDT 24 89241024884 ps
T369 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3513369015 May 05 12:41:57 PM PDT 24 May 05 12:42:20 PM PDT 24 1968478835 ps
T86 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1448195009 May 05 12:42:13 PM PDT 24 May 05 12:42:46 PM PDT 24 8014811069 ps
T370 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3489012392 May 05 12:41:57 PM PDT 24 May 05 12:42:07 PM PDT 24 211505029 ps
T371 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3829527018 May 05 12:42:12 PM PDT 24 May 05 12:42:44 PM PDT 24 24630216770 ps
T372 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4169941128 May 05 12:41:57 PM PDT 24 May 05 12:42:21 PM PDT 24 1571723572 ps
T373 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1066129695 May 05 12:41:55 PM PDT 24 May 05 12:42:11 PM PDT 24 1646518846 ps
T87 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1637164188 May 05 12:42:15 PM PDT 24 May 05 12:42:46 PM PDT 24 14755990663 ps
T115 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1328371935 May 05 12:41:56 PM PDT 24 May 05 12:44:49 PM PDT 24 32617996226 ps
T374 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3377735192 May 05 12:41:56 PM PDT 24 May 05 12:42:22 PM PDT 24 37807658039 ps
T375 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.646312292 May 05 12:42:10 PM PDT 24 May 05 12:42:34 PM PDT 24 2623974426 ps
T376 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3073584896 May 05 12:41:59 PM PDT 24 May 05 12:42:35 PM PDT 24 15582976117 ps
T377 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3903860101 May 05 12:41:56 PM PDT 24 May 05 12:42:13 PM PDT 24 8924353466 ps
T378 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2024798543 May 05 12:41:58 PM PDT 24 May 05 12:42:12 PM PDT 24 174658784 ps
T379 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3086004231 May 05 12:42:37 PM PDT 24 May 05 12:43:05 PM PDT 24 3285614465 ps
T89 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2758143071 May 05 12:41:52 PM PDT 24 May 05 12:42:49 PM PDT 24 3667486791 ps
T380 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2667743027 May 05 12:41:56 PM PDT 24 May 05 12:42:25 PM PDT 24 5118371320 ps
T381 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.400032185 May 05 12:41:56 PM PDT 24 May 05 12:42:54 PM PDT 24 2027576427 ps
T382 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1874630026 May 05 12:42:05 PM PDT 24 May 05 12:42:45 PM PDT 24 16838732254 ps
T108 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.935653539 May 05 12:41:55 PM PDT 24 May 05 12:43:38 PM PDT 24 16595160008 ps
T383 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1395041304 May 05 12:42:13 PM PDT 24 May 05 12:42:45 PM PDT 24 6516686768 ps
T384 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4138885699 May 05 12:41:59 PM PDT 24 May 05 12:42:34 PM PDT 24 4266562278 ps
T90 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.463877488 May 05 12:41:52 PM PDT 24 May 05 12:43:41 PM PDT 24 8664411069 ps
T385 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2864293644 May 05 12:41:57 PM PDT 24 May 05 12:42:27 PM PDT 24 2779322059 ps
T386 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2612154793 May 05 12:42:08 PM PDT 24 May 05 12:42:18 PM PDT 24 339368798 ps
T387 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.481797670 May 05 12:41:54 PM PDT 24 May 05 12:42:14 PM PDT 24 2691188227 ps
T388 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1704284149 May 05 12:41:58 PM PDT 24 May 05 12:42:29 PM PDT 24 24316419266 ps
T389 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.559619688 May 05 12:41:56 PM PDT 24 May 05 12:42:06 PM PDT 24 176441902 ps
T390 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.235587388 May 05 12:42:01 PM PDT 24 May 05 12:42:25 PM PDT 24 4275718706 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4293004305 May 05 12:41:57 PM PDT 24 May 05 12:42:16 PM PDT 24 1438443921 ps
T107 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2112806575 May 05 12:42:32 PM PDT 24 May 05 12:44:03 PM PDT 24 7055535501 ps
T392 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.415133487 May 05 12:41:53 PM PDT 24 May 05 12:42:18 PM PDT 24 8860360283 ps
T88 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2045858048 May 05 12:41:57 PM PDT 24 May 05 12:42:27 PM PDT 24 3709954810 ps
T393 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3286253792 May 05 12:41:55 PM PDT 24 May 05 12:42:08 PM PDT 24 1763956390 ps
T394 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3688820390 May 05 12:42:14 PM PDT 24 May 05 12:42:46 PM PDT 24 7839511956 ps
T116 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.449580110 May 05 12:41:54 PM PDT 24 May 05 12:43:23 PM PDT 24 1017615893 ps
T91 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2911799306 May 05 12:42:05 PM PDT 24 May 05 12:43:01 PM PDT 24 2740124083 ps
T395 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3396550322 May 05 12:41:53 PM PDT 24 May 05 12:42:10 PM PDT 24 956842558 ps
T396 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.25468632 May 05 12:42:00 PM PDT 24 May 05 12:44:38 PM PDT 24 3230606725 ps
T397 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3570975580 May 05 12:42:18 PM PDT 24 May 05 12:42:27 PM PDT 24 170709873 ps
T398 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1066372316 May 05 12:42:00 PM PDT 24 May 05 12:42:57 PM PDT 24 6065443853 ps
T399 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2610744639 May 05 12:41:55 PM PDT 24 May 05 12:42:06 PM PDT 24 259291944 ps
T400 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.462495481 May 05 12:42:16 PM PDT 24 May 05 12:42:53 PM PDT 24 14090452893 ps
T401 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4212927905 May 05 12:42:08 PM PDT 24 May 05 12:42:28 PM PDT 24 2044657728 ps
T402 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.534515697 May 05 12:41:56 PM PDT 24 May 05 12:42:31 PM PDT 24 6026295695 ps
T403 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2729651885 May 05 12:42:03 PM PDT 24 May 05 12:42:26 PM PDT 24 24540452941 ps
T112 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2884680527 May 05 12:42:01 PM PDT 24 May 05 12:44:47 PM PDT 24 2822028769 ps
T404 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2617400197 May 05 12:41:54 PM PDT 24 May 05 12:42:21 PM PDT 24 2908203672 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2844501780 May 05 12:41:52 PM PDT 24 May 05 12:42:24 PM PDT 24 3879483859 ps
T406 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3227318327 May 05 12:42:26 PM PDT 24 May 05 12:42:51 PM PDT 24 10223855672 ps
T94 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.370098420 May 05 12:42:18 PM PDT 24 May 05 12:44:52 PM PDT 24 57849565026 ps
T407 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3026928496 May 05 12:41:55 PM PDT 24 May 05 12:42:09 PM PDT 24 2626163743 ps
T408 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1567218793 May 05 12:42:12 PM PDT 24 May 05 12:43:05 PM PDT 24 5609415436 ps
T92 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.162439835 May 05 12:41:51 PM PDT 24 May 05 12:42:48 PM PDT 24 1084122104 ps
T409 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3623685598 May 05 12:41:56 PM PDT 24 May 05 12:42:06 PM PDT 24 307327033 ps
T410 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1564440161 May 05 12:42:20 PM PDT 24 May 05 12:42:45 PM PDT 24 2748661192 ps
T411 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.358561894 May 05 12:42:00 PM PDT 24 May 05 12:42:32 PM PDT 24 8238604827 ps
T412 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1540147314 May 05 12:42:26 PM PDT 24 May 05 12:45:23 PM PDT 24 21985884075 ps
T413 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.278591578 May 05 12:42:21 PM PDT 24 May 05 12:42:41 PM PDT 24 2619683341 ps
T114 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2002396248 May 05 12:41:57 PM PDT 24 May 05 12:44:41 PM PDT 24 1457698084 ps
T414 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3631410005 May 05 12:42:23 PM PDT 24 May 05 12:43:01 PM PDT 24 19932440080 ps
T415 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2937116231 May 05 12:41:56 PM PDT 24 May 05 12:42:09 PM PDT 24 231696580 ps
T416 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.282063622 May 05 12:41:55 PM PDT 24 May 05 12:42:05 PM PDT 24 972097171 ps
T93 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4064410623 May 05 12:42:13 PM PDT 24 May 05 12:44:09 PM PDT 24 39041865866 ps
T417 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1833677965 May 05 12:41:56 PM PDT 24 May 05 12:42:07 PM PDT 24 167805444 ps
T418 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3998692188 May 05 12:41:58 PM PDT 24 May 05 12:42:22 PM PDT 24 4618361581 ps
T419 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2716106286 May 05 12:42:10 PM PDT 24 May 05 12:43:07 PM PDT 24 1063399384 ps
T420 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2833683415 May 05 12:42:16 PM PDT 24 May 05 12:42:34 PM PDT 24 1480229748 ps
T421 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2271353690 May 05 12:42:21 PM PDT 24 May 05 12:42:32 PM PDT 24 298310492 ps
T422 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.946133641 May 05 12:42:01 PM PDT 24 May 05 12:42:34 PM PDT 24 3783449148 ps
T423 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4279632692 May 05 12:41:54 PM PDT 24 May 05 12:42:20 PM PDT 24 14309025318 ps
T424 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3984478970 May 05 12:42:03 PM PDT 24 May 05 12:42:25 PM PDT 24 2225544099 ps
T425 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3598343589 May 05 12:42:28 PM PDT 24 May 05 12:43:27 PM PDT 24 6234957739 ps
T426 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4139438373 May 05 12:41:57 PM PDT 24 May 05 12:42:28 PM PDT 24 3437034526 ps
T427 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4078666633 May 05 12:42:01 PM PDT 24 May 05 12:42:35 PM PDT 24 3488947147 ps
T428 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3075424334 May 05 12:41:59 PM PDT 24 May 05 12:42:13 PM PDT 24 202994634 ps
T429 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3186131909 May 05 12:41:55 PM PDT 24 May 05 12:42:05 PM PDT 24 170918169 ps
T430 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1291978556 May 05 12:41:57 PM PDT 24 May 05 12:42:30 PM PDT 24 3431325114 ps
T431 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4118064819 May 05 12:41:58 PM PDT 24 May 05 12:42:16 PM PDT 24 4821777030 ps
T109 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1484152157 May 05 12:42:04 PM PDT 24 May 05 12:45:00 PM PDT 24 16902659782 ps
T432 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3978418910 May 05 12:42:28 PM PDT 24 May 05 12:42:40 PM PDT 24 174270423 ps
T433 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.32505855 May 05 12:42:12 PM PDT 24 May 05 12:42:30 PM PDT 24 6752777647 ps
T434 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2565530153 May 05 12:41:55 PM PDT 24 May 05 12:42:24 PM PDT 24 3346397518 ps
T435 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4262677476 May 05 12:42:27 PM PDT 24 May 05 12:43:38 PM PDT 24 7510436051 ps
T436 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.642634959 May 05 12:42:12 PM PDT 24 May 05 12:42:27 PM PDT 24 914733697 ps
T437 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3469326568 May 05 12:42:02 PM PDT 24 May 05 12:42:17 PM PDT 24 2901928809 ps
T438 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2436929409 May 05 12:41:57 PM PDT 24 May 05 12:42:19 PM PDT 24 1448552478 ps
T439 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1626925066 May 05 12:41:55 PM PDT 24 May 05 12:42:18 PM PDT 24 3525295715 ps
T440 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1455606150 May 05 12:41:54 PM PDT 24 May 05 12:42:21 PM PDT 24 3038549450 ps
T441 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1787948502 May 05 12:42:22 PM PDT 24 May 05 12:42:39 PM PDT 24 2261440294 ps
T442 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4031167819 May 05 12:41:58 PM PDT 24 May 05 12:42:12 PM PDT 24 2299771093 ps
T443 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3643656392 May 05 12:41:57 PM PDT 24 May 05 12:42:28 PM PDT 24 5720359146 ps
T444 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2773300364 May 05 12:41:56 PM PDT 24 May 05 12:42:27 PM PDT 24 7342782725 ps
T445 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2440933886 May 05 12:41:56 PM PDT 24 May 05 12:44:52 PM PDT 24 8487739257 ps
T446 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3709608394 May 05 12:41:59 PM PDT 24 May 05 12:44:42 PM PDT 24 3205712292 ps
T447 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2508923157 May 05 12:42:12 PM PDT 24 May 05 12:43:20 PM PDT 24 76905146098 ps
T448 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2257834949 May 05 12:41:51 PM PDT 24 May 05 12:42:05 PM PDT 24 2122020483 ps
T449 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1048716108 May 05 12:42:15 PM PDT 24 May 05 12:42:24 PM PDT 24 687924504 ps
T450 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2526635077 May 05 12:42:03 PM PDT 24 May 05 12:42:44 PM PDT 24 8545244973 ps
T451 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.261418475 May 05 12:41:57 PM PDT 24 May 05 12:42:18 PM PDT 24 1731755609 ps
T452 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.891805129 May 05 12:41:54 PM PDT 24 May 05 12:42:23 PM PDT 24 9183464031 ps
T453 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.99001847 May 05 12:42:00 PM PDT 24 May 05 12:43:32 PM PDT 24 8784310946 ps

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2050855818
Short name T5
Test name
Test status
Simulation time 93945704463 ps
CPU time 479.44 seconds
Started May 05 12:42:41 PM PDT 24
Finished May 05 12:50:41 PM PDT 24
Peak memory 238452 kb
Host smart-f89f721b-1a5f-4626-82de-018d86979e81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050855818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2050855818
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2988423063
Short name T14
Test name
Test status
Simulation time 15479984661 ps
CPU time 303.77 seconds
Started May 05 12:42:45 PM PDT 24
Finished May 05 12:47:52 PM PDT 24
Peak memory 236344 kb
Host smart-1a4564e4-cd19-4618-bbbd-76fededd0607
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988423063 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.2988423063
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2762014445
Short name T181
Test name
Test status
Simulation time 542414669232 ps
CPU time 786.73 seconds
Started May 05 12:42:49 PM PDT 24
Finished May 05 12:55:58 PM PDT 24
Peak memory 234380 kb
Host smart-efb07e2f-a95b-4d58-ad10-779dbbd88916
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762014445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2762014445
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.454120722
Short name T4
Test name
Test status
Simulation time 37942393554 ps
CPU time 47.09 seconds
Started May 05 12:42:30 PM PDT 24
Finished May 05 12:43:18 PM PDT 24
Peak memory 218596 kb
Host smart-d1d30f2d-2bb6-4a3d-9a09-89948efd6a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454120722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.454120722
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3717840983
Short name T106
Test name
Test status
Simulation time 3714258173 ps
CPU time 163.3 seconds
Started May 05 12:41:59 PM PDT 24
Finished May 05 12:44:44 PM PDT 24
Peak memory 213140 kb
Host smart-eb549703-6eb5-4641-abd6-388bbf081cec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717840983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3717840983
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2575435254
Short name T32
Test name
Test status
Simulation time 4061962057 ps
CPU time 246.63 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:46:06 PM PDT 24
Peak memory 238512 kb
Host smart-de705d85-66e6-4d08-b139-2218407db13c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575435254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2575435254
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2773701509
Short name T75
Test name
Test status
Simulation time 172167774760 ps
CPU time 189.53 seconds
Started May 05 12:42:32 PM PDT 24
Finished May 05 12:45:43 PM PDT 24
Peak memory 214684 kb
Host smart-f9b59e37-43ee-4190-9240-5cbac58d33e0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773701509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2773701509
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2901411642
Short name T9
Test name
Test status
Simulation time 345487316 ps
CPU time 8.32 seconds
Started May 05 12:42:17 PM PDT 24
Finished May 05 12:42:26 PM PDT 24
Peak memory 211756 kb
Host smart-16bddfd7-20ae-444a-8f66-6350ecd8da96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901411642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2901411642
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2884680527
Short name T112
Test name
Test status
Simulation time 2822028769 ps
CPU time 164.45 seconds
Started May 05 12:42:01 PM PDT 24
Finished May 05 12:44:47 PM PDT 24
Peak memory 214140 kb
Host smart-1f32ab22-2ed7-4a50-9445-862bcba28e22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884680527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2884680527
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2894524202
Short name T124
Test name
Test status
Simulation time 80060603970 ps
CPU time 137.38 seconds
Started May 05 12:42:34 PM PDT 24
Finished May 05 12:44:52 PM PDT 24
Peak memory 220744 kb
Host smart-75fe1d7f-e667-4763-bfa8-fd4c44325837
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894524202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2894524202
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3122147635
Short name T25
Test name
Test status
Simulation time 22800653826 ps
CPU time 57.67 seconds
Started May 05 12:41:59 PM PDT 24
Finished May 05 12:42:58 PM PDT 24
Peak memory 214304 kb
Host smart-621532ce-f3c1-4adb-8a07-5353848a7cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122147635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3122147635
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.874159058
Short name T20
Test name
Test status
Simulation time 342403592 ps
CPU time 19.09 seconds
Started May 05 12:42:26 PM PDT 24
Finished May 05 12:42:45 PM PDT 24
Peak memory 215320 kb
Host smart-0bcc90bc-e284-4601-95c6-cfdd65a82778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874159058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.874159058
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4135429451
Short name T24
Test name
Test status
Simulation time 23109900068 ps
CPU time 53.25 seconds
Started May 05 12:42:50 PM PDT 24
Finished May 05 12:43:45 PM PDT 24
Peak memory 214520 kb
Host smart-16623248-52fd-4f31-aa8e-0cb2fbf7ccef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135429451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4135429451
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1822210016
Short name T51
Test name
Test status
Simulation time 3638197033 ps
CPU time 158.42 seconds
Started May 05 12:42:13 PM PDT 24
Finished May 05 12:44:52 PM PDT 24
Peak memory 213200 kb
Host smart-8f4ce5dd-42d8-4a78-8016-d887e73deea2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822210016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1822210016
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.370098420
Short name T94
Test name
Test status
Simulation time 57849565026 ps
CPU time 153.04 seconds
Started May 05 12:42:18 PM PDT 24
Finished May 05 12:44:52 PM PDT 24
Peak memory 214700 kb
Host smart-c7704c3a-ef93-4412-af6c-3397ecd7de51
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370098420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.370098420
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3705137258
Short name T17
Test name
Test status
Simulation time 163474638091 ps
CPU time 1378.36 seconds
Started May 05 12:42:44 PM PDT 24
Finished May 05 01:05:44 PM PDT 24
Peak memory 237940 kb
Host smart-db72f0de-2b3d-4063-8de5-3b04aa0aff11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705137258 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3705137258
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2045858048
Short name T88
Test name
Test status
Simulation time 3709954810 ps
CPU time 28.68 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:27 PM PDT 24
Peak memory 211016 kb
Host smart-2bc1ce07-b8be-4e1d-b1da-b4aab14f66d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045858048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2045858048
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.669543737
Short name T72
Test name
Test status
Simulation time 39178339748 ps
CPU time 20.71 seconds
Started May 05 12:42:00 PM PDT 24
Finished May 05 12:42:22 PM PDT 24
Peak memory 211944 kb
Host smart-e910b78c-461a-4ce9-a548-9ef5fdd22e06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669543737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.669543737
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1529919359
Short name T67
Test name
Test status
Simulation time 32819019276 ps
CPU time 29.06 seconds
Started May 05 12:41:59 PM PDT 24
Finished May 05 12:42:30 PM PDT 24
Peak memory 213272 kb
Host smart-1df86d3a-0923-4e7d-a7ad-80640919018e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1529919359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1529919359
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3073463914
Short name T119
Test name
Test status
Simulation time 1548212194 ps
CPU time 19.8 seconds
Started May 05 12:42:25 PM PDT 24
Finished May 05 12:42:50 PM PDT 24
Peak memory 216512 kb
Host smart-53fb7368-961c-4260-be12-f73f10384430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073463914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3073463914
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3100967078
Short name T358
Test name
Test status
Simulation time 172709949 ps
CPU time 8.22 seconds
Started May 05 12:41:55 PM PDT 24
Finished May 05 12:42:05 PM PDT 24
Peak memory 210680 kb
Host smart-06e8a551-29d9-4339-b559-25aae191182e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100967078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3100967078
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2526635077
Short name T450
Test name
Test status
Simulation time 8545244973 ps
CPU time 39.47 seconds
Started May 05 12:42:03 PM PDT 24
Finished May 05 12:42:44 PM PDT 24
Peak memory 211476 kb
Host smart-9275618b-2198-4511-870b-8e5bf21fb537
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526635077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2526635077
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1406937950
Short name T368
Test name
Test status
Simulation time 10915487479 ps
CPU time 16.83 seconds
Started May 05 12:41:53 PM PDT 24
Finished May 05 12:42:11 PM PDT 24
Peak memory 216280 kb
Host smart-c70e0ef6-7b7f-42fd-ba69-1962da634044
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406937950 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1406937950
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4138885699
Short name T384
Test name
Test status
Simulation time 4266562278 ps
CPU time 32.56 seconds
Started May 05 12:41:59 PM PDT 24
Finished May 05 12:42:34 PM PDT 24
Peak memory 210324 kb
Host smart-ef4770b5-ce88-4267-b473-ed4e1ff6fa7e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138885699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4138885699
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2773300364
Short name T444
Test name
Test status
Simulation time 7342782725 ps
CPU time 29.24 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:42:27 PM PDT 24
Peak memory 210408 kb
Host smart-6f21e5c5-248d-4722-9777-1d8274b0deb6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773300364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2773300364
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.162439835
Short name T92
Test name
Test status
Simulation time 1084122104 ps
CPU time 56.16 seconds
Started May 05 12:41:51 PM PDT 24
Finished May 05 12:42:48 PM PDT 24
Peak memory 212892 kb
Host smart-07a1c07e-6b8e-435a-8d66-c77f1cdedc88
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162439835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.162439835
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.646312292
Short name T375
Test name
Test status
Simulation time 2623974426 ps
CPU time 23.9 seconds
Started May 05 12:42:10 PM PDT 24
Finished May 05 12:42:34 PM PDT 24
Peak memory 211524 kb
Host smart-0b9c05fa-e394-4f41-9542-cf8967e86c0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646312292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.646312292
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.415133487
Short name T392
Test name
Test status
Simulation time 8860360283 ps
CPU time 23.09 seconds
Started May 05 12:41:53 PM PDT 24
Finished May 05 12:42:18 PM PDT 24
Peak memory 217568 kb
Host smart-b8117e59-6c90-4197-880e-08127b9099f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415133487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.415133487
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1455606150
Short name T440
Test name
Test status
Simulation time 3038549450 ps
CPU time 25.76 seconds
Started May 05 12:41:54 PM PDT 24
Finished May 05 12:42:21 PM PDT 24
Peak memory 218648 kb
Host smart-b7f73ad3-c942-41d5-ade0-87fe40a0782c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455606150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1455606150
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4279632692
Short name T423
Test name
Test status
Simulation time 14309025318 ps
CPU time 25.15 seconds
Started May 05 12:41:54 PM PDT 24
Finished May 05 12:42:20 PM PDT 24
Peak memory 211448 kb
Host smart-857be01b-5de6-4794-93be-74f7a6309aa9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279632692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4279632692
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.534515697
Short name T402
Test name
Test status
Simulation time 6026295695 ps
CPU time 33.99 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:42:31 PM PDT 24
Peak memory 211376 kb
Host smart-ad08508d-b7d1-4e5b-8422-76320747410a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534515697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.534515697
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3984478970
Short name T424
Test name
Test status
Simulation time 2225544099 ps
CPU time 20.89 seconds
Started May 05 12:42:03 PM PDT 24
Finished May 05 12:42:25 PM PDT 24
Peak memory 215184 kb
Host smart-ef511a76-fe93-4f49-9ca4-fd20ffdf3c4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984478970 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3984478970
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3336261909
Short name T365
Test name
Test status
Simulation time 1822121815 ps
CPU time 14.63 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:14 PM PDT 24
Peak memory 211052 kb
Host smart-5a8f2029-f9f0-4489-8453-6e008ee903bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336261909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3336261909
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1833677965
Short name T417
Test name
Test status
Simulation time 167805444 ps
CPU time 8.28 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:42:07 PM PDT 24
Peak memory 210240 kb
Host smart-5144001c-0d4a-4f7d-9a5f-48636155f700
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833677965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1833677965
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.481797670
Short name T387
Test name
Test status
Simulation time 2691188227 ps
CPU time 19.16 seconds
Started May 05 12:41:54 PM PDT 24
Finished May 05 12:42:14 PM PDT 24
Peak memory 210420 kb
Host smart-32ee3589-9ec2-4c68-a33a-9a32645e2e8d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481797670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
481797670
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.393115702
Short name T98
Test name
Test status
Simulation time 3812410333 ps
CPU time 30.83 seconds
Started May 05 12:41:50 PM PDT 24
Finished May 05 12:42:22 PM PDT 24
Peak memory 211576 kb
Host smart-3b6c9eb7-787a-4b91-8fb0-86a5fa22bdfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393115702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.393115702
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4284689192
Short name T360
Test name
Test status
Simulation time 174402010 ps
CPU time 12.58 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:12 PM PDT 24
Peak memory 218688 kb
Host smart-20add9c8-0c9a-4edb-acba-853c6aa1688b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284689192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.4284689192
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.768778715
Short name T113
Test name
Test status
Simulation time 2375742052 ps
CPU time 93.77 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:43:31 PM PDT 24
Peak memory 212836 kb
Host smart-6ca0b81e-12b2-45b0-bb0d-3775d30fd9ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768778715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.768778715
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3286253792
Short name T393
Test name
Test status
Simulation time 1763956390 ps
CPU time 12.17 seconds
Started May 05 12:41:55 PM PDT 24
Finished May 05 12:42:08 PM PDT 24
Peak memory 216488 kb
Host smart-fad176b6-fcb8-4260-bc1c-b08477bac3ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286253792 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3286253792
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.704309784
Short name T85
Test name
Test status
Simulation time 2346141864 ps
CPU time 15.45 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:15 PM PDT 24
Peak memory 210484 kb
Host smart-8c939993-956a-4875-9ff4-96d3a23734aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704309784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.704309784
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4072784984
Short name T104
Test name
Test status
Simulation time 89241024884 ps
CPU time 78.09 seconds
Started May 05 12:42:00 PM PDT 24
Finished May 05 12:43:20 PM PDT 24
Peak memory 212584 kb
Host smart-c2ba9822-c6e7-49d6-bbb9-e039c7857d08
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072784984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.4072784984
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3513369015
Short name T369
Test name
Test status
Simulation time 1968478835 ps
CPU time 20.06 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:20 PM PDT 24
Peak memory 211408 kb
Host smart-e42bd864-3e92-4240-b809-c081fdd50e71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513369015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3513369015
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.300510338
Short name T68
Test name
Test status
Simulation time 688241303 ps
CPU time 11.14 seconds
Started May 05 12:42:07 PM PDT 24
Finished May 05 12:42:19 PM PDT 24
Peak memory 216632 kb
Host smart-2624adf9-ce3d-4a19-8d36-19b7b5a309b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300510338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.300510338
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2112806575
Short name T107
Test name
Test status
Simulation time 7055535501 ps
CPU time 89.96 seconds
Started May 05 12:42:32 PM PDT 24
Finished May 05 12:44:03 PM PDT 24
Peak memory 213236 kb
Host smart-135874ef-09c3-4a5a-a9aa-798fddb48183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112806575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2112806575
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4118064819
Short name T431
Test name
Test status
Simulation time 4821777030 ps
CPU time 15.6 seconds
Started May 05 12:41:58 PM PDT 24
Finished May 05 12:42:16 PM PDT 24
Peak memory 215116 kb
Host smart-be894a8a-d9fd-4028-a962-023ced0f31d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118064819 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4118064819
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.917927954
Short name T73
Test name
Test status
Simulation time 2427315366 ps
CPU time 22.58 seconds
Started May 05 12:41:58 PM PDT 24
Finished May 05 12:42:27 PM PDT 24
Peak memory 211060 kb
Host smart-e823a300-ee57-4519-a7b4-b3d398816fad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917927954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.917927954
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1752303001
Short name T99
Test name
Test status
Simulation time 31115420695 ps
CPU time 144.16 seconds
Started May 05 12:42:00 PM PDT 24
Finished May 05 12:44:26 PM PDT 24
Peak memory 214812 kb
Host smart-83d464c4-99fb-464e-94d4-e5ba27999189
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752303001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1752303001
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3489012392
Short name T370
Test name
Test status
Simulation time 211505029 ps
CPU time 8.25 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:07 PM PDT 24
Peak memory 210360 kb
Host smart-5c83a5eb-58f1-4825-a116-116b4db995bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489012392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3489012392
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.523765938
Short name T363
Test name
Test status
Simulation time 26575297981 ps
CPU time 25.63 seconds
Started May 05 12:42:15 PM PDT 24
Finished May 05 12:42:42 PM PDT 24
Peak memory 218800 kb
Host smart-0bcea42a-928f-48d6-9ff5-efac52279def
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523765938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.523765938
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2237027443
Short name T50
Test name
Test status
Simulation time 2932055129 ps
CPU time 95.67 seconds
Started May 05 12:42:04 PM PDT 24
Finished May 05 12:43:41 PM PDT 24
Peak memory 218656 kb
Host smart-f6974856-f78c-4bcb-a098-379a371c91ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237027443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2237027443
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2612154793
Short name T386
Test name
Test status
Simulation time 339368798 ps
CPU time 9.36 seconds
Started May 05 12:42:08 PM PDT 24
Finished May 05 12:42:18 PM PDT 24
Peak memory 216032 kb
Host smart-fc9a5757-42db-4a84-bf59-d89dd8d9e9a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612154793 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2612154793
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1448195009
Short name T86
Test name
Test status
Simulation time 8014811069 ps
CPU time 31.81 seconds
Started May 05 12:42:13 PM PDT 24
Finished May 05 12:42:46 PM PDT 24
Peak memory 211816 kb
Host smart-f75217b0-7589-432b-81b5-ad93d3ea6f8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448195009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1448195009
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2716106286
Short name T419
Test name
Test status
Simulation time 1063399384 ps
CPU time 55.97 seconds
Started May 05 12:42:10 PM PDT 24
Finished May 05 12:43:07 PM PDT 24
Peak memory 214056 kb
Host smart-fa945070-2427-4b2f-8e02-e491a7a87622
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716106286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2716106286
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2617400197
Short name T404
Test name
Test status
Simulation time 2908203672 ps
CPU time 26 seconds
Started May 05 12:41:54 PM PDT 24
Finished May 05 12:42:21 PM PDT 24
Peak memory 211176 kb
Host smart-3a9af3e6-f32e-4323-8be3-3f18ac25c225
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617400197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2617400197
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1395041304
Short name T383
Test name
Test status
Simulation time 6516686768 ps
CPU time 31.36 seconds
Started May 05 12:42:13 PM PDT 24
Finished May 05 12:42:45 PM PDT 24
Peak memory 217168 kb
Host smart-88cbc859-cf22-45bb-b7d2-d792ab7d92c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395041304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1395041304
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2440933886
Short name T445
Test name
Test status
Simulation time 8487739257 ps
CPU time 174.74 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:44:52 PM PDT 24
Peak memory 213304 kb
Host smart-fd6767aa-b0d6-4d32-be7c-bb7e77ca547f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440933886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2440933886
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2271353690
Short name T421
Test name
Test status
Simulation time 298310492 ps
CPU time 9.16 seconds
Started May 05 12:42:21 PM PDT 24
Finished May 05 12:42:32 PM PDT 24
Peak memory 216472 kb
Host smart-8f7126a6-9370-4ad2-97a7-0623a6cd15fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271353690 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2271353690
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2833683415
Short name T420
Test name
Test status
Simulation time 1480229748 ps
CPU time 17.23 seconds
Started May 05 12:42:16 PM PDT 24
Finished May 05 12:42:34 PM PDT 24
Peak memory 211028 kb
Host smart-2296f3c4-49dc-40ce-b090-0bd9a82f9eda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833683415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2833683415
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4064410623
Short name T93
Test name
Test status
Simulation time 39041865866 ps
CPU time 112.01 seconds
Started May 05 12:42:13 PM PDT 24
Finished May 05 12:44:09 PM PDT 24
Peak memory 214632 kb
Host smart-9e5154a1-06bb-434e-bd02-e3122a9784a6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064410623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.4064410623
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3075424334
Short name T428
Test name
Test status
Simulation time 202994634 ps
CPU time 12.1 seconds
Started May 05 12:41:59 PM PDT 24
Finished May 05 12:42:13 PM PDT 24
Peak memory 211660 kb
Host smart-d7c4eaf0-7d88-4505-b0e2-ec2f088ff955
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075424334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3075424334
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3978418910
Short name T432
Test name
Test status
Simulation time 174270423 ps
CPU time 11.21 seconds
Started May 05 12:42:28 PM PDT 24
Finished May 05 12:42:40 PM PDT 24
Peak memory 218676 kb
Host smart-20b1c824-b977-46b1-87ad-a65964e79e9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978418910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3978418910
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3377735192
Short name T374
Test name
Test status
Simulation time 37807658039 ps
CPU time 24.94 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:42:22 PM PDT 24
Peak memory 218064 kb
Host smart-fe6125e0-bc48-47d9-99ae-9647f8c9a4ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377735192 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3377735192
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3688820390
Short name T394
Test name
Test status
Simulation time 7839511956 ps
CPU time 30.99 seconds
Started May 05 12:42:14 PM PDT 24
Finished May 05 12:42:46 PM PDT 24
Peak memory 211824 kb
Host smart-342a1f43-47bd-4e61-a822-80513c9fa456
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688820390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3688820390
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4262677476
Short name T435
Test name
Test status
Simulation time 7510436051 ps
CPU time 70.07 seconds
Started May 05 12:42:27 PM PDT 24
Finished May 05 12:43:38 PM PDT 24
Peak memory 213692 kb
Host smart-addbc810-d609-4f95-aade-0b22eeed586e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262677476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.4262677476
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1541228683
Short name T96
Test name
Test status
Simulation time 13869512187 ps
CPU time 31.47 seconds
Started May 05 12:42:13 PM PDT 24
Finished May 05 12:42:46 PM PDT 24
Peak memory 211864 kb
Host smart-ea9884d2-2a8d-45c9-83b1-485cfcd740f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541228683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1541228683
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3073584896
Short name T376
Test name
Test status
Simulation time 15582976117 ps
CPU time 34.58 seconds
Started May 05 12:41:59 PM PDT 24
Finished May 05 12:42:35 PM PDT 24
Peak memory 218760 kb
Host smart-08831d8d-fc05-450e-9bc0-c9848bc57ab2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073584896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3073584896
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.99001847
Short name T453
Test name
Test status
Simulation time 8784310946 ps
CPU time 90.21 seconds
Started May 05 12:42:00 PM PDT 24
Finished May 05 12:43:32 PM PDT 24
Peak memory 218668 kb
Host smart-e1b89d30-1e91-4940-907a-d0a43633dc2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99001847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_int
g_err.99001847
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.642634959
Short name T436
Test name
Test status
Simulation time 914733697 ps
CPU time 14.17 seconds
Started May 05 12:42:12 PM PDT 24
Finished May 05 12:42:27 PM PDT 24
Peak memory 218656 kb
Host smart-64c09594-3dd8-4ebd-9bd1-d8245ba732e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642634959 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.642634959
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1048716108
Short name T449
Test name
Test status
Simulation time 687924504 ps
CPU time 8.17 seconds
Started May 05 12:42:15 PM PDT 24
Finished May 05 12:42:24 PM PDT 24
Peak memory 210444 kb
Host smart-70cfbf2a-3c82-495f-90b3-512d7a52e6c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048716108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1048716108
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.748277958
Short name T71
Test name
Test status
Simulation time 1081408302 ps
CPU time 56 seconds
Started May 05 12:42:36 PM PDT 24
Finished May 05 12:43:33 PM PDT 24
Peak memory 213608 kb
Host smart-fe2f19d6-40c2-4b7e-9976-1738cdf33efb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748277958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.748277958
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3186131909
Short name T429
Test name
Test status
Simulation time 170918169 ps
CPU time 8.25 seconds
Started May 05 12:41:55 PM PDT 24
Finished May 05 12:42:05 PM PDT 24
Peak memory 210296 kb
Host smart-1198af66-c452-4bca-ad1f-a3320213bdab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186131909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3186131909
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1291978556
Short name T430
Test name
Test status
Simulation time 3431325114 ps
CPU time 31.26 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:30 PM PDT 24
Peak memory 216640 kb
Host smart-70c18a59-9191-47f4-a741-371712ffa12e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291978556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1291978556
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2822541486
Short name T111
Test name
Test status
Simulation time 4911961684 ps
CPU time 86.84 seconds
Started May 05 12:42:13 PM PDT 24
Finished May 05 12:43:41 PM PDT 24
Peak memory 218760 kb
Host smart-b2cea82b-f31b-454d-ab13-bb6773dd9a40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822541486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2822541486
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.32505855
Short name T433
Test name
Test status
Simulation time 6752777647 ps
CPU time 17.5 seconds
Started May 05 12:42:12 PM PDT 24
Finished May 05 12:42:30 PM PDT 24
Peak memory 218804 kb
Host smart-662c815a-35bd-4c6d-b836-28cb2d64e148
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32505855 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.32505855
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.233416478
Short name T101
Test name
Test status
Simulation time 3501500014 ps
CPU time 27.34 seconds
Started May 05 12:42:01 PM PDT 24
Finished May 05 12:42:30 PM PDT 24
Peak memory 211452 kb
Host smart-6f03bd57-7dbd-493b-afc9-2ab4a83e0ae4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233416478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.233416478
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1567218793
Short name T408
Test name
Test status
Simulation time 5609415436 ps
CPU time 47.31 seconds
Started May 05 12:42:12 PM PDT 24
Finished May 05 12:43:05 PM PDT 24
Peak memory 214672 kb
Host smart-60c267ef-f911-4e6e-8440-8e309a95e53b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567218793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1567218793
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2228094316
Short name T77
Test name
Test status
Simulation time 6146422756 ps
CPU time 21.51 seconds
Started May 05 12:42:12 PM PDT 24
Finished May 05 12:42:34 PM PDT 24
Peak memory 212020 kb
Host smart-570dc4da-6619-4909-a585-8ca04eba1816
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228094316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2228094316
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1626925066
Short name T439
Test name
Test status
Simulation time 3525295715 ps
CPU time 21.94 seconds
Started May 05 12:41:55 PM PDT 24
Finished May 05 12:42:18 PM PDT 24
Peak memory 218756 kb
Host smart-73413e87-22ff-4905-b95e-4f41d61b2a50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626925066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1626925066
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3709608394
Short name T446
Test name
Test status
Simulation time 3205712292 ps
CPU time 161.03 seconds
Started May 05 12:41:59 PM PDT 24
Finished May 05 12:44:42 PM PDT 24
Peak memory 213072 kb
Host smart-be480a42-ce78-4e3b-9759-6c0cf85bd56c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709608394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3709608394
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.358561894
Short name T411
Test name
Test status
Simulation time 8238604827 ps
CPU time 30.83 seconds
Started May 05 12:42:00 PM PDT 24
Finished May 05 12:42:32 PM PDT 24
Peak memory 216864 kb
Host smart-929910eb-be65-42fe-9a39-53080559b88d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358561894 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.358561894
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3552477253
Short name T74
Test name
Test status
Simulation time 3768814103 ps
CPU time 19.43 seconds
Started May 05 12:42:06 PM PDT 24
Finished May 05 12:42:26 PM PDT 24
Peak memory 211040 kb
Host smart-ad5acb1e-d9b4-42fb-9d43-f2e963f20013
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552477253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3552477253
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4106464258
Short name T84
Test name
Test status
Simulation time 20024805642 ps
CPU time 168.96 seconds
Started May 05 12:42:05 PM PDT 24
Finished May 05 12:44:55 PM PDT 24
Peak memory 214760 kb
Host smart-7c6eabe4-95c1-4519-8442-abb6d36c8580
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106464258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4106464258
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4212927905
Short name T401
Test name
Test status
Simulation time 2044657728 ps
CPU time 19.88 seconds
Started May 05 12:42:08 PM PDT 24
Finished May 05 12:42:28 PM PDT 24
Peak memory 211564 kb
Host smart-4b91192d-c180-4da8-b83e-1bdc3cf98cf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212927905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.4212927905
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3386077025
Short name T52
Test name
Test status
Simulation time 20243578542 ps
CPU time 29.5 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:29 PM PDT 24
Peak memory 217024 kb
Host smart-c6044354-6c49-469e-84cd-3c0045d1274a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386077025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3386077025
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3389858697
Short name T110
Test name
Test status
Simulation time 657456131 ps
CPU time 156.03 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:44:34 PM PDT 24
Peak memory 212968 kb
Host smart-bd34f518-b893-4181-b9c1-991f49b09353
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389858697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3389858697
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3469326568
Short name T437
Test name
Test status
Simulation time 2901928809 ps
CPU time 14.46 seconds
Started May 05 12:42:02 PM PDT 24
Finished May 05 12:42:17 PM PDT 24
Peak memory 214400 kb
Host smart-08c37145-1e7c-418f-b052-19b474fdade1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469326568 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3469326568
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2895055105
Short name T100
Test name
Test status
Simulation time 11379979177 ps
CPU time 26.63 seconds
Started May 05 12:42:15 PM PDT 24
Finished May 05 12:42:46 PM PDT 24
Peak memory 211412 kb
Host smart-5146ac1a-c4d5-410a-bf5b-6a3fe0747aca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895055105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2895055105
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3598343589
Short name T425
Test name
Test status
Simulation time 6234957739 ps
CPU time 57.8 seconds
Started May 05 12:42:28 PM PDT 24
Finished May 05 12:43:27 PM PDT 24
Peak memory 213664 kb
Host smart-a7e7cf1b-9e1d-40dc-9cf4-9267e9ae7926
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598343589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3598343589
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.261418475
Short name T451
Test name
Test status
Simulation time 1731755609 ps
CPU time 18.92 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:18 PM PDT 24
Peak memory 211244 kb
Host smart-79d9d1b3-3b2f-44fd-8aeb-570f4a2b0959
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261418475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.261418475
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2729651885
Short name T403
Test name
Test status
Simulation time 24540452941 ps
CPU time 21.62 seconds
Started May 05 12:42:03 PM PDT 24
Finished May 05 12:42:26 PM PDT 24
Peak memory 218776 kb
Host smart-206b872b-461d-4d33-9b76-3767c5e52dcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729651885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2729651885
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1218238380
Short name T105
Test name
Test status
Simulation time 5380260567 ps
CPU time 168.49 seconds
Started May 05 12:42:16 PM PDT 24
Finished May 05 12:45:05 PM PDT 24
Peak memory 213644 kb
Host smart-5e8f9e56-1353-44bf-9405-c48b3a0fc49a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218238380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1218238380
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1787948502
Short name T441
Test name
Test status
Simulation time 2261440294 ps
CPU time 15.33 seconds
Started May 05 12:42:22 PM PDT 24
Finished May 05 12:42:39 PM PDT 24
Peak memory 215844 kb
Host smart-d533df22-60d7-4c36-8f41-587f66e378ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787948502 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1787948502
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.282063622
Short name T416
Test name
Test status
Simulation time 972097171 ps
CPU time 8.19 seconds
Started May 05 12:41:55 PM PDT 24
Finished May 05 12:42:05 PM PDT 24
Peak memory 210388 kb
Host smart-c70b5dd6-3842-415b-a982-2561eb53c672
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282063622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.282063622
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2911799306
Short name T91
Test name
Test status
Simulation time 2740124083 ps
CPU time 55.76 seconds
Started May 05 12:42:05 PM PDT 24
Finished May 05 12:43:01 PM PDT 24
Peak memory 212556 kb
Host smart-1a7592bd-7c45-45da-9219-9f405b35a8c9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911799306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2911799306
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3570975580
Short name T397
Test name
Test status
Simulation time 170709873 ps
CPU time 8.56 seconds
Started May 05 12:42:18 PM PDT 24
Finished May 05 12:42:27 PM PDT 24
Peak memory 210448 kb
Host smart-70647422-29e5-4e7a-b9c4-bee0e28367ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570975580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3570975580
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4078666633
Short name T427
Test name
Test status
Simulation time 3488947147 ps
CPU time 32.76 seconds
Started May 05 12:42:01 PM PDT 24
Finished May 05 12:42:35 PM PDT 24
Peak memory 218736 kb
Host smart-35d1e7a6-89a1-4834-b461-5d7da0a1dcfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078666633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.4078666633
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2610744639
Short name T399
Test name
Test status
Simulation time 259291944 ps
CPU time 9.56 seconds
Started May 05 12:41:55 PM PDT 24
Finished May 05 12:42:06 PM PDT 24
Peak memory 210400 kb
Host smart-43fd28c3-e19d-46be-9bac-e4979ca5f7e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610744639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2610744639
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.946133641
Short name T422
Test name
Test status
Simulation time 3783449148 ps
CPU time 31.17 seconds
Started May 05 12:42:01 PM PDT 24
Finished May 05 12:42:34 PM PDT 24
Peak memory 211272 kb
Host smart-48bb9864-f75d-4fba-a69e-f5611ca9617a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946133641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.946133641
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2937116231
Short name T415
Test name
Test status
Simulation time 231696580 ps
CPU time 11.65 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:42:09 PM PDT 24
Peak memory 210348 kb
Host smart-88b1abd6-9acb-4082-8d82-91f7def36310
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937116231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2937116231
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4293004305
Short name T391
Test name
Test status
Simulation time 1438443921 ps
CPU time 17.32 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:16 PM PDT 24
Peak memory 218676 kb
Host smart-3eabe0f7-7fe7-469c-94f7-fdc0f20e8431
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293004305 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4293004305
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3396550322
Short name T395
Test name
Test status
Simulation time 956842558 ps
CPU time 9.82 seconds
Started May 05 12:41:53 PM PDT 24
Finished May 05 12:42:10 PM PDT 24
Peak memory 210392 kb
Host smart-3012a15e-92e8-4aa0-940c-fa8bea2d0ffb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396550322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3396550322
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2565530153
Short name T434
Test name
Test status
Simulation time 3346397518 ps
CPU time 27.69 seconds
Started May 05 12:41:55 PM PDT 24
Finished May 05 12:42:24 PM PDT 24
Peak memory 210616 kb
Host smart-472839c7-cd20-4278-9e39-8ef9c909fe92
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565530153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2565530153
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2257834949
Short name T448
Test name
Test status
Simulation time 2122020483 ps
CPU time 12.28 seconds
Started May 05 12:41:51 PM PDT 24
Finished May 05 12:42:05 PM PDT 24
Peak memory 210344 kb
Host smart-7aa4d8e4-7408-428a-8f1b-fe91fd090f8c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257834949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2257834949
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1369997600
Short name T103
Test name
Test status
Simulation time 23015222237 ps
CPU time 99.45 seconds
Started May 05 12:41:58 PM PDT 24
Finished May 05 12:43:39 PM PDT 24
Peak memory 214992 kb
Host smart-c1aa5741-f195-4bf4-8c61-e244da49de26
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369997600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1369997600
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3643656392
Short name T443
Test name
Test status
Simulation time 5720359146 ps
CPU time 28.79 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:28 PM PDT 24
Peak memory 212212 kb
Host smart-3e532cad-759d-4c01-8711-78b74ad260cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643656392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3643656392
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1066129695
Short name T373
Test name
Test status
Simulation time 1646518846 ps
CPU time 13.67 seconds
Started May 05 12:41:55 PM PDT 24
Finished May 05 12:42:11 PM PDT 24
Peak memory 218728 kb
Host smart-f87e55c0-0b83-4dc4-89f8-3375a4b0725a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066129695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1066129695
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1328371935
Short name T115
Test name
Test status
Simulation time 32617996226 ps
CPU time 170.81 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:44:49 PM PDT 24
Peak memory 218704 kb
Host smart-6ffa1973-e889-4105-b1b6-f5ceffe130fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328371935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1328371935
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1637164188
Short name T87
Test name
Test status
Simulation time 14755990663 ps
CPU time 30.49 seconds
Started May 05 12:42:15 PM PDT 24
Finished May 05 12:42:46 PM PDT 24
Peak memory 211280 kb
Host smart-3bfc9742-af67-4fc3-9218-888b49605a22
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637164188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1637164188
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3623685598
Short name T409
Test name
Test status
Simulation time 307327033 ps
CPU time 8.3 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:42:06 PM PDT 24
Peak memory 210416 kb
Host smart-fa8579d8-5e56-45e2-90f6-e95f301d6611
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623685598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3623685598
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1874630026
Short name T382
Test name
Test status
Simulation time 16838732254 ps
CPU time 39.13 seconds
Started May 05 12:42:05 PM PDT 24
Finished May 05 12:42:45 PM PDT 24
Peak memory 211340 kb
Host smart-9546d149-cada-4b79-8756-2e3950e2929c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874630026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1874630026
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2844501780
Short name T405
Test name
Test status
Simulation time 3879483859 ps
CPU time 29.8 seconds
Started May 05 12:41:52 PM PDT 24
Finished May 05 12:42:24 PM PDT 24
Peak memory 218700 kb
Host smart-c8d28a62-a664-4a37-acff-ae2ee43e29e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844501780 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2844501780
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2095673974
Short name T361
Test name
Test status
Simulation time 3944424925 ps
CPU time 31.85 seconds
Started May 05 12:41:55 PM PDT 24
Finished May 05 12:42:28 PM PDT 24
Peak memory 210492 kb
Host smart-dd5cfe0f-0812-44f6-aab3-836ad0d86f4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095673974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2095673974
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3903860101
Short name T377
Test name
Test status
Simulation time 8924353466 ps
CPU time 14.8 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:42:13 PM PDT 24
Peak memory 210420 kb
Host smart-f5a52cd9-222d-403c-8b46-ed18d217c12c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903860101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3903860101
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.305723926
Short name T362
Test name
Test status
Simulation time 20608556271 ps
CPU time 23.8 seconds
Started May 05 12:41:54 PM PDT 24
Finished May 05 12:42:19 PM PDT 24
Peak memory 210480 kb
Host smart-4959a88f-4a40-4195-8c4d-5741bb88f502
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305723926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
305723926
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2508923157
Short name T447
Test name
Test status
Simulation time 76905146098 ps
CPU time 66.85 seconds
Started May 05 12:42:12 PM PDT 24
Finished May 05 12:43:20 PM PDT 24
Peak memory 210620 kb
Host smart-ac5086b8-1d9b-4edd-9e60-b38cf113ec67
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508923157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2508923157
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3631410005
Short name T414
Test name
Test status
Simulation time 19932440080 ps
CPU time 35.94 seconds
Started May 05 12:42:23 PM PDT 24
Finished May 05 12:43:01 PM PDT 24
Peak memory 211992 kb
Host smart-7371ad29-1681-47c5-a77b-4ad85c5e51bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631410005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3631410005
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2864293644
Short name T385
Test name
Test status
Simulation time 2779322059 ps
CPU time 28.37 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:27 PM PDT 24
Peak memory 218736 kb
Host smart-da39fedd-0323-4d8d-94e2-d3c0272fac86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864293644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2864293644
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.449580110
Short name T116
Test name
Test status
Simulation time 1017615893 ps
CPU time 87.1 seconds
Started May 05 12:41:54 PM PDT 24
Finished May 05 12:43:23 PM PDT 24
Peak memory 218608 kb
Host smart-632066b7-e262-499b-8d9d-5046eb197370
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449580110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.449580110
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3998692188
Short name T418
Test name
Test status
Simulation time 4618361581 ps
CPU time 22.1 seconds
Started May 05 12:41:58 PM PDT 24
Finished May 05 12:42:22 PM PDT 24
Peak memory 210880 kb
Host smart-e6cab907-ddac-4f99-9162-db75717dafb2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998692188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3998692188
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4031167819
Short name T442
Test name
Test status
Simulation time 2299771093 ps
CPU time 11.98 seconds
Started May 05 12:41:58 PM PDT 24
Finished May 05 12:42:12 PM PDT 24
Peak memory 210456 kb
Host smart-7da6bbb5-a3e4-4295-8f0a-092e0a8f80af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031167819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.4031167819
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.278591578
Short name T413
Test name
Test status
Simulation time 2619683341 ps
CPU time 19.24 seconds
Started May 05 12:42:21 PM PDT 24
Finished May 05 12:42:41 PM PDT 24
Peak memory 211200 kb
Host smart-cdda9ebf-4de9-4dfb-8227-267397ea495d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278591578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.278591578
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1226448409
Short name T359
Test name
Test status
Simulation time 179491233 ps
CPU time 8.92 seconds
Started May 05 12:41:51 PM PDT 24
Finished May 05 12:42:00 PM PDT 24
Peak memory 218644 kb
Host smart-53c049a1-42e7-4088-b024-d88c277265fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226448409 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1226448409
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4093399330
Short name T367
Test name
Test status
Simulation time 11039135853 ps
CPU time 24.52 seconds
Started May 05 12:41:58 PM PDT 24
Finished May 05 12:42:25 PM PDT 24
Peak memory 211496 kb
Host smart-1aaae75e-839e-4d87-a585-90f5c228e4f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093399330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.4093399330
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3829527018
Short name T371
Test name
Test status
Simulation time 24630216770 ps
CPU time 31.04 seconds
Started May 05 12:42:12 PM PDT 24
Finished May 05 12:42:44 PM PDT 24
Peak memory 210436 kb
Host smart-55831f3e-8d3a-4d62-b1be-0c53fd0cd025
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829527018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3829527018
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3227318327
Short name T406
Test name
Test status
Simulation time 10223855672 ps
CPU time 23.85 seconds
Started May 05 12:42:26 PM PDT 24
Finished May 05 12:42:51 PM PDT 24
Peak memory 210468 kb
Host smart-a6677bcf-f6d0-40a1-a185-3e5b487cddba
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227318327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3227318327
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2758143071
Short name T89
Test name
Test status
Simulation time 3667486791 ps
CPU time 56.32 seconds
Started May 05 12:41:52 PM PDT 24
Finished May 05 12:42:49 PM PDT 24
Peak memory 214696 kb
Host smart-ed266908-6057-472e-a6ad-9d6db8f7347d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758143071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2758143071
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3988082219
Short name T95
Test name
Test status
Simulation time 17377929526 ps
CPU time 32.06 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:42:30 PM PDT 24
Peak memory 210560 kb
Host smart-4df1a86d-f86c-4691-bbb4-be3cf7026f8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988082219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3988082219
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2436929409
Short name T438
Test name
Test status
Simulation time 1448552478 ps
CPU time 19.8 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:19 PM PDT 24
Peak memory 218668 kb
Host smart-cb4499d4-441a-4a53-b030-4a02b57100f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436929409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2436929409
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2002396248
Short name T114
Test name
Test status
Simulation time 1457698084 ps
CPU time 162.17 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:44:41 PM PDT 24
Peak memory 213116 kb
Host smart-a7109393-f4f4-40e4-8e7c-4deca9fd5939
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002396248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2002396248
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1004828077
Short name T366
Test name
Test status
Simulation time 1618920994 ps
CPU time 18.15 seconds
Started May 05 12:41:59 PM PDT 24
Finished May 05 12:42:19 PM PDT 24
Peak memory 218676 kb
Host smart-9434b2af-9efe-4c61-bfde-4fc4a8d5a793
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004828077 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1004828077
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.559619688
Short name T389
Test name
Test status
Simulation time 176441902 ps
CPU time 8.45 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:42:06 PM PDT 24
Peak memory 210396 kb
Host smart-8cb45b74-c596-4866-a075-46dbf362715d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559619688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.559619688
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.400032185
Short name T381
Test name
Test status
Simulation time 2027576427 ps
CPU time 56.88 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:42:54 PM PDT 24
Peak memory 214672 kb
Host smart-0b068692-860a-4c8d-afd6-dc3b20f5b35d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400032185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.400032185
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1704284149
Short name T388
Test name
Test status
Simulation time 24316419266 ps
CPU time 29.32 seconds
Started May 05 12:41:58 PM PDT 24
Finished May 05 12:42:29 PM PDT 24
Peak memory 211936 kb
Host smart-5686d60c-6c57-4eb7-a2f6-cd34058c7d5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704284149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1704284149
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.235587388
Short name T390
Test name
Test status
Simulation time 4275718706 ps
CPU time 22.14 seconds
Started May 05 12:42:01 PM PDT 24
Finished May 05 12:42:25 PM PDT 24
Peak memory 215508 kb
Host smart-36c5775c-eaf1-4050-8cf7-d24b4318b5ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235587388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.235587388
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1484152157
Short name T109
Test name
Test status
Simulation time 16902659782 ps
CPU time 174.32 seconds
Started May 05 12:42:04 PM PDT 24
Finished May 05 12:45:00 PM PDT 24
Peak memory 213328 kb
Host smart-b531430e-315c-40ec-8a3e-ba79a3fe1188
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484152157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1484152157
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4139438373
Short name T426
Test name
Test status
Simulation time 3437034526 ps
CPU time 29.05 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:28 PM PDT 24
Peak memory 218700 kb
Host smart-e964fac1-5a7f-4976-a649-7a770190d625
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139438373 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.4139438373
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.521702570
Short name T62
Test name
Test status
Simulation time 768703788 ps
CPU time 13.28 seconds
Started May 05 12:42:21 PM PDT 24
Finished May 05 12:42:36 PM PDT 24
Peak memory 210440 kb
Host smart-1b03d8fe-c09d-438e-bcb1-948dbafc626b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521702570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.521702570
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.463877488
Short name T90
Test name
Test status
Simulation time 8664411069 ps
CPU time 107.41 seconds
Started May 05 12:41:52 PM PDT 24
Finished May 05 12:43:41 PM PDT 24
Peak memory 214820 kb
Host smart-71b45d21-e48a-419d-b514-80a358847c31
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463877488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.463877488
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1346370801
Short name T61
Test name
Test status
Simulation time 1956473597 ps
CPU time 20.39 seconds
Started May 05 12:42:21 PM PDT 24
Finished May 05 12:42:44 PM PDT 24
Peak memory 211560 kb
Host smart-c9354796-bcf2-44ed-9e05-7af3a46d127d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346370801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1346370801
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4169941128
Short name T372
Test name
Test status
Simulation time 1571723572 ps
CPU time 21.77 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:21 PM PDT 24
Peak memory 218688 kb
Host smart-7bf452ba-724a-4e75-94dc-c982c589588e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169941128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.4169941128
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3874239242
Short name T60
Test name
Test status
Simulation time 4430887718 ps
CPU time 157.47 seconds
Started May 05 12:41:54 PM PDT 24
Finished May 05 12:44:33 PM PDT 24
Peak memory 213636 kb
Host smart-63d11076-1dc6-4637-9a93-8facbf9bd14b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874239242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3874239242
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3086004231
Short name T379
Test name
Test status
Simulation time 3285614465 ps
CPU time 27.72 seconds
Started May 05 12:42:37 PM PDT 24
Finished May 05 12:43:05 PM PDT 24
Peak memory 215980 kb
Host smart-99438103-d990-41a8-a404-0761dd6e6997
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086004231 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3086004231
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.891805129
Short name T452
Test name
Test status
Simulation time 9183464031 ps
CPU time 22.5 seconds
Started May 05 12:41:54 PM PDT 24
Finished May 05 12:42:23 PM PDT 24
Peak memory 211540 kb
Host smart-70043ba6-dbd9-4044-b572-7f11428971db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891805129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.891805129
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1066372316
Short name T398
Test name
Test status
Simulation time 6065443853 ps
CPU time 55.11 seconds
Started May 05 12:42:00 PM PDT 24
Finished May 05 12:42:57 PM PDT 24
Peak memory 215232 kb
Host smart-df337665-8c7d-43b9-b8b5-46e723b88501
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066372316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1066372316
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2667743027
Short name T380
Test name
Test status
Simulation time 5118371320 ps
CPU time 27.7 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:42:25 PM PDT 24
Peak memory 211988 kb
Host smart-2104a6ef-970d-47d8-bbeb-4fe02cb714fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667743027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2667743027
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.462495481
Short name T400
Test name
Test status
Simulation time 14090452893 ps
CPU time 34 seconds
Started May 05 12:42:16 PM PDT 24
Finished May 05 12:42:53 PM PDT 24
Peak memory 218016 kb
Host smart-36678b5e-946d-4898-9e85-63597b69b2a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462495481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.462495481
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.25468632
Short name T396
Test name
Test status
Simulation time 3230606725 ps
CPU time 156.47 seconds
Started May 05 12:42:00 PM PDT 24
Finished May 05 12:44:38 PM PDT 24
Peak memory 218640 kb
Host smart-d51d4d5c-5add-4820-a639-86b6bef5a3ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25468632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg
_err.25468632
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3936992036
Short name T49
Test name
Test status
Simulation time 373254693 ps
CPU time 8.84 seconds
Started May 05 12:42:01 PM PDT 24
Finished May 05 12:42:11 PM PDT 24
Peak memory 218652 kb
Host smart-d6d49efd-5f62-4f33-83e9-21fc54c79293
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936992036 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3936992036
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3026928496
Short name T407
Test name
Test status
Simulation time 2626163743 ps
CPU time 12.89 seconds
Started May 05 12:41:55 PM PDT 24
Finished May 05 12:42:09 PM PDT 24
Peak memory 210444 kb
Host smart-30504472-7756-412f-be45-0b5bd094c25b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026928496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3026928496
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2711061809
Short name T70
Test name
Test status
Simulation time 23896665870 ps
CPU time 109.43 seconds
Started May 05 12:42:00 PM PDT 24
Finished May 05 12:43:51 PM PDT 24
Peak memory 218680 kb
Host smart-40f75667-7d01-4e2f-8fe2-f528686660a8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711061809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2711061809
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2872798445
Short name T97
Test name
Test status
Simulation time 689188137 ps
CPU time 8.21 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:07 PM PDT 24
Peak memory 210436 kb
Host smart-34fc7634-da45-4bb5-9e93-9901cfe8b932
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872798445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2872798445
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2024798543
Short name T378
Test name
Test status
Simulation time 174658784 ps
CPU time 11.75 seconds
Started May 05 12:41:58 PM PDT 24
Finished May 05 12:42:12 PM PDT 24
Peak memory 218636 kb
Host smart-3c5cf79b-72c8-4f13-9883-3c918cf06248
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024798543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2024798543
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.935653539
Short name T108
Test name
Test status
Simulation time 16595160008 ps
CPU time 101.31 seconds
Started May 05 12:41:55 PM PDT 24
Finished May 05 12:43:38 PM PDT 24
Peak memory 212820 kb
Host smart-a50a9cd1-57fb-4a60-a64c-70ebd91a6549
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935653539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.935653539
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1194128257
Short name T364
Test name
Test status
Simulation time 1019295158 ps
CPU time 12.8 seconds
Started May 05 12:41:50 PM PDT 24
Finished May 05 12:42:04 PM PDT 24
Peak memory 215812 kb
Host smart-ff6084bb-ca5e-4288-b621-8631e7070555
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194128257 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1194128257
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2252910410
Short name T76
Test name
Test status
Simulation time 3265322050 ps
CPU time 26.93 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:42:25 PM PDT 24
Peak memory 210492 kb
Host smart-f00efa63-82b5-426e-8832-a27d951d3e79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252910410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2252910410
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1564440161
Short name T410
Test name
Test status
Simulation time 2748661192 ps
CPU time 24.51 seconds
Started May 05 12:42:20 PM PDT 24
Finished May 05 12:42:45 PM PDT 24
Peak memory 211344 kb
Host smart-4f4f6b04-22fe-4de8-9e77-1f6d2c9174a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564440161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1564440161
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3454734888
Short name T69
Test name
Test status
Simulation time 8856390847 ps
CPU time 24.34 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:42:21 PM PDT 24
Peak memory 218812 kb
Host smart-a72b6800-a247-477a-836a-d9059260b72e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454734888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3454734888
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1540147314
Short name T412
Test name
Test status
Simulation time 21985884075 ps
CPU time 175.8 seconds
Started May 05 12:42:26 PM PDT 24
Finished May 05 12:45:23 PM PDT 24
Peak memory 218760 kb
Host smart-9c12d953-4011-487b-9f55-e50a694375f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540147314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1540147314
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1324110047
Short name T168
Test name
Test status
Simulation time 72337016794 ps
CPU time 30.65 seconds
Started May 05 12:42:08 PM PDT 24
Finished May 05 12:42:39 PM PDT 24
Peak memory 212404 kb
Host smart-f25b8415-7dae-4e30-b02c-e72a361e656f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324110047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1324110047
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2291141169
Short name T298
Test name
Test status
Simulation time 7896510936 ps
CPU time 171.84 seconds
Started May 05 12:41:55 PM PDT 24
Finished May 05 12:44:48 PM PDT 24
Peak memory 217852 kb
Host smart-c59bf267-7b11-42ae-8205-ebc66e9ad9cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291141169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2291141169
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1029780846
Short name T145
Test name
Test status
Simulation time 11707981507 ps
CPU time 22.42 seconds
Started May 05 12:42:18 PM PDT 24
Finished May 05 12:42:41 PM PDT 24
Peak memory 213040 kb
Host smart-cbe1de35-02f3-4602-ae27-e54c6856cc04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1029780846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1029780846
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1128395098
Short name T36
Test name
Test status
Simulation time 1507400868 ps
CPU time 236.88 seconds
Started May 05 12:42:04 PM PDT 24
Finished May 05 12:46:02 PM PDT 24
Peak memory 239332 kb
Host smart-96a68d3b-5f29-489a-9d7a-88ce1a8cd2c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128395098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1128395098
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3895903775
Short name T304
Test name
Test status
Simulation time 366921848 ps
CPU time 20.66 seconds
Started May 05 12:42:15 PM PDT 24
Finished May 05 12:42:37 PM PDT 24
Peak memory 217012 kb
Host smart-8aa7b3fd-6ea5-4650-b4a8-ec20b7191b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895903775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3895903775
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2246543357
Short name T121
Test name
Test status
Simulation time 2812006751 ps
CPU time 28.2 seconds
Started May 05 12:42:18 PM PDT 24
Finished May 05 12:42:47 PM PDT 24
Peak memory 213168 kb
Host smart-4ec57b73-afbc-4056-bc9f-e370c3038a3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246543357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2246543357
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1659320989
Short name T186
Test name
Test status
Simulation time 16276004841 ps
CPU time 32.23 seconds
Started May 05 12:41:59 PM PDT 24
Finished May 05 12:42:33 PM PDT 24
Peak memory 212700 kb
Host smart-aab2b32e-ad5b-4f01-8245-dc9b198187f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659320989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1659320989
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3997840501
Short name T22
Test name
Test status
Simulation time 93818678480 ps
CPU time 924.01 seconds
Started May 05 12:42:29 PM PDT 24
Finished May 05 12:57:54 PM PDT 24
Peak memory 218216 kb
Host smart-3b3f3e04-9f8b-45c6-8a67-b7b8c18bc58f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997840501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3997840501
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2469909522
Short name T138
Test name
Test status
Simulation time 32057133525 ps
CPU time 55.22 seconds
Started May 05 12:41:59 PM PDT 24
Finished May 05 12:42:56 PM PDT 24
Peak memory 215568 kb
Host smart-4675b1fe-e6b6-428d-aaeb-b07762db2a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469909522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2469909522
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1343299307
Short name T170
Test name
Test status
Simulation time 359456525 ps
CPU time 10.57 seconds
Started May 05 12:42:07 PM PDT 24
Finished May 05 12:42:19 PM PDT 24
Peak memory 212780 kb
Host smart-b87dd635-222c-455c-ad52-c05e17a7b515
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1343299307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1343299307
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.429820925
Short name T30
Test name
Test status
Simulation time 3855700445 ps
CPU time 140.58 seconds
Started May 05 12:42:07 PM PDT 24
Finished May 05 12:44:29 PM PDT 24
Peak memory 237780 kb
Host smart-6d8aa750-3473-4c5b-8f8c-d60c68ad0762
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429820925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.429820925
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3045173384
Short name T283
Test name
Test status
Simulation time 1696467798 ps
CPU time 32.11 seconds
Started May 05 12:42:22 PM PDT 24
Finished May 05 12:42:55 PM PDT 24
Peak memory 215468 kb
Host smart-87368c7e-445e-4819-be2d-152117c29707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045173384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3045173384
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2658390739
Short name T133
Test name
Test status
Simulation time 1855866810 ps
CPU time 13.53 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:42:11 PM PDT 24
Peak memory 211768 kb
Host smart-932bcab6-2117-4641-b738-6863f13de004
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658390739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2658390739
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1579170561
Short name T301
Test name
Test status
Simulation time 11165946355 ps
CPU time 228.19 seconds
Started May 05 12:42:05 PM PDT 24
Finished May 05 12:45:54 PM PDT 24
Peak memory 217688 kb
Host smart-6a361344-d9c0-49ee-a800-898128d91d00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579170561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1579170561
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.4006457327
Short name T161
Test name
Test status
Simulation time 16976227532 ps
CPU time 69.04 seconds
Started May 05 12:42:04 PM PDT 24
Finished May 05 12:43:14 PM PDT 24
Peak memory 215536 kb
Host smart-6d05edf5-0fa3-4785-b870-cd8048c92c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006457327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.4006457327
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2240645819
Short name T223
Test name
Test status
Simulation time 1401942743 ps
CPU time 19.69 seconds
Started May 05 12:41:58 PM PDT 24
Finished May 05 12:42:20 PM PDT 24
Peak memory 211772 kb
Host smart-e3cb5deb-c9f1-4d59-946f-5e28fe4eff06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2240645819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2240645819
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3762784004
Short name T227
Test name
Test status
Simulation time 6018242145 ps
CPU time 28.69 seconds
Started May 05 12:42:03 PM PDT 24
Finished May 05 12:42:33 PM PDT 24
Peak memory 217964 kb
Host smart-1797dbeb-dbc8-4884-9018-de7af9b141c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762784004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3762784004
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1949706219
Short name T259
Test name
Test status
Simulation time 3054992667 ps
CPU time 37.66 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:37 PM PDT 24
Peak memory 214280 kb
Host smart-9eb1599e-c11b-455f-9b4c-27b78d12f61f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949706219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1949706219
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3021588613
Short name T15
Test name
Test status
Simulation time 64131771145 ps
CPU time 2444.81 seconds
Started May 05 12:42:34 PM PDT 24
Finished May 05 01:23:20 PM PDT 24
Peak memory 241236 kb
Host smart-5ce29d9b-2671-4317-befd-16691ac0321d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021588613 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3021588613
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2525035621
Short name T64
Test name
Test status
Simulation time 8976873268 ps
CPU time 21.15 seconds
Started May 05 12:42:28 PM PDT 24
Finished May 05 12:42:50 PM PDT 24
Peak memory 212752 kb
Host smart-313fb40a-9f30-4c88-ab1f-32d51387e933
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525035621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2525035621
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3214794145
Short name T206
Test name
Test status
Simulation time 13420916488 ps
CPU time 250.9 seconds
Started May 05 12:42:00 PM PDT 24
Finished May 05 12:46:13 PM PDT 24
Peak memory 241328 kb
Host smart-d7bfdbe6-67a5-41b4-be77-86491c4db093
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214794145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3214794145
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3145671769
Short name T219
Test name
Test status
Simulation time 26160755618 ps
CPU time 38.06 seconds
Started May 05 12:42:16 PM PDT 24
Finished May 05 12:42:55 PM PDT 24
Peak memory 215540 kb
Host smart-a90ea914-78be-46b0-bebf-1890ca0697fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145671769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3145671769
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1649009705
Short name T204
Test name
Test status
Simulation time 1363704230 ps
CPU time 17.9 seconds
Started May 05 12:42:26 PM PDT 24
Finished May 05 12:42:44 PM PDT 24
Peak memory 211724 kb
Host smart-2e5493a9-4380-4731-a719-d99a29ac2077
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1649009705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1649009705
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.415729106
Short name T141
Test name
Test status
Simulation time 47044667444 ps
CPU time 102.96 seconds
Started May 05 12:42:16 PM PDT 24
Finished May 05 12:44:00 PM PDT 24
Peak memory 219832 kb
Host smart-114c26a0-faa1-44e1-9b80-add8c42f0a3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415729106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.415729106
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.700970701
Short name T255
Test name
Test status
Simulation time 2117426509 ps
CPU time 21.59 seconds
Started May 05 12:42:38 PM PDT 24
Finished May 05 12:43:01 PM PDT 24
Peak memory 211744 kb
Host smart-b7f439ae-614c-4048-862d-5598bb5ec1a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700970701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.700970701
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1235164615
Short name T317
Test name
Test status
Simulation time 81267791042 ps
CPU time 732.08 seconds
Started May 05 12:42:34 PM PDT 24
Finished May 05 12:54:48 PM PDT 24
Peak memory 225480 kb
Host smart-705adc79-2f76-4361-a50d-8ba7897f0dc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235164615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1235164615
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2904221699
Short name T153
Test name
Test status
Simulation time 398436746 ps
CPU time 12.84 seconds
Started May 05 12:42:00 PM PDT 24
Finished May 05 12:42:15 PM PDT 24
Peak memory 211828 kb
Host smart-6399048f-1bf5-48f2-a565-e80a78d0512d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2904221699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2904221699
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3592819400
Short name T316
Test name
Test status
Simulation time 580392744 ps
CPU time 19.58 seconds
Started May 05 12:42:28 PM PDT 24
Finished May 05 12:42:49 PM PDT 24
Peak memory 218012 kb
Host smart-e7143a50-b3bf-4da2-9ead-9438b3961959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592819400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3592819400
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3753918651
Short name T189
Test name
Test status
Simulation time 23868170045 ps
CPU time 57.71 seconds
Started May 05 12:42:42 PM PDT 24
Finished May 05 12:43:40 PM PDT 24
Peak memory 219520 kb
Host smart-3aba2f30-1e7f-4558-9d34-93b68299a47f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753918651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3753918651
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.4286919409
Short name T54
Test name
Test status
Simulation time 206103372 ps
CPU time 8.34 seconds
Started May 05 12:42:26 PM PDT 24
Finished May 05 12:42:35 PM PDT 24
Peak memory 211716 kb
Host smart-ffd77199-19f1-4d01-9074-2d88a9539bff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286919409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.4286919409
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4278573753
Short name T205
Test name
Test status
Simulation time 50695019221 ps
CPU time 480.77 seconds
Started May 05 12:42:23 PM PDT 24
Finished May 05 12:50:25 PM PDT 24
Peak memory 238384 kb
Host smart-ea1604b9-3336-43bf-bf82-8c07174a98e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278573753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.4278573753
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3949168582
Short name T278
Test name
Test status
Simulation time 1378185706 ps
CPU time 18.86 seconds
Started May 05 12:42:15 PM PDT 24
Finished May 05 12:42:35 PM PDT 24
Peak memory 215544 kb
Host smart-927366d5-8e1d-4677-ab9c-e69be10b3aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949168582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3949168582
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2359136504
Short name T250
Test name
Test status
Simulation time 50498135523 ps
CPU time 78.69 seconds
Started May 05 12:42:06 PM PDT 24
Finished May 05 12:43:25 PM PDT 24
Peak memory 216168 kb
Host smart-c1ca8413-0239-4df6-9498-c11afd8e20e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359136504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2359136504
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.527251869
Short name T34
Test name
Test status
Simulation time 991289328 ps
CPU time 9.83 seconds
Started May 05 12:42:01 PM PDT 24
Finished May 05 12:42:12 PM PDT 24
Peak memory 211792 kb
Host smart-0952e0d1-8beb-4f8d-8de8-f0b5b7ba7dd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527251869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.527251869
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.25567961
Short name T172
Test name
Test status
Simulation time 9069998501 ps
CPU time 160.3 seconds
Started May 05 12:42:12 PM PDT 24
Finished May 05 12:44:53 PM PDT 24
Peak memory 225144 kb
Host smart-cf1158fc-51d8-49e0-913d-de0ee1c82932
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25567961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_co
rrupt_sig_fatal_chk.25567961
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.284617897
Short name T296
Test name
Test status
Simulation time 6554515424 ps
CPU time 52.93 seconds
Started May 05 12:42:27 PM PDT 24
Finished May 05 12:43:21 PM PDT 24
Peak memory 215676 kb
Host smart-2e64ad9f-1b1e-415b-ab43-655d52f4ea1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284617897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.284617897
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4065411629
Short name T102
Test name
Test status
Simulation time 681093004 ps
CPU time 15.5 seconds
Started May 05 12:42:08 PM PDT 24
Finished May 05 12:42:24 PM PDT 24
Peak memory 211760 kb
Host smart-d49f900c-3a75-4f52-a3fd-ee2723882e62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4065411629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4065411629
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.4289309270
Short name T39
Test name
Test status
Simulation time 722547628 ps
CPU time 20.34 seconds
Started May 05 12:42:12 PM PDT 24
Finished May 05 12:42:33 PM PDT 24
Peak memory 217180 kb
Host smart-0203173e-137a-4bf0-8537-0093ce2a860c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289309270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.4289309270
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.248470988
Short name T165
Test name
Test status
Simulation time 46336730067 ps
CPU time 141.45 seconds
Started May 05 12:42:28 PM PDT 24
Finished May 05 12:44:50 PM PDT 24
Peak memory 222932 kb
Host smart-67d1849d-933f-42f0-b810-56e125a5a3c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248470988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.248470988
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2907999887
Short name T343
Test name
Test status
Simulation time 1842491864 ps
CPU time 14.16 seconds
Started May 05 12:42:20 PM PDT 24
Finished May 05 12:42:36 PM PDT 24
Peak memory 211700 kb
Host smart-3eed6d91-0ffe-4a3a-aad8-324ee7d0e63e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907999887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2907999887
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2888219067
Short name T44
Test name
Test status
Simulation time 3461284149 ps
CPU time 96.3 seconds
Started May 05 12:42:13 PM PDT 24
Finished May 05 12:43:50 PM PDT 24
Peak memory 216860 kb
Host smart-92fda784-d8e9-4d5b-ad4a-ec9af2fdc74a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888219067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2888219067
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3877039250
Short name T330
Test name
Test status
Simulation time 690808101 ps
CPU time 19.06 seconds
Started May 05 12:42:21 PM PDT 24
Finished May 05 12:42:42 PM PDT 24
Peak memory 215636 kb
Host smart-65362dd5-de97-415f-961f-1cd878588924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877039250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3877039250
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1067934381
Short name T336
Test name
Test status
Simulation time 3109316491 ps
CPU time 27.6 seconds
Started May 05 12:42:20 PM PDT 24
Finished May 05 12:42:49 PM PDT 24
Peak memory 211844 kb
Host smart-83e3cbe4-7212-4a29-9cb2-0b94e2282675
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1067934381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1067934381
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1233051192
Short name T197
Test name
Test status
Simulation time 1401583810 ps
CPU time 19.38 seconds
Started May 05 12:42:32 PM PDT 24
Finished May 05 12:42:52 PM PDT 24
Peak memory 217976 kb
Host smart-af76543e-a093-4be3-a9c3-6fd8f03731cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233051192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1233051192
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.632423696
Short name T243
Test name
Test status
Simulation time 4596956475 ps
CPU time 24.74 seconds
Started May 05 12:42:08 PM PDT 24
Finished May 05 12:42:33 PM PDT 24
Peak memory 213504 kb
Host smart-13a09fce-40d2-4767-8eac-70229d27b24d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632423696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.632423696
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2916779004
Short name T209
Test name
Test status
Simulation time 4936949981 ps
CPU time 12 seconds
Started May 05 12:42:00 PM PDT 24
Finished May 05 12:42:13 PM PDT 24
Peak memory 211920 kb
Host smart-90ce9281-3178-4672-8273-c188931983b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916779004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2916779004
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2665868078
Short name T28
Test name
Test status
Simulation time 16039190588 ps
CPU time 250.32 seconds
Started May 05 12:42:16 PM PDT 24
Finished May 05 12:46:28 PM PDT 24
Peak memory 220168 kb
Host smart-f39b7acb-e916-4b85-ac49-a0fa753b3dd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665868078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2665868078
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2277777936
Short name T261
Test name
Test status
Simulation time 342466776 ps
CPU time 19.15 seconds
Started May 05 12:42:18 PM PDT 24
Finished May 05 12:42:38 PM PDT 24
Peak memory 215412 kb
Host smart-37e1c6b0-ff1a-486e-b7e3-be251b14a576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277777936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2277777936
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2837222285
Short name T132
Test name
Test status
Simulation time 3889624574 ps
CPU time 31.15 seconds
Started May 05 12:42:21 PM PDT 24
Finished May 05 12:42:53 PM PDT 24
Peak memory 211868 kb
Host smart-18c6f6bf-7ba6-4d30-8212-6eb1f214db95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2837222285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2837222285
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3929552010
Short name T264
Test name
Test status
Simulation time 30540506915 ps
CPU time 69.16 seconds
Started May 05 12:42:10 PM PDT 24
Finished May 05 12:43:20 PM PDT 24
Peak memory 216152 kb
Host smart-b03b9617-042c-458d-96a7-e4d781ae6034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929552010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3929552010
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2416151199
Short name T140
Test name
Test status
Simulation time 17266483870 ps
CPU time 173.52 seconds
Started May 05 12:42:17 PM PDT 24
Finished May 05 12:45:12 PM PDT 24
Peak memory 220664 kb
Host smart-3ba8e135-c1a3-4afc-b815-d8ba9e53f5bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416151199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2416151199
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.523820402
Short name T199
Test name
Test status
Simulation time 12356185708 ps
CPU time 26.4 seconds
Started May 05 12:42:27 PM PDT 24
Finished May 05 12:42:55 PM PDT 24
Peak memory 211892 kb
Host smart-91c6630c-1fce-4c0b-aebe-bb22b8911b56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523820402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.523820402
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.115128390
Short name T300
Test name
Test status
Simulation time 13829696171 ps
CPU time 291.4 seconds
Started May 05 12:42:40 PM PDT 24
Finished May 05 12:47:32 PM PDT 24
Peak memory 240508 kb
Host smart-d833446c-27ef-4fad-8995-1e572ecadf49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115128390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.115128390
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1181366607
Short name T214
Test name
Test status
Simulation time 8539928271 ps
CPU time 67.31 seconds
Started May 05 12:42:16 PM PDT 24
Finished May 05 12:43:24 PM PDT 24
Peak memory 215212 kb
Host smart-72498b98-f0d1-4e17-abb9-450da760d4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181366607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1181366607
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2988647763
Short name T8
Test name
Test status
Simulation time 6744094485 ps
CPU time 16.82 seconds
Started May 05 12:42:35 PM PDT 24
Finished May 05 12:42:52 PM PDT 24
Peak memory 212384 kb
Host smart-672a9287-9032-426d-a2a6-2ffc0c04318e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2988647763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2988647763
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1341909144
Short name T354
Test name
Test status
Simulation time 23851286979 ps
CPU time 59.36 seconds
Started May 05 12:42:17 PM PDT 24
Finished May 05 12:43:17 PM PDT 24
Peak memory 217152 kb
Host smart-6830747a-d0fa-4bd1-acbf-267bdb28c7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341909144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1341909144
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.302365776
Short name T329
Test name
Test status
Simulation time 41417299037 ps
CPU time 115.33 seconds
Started May 05 12:42:27 PM PDT 24
Finished May 05 12:44:23 PM PDT 24
Peak memory 222716 kb
Host smart-98ffe7ce-1444-4a88-8c84-ef031bd1b469
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302365776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.302365776
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2834648039
Short name T16
Test name
Test status
Simulation time 79031574097 ps
CPU time 9896.56 seconds
Started May 05 12:42:13 PM PDT 24
Finished May 05 03:27:11 PM PDT 24
Peak memory 249940 kb
Host smart-149864ca-1081-4a02-a7aa-543982ccae75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834648039 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2834648039
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.4250492469
Short name T357
Test name
Test status
Simulation time 9840911640 ps
CPU time 24.09 seconds
Started May 05 12:42:27 PM PDT 24
Finished May 05 12:42:53 PM PDT 24
Peak memory 211872 kb
Host smart-70d961d6-abf2-417f-80f9-09b96011ea53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250492469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.4250492469
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2031716821
Short name T217
Test name
Test status
Simulation time 323347813901 ps
CPU time 765.26 seconds
Started May 05 12:42:14 PM PDT 24
Finished May 05 12:55:00 PM PDT 24
Peak memory 240028 kb
Host smart-088d1b9c-67d9-45ef-8a5c-c0224f9ad4df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031716821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2031716821
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.4129160264
Short name T286
Test name
Test status
Simulation time 6329937482 ps
CPU time 55.48 seconds
Started May 05 12:42:28 PM PDT 24
Finished May 05 12:43:24 PM PDT 24
Peak memory 215544 kb
Host smart-33c4c8fc-14d6-4d71-a8b5-2337e0675a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129160264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.4129160264
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2915589367
Short name T239
Test name
Test status
Simulation time 9213609241 ps
CPU time 24.03 seconds
Started May 05 12:42:28 PM PDT 24
Finished May 05 12:42:53 PM PDT 24
Peak memory 213236 kb
Host smart-71eba9d0-6a46-4aab-93d2-a7b97ddfb7b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2915589367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2915589367
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1435187616
Short name T241
Test name
Test status
Simulation time 10883506413 ps
CPU time 54.41 seconds
Started May 05 12:42:21 PM PDT 24
Finished May 05 12:43:16 PM PDT 24
Peak memory 216872 kb
Host smart-163c9672-8326-461e-b400-0941e77281b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435187616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1435187616
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1799855242
Short name T281
Test name
Test status
Simulation time 16378504861 ps
CPU time 161.1 seconds
Started May 05 12:42:15 PM PDT 24
Finished May 05 12:44:57 PM PDT 24
Peak memory 219904 kb
Host smart-96ef8c95-33ee-4db6-8003-e4148fc33002
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799855242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1799855242
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.745295440
Short name T33
Test name
Test status
Simulation time 10217655979 ps
CPU time 23.27 seconds
Started May 05 12:42:33 PM PDT 24
Finished May 05 12:42:58 PM PDT 24
Peak memory 212688 kb
Host smart-1ba0cafc-596e-4708-89d2-95e83ada42b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745295440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.745295440
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1517172364
Short name T37
Test name
Test status
Simulation time 3677350233 ps
CPU time 243.8 seconds
Started May 05 12:42:16 PM PDT 24
Finished May 05 12:46:21 PM PDT 24
Peak memory 226324 kb
Host smart-b3484b2d-546d-4705-866e-cfc7229eda29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517172364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1517172364
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2260124057
Short name T245
Test name
Test status
Simulation time 21773536746 ps
CPU time 54.41 seconds
Started May 05 12:42:24 PM PDT 24
Finished May 05 12:43:20 PM PDT 24
Peak memory 214420 kb
Host smart-bef6ddb7-3833-4b7f-a83f-746dccb3402a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260124057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2260124057
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1718175974
Short name T45
Test name
Test status
Simulation time 4461569588 ps
CPU time 22.32 seconds
Started May 05 12:42:37 PM PDT 24
Finished May 05 12:43:00 PM PDT 24
Peak memory 213128 kb
Host smart-76122b3f-60aa-4353-b127-99b680637260
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1718175974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1718175974
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1301980543
Short name T6
Test name
Test status
Simulation time 15466954596 ps
CPU time 80.66 seconds
Started May 05 12:42:15 PM PDT 24
Finished May 05 12:43:37 PM PDT 24
Peak memory 218128 kb
Host smart-6724b4f4-8134-4e99-bd93-30b36d31fe9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301980543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1301980543
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1710152567
Short name T272
Test name
Test status
Simulation time 205531153 ps
CPU time 14.19 seconds
Started May 05 12:42:17 PM PDT 24
Finished May 05 12:42:32 PM PDT 24
Peak memory 214100 kb
Host smart-2f9103b7-35b2-45d3-a295-c600fa2581d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710152567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1710152567
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3590982906
Short name T253
Test name
Test status
Simulation time 8002381406 ps
CPU time 32.28 seconds
Started May 05 12:41:56 PM PDT 24
Finished May 05 12:42:30 PM PDT 24
Peak memory 212684 kb
Host smart-7e7a5410-c80c-4b75-8bfe-36537a199dca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590982906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3590982906
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3817724312
Short name T156
Test name
Test status
Simulation time 22134404547 ps
CPU time 361.35 seconds
Started May 05 12:42:01 PM PDT 24
Finished May 05 12:48:04 PM PDT 24
Peak memory 234960 kb
Host smart-395848c7-9d49-44e8-8469-4bce3adda95a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817724312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3817724312
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4026336725
Short name T282
Test name
Test status
Simulation time 26725959151 ps
CPU time 56.86 seconds
Started May 05 12:42:40 PM PDT 24
Finished May 05 12:43:38 PM PDT 24
Peak memory 213592 kb
Host smart-4e933e40-93b4-4fd2-8e32-df0e88bb3637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026336725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.4026336725
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1855465085
Short name T40
Test name
Test status
Simulation time 3716338037 ps
CPU time 31.82 seconds
Started May 05 12:42:22 PM PDT 24
Finished May 05 12:42:56 PM PDT 24
Peak memory 212728 kb
Host smart-30c23199-cd39-4e6d-8b81-0e6a26902f9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1855465085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1855465085
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2107359093
Short name T31
Test name
Test status
Simulation time 6663120894 ps
CPU time 135.09 seconds
Started May 05 12:42:12 PM PDT 24
Finished May 05 12:44:28 PM PDT 24
Peak memory 237228 kb
Host smart-2ad39504-dbac-47a8-a4ca-c1f9204c2286
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107359093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2107359093
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3994102151
Short name T125
Test name
Test status
Simulation time 27360524523 ps
CPU time 54.4 seconds
Started May 05 12:42:24 PM PDT 24
Finished May 05 12:43:20 PM PDT 24
Peak memory 219040 kb
Host smart-f8397357-ff9a-4ce2-8741-cf1ca2c36b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994102151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3994102151
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2872699580
Short name T221
Test name
Test status
Simulation time 338936989 ps
CPU time 8.22 seconds
Started May 05 12:42:41 PM PDT 24
Finished May 05 12:42:50 PM PDT 24
Peak memory 211716 kb
Host smart-3e23e213-8619-4a32-a941-57915a7d0c6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872699580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2872699580
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1640946040
Short name T275
Test name
Test status
Simulation time 45681342115 ps
CPU time 594.9 seconds
Started May 05 12:42:37 PM PDT 24
Finished May 05 12:52:33 PM PDT 24
Peak memory 240492 kb
Host smart-d5db4349-38f8-4bfd-910d-2267923778a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640946040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1640946040
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2537209675
Short name T152
Test name
Test status
Simulation time 9256972440 ps
CPU time 70.44 seconds
Started May 05 12:42:43 PM PDT 24
Finished May 05 12:43:55 PM PDT 24
Peak memory 214556 kb
Host smart-47069d40-7881-4af0-ba5a-805193311ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537209675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2537209675
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1861453921
Short name T309
Test name
Test status
Simulation time 914383260 ps
CPU time 15.95 seconds
Started May 05 12:42:41 PM PDT 24
Finished May 05 12:42:58 PM PDT 24
Peak memory 212940 kb
Host smart-29d73b84-2d54-47d7-93da-c1a45aad9482
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1861453921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1861453921
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2985780431
Short name T122
Test name
Test status
Simulation time 6901914147 ps
CPU time 32.38 seconds
Started May 05 12:42:20 PM PDT 24
Finished May 05 12:42:54 PM PDT 24
Peak memory 216376 kb
Host smart-8db379fa-654c-4f44-8bf1-0ec268866438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985780431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2985780431
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3494382109
Short name T130
Test name
Test status
Simulation time 5743896108 ps
CPU time 49.99 seconds
Started May 05 12:42:37 PM PDT 24
Finished May 05 12:43:28 PM PDT 24
Peak memory 217928 kb
Host smart-22185a75-2e4a-4e86-b5cc-5095d4ba339b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494382109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3494382109
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2815804008
Short name T352
Test name
Test status
Simulation time 2096871750 ps
CPU time 20.81 seconds
Started May 05 12:42:42 PM PDT 24
Finished May 05 12:43:04 PM PDT 24
Peak memory 212364 kb
Host smart-1584efb1-9a6a-4edc-b67b-03be2761b678
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815804008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2815804008
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.515039951
Short name T117
Test name
Test status
Simulation time 25112974764 ps
CPU time 287.13 seconds
Started May 05 12:42:21 PM PDT 24
Finished May 05 12:47:10 PM PDT 24
Peak memory 240196 kb
Host smart-aa120007-ea24-41c8-8230-67201004d2b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515039951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.515039951
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.91823847
Short name T149
Test name
Test status
Simulation time 1493789821 ps
CPU time 29.78 seconds
Started May 05 12:42:22 PM PDT 24
Finished May 05 12:42:54 PM PDT 24
Peak memory 215020 kb
Host smart-262e4747-7773-4408-ad99-dcf28a4b8344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91823847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.91823847
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1532858798
Short name T339
Test name
Test status
Simulation time 2096246418 ps
CPU time 13.84 seconds
Started May 05 12:42:40 PM PDT 24
Finished May 05 12:42:54 PM PDT 24
Peak memory 211776 kb
Host smart-8ea62a2b-0464-41e2-b4c4-ad0c57f29954
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1532858798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1532858798
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2925501650
Short name T228
Test name
Test status
Simulation time 535704746 ps
CPU time 22.95 seconds
Started May 05 12:42:34 PM PDT 24
Finished May 05 12:42:58 PM PDT 24
Peak memory 217092 kb
Host smart-2cada95d-d95a-41ce-a6af-558e0475921a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925501650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2925501650
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2998509064
Short name T249
Test name
Test status
Simulation time 1402457435 ps
CPU time 27.23 seconds
Started May 05 12:42:40 PM PDT 24
Finished May 05 12:43:08 PM PDT 24
Peak memory 215980 kb
Host smart-f55a4d26-c45a-4e7b-8ef5-75f21fcdf053
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998509064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2998509064
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1987697593
Short name T190
Test name
Test status
Simulation time 1375343103 ps
CPU time 19.25 seconds
Started May 05 12:42:42 PM PDT 24
Finished May 05 12:43:02 PM PDT 24
Peak memory 215192 kb
Host smart-ed45b461-add2-4a8c-aa73-7519d52db8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987697593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1987697593
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1756602564
Short name T270
Test name
Test status
Simulation time 835971071 ps
CPU time 10.55 seconds
Started May 05 12:42:20 PM PDT 24
Finished May 05 12:42:37 PM PDT 24
Peak memory 213016 kb
Host smart-1da90a7a-3bb7-4cc8-97d4-ba63447db606
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1756602564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1756602564
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1463257753
Short name T315
Test name
Test status
Simulation time 2643351591 ps
CPU time 40.23 seconds
Started May 05 12:42:41 PM PDT 24
Finished May 05 12:43:23 PM PDT 24
Peak memory 217864 kb
Host smart-f0b2c979-68e1-45d8-bced-66eafab81620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463257753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1463257753
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.397512743
Short name T303
Test name
Test status
Simulation time 26769037583 ps
CPU time 107.27 seconds
Started May 05 12:42:24 PM PDT 24
Finished May 05 12:44:12 PM PDT 24
Peak memory 222684 kb
Host smart-060032ec-102a-47b7-a199-d0057630c25d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397512743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.397512743
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1126854178
Short name T134
Test name
Test status
Simulation time 9819610116 ps
CPU time 23.45 seconds
Started May 05 12:42:17 PM PDT 24
Finished May 05 12:42:41 PM PDT 24
Peak memory 211928 kb
Host smart-bcc02c76-f2c4-4515-b60b-874e16628510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126854178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1126854178
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.671851462
Short name T267
Test name
Test status
Simulation time 618325431496 ps
CPU time 908.36 seconds
Started May 05 12:42:22 PM PDT 24
Finished May 05 12:57:32 PM PDT 24
Peak memory 218248 kb
Host smart-593b5e52-5cb7-4a56-87ec-5d48bfad99d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671851462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.671851462
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1687816883
Short name T173
Test name
Test status
Simulation time 8525140909 ps
CPU time 68.78 seconds
Started May 05 12:42:43 PM PDT 24
Finished May 05 12:43:52 PM PDT 24
Peak memory 215504 kb
Host smart-60c93083-7660-47e5-9e91-6737c6c2eca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687816883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1687816883
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.797338576
Short name T182
Test name
Test status
Simulation time 12390590596 ps
CPU time 24.27 seconds
Started May 05 12:42:12 PM PDT 24
Finished May 05 12:42:37 PM PDT 24
Peak memory 212164 kb
Host smart-58c1edc6-ab9f-4d3d-8f96-2ab81ac18df0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=797338576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.797338576
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2279493244
Short name T257
Test name
Test status
Simulation time 26202086401 ps
CPU time 59.48 seconds
Started May 05 12:42:40 PM PDT 24
Finished May 05 12:43:40 PM PDT 24
Peak memory 218440 kb
Host smart-4d1beadf-8433-411b-bf19-b7fb84934574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279493244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2279493244
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3306947501
Short name T293
Test name
Test status
Simulation time 3130211357 ps
CPU time 24.61 seconds
Started May 05 12:42:36 PM PDT 24
Finished May 05 12:43:02 PM PDT 24
Peak memory 214028 kb
Host smart-a26f9e84-27d5-4d00-b335-5d2db2409cb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306947501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3306947501
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1364735190
Short name T321
Test name
Test status
Simulation time 394349042 ps
CPU time 8.07 seconds
Started May 05 12:42:42 PM PDT 24
Finished May 05 12:42:51 PM PDT 24
Peak memory 211724 kb
Host smart-cfaa1522-1ab0-4bf5-8ddc-de137c2f8f1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364735190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1364735190
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3842159483
Short name T229
Test name
Test status
Simulation time 113974226458 ps
CPU time 1153.97 seconds
Started May 05 12:42:41 PM PDT 24
Finished May 05 01:01:56 PM PDT 24
Peak memory 239252 kb
Host smart-b2de79e6-c787-40ab-8a85-19489b9950f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842159483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3842159483
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.315550417
Short name T26
Test name
Test status
Simulation time 7712257968 ps
CPU time 44.7 seconds
Started May 05 12:42:40 PM PDT 24
Finished May 05 12:43:26 PM PDT 24
Peak memory 213520 kb
Host smart-4506df41-d153-4bf0-8fbf-7a09e643432e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315550417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.315550417
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1656988493
Short name T254
Test name
Test status
Simulation time 12797818351 ps
CPU time 33.1 seconds
Started May 05 12:42:22 PM PDT 24
Finished May 05 12:42:57 PM PDT 24
Peak memory 213268 kb
Host smart-dc5efa44-ebfe-407f-8036-92d266a9e8df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1656988493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1656988493
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2703833845
Short name T320
Test name
Test status
Simulation time 40047097044 ps
CPU time 64.35 seconds
Started May 05 12:42:33 PM PDT 24
Finished May 05 12:43:39 PM PDT 24
Peak memory 217744 kb
Host smart-e50a522d-7240-4154-9f19-007c01c7cfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703833845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2703833845
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1386841401
Short name T184
Test name
Test status
Simulation time 3915996830 ps
CPU time 34.93 seconds
Started May 05 12:42:39 PM PDT 24
Finished May 05 12:43:14 PM PDT 24
Peak memory 212820 kb
Host smart-bedf61d2-c6da-4cc9-b6c2-929eef8ca75d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386841401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1386841401
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2021957157
Short name T279
Test name
Test status
Simulation time 3030563645 ps
CPU time 27.22 seconds
Started May 05 12:42:28 PM PDT 24
Finished May 05 12:42:56 PM PDT 24
Peak memory 212460 kb
Host smart-45c2bf7e-935b-4784-bf82-07e00142b716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021957157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2021957157
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.844346938
Short name T21
Test name
Test status
Simulation time 70870633149 ps
CPU time 677.93 seconds
Started May 05 12:42:43 PM PDT 24
Finished May 05 12:54:03 PM PDT 24
Peak memory 234560 kb
Host smart-a37623fd-a163-4756-888d-59441ad5bc8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844346938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.844346938
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.443051311
Short name T323
Test name
Test status
Simulation time 988813462 ps
CPU time 21.76 seconds
Started May 05 12:42:41 PM PDT 24
Finished May 05 12:43:04 PM PDT 24
Peak memory 213160 kb
Host smart-89481af6-e548-420a-80b7-1cd2fe40fcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443051311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.443051311
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2471944290
Short name T150
Test name
Test status
Simulation time 185049495 ps
CPU time 10.32 seconds
Started May 05 12:42:33 PM PDT 24
Finished May 05 12:42:44 PM PDT 24
Peak memory 212728 kb
Host smart-d6f0d508-30fa-4c49-9240-03d72d5d46eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2471944290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2471944290
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1096067620
Short name T177
Test name
Test status
Simulation time 13391205916 ps
CPU time 69.04 seconds
Started May 05 12:42:41 PM PDT 24
Finished May 05 12:43:51 PM PDT 24
Peak memory 218684 kb
Host smart-38f192cd-51b1-46b2-9dcd-01d143b8fba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096067620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1096067620
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3355360254
Short name T215
Test name
Test status
Simulation time 12886610559 ps
CPU time 108.81 seconds
Started May 05 12:42:45 PM PDT 24
Finished May 05 12:44:37 PM PDT 24
Peak memory 220340 kb
Host smart-cb014672-e61f-4747-bbae-3043d0b55886
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355360254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3355360254
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2023346857
Short name T48
Test name
Test status
Simulation time 22610688571 ps
CPU time 796.21 seconds
Started May 05 12:42:21 PM PDT 24
Finished May 05 12:55:39 PM PDT 24
Peak memory 231300 kb
Host smart-db7f73ae-1b40-403c-b012-04d1a08521c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023346857 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2023346857
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.68689439
Short name T136
Test name
Test status
Simulation time 2299002567 ps
CPU time 22.22 seconds
Started May 05 12:42:42 PM PDT 24
Finished May 05 12:43:09 PM PDT 24
Peak memory 212500 kb
Host smart-63e99228-f5ab-4c0c-9978-d1a0e6df22bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68689439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.68689439
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4161428347
Short name T222
Test name
Test status
Simulation time 62824028766 ps
CPU time 348.4 seconds
Started May 05 12:42:41 PM PDT 24
Finished May 05 12:48:30 PM PDT 24
Peak memory 225604 kb
Host smart-05fffffd-4c88-4b4c-8fb8-0b0d2ead9c49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161428347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.4161428347
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3309485174
Short name T198
Test name
Test status
Simulation time 2841196668 ps
CPU time 25.21 seconds
Started May 05 12:42:27 PM PDT 24
Finished May 05 12:42:53 PM PDT 24
Peak memory 215304 kb
Host smart-ebb91286-b351-47e2-b9d0-5f60510d0607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309485174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3309485174
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3730575857
Short name T46
Test name
Test status
Simulation time 22720557665 ps
CPU time 27.02 seconds
Started May 05 12:42:21 PM PDT 24
Finished May 05 12:42:50 PM PDT 24
Peak memory 213416 kb
Host smart-79728f3a-ebf6-412d-a78d-a8ddf2d99bf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3730575857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3730575857
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3201912649
Short name T252
Test name
Test status
Simulation time 4647687328 ps
CPU time 34.77 seconds
Started May 05 12:42:39 PM PDT 24
Finished May 05 12:43:15 PM PDT 24
Peak memory 218472 kb
Host smart-33a454ed-bbad-42eb-8c3b-f0533271fc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201912649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3201912649
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.4097442543
Short name T318
Test name
Test status
Simulation time 67055404639 ps
CPU time 186.84 seconds
Started May 05 12:42:43 PM PDT 24
Finished May 05 12:45:51 PM PDT 24
Peak memory 221132 kb
Host smart-33fd5fcb-6f66-4bc3-b453-b01e8122f5e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097442543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.4097442543
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3596543835
Short name T47
Test name
Test status
Simulation time 227205532224 ps
CPU time 1932.67 seconds
Started May 05 12:42:42 PM PDT 24
Finished May 05 01:14:56 PM PDT 24
Peak memory 244528 kb
Host smart-86c065e2-78e9-4ba5-9651-7243782d3af0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596543835 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3596543835
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3577446434
Short name T224
Test name
Test status
Simulation time 5255665901 ps
CPU time 17.17 seconds
Started May 05 12:42:39 PM PDT 24
Finished May 05 12:42:57 PM PDT 24
Peak memory 211912 kb
Host smart-9640c421-3df7-463c-916c-bf8b0a7739bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577446434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3577446434
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2204905761
Short name T12
Test name
Test status
Simulation time 105305189462 ps
CPU time 375.87 seconds
Started May 05 12:42:26 PM PDT 24
Finished May 05 12:48:43 PM PDT 24
Peak memory 217632 kb
Host smart-6924a655-e22f-41e5-9873-fd4be42280e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204905761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2204905761
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3720971675
Short name T338
Test name
Test status
Simulation time 36991750720 ps
CPU time 73.55 seconds
Started May 05 12:42:22 PM PDT 24
Finished May 05 12:43:37 PM PDT 24
Peak memory 215528 kb
Host smart-a1335fb3-cf2e-4d8b-83d9-207b72ee3c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720971675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3720971675
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.588849496
Short name T313
Test name
Test status
Simulation time 349287585 ps
CPU time 10.04 seconds
Started May 05 12:42:39 PM PDT 24
Finished May 05 12:42:50 PM PDT 24
Peak memory 212980 kb
Host smart-7d19b5a4-218e-4964-ad8f-83eaa9cb6637
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=588849496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.588849496
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3593893574
Short name T179
Test name
Test status
Simulation time 25408913325 ps
CPU time 66.21 seconds
Started May 05 12:42:32 PM PDT 24
Finished May 05 12:43:39 PM PDT 24
Peak memory 218428 kb
Host smart-453fdf06-ef5c-4942-a257-44b9e8fa4f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593893574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3593893574
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2016983450
Short name T220
Test name
Test status
Simulation time 7108455101 ps
CPU time 48.5 seconds
Started May 05 12:42:25 PM PDT 24
Finished May 05 12:43:14 PM PDT 24
Peak memory 219860 kb
Host smart-88c7d7fe-f38c-4785-9476-b3e51e268953
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016983450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2016983450
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.4242400664
Short name T210
Test name
Test status
Simulation time 522416792 ps
CPU time 12.21 seconds
Started May 05 12:42:37 PM PDT 24
Finished May 05 12:42:50 PM PDT 24
Peak memory 211748 kb
Host smart-151f163f-f4d0-4dbd-ad8f-a5f8ce1c899d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242400664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.4242400664
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2709183676
Short name T192
Test name
Test status
Simulation time 37021264749 ps
CPU time 491.66 seconds
Started May 05 12:42:25 PM PDT 24
Finished May 05 12:50:38 PM PDT 24
Peak memory 240240 kb
Host smart-1edf1785-5011-4661-9050-e96dd0737b72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709183676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2709183676
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1758413715
Short name T2
Test name
Test status
Simulation time 3628773267 ps
CPU time 40.3 seconds
Started May 05 12:42:29 PM PDT 24
Finished May 05 12:43:10 PM PDT 24
Peak memory 215300 kb
Host smart-90305bb6-1549-4a68-8e87-cb5ddd5912d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758413715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1758413715
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.796229786
Short name T307
Test name
Test status
Simulation time 3390647880 ps
CPU time 30.62 seconds
Started May 05 12:42:36 PM PDT 24
Finished May 05 12:43:07 PM PDT 24
Peak memory 212896 kb
Host smart-93be6818-56e5-4552-b5e9-221c769f15fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=796229786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.796229786
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2078924563
Short name T83
Test name
Test status
Simulation time 17524665660 ps
CPU time 42.82 seconds
Started May 05 12:42:23 PM PDT 24
Finished May 05 12:43:07 PM PDT 24
Peak memory 216016 kb
Host smart-6285ca19-a52d-4998-8b25-3d46b083d63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078924563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2078924563
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3064401335
Short name T331
Test name
Test status
Simulation time 15418005698 ps
CPU time 155.96 seconds
Started May 05 12:42:44 PM PDT 24
Finished May 05 12:45:22 PM PDT 24
Peak memory 221888 kb
Host smart-e3d2399c-f113-434a-b1eb-762a27eaa282
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064401335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3064401335
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1131921888
Short name T325
Test name
Test status
Simulation time 190077368 ps
CPU time 8.4 seconds
Started May 05 12:42:39 PM PDT 24
Finished May 05 12:42:48 PM PDT 24
Peak memory 211740 kb
Host smart-91f25018-7047-4043-92fa-4322be030221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131921888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1131921888
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1042263988
Short name T191
Test name
Test status
Simulation time 54602954365 ps
CPU time 224.91 seconds
Started May 05 12:42:39 PM PDT 24
Finished May 05 12:46:25 PM PDT 24
Peak memory 236964 kb
Host smart-94c10865-e951-4eaf-8c90-a7e83ec2eebb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042263988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1042263988
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.306027567
Short name T289
Test name
Test status
Simulation time 660861652 ps
CPU time 19.13 seconds
Started May 05 12:42:41 PM PDT 24
Finished May 05 12:43:01 PM PDT 24
Peak memory 215144 kb
Host smart-bb968647-16bd-416d-a56e-db6232f19be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306027567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.306027567
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1290227911
Short name T280
Test name
Test status
Simulation time 2365686260 ps
CPU time 17.66 seconds
Started May 05 12:42:38 PM PDT 24
Finished May 05 12:42:56 PM PDT 24
Peak memory 211980 kb
Host smart-5399feff-48ca-4771-882d-39ad41a752e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1290227911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1290227911
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2776972097
Short name T263
Test name
Test status
Simulation time 6623325907 ps
CPU time 31.76 seconds
Started May 05 12:42:44 PM PDT 24
Finished May 05 12:43:18 PM PDT 24
Peak memory 215484 kb
Host smart-16a36b95-3572-4c28-a2b5-2e2761d9917e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776972097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2776972097
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2758026434
Short name T235
Test name
Test status
Simulation time 16587210784 ps
CPU time 88.63 seconds
Started May 05 12:42:37 PM PDT 24
Finished May 05 12:44:06 PM PDT 24
Peak memory 222976 kb
Host smart-2060f021-8c18-40fb-a911-21d0fa5407c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758026434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2758026434
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3028809440
Short name T332
Test name
Test status
Simulation time 661218279 ps
CPU time 8.43 seconds
Started May 05 12:42:33 PM PDT 24
Finished May 05 12:42:42 PM PDT 24
Peak memory 211692 kb
Host smart-340a22d0-21d6-49a3-8de3-b0b0b0de8c53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028809440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3028809440
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2587754685
Short name T299
Test name
Test status
Simulation time 221068573911 ps
CPU time 540.47 seconds
Started May 05 12:41:58 PM PDT 24
Finished May 05 12:51:01 PM PDT 24
Peak memory 237816 kb
Host smart-b7ae0b32-9c27-4bcd-9eee-e18ba81c0532
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587754685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2587754685
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.158127306
Short name T260
Test name
Test status
Simulation time 12053741873 ps
CPU time 55.41 seconds
Started May 05 12:42:27 PM PDT 24
Finished May 05 12:43:23 PM PDT 24
Peak memory 215384 kb
Host smart-2f7db999-1b6b-4186-b784-713bdd3c5d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158127306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.158127306
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1260211193
Short name T155
Test name
Test status
Simulation time 672893098 ps
CPU time 15.13 seconds
Started May 05 12:42:01 PM PDT 24
Finished May 05 12:42:18 PM PDT 24
Peak memory 211720 kb
Host smart-99511da4-6b09-4f3e-b1cc-b7014dd812ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260211193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1260211193
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1562446143
Short name T35
Test name
Test status
Simulation time 3196940777 ps
CPU time 232.95 seconds
Started May 05 12:42:18 PM PDT 24
Finished May 05 12:46:12 PM PDT 24
Peak memory 239396 kb
Host smart-03a4ad3d-9a9f-467b-83ce-d994cd1b6f24
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562446143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1562446143
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.156022660
Short name T328
Test name
Test status
Simulation time 1384358928 ps
CPU time 19.77 seconds
Started May 05 12:42:33 PM PDT 24
Finished May 05 12:42:54 PM PDT 24
Peak memory 217996 kb
Host smart-9eca0251-e28d-4ae8-90c6-a6cdcb112631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156022660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.156022660
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2661459874
Short name T118
Test name
Test status
Simulation time 111317400566 ps
CPU time 149.09 seconds
Started May 05 12:42:14 PM PDT 24
Finished May 05 12:44:49 PM PDT 24
Peak memory 220316 kb
Host smart-f9c982fb-0fa8-44b2-b8fe-c36a1a6bdb12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661459874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2661459874
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2892216845
Short name T65
Test name
Test status
Simulation time 636253986 ps
CPU time 8.28 seconds
Started May 05 12:42:49 PM PDT 24
Finished May 05 12:42:59 PM PDT 24
Peak memory 211720 kb
Host smart-8c35744d-d714-4d74-8e9f-cf8bb33cbdc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892216845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2892216845
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.405136398
Short name T231
Test name
Test status
Simulation time 43594077144 ps
CPU time 413.14 seconds
Started May 05 12:42:33 PM PDT 24
Finished May 05 12:49:27 PM PDT 24
Peak memory 229184 kb
Host smart-a6d33c75-d4f2-41aa-b93f-bab5aebcf2e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405136398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.405136398
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2889812364
Short name T348
Test name
Test status
Simulation time 6825419781 ps
CPU time 30.82 seconds
Started May 05 12:42:43 PM PDT 24
Finished May 05 12:43:15 PM PDT 24
Peak memory 215864 kb
Host smart-5795488f-3621-4ac3-9e35-9c91d27072d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889812364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2889812364
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3728978452
Short name T137
Test name
Test status
Simulation time 703518527 ps
CPU time 10.65 seconds
Started May 05 12:42:44 PM PDT 24
Finished May 05 12:42:58 PM PDT 24
Peak memory 212676 kb
Host smart-135a0d1b-4179-46d4-bad7-7893b6882c28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3728978452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3728978452
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1979190741
Short name T82
Test name
Test status
Simulation time 1305441003 ps
CPU time 26.39 seconds
Started May 05 12:42:30 PM PDT 24
Finished May 05 12:42:57 PM PDT 24
Peak memory 216336 kb
Host smart-1212887f-e36d-4088-8bc8-17cd35472105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979190741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1979190741
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1157035284
Short name T350
Test name
Test status
Simulation time 39243129892 ps
CPU time 90.18 seconds
Started May 05 12:42:44 PM PDT 24
Finished May 05 12:44:16 PM PDT 24
Peak memory 219384 kb
Host smart-0ec1265e-77eb-471c-8c88-cda486c80b18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157035284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1157035284
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.4089064295
Short name T187
Test name
Test status
Simulation time 25282290483 ps
CPU time 35.58 seconds
Started May 05 12:42:42 PM PDT 24
Finished May 05 12:43:18 PM PDT 24
Peak memory 212720 kb
Host smart-087b4c36-ad64-4db4-8360-6ad120f3d56f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089064295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4089064295
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1224434023
Short name T322
Test name
Test status
Simulation time 347121396379 ps
CPU time 856.9 seconds
Started May 05 12:42:50 PM PDT 24
Finished May 05 12:57:09 PM PDT 24
Peak memory 240436 kb
Host smart-a099a44d-962c-44ba-9efe-b6906293e9b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224434023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1224434023
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3099212568
Short name T43
Test name
Test status
Simulation time 15953246974 ps
CPU time 57.74 seconds
Started May 05 12:42:43 PM PDT 24
Finished May 05 12:43:41 PM PDT 24
Peak memory 215588 kb
Host smart-2cb4725b-0723-4d5f-a0d4-048df86e2731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099212568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3099212568
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1203822323
Short name T151
Test name
Test status
Simulation time 37961947680 ps
CPU time 30.71 seconds
Started May 05 12:42:41 PM PDT 24
Finished May 05 12:43:13 PM PDT 24
Peak memory 212280 kb
Host smart-128dde89-bd70-499f-94db-ffd397ba0dd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1203822323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1203822323
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3031275535
Short name T236
Test name
Test status
Simulation time 12973682145 ps
CPU time 64.43 seconds
Started May 05 12:42:26 PM PDT 24
Finished May 05 12:43:31 PM PDT 24
Peak memory 218600 kb
Host smart-9aa736e7-a667-409a-b8df-02106e92f55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031275535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3031275535
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3882453878
Short name T81
Test name
Test status
Simulation time 11128837421 ps
CPU time 64.08 seconds
Started May 05 12:42:44 PM PDT 24
Finished May 05 12:43:52 PM PDT 24
Peak memory 216092 kb
Host smart-e31cd00a-5746-40cb-8fde-34b53fc1dee4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882453878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3882453878
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1061328406
Short name T353
Test name
Test status
Simulation time 3425091817 ps
CPU time 28.48 seconds
Started May 05 12:42:47 PM PDT 24
Finished May 05 12:43:18 PM PDT 24
Peak memory 212400 kb
Host smart-01b64efe-b6c3-4f7d-a920-324a39350839
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061328406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1061328406
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.997616707
Short name T251
Test name
Test status
Simulation time 69456758251 ps
CPU time 704.42 seconds
Started May 05 12:42:25 PM PDT 24
Finished May 05 12:54:11 PM PDT 24
Peak memory 225488 kb
Host smart-c196bfda-ab9f-4838-86d1-4ab7953f6810
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997616707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.997616707
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3150420211
Short name T294
Test name
Test status
Simulation time 332777364 ps
CPU time 19.56 seconds
Started May 05 12:42:25 PM PDT 24
Finished May 05 12:42:46 PM PDT 24
Peak memory 215164 kb
Host smart-22d52634-2e00-414a-8b94-dc3b5fd2a5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150420211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3150420211
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2799218156
Short name T3
Test name
Test status
Simulation time 1326541164 ps
CPU time 10.38 seconds
Started May 05 12:42:44 PM PDT 24
Finished May 05 12:42:56 PM PDT 24
Peak memory 212964 kb
Host smart-7beb110e-32d4-4442-a4d3-b84068c8ca57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2799218156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2799218156
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2029146610
Short name T147
Test name
Test status
Simulation time 5593200485 ps
CPU time 53.16 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:43:41 PM PDT 24
Peak memory 218068 kb
Host smart-51da619f-5e7c-4e87-8382-04af51cc3ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029146610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2029146610
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1937104927
Short name T334
Test name
Test status
Simulation time 31059987598 ps
CPU time 76.08 seconds
Started May 05 12:42:43 PM PDT 24
Finished May 05 12:44:00 PM PDT 24
Peak memory 216580 kb
Host smart-f80368c8-bae4-4d75-81c5-c64ba211a6d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937104927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1937104927
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3736210679
Short name T55
Test name
Test status
Simulation time 4966091940 ps
CPU time 31.81 seconds
Started May 05 12:42:43 PM PDT 24
Finished May 05 12:43:16 PM PDT 24
Peak memory 212696 kb
Host smart-ab69be9b-d388-4560-aa8e-25dcc97c5f9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736210679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3736210679
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3591800892
Short name T188
Test name
Test status
Simulation time 25393643049 ps
CPU time 297.07 seconds
Started May 05 12:42:34 PM PDT 24
Finished May 05 12:47:32 PM PDT 24
Peak memory 240996 kb
Host smart-609d2d8d-eff5-4eaf-adc3-13749e19ff75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591800892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3591800892
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1430257798
Short name T308
Test name
Test status
Simulation time 2838642161 ps
CPU time 37.61 seconds
Started May 05 12:42:42 PM PDT 24
Finished May 05 12:43:20 PM PDT 24
Peak memory 215268 kb
Host smart-3f774f9c-5afe-427d-9c30-3dd91e460ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430257798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1430257798
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.373670180
Short name T302
Test name
Test status
Simulation time 2972461978 ps
CPU time 27.87 seconds
Started May 05 12:42:44 PM PDT 24
Finished May 05 12:43:13 PM PDT 24
Peak memory 212776 kb
Host smart-b689e6bd-a0c6-45c2-8f00-817b7de4c36f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=373670180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.373670180
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1791043749
Short name T154
Test name
Test status
Simulation time 7046219431 ps
CPU time 65.12 seconds
Started May 05 12:42:27 PM PDT 24
Finished May 05 12:43:33 PM PDT 24
Peak memory 218012 kb
Host smart-dd714e97-2d47-4196-8afa-ad63c8f9d0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791043749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1791043749
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2892662781
Short name T120
Test name
Test status
Simulation time 867775078 ps
CPU time 11.38 seconds
Started May 05 12:42:44 PM PDT 24
Finished May 05 12:42:57 PM PDT 24
Peak memory 213728 kb
Host smart-049aeae4-ecf4-4204-856d-7f3eacc11a19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892662781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2892662781
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.533833876
Short name T355
Test name
Test status
Simulation time 3845279738 ps
CPU time 19.92 seconds
Started May 05 12:42:47 PM PDT 24
Finished May 05 12:43:09 PM PDT 24
Peak memory 211920 kb
Host smart-f427597d-614f-40bb-8f31-169d163595e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533833876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.533833876
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3151610832
Short name T23
Test name
Test status
Simulation time 111919911400 ps
CPU time 323.01 seconds
Started May 05 12:42:32 PM PDT 24
Finished May 05 12:47:56 PM PDT 24
Peak memory 237428 kb
Host smart-791f3efb-732e-4b03-b703-244a8cde3136
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151610832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3151610832
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.728322055
Short name T18
Test name
Test status
Simulation time 1320783997 ps
CPU time 18.9 seconds
Started May 05 12:42:45 PM PDT 24
Finished May 05 12:43:07 PM PDT 24
Peak memory 215096 kb
Host smart-78eb5e3a-c283-44c6-a255-0c05aaf09918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728322055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.728322055
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1250399947
Short name T247
Test name
Test status
Simulation time 15576484152 ps
CPU time 29.83 seconds
Started May 05 12:42:43 PM PDT 24
Finished May 05 12:43:13 PM PDT 24
Peak memory 212156 kb
Host smart-bca1e809-0ef0-4a1f-8461-8737ad5527d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1250399947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1250399947
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3588790861
Short name T262
Test name
Test status
Simulation time 3133145701 ps
CPU time 19.91 seconds
Started May 05 12:42:45 PM PDT 24
Finished May 05 12:43:06 PM PDT 24
Peak memory 218712 kb
Host smart-2c1b5ebd-b5bc-40ed-8388-8deb7dcba664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588790861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3588790861
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.178909091
Short name T273
Test name
Test status
Simulation time 6371249146 ps
CPU time 62.83 seconds
Started May 05 12:42:35 PM PDT 24
Finished May 05 12:43:39 PM PDT 24
Peak memory 217576 kb
Host smart-e4300137-2725-4869-8414-7dc865afcacb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178909091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.178909091
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2560479739
Short name T194
Test name
Test status
Simulation time 1615138520 ps
CPU time 13.58 seconds
Started May 05 12:42:45 PM PDT 24
Finished May 05 12:43:01 PM PDT 24
Peak memory 211572 kb
Host smart-4576ef49-5ae4-486a-843b-e93a7f4d190e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560479739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2560479739
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.624131564
Short name T41
Test name
Test status
Simulation time 183983967976 ps
CPU time 911.26 seconds
Started May 05 12:42:41 PM PDT 24
Finished May 05 12:57:54 PM PDT 24
Peak memory 234400 kb
Host smart-b61e54a8-77ba-4f9f-9dad-735118ca162b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624131564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.624131564
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.554642930
Short name T176
Test name
Test status
Simulation time 971682394 ps
CPU time 18.95 seconds
Started May 05 12:42:44 PM PDT 24
Finished May 05 12:43:04 PM PDT 24
Peak memory 215172 kb
Host smart-4549c8a7-cb87-483b-9624-5a77516700a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554642930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.554642930
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4268027455
Short name T291
Test name
Test status
Simulation time 441908057 ps
CPU time 13.76 seconds
Started May 05 12:42:47 PM PDT 24
Finished May 05 12:43:04 PM PDT 24
Peak memory 211828 kb
Host smart-5f5ee9f7-d331-4144-b728-8055ea918324
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4268027455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4268027455
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.391881132
Short name T287
Test name
Test status
Simulation time 12510688206 ps
CPU time 58.39 seconds
Started May 05 12:42:43 PM PDT 24
Finished May 05 12:43:43 PM PDT 24
Peak memory 217584 kb
Host smart-8b05414e-3dfa-4929-94d5-99872419efcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391881132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.391881132
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3544627429
Short name T180
Test name
Test status
Simulation time 5318384756 ps
CPU time 60.55 seconds
Started May 05 12:42:43 PM PDT 24
Finished May 05 12:43:45 PM PDT 24
Peak memory 218128 kb
Host smart-f0921480-a5ad-4d13-8beb-29a7e967f207
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544627429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3544627429
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3265980998
Short name T311
Test name
Test status
Simulation time 424480302 ps
CPU time 8.49 seconds
Started May 05 12:42:36 PM PDT 24
Finished May 05 12:42:45 PM PDT 24
Peak memory 211820 kb
Host smart-4c3c8207-cd5a-4a0a-b8f1-4ea549d47266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265980998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3265980998
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1061041543
Short name T203
Test name
Test status
Simulation time 15976758971 ps
CPU time 166.78 seconds
Started May 05 12:42:39 PM PDT 24
Finished May 05 12:45:27 PM PDT 24
Peak memory 237280 kb
Host smart-97ddacad-aea6-40f9-808c-eb7d1832dea1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061041543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1061041543
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4066260020
Short name T19
Test name
Test status
Simulation time 625855425 ps
CPU time 19.07 seconds
Started May 05 12:42:49 PM PDT 24
Finished May 05 12:43:10 PM PDT 24
Peak memory 216016 kb
Host smart-13ef0631-b4d7-40f1-8e7a-5bf2715df2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066260020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4066260020
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1830172927
Short name T244
Test name
Test status
Simulation time 2962395051 ps
CPU time 26.92 seconds
Started May 05 12:42:36 PM PDT 24
Finished May 05 12:43:03 PM PDT 24
Peak memory 212748 kb
Host smart-0ca05ee5-c1e8-4d24-8ce5-a5b8118c8513
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1830172927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1830172927
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.895092103
Short name T7
Test name
Test status
Simulation time 4411530105 ps
CPU time 45.69 seconds
Started May 05 12:42:38 PM PDT 24
Finished May 05 12:43:24 PM PDT 24
Peak memory 217972 kb
Host smart-243979f9-850c-4196-b744-689f5231e009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895092103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.895092103
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.76079712
Short name T63
Test name
Test status
Simulation time 28209396983 ps
CPU time 69.5 seconds
Started May 05 12:42:43 PM PDT 24
Finished May 05 12:43:54 PM PDT 24
Peak memory 218572 kb
Host smart-39160d10-8fca-417f-a275-54984acde762
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76079712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 36.rom_ctrl_stress_all.76079712
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1999672736
Short name T226
Test name
Test status
Simulation time 13687818461 ps
CPU time 27.44 seconds
Started May 05 12:43:07 PM PDT 24
Finished May 05 12:43:36 PM PDT 24
Peak memory 211904 kb
Host smart-b4433b65-ff10-4270-ab64-b7c7e3963725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999672736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1999672736
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2758832430
Short name T27
Test name
Test status
Simulation time 2940044729 ps
CPU time 193.68 seconds
Started May 05 12:42:37 PM PDT 24
Finished May 05 12:45:51 PM PDT 24
Peak memory 225904 kb
Host smart-78fd659b-6ad1-47eb-b09c-fec4a290bb1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758832430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2758832430
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.4161779854
Short name T131
Test name
Test status
Simulation time 1649564402 ps
CPU time 30.81 seconds
Started May 05 12:42:38 PM PDT 24
Finished May 05 12:43:10 PM PDT 24
Peak memory 215156 kb
Host smart-8d7e4c58-f5e6-4c5e-9e31-227150d79ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161779854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.4161779854
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3955598243
Short name T201
Test name
Test status
Simulation time 1209052390 ps
CPU time 18.63 seconds
Started May 05 12:42:41 PM PDT 24
Finished May 05 12:43:01 PM PDT 24
Peak memory 211768 kb
Host smart-8914d4f4-512f-425a-b8f2-fef6648be2b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3955598243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3955598243
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1182655083
Short name T269
Test name
Test status
Simulation time 2811259548 ps
CPU time 23.37 seconds
Started May 05 12:42:45 PM PDT 24
Finished May 05 12:43:10 PM PDT 24
Peak memory 218428 kb
Host smart-82ee71a0-8e12-4822-bb5f-e3ce6a9ddac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182655083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1182655083
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2367683806
Short name T148
Test name
Test status
Simulation time 718380379 ps
CPU time 16.82 seconds
Started May 05 12:42:47 PM PDT 24
Finished May 05 12:43:06 PM PDT 24
Peak memory 211916 kb
Host smart-8597ecc6-e511-4cd7-9282-3827c46afc75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367683806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2367683806
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1748357110
Short name T146
Test name
Test status
Simulation time 4184340597 ps
CPU time 32.66 seconds
Started May 05 12:42:37 PM PDT 24
Finished May 05 12:43:11 PM PDT 24
Peak memory 212376 kb
Host smart-8828a3cb-7803-4e45-a463-ef86a556f87a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748357110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1748357110
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4045254806
Short name T169
Test name
Test status
Simulation time 7279108759 ps
CPU time 312.78 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:48:01 PM PDT 24
Peak memory 218568 kb
Host smart-343d28db-8df6-4f2c-b46a-984574993c3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045254806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4045254806
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.237069871
Short name T344
Test name
Test status
Simulation time 13188524051 ps
CPU time 56.54 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:43:45 PM PDT 24
Peak memory 215644 kb
Host smart-f550206a-79aa-4db2-807c-25debdec3d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237069871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.237069871
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.549836991
Short name T351
Test name
Test status
Simulation time 4423243035 ps
CPU time 14.58 seconds
Started May 05 12:43:02 PM PDT 24
Finished May 05 12:43:23 PM PDT 24
Peak memory 212368 kb
Host smart-2b1c72d1-ebf2-4fbe-926d-66f58b27d0de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=549836991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.549836991
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.438390434
Short name T238
Test name
Test status
Simulation time 816074531 ps
CPU time 20.56 seconds
Started May 05 12:42:47 PM PDT 24
Finished May 05 12:43:10 PM PDT 24
Peak memory 217368 kb
Host smart-bc2ed697-a0bc-4ef2-acf8-d09ca3e85f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438390434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.438390434
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3340494036
Short name T349
Test name
Test status
Simulation time 49812404711 ps
CPU time 129.04 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:44:58 PM PDT 24
Peak memory 220520 kb
Host smart-b723e787-29da-4692-8c48-74f670c871ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340494036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3340494036
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1734011752
Short name T196
Test name
Test status
Simulation time 4236272988 ps
CPU time 32.32 seconds
Started May 05 12:42:47 PM PDT 24
Finished May 05 12:43:22 PM PDT 24
Peak memory 212348 kb
Host smart-64908089-afbd-453f-9210-91af72cb22b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734011752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1734011752
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2804125499
Short name T271
Test name
Test status
Simulation time 104694836669 ps
CPU time 391.73 seconds
Started May 05 12:42:39 PM PDT 24
Finished May 05 12:49:11 PM PDT 24
Peak memory 238504 kb
Host smart-abe162d6-97de-46ce-8e37-c7428d9a6b23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804125499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2804125499
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.180216779
Short name T212
Test name
Test status
Simulation time 1737788737 ps
CPU time 19.62 seconds
Started May 05 12:42:50 PM PDT 24
Finished May 05 12:43:11 PM PDT 24
Peak memory 215080 kb
Host smart-13d0491c-7c25-4e6e-bbc4-101755993701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180216779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.180216779
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3928685031
Short name T305
Test name
Test status
Simulation time 3543627630 ps
CPU time 20.69 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:43:09 PM PDT 24
Peak memory 213064 kb
Host smart-c41cfec2-d104-4f3a-87ff-ea0749ff2bea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3928685031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3928685031
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1922298084
Short name T246
Test name
Test status
Simulation time 17506401888 ps
CPU time 66.63 seconds
Started May 05 12:42:44 PM PDT 24
Finished May 05 12:43:51 PM PDT 24
Peak memory 218596 kb
Host smart-c3ed887a-70ea-470a-b64a-386bbd2e8fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922298084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1922298084
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3075932899
Short name T297
Test name
Test status
Simulation time 2840429910 ps
CPU time 27 seconds
Started May 05 12:42:50 PM PDT 24
Finished May 05 12:43:19 PM PDT 24
Peak memory 219112 kb
Host smart-67f3f610-50ee-47c4-9776-94631411d69f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075932899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3075932899
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1863163817
Short name T66
Test name
Test status
Simulation time 1374246574 ps
CPU time 8.11 seconds
Started May 05 12:42:24 PM PDT 24
Finished May 05 12:42:34 PM PDT 24
Peak memory 211804 kb
Host smart-ab3ff296-4b8c-4c51-9ab2-638e90d31e48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863163817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1863163817
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1221686181
Short name T284
Test name
Test status
Simulation time 8006850277 ps
CPU time 279.23 seconds
Started May 05 12:42:06 PM PDT 24
Finished May 05 12:46:46 PM PDT 24
Peak memory 220180 kb
Host smart-253577f0-e52b-404f-998b-207e194d43c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221686181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1221686181
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2678546530
Short name T234
Test name
Test status
Simulation time 7615618688 ps
CPU time 65.43 seconds
Started May 05 12:42:28 PM PDT 24
Finished May 05 12:43:34 PM PDT 24
Peak memory 215588 kb
Host smart-934f5161-18d7-4634-a526-022da2a2cd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678546530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2678546530
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3212833303
Short name T319
Test name
Test status
Simulation time 2749847807 ps
CPU time 18.11 seconds
Started May 05 12:42:22 PM PDT 24
Finished May 05 12:42:42 PM PDT 24
Peak memory 212760 kb
Host smart-41d43e95-e220-464b-9a44-8f2f9771f59d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3212833303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3212833303
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2230775883
Short name T11
Test name
Test status
Simulation time 858045914 ps
CPU time 25.29 seconds
Started May 05 12:42:21 PM PDT 24
Finished May 05 12:42:47 PM PDT 24
Peak memory 218540 kb
Host smart-03114f7f-75b5-42fd-bbf8-917581e1359f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230775883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2230775883
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.437347127
Short name T58
Test name
Test status
Simulation time 75983354845 ps
CPU time 182.92 seconds
Started May 05 12:41:55 PM PDT 24
Finished May 05 12:45:00 PM PDT 24
Peak memory 220856 kb
Host smart-232a8b88-2eec-472a-8bd0-64931b7e23fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437347127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.437347127
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2772745835
Short name T345
Test name
Test status
Simulation time 11461842178 ps
CPU time 25.19 seconds
Started May 05 12:42:45 PM PDT 24
Finished May 05 12:43:12 PM PDT 24
Peak memory 211808 kb
Host smart-7c58ed77-b154-4d1d-aadd-f97323abfd15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772745835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2772745835
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1280440329
Short name T171
Test name
Test status
Simulation time 44491640553 ps
CPU time 443.2 seconds
Started May 05 12:42:59 PM PDT 24
Finished May 05 12:50:22 PM PDT 24
Peak memory 240768 kb
Host smart-e06e5dd1-6d66-4aea-8359-a7aa5ea1dc7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280440329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1280440329
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2799580193
Short name T144
Test name
Test status
Simulation time 15151408169 ps
CPU time 65.09 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:43:54 PM PDT 24
Peak memory 215396 kb
Host smart-fd398a20-89e3-4c9f-999a-eb602871179c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799580193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2799580193
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.4242897116
Short name T195
Test name
Test status
Simulation time 3945824828 ps
CPU time 17.01 seconds
Started May 05 12:42:45 PM PDT 24
Finished May 05 12:43:04 PM PDT 24
Peak memory 212068 kb
Host smart-e5039cbe-bdf9-4956-909a-b3cbd665df41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4242897116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.4242897116
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2845343488
Short name T265
Test name
Test status
Simulation time 4351059489 ps
CPU time 49 seconds
Started May 05 12:42:41 PM PDT 24
Finished May 05 12:43:31 PM PDT 24
Peak memory 215748 kb
Host smart-0e20f9ef-1fb2-4320-b3f9-f9a27c94518d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845343488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2845343488
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2894141823
Short name T327
Test name
Test status
Simulation time 6617687730 ps
CPU time 20.34 seconds
Started May 05 12:42:44 PM PDT 24
Finished May 05 12:43:05 PM PDT 24
Peak memory 212776 kb
Host smart-29fcc4d7-9b58-44c6-97aa-bcbda58e04cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894141823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2894141823
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.599840048
Short name T160
Test name
Test status
Simulation time 42660854537 ps
CPU time 411.61 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:49:40 PM PDT 24
Peak memory 216316 kb
Host smart-3b983750-699e-48a3-a069-d75c5b4d9bfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599840048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.599840048
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.35873847
Short name T248
Test name
Test status
Simulation time 3342261815 ps
CPU time 40.26 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:43:28 PM PDT 24
Peak memory 215260 kb
Host smart-48b9c8dc-4f73-4c01-a771-8b7893416687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35873847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.35873847
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.254951764
Short name T157
Test name
Test status
Simulation time 181827501 ps
CPU time 9.81 seconds
Started May 05 12:42:49 PM PDT 24
Finished May 05 12:43:01 PM PDT 24
Peak memory 212752 kb
Host smart-12ddfeac-062c-4f64-961e-938b49942462
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=254951764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.254951764
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1483927170
Short name T274
Test name
Test status
Simulation time 23338853168 ps
CPU time 63.34 seconds
Started May 05 12:43:08 PM PDT 24
Finished May 05 12:44:18 PM PDT 24
Peak memory 217784 kb
Host smart-e12b4f02-a106-4c5a-8593-dfab9b9ccd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483927170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1483927170
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3397704484
Short name T166
Test name
Test status
Simulation time 10616683994 ps
CPU time 94.71 seconds
Started May 05 12:42:59 PM PDT 24
Finished May 05 12:44:35 PM PDT 24
Peak memory 219844 kb
Host smart-6636a79e-6256-460a-95e5-88c7f6e09509
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397704484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3397704484
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2895045454
Short name T340
Test name
Test status
Simulation time 10157532656 ps
CPU time 23.57 seconds
Started May 05 12:42:48 PM PDT 24
Finished May 05 12:43:14 PM PDT 24
Peak memory 212604 kb
Host smart-a2e2ee0c-2140-49de-b57c-01c54335995b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895045454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2895045454
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.188783344
Short name T175
Test name
Test status
Simulation time 346250162 ps
CPU time 19.06 seconds
Started May 05 12:42:48 PM PDT 24
Finished May 05 12:43:09 PM PDT 24
Peak memory 215084 kb
Host smart-e1288af6-b48d-44c9-8673-933aee52cb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188783344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.188783344
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3243898278
Short name T13
Test name
Test status
Simulation time 4659424963 ps
CPU time 30.59 seconds
Started May 05 12:42:38 PM PDT 24
Finished May 05 12:43:09 PM PDT 24
Peak memory 211868 kb
Host smart-a0564725-4351-48d6-b249-267405b66dec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3243898278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3243898278
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1800821609
Short name T123
Test name
Test status
Simulation time 8917310068 ps
CPU time 33.24 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:43:22 PM PDT 24
Peak memory 218032 kb
Host smart-a35eed10-f958-4f5b-9ae7-3cd46eb0d0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800821609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1800821609
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2882818250
Short name T202
Test name
Test status
Simulation time 723581543 ps
CPU time 18.8 seconds
Started May 05 12:42:39 PM PDT 24
Finished May 05 12:42:58 PM PDT 24
Peak memory 212680 kb
Host smart-a251b23a-e526-49ce-9e81-880aa814c79b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882818250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2882818250
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3739156819
Short name T276
Test name
Test status
Simulation time 167609505 ps
CPU time 8.4 seconds
Started May 05 12:43:03 PM PDT 24
Finished May 05 12:43:12 PM PDT 24
Peak memory 211784 kb
Host smart-37ae54d0-6e49-4a9e-b698-a125fa22bca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739156819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3739156819
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3262555219
Short name T200
Test name
Test status
Simulation time 66527701392 ps
CPU time 406.96 seconds
Started May 05 12:42:43 PM PDT 24
Finished May 05 12:49:31 PM PDT 24
Peak memory 240432 kb
Host smart-16428ce9-d6ae-4977-8b3e-f33f46dc3087
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262555219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3262555219
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3033552884
Short name T342
Test name
Test status
Simulation time 6933131238 ps
CPU time 33.94 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:43:22 PM PDT 24
Peak memory 213288 kb
Host smart-b0558476-6efe-4290-a70e-51e1978aeeb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3033552884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3033552884
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.704280999
Short name T80
Test name
Test status
Simulation time 29332356130 ps
CPU time 39.98 seconds
Started May 05 12:42:48 PM PDT 24
Finished May 05 12:43:31 PM PDT 24
Peak memory 217720 kb
Host smart-6f2cd875-55a8-4614-b129-f0ff6fc9b58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704280999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.704280999
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.469928027
Short name T1
Test name
Test status
Simulation time 15957895145 ps
CPU time 79.87 seconds
Started May 05 12:42:34 PM PDT 24
Finished May 05 12:43:55 PM PDT 24
Peak memory 219916 kb
Host smart-e50a8a06-7eb4-465c-a5d8-361e45d3841e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469928027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.469928027
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2238937813
Short name T266
Test name
Test status
Simulation time 10466623345 ps
CPU time 23.31 seconds
Started May 05 12:42:47 PM PDT 24
Finished May 05 12:43:13 PM PDT 24
Peak memory 211712 kb
Host smart-00f28ffa-1bea-4c59-a19e-e09c19de3c9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238937813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2238937813
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1040746952
Short name T268
Test name
Test status
Simulation time 72832358188 ps
CPU time 679.27 seconds
Started May 05 12:42:37 PM PDT 24
Finished May 05 12:53:57 PM PDT 24
Peak memory 238320 kb
Host smart-5ec8ad3c-3f43-4be2-85e5-ba7f8fa4615d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040746952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1040746952
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.386531238
Short name T178
Test name
Test status
Simulation time 3275691670 ps
CPU time 25.35 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:43:14 PM PDT 24
Peak memory 215264 kb
Host smart-28007a99-3bf9-484b-ab3d-127fce8faed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386531238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.386531238
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3857439332
Short name T135
Test name
Test status
Simulation time 348868345 ps
CPU time 12.81 seconds
Started May 05 12:42:45 PM PDT 24
Finished May 05 12:42:59 PM PDT 24
Peak memory 211784 kb
Host smart-1288e63d-9f96-4ea4-a767-e17126bdf939
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3857439332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3857439332
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2387534913
Short name T143
Test name
Test status
Simulation time 2621651320 ps
CPU time 35.74 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:43:24 PM PDT 24
Peak memory 217652 kb
Host smart-b3923ac2-9b63-4dd2-b132-8f8fb0d9d81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387534913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2387534913
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2216389160
Short name T337
Test name
Test status
Simulation time 4288712157 ps
CPU time 49.63 seconds
Started May 05 12:42:44 PM PDT 24
Finished May 05 12:43:35 PM PDT 24
Peak memory 219640 kb
Host smart-c9fe4889-3937-4d9f-9c77-e97fa1632cf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216389160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2216389160
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.277964342
Short name T258
Test name
Test status
Simulation time 52406324971 ps
CPU time 34.49 seconds
Started May 05 12:42:43 PM PDT 24
Finished May 05 12:43:23 PM PDT 24
Peak memory 212744 kb
Host smart-d9d59991-2f62-4e8b-9b92-314e2c653ecf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277964342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.277964342
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2100215961
Short name T225
Test name
Test status
Simulation time 159493735079 ps
CPU time 335.02 seconds
Started May 05 12:42:47 PM PDT 24
Finished May 05 12:48:24 PM PDT 24
Peak memory 240760 kb
Host smart-e02c26d2-635f-4b96-b389-ff45f557100c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100215961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2100215961
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1267966601
Short name T127
Test name
Test status
Simulation time 27211283570 ps
CPU time 59.89 seconds
Started May 05 12:42:45 PM PDT 24
Finished May 05 12:43:52 PM PDT 24
Peak memory 214704 kb
Host smart-f0b55efe-f4c5-4d1e-92cb-e3694bbb8f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267966601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1267966601
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3286935946
Short name T174
Test name
Test status
Simulation time 2341311944 ps
CPU time 14.22 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:43:02 PM PDT 24
Peak memory 211536 kb
Host smart-e0ccfe51-1987-4839-b55f-676d32b93cfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3286935946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3286935946
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.4096469009
Short name T53
Test name
Test status
Simulation time 348034264 ps
CPU time 19.44 seconds
Started May 05 12:42:45 PM PDT 24
Finished May 05 12:43:07 PM PDT 24
Peak memory 216292 kb
Host smart-5bbbbfd3-4d4c-4369-86e6-15549bf427a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096469009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.4096469009
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2264572519
Short name T347
Test name
Test status
Simulation time 7720273164 ps
CPU time 86.9 seconds
Started May 05 12:42:48 PM PDT 24
Finished May 05 12:44:18 PM PDT 24
Peak memory 220088 kb
Host smart-dfdb7143-119e-472e-9b67-62a648fcfe66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264572519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2264572519
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.19075657
Short name T233
Test name
Test status
Simulation time 4164394527 ps
CPU time 31.89 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:43:21 PM PDT 24
Peak memory 212344 kb
Host smart-adb1fe5f-d471-4dd0-b3ba-fd2743547a0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19075657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.19075657
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1573179873
Short name T213
Test name
Test status
Simulation time 275091445097 ps
CPU time 582.69 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:52:31 PM PDT 24
Peak memory 241192 kb
Host smart-de8dcdcd-0044-4180-b6ec-a701a6cf71a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573179873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1573179873
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4091638737
Short name T129
Test name
Test status
Simulation time 4908742729 ps
CPU time 49.32 seconds
Started May 05 12:42:44 PM PDT 24
Finished May 05 12:43:35 PM PDT 24
Peak memory 216000 kb
Host smart-fc01767f-5602-4de2-bc22-4c37bc1e5133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091638737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4091638737
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.4016230487
Short name T333
Test name
Test status
Simulation time 3981656026 ps
CPU time 29.47 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:43:18 PM PDT 24
Peak memory 211764 kb
Host smart-fe097884-bbc4-4b4b-99df-8c7aa5db3d47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4016230487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.4016230487
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2641279288
Short name T79
Test name
Test status
Simulation time 6561201763 ps
CPU time 54.23 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:43:43 PM PDT 24
Peak memory 217100 kb
Host smart-b72340d5-07e7-4dbd-9c8a-7bbd535c6686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641279288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2641279288
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.557732257
Short name T230
Test name
Test status
Simulation time 1538590016 ps
CPU time 43.31 seconds
Started May 05 12:42:51 PM PDT 24
Finished May 05 12:43:35 PM PDT 24
Peak memory 219696 kb
Host smart-517cc2a5-87a0-47d4-9178-3c6f16375883
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557732257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.557732257
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1722889034
Short name T346
Test name
Test status
Simulation time 3589418046 ps
CPU time 29.12 seconds
Started May 05 12:42:47 PM PDT 24
Finished May 05 12:43:18 PM PDT 24
Peak memory 212376 kb
Host smart-46795a82-cb7c-4b13-8003-9d0894801db7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722889034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1722889034
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4004985656
Short name T29
Test name
Test status
Simulation time 206409343869 ps
CPU time 1024.89 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:59:54 PM PDT 24
Peak memory 239052 kb
Host smart-87f1dd4d-e344-454e-8edb-f71260625f92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004985656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.4004985656
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4086720339
Short name T240
Test name
Test status
Simulation time 8361154349 ps
CPU time 68.02 seconds
Started May 05 12:43:06 PM PDT 24
Finished May 05 12:44:15 PM PDT 24
Peak memory 215616 kb
Host smart-b7069a08-bae1-4399-a4c9-b162403bac6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086720339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.4086720339
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.230336051
Short name T38
Test name
Test status
Simulation time 4012088117 ps
CPU time 33.62 seconds
Started May 05 12:43:09 PM PDT 24
Finished May 05 12:43:44 PM PDT 24
Peak memory 212900 kb
Host smart-4d9b034f-83b4-4a5e-9fb6-df18bafd4b63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=230336051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.230336051
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1204569875
Short name T341
Test name
Test status
Simulation time 6728938507 ps
CPU time 58.9 seconds
Started May 05 12:42:49 PM PDT 24
Finished May 05 12:43:50 PM PDT 24
Peak memory 218268 kb
Host smart-a2804797-3f23-436b-b5ca-ae4a6f0dc75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204569875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1204569875
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.4224628794
Short name T162
Test name
Test status
Simulation time 521351650 ps
CPU time 22.82 seconds
Started May 05 12:42:47 PM PDT 24
Finished May 05 12:43:13 PM PDT 24
Peak memory 216504 kb
Host smart-eec5e062-fc6f-4f02-94e7-c3e7405d450c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224628794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.4224628794
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.599510534
Short name T167
Test name
Test status
Simulation time 71123811233 ps
CPU time 33.96 seconds
Started May 05 12:42:48 PM PDT 24
Finished May 05 12:43:24 PM PDT 24
Peak memory 211836 kb
Host smart-f97bab50-7123-4c72-a92d-f36ba4790a07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599510534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.599510534
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2250904050
Short name T42
Test name
Test status
Simulation time 23164757493 ps
CPU time 513.92 seconds
Started May 05 12:42:54 PM PDT 24
Finished May 05 12:51:29 PM PDT 24
Peak memory 235560 kb
Host smart-4581a9e9-562f-4103-8b9f-e57be2ee872c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250904050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2250904050
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1974882086
Short name T59
Test name
Test status
Simulation time 12462163845 ps
CPU time 53.24 seconds
Started May 05 12:42:45 PM PDT 24
Finished May 05 12:43:41 PM PDT 24
Peak memory 215612 kb
Host smart-868bd55f-0942-4eb6-90f6-2836c35402d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974882086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1974882086
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.869503239
Short name T159
Test name
Test status
Simulation time 15438702753 ps
CPU time 28.67 seconds
Started May 05 12:42:45 PM PDT 24
Finished May 05 12:43:16 PM PDT 24
Peak memory 212304 kb
Host smart-bcda3b62-70ab-4e01-9f43-42331aecf5e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=869503239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.869503239
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1752657806
Short name T295
Test name
Test status
Simulation time 1325564938 ps
CPU time 30.14 seconds
Started May 05 12:42:45 PM PDT 24
Finished May 05 12:43:18 PM PDT 24
Peak memory 216240 kb
Host smart-1f9411de-6bd4-48c2-ac8f-5766b1f38ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752657806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1752657806
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.4232682321
Short name T211
Test name
Test status
Simulation time 735413734 ps
CPU time 42.88 seconds
Started May 05 12:43:02 PM PDT 24
Finished May 05 12:43:45 PM PDT 24
Peak memory 216432 kb
Host smart-53e4ddc3-6737-4dbf-90ef-aa40d98c06c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232682321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.4232682321
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2891498235
Short name T128
Test name
Test status
Simulation time 174628496 ps
CPU time 8.42 seconds
Started May 05 12:42:50 PM PDT 24
Finished May 05 12:43:00 PM PDT 24
Peak memory 211760 kb
Host smart-1d108a5b-5a30-417f-a57b-aaf9d94a00f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891498235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2891498235
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1950088209
Short name T314
Test name
Test status
Simulation time 47096274218 ps
CPU time 352.72 seconds
Started May 05 12:42:38 PM PDT 24
Finished May 05 12:48:31 PM PDT 24
Peak memory 225148 kb
Host smart-9af8bada-86bd-4c3d-a635-cd2f842b4ee5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950088209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1950088209
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2983881051
Short name T237
Test name
Test status
Simulation time 6846766956 ps
CPU time 30.24 seconds
Started May 05 12:42:53 PM PDT 24
Finished May 05 12:43:24 PM PDT 24
Peak memory 216052 kb
Host smart-ba10bccd-b5cd-41bc-b0fe-76922f73f7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983881051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2983881051
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.213581075
Short name T290
Test name
Test status
Simulation time 2450369337 ps
CPU time 14.97 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:43:03 PM PDT 24
Peak memory 211792 kb
Host smart-d68d718b-1149-4af4-9835-1a896fc5bc90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=213581075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.213581075
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1332017117
Short name T139
Test name
Test status
Simulation time 4280135450 ps
CPU time 44.01 seconds
Started May 05 12:42:48 PM PDT 24
Finished May 05 12:43:34 PM PDT 24
Peak memory 217280 kb
Host smart-7c2bff76-9197-42c5-bebc-f4d1216ec975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332017117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1332017117
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2372027115
Short name T218
Test name
Test status
Simulation time 12085071759 ps
CPU time 121.23 seconds
Started May 05 12:42:45 PM PDT 24
Finished May 05 12:44:49 PM PDT 24
Peak memory 219844 kb
Host smart-ef70078a-eba0-49db-ba91-320f3db7ae85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372027115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2372027115
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.152070694
Short name T216
Test name
Test status
Simulation time 31218385571 ps
CPU time 19.85 seconds
Started May 05 12:41:59 PM PDT 24
Finished May 05 12:42:21 PM PDT 24
Peak memory 211820 kb
Host smart-fcb4504b-4c51-46c7-8c03-b398542c698b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152070694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.152070694
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3362847271
Short name T183
Test name
Test status
Simulation time 75516961173 ps
CPU time 442.12 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:49:21 PM PDT 24
Peak memory 238436 kb
Host smart-c7ab74e3-6699-4c51-8ac3-0cf2b2b47adb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362847271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3362847271
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1118173520
Short name T193
Test name
Test status
Simulation time 3427713469 ps
CPU time 25.57 seconds
Started May 05 12:42:11 PM PDT 24
Finished May 05 12:42:37 PM PDT 24
Peak memory 214296 kb
Host smart-2c50686b-718c-4864-badb-21fdd1e61c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118173520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1118173520
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.202191023
Short name T306
Test name
Test status
Simulation time 4840725125 ps
CPU time 24.17 seconds
Started May 05 12:41:53 PM PDT 24
Finished May 05 12:42:19 PM PDT 24
Peak memory 213316 kb
Host smart-ac66169c-a1ad-45d3-98d2-79a9f0093620
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=202191023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.202191023
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3163245322
Short name T163
Test name
Test status
Simulation time 26616776748 ps
CPU time 187.92 seconds
Started May 05 12:42:20 PM PDT 24
Finished May 05 12:45:29 PM PDT 24
Peak memory 220048 kb
Host smart-85ebdb69-34c2-4c52-a3f3-5c608275ccfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163245322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3163245322
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3447947559
Short name T232
Test name
Test status
Simulation time 4289049546 ps
CPU time 22.98 seconds
Started May 05 12:42:01 PM PDT 24
Finished May 05 12:42:26 PM PDT 24
Peak memory 211868 kb
Host smart-63222bd6-2896-4cc2-824d-b4532ee6fe94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447947559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3447947559
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1235734566
Short name T158
Test name
Test status
Simulation time 35666107214 ps
CPU time 458.12 seconds
Started May 05 12:42:35 PM PDT 24
Finished May 05 12:50:14 PM PDT 24
Peak memory 229276 kb
Host smart-de0024e0-fffd-4a4b-91d5-5817e72b82b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235734566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1235734566
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3922140363
Short name T256
Test name
Test status
Simulation time 18347831308 ps
CPU time 46.87 seconds
Started May 05 12:41:58 PM PDT 24
Finished May 05 12:42:47 PM PDT 24
Peak memory 214724 kb
Host smart-8551f989-6e8a-4b7d-80e5-fd35ffffd0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922140363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3922140363
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3835455059
Short name T56
Test name
Test status
Simulation time 354866047 ps
CPU time 10.93 seconds
Started May 05 12:42:02 PM PDT 24
Finished May 05 12:42:14 PM PDT 24
Peak memory 212700 kb
Host smart-7e1cd7cf-64d8-4064-a37a-6a82b0f3013a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3835455059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3835455059
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.333262166
Short name T78
Test name
Test status
Simulation time 24280558067 ps
CPU time 62.31 seconds
Started May 05 12:42:00 PM PDT 24
Finished May 05 12:43:04 PM PDT 24
Peak memory 218724 kb
Host smart-41f29170-1af4-4d6d-bdba-837a37868b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333262166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.333262166
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.295155233
Short name T126
Test name
Test status
Simulation time 15518672469 ps
CPU time 61.97 seconds
Started May 05 12:41:58 PM PDT 24
Finished May 05 12:43:02 PM PDT 24
Peak memory 219508 kb
Host smart-28281efe-c0bf-4f44-9727-5c06258de899
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295155233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.295155233
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1073350741
Short name T142
Test name
Test status
Simulation time 2256802048 ps
CPU time 22.16 seconds
Started May 05 12:42:17 PM PDT 24
Finished May 05 12:42:40 PM PDT 24
Peak memory 212464 kb
Host smart-a23a8c5a-ab38-4595-9f15-759b983deca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073350741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1073350741
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2972694311
Short name T285
Test name
Test status
Simulation time 196392403058 ps
CPU time 539.52 seconds
Started May 05 12:42:27 PM PDT 24
Finished May 05 12:51:27 PM PDT 24
Peak memory 237224 kb
Host smart-013c649b-f268-40af-bde0-787ad0ca4180
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972694311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2972694311
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1765437561
Short name T57
Test name
Test status
Simulation time 3330443430 ps
CPU time 34.7 seconds
Started May 05 12:42:05 PM PDT 24
Finished May 05 12:42:40 PM PDT 24
Peak memory 215340 kb
Host smart-eadbdf6b-d0aa-430f-b69d-ce0df294b32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765437561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1765437561
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2981493357
Short name T164
Test name
Test status
Simulation time 1665977140 ps
CPU time 21.06 seconds
Started May 05 12:42:22 PM PDT 24
Finished May 05 12:42:44 PM PDT 24
Peak memory 211796 kb
Host smart-fbe9dc61-0d11-4810-a059-53551e76dd35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2981493357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2981493357
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2889177300
Short name T10
Test name
Test status
Simulation time 11124923169 ps
CPU time 50.27 seconds
Started May 05 12:42:01 PM PDT 24
Finished May 05 12:42:53 PM PDT 24
Peak memory 218280 kb
Host smart-3577f87c-11fa-42f2-9250-d96506c3d9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889177300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2889177300
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.857153304
Short name T207
Test name
Test status
Simulation time 352879266 ps
CPU time 9.88 seconds
Started May 05 12:41:57 PM PDT 24
Finished May 05 12:42:09 PM PDT 24
Peak memory 212636 kb
Host smart-6bc2e736-92c4-4bb3-ac8d-5f741df0e7d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857153304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.857153304
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.371496252
Short name T335
Test name
Test status
Simulation time 7857495741 ps
CPU time 19.74 seconds
Started May 05 12:42:24 PM PDT 24
Finished May 05 12:42:45 PM PDT 24
Peak memory 211900 kb
Host smart-d75bf9cf-b1ce-43ca-9d04-9511dbee327c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371496252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.371496252
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1415341244
Short name T277
Test name
Test status
Simulation time 6773889613 ps
CPU time 180.93 seconds
Started May 05 12:42:08 PM PDT 24
Finished May 05 12:45:09 PM PDT 24
Peak memory 218420 kb
Host smart-40d11fdf-e856-4c9f-9d00-e6688d679e0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415341244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1415341244
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.48318689
Short name T324
Test name
Test status
Simulation time 20592851186 ps
CPU time 51.84 seconds
Started May 05 12:42:13 PM PDT 24
Finished May 05 12:43:08 PM PDT 24
Peak memory 213380 kb
Host smart-de7fa354-3704-4e28-876f-c91b5c83760f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48318689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.48318689
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1110424600
Short name T185
Test name
Test status
Simulation time 13301587375 ps
CPU time 29.15 seconds
Started May 05 12:41:59 PM PDT 24
Finished May 05 12:42:30 PM PDT 24
Peak memory 213328 kb
Host smart-2709021f-00e2-442d-b0a3-f8a29cafb6ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1110424600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1110424600
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.181013459
Short name T310
Test name
Test status
Simulation time 3489950122 ps
CPU time 26.11 seconds
Started May 05 12:42:25 PM PDT 24
Finished May 05 12:42:52 PM PDT 24
Peak memory 218520 kb
Host smart-2e3906f6-5be4-43ad-8e97-37f51aa4b4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181013459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.181013459
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1555140165
Short name T356
Test name
Test status
Simulation time 194840669 ps
CPU time 17.45 seconds
Started May 05 12:42:40 PM PDT 24
Finished May 05 12:42:58 PM PDT 24
Peak memory 211660 kb
Host smart-e6791686-6b06-406f-a446-a73ade941c68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555140165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1555140165
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2185468865
Short name T208
Test name
Test status
Simulation time 344361727 ps
CPU time 10.89 seconds
Started May 05 12:42:07 PM PDT 24
Finished May 05 12:42:18 PM PDT 24
Peak memory 211760 kb
Host smart-83d2db91-2fd5-422c-ad15-f477bf059f43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185468865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2185468865
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1031766141
Short name T292
Test name
Test status
Simulation time 56850809930 ps
CPU time 431.44 seconds
Started May 05 12:42:18 PM PDT 24
Finished May 05 12:49:31 PM PDT 24
Peak memory 239240 kb
Host smart-dd68e5ea-c980-4cb5-858a-8db6ea3c4e4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031766141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1031766141
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2577835511
Short name T312
Test name
Test status
Simulation time 9365990166 ps
CPU time 32.31 seconds
Started May 05 12:41:58 PM PDT 24
Finished May 05 12:42:32 PM PDT 24
Peak memory 214744 kb
Host smart-fecf93bd-3ffc-42af-a9cc-ef43d07107fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577835511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2577835511
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.889686492
Short name T288
Test name
Test status
Simulation time 2542964440 ps
CPU time 24.45 seconds
Started May 05 12:42:14 PM PDT 24
Finished May 05 12:42:40 PM PDT 24
Peak memory 212148 kb
Host smart-7c424fdf-f73a-4538-87ff-273ccda36f5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=889686492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.889686492
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.4363162
Short name T242
Test name
Test status
Simulation time 5632292546 ps
CPU time 53.72 seconds
Started May 05 12:42:26 PM PDT 24
Finished May 05 12:43:21 PM PDT 24
Peak memory 216888 kb
Host smart-faf2aae6-e127-4941-b903-432b67a1a6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4363162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.4363162
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.4184106671
Short name T326
Test name
Test status
Simulation time 12506332724 ps
CPU time 82.35 seconds
Started May 05 12:42:09 PM PDT 24
Finished May 05 12:43:32 PM PDT 24
Peak memory 218544 kb
Host smart-6f5717ce-c5ce-41be-a2d6-24b25f1099a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184106671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.4184106671
Directory /workspace/9.rom_ctrl_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%